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@@ -342,7 +342,7 @@ TEST_CASE("ULP FSM I_WR_REG instruction test", "[ulp]")
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for (size_t i = 0; i < test_items_count; ++i) {
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const uint32_t mask = (uint32_t) (((1ULL << test_items[i].width) - 1) << test_items[i].low);
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const uint32_t not_mask = ~mask;
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- printf("#%2d: low: %2d width: %2d mask: %08x expected: %08x ", i,
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+ printf("#%2d: low: %2d width: %2d mask: %08" PRIx32 " expected: %08" PRIx32 " ", i,
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test_items[i].low, test_items[i].width,
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mask, not_mask);
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@@ -377,7 +377,7 @@ TEST_CASE("ULP FSM I_WR_REG instruction test", "[ulp]")
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/* Verify the test results */
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uint32_t clear = REG_READ(RTC_CNTL_STORE0_REG);
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uint32_t set = REG_READ(RTC_CNTL_STORE1_REG);
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- printf("clear: %08x set: %08x\n", clear, set);
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+ printf("clear: %08" PRIx32 " set: %08" PRIx32 "\n", clear, set);
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/* Restore initial calibration values */
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REG_WRITE(RTC_CNTL_STORE0_REG, rtc_store0);
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@@ -548,7 +548,7 @@ TEST_CASE("ULP FSM timer setting", "[ulp]")
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uint32_t expected_counter = 1000000 / cycles_to_test[i];
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uint32_t tolerance = (expected_counter * 15 / 100);
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tolerance = tolerance ? tolerance : 1; // Keep a tolerance of at least 1 count
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- printf("expected: %u\t tolerance: +/- %u\t actual: %u\n", expected_counter, tolerance, counter);
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+ printf("expected: %" PRIu32 "\t tolerance: +/- %" PRIu32 "\t actual: %" PRIu32 "\n", expected_counter, tolerance, counter);
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// Should be within 15%
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TEST_ASSERT_INT_WITHIN(tolerance, expected_counter, counter);
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}
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