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@@ -110,6 +110,19 @@ typedef enum {
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#define ADC_LL_SAR1_SAMPLE_CYCLE_ADDR 0x2
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#define ADC_LL_SAR1_SAMPLE_CYCLE_ADDR_MSB 0x2
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#define ADC_LL_SAR1_SAMPLE_CYCLE_ADDR_LSB 0x0
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+
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+#define ADC_LL_SARADC_DTEST_RTC_ADDR 0x7
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+#define ADC_LL_SARADC_DTEST_RTC_ADDR_MSB 1
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+#define ADC_LL_SARADC_DTEST_RTC_ADDR_LSB 0
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+
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+#define ADC_LL_SARADC_ENT_TSENS_ADDR 0x7
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+#define ADC_LL_SARADC_ENT_TSENS_ADDR_MSB 2
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+#define ADC_LL_SARADC_ENT_TSENS_ADDR_LSB 2
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+
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+#define ADC_LL_SARADC_ENT_RTC_ADDR 0x7
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+#define ADC_LL_SARADC_ENT_RTC_ADDR_MSB 3
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+#define ADC_LL_SARADC_ENT_RTC_ADDR_LSB 3
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+
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/* ADC calibration defines end. */
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/*---------------------------------------------------------------
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@@ -1248,6 +1261,59 @@ static inline void adc_ll_set_calibration_param(adc_ll_num_t adc_n, uint32_t par
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}
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/* Temp code end. */
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+/**
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+ * Output ADCn inter reference voltage to ADC2 channels.
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+ *
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+ * This function routes the internal reference voltage of ADCn to one of
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+ * ADC2's channels. This reference voltage can then be manually measured
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+ * for calibration purposes.
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+ *
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+ * @param[in] adc ADC unit select
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+ * @param[in] channel ADC2 channel number
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+ * @param[in] en Enable/disable the reference voltage output
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+ */
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+static inline void adc_ll_vref_output(adc_ll_num_t adc, adc_channel_t channel, bool en)
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+{
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+ /* Should be called before writing I2C registers. */
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+ void phy_get_romfunc_addr(void);
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+ phy_get_romfunc_addr();
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+ SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_FORCE_PU_M);
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+ CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, BIT(18));
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+ SET_PERI_REG_MASK(ADC_LL_ANA_CONFIG2_REG, BIT(16));
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+
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+ if (en) {
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+ if (adc == ADC_NUM_1) {
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+ /* Config test mux to route v_ref to ADC1 Channels */
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+ I2C_WRITEREG_MASK_RTC(ADC_LL_I2C_ADC, ADC_LL_SARADC_DTEST_RTC_ADDR, 1);
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+ I2C_WRITEREG_MASK_RTC(ADC_LL_I2C_ADC, ADC_LL_SARADC_ENT_TSENS_ADDR, 0);
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+ I2C_WRITEREG_MASK_RTC(ADC_LL_I2C_ADC, ADC_LL_SARADC_ENT_RTC_ADDR, 1);
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+ } else {
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+ /* Config test mux to route v_ref to ADC2 Channels */
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+ I2C_WRITEREG_MASK_RTC(ADC_LL_I2C_ADC, ADC_LL_SARADC_DTEST_RTC_ADDR, 0);
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+ I2C_WRITEREG_MASK_RTC(ADC_LL_I2C_ADC, ADC_LL_SARADC_ENT_TSENS_ADDR, 1);
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+ I2C_WRITEREG_MASK_RTC(ADC_LL_I2C_ADC, ADC_LL_SARADC_ENT_RTC_ADDR, 0);
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+ }
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+ //in sleep force to use rtc to control ADC
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+ SENS.sar_meas2_mux.sar2_rtc_force = 1;
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+ //set sar2_en_test
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+ SENS.sar_meas2_ctrl1.sar2_en_test = 1;
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+ //set sar2 en force
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+ SENS.sar_meas2_ctrl2.sar2_en_pad_force = 1; //Pad bitmap controlled by SW
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+ //set en_pad for ADC2 channels (bits 0x380)
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+ SENS.sar_meas2_ctrl2.sar2_en_pad = 1 << channel;
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+ } else {
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+ I2C_WRITEREG_MASK_RTC(ADC_LL_I2C_ADC, ADC_LL_SARADC_ENT_TSENS_ADDR, 0);
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+ I2C_WRITEREG_MASK_RTC(ADC_LL_I2C_ADC, ADC_LL_SARADC_ENT_RTC_ADDR, 0);
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+ SENS.sar_meas2_mux.sar2_rtc_force = 0;
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+ //set sar2_en_test
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+ SENS.sar_meas2_ctrl1.sar2_en_test = 0;
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+ //set sar2 en force
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+ SENS.sar_meas2_ctrl2.sar2_en_pad_force = 0; //Pad bitmap controlled by SW
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+ //set en_pad for ADC2 channels (bits 0x380)
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+ SENS.sar_meas2_ctrl2.sar2_en_pad = 0;
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+ }
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+}
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+
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#ifdef __cplusplus
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}
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#endif
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