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@@ -59,238 +59,188 @@
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#define LEDC_EVT_TIMER1_CMP 50
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#define LEDC_EVT_TIMER2_CMP 51
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#define LEDC_EVT_TIMER3_CMP 52
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-#define PCNT_EVT_CNT_EQ_THRESH 53
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-#define PCNT_EVT_CNT_EQ_LMT 54
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-#define PCNT_EVT_CNT_EQ_ZERO 55
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-#define TG0_EVT_CNT_CMP_TIMER0 56
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-#define TG0_EVT_CNT_CMP_TIMER1 57
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-#define TG1_EVT_CNT_CMP_TIMER0 58
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-#define TG1_EVT_CNT_CMP_TIMER1 59
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-#define SYSTIMER_EVT_CNT_CMP0 60
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-#define SYSTIMER_EVT_CNT_CMP1 61
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-#define SYSTIMER_EVT_CNT_CMP2 62
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-#define RMT_EVT_TX_END 63
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-#define RMT_EVT_TX_LOOP 64
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-#define RMT_EVT_RX_END 65
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-#define RMT_EVT_TX_THRESH 66
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-#define RMT_EVT_RX_THRESH 67
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-#define MCPWM0_EVT_TIMER0_STOP 68
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-#define MCPWM0_EVT_TIMER1_STOP 69
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-#define MCPWM0_EVT_TIMER2_STOP 70
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-#define MCPWM0_EVT_TIMER0_TEZ 71
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-#define MCPWM0_EVT_TIMER1_TEZ 72
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-#define MCPWM0_EVT_TIMER2_TEZ 73
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-#define MCPWM0_EVT_TIMER0_TEP 74
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-#define MCPWM0_EVT_TIMER1_TEP 75
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-#define MCPWM0_EVT_TIMER2_TEP 76
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-#define MCPWM0_EVT_OP0_TEA 77
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-#define MCPWM0_EVT_OP1_TEA 78
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-#define MCPWM0_EVT_OP2_TEA 79
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-#define MCPWM0_EVT_OP0_TEB 80
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-#define MCPWM0_EVT_OP1_TEB 81
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-#define MCPWM0_EVT_OP2_TEB 82
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-#define MCPWM0_EVT_F0 83
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-#define MCPWM0_EVT_F1 84
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-#define MCPWM0_EVT_F2 85
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-#define MCPWM0_EVT_F0_CLR 86
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-#define MCPWM0_EVT_F1_CLR 87
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-#define MCPWM0_EVT_F2_CLR 88
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-#define MCPWM0_EVT_TZ0_CBC 89
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-#define MCPWM0_EVT_TZ1_CBC 90
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-#define MCPWM0_EVT_TZ2_CBC 91
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-#define MCPWM0_EVT_TZ0_OST 92
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-#define MCPWM0_EVT_TZ1_OST 93
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-#define MCPWM0_EVT_TZ2_OST 94
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-#define MCPWM0_EVT_CAP0 95
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-#define MCPWM0_EVT_CAP1 96
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-#define MCPWM0_EVT_CAP2 97
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-#define MCPWM0_EVT_OP0_TEE1 98
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-#define MCPWM0_EVT_OP1_TEE1 99
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-#define MCPWM0_EVT_OP2_TEE1 100
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-#define MCPWM0_EVT_OP0_TEE2 101
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-#define MCPWM0_EVT_OP1_TEE2 102
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-#define MCPWM0_EVT_OP2_TEE2 103
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-#define MCPWM1_EVT_TIMER0_STOP 104
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-#define MCPWM1_EVT_TIMER1_STOP 105
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-#define MCPWM1_EVT_TIMER2_STOP 106
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-#define MCPWM1_EVT_TIMER0_TEZ 107
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-#define MCPWM1_EVT_TIMER1_TEZ 108
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-#define MCPWM1_EVT_TIMER2_TEZ 109
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-#define MCPWM1_EVT_TIMER0_TEP 110
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-#define MCPWM1_EVT_TIMER1_TEP 111
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-#define MCPWM1_EVT_TIMER2_TEP 112
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-#define MCPWM1_EVT_OP0_TEA 113
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-#define MCPWM1_EVT_OP1_TEA 114
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-#define MCPWM1_EVT_OP2_TEA 115
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-#define MCPWM1_EVT_OP0_TEB 116
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-#define MCPWM1_EVT_OP1_TEB 117
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-#define MCPWM1_EVT_OP2_TEB 118
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-#define MCPWM1_EVT_F0 119
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-#define MCPWM1_EVT_F1 120
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-#define MCPWM1_EVT_F2 121
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-#define MCPWM1_EVT_F0_CLR 122
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-#define MCPWM1_EVT_F1_CLR 123
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-#define MCPWM1_EVT_F2_CLR 124
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-#define MCPWM1_EVT_TZ0_CBC 125
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-#define MCPWM1_EVT_TZ1_CBC 126
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-#define MCPWM1_EVT_TZ2_CBC 127
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-#define MCPWM1_EVT_TZ0_OST 128
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-#define MCPWM1_EVT_TZ1_OST 129
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-#define MCPWM1_EVT_TZ2_OST 130
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-#define MCPWM1_EVT_CAP0 131
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-#define MCPWM1_EVT_CAP1 132
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-#define MCPWM1_EVT_CAP2 133
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-#define MCPWM1_EVT_OP0_TEE1 134
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-#define MCPWM1_EVT_OP1_TEE1 135
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-#define MCPWM1_EVT_OP2_TEE1 136
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-#define MCPWM1_EVT_OP0_TEE2 137
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-#define MCPWM1_EVT_OP1_TEE2 138
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-#define MCPWM1_EVT_OP2_TEE2 139
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-#define ADC_EVT_CONV_CMPLT0 140
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-#define ADC_EVT_EQ_ABOVE_THRESH0 141
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-#define ADC_EVT_EQ_ABOVE_THRESH1 142
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-#define ADC_EVT_EQ_BELOW_THRESH0 143
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-#define ADC_EVT_EQ_BELOW_THRESH1 144
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-#define ADC_EVT_RESULT_DONE0 145
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-#define ADC_EVT_STOPPED0 146
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-#define ADC_EVT_STARTED0 147
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-#define REGDMA_EVT_DONE0 148
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-#define REGDMA_EVT_DONE1 149
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-#define REGDMA_EVT_DONE2 150
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-#define REGDMA_EVT_DONE3 151
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-#define REGDMA_EVT_ERR0 152
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-#define REGDMA_EVT_ERR1 153
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-#define REGDMA_EVT_ERR2 154
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-#define REGDMA_EVT_ERR3 155
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-#define PDMA_EVT_TX_DONE 156
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-#define PDMA_EVT_OUT_EOF 157
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-#define PDMA_EVT_IN_SUC_EOF 158
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-#define PDMA_EVT_FULL_OR_EMPTY 159
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-#define PDMA_EVT_ALL_DONE 160
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-#define PDMA_EVT_RX_DONE 161
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-#define TMPSNSR_EVT_OVER_LIMIT 162
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-#define UART_EVT_REC_DATA_OVF0 163
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-#define UART_EVT_REC_DATA_OVF1 164
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-#define UART_EVT_TX_DONE0 165
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-#define UART_EVT_TX_DONE1 166
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-#define UART_EVT_TIMEOUT0 167
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-#define UART_EVT_TIMEOUT1 168
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-#define UART_EVT_ERR0 169
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-#define UART_EVT_ERR1 170
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-#define UART_EVT_CTS0 171
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-#define UART_EVT_CTS1 172
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-#define UART_EVT_TX_EMPTY0 173
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-#define UART_EVT_TX_EMPTY1 174
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-#define UART_EVT_AT_PATTERNS0 175
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-#define UART_EVT_AT_PATTERNS1 176
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-#define SPI_EVT_STOPPED 177
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-#define I2S0_EVT_RX_DONE 178
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-#define I2S0_EVT_TX_DONE 179
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-#define I2S0_EVT_X_WORDS_RECEIVED 180
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-#define I2S0_EVT_X_WORDS_SENT 181
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-#define I2S1_EVT_RX_DONE 182
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-#define I2S1_EVT_TX_DONE 183
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-#define I2S1_EVT_X_WORDS_RECEIVED 184
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-#define I2S1_EVT_X_WORDS_SENT 185
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-#define I2S2_EVT_RX_DONE 186
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-#define I2S2_EVT_TX_DONE 187
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-#define I2S2_EVT_X_WORDS_RECEIVED 188
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-#define I2S2_EVT_X_WORDS_SENT 189
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-#define I2C_EVT_TRANS_DONE 190
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-#define LCDCAM_EVT_TRANS_DONE 191
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-#define CAN_EVT_TRANS_DONE 192
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-#define ULP_EVT_ERR_INTR 193
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-#define ULP_EVT_HALT 194
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-#define ULP_EVT_START_INTR 195
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-#define RTC_EVT_TICK 196
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-#define RTC_EVT_OVF 197
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-#define RTC_EVT_CMP 198
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-#define GDMA_AHB_EVT_IN_DONE_CH0 199
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-#define GDMA_AHB_EVT_IN_DONE_CH1 200
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-#define GDMA_AHB_EVT_IN_DONE_CH2 201
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-#define GDMA_AHB_EVT_IN_SUC_EOF_CH0 202
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-#define GDMA_AHB_EVT_IN_SUC_EOF_CH1 203
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-#define GDMA_AHB_EVT_IN_SUC_EOF_CH2 204
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-#define GDMA_AHB_EVT_IN_FIFO_EMPTY_CH0 205
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-#define GDMA_AHB_EVT_IN_FIFO_EMPTY_CH1 206
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-#define GDMA_AHB_EVT_IN_FIFO_EMPTY_CH2 207
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-#define GDMA_AHB_EVT_IN_FIFO_FULL_CH0 208
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-#define GDMA_AHB_EVT_IN_FIFO_FULL_CH1 209
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-#define GDMA_AHB_EVT_IN_FIFO_FULL_CH2 210
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-#define GDMA_AHB_EVT_OUT_DONE_CH0 211
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-#define GDMA_AHB_EVT_OUT_DONE_CH1 212
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-#define GDMA_AHB_EVT_OUT_DONE_CH2 213
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-#define GDMA_AHB_EVT_OUT_EOF_CH0 214
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-#define GDMA_AHB_EVT_OUT_EOF_CH1 215
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-#define GDMA_AHB_EVT_OUT_EOF_CH2 216
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-#define GDMA_AHB_EVT_OUT_TOTAL_EOF_CH0 217
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-#define GDMA_AHB_EVT_OUT_TOTAL_EOF_CH1 218
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-#define GDMA_AHB_EVT_OUT_TOTAL_EOF_CH2 219
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-#define GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0 220
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-#define GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1 221
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-#define GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2 222
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-#define GDMA_AHB_EVT_OUT_FIFO_FULL_CH0 223
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-#define GDMA_AHB_EVT_OUT_FIFO_FULL_CH1 224
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-#define GDMA_AHB_EVT_OUT_FIFO_FULL_CH2 225
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-#define GDMA_AXI_EVT_IN_DONE_CH0 226
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-#define GDMA_AXI_EVT_IN_DONE_CH1 227
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-#define GDMA_AXI_EVT_IN_DONE_CH2 228
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-#define GDMA_AXI_EVT_IN_DONE_CH3 229
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-#define GDMA_AXI_EVT_IN_DONE_CH4 230
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-#define GDMA_AXI_EVT_IN_SUC_EOF_CH0 231
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-#define GDMA_AXI_EVT_IN_SUC_EOF_CH1 232
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-#define GDMA_AXI_EVT_IN_SUC_EOF_CH2 233
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-#define GDMA_AXI_EVT_IN_SUC_EOF_CH3 234
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-#define GDMA_AXI_EVT_IN_SUC_EOF_CH4 235
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-#define GDMA_AXI_EVT_IN_FIFO_EMPTY_CH0 236
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-#define GDMA_AXI_EVT_IN_FIFO_EMPTY_CH1 237
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-#define GDMA_AXI_EVT_IN_FIFO_EMPTY_CH2 238
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-#define GDMA_AXI_EVT_IN_FIFO_EMPTY_CH3 239
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-#define GDMA_AXI_EVT_IN_FIFO_EMPTY_CH4 240
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-#define GDMA_AXI_EVT_IN_FIFO_FULL_CH0 241
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-#define GDMA_AXI_EVT_IN_FIFO_FULL_CH1 242
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-#define GDMA_AXI_EVT_IN_FIFO_FULL_CH2 243
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-#define GDMA_AXI_EVT_IN_FIFO_FULL_CH3 244
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-#define GDMA_AXI_EVT_IN_FIFO_FULL_CH4 245
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-#define GDMA_AXI_EVT_OUT_DONE_CH0 246
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-#define GDMA_AXI_EVT_OUT_DONE_CH1 247
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-#define GDMA_AXI_EVT_OUT_DONE_CH2 248
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-#define GDMA_AXI_EVT_OUT_DONE_CH3 249
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-#define GDMA_AXI_EVT_OUT_DONE_CH4 250
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-#define GDMA_AXI_EVT_OUT_EOF_CH0 251
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-#define GDMA_AXI_EVT_OUT_EOF_CH1 252
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-#define GDMA_AXI_EVT_OUT_EOF_CH2 253
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-#define GDMA_AXI_EVT_OUT_EOF_CH3 254
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-#define GDMA_AXI_EVT_OUT_EOF_CH4 255
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-#define GDMA_AXI_EVT_OUT_TOTAL_EOF_CH0 256
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-#define GDMA_AXI_EVT_OUT_TOTAL_EOF_CH1 257
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-#define GDMA_AXI_EVT_OUT_TOTAL_EOF_CH2 258
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-#define GDMA_AXI_EVT_OUT_TOTAL_EOF_CH3 259
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-#define GDMA_AXI_EVT_OUT_TOTAL_EOF_CH4 260
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-#define GDMA_AXI_EVT_OUT_FIFO_EMPTY_CH0 261
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-#define GDMA_AXI_EVT_OUT_FIFO_EMPTY_CH1 262
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-#define GDMA_AXI_EVT_OUT_FIFO_EMPTY_CH2 263
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-#define GDMA_AXI_EVT_OUT_FIFO_EMPTY_CH3 264
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-#define GDMA_AXI_EVT_OUT_FIFO_EMPTY_CH4 265
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-#define GDMA_AXI_EVT_OUT_FIFO_FULL_CH0 266
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-#define GDMA_AXI_EVT_OUT_FIFO_FULL_CH1 267
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-#define GDMA_AXI_EVT_OUT_FIFO_FULL_CH2 268
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-#define GDMA_AXI_EVT_OUT_FIFO_FULL_CH3 269
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-#define GDMA_AXI_EVT_OUT_FIFO_FULL_CH4 270
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-#define PMU_EVT_SLEEP_WEEKUP 271
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-#define DMA2D_EVT_IN_DONE_CH0 272
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-#define DMA2D_EVT_IN_DONE_CH1 273
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-#define DMA2D_EVT_IN_SUC_EOF_CH0 274
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-#define DMA2D_EVT_IN_SUC_EOF_CH1 275
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-#define DMA2D_EVT_OUT_DONE_CH0 276
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-#define DMA2D_EVT_OUT_DONE_CH1 277
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-#define DMA2D_EVT_OUT_DONE_CH2 278
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-#define DMA2D_EVT_OUT_EOF_CH0 279
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-#define DMA2D_EVT_OUT_EOF_CH1 280
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-#define DMA2D_EVT_OUT_EOF_CH2 281
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-#define DMA2D_EVT_OUT_TOTAL_EOF_CH0 282
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-#define DMA2D_EVT_OUT_TOTAL_EOF_CH1 283
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-#define DMA2D_EVT_OUT_TOTAL_EOF_CH2 284
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+#define TG0_EVT_CNT_CMP_TIMER0 53
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+#define TG0_EVT_CNT_CMP_TIMER1 54
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+#define TG1_EVT_CNT_CMP_TIMER0 55
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+#define TG1_EVT_CNT_CMP_TIMER1 56
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+#define SYSTIMER_EVT_CNT_CMP0 57
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+#define SYSTIMER_EVT_CNT_CMP1 58
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+#define SYSTIMER_EVT_CNT_CMP2 59
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+#define MCPWM0_EVT_TIMER0_STOP 60
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+#define MCPWM0_EVT_TIMER1_STOP 61
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+#define MCPWM0_EVT_TIMER2_STOP 62
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+#define MCPWM0_EVT_TIMER0_TEZ 63
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+#define MCPWM0_EVT_TIMER1_TEZ 64
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+#define MCPWM0_EVT_TIMER2_TEZ 65
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+#define MCPWM0_EVT_TIMER0_TEP 66
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+#define MCPWM0_EVT_TIMER1_TEP 67
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+#define MCPWM0_EVT_TIMER2_TEP 68
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+#define MCPWM0_EVT_OP0_TEA 69
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+#define MCPWM0_EVT_OP1_TEA 70
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+#define MCPWM0_EVT_OP2_TEA 71
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+#define MCPWM0_EVT_OP0_TEB 72
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+#define MCPWM0_EVT_OP1_TEB 73
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+#define MCPWM0_EVT_OP2_TEB 74
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+#define MCPWM0_EVT_F0 75
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+#define MCPWM0_EVT_F1 76
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+#define MCPWM0_EVT_F2 77
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+#define MCPWM0_EVT_F0_CLR 78
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+#define MCPWM0_EVT_F1_CLR 79
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+#define MCPWM0_EVT_F2_CLR 80
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+#define MCPWM0_EVT_TZ0_CBC 81
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+#define MCPWM0_EVT_TZ1_CBC 82
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+#define MCPWM0_EVT_TZ2_CBC 83
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+#define MCPWM0_EVT_TZ0_OST 84
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+#define MCPWM0_EVT_TZ1_OST 85
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+#define MCPWM0_EVT_TZ2_OST 86
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+#define MCPWM0_EVT_CAP0 87
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+#define MCPWM0_EVT_CAP1 88
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+#define MCPWM0_EVT_CAP2 89
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+#define MCPWM0_EVT_OP0_TEE1 90
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+#define MCPWM0_EVT_OP1_TEE1 91
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+#define MCPWM0_EVT_OP2_TEE1 92
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+#define MCPWM0_EVT_OP0_TEE2 93
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+#define MCPWM0_EVT_OP1_TEE2 94
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+#define MCPWM0_EVT_OP2_TEE2 95
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+#define MCPWM1_EVT_TIMER0_STOP 96
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+#define MCPWM1_EVT_TIMER1_STOP 97
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+#define MCPWM1_EVT_TIMER2_STOP 98
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+#define MCPWM1_EVT_TIMER0_TEZ 99
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+#define MCPWM1_EVT_TIMER1_TEZ 100
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+#define MCPWM1_EVT_TIMER2_TEZ 101
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+#define MCPWM1_EVT_TIMER0_TEP 102
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+#define MCPWM1_EVT_TIMER1_TEP 103
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+#define MCPWM1_EVT_TIMER2_TEP 104
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+#define MCPWM1_EVT_OP0_TEA 105
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+#define MCPWM1_EVT_OP1_TEA 106
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+#define MCPWM1_EVT_OP2_TEA 107
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|
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+#define MCPWM1_EVT_OP0_TEB 108
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|
|
+#define MCPWM1_EVT_OP1_TEB 109
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|
|
+#define MCPWM1_EVT_OP2_TEB 110
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|
|
+#define MCPWM1_EVT_F0 111
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|
|
+#define MCPWM1_EVT_F1 112
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|
|
+#define MCPWM1_EVT_F2 113
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|
|
+#define MCPWM1_EVT_F0_CLR 114
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|
|
+#define MCPWM1_EVT_F1_CLR 115
|
|
|
+#define MCPWM1_EVT_F2_CLR 116
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|
|
+#define MCPWM1_EVT_TZ0_CBC 117
|
|
|
+#define MCPWM1_EVT_TZ1_CBC 118
|
|
|
+#define MCPWM1_EVT_TZ2_CBC 119
|
|
|
+#define MCPWM1_EVT_TZ0_OST 120
|
|
|
+#define MCPWM1_EVT_TZ1_OST 121
|
|
|
+#define MCPWM1_EVT_TZ2_OST 122
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|
|
+#define MCPWM1_EVT_CAP0 123
|
|
|
+#define MCPWM1_EVT_CAP1 124
|
|
|
+#define MCPWM1_EVT_CAP2 125
|
|
|
+#define MCPWM1_EVT_OP0_TEE1 126
|
|
|
+#define MCPWM1_EVT_OP1_TEE1 127
|
|
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+#define MCPWM1_EVT_OP2_TEE1 128
|
|
|
+#define MCPWM1_EVT_OP0_TEE2 129
|
|
|
+#define MCPWM1_EVT_OP1_TEE2 130
|
|
|
+#define MCPWM1_EVT_OP2_TEE2 131
|
|
|
+#define ADC_EVT_CONV_CMPLT0 132
|
|
|
+#define ADC_EVT_EQ_ABOVE_THRESH0 133
|
|
|
+#define ADC_EVT_EQ_ABOVE_THRESH1 134
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|
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+#define ADC_EVT_EQ_BELOW_THRESH0 135
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|
|
+#define ADC_EVT_EQ_BELOW_THRESH1 136
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|
|
+#define ADC_EVT_RESULT_DONE0 137
|
|
|
+#define ADC_EVT_STOPPED0 138
|
|
|
+#define ADC_EVT_STARTED0 139
|
|
|
+#define REGDMA_EVT_DONE0 140
|
|
|
+#define REGDMA_EVT_DONE1 141
|
|
|
+#define REGDMA_EVT_DONE2 142
|
|
|
+#define REGDMA_EVT_DONE3 143
|
|
|
+#define REGDMA_EVT_ERR0 144
|
|
|
+#define REGDMA_EVT_ERR1 145
|
|
|
+#define REGDMA_EVT_ERR2 146
|
|
|
+#define REGDMA_EVT_ERR3 147
|
|
|
+#define TMPSNSR_EVT_OVER_LIMIT 148
|
|
|
+#define I2S0_EVT_RX_DONE 149
|
|
|
+#define I2S0_EVT_TX_DONE 150
|
|
|
+#define I2S0_EVT_X_WORDS_RECEIVED 151
|
|
|
+#define I2S0_EVT_X_WORDS_SENT 152
|
|
|
+#define I2S1_EVT_RX_DONE 153
|
|
|
+#define I2S1_EVT_TX_DONE 154
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|
|
+#define I2S1_EVT_X_WORDS_RECEIVED 155
|
|
|
+#define I2S1_EVT_X_WORDS_SENT 156
|
|
|
+#define I2S2_EVT_RX_DONE 157
|
|
|
+#define I2S2_EVT_TX_DONE 158
|
|
|
+#define I2S2_EVT_X_WORDS_RECEIVED 159
|
|
|
+#define I2S2_EVT_X_WORDS_SENT 160
|
|
|
+#define ULP_EVT_ERR_INTR 161
|
|
|
+#define ULP_EVT_HALT 162
|
|
|
+#define ULP_EVT_START_INTR 163
|
|
|
+#define RTC_EVT_TICK 164
|
|
|
+#define RTC_EVT_OVF 165
|
|
|
+#define RTC_EVT_CMP 166
|
|
|
+#define PDMA_AHB_EVT_IN_DONE_CH0 167
|
|
|
+#define PDMA_AHB_EVT_IN_DONE_CH1 168
|
|
|
+#define PDMA_AHB_EVT_IN_DONE_CH2 169
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|
|
+#define PDMA_AHB_EVT_IN_SUC_EOF_CH0 170
|
|
|
+#define PDMA_AHB_EVT_IN_SUC_EOF_CH1 171
|
|
|
+#define PDMA_AHB_EVT_IN_SUC_EOF_CH2 172
|
|
|
+#define PDMA_AHB_EVT_IN_FIFO_EMPTY_CH0 173
|
|
|
+#define PDMA_AHB_EVT_IN_FIFO_EMPTY_CH1 174
|
|
|
+#define PDMA_AHB_EVT_IN_FIFO_EMPTY_CH2 175
|
|
|
+#define PDMA_AHB_EVT_IN_FIFO_FULL_CH0 176
|
|
|
+#define PDMA_AHB_EVT_IN_FIFO_FULL_CH1 177
|
|
|
+#define PDMA_AHB_EVT_IN_FIFO_FULL_CH2 178
|
|
|
+#define PDMA_AHB_EVT_OUT_DONE_CH0 179
|
|
|
+#define PDMA_AHB_EVT_OUT_DONE_CH1 180
|
|
|
+#define PDMA_AHB_EVT_OUT_DONE_CH2 181
|
|
|
+#define PDMA_AHB_EVT_OUT_EOF_CH0 182
|
|
|
+#define PDMA_AHB_EVT_OUT_EOF_CH1 183
|
|
|
+#define PDMA_AHB_EVT_OUT_EOF_CH2 184
|
|
|
+#define PDMA_AHB_EVT_OUT_TOTAL_EOF_CH0 185
|
|
|
+#define PDMA_AHB_EVT_OUT_TOTAL_EOF_CH1 186
|
|
|
+#define PDMA_AHB_EVT_OUT_TOTAL_EOF_CH2 187
|
|
|
+#define PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0 188
|
|
|
+#define PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1 189
|
|
|
+#define PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2 190
|
|
|
+#define PDMA_AHB_EVT_OUT_FIFO_FULL_CH0 191
|
|
|
+#define PDMA_AHB_EVT_OUT_FIFO_FULL_CH1 192
|
|
|
+#define PDMA_AHB_EVT_OUT_FIFO_FULL_CH2 193
|
|
|
+#define PDMA_AXI_EVT_IN_DONE_CH0 194
|
|
|
+#define PDMA_AXI_EVT_IN_DONE_CH1 195
|
|
|
+#define PDMA_AXI_EVT_IN_DONE_CH2 196
|
|
|
+#define PDMA_AXI_EVT_IN_SUC_EOF_CH0 197
|
|
|
+#define PDMA_AXI_EVT_IN_SUC_EOF_CH1 198
|
|
|
+#define PDMA_AXI_EVT_IN_SUC_EOF_CH2 199
|
|
|
+#define PDMA_AXI_EVT_IN_FIFO_EMPTY_CH0 200
|
|
|
+#define PDMA_AXI_EVT_IN_FIFO_EMPTY_CH1 201
|
|
|
+#define PDMA_AXI_EVT_IN_FIFO_EMPTY_CH2 202
|
|
|
+#define PDMA_AXI_EVT_IN_FIFO_FULL_CH0 203
|
|
|
+#define PDMA_AXI_EVT_IN_FIFO_FULL_CH1 204
|
|
|
+#define PDMA_AXI_EVT_IN_FIFO_FULL_CH2 205
|
|
|
+#define PDMA_AXI_EVT_OUT_DONE_CH0 206
|
|
|
+#define PDMA_AXI_EVT_OUT_DONE_CH1 207
|
|
|
+#define PDMA_AXI_EVT_OUT_DONE_CH2 208
|
|
|
+#define PDMA_AXI_EVT_OUT_EOF_CH0 209
|
|
|
+#define PDMA_AXI_EVT_OUT_EOF_CH1 210
|
|
|
+#define PDMA_AXI_EVT_OUT_EOF_CH2 211
|
|
|
+#define PDMA_AXI_EVT_OUT_TOTAL_EOF_CH0 212
|
|
|
+#define PDMA_AXI_EVT_OUT_TOTAL_EOF_CH1 213
|
|
|
+#define PDMA_AXI_EVT_OUT_TOTAL_EOF_CH2 214
|
|
|
+#define PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH0 215
|
|
|
+#define PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH1 216
|
|
|
+#define PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH2 217
|
|
|
+#define PDMA_AXI_EVT_OUT_FIFO_FULL_CH0 218
|
|
|
+#define PDMA_AXI_EVT_OUT_FIFO_FULL_CH1 219
|
|
|
+#define PDMA_AXI_EVT_OUT_FIFO_FULL_CH2 220
|
|
|
+#define PMU_EVT_SLEEP_WEEKUP 221
|
|
|
+#define DMA2D_EVT_IN_DONE_CH0 222
|
|
|
+#define DMA2D_EVT_IN_DONE_CH1 223
|
|
|
+#define DMA2D_EVT_IN_SUC_EOF_CH0 224
|
|
|
+#define DMA2D_EVT_IN_SUC_EOF_CH1 225
|
|
|
+#define DMA2D_EVT_OUT_DONE_CH0 226
|
|
|
+#define DMA2D_EVT_OUT_DONE_CH1 227
|
|
|
+#define DMA2D_EVT_OUT_DONE_CH2 228
|
|
|
+#define DMA2D_EVT_OUT_EOF_CH0 229
|
|
|
+#define DMA2D_EVT_OUT_EOF_CH1 230
|
|
|
+#define DMA2D_EVT_OUT_EOF_CH2 231
|
|
|
+#define DMA2D_EVT_OUT_TOTAL_EOF_CH0 232
|
|
|
+#define DMA2D_EVT_OUT_TOTAL_EOF_CH1 233
|
|
|
+#define DMA2D_EVT_OUT_TOTAL_EOF_CH2 234
|
|
|
|
|
|
#define GPIO_TASK_CH0_SET 1
|
|
|
#define GPIO_TASK_CH1_SET 2
|
|
|
@@ -320,213 +270,182 @@
|
|
|
#define LEDC_TASK_TIMER1_RES_UPDATE 26
|
|
|
#define LEDC_TASK_TIMER2_RES_UPDATE 27
|
|
|
#define LEDC_TASK_TIMER3_RES_UPDATE 28
|
|
|
-#define LEDC_TASK_RSV0 29
|
|
|
-#define LEDC_TASK_RSV1 30
|
|
|
-#define LEDC_TASK_DUTY_SCALE_UPDATE_CH0 31
|
|
|
-#define LEDC_TASK_DUTY_SCALE_UPDATE_CH1 32
|
|
|
-#define LEDC_TASK_DUTY_SCALE_UPDATE_CH2 33
|
|
|
-#define LEDC_TASK_DUTY_SCALE_UPDATE_CH3 34
|
|
|
-#define LEDC_TASK_DUTY_SCALE_UPDATE_CH4 35
|
|
|
-#define LEDC_TASK_DUTY_SCALE_UPDATE_CH5 36
|
|
|
-#define LEDC_TASK_DUTY_SCALE_UPDATE_CH6 37
|
|
|
-#define LEDC_TASK_DUTY_SCALE_UPDATE_CH7 38
|
|
|
-#define LEDC_TASK_TIMER0_CAP 39
|
|
|
-#define LEDC_TASK_TIMER1_CAP 40
|
|
|
-#define LEDC_TASK_TIMER2_CAP 41
|
|
|
-#define LEDC_TASK_TIMER3_CAP 42
|
|
|
-#define LEDC_TASK_SIG_OUT_DIS_CH0 43
|
|
|
-#define LEDC_TASK_SIG_OUT_DIS_CH1 44
|
|
|
-#define LEDC_TASK_SIG_OUT_DIS_CH2 45
|
|
|
-#define LEDC_TASK_SIG_OUT_DIS_CH3 46
|
|
|
-#define LEDC_TASK_SIG_OUT_DIS_CH4 47
|
|
|
-#define LEDC_TASK_SIG_OUT_DIS_CH5 48
|
|
|
-#define LEDC_TASK_SIG_OUT_DIS_CH6 49
|
|
|
-#define LEDC_TASK_SIG_OUT_DIS_CH7 50
|
|
|
-#define LEDC_TASK_OVF_CNT_RST_CH0 51
|
|
|
-#define LEDC_TASK_OVF_CNT_RST_CH1 52
|
|
|
-#define LEDC_TASK_OVF_CNT_RST_CH2 53
|
|
|
-#define LEDC_TASK_OVF_CNT_RST_CH3 54
|
|
|
-#define LEDC_TASK_OVF_CNT_RST_CH4 55
|
|
|
-#define LEDC_TASK_OVF_CNT_RST_CH5 56
|
|
|
-#define LEDC_TASK_OVF_CNT_RST_CH6 57
|
|
|
-#define LEDC_TASK_OVF_CNT_RST_CH7 58
|
|
|
-#define LEDC_TASK_TIMER0_RST 59
|
|
|
-#define LEDC_TASK_TIMER1_RST 60
|
|
|
-#define LEDC_TASK_TIMER2_RST 61
|
|
|
-#define LEDC_TASK_TIMER3_RST 62
|
|
|
-#define LEDC_TASK_TIMER0_RESUME 63
|
|
|
-#define LEDC_TASK_TIMER1_RESUME 64
|
|
|
-#define LEDC_TASK_TIMER2_RESUME 65
|
|
|
-#define LEDC_TASK_TIMER3_RESUME 66
|
|
|
-#define LEDC_TASK_TIMER0_PAUSE 67
|
|
|
-#define LEDC_TASK_TIMER1_PAUSE 68
|
|
|
-#define LEDC_TASK_TIMER2_PAUSE 69
|
|
|
-#define LEDC_TASK_TIMER3_PAUSE 70
|
|
|
-#define LEDC_TASK_GAMMA_RESTART_CH0 71
|
|
|
-#define LEDC_TASK_GAMMA_RESTART_CH1 72
|
|
|
-#define LEDC_TASK_GAMMA_RESTART_CH2 73
|
|
|
-#define LEDC_TASK_GAMMA_RESTART_CH3 74
|
|
|
-#define LEDC_TASK_GAMMA_RESTART_CH4 75
|
|
|
-#define LEDC_TASK_GAMMA_RESTART_CH5 76
|
|
|
-#define LEDC_TASK_GAMMA_RESTART_CH6 77
|
|
|
-#define LEDC_TASK_GAMMA_RESTART_CH7 78
|
|
|
-#define LEDC_TASK_GAMMA_PAUSE_CH0 79
|
|
|
-#define LEDC_TASK_GAMMA_PAUSE_CH1 80
|
|
|
-#define LEDC_TASK_GAMMA_PAUSE_CH2 81
|
|
|
-#define LEDC_TASK_GAMMA_PAUSE_CH3 82
|
|
|
-#define LEDC_TASK_GAMMA_PAUSE_CH4 83
|
|
|
-#define LEDC_TASK_GAMMA_PAUSE_CH5 84
|
|
|
-#define LEDC_TASK_GAMMA_PAUSE_CH6 85
|
|
|
-#define LEDC_TASK_GAMMA_PAUSE_CH7 86
|
|
|
-#define LEDC_TASK_GAMMA_RESUME_CH0 87
|
|
|
-#define LEDC_TASK_GAMMA_RESUME_CH1 88
|
|
|
-#define LEDC_TASK_GAMMA_RESUME_CH2 89
|
|
|
-#define LEDC_TASK_GAMMA_RESUME_CH3 90
|
|
|
-#define LEDC_TASK_GAMMA_RESUME_CH4 91
|
|
|
-#define LEDC_TASK_GAMMA_RESUME_CH5 92
|
|
|
-#define LEDC_TASK_GAMMA_RESUME_CH6 93
|
|
|
-#define LEDC_TASK_GAMMA_RESUME_CH7 94
|
|
|
-#define PCNT_TASK_START 95
|
|
|
-#define PCNT_TASK_STOP 96
|
|
|
-#define PCNT_TASK_CNT_INC 97
|
|
|
-#define PCNT_TASK_CNT_DEC 98
|
|
|
-#define PCNT_TASK_CNT_RST 99
|
|
|
-#define TG0_TASK_CNT_START_TIMER0 100
|
|
|
-#define TG0_TASK_ALARM_START_TIMER0 101
|
|
|
-#define TG0_TASK_CNT_STOP_TIMER0 102
|
|
|
-#define TG0_TASK_CNT_RELOAD_TIMER0 103
|
|
|
-#define TG0_TASK_CNT_CAP_TIMER0 104
|
|
|
-#define TG0_TASK_CNT_START_TIMER1 105
|
|
|
-#define TG0_TASK_ALARM_START_TIMER1 106
|
|
|
-#define TG0_TASK_CNT_STOP_TIMER1 107
|
|
|
-#define TG0_TASK_CNT_RELOAD_TIMER1 108
|
|
|
-#define TG0_TASK_CNT_CAP_TIMER1 109
|
|
|
-#define TG1_TASK_CNT_START_TIMER0 110
|
|
|
-#define TG1_TASK_ALARM_START_TIMER0 111
|
|
|
-#define TG1_TASK_CNT_STOP_TIMER0 112
|
|
|
-#define TG1_TASK_CNT_RELOAD_TIMER0 113
|
|
|
-#define TG1_TASK_CNT_CAP_TIMER0 114
|
|
|
-#define TG1_TASK_CNT_START_TIMER1 115
|
|
|
-#define TG1_TASK_ALARM_START_TIMER1 116
|
|
|
-#define TG1_TASK_CNT_STOP_TIMER1 117
|
|
|
-#define TG1_TASK_CNT_RELOAD_TIMER1 118
|
|
|
-#define TG1_TASK_CNT_CAP_TIMER1 119
|
|
|
-#define RMT_TASK_TX_START 120
|
|
|
-#define RMT_TASK_TX_STOP 121
|
|
|
-#define RMT_TASK_RX_DONE 122
|
|
|
-#define RMT_TASK_RX_START 123
|
|
|
-#define MCPWM0_TASK_CMPR0_A_UP 124
|
|
|
-#define MCPWM0_TASK_CMPR1_A_UP 125
|
|
|
-#define MCPWM0_TASK_CMPR2_A_UP 126
|
|
|
-#define MCPWM0_TASK_CMPR0_B_UP 127
|
|
|
-#define MCPWM0_TASK_CMPR1_B_UP 128
|
|
|
-#define MCPWM0_TASK_CMPR2_B_UP 129
|
|
|
-#define MCPWM0_TASK_GEN_STOP 130
|
|
|
-#define MCPWM0_TASK_TIMER0_SYN 131
|
|
|
-#define MCPWM0_TASK_TIMER1_SYN 132
|
|
|
-#define MCPWM0_TASK_TIMER2_SYN 133
|
|
|
-#define MCPWM0_TASK_TIMER0_PERIOD_UP 134
|
|
|
-#define MCPWM0_TASK_TIMER1_PERIOD_UP 135
|
|
|
-#define MCPWM0_TASK_TIMER2_PERIOD_UP 136
|
|
|
-#define MCPWM0_TASK_TZ0_OST 137
|
|
|
-#define MCPWM0_TASK_TZ1_OST 138
|
|
|
-#define MCPWM0_TASK_TZ2_OST 139
|
|
|
-#define MCPWM0_TASK_CLR0_OST 140
|
|
|
-#define MCPWM0_TASK_CLR1_OST 141
|
|
|
-#define MCPWM0_TASK_CLR2_OST 142
|
|
|
-#define MCPWM0_TASK_CAP0 143
|
|
|
-#define MCPWM0_TASK_CAP1 144
|
|
|
-#define MCPWM0_TASK_CAP2 145
|
|
|
-#define MCPWM1_TASK_CMPR0_A_UP 146
|
|
|
-#define MCPWM1_TASK_CMPR1_A_UP 147
|
|
|
-#define MCPWM1_TASK_CMPR2_A_UP 148
|
|
|
-#define MCPWM1_TASK_CMPR0_B_UP 149
|
|
|
-#define MCPWM1_TASK_CMPR1_B_UP 150
|
|
|
-#define MCPWM1_TASK_CMPR2_B_UP 151
|
|
|
-#define MCPWM1_TASK_GEN_STOP 152
|
|
|
-#define MCPWM1_TASK_TIMER0_SYN 153
|
|
|
-#define MCPWM1_TASK_TIMER1_SYN 154
|
|
|
-#define MCPWM1_TASK_TIMER2_SYN 155
|
|
|
-#define MCPWM1_TASK_TIMER0_PERIOD_UP 156
|
|
|
-#define MCPWM1_TASK_TIMER1_PERIOD_UP 157
|
|
|
-#define MCPWM1_TASK_TIMER2_PERIOD_UP 158
|
|
|
-#define MCPWM1_TASK_TZ0_OST 159
|
|
|
-#define MCPWM1_TASK_TZ1_OST 160
|
|
|
-#define MCPWM1_TASK_TZ2_OST 161
|
|
|
-#define MCPWM1_TASK_CLR0_OST 162
|
|
|
-#define MCPWM1_TASK_CLR1_OST 163
|
|
|
-#define MCPWM1_TASK_CLR2_OST 164
|
|
|
-#define MCPWM1_TASK_CAP0 165
|
|
|
-#define MCPWM1_TASK_CAP1 166
|
|
|
-#define MCPWM1_TASK_CAP2 167
|
|
|
-#define ADC_TASK_SAMPLE0 168
|
|
|
-#define ADC_TASK_SAMPLE1 169
|
|
|
-#define ADC_TASK_START0 170
|
|
|
-#define ADC_TASK_STOP0 171
|
|
|
-#define REGDMA_TASK_START0 172
|
|
|
-#define REGDMA_TASK_START1 173
|
|
|
-#define REGDMA_TASK_START2 174
|
|
|
-#define REGDMA_TASK_START3 175
|
|
|
-#define PDMA_TASK_START_TX 176
|
|
|
-#define PDMA_TASK_START_RX 177
|
|
|
-#define PDMA_TASK_STOP 178
|
|
|
-#define TMPSNSR_TASK_START_SAMPLE 179
|
|
|
-#define TMPSNSR_TASK_STOP_SAMPLE 180
|
|
|
-#define UART_TASK_TX_START0 181
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-#define UART_TASK_TX_START1 182
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-#define UART_TASK_TX_STOP0 183
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-#define UART_TASK_TX_STOP1 184
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-#define UART_TASK_RX_START0 185
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-#define UART_TASK_RX_START1 186
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-#define UART_TASK_RX_STOP0 187
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-#define UART_TASK_RX_STOP1 188
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-#define SPI_TASK_TX_START 189
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-#define SPI_TASK_SLAVE_HD 190
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-#define SPI_TASK_STOP 191
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-#define I2S0_TASK_START_RX 192
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-#define I2S0_TASK_START_TX 193
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-#define I2S0_TASK_STOP_RX 194
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-#define I2S0_TASK_STOP_TX 195
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-#define I2S1_TASK_START_RX 196
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-#define I2S1_TASK_START_TX 197
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-#define I2S1_TASK_STOP_RX 198
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-#define I2S1_TASK_STOP_TX 199
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-#define I2S2_TASK_START_RX 200
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-#define I2S2_TASK_START_TX 201
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-#define I2S2_TASK_STOP_RX 202
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-#define I2S2_TASK_STOP_TX 203
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-#define I2C_TASK_START_TRANS 204
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-#define CAN_TASK_TRANS_START 205
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-#define ULP_TASK_WAKEUP_CPU 206
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-#define ULP_TASK_INT_CPU 207
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-#define RTC_TASK_START 208
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-#define RTC_TASK_STOP 209
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-#define RTC_TASK_CLR 210
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-#define RTC_TASK_TRIGGERFLW 211
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-#define GDMA_AHB_TASK_IN_START_CH0 212
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-#define GDMA_AHB_TASK_IN_START_CH1 213
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-#define GDMA_AHB_TASK_IN_START_CH2 214
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-#define GDMA_AHB_TASK_OUT_START_CH0 215
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-#define GDMA_AHB_TASK_OUT_START_CH1 216
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-#define GDMA_AHB_TASK_OUT_START_CH2 217
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-#define GDMA_AXI_TASK_IN_START_CH0 218
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-#define GDMA_AXI_TASK_IN_START_CH1 219
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-#define GDMA_AXI_TASK_IN_START_CH2 220
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-#define GDMA_AXI_TASK_IN_START_CH3 221
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-#define GDMA_AXI_TASK_IN_START_CH4 222
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-#define GDMA_AXI_TASK_OUT_START_CH0 223
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-#define GDMA_AXI_TASK_OUT_START_CH1 224
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-#define GDMA_AXI_TASK_OUT_START_CH2 225
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-#define GDMA_AXI_TASK_OUT_START_CH3 226
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-#define GDMA_AXI_TASK_OUT_START_CH4 227
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-#define PMU_TASK_SLEEP_REQ 228
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-#define DMA2D_TASK_IN_START_CH0 229
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-#define DMA2D_TASK_IN_START_CH1 230
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-#define DMA2D_TASK_IN_DSCR_READY_CH0 231
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-#define DMA2D_TASK_IN_DSCR_READY_CH1 232
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-#define DMA2D_TASK_OUT_START_CH0 233
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-#define DMA2D_TASK_OUT_START_CH1 234
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-#define DMA2D_TASK_OUT_START_CH2 235
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-#define DMA2D_TASK_OUT_DSCR_READY_CH0 236
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-#define DMA2D_TASK_OUT_DSCR_READY_CH1 237
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-#define DMA2D_TASK_OUT_DSCR_READY_CH2 238
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+#define LEDC_TASK_DUTY_SCALE_UPDATE_CH0 29
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+#define LEDC_TASK_DUTY_SCALE_UPDATE_CH1 30
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+#define LEDC_TASK_DUTY_SCALE_UPDATE_CH2 31
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+#define LEDC_TASK_DUTY_SCALE_UPDATE_CH3 32
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+#define LEDC_TASK_DUTY_SCALE_UPDATE_CH4 33
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+#define LEDC_TASK_DUTY_SCALE_UPDATE_CH5 34
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+#define LEDC_TASK_DUTY_SCALE_UPDATE_CH6 35
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+#define LEDC_TASK_DUTY_SCALE_UPDATE_CH7 36
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+#define LEDC_TASK_TIMER0_CAP 37
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+#define LEDC_TASK_TIMER1_CAP 38
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+#define LEDC_TASK_TIMER2_CAP 39
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+#define LEDC_TASK_TIMER3_CAP 40
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+#define LEDC_TASK_SIG_OUT_DIS_CH0 41
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+#define LEDC_TASK_SIG_OUT_DIS_CH1 42
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+#define LEDC_TASK_SIG_OUT_DIS_CH2 43
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+#define LEDC_TASK_SIG_OUT_DIS_CH3 44
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+#define LEDC_TASK_SIG_OUT_DIS_CH4 45
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+#define LEDC_TASK_SIG_OUT_DIS_CH5 46
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+#define LEDC_TASK_SIG_OUT_DIS_CH6 47
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+#define LEDC_TASK_SIG_OUT_DIS_CH7 48
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+#define LEDC_TASK_OVF_CNT_RST_CH0 49
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+#define LEDC_TASK_OVF_CNT_RST_CH1 50
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+#define LEDC_TASK_OVF_CNT_RST_CH2 51
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+#define LEDC_TASK_OVF_CNT_RST_CH3 52
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+#define LEDC_TASK_OVF_CNT_RST_CH4 53
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+#define LEDC_TASK_OVF_CNT_RST_CH5 54
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+#define LEDC_TASK_OVF_CNT_RST_CH6 55
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+#define LEDC_TASK_OVF_CNT_RST_CH7 56
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+#define LEDC_TASK_TIMER0_RST 57
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+#define LEDC_TASK_TIMER1_RST 58
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+#define LEDC_TASK_TIMER2_RST 59
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+#define LEDC_TASK_TIMER3_RST 60
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+#define LEDC_TASK_TIMER0_RESUME 61
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+#define LEDC_TASK_TIMER1_RESUME 62
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+#define LEDC_TASK_TIMER2_RESUME 63
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+#define LEDC_TASK_TIMER3_RESUME 64
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+#define LEDC_TASK_TIMER0_PAUSE 65
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+#define LEDC_TASK_TIMER1_PAUSE 66
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+#define LEDC_TASK_TIMER2_PAUSE 67
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+#define LEDC_TASK_TIMER3_PAUSE 68
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+#define LEDC_TASK_GAMMA_RESTART_CH0 69
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+#define LEDC_TASK_GAMMA_RESTART_CH1 70
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+#define LEDC_TASK_GAMMA_RESTART_CH2 71
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+#define LEDC_TASK_GAMMA_RESTART_CH3 72
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+#define LEDC_TASK_GAMMA_RESTART_CH4 73
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+#define LEDC_TASK_GAMMA_RESTART_CH5 74
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+#define LEDC_TASK_GAMMA_RESTART_CH6 75
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+#define LEDC_TASK_GAMMA_RESTART_CH7 76
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+#define LEDC_TASK_GAMMA_PAUSE_CH0 77
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+#define LEDC_TASK_GAMMA_PAUSE_CH1 78
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+#define LEDC_TASK_GAMMA_PAUSE_CH2 79
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+#define LEDC_TASK_GAMMA_PAUSE_CH3 80
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+#define LEDC_TASK_GAMMA_PAUSE_CH4 81
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+#define LEDC_TASK_GAMMA_PAUSE_CH5 82
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|
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+#define LEDC_TASK_GAMMA_PAUSE_CH6 83
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+#define LEDC_TASK_GAMMA_PAUSE_CH7 84
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+#define LEDC_TASK_GAMMA_RESUME_CH0 85
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+#define LEDC_TASK_GAMMA_RESUME_CH1 86
|
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+#define LEDC_TASK_GAMMA_RESUME_CH2 87
|
|
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+#define LEDC_TASK_GAMMA_RESUME_CH3 88
|
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+#define LEDC_TASK_GAMMA_RESUME_CH4 89
|
|
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+#define LEDC_TASK_GAMMA_RESUME_CH5 90
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|
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+#define LEDC_TASK_GAMMA_RESUME_CH6 91
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|
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+#define LEDC_TASK_GAMMA_RESUME_CH7 92
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|
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+#define TG0_TASK_CNT_START_TIMER0 93
|
|
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+#define TG0_TASK_ALARM_START_TIMER0 94
|
|
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+#define TG0_TASK_CNT_STOP_TIMER0 95
|
|
|
+#define TG0_TASK_CNT_RELOAD_TIMER0 96
|
|
|
+#define TG0_TASK_CNT_CAP_TIMER0 97
|
|
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+#define TG0_TASK_CNT_START_TIMER1 98
|
|
|
+#define TG0_TASK_ALARM_START_TIMER1 99
|
|
|
+#define TG0_TASK_CNT_STOP_TIMER1 100
|
|
|
+#define TG0_TASK_CNT_RELOAD_TIMER1 101
|
|
|
+#define TG0_TASK_CNT_CAP_TIMER1 102
|
|
|
+#define TG1_TASK_CNT_START_TIMER0 103
|
|
|
+#define TG1_TASK_ALARM_START_TIMER0 104
|
|
|
+#define TG1_TASK_CNT_STOP_TIMER0 105
|
|
|
+#define TG1_TASK_CNT_RELOAD_TIMER0 106
|
|
|
+#define TG1_TASK_CNT_CAP_TIMER0 107
|
|
|
+#define TG1_TASK_CNT_START_TIMER1 108
|
|
|
+#define TG1_TASK_ALARM_START_TIMER1 109
|
|
|
+#define TG1_TASK_CNT_STOP_TIMER1 110
|
|
|
+#define TG1_TASK_CNT_RELOAD_TIMER1 111
|
|
|
+#define TG1_TASK_CNT_CAP_TIMER1 112
|
|
|
+#define MCPWM0_TASK_CMPR0_A_UP 113
|
|
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+#define MCPWM0_TASK_CMPR1_A_UP 114
|
|
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+#define MCPWM0_TASK_CMPR2_A_UP 115
|
|
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+#define MCPWM0_TASK_CMPR0_B_UP 116
|
|
|
+#define MCPWM0_TASK_CMPR1_B_UP 117
|
|
|
+#define MCPWM0_TASK_CMPR2_B_UP 118
|
|
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+#define MCPWM0_TASK_GEN_STOP 119
|
|
|
+#define MCPWM0_TASK_TIMER0_SYN 120
|
|
|
+#define MCPWM0_TASK_TIMER1_SYN 121
|
|
|
+#define MCPWM0_TASK_TIMER2_SYN 122
|
|
|
+#define MCPWM0_TASK_TIMER0_PERIOD_UP 123
|
|
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+#define MCPWM0_TASK_TIMER1_PERIOD_UP 124
|
|
|
+#define MCPWM0_TASK_TIMER2_PERIOD_UP 125
|
|
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+#define MCPWM0_TASK_TZ0_OST 126
|
|
|
+#define MCPWM0_TASK_TZ1_OST 127
|
|
|
+#define MCPWM0_TASK_TZ2_OST 128
|
|
|
+#define MCPWM0_TASK_CLR0_OST 129
|
|
|
+#define MCPWM0_TASK_CLR1_OST 130
|
|
|
+#define MCPWM0_TASK_CLR2_OST 131
|
|
|
+#define MCPWM0_TASK_CAP0 132
|
|
|
+#define MCPWM0_TASK_CAP1 133
|
|
|
+#define MCPWM0_TASK_CAP2 134
|
|
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+#define MCPWM1_TASK_CMPR0_A_UP 135
|
|
|
+#define MCPWM1_TASK_CMPR1_A_UP 136
|
|
|
+#define MCPWM1_TASK_CMPR2_A_UP 137
|
|
|
+#define MCPWM1_TASK_CMPR0_B_UP 138
|
|
|
+#define MCPWM1_TASK_CMPR1_B_UP 139
|
|
|
+#define MCPWM1_TASK_CMPR2_B_UP 140
|
|
|
+#define MCPWM1_TASK_GEN_STOP 141
|
|
|
+#define MCPWM1_TASK_TIMER0_SYN 142
|
|
|
+#define MCPWM1_TASK_TIMER1_SYN 143
|
|
|
+#define MCPWM1_TASK_TIMER2_SYN 144
|
|
|
+#define MCPWM1_TASK_TIMER0_PERIOD_UP 145
|
|
|
+#define MCPWM1_TASK_TIMER1_PERIOD_UP 146
|
|
|
+#define MCPWM1_TASK_TIMER2_PERIOD_UP 147
|
|
|
+#define MCPWM1_TASK_TZ0_OST 148
|
|
|
+#define MCPWM1_TASK_TZ1_OST 149
|
|
|
+#define MCPWM1_TASK_TZ2_OST 150
|
|
|
+#define MCPWM1_TASK_CLR0_OST 151
|
|
|
+#define MCPWM1_TASK_CLR1_OST 152
|
|
|
+#define MCPWM1_TASK_CLR2_OST 153
|
|
|
+#define MCPWM1_TASK_CAP0 154
|
|
|
+#define MCPWM1_TASK_CAP1 155
|
|
|
+#define MCPWM1_TASK_CAP2 156
|
|
|
+#define ADC_TASK_SAMPLE0 157
|
|
|
+#define ADC_TASK_SAMPLE1 158
|
|
|
+#define ADC_TASK_START0 159
|
|
|
+#define ADC_TASK_STOP0 160
|
|
|
+#define REGDMA_TASK_START0 161
|
|
|
+#define REGDMA_TASK_START1 162
|
|
|
+#define REGDMA_TASK_START2 163
|
|
|
+#define REGDMA_TASK_START3 164
|
|
|
+#define TMPSNSR_TASK_START_SAMPLE 165
|
|
|
+#define TMPSNSR_TASK_STOP_SAMPLE 166
|
|
|
+#define I2S0_TASK_START_RX 167
|
|
|
+#define I2S0_TASK_START_TX 168
|
|
|
+#define I2S0_TASK_STOP_RX 169
|
|
|
+#define I2S0_TASK_STOP_TX 170
|
|
|
+#define I2S1_TASK_START_RX 171
|
|
|
+#define I2S1_TASK_START_TX 172
|
|
|
+#define I2S1_TASK_STOP_RX 173
|
|
|
+#define I2S1_TASK_STOP_TX 174
|
|
|
+#define I2S2_TASK_START_RX 175
|
|
|
+#define I2S2_TASK_START_TX 176
|
|
|
+#define I2S2_TASK_STOP_RX 177
|
|
|
+#define I2S2_TASK_STOP_TX 178
|
|
|
+#define ULP_TASK_WAKEUP_CPU 179
|
|
|
+#define ULP_TASK_INT_CPU 180
|
|
|
+#define RTC_TASK_START 181
|
|
|
+#define RTC_TASK_STOP 182
|
|
|
+#define RTC_TASK_CLR 183
|
|
|
+#define RTC_TASK_TRIGGERFLW 184
|
|
|
+#define PDMA_AHB_TASK_IN_START_CH0 185
|
|
|
+#define PDMA_AHB_TASK_IN_START_CH1 186
|
|
|
+#define PDMA_AHB_TASK_IN_START_CH2 187
|
|
|
+#define PDMA_AHB_TASK_OUT_START_CH0 188
|
|
|
+#define PDMA_AHB_TASK_OUT_START_CH1 189
|
|
|
+#define PDMA_AHB_TASK_OUT_START_CH2 190
|
|
|
+#define PDMA_AXI_TASK_IN_START_CH0 191
|
|
|
+#define PDMA_AXI_TASK_IN_START_CH1 192
|
|
|
+#define PDMA_AXI_TASK_IN_START_CH2 193
|
|
|
+#define PDMA_AXI_TASK_OUT_START_CH0 194
|
|
|
+#define PDMA_AXI_TASK_OUT_START_CH1 195
|
|
|
+#define PDMA_AXI_TASK_OUT_START_CH2 196
|
|
|
+#define PMU_TASK_SLEEP_REQ 197
|
|
|
+#define DMA2D_TASK_IN_START_CH0 198
|
|
|
+#define DMA2D_TASK_IN_START_CH1 199
|
|
|
+#define DMA2D_TASK_IN_DSCR_READY_CH0 200
|
|
|
+#define DMA2D_TASK_IN_DSCR_READY_CH1 201
|
|
|
+#define DMA2D_TASK_OUT_START_CH0 202
|
|
|
+#define DMA2D_TASK_OUT_START_CH1 203
|
|
|
+#define DMA2D_TASK_OUT_START_CH2 204
|
|
|
+#define DMA2D_TASK_OUT_DSCR_READY_CH0 205
|
|
|
+#define DMA2D_TASK_OUT_DSCR_READY_CH1 206
|
|
|
+#define DMA2D_TASK_OUT_DSCR_READY_CH2 207
|
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