ci: add access psram with DFS unity test

components/esp_hw_support/.build-test-rules.yml

@@ -20,6 +20,9 @@ components/esp_hw_support/test_apps/host_test_linux:
 components/esp_hw_support/test_apps/mspi:
   disable:
     - if: IDF_TARGET != "esp32s3"
+components/esp_hw_support/test_apps/mspi_psram_with_dfs:
+  disable:
+    - if: IDF_TARGET != "esp32s3"
 
 components/esp_hw_support/test_apps/rtc_clk:
   disable:

components/esp_hw_support/test_apps/mspi/main/test_flash_psram.c

@@ -36,33 +36,33 @@ TEST_CASE("MSPI: Test_SPI0_PSRAM", "[mspi]")
 {
     printf("----------SPI0 PSRAM Test----------\n");
 
-    uint8_t *psram_wr_buf = (uint8_t *)heap_caps_malloc(LENGTH_PER_TIME, MALLOC_CAP_32BIT | MALLOC_CAP_SPIRAM);
-    if (!psram_wr_buf) {
+    uint8_t *psram_rd_buf = (uint8_t *)heap_caps_malloc(LENGTH_PER_TIME, MALLOC_CAP_32BIT | MALLOC_CAP_SPIRAM);
+    if (!psram_rd_buf) {
         printf("no memory\n");
         abort();
     }
 
-    uint32_t *psram_rd_buf = (uint32_t *)heap_caps_malloc(SPI0_PSRAM_TEST_LEN, MALLOC_CAP_32BIT | MALLOC_CAP_SPIRAM);
-    if (!psram_rd_buf) {
+    uint8_t *psram_wr_buf = (uint8_t *)heap_caps_malloc(SPI0_PSRAM_TEST_LEN, MALLOC_CAP_32BIT | MALLOC_CAP_SPIRAM);
+    if (!psram_wr_buf) {
         printf("no memory\n");
         abort();
     }
 
     srand(399);
     for (int i = 0; i < SPI0_PSRAM_TEST_LEN / LENGTH_PER_TIME; i++) {
-        for (int j = 0; j < sizeof(psram_wr_buf); j++) {
-            psram_wr_buf[j] = rand();
+        for (int j = 0; j < sizeof(psram_rd_buf); j++) {
+            psram_rd_buf[j] = rand();
         }
-        memcpy(psram_rd_buf + i * LENGTH_PER_TIME, psram_wr_buf, LENGTH_PER_TIME);
+        memcpy(psram_wr_buf + i * LENGTH_PER_TIME, psram_rd_buf, LENGTH_PER_TIME);
 
-        if (memcmp(psram_rd_buf + i * LENGTH_PER_TIME, psram_wr_buf, LENGTH_PER_TIME) != 0) {
-            free(psram_rd_buf);
+        if (memcmp(psram_wr_buf + i * LENGTH_PER_TIME, psram_rd_buf, LENGTH_PER_TIME) != 0) {
             free(psram_wr_buf);
+            free(psram_rd_buf);
             TEST_FAIL_MESSAGE("SPI0 PSRAM Test Fail");
         }
     }
-    free(psram_rd_buf);
     free(psram_wr_buf);
+    free(psram_rd_buf);
     printf(DRAM_STR("----------SPI0 PSRAM Test Success----------\n\n"));
 }
 #endif

components/esp_hw_support/test_apps/mspi_psram_with_dfs/CMakeLists.txt

@@ -0,0 +1,5 @@
+# This is the project CMakeLists.txt file for the test subproject
+cmake_minimum_required(VERSION 3.16)
+
+include($ENV{IDF_PATH}/tools/cmake/project.cmake)
+project(mspi_psram_test_app)

components/esp_hw_support/test_apps/mspi_psram_with_dfs/README.md

@@ -0,0 +1,7 @@
+| Supported Targets | ESP32-S3 |
+| ----------------- | -------- |
+
+This project tests if PSRAM can work under different CPU clock configurations.
+To add new configuration, create one more sdkconfig.ci.NAME file in this directory.
+
+If you need to test for anything other than flash and psram, create another test project.

components/esp_hw_support/test_apps/mspi_psram_with_dfs/main/CMakeLists.txt

@@ -0,0 +1,9 @@
+set(srcs
+    "test_app_main.c"
+    "test_psram_with_dfs.c"
+)
+
+# In order for the cases defined by `TEST_CASE` to be linked into the final elf,
+# the component can be registered as WHOLE_ARCHIVE
+idf_component_register(SRCS ${srcs}
+                       WHOLE_ARCHIVE)

components/esp_hw_support/test_apps/mspi_psram_with_dfs/main/test_app_main.c

@@ -0,0 +1,30 @@
+/*
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "unity.h"
+#include "unity_test_utils.h"
+#include "esp_heap_caps.h"
+
+// load partition table in tests will use memory
+#define TEST_MEMORY_LEAK_THRESHOLD (450)
+
+void setUp(void)
+{
+    unity_utils_record_free_mem();
+}
+
+void tearDown(void)
+{
+    esp_reent_cleanup();    //clean up some of the newlib's lazy allocations
+    unity_utils_evaluate_leaks_direct(TEST_MEMORY_LEAK_THRESHOLD);
+}
+
+void app_main(void)
+{
+    printf("\n");
+    printf("===================TEST MSPI PSRAM WITH DFS=================\n");
+    unity_run_menu();
+}

components/esp_hw_support/test_apps/mspi_psram_with_dfs/main/test_psram_with_dfs.c

@@ -0,0 +1,178 @@
+/*
+ * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdio.h>
+#include <string.h>
+#include "unity.h"
+#include "sdkconfig.h"
+#include "freertos/FreeRTOS.h"
+#include "freertos/task.h"
+#include "freertos/semphr.h"
+#include "esp_system.h"
+#include "esp_check.h"
+#include "esp_attr.h"
+#include "esp_flash.h"
+#include "esp_partition.h"
+#include "esp_pm.h"
+#include "esp_private/esp_clk.h"
+#if CONFIG_IDF_TARGET_ESP32S3
+#include "esp32s3/rom/spi_flash.h"
+#include "esp32s3/rom/opi_flash.h"
+#endif
+
+
+//-----------------------------------------SPI0 PSRAM TEST-----------------------------------------------//
+#if CONFIG_SPIRAM
+
+#if CONFIG_SPIRAM_MODE_OCT
+#define SPI0_PSRAM_TEST_LEN    (512 * 1024)
+#define LENGTH_PER_TIME        1024
+#else
+#define SPI0_PSRAM_TEST_LEN    (128 * 1024)
+#define LENGTH_PER_TIME        1024
+#endif
+
+#define MHZ (1000000)
+#ifndef MIN
+#define MIN(x, y) (((x) < (y)) ? (x) : (y))
+#endif
+
+static SemaphoreHandle_t DoneSemphr;
+static SemaphoreHandle_t StopSemphr;
+
+static void psram_read_write_task(void* arg)
+{
+    printf("----------SPI0 PSRAM Access Test----------\n");
+
+    uint8_t *psram_rd_buf = (uint8_t *)heap_caps_malloc(LENGTH_PER_TIME, MALLOC_CAP_32BIT | MALLOC_CAP_SPIRAM);
+    if (!psram_rd_buf) {
+        printf("no memory\n");
+        abort();
+    }
+
+    uint8_t *psram_wr_buf = (uint8_t *)heap_caps_malloc(SPI0_PSRAM_TEST_LEN, MALLOC_CAP_32BIT | MALLOC_CAP_SPIRAM);
+    if (!psram_wr_buf) {
+        printf("no memory\n");
+        abort();
+    }
+
+    srand(399);
+    for (uint32_t loop = 0; loop < (uint32_t)(arg); loop++) {
+        for (int i = 0; i < SPI0_PSRAM_TEST_LEN / LENGTH_PER_TIME; i++) {
+            for (int j = 0; j < sizeof(psram_rd_buf); j++) {
+                psram_rd_buf[j] = rand();
+            }
+            memcpy(psram_wr_buf + i * LENGTH_PER_TIME, psram_rd_buf, LENGTH_PER_TIME);
+
+            if (memcmp(psram_wr_buf + i * LENGTH_PER_TIME, psram_rd_buf, LENGTH_PER_TIME) != 0) {
+                free(psram_wr_buf);
+                free(psram_rd_buf);
+                TEST_FAIL_MESSAGE("SPI0 PSRAM Test Fail");
+            }
+        }
+        xSemaphoreGive(DoneSemphr);
+        vTaskDelay(10);
+    }
+    free(psram_wr_buf);
+    free(psram_rd_buf);
+    vTaskDelete(NULL);
+}
+
+static void pm_light_sleep_enable(void)
+{
+    int cur_freq_mhz = esp_clk_cpu_freq() / MHZ;
+    int xtal_freq = esp_clk_xtal_freq() / MHZ;
+
+    esp_pm_config_t pm_config = {
+        .max_freq_mhz = cur_freq_mhz,
+        .min_freq_mhz = xtal_freq,
+        .light_sleep_enable = true
+    };
+    TEST_ESP_OK( esp_pm_configure(&pm_config) );
+}
+
+static void pm_light_sleep_disable(void)
+{
+    int cur_freq_mhz = esp_clk_cpu_freq() / MHZ;
+
+    esp_pm_config_t pm_config = {
+        .max_freq_mhz = cur_freq_mhz,
+        .min_freq_mhz = cur_freq_mhz,
+    };
+    TEST_ESP_OK( esp_pm_configure(&pm_config) );
+}
+
+static void pm_switch_freq(int max_cpu_freq_mhz)
+{
+    int xtal_freq_mhz = esp_clk_xtal_freq() / MHZ;
+
+    esp_pm_config_t pm_config = {
+        .max_freq_mhz = max_cpu_freq_mhz,
+        .min_freq_mhz = MIN(max_cpu_freq_mhz, xtal_freq_mhz),
+    };
+    TEST_ESP_OK( esp_pm_configure(&pm_config) );
+    printf("Waiting for frequency to be set to %d MHz...\n", max_cpu_freq_mhz);
+    while (esp_clk_cpu_freq() / MHZ != max_cpu_freq_mhz)
+    {
+        vTaskDelay(pdMS_TO_TICKS(200));
+        printf("Frequency is %d MHz\n", esp_clk_cpu_freq() / MHZ);
+    }
+}
+
+static void goto_idle_and_check_stop(uint32_t period)
+{
+    if (xSemaphoreTake(StopSemphr, pdMS_TO_TICKS(period)) == pdTRUE) {
+        pm_switch_freq(CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ);
+        vSemaphoreDelete(StopSemphr);
+        vTaskDelete(NULL);
+    }
+}
+
+static void pm_switch_task(void *arg)
+{
+    pm_light_sleep_disable();
+    uint32_t period = 100;
+    StopSemphr = xSemaphoreCreateBinary();
+    while (1) {
+        pm_light_sleep_enable();
+        goto_idle_and_check_stop(period);
+        pm_light_sleep_disable();
+        goto_idle_and_check_stop(period);
+        pm_switch_freq(10);
+        goto_idle_and_check_stop(period);
+        pm_switch_freq(80);
+        goto_idle_and_check_stop(period);
+        pm_switch_freq(40);
+        goto_idle_and_check_stop(period);
+    }
+}
+
+TEST_CASE("MSPI: Test_SPI0_PSRAM with DFS", "[mspi]")
+{
+    printf("----------Access SPI0 PSRAM with DFS Test----------\n");
+
+    uint32_t test_loop = 50;
+    DoneSemphr = xSemaphoreCreateCounting(test_loop, 0);
+
+    xTaskCreatePinnedToCore(pm_switch_task, "", 4096, NULL, 3, NULL, 0);
+    xTaskCreatePinnedToCore(psram_read_write_task, "", 2048, (void *)(test_loop), 3, NULL, 1);
+
+    int cnt = 0;
+    while (cnt < test_loop) {
+        if (xSemaphoreTake(DoneSemphr, pdMS_TO_TICKS(1000)) == pdTRUE) {
+            cnt++;
+        } else {
+            vSemaphoreDelete(DoneSemphr);
+            TEST_FAIL_MESSAGE(DRAM_STR("SPI0 PSRAM Test Timeout"));
+        }
+    }
+    xSemaphoreGive(StopSemphr);
+    vSemaphoreDelete(DoneSemphr);
+    /* Wait for test_task to finish up */
+    vTaskDelay(pdMS_TO_TICKS(500));
+    printf(DRAM_STR("----------Access SPI0 PSRAM with DFS Test Success----------\n\n"));
+}
+#endif

components/esp_hw_support/test_apps/mspi_psram_with_dfs/pytest_psram_with_dfs.py

@@ -0,0 +1,39 @@
+# SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+# SPDX-License-Identifier: CC0-1.0
+
+import os
+import pathlib
+
+import pytest
+from pytest_embedded_idf import IdfDut
+
+MSPI_F8R8_configs = [p.name.replace('sdkconfig.ci.', '') for p in pathlib.Path(os.path.dirname(__file__)).glob('sdkconfig.ci.f8r8*')]
+
+
+@pytest.mark.esp32s3
+@pytest.mark.MSPI_F8R8
+@pytest.mark.parametrize('config', MSPI_F8R8_configs, indirect=True)
+def test_flash8_psram8_with_dfs(dut: IdfDut) -> None:
+    dut.run_all_single_board_cases()
+
+
+# For F4R8 board (Quad Flash and Octal PSRAM)
+MSPI_F4R8_configs = [p.name.replace('sdkconfig.ci.', '') for p in pathlib.Path(os.path.dirname(__file__)).glob('sdkconfig.ci.f4r8*')]
+
+
+@pytest.mark.esp32s3
+@pytest.mark.MSPI_F4R8
+@pytest.mark.parametrize('config', MSPI_F4R8_configs, indirect=True)
+def test_flash4_psram8_with_dfs(dut: IdfDut) -> None:
+    dut.run_all_single_board_cases()
+
+
+# For F4R4 board (Quad Flash and Quad PSRAM)
+MSPI_F4R4_configs = [p.name.replace('sdkconfig.ci.', '') for p in pathlib.Path(os.path.dirname(__file__)).glob('sdkconfig.ci.f4r4*')]
+
+
+@pytest.mark.esp32s3
+@pytest.mark.MSPI_F4R4
+@pytest.mark.parametrize('config', MSPI_F4R4_configs, indirect=True)
+def test_flash4_psram4_with_dfs(dut: IdfDut) -> None:
+    dut.run_all_single_board_cases()

components/esp_hw_support/test_apps/mspi_psram_with_dfs/sdkconfig.ci.f4r4_120sdr

@@ -0,0 +1,4 @@
+# Legacy, F4R4, Flash 120M SDR, PSRAM disable
+
+CONFIG_ESPTOOLPY_FLASHFREQ_120M=y
+CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y

components/esp_hw_support/test_apps/mspi_psram_with_dfs/sdkconfig.ci.f4r4_120sdr_120sdr

@@ -0,0 +1,6 @@
+# Legacy, F4R4, Flash 120M SDR, PSRAM 120M SDR
+
+CONFIG_ESPTOOLPY_FLASHFREQ_120M=y
+CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y
+CONFIG_SPIRAM=y
+CONFIG_SPIRAM_SPEED_120M=y

components/esp_hw_support/test_apps/mspi_psram_with_dfs/sdkconfig.ci.f4r4_120sdr_40sdr

@@ -0,0 +1,6 @@
+# Legacy, F4R4, Flash 120M SDR, PSRAM 40M SDR
+
+CONFIG_ESPTOOLPY_FLASHFREQ_120M=y
+CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y
+CONFIG_SPIRAM=y
+CONFIG_SPIRAM_SPEED_40M=y

components/esp_hw_support/test_apps/mspi_psram_with_dfs/sdkconfig.ci.f4r4_120sdr_os_silent

@@ -0,0 +1,8 @@
+# Legacy, F4R4, Flash 120M SDR, PSRAM disable, compiler -Os and silent
+
+CONFIG_COMPILER_OPTIMIZATION_SIZE=y
+CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y
+CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT=y
+
+CONFIG_ESPTOOLPY_FLASHFREQ_120M=y
+CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y

components/esp_hw_support/test_apps/mspi_psram_with_dfs/sdkconfig.ci.f4r4_40sdr_120sdr

@@ -0,0 +1,6 @@
+# Legacy, F4R4, Flash 40M SDR, PSRAM 120M SDR
+
+CONFIG_ESPTOOLPY_FLASHFREQ_40M=y
+CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y
+CONFIG_SPIRAM=y
+CONFIG_SPIRAM_SPEED_120M=y

components/esp_hw_support/test_apps/mspi_psram_with_dfs/sdkconfig.ci.f4r4_80sdr_80sdr

@@ -0,0 +1,6 @@
+# Legacy, F4R4, Flash 80M SDR, PSRAM 80M SDR
+
+CONFIG_ESPTOOLPY_FLASHFREQ_80M=y
+CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y
+CONFIG_SPIRAM=y
+CONFIG_SPIRAM_SPEED_80M=y

components/esp_hw_support/test_apps/mspi_psram_with_dfs/sdkconfig.ci.f4r8_120sdr

@@ -0,0 +1,4 @@
+# Legacy, F4R8, Flash 120M SDR, PSRAM disable
+
+CONFIG_ESPTOOLPY_FLASHFREQ_120M=y
+CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y

components/esp_hw_support/test_apps/mspi_psram_with_dfs/sdkconfig.ci.f4r8_80sdr_40ddr

@@ -0,0 +1,7 @@
+# Legacy, F4R8, Flash 80M SDR, PSRAM 40M DDR
+
+CONFIG_ESPTOOLPY_FLASHFREQ_80M=y
+CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y
+CONFIG_SPIRAM=y
+CONFIG_SPIRAM_MODE_OCT=y
+CONFIG_SPIRAM_SPEED_40M=y

components/esp_hw_support/test_apps/mspi_psram_with_dfs/sdkconfig.ci.f4r8_80sdr_80ddr

@@ -0,0 +1,7 @@
+# Legacy, F4R8, Flash 80M SDR, PSRAM 80M DDR
+
+CONFIG_ESPTOOLPY_FLASHFREQ_80M=y
+CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y
+CONFIG_SPIRAM=y
+CONFIG_SPIRAM_MODE_OCT=y
+CONFIG_SPIRAM_SPEED_80M=y

components/esp_hw_support/test_apps/mspi_psram_with_dfs/sdkconfig.ci.f8r8_120sdr

@@ -0,0 +1,7 @@
+# Legacy, F8R8, Flash 120M SDR, PSRAM disable
+
+CONFIG_ESPTOOLPY_OCT_FLASH=y
+CONFIG_ESPTOOLPY_FLASH_SAMPLE_MODE_STR=y
+CONFIG_ESPTOOLPY_FLASHFREQ_120M=y
+CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y
+CONFIG_SPIRAM=n

components/esp_hw_support/test_apps/mspi_psram_with_dfs/sdkconfig.ci.f8r8_40ddr_40ddr

@@ -0,0 +1,9 @@
+# Legacy, F8R8, Flash 40M DDR, PSRAM 40M DDR
+
+CONFIG_ESPTOOLPY_OCT_FLASH=y
+CONFIG_ESPTOOLPY_FLASH_SAMPLE_MODE_DTR=y
+CONFIG_ESPTOOLPY_FLASHFREQ_40M=y
+CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y
+CONFIG_SPIRAM=y
+CONFIG_SPIRAM_MODE_OCT=y
+CONFIG_SPIRAM_SPEED_40M=y

components/esp_hw_support/test_apps/mspi_psram_with_dfs/sdkconfig.ci.f8r8_40ddr_80ddr

@@ -0,0 +1,9 @@
+# Legacy, F8R8, Flash 40M DDR, PSRAM 80M DDR
+
+CONFIG_ESPTOOLPY_OCT_FLASH=y
+CONFIG_ESPTOOLPY_FLASH_SAMPLE_MODE_DTR=y
+CONFIG_ESPTOOLPY_FLASHFREQ_40M=y
+CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y
+CONFIG_SPIRAM=y
+CONFIG_SPIRAM_MODE_OCT=y
+CONFIG_SPIRAM_SPEED_80M=y

components/esp_hw_support/test_apps/mspi_psram_with_dfs/sdkconfig.ci.f8r8_80ddr_40ddr

@@ -0,0 +1,9 @@
+# Legacy, F8R8, Flash 80M DDR, PSRAM 40M DDR
+
+CONFIG_ESPTOOLPY_OCT_FLASH=y
+CONFIG_ESPTOOLPY_FLASH_SAMPLE_MODE_DTR=y
+CONFIG_ESPTOOLPY_FLASHFREQ_80M=y
+CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y
+CONFIG_SPIRAM=y
+CONFIG_SPIRAM_MODE_OCT=y
+CONFIG_SPIRAM_SPEED_40M=y

components/esp_hw_support/test_apps/mspi_psram_with_dfs/sdkconfig.ci.f8r8_80ddr_80ddr

@@ -0,0 +1,9 @@
+# Legacy, F8R8, Flash 80M DDR, PSRAM 80M DDR
+
+CONFIG_ESPTOOLPY_OCT_FLASH=y
+CONFIG_ESPTOOLPY_FLASH_SAMPLE_MODE_DTR=y
+CONFIG_ESPTOOLPY_FLASHFREQ_80M=y
+CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y
+CONFIG_SPIRAM=y
+CONFIG_SPIRAM_MODE_OCT=y
+CONFIG_SPIRAM_SPEED_80M=y

components/esp_hw_support/test_apps/mspi_psram_with_dfs/sdkconfig.ci.f8r8_80ddr_80ddr_ecc

@@ -0,0 +1,10 @@
+# Legacy, F8R8, Flash 80M DDR, PSRAM 80M DDR
+
+CONFIG_ESPTOOLPY_OCT_FLASH=y
+CONFIG_ESPTOOLPY_FLASH_SAMPLE_MODE_DTR=y
+CONFIG_ESPTOOLPY_FLASHFREQ_80M=y
+CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y
+CONFIG_SPIRAM=y
+CONFIG_SPIRAM_MODE_OCT=y
+CONFIG_SPIRAM_SPEED_80M=y
+CONFIG_SPIRAM_ECC_ENABLE = y

components/esp_hw_support/test_apps/mspi_psram_with_dfs/sdkconfig.ci.f8r8_80sdr_80ddr

@@ -0,0 +1,9 @@
+# Legacy, F8R8, Flash 80M SDR, PSRAM 80M DDR
+
+CONFIG_ESPTOOLPY_OCT_FLASH=y
+CONFIG_ESPTOOLPY_FLASH_SAMPLE_MODE_STR=y
+CONFIG_ESPTOOLPY_FLASHFREQ_80M=y
+CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y
+CONFIG_SPIRAM=y
+CONFIG_SPIRAM_MODE_OCT=y
+CONFIG_SPIRAM_SPEED_80M=y

components/esp_hw_support/test_apps/mspi_psram_with_dfs/sdkconfig.defaults

@@ -0,0 +1,8 @@
+CONFIG_FREERTOS_HZ=1000
+
+# For test access psram with DFS enabled
+CONFIG_SPIRAM_FETCH_INSTRUCTIONS=y
+CONFIG_SPIRAM_RODATA=y
+CONFIG_PM_ENABLE=y
+CONFIG_FREERTOS_USE_TICKLESS_IDLE=y
+CONFIG_FREERTOS_IDLE_TIME_BEFORE_SLEEP=5