esp32s3/memprot: Fix DRAM fault address calculation

components/hal/esp32s3/include/hal/memprot_ll.h

@@ -627,7 +627,7 @@ static inline memprot_hal_err_t memprot_ll_iram0_get_monitor_status_fault_addr(c
             return MEMP_HAL_ERR_CORE_INVALID;
     }
 
-    *addr = (void*)(reg_off > 0 ? (reg_off << I_D_FAULT_ADDR_SHIFT) + IRAM0_ADDRESS_LOW : 0);
+    *addr = (void*)(reg_off > 0 ? (reg_off << I_FAULT_ADDR_SHIFT) + IRAM0_ADDRESS_LOW : 0);
 
     return MEMP_HAL_OK;
 }
@@ -1646,7 +1646,7 @@ static inline memprot_hal_err_t memprot_ll_dram0_get_monitor_status_fault_addr(c
             return MEMP_HAL_ERR_CORE_INVALID;
     }
 
-    *addr = (void*)(reg_off > 0 ? (reg_off << I_D_FAULT_ADDR_SHIFT) + IRAM0_ADDRESS_LOW : 0);
+    *addr = (void*)(reg_off > 0 ? (reg_off << D_FAULT_ADDR_SHIFT) + DRAM0_ADDRESS_LOW : 0);
 
     return MEMP_HAL_OK;
 }

components/soc/esp32s3/include/soc/memprot_defs.h

@@ -39,7 +39,8 @@ typedef union {
 #define I_D_SRAM_SEGMENT_SIZE       0x10000
 #define I_D_SPLIT_LINE_ALIGN        0x100
 #define I_D_SPLIT_LINE_SHIFT        0x8
-#define I_D_FAULT_ADDR_SHIFT        0x2
+#define I_FAULT_ADDR_SHIFT          0x2
+#define D_FAULT_ADDR_SHIFT          0x4
 
 //Icache
 #define SENSITIVE_CORE_X_ICACHE_PMS_CONSTRAIN_SRAM_WORLD_X_R  0x1