Merge branch 'feature/esp32h2_clock_basic_support' into 'master'

clk: Add basic clock support for esp32h2

Closes IDF-6265 and IDF-5973

See merge request espressif/esp-idf!21943

Kconfig

@@ -13,7 +13,6 @@ mainmenu "Espressif IoT Development Framework Configuration"
     config IDF_ENV_FPGA
         # This option is for internal use only
         bool
-        default "y" if IDF_TARGET_ESP32H2 # TODO: IDF-5630
         option env="IDF_ENV_FPGA"
 
     config IDF_CI_BUILD

components/bootloader_support/src/bootloader_clock_init.c

@@ -33,8 +33,8 @@ __attribute__((weak)) void bootloader_clock_configure(void)
     // and will be done with the bootloader much earlier than UART FIFO is empty.
     esp_rom_uart_tx_wait_idle(0);
 
-    /* Set CPU to 80MHz. Keep other clocks unmodified. */
-    int cpu_freq_mhz = 80;
+    /* Set CPU to a higher certain frequency. Keep other clocks unmodified. */
+    int cpu_freq_mhz = CPU_CLK_FREQ_MHZ_BTLD;
 
 #if CONFIG_IDF_TARGET_ESP32
     /* On ESP32 rev 0, switching to 80/160 MHz if clock was previously set to
@@ -46,8 +46,6 @@ __attribute__((weak)) void bootloader_clock_configure(void)
             clk_ll_cpu_get_freq_mhz_from_pll() == CLK_LL_PLL_240M_FREQ_MHZ) {
         cpu_freq_mhz = 240;
     }
-#elif CONFIG_IDF_TARGET_ESP32H4
-    cpu_freq_mhz = 64;
 #endif
 
     if (esp_rom_get_reset_reason(0) != RESET_REASON_CPU0_SW || rtc_clk_apb_freq_get() < APB_CLK_FREQ) {
@@ -114,7 +112,7 @@ __attribute__((weak)) void bootloader_clock_configure(void)
     SET_PERI_REG_MASK(LP_ANALOG_PERI_LP_ANA_LP_INT_CLR_REG, LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_CLR);    /* BROWN_OUT */
     SET_PERI_REG_MASK(LP_WDT_INT_CLR_REG, LP_WDT_LP_WDT_INT_CLR);                                           /* WDT */
     SET_PERI_REG_MASK(PMU_HP_INT_CLR_REG, PMU_SOC_WAKEUP_INT_CLR);                                          /* SLP_REJECT */
-    SET_PERI_REG_MASK(PMU_SOC_SLEEP_REJECT_INT_CLR, PMU_SOC_SLEEP_REJECT_INT_CLR);                          /* SLP_WAKEUP */
+    SET_PERI_REG_MASK(PMU_HP_INT_CLR_REG, PMU_SOC_SLEEP_REJECT_INT_CLR);                                    /* SLP_WAKEUP */
 #else
     REG_WRITE(RTC_CNTL_INT_ENA_REG, 0);
     REG_WRITE(RTC_CNTL_INT_CLR_REG, UINT32_MAX);

components/bootloader_support/src/esp32h2/bootloader_esp32h2.c

@@ -43,7 +43,7 @@
 #include "hal/cache_hal.h"
 #include "soc/lp_wdt_reg.h"
 #include "hal/efuse_hal.h"
-
+#include "modem/modem_lpcon_reg.h"
 
 static const char *TAG = "boot.esp32h2";
 
@@ -86,8 +86,9 @@ static void bootloader_super_wdt_auto_feed(void)
 
 static inline void bootloader_hardware_init(void)
 {
-    // ESP32H2-TODO: IDF-5990
-    SET_PERI_REG_MASK(MODEM_LPCON_CLK_CONF_FORCE_ON_REG, MODEM_LPCON_CLK_I2C_MST_FO);
+    // TODO: IDF-6267
+    /* Enable analog i2c master clock */
+    SET_PERI_REG_MASK(MODEM_LPCON_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_EN);
 }
 
 static inline void bootloader_ana_reset_config(void)

components/driver/ledc/ledc.c

@@ -404,7 +404,9 @@ static uint32_t ledc_auto_clk_divisor(ledc_mode_t speed_mode, int freq_hz, uint3
     return ret;
 }
 
+#if !CONFIG_IDF_TARGET_ESP32H2 // TODO: IDF-6267 Remove when H2 light sleep supported
 extern void esp_sleep_periph_use_8m(bool use_or_not);
+#endif
 
 /**
  * @brief Function setting the LEDC timer divisor with the given source clock,
@@ -502,7 +504,9 @@ static esp_err_t ledc_set_timer_div(ledc_mode_t speed_mode, ledc_timer_t timer_n
         ESP_LOGD(LEDC_TAG, "In slow speed mode, global clk set: %d", glb_clk);
 
         /* keep ESP_PD_DOMAIN_RC_FAST on during light sleep */
+#if !CONFIG_IDF_TARGET_ESP32H2 // TODO: IDF-6267 Remove when H2 light sleep supported
         esp_sleep_periph_use_8m(glb_clk == LEDC_SLOW_CLK_RC_FAST);
+#endif
 
         portENTER_CRITICAL(&ledc_spinlock);
         ledc_hal_set_slow_clk_sel(&(p_ledc_obj[speed_mode]->ledc_hal), glb_clk);

components/esp_hw_support/CMakeLists.txt

@@ -105,7 +105,8 @@ if(NOT BOOTLOADER_BUILD)
     if(CONFIG_IDF_TARGET_ESP32H2)
         list(REMOVE_ITEM srcs
                 "adc_share_hw_ctrl.c" # TODO: IDF-6215
-                "port/clk_tree_common.c" # TODO: IDF-6265
+                "sleep_cpu.c"         # TODO: IDF-6267
+                "sleep_modes.c"       # TODO: IDF-6267
             )
     endif()
 else()

components/esp_hw_support/esp_clk.c

@@ -38,6 +38,9 @@
 #elif CONFIG_IDF_TARGET_ESP32C6
 #include "esp32c6/rom/rtc.h"
 #include "esp32c6/rtc.h"
+#elif CONFIG_IDF_TARGET_ESP32H2
+#include "esp32h2/rom/rtc.h"
+#include "esp32h2/rtc.h"
 #endif
 
 #define MHZ (1000000)
@@ -73,7 +76,7 @@ int IRAM_ATTR esp_clk_cpu_freq(void)
 int IRAM_ATTR esp_clk_apb_freq(void)
 {
     // TODO: IDF-5173 Require cleanup, implementation should be unified
-#if CONFIG_IDF_TARGET_ESP32C6
+#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2
     return rtc_clk_apb_freq_get();
 #else
     return MIN(s_get_cpu_freq_mhz() * MHZ, APB_CLK_FREQ);

components/esp_hw_support/port/clk_tree_common.c

@@ -182,6 +182,10 @@ uint32_t clk_tree_lp_fast_get_freq_hz(clk_tree_src_freq_precision_t precision)
 #endif
     case SOC_RTC_FAST_CLK_SRC_RC_FAST:
         return clk_tree_rc_fast_get_freq_hz(precision) / clk_ll_rc_fast_get_divider();
+#if SOC_CLK_LP_FAST_SUPPORT_LP_PLL
+    case SOC_RTC_FAST_CLK_SRC_LP_PLL:
+        return clk_ll_lp_pll_get_freq_mhz() * MHZ;
+#endif
     default:
         // Invalid clock source
         assert(false);

components/esp_hw_support/port/esp32h2/CMakeLists.txt

@@ -1,8 +1,8 @@
 set(srcs "rtc_clk_init.c"
          "rtc_clk.c"
-         # "rtc_init.c"     // ESP32H2-TODO
-         # "rtc_pm.c"       // ESP32H2-TODO
-         # "rtc_sleep.c"    // ESP32H2-TODO
+         "pmu_param.c"
+         "pmu_init.c"
+         "pmu_sleep.c"
          "rtc_time.c"
          "chip_info.c"
          )

components/esp_hw_support/port/esp32h2/clk_tree.c

@@ -9,10 +9,12 @@
 #include "esp_err.h"
 #include "esp_check.h"
 #include "soc/rtc.h"
+#include "hal/clk_tree_hal.h"
+#include "hal/clk_tree_ll.h"
+#include "esp_private/clk_tree_common.h"
 
 static const char *TAG = "clk_tree";
 
-// TODO: IDF-6265
 esp_err_t clk_tree_src_get_freq_hz(soc_module_clk_t clk_src, clk_tree_src_freq_precision_t precision,
 uint32_t *freq_value)
 {
@@ -22,17 +24,32 @@ uint32_t *freq_value)
 
     uint32_t clk_src_freq = 0;
     switch (clk_src) {
+    case SOC_MOD_CLK_CPU:
+        clk_src_freq = clk_hal_cpu_get_freq_hz();
+        break;
     case SOC_MOD_CLK_XTAL:
-        clk_src_freq = 32 * MHZ;
+        clk_src_freq = clk_hal_xtal_get_freq_mhz() * MHZ;
+        break;
+    case SOC_MOD_CLK_PLL_F48M:
+        clk_src_freq = CLK_LL_PLL_48M_FREQ_MHZ * MHZ;
+        break;
+    case SOC_MOD_CLK_PLL_F64M:
+        clk_src_freq = CLK_LL_PLL_64M_FREQ_MHZ * MHZ;
         break;
     case SOC_MOD_CLK_PLL_F96M:
-        clk_src_freq = 96 * MHZ;
+        clk_src_freq = CLK_LL_PLL_96M_FREQ_MHZ * MHZ;
         break;
-    case SOC_MOD_CLK_PLL_F48M:
-        clk_src_freq = 48 * MHZ;
+    case SOC_MOD_CLK_RTC_SLOW:
+        clk_src_freq = clk_tree_lp_slow_get_freq_hz(precision);
+        break;
+    case SOC_MOD_CLK_RTC_FAST:
+        clk_src_freq = clk_tree_lp_fast_get_freq_hz(precision);
         break;
     case SOC_MOD_CLK_RC_FAST:
-        clk_src_freq = SOC_CLK_RC_FAST_FREQ_APPROX;
+        clk_src_freq = clk_tree_rc_fast_get_freq_hz(precision);
+        break;
+    case SOC_MOD_CLK_XTAL32K:
+        clk_src_freq = clk_tree_xtal32k_get_freq_hz(precision);
         break;
     default:
         break;

components/esp_hw_support/port/esp32h2/pmu_init.c

@@ -0,0 +1,222 @@
+/*
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <esp_types.h>
+#include "sdkconfig.h"
+#include "esp_attr.h"
+#include "soc/soc.h"
+#include "soc/pmu_struct.h"
+#include "hal/pmu_hal.h"
+#include "pmu_param.h"
+#include "esp_private/esp_pmu.h"
+#include "soc/regi2c_pmu.h"
+#include "regi2c_ctrl.h"
+
+// TODO: IDF-6267
+
+static __attribute__((unused)) const char *TAG = "pmu_init";
+
+typedef struct {
+    const pmu_hp_system_power_param_t     *power;
+    const pmu_hp_system_clock_param_t     *clock;
+    const pmu_hp_system_digital_param_t   *digital;
+    const pmu_hp_system_analog_param_t    *analog;
+    const pmu_hp_system_retention_param_t *retent;
+} pmu_hp_system_param_t;
+
+typedef struct {
+    const pmu_lp_system_power_param_t  *power;
+    const pmu_lp_system_analog_param_t *analog;
+} pmu_lp_system_param_t;
+
+pmu_context_t * __attribute__((weak)) IRAM_ATTR PMU_instance(void)
+{
+    /* It should be explicitly defined in the internal RAM, because this
+     * instance will be used in pmu_sleep.c */
+    static DRAM_ATTR pmu_hal_context_t pmu_hal = { .dev = &PMU };
+    // static DRAM_ATTR pmu_sleep_machine_constant_t pmu_mc = PMU_SLEEP_MC_DEFAULT();
+    static DRAM_ATTR pmu_context_t pmu_context = { .hal = &pmu_hal,
+                                                //    .mc = (void *)&pmu_mc
+                                                 };
+    return &pmu_context;
+}
+
+void pmu_hp_system_init(pmu_context_t *ctx, pmu_hp_mode_t mode, pmu_hp_system_param_t *param)
+{
+    const pmu_hp_system_power_param_t *power = param->power;
+    const pmu_hp_system_clock_param_t *clock = param->clock;
+    const pmu_hp_system_digital_param_t *dig = param->digital;
+    const pmu_hp_system_analog_param_t *anlg = param->analog;
+    const pmu_hp_system_retention_param_t *ret = param->retent;
+
+    assert(ctx->hal);
+    /* Default configuration of hp-system power in active, modem and sleep modes */
+    pmu_ll_hp_set_dig_power(ctx->hal->dev, mode, power->dig_power.val);
+    pmu_ll_hp_set_clk_power(ctx->hal->dev, mode, power->clk_power.val);
+    pmu_ll_hp_set_xtal_xpd (ctx->hal->dev, mode, power->xtal.xpd_xtal);
+
+    /* Default configuration of hp-system clock in active, modem and sleep modes */
+    pmu_ll_hp_set_icg_func          (ctx->hal->dev, mode, clock->icg_func);
+    pmu_ll_hp_set_icg_apb           (ctx->hal->dev, mode, clock->icg_apb);
+    pmu_ll_hp_set_icg_modem         (ctx->hal->dev, mode, clock->icg_modem.code);
+    pmu_ll_hp_set_sysclk_nodiv      (ctx->hal->dev, mode, clock->sysclk.dig_sysclk_nodiv);
+    pmu_ll_hp_set_icg_sysclk_enable (ctx->hal->dev, mode, clock->sysclk.icg_sysclk_en);
+    pmu_ll_hp_set_sysclk_slp_sel    (ctx->hal->dev, mode, clock->sysclk.sysclk_slp_sel);
+    pmu_ll_hp_set_icg_sysclk_slp_sel(ctx->hal->dev, mode, clock->sysclk.icg_slp_sel);
+    pmu_ll_hp_set_dig_sysclk        (ctx->hal->dev, mode, clock->sysclk.dig_sysclk_sel);
+
+    /* Default configuration of hp-system digital sub-system in active, modem
+     * and sleep modes */
+    pmu_ll_hp_set_uart_wakeup_enable(ctx->hal->dev, mode, dig->syscntl.uart_wakeup_en);
+    pmu_ll_hp_set_hold_all_lp_pad   (ctx->hal->dev, mode, dig->syscntl.lp_pad_hold_all);
+    pmu_ll_hp_set_hold_all_hp_pad   (ctx->hal->dev, mode, dig->syscntl.hp_pad_hold_all);
+    pmu_ll_hp_set_dig_pad_slp_sel   (ctx->hal->dev, mode, dig->syscntl.dig_pad_slp_sel);
+    pmu_ll_hp_set_pause_watchdog    (ctx->hal->dev, mode, dig->syscntl.dig_pause_wdt);
+    pmu_ll_hp_set_cpu_stall         (ctx->hal->dev, mode, dig->syscntl.dig_cpu_stall);
+
+    /* Default configuration of hp-system analog sub-system in active, modem and
+     * sleep modes */
+    pmu_ll_hp_set_bias_xpd                    (ctx->hal->dev, mode, anlg->bias.xpd_bias);
+    pmu_ll_hp_set_trx_xpd                     (ctx->hal->dev, mode, anlg->bias.xpd_trx);
+    pmu_ll_hp_set_current_power_off           (ctx->hal->dev, mode, anlg->bias.pd_cur);
+    pmu_ll_hp_set_bias_sleep_enable           (ctx->hal->dev, mode, anlg->bias.bias_sleep);
+    pmu_ll_hp_set_regulator_sleep_memory_xpd  (ctx->hal->dev, mode, anlg->regulator0.slp_mem_xpd);
+    pmu_ll_hp_set_regulator_sleep_logic_xpd   (ctx->hal->dev, mode, anlg->regulator0.slp_logic_xpd);
+    pmu_ll_hp_set_regulator_xpd               (ctx->hal->dev, mode, anlg->regulator0.xpd);
+    pmu_ll_hp_set_regulator_sleep_memory_dbias(ctx->hal->dev, mode, anlg->regulator0.slp_mem_dbias);
+    pmu_ll_hp_set_regulator_sleep_logic_dbias (ctx->hal->dev, mode, anlg->regulator0.slp_logic_dbias);
+    pmu_ll_hp_set_regulator_dbias             (ctx->hal->dev, mode, anlg->regulator0.dbias);
+    pmu_ll_hp_set_regulator_driver_bar        (ctx->hal->dev, mode, anlg->regulator1.drv_b);
+
+    /* Default configuration of hp-system retention sub-system in active, modem
+     * and sleep modes */
+    pmu_ll_hp_set_retention_param(ctx->hal->dev, mode, ret->retention.val);
+    pmu_ll_hp_set_backup_icg_func(ctx->hal->dev, mode, ret->backup_clk);
+
+    // /* Some PMU initial parameter configuration */
+    // pmu_ll_imm_update_dig_icg_modem_code(ctx->hal->dev, true);
+    // pmu_ll_imm_update_dig_icg_switch(ctx->hal->dev, true);
+
+    // pmu_ll_hp_set_sleep_protect_mode(ctx->hal->dev, PMU_SLEEP_PROTECT_HP_LP_SLEEP);
+}
+
+void pmu_lp_system_init(pmu_context_t *ctx, pmu_lp_mode_t mode, pmu_lp_system_param_t *param)
+{
+    const pmu_lp_system_power_param_t *power = param->power;
+    const pmu_lp_system_analog_param_t *anlg = param->analog;
+
+    assert(ctx->hal);
+    /* Default configuration of lp-system power in active and sleep modes */
+    pmu_ll_lp_set_dig_power(ctx->hal->dev, mode, power->dig_power.val);
+    pmu_ll_lp_set_clk_power(ctx->hal->dev, mode, power->clk_power.val);
+    pmu_ll_lp_set_xtal_xpd (ctx->hal->dev, PMU_MODE_LP_SLEEP, power->xtal.xpd_xtal);
+
+    /* Default configuration of lp-system analog sub-system in active and
+     * sleep modes */
+    pmu_ll_lp_set_bias_xpd             (ctx->hal->dev, PMU_MODE_LP_SLEEP, anlg->bias.xpd_bias);
+    pmu_ll_lp_set_current_power_off    (ctx->hal->dev, PMU_MODE_LP_SLEEP, anlg->bias.pd_cur);
+    pmu_ll_lp_set_bias_sleep_enable    (ctx->hal->dev, PMU_MODE_LP_SLEEP, anlg->bias.bias_sleep);
+    pmu_ll_lp_set_regulator_slp_xpd    (ctx->hal->dev, mode, anlg->regulator0.slp_xpd);
+    pmu_ll_lp_set_regulator_xpd        (ctx->hal->dev, mode, anlg->regulator0.xpd);
+    pmu_ll_lp_set_regulator_sleep_dbias(ctx->hal->dev, mode, anlg->regulator0.slp_dbias);
+    pmu_ll_lp_set_regulator_dbias      (ctx->hal->dev, mode, anlg->regulator0.dbias);
+    pmu_ll_lp_set_regulator_driver_bar (ctx->hal->dev, mode, anlg->regulator1.drv_b);
+}
+
+static inline void pmu_power_domain_force_default(pmu_context_t *ctx)
+{
+    assert(ctx);
+    // for bypass reserved power domain
+    const pmu_hp_power_domain_t pmu_hp_domains[] = {
+        PMU_HP_PD_TOP,
+        PMU_HP_PD_AON,
+        PMU_HP_PD_CPU,
+        PMU_HP_PD_WIFI
+    };
+
+    for (uint8_t idx = 0; idx < (sizeof(pmu_hp_domains) / sizeof(pmu_hp_power_domain_t)); idx++) {
+        pmu_ll_hp_set_power_force_reset     (ctx->hal->dev, pmu_hp_domains[idx], false);
+        pmu_ll_hp_set_power_force_isolate   (ctx->hal->dev, pmu_hp_domains[idx], false);
+        pmu_ll_hp_set_power_force_power_up  (ctx->hal->dev, pmu_hp_domains[idx], false);
+        pmu_ll_hp_set_power_force_no_reset  (ctx->hal->dev, pmu_hp_domains[idx], false);
+        pmu_ll_hp_set_power_force_no_isolate(ctx->hal->dev, pmu_hp_domains[idx], false);
+        pmu_ll_hp_set_power_force_power_down(ctx->hal->dev, pmu_hp_domains[idx], false);
+    }
+    // /* Isolate all memory banks while sleeping, avoid memory leakage current */
+    // pmu_ll_hp_set_memory_no_isolate     (ctx->hal->dev, 0);
+
+    pmu_ll_lp_set_power_force_reset     (ctx->hal->dev, false);
+    pmu_ll_lp_set_power_force_isolate   (ctx->hal->dev, false);
+    pmu_ll_lp_set_power_force_power_up  (ctx->hal->dev, false);
+    pmu_ll_lp_set_power_force_no_reset  (ctx->hal->dev, false);
+    pmu_ll_lp_set_power_force_no_isolate(ctx->hal->dev, false);
+    pmu_ll_lp_set_power_force_power_down(ctx->hal->dev, false);
+}
+
+static inline void pmu_hp_system_param_default(pmu_hp_mode_t mode, pmu_hp_system_param_t *param)
+{
+    param->power = pmu_hp_system_power_param_default(mode);
+    param->clock = pmu_hp_system_clock_param_default(mode);
+    param->digital = pmu_hp_system_digital_param_default(mode);
+    param->analog = pmu_hp_system_analog_param_default(mode);
+    param->retent = pmu_hp_system_retention_param_default(mode);
+}
+
+static void pmu_hp_system_init_default(pmu_context_t *ctx)
+{
+    assert(ctx);
+    pmu_hp_system_param_t param = { 0 };
+    for (pmu_hp_mode_t mode = PMU_MODE_HP_ACTIVE; mode < PMU_MODE_HP_MAX; mode++) {
+        pmu_hp_system_param_default(mode, &param);
+        pmu_hp_system_init(ctx, mode, &param);
+    }
+}
+
+static inline void pmu_lp_system_param_default(pmu_lp_mode_t mode, pmu_lp_system_param_t *param)
+{
+    param->power = pmu_lp_system_power_param_default(mode);
+    param->analog = pmu_lp_system_analog_param_default(mode);
+}
+
+static void pmu_lp_system_init_default(pmu_context_t *ctx)
+{
+    assert(ctx);
+    pmu_lp_system_param_t param;
+    for (pmu_lp_mode_t mode = PMU_MODE_LP_ACTIVE; mode < PMU_MODE_LP_MAX; mode++) {
+        pmu_lp_system_param_default(mode, &param);
+        pmu_lp_system_init(ctx, mode, &param);
+    }
+}
+
+void pmu_init()
+{
+    /* No peripheral reg i2c power up required on the target */
+
+    REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_EN_I2C_RTC_DREG, 0);
+    REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_EN_I2C_DIG_DREG, 0);
+    REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_EN_I2C_RTC_DREG_SLP, 0);
+    REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_EN_I2C_DIG_DREG_SLP, 0);
+    REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_OR_XPD_RTC_REG, 0);
+    REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_OR_XPD_DIG_REG, 0);
+    REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_OR_XPD_TRX, 0);
+
+    WRITE_PERI_REG(PMU_POWER_PD_TOP_CNTL_REG, 0);
+    WRITE_PERI_REG(PMU_POWER_PD_HPAON_CNTL_REG, 0);
+    WRITE_PERI_REG(PMU_POWER_PD_HPCPU_CNTL_REG, 0);
+    WRITE_PERI_REG(PMU_POWER_PD_HPPERI_RESERVE_REG, 0);
+    WRITE_PERI_REG(PMU_POWER_PD_HPWIFI_CNTL_REG, 0);
+    WRITE_PERI_REG(PMU_POWER_PD_LPPERI_CNTL_REG, 0);
+
+    pmu_hp_system_init_default(PMU_instance());
+    pmu_lp_system_init_default(PMU_instance());
+
+    pmu_power_domain_force_default(PMU_instance());
+
+    REG_SET_FIELD(PMU_SLP_WAKEUP_CNTL5_REG, PMU_LP_ANA_WAIT_TARGET, 15);    // wait lp ldo stable when wakeup from sleep, need about 100us (slow clk)
+    REG_SET_FIELD(PMU_SLP_WAKEUP_CNTL7_REG, PMU_ANA_WAIT_TARGET, 1700);   // wait hp ldo stable when wakeup from sleep, need about 100us (fast clk)
+}

components/esp_hw_support/port/esp32h2/pmu_param.c

@@ -0,0 +1,438 @@
+/*
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <esp_types.h>
+#include "sdkconfig.h"
+#include "soc/soc.h"
+#include "pmu_param.h"
+#include "soc/pmu_icg_mapping.h"
+#include "esp_private/esp_pmu.h"
+
+#ifndef ARRAY_SIZE
+#define ARRAY_SIZE(a)   (sizeof(a) / sizeof((a)[0]))
+#endif
+
+//TODO: IDF-6254
+#define PMU_HP_ACTIVE_POWER_CONFIG_DEFAULT() { \
+    .dig_power = {          \
+        .vdd_spi_pd_en = 0, \
+        .mem_dslp      = 0, \
+        .mem_pd_en     = 0, \
+        .wifi_pd_en    = 0, \
+        .cpu_pd_en     = 0, \
+        .aon_pd_en     = 0, \
+        .top_pd_en     = 0  \
+    }, \
+    .clk_power = {          \
+        .i2c_iso_en    = 0, \
+        .i2c_retention = 0, \
+        .xpd_bb_i2c    = 1, \
+        .xpd_bbpll_i2c = 1, \
+        .xpd_bbpll     = 1  \
+    }, \
+    .xtal = {               \
+        .xpd_xtal      = 1  \
+    } \
+}
+
+#define PMU_HP_MODEM_POWER_CONFIG_DEFAULT() { \
+    .dig_power = {          \
+        .vdd_spi_pd_en = 0, \
+        .mem_dslp      = 1, \
+        .mem_pd_en     = 0, \
+        .wifi_pd_en    = 0, \
+        .cpu_pd_en     = 1, \
+        .aon_pd_en     = 0, \
+        .top_pd_en     = 0  \
+    }, \
+    .clk_power = {          \
+        .i2c_iso_en    = 0, \
+        .i2c_retention = 0, \
+        .xpd_bb_i2c    = 1, \
+        .xpd_bbpll_i2c = 1, \
+        .xpd_bbpll     = 1  \
+    }, \
+    .xtal = {               \
+        .xpd_xtal      = 1  \
+    } \
+}
+
+#define PMU_HP_SLEEP_POWER_CONFIG_DEFAULT() { \
+    .dig_power = {          \
+        .vdd_spi_pd_en = 1, \
+        .mem_dslp      = 0, \
+        .mem_pd_en     = 0, \
+        .wifi_pd_en    = 1, \
+        .cpu_pd_en     = 1, \
+        .aon_pd_en     = 0, \
+        .top_pd_en     = 1  \
+    }, \
+    .clk_power = {          \
+        .i2c_iso_en    = 1, \
+        .i2c_retention = 0, \
+        .xpd_bb_i2c    = 0, \
+        .xpd_bbpll_i2c = 0, \
+        .xpd_bbpll     = 0, \
+    }, \
+    .xtal = {               \
+        .xpd_xtal      = 0  \
+    } \
+}
+
+const pmu_hp_system_power_param_t * pmu_hp_system_power_param_default(pmu_hp_mode_t mode)
+{
+    static const pmu_hp_system_power_param_t hp_power[] = {
+        PMU_HP_ACTIVE_POWER_CONFIG_DEFAULT(),
+        PMU_HP_MODEM_POWER_CONFIG_DEFAULT(),
+        PMU_HP_SLEEP_POWER_CONFIG_DEFAULT()
+    };
+    assert(mode < ARRAY_SIZE(hp_power));
+    return &hp_power[mode];
+}
+
+#define PMU_HP_ACTIVE_CLOCK_CONFIG_DEFAULT() {  \
+    .icg_func   = 0xffffffff,                   \
+    .icg_apb    = 0xffffffff,                   \
+    .icg_modem  = {                             \
+        .code = 0                               \
+    }, \
+    .sysclk     = {                             \
+        .dig_sysclk_nodiv = 0,                  \
+        .icg_sysclk_en    = 1,                  \
+        .sysclk_slp_sel   = 0,                  \
+        .icg_slp_sel      = 0,                  \
+        .dig_sysclk_sel   = PMU_HP_SYSCLK_XTAL  \
+    } \
+}
+
+#define PMU_HP_MODEM_CLOCK_CONFIG_DEFAULT() {   \
+    .icg_func   = 0,                            \
+    .icg_apb    = 0,                            \
+    .icg_modem  = {                             \
+        .code = 0                               \
+    }, \
+    .sysclk     = {                             \
+        .dig_sysclk_nodiv = 0,                  \
+        .icg_sysclk_en    = 1,                  \
+        .sysclk_slp_sel   = 1,                  \
+        .icg_slp_sel      = 1,                  \
+        .dig_sysclk_sel   = PMU_HP_SYSCLK_PLL   \
+    } \
+}
+
+#define PMU_HP_SLEEP_CLOCK_CONFIG_DEFAULT() {   \
+    .icg_func   = 0,                            \
+    .icg_apb    = 0,                            \
+    .icg_modem  = {                             \
+        .code = 2                               \
+    }, \
+    .sysclk     = {                             \
+        .dig_sysclk_nodiv = 0,                  \
+        .icg_sysclk_en    = 0,                  \
+        .sysclk_slp_sel   = 1,                  \
+        .icg_slp_sel      = 1,                  \
+        .dig_sysclk_sel   = PMU_HP_SYSCLK_XTAL  \
+    } \
+}
+
+const pmu_hp_system_clock_param_t * pmu_hp_system_clock_param_default(pmu_hp_mode_t mode)
+{
+    static const pmu_hp_system_clock_param_t hp_clock[] = {
+        PMU_HP_ACTIVE_CLOCK_CONFIG_DEFAULT(),
+        PMU_HP_MODEM_CLOCK_CONFIG_DEFAULT(),
+        PMU_HP_SLEEP_CLOCK_CONFIG_DEFAULT()
+    };
+    assert(mode < ARRAY_SIZE(hp_clock));
+    return &hp_clock[mode];
+}
+
+#define PMU_HP_ACTIVE_DIGITAL_CONFIG_DEFAULT() { \
+    .syscntl = {                \
+        .uart_wakeup_en  = 0,   \
+        .lp_pad_hold_all = 0,   \
+        .hp_pad_hold_all = 0,   \
+        .dig_pad_slp_sel = 0,   \
+        .dig_pause_wdt   = 0,   \
+        .dig_cpu_stall   = 0    \
+    } \
+}
+
+#define PMU_HP_MODEM_DIGITAL_CONFIG_DEFAULT() { \
+    .syscntl = {                \
+        .uart_wakeup_en  = 1,   \
+        .lp_pad_hold_all = 0,   \
+        .hp_pad_hold_all = 1,   \
+        .dig_pad_slp_sel = 1,   \
+        .dig_pause_wdt   = 1,   \
+        .dig_cpu_stall   = 1    \
+    } \
+}
+
+#define PMU_HP_SLEEP_DIGITAL_CONFIG_DEFAULT() { \
+    .syscntl = {                \
+        .uart_wakeup_en  = 1,   \
+        .lp_pad_hold_all = 1,   \
+        .hp_pad_hold_all = 1,   \
+        .dig_pad_slp_sel = 0,   \
+        .dig_pause_wdt   = 1,   \
+        .dig_cpu_stall   = 1    \
+    } \
+}
+
+const pmu_hp_system_digital_param_t * pmu_hp_system_digital_param_default(pmu_hp_mode_t mode)
+{
+    static const pmu_hp_system_digital_param_t hp_digital[] = {
+        PMU_HP_ACTIVE_DIGITAL_CONFIG_DEFAULT(),
+        PMU_HP_MODEM_DIGITAL_CONFIG_DEFAULT(),
+        PMU_HP_SLEEP_DIGITAL_CONFIG_DEFAULT()
+    };
+    assert(mode < ARRAY_SIZE(hp_digital));
+    return &hp_digital[mode];
+}
+
+#define PMU_HP_ACTIVE_ANALOG_CONFIG_DEFAULT() { \
+    .bias = {                   \
+        .xpd_trx         = 1,   \
+        .xpd_bias        = 1,   \
+        .pd_cur          = 0,   \
+        .bias_sleep      = 0    \
+    }, \
+    .regulator0 = {             \
+        .lp_dbias_vol    = 0xd, \
+        .hp_dbias_vol    = 0x1c,\
+        .dbias_sel       = 1,   \
+        .dbias_init      = 1,   \
+        .slp_mem_xpd     = 0,   \
+        .slp_logic_xpd   = 0,   \
+        .xpd             = 1,   \
+        .slp_mem_dbias   = 0x5, \
+        .slp_logic_dbias = 0xc, \
+        .dbias           = 0xc \
+    }, \
+    .regulator1 = {             \
+        .drv_b           = 0x1a \
+    } \
+}
+
+#define PMU_HP_MODEM_ANALOG_CONFIG_DEFAULT() { \
+    .bias = {                   \
+        .xpd_trx         = 1,   \
+        .xpd_bias        = 1,   \
+        .pd_cur          = 0,   \
+        .bias_sleep      = 0    \
+    }, \
+    .regulator0 = {             \
+        .slp_mem_xpd     = 0,   \
+        .slp_logic_xpd   = 0,   \
+        .xpd             = 1,   \
+        .slp_mem_dbias   = 0x5, \
+        .slp_logic_dbias = 0xc, \
+        .dbias           = 0xd  \
+    }, \
+    .regulator1 = {             \
+        .drv_b           = 0x1b \
+    } \
+}
+
+#define PMU_HP_SLEEP_ANALOG_CONFIG_DEFAULT() { \
+    .bias = {                   \
+        .xpd_trx         = 0,   \
+        .xpd_bias        = 0,   \
+        .pd_cur          = 1,   \
+        .bias_sleep      = 1    \
+    }, \
+    .regulator0 = {             \
+        .slp_mem_xpd     = 1,   \
+        .slp_logic_xpd   = 1,   \
+        .xpd             = 0,   \
+        .slp_mem_dbias   = 0x1, \
+        .slp_logic_dbias = 0x5, \
+        .dbias           = 0  \
+    }, \
+    .regulator1 = {             \
+        .drv_b           = 0x13 \
+    } \
+}
+
+const pmu_hp_system_analog_param_t * pmu_hp_system_analog_param_default(pmu_hp_mode_t mode)
+{
+    static const pmu_hp_system_analog_param_t hp_analog[] = {
+        PMU_HP_ACTIVE_ANALOG_CONFIG_DEFAULT(),
+        PMU_HP_MODEM_ANALOG_CONFIG_DEFAULT(),
+        PMU_HP_SLEEP_ANALOG_CONFIG_DEFAULT()
+    };
+    assert(mode < ARRAY_SIZE(hp_analog));
+    return &hp_analog[mode];
+}
+
+#define PMU_HP_RETENTION_REGDMA_CONFIG(dir, entry)  ((((dir)<<2) | (entry & 0x3)) & 0x7)
+
+#define PMU_HP_ACTIVE_RETENTION_CONFIG_DEFAULT() {  \
+    .retention = {                                  \
+        .hp_sleep2active_backup_modem_clk_code = 3, \
+        .hp_modem2active_backup_modem_clk_code = 1, \
+        .hp_active_retention_mode       = 0, \
+        .hp_sleep2active_retention_en   = 0, \
+        .hp_modem2active_retention_en   = 0, \
+        .hp_sleep2active_backup_clk_sel = 0, \
+        .hp_modem2active_backup_clk_sel = 0, \
+        .hp_sleep2active_backup_mode    = PMU_HP_RETENTION_REGDMA_CONFIG(0, 0), \
+        .hp_modem2active_backup_mode    = PMU_HP_RETENTION_REGDMA_CONFIG(0, 2), \
+        .hp_sleep2active_backup_en      = 0, \
+        .hp_modem2active_backup_en      = 0, \
+    }, \
+    .backup_clk = (BIT(PMU_ICG_FUNC_ENA_REGDMA) \
+        | BIT(PMU_ICG_FUNC_ENA_TG0)             \
+        | BIT(PMU_ICG_FUNC_ENA_HPBUS)           \
+        | BIT(PMU_ICG_FUNC_ENA_MSPI)            \
+        | BIT(PMU_ICG_FUNC_ENA_IOMUX)           \
+        | BIT(PMU_ICG_FUNC_ENA_SPI2)            \
+        | BIT(PMU_ICG_FUNC_ENA_SEC)             \
+        | BIT(PMU_ICG_FUNC_ENA_PWM)             \
+        | BIT(PMU_ICG_FUNC_ENA_SYSTIMER)        \
+        | BIT(PMU_ICG_FUNC_ENA_UART0)),         \
+}
+
+#define PMU_HP_MODEM_RETENTION_CONFIG_DEFAULT() {   \
+    .retention = {                                  \
+        .hp_sleep2modem_backup_modem_clk_code  = 3, \
+        .hp_modem_retention_mode        = 0, \
+        .hp_sleep2modem_retention_en    = 0, \
+        .hp_sleep2modem_backup_clk_sel  = 0, \
+        .hp_sleep2modem_backup_mode     = PMU_HP_RETENTION_REGDMA_CONFIG(0, 1), \
+        .hp_sleep2modem_backup_en       = 0, \
+    }, \
+    .backup_clk = (BIT(PMU_ICG_FUNC_ENA_REGDMA) \
+        | BIT(PMU_ICG_FUNC_ENA_TG0)             \
+        | BIT(PMU_ICG_FUNC_ENA_HPBUS)           \
+        | BIT(PMU_ICG_FUNC_ENA_MSPI)            \
+        | BIT(PMU_ICG_FUNC_ENA_IOMUX)           \
+        | BIT(PMU_ICG_FUNC_ENA_SPI2)            \
+        | BIT(PMU_ICG_FUNC_ENA_SEC)            \
+        | BIT(PMU_ICG_FUNC_ENA_PWM)            \
+        | BIT(PMU_ICG_FUNC_ENA_SYSTIMER)        \
+        | BIT(PMU_ICG_FUNC_ENA_UART0)),         \
+}
+
+#define PMU_HP_SLEEP_RETENTION_CONFIG_DEFAULT() {   \
+    .retention = {                                  \
+        .hp_modem2sleep_backup_modem_clk_code  = 3, \
+        .hp_active2sleep_backup_modem_clk_code = 3, \
+        .hp_sleep_retention_mode        = 0, \
+        .hp_modem2sleep_retention_en    = 0, \
+        .hp_active2sleep_retention_en   = 0, \
+        .hp_modem2sleep_backup_clk_sel  = 0, \
+        .hp_active2sleep_backup_clk_sel = 0, \
+        .hp_modem2sleep_backup_mode     = PMU_HP_RETENTION_REGDMA_CONFIG(1, 1), \
+        .hp_active2sleep_backup_mode    = PMU_HP_RETENTION_REGDMA_CONFIG(1, 0), \
+        .hp_modem2sleep_backup_en       = 0, \
+        .hp_active2sleep_backup_en      = 0, \
+    }, \
+    .backup_clk = (BIT(PMU_ICG_FUNC_ENA_REGDMA) \
+        | BIT(PMU_ICG_FUNC_ENA_TG0)             \
+        | BIT(PMU_ICG_FUNC_ENA_HPBUS)           \
+        | BIT(PMU_ICG_FUNC_ENA_MSPI)            \
+        | BIT(PMU_ICG_FUNC_ENA_IOMUX)           \
+        | BIT(PMU_ICG_FUNC_ENA_SPI2)            \
+        | BIT(PMU_ICG_FUNC_ENA_SEC)            \
+        | BIT(PMU_ICG_FUNC_ENA_PWM)            \
+        | BIT(PMU_ICG_FUNC_ENA_SYSTIMER)        \
+        | BIT(PMU_ICG_FUNC_ENA_UART0)),         \
+}
+
+const pmu_hp_system_retention_param_t * pmu_hp_system_retention_param_default(pmu_hp_mode_t mode)
+{
+    static const pmu_hp_system_retention_param_t hp_retention[] = {
+        PMU_HP_ACTIVE_RETENTION_CONFIG_DEFAULT(),
+        PMU_HP_MODEM_RETENTION_CONFIG_DEFAULT(),
+        PMU_HP_SLEEP_RETENTION_CONFIG_DEFAULT()
+    };
+    assert(mode < ARRAY_SIZE(hp_retention));
+    return &hp_retention[mode];
+}
+
+
+/** LP system default parameter */
+
+#define PMU_LP_ACTIVE_POWER_CONFIG_DEFAULT() { \
+    .dig_power = {              \
+        .mem_dslp       = 0,    \
+        .peri_pd_en     = 0,    \
+    }, \
+    .clk_power = {              \
+        .xpd_xtal32k    = 0,    \
+        .xpd_rc32k      = 0,    \
+        .xpd_fosc       = 1,    \
+        .pd_osc         = 0     \
+    } \
+}
+
+#define PMU_LP_SLEEP_POWER_CONFIG_DEFAULT() { \
+    .dig_power = {              \
+        .mem_dslp       = 1,    \
+        .peri_pd_en     = 0,    \
+    }, \
+    .clk_power = {              \
+        .xpd_xtal32k    = 0,    \
+        .xpd_rc32k      = 0,    \
+        .xpd_fosc       = 0,    \
+        .pd_osc         = 0     \
+    }, \
+    .xtal = {                   \
+        .xpd_xtal       = 0     \
+    } \
+}
+
+const pmu_lp_system_power_param_t * pmu_lp_system_power_param_default(pmu_lp_mode_t mode)
+{
+    static const pmu_lp_system_power_param_t lp_power[] = {
+        PMU_LP_ACTIVE_POWER_CONFIG_DEFAULT(),
+        PMU_LP_SLEEP_POWER_CONFIG_DEFAULT()
+    };
+    assert(mode < ARRAY_SIZE(lp_power));
+    return &lp_power[mode];
+}
+
+#define PMU_LP_ACTIVE_ANALOG_CONFIG_DEFAULT() { \
+    .regulator0 = {         \
+        .slp_xpd    = 0,    \
+        .xpd        = 1,    \
+        .slp_dbias  = 0,  \
+        .dbias      = 0xe  \
+    }, \
+    .regulator1 = {         \
+        .drv_b      = 3     \
+    } \
+}
+
+#define PMU_LP_SLEEP_ANALOG_CONFIG_DEFAULT() { \
+    .bias = {               \
+        .xpd_bias   = 0,    \
+        .pd_cur     = 1,    \
+        .bias_sleep = 1,    \
+    }, \
+    .regulator0 = {         \
+        .slp_xpd    = 1,    \
+        .xpd        = 0,    \
+        .slp_dbias  = 0xf,  \
+        .dbias      = 0  \
+    }, \
+    .regulator1 = {         \
+        .drv_b      = 9     \
+    } \
+}
+
+const pmu_lp_system_analog_param_t * pmu_lp_system_analog_param_default(pmu_lp_mode_t mode)
+{
+    static const pmu_lp_system_analog_param_t lp_analog[] = {
+        PMU_LP_ACTIVE_ANALOG_CONFIG_DEFAULT(),
+        PMU_LP_SLEEP_ANALOG_CONFIG_DEFAULT()
+    };
+    assert(mode < ARRAY_SIZE(lp_analog));
+    return &lp_analog[mode];
+}

components/esp_hw_support/port/esp32h2/pmu_sleep.c

@@ -0,0 +1,7 @@
+/*
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// TODO: IDF-6267

components/esp_hw_support/port/esp32h2/private_include/pmu_param.h

@@ -0,0 +1,110 @@
+/*
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <esp_types.h>
+#include "soc/pmu_struct.h"
+#include "hal/pmu_hal.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct {
+    pmu_hp_dig_power_reg_t  dig_power;
+    pmu_hp_clk_power_reg_t  clk_power;
+    pmu_hp_xtal_reg_t       xtal;
+} pmu_hp_system_power_param_t;
+
+const pmu_hp_system_power_param_t * pmu_hp_system_power_param_default(pmu_hp_mode_t mode);
+
+typedef struct {
+    uint32_t                icg_func;
+    uint32_t                icg_apb;
+    pmu_hp_icg_modem_reg_t  icg_modem;
+    pmu_hp_sysclk_reg_t     sysclk;
+} pmu_hp_system_clock_param_t;
+
+const pmu_hp_system_clock_param_t * pmu_hp_system_clock_param_default(pmu_hp_mode_t mode);
+
+typedef struct {
+    pmu_hp_sys_cntl_reg_t   syscntl;
+} pmu_hp_system_digital_param_t;
+
+const pmu_hp_system_digital_param_t * pmu_hp_system_digital_param_default(pmu_hp_mode_t mode);
+
+typedef struct {
+    pmu_hp_bias_reg_t       bias;
+    pmu_hp_regulator0_reg_t regulator0;
+    pmu_hp_regulator1_reg_t regulator1;
+} pmu_hp_system_analog_param_t;
+
+const pmu_hp_system_analog_param_t * pmu_hp_system_analog_param_default(pmu_hp_mode_t mode);
+
+typedef struct {
+    pmu_hp_backup_reg_t     retention;
+    uint32_t                backup_clk;
+} pmu_hp_system_retention_param_t;
+
+const pmu_hp_system_retention_param_t * pmu_hp_system_retention_param_default(pmu_hp_mode_t mode);
+
+typedef struct {
+    pmu_lp_dig_power_reg_t  dig_power;
+    pmu_lp_clk_power_reg_t  clk_power;
+    pmu_lp_xtal_reg_t       xtal;
+} pmu_lp_system_power_param_t;
+
+const pmu_lp_system_power_param_t * pmu_lp_system_power_param_default(pmu_lp_mode_t mode);
+
+typedef struct {
+    pmu_lp_bias_reg_t       bias;
+    pmu_lp_regulator0_reg_t regulator0;
+    pmu_lp_regulator1_reg_t regulator1;
+} pmu_lp_system_analog_param_t;
+
+const pmu_lp_system_analog_param_t * pmu_lp_system_analog_param_default(pmu_lp_mode_t mode);
+
+
+typedef struct {
+    struct {
+        pmu_hp_power_t  dig_power;
+        pmu_hp_power_t  clk_power;
+        pmu_hp_power_t  xtal;
+    } hp_sys;
+    struct {
+        pmu_lp_power_t  dig_power;
+        pmu_lp_power_t  clk_power;
+        pmu_lp_power_t  xtal;
+    } lp_sys[PMU_MODE_LP_MAX];
+} pmu_sleep_power_config_t;
+
+typedef struct {
+    struct {
+        pmu_hp_analog_t analog;
+    } hp_sys;
+    struct {
+        pmu_lp_analog_t analog;
+    } lp_sys[PMU_MODE_LP_MAX];
+} pmu_sleep_analog_config_t;
+
+typedef struct {
+    pmu_hp_param_t      hp_sys;
+    pmu_lp_param_t      lp_sys;
+    pmu_hp_lp_param_t   hp_lp;
+} pmu_sleep_param_config_t;
+
+typedef struct {
+    pmu_sleep_power_config_t  power;
+    pmu_sleep_analog_config_t analog;
+    pmu_sleep_param_config_t  param;
+} pmu_sleep_config_t;
+
+#ifdef __cplusplus
+}
+#endif

components/esp_hw_support/port/esp32h2/rtc_clk.c

@@ -18,20 +18,102 @@
 #include "hal/usb_serial_jtag_ll.h"
 #include "hal/clk_tree_ll.h"
 #include "hal/regi2c_ctrl_ll.h"
-#include "soc/lp_clkrst_reg.h"
-
+#include "soc/io_mux_reg.h"
+#include "soc/lp_aon_reg.h"
 
 static const char *TAG = "rtc_clk";
 
+// Current PLL frequency, in 96MHz. Zero if PLL is not enabled.
+static int s_cur_pll_freq;
+
+static bool rtc_clk_set_bbpll_always_on(void);
+
+void rtc_clk_32k_enable(bool enable)
+{
+    if (enable) {
+        clk_ll_xtal32k_enable(CLK_LL_XTAL32K_ENABLE_MODE_CRYSTAL);
+    } else {
+        clk_ll_xtal32k_disable();
+    }
+}
+
+void rtc_clk_32k_enable_external(void)
+{
+    // EXT_OSC_SLOW_GPIO_NUM == GPIO_NUM_13
+    PIN_INPUT_ENABLE(IO_MUX_GPIO13_REG);
+    REG_SET_BIT(LP_AON_GPIO_HOLD0_REG, BIT(EXT_OSC_SLOW_GPIO_NUM));
+    clk_ll_xtal32k_enable(CLK_LL_XTAL32K_ENABLE_MODE_EXTERNAL);
+}
+
+void rtc_clk_32k_bootstrap(uint32_t cycle)
+{
+    /* No special bootstrapping needed for ESP32-H2, 'cycle' argument is to keep the signature
+     * same as for the ESP32. Just enable the XTAL here.
+     */
+    (void)cycle;
+    rtc_clk_32k_enable(true);
+}
+
+bool rtc_clk_32k_enabled(void)
+{
+    return clk_ll_xtal32k_is_enabled();
+}
+
+void rtc_clk_rc32k_enable(bool enable)
+{
+    if (enable) {
+        clk_ll_rc32k_enable();
+        esp_rom_delay_us(SOC_DELAY_RC32K_ENABLE);
+    } else {
+        clk_ll_rc32k_disable();
+    }
+}
+
+void rtc_clk_8m_enable(bool clk_8m_en)
+{
+    if (clk_8m_en) {
+        clk_ll_rc_fast_enable();
+        esp_rom_delay_us(SOC_DELAY_RC_FAST_ENABLE);
+    } else {
+        clk_ll_rc_fast_disable();
+    }
+}
+
+bool rtc_clk_8m_enabled(void)
+{
+    return clk_ll_rc_fast_is_enabled();
+}
+
+void rtc_clk_lp_pll_enable(bool enable)
+{
+    if (enable) {
+        clk_ll_lp_pll_enable();
+        esp_rom_delay_us(SOC_DELAY_LP_PLL_ENABLE);
+    } else {
+        clk_ll_lp_pll_disable();
+    }
+}
+
+void rtc_clk_lp_pll_src_set(soc_lp_pll_clk_src_t clk_src)
+{
+    clk_ll_lp_pll_set_src(clk_src);
+    esp_rom_delay_us(SOC_DELAY_LP_PLL_SWITCH);
+}
+
+void rtc_clk_slow_src_set(soc_rtc_slow_clk_src_t clk_src)
+{
+    clk_ll_rtc_slow_set_src(clk_src);
+    esp_rom_delay_us(SOC_DELAY_RTC_SLOW_CLK_SWITCH);
+}
+
 soc_rtc_slow_clk_src_t rtc_clk_slow_src_get(void)
 {
-    // ESP32H2-TODO: IDF-6254
-    return REG_GET_FIELD(LP_CLKRST_LP_CLK_CONF_REG, LP_CLKRST_SLOW_CLK_SEL);
+    return clk_ll_rtc_slow_get_src();
 }
 
 uint32_t rtc_clk_slow_freq_get_hz(void)
 {
-    switch (rtc_clk_slow_freq_get()) {
+    switch (rtc_clk_slow_src_get()) {
     case SOC_RTC_SLOW_CLK_SRC_RC_SLOW: return SOC_CLK_RC_SLOW_FREQ_APPROX;
     case SOC_RTC_SLOW_CLK_SRC_XTAL32K: return SOC_CLK_XTAL32K_FREQ_APPROX;
     case SOC_RTC_SLOW_CLK_SRC_RC32K: return SOC_CLK_RC32K_FREQ_APPROX;
@@ -40,33 +122,295 @@ uint32_t rtc_clk_slow_freq_get_hz(void)
     }
 }
 
+void rtc_clk_fast_src_set(soc_rtc_fast_clk_src_t clk_src)
+{
+    clk_ll_rtc_fast_set_src(clk_src);
+    esp_rom_delay_us(SOC_DELAY_RTC_FAST_CLK_SWITCH);
+}
+
+soc_rtc_fast_clk_src_t rtc_clk_fast_src_get(void)
+{
+    return clk_ll_rtc_fast_get_src();
+}
+
+static void rtc_clk_bbpll_disable(void)
+{
+    clk_ll_bbpll_disable();
+    s_cur_pll_freq = 0;
+}
+
+static void rtc_clk_bbpll_enable(void)
+{
+    clk_ll_bbpll_enable();
+}
+
+static void rtc_clk_bbpll_configure(rtc_xtal_freq_t xtal_freq, int pll_freq)
+{
+    /* Digital part */
+    clk_ll_bbpll_set_freq_mhz(pll_freq);
+    /* Analog part */
+    /* BBPLL CALIBRATION START */
+    regi2c_ctrl_ll_bbpll_calibration_start();
+    clk_ll_bbpll_set_config(pll_freq, xtal_freq);
+    /* WAIT CALIBRATION DONE */
+    while(!regi2c_ctrl_ll_bbpll_calibration_is_done());
+    /* BBPLL CALIBRATION STOP */
+    regi2c_ctrl_ll_bbpll_calibration_stop();
+
+    s_cur_pll_freq = pll_freq;
+}
+
+/**
+ * Switch to XTAL frequency. Does not disable the PLL.
+ */
+static void rtc_clk_cpu_freq_to_xtal(int freq, int div)
+{
+    // let f_cpu = f_ahb
+    clk_ll_cpu_set_divider(div);
+    clk_ll_ahb_set_divider(div);
+    clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_XTAL);
+    clk_ll_bus_update();
+    ets_update_cpu_frequency(freq);
+}
+
+static void rtc_clk_cpu_freq_to_8m(void)
+{
+    // let f_cpu = f_ahb
+    clk_ll_cpu_set_divider(1);
+    clk_ll_ahb_set_divider(1);
+    clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_RC_FAST);
+    clk_ll_bus_update();
+    ets_update_cpu_frequency(8);
+}
+
+/**
+ * Switch to one of PLL-based frequencies. Current frequency can be XTAL or PLL.
+ * PLL must already be enabled.
+ * @param cpu_freq new CPU frequency
+ */
+static void rtc_clk_cpu_freq_to_pll_mhz(int cpu_freq_mhz)
+{
+    // f_hp_root = 96MHz
+    uint32_t cpu_divider = CLK_LL_PLL_96M_FREQ_MHZ / cpu_freq_mhz;
+    clk_ll_cpu_set_divider(cpu_divider);
+    // Constraint: f_ahb <= 32MHz; f_cpu = N * f_ahb (N = 1, 2, 3...)
+    uint32_t ahb_divider = (cpu_divider == 1) ? 3 :
+                           (cpu_divider == 2) ? 4 : cpu_divider;
+    clk_ll_ahb_set_divider(ahb_divider);
+    clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_PLL);
+    clk_ll_bus_update();
+    ets_update_cpu_frequency(cpu_freq_mhz);
+}
+
+/**
+ * Switch to FLASH_PLL as cpu clock source.
+ * On ESP32H2, FLASH_PLL frequency is 64MHz.
+ * PLL must alreay be enabled.
+ */
+static void rtc_clk_cpu_freq_to_flash_pll(uint32_t cpu_freq_mhz, uint32_t cpu_divider)
+{
+    // f_hp_root = 64MHz
+    clk_ll_cpu_set_divider(cpu_divider);
+    // Constraint: f_ahb <= 32MHz; f_cpu = N * f_ahb (N = 1, 2, 3...)
+    uint32_t ahb_divider = (cpu_divider == 1) ? 2 : cpu_divider;
+    clk_ll_ahb_set_divider(ahb_divider);
+    clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_FLASH_PLL);
+    clk_ll_bus_update();
+    ets_update_cpu_frequency(cpu_freq_mhz);
+}
+
+bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *out_config)
+{
+    uint32_t source_freq_mhz;
+    soc_cpu_clk_src_t source;
+    uint32_t divider; // divider = freq of SOC_ROOT_CLK / freq of CPU_CLK
+    uint32_t real_freq_mhz;
+
+    uint32_t xtal_freq = (uint32_t)rtc_clk_xtal_freq_get();
+    if (freq_mhz <= xtal_freq && freq_mhz != 0) {
+        divider = xtal_freq / freq_mhz;
+        real_freq_mhz = (xtal_freq + divider / 2) / divider; /* round */
+        if (real_freq_mhz != freq_mhz) {
+            // no suitable divider
+            return false;
+        }
+
+        source_freq_mhz = xtal_freq;
+        source = SOC_CPU_CLK_SRC_XTAL;
+    } else if (freq_mhz == 96) {
+        real_freq_mhz = freq_mhz;
+        source = SOC_CPU_CLK_SRC_PLL;
+        source_freq_mhz = CLK_LL_PLL_96M_FREQ_MHZ;
+        divider = 1;
+    } else if (freq_mhz == 64) {
+        real_freq_mhz = freq_mhz;
+        source = SOC_CPU_CLK_SRC_FLASH_PLL;
+        source_freq_mhz = CLK_LL_PLL_64M_FREQ_MHZ;
+        divider = 1;
+    } else if (freq_mhz == 48) {
+        real_freq_mhz = freq_mhz;
+        source = SOC_CPU_CLK_SRC_PLL;
+        source_freq_mhz = CLK_LL_PLL_96M_FREQ_MHZ;
+        divider = 2;
+    } else {
+        // unsupported frequency
+        return false;
+    }
+    *out_config = (rtc_cpu_freq_config_t) {
+        .source = source,
+        .div = divider,
+        .source_freq_mhz = source_freq_mhz,
+        .freq_mhz = real_freq_mhz
+    };
+    return true;
+}
+
+void rtc_clk_cpu_freq_set_config(const rtc_cpu_freq_config_t *config)
+{
+    soc_cpu_clk_src_t old_cpu_clk_src = clk_ll_cpu_get_src();
+    if (config->source == SOC_CPU_CLK_SRC_XTAL) {
+        rtc_clk_cpu_freq_to_xtal(config->freq_mhz, config->div);
+        if ((old_cpu_clk_src == SOC_CPU_CLK_SRC_PLL || old_cpu_clk_src == SOC_CPU_CLK_SRC_FLASH_PLL) &&
+            !rtc_clk_set_bbpll_always_on()) {
+            rtc_clk_bbpll_disable();
+        }
+    } else if (config->source == SOC_CPU_CLK_SRC_PLL) {
+        if (old_cpu_clk_src != SOC_CPU_CLK_SRC_PLL && old_cpu_clk_src != SOC_CPU_CLK_SRC_FLASH_PLL) {
+            rtc_clk_bbpll_enable();
+            rtc_clk_bbpll_configure(rtc_clk_xtal_freq_get(), config->source_freq_mhz);
+        }
+        rtc_clk_cpu_freq_to_pll_mhz(config->freq_mhz);
+    } else if (config->source == SOC_CPU_CLK_SRC_RC_FAST) {
+        rtc_clk_cpu_freq_to_8m();
+        if ((old_cpu_clk_src == SOC_CPU_CLK_SRC_PLL || old_cpu_clk_src == SOC_CPU_CLK_SRC_FLASH_PLL) &&
+            !rtc_clk_set_bbpll_always_on()) {
+            rtc_clk_bbpll_disable();
+        }
+    } else if (config->source == SOC_CPU_CLK_SRC_FLASH_PLL) {
+        if (old_cpu_clk_src != SOC_CPU_CLK_SRC_PLL && old_cpu_clk_src != SOC_CPU_CLK_SRC_FLASH_PLL) {
+            // On ESP32H2, FLASH_PLL (64MHz) is directly derived from the BBPLL (96MHz)
+            // Therefore, enabling and configuration are applied to BBPLL.
+            rtc_clk_bbpll_enable();
+            rtc_clk_bbpll_configure(rtc_clk_xtal_freq_get(), CLK_LL_PLL_96M_FREQ_MHZ);
+        }
+        rtc_clk_cpu_freq_to_flash_pll(config->freq_mhz, config->div);
+    }
+}
+
+void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t *out_config)
+{
+    soc_cpu_clk_src_t source = clk_ll_cpu_get_src();
+    uint32_t source_freq_mhz;
+    uint32_t div = clk_ll_cpu_get_divider(); // div = freq of SOC_ROOT_CLK / freq of CPU_CLK
+    uint32_t freq_mhz;
+    switch (source) {
+    case SOC_CPU_CLK_SRC_XTAL: {
+        source_freq_mhz = (uint32_t)rtc_clk_xtal_freq_get();
+        freq_mhz = source_freq_mhz / div;
+        break;
+    }
+    case SOC_CPU_CLK_SRC_PLL: {
+        source_freq_mhz = clk_ll_bbpll_get_freq_mhz();
+        freq_mhz = source_freq_mhz / div;
+        break;
+    }
+    case SOC_CPU_CLK_SRC_RC_FAST:
+        source_freq_mhz = 8;
+        freq_mhz = source_freq_mhz / div;
+        break;
+    case SOC_CPU_CLK_SRC_FLASH_PLL:
+        source_freq_mhz = clk_ll_flash_pll_get_freq_mhz();
+        freq_mhz = source_freq_mhz / div;
+        break;
+    default:
+        ESP_HW_LOGE(TAG, "unsupported frequency configuration");
+        abort();
+    }
+    *out_config = (rtc_cpu_freq_config_t) {
+        .source = source,
+        .source_freq_mhz = source_freq_mhz,
+        .div = div,
+        .freq_mhz = freq_mhz
+    };
+}
+
+void rtc_clk_cpu_freq_set_config_fast(const rtc_cpu_freq_config_t *config)
+{
+    if (config->source == SOC_CPU_CLK_SRC_XTAL) {
+        rtc_clk_cpu_freq_to_xtal(config->freq_mhz, config->div);
+    } else if (config->source == SOC_CPU_CLK_SRC_PLL &&
+               s_cur_pll_freq == config->source_freq_mhz) {
+        rtc_clk_cpu_freq_to_pll_mhz(config->freq_mhz);
+    } else if (config->source == SOC_CPU_CLK_SRC_RC_FAST) {
+        rtc_clk_cpu_freq_to_8m();
+    } else if (config->source == SOC_CPU_CLK_SRC_FLASH_PLL &&
+               s_cur_pll_freq == clk_ll_bbpll_get_freq_mhz()) {
+        // On ESP32H2, FLASH_PLL (64MHz) is directly derived from the BBPLL (96MHz)
+        // Therefore, as long as bbpll was not disabled, no need to re-enable and re-configure parameters for the source clock
+        rtc_clk_cpu_freq_to_flash_pll(config->freq_mhz, config->div);
+    } else {
+        /* fallback */
+        rtc_clk_cpu_freq_set_config(config);
+    }
+}
+
 void rtc_clk_cpu_freq_set_xtal(void)
 {
-    // ESP32H2-TODO: IDF-6254
+    int freq_mhz = (int)rtc_clk_xtal_freq_get();
+
+    rtc_clk_cpu_freq_to_xtal(freq_mhz, 1);
+    // TODO: IDF-6243 MSPI clock source could also depend on bbpll, cpu restart should not disable bbpll
+    // We don't turn off the bbpll if some consumers only depends on bbpll
+    if (!rtc_clk_set_bbpll_always_on()) {
+        rtc_clk_bbpll_disable();
+    }
 }
 
 rtc_xtal_freq_t rtc_clk_xtal_freq_get(void)
 {
-    ESP_EARLY_LOGW(TAG, "rtc_clk_xtal_freq_get() has not benn implemented yet");
-    // ESP32H2-TODO: IDF-6254
-    return 32;
+    uint32_t xtal_freq_mhz = clk_ll_xtal_load_freq_mhz();
+    if (xtal_freq_mhz == 0) {
+        ESP_HW_LOGW(TAG, "invalid RTC_XTAL_FREQ_REG value, assume 32MHz");
+        return RTC_XTAL_FREQ_32M;
+    }
+    return (rtc_xtal_freq_t)xtal_freq_mhz;
 }
 
 void rtc_clk_xtal_freq_update(rtc_xtal_freq_t xtal_freq)
 {
-    // ESP32H2-TODO: IDF-6254
+    clk_ll_xtal_store_freq_mhz(xtal_freq);
 }
 
-void rtc_clk_apb_freq_update(uint32_t apb_freq)
+static uint32_t rtc_clk_ahb_freq_get(void)
 {
-    // ESP32H2-TODO: IDF-6254
+    soc_cpu_clk_src_t source = clk_ll_cpu_get_src();
+    uint32_t soc_root_freq_mhz;
+    uint32_t divider = clk_ll_ahb_get_divider();
+    switch (source) {
+    case SOC_CPU_CLK_SRC_XTAL:
+        soc_root_freq_mhz = rtc_clk_xtal_freq_get();
+        break;
+    case SOC_CPU_CLK_SRC_PLL:
+        soc_root_freq_mhz = clk_ll_bbpll_get_freq_mhz();
+        break;
+    case SOC_CPU_CLK_SRC_RC_FAST:
+        soc_root_freq_mhz = 8;
+        break;
+    case SOC_CPU_CLK_SRC_FLASH_PLL:
+        soc_root_freq_mhz = clk_ll_flash_pll_get_freq_mhz();
+        break;
+    default:
+        // Unknown SOC_ROOT clock source
+        soc_root_freq_mhz = 0;
+        ESP_HW_LOGE(TAG, "Invalid SOC_ROOT_CLK");
+        break;
+    }
+    return soc_root_freq_mhz / divider;
 }
 
 uint32_t rtc_clk_apb_freq_get(void)
 {
-    ESP_EARLY_LOGW(TAG, "rtc_clk_apb_freq_get() has not benn implemented yet");
-    // ESP32H2-TODO: IDF-6254
-    return 0;
+    return rtc_clk_ahb_freq_get() / clk_ll_apb_get_divider() * MHZ;
 }
 
 void rtc_dig_clk8m_enable(void)
@@ -80,3 +424,23 @@ void rtc_dig_clk8m_disable(void)
     clk_ll_rc_fast_digi_disable();
     esp_rom_delay_us(SOC_DELAY_RC_FAST_DIGI_SWITCH);
 }
+
+bool rtc_dig_8m_enabled(void)
+{
+    return clk_ll_rc_fast_digi_is_enabled();
+}
+
+static bool rtc_clk_set_bbpll_always_on(void)
+{
+    /* We just keep the rtc bbpll clock on just under the case that
+    user selects the `RTC_CLOCK_BBPLL_POWER_ON_WITH_USB` as well as
+    the USB_SERIAL_JTAG is connected with PC.
+    */
+    bool is_bbpll_on = false;
+#if CONFIG_RTC_CLOCK_BBPLL_POWER_ON_WITH_USB
+    if (usb_serial_jtag_ll_txfifo_writable() == 1) {
+        is_bbpll_on = true;
+    }
+#endif
+    return is_bbpll_on;
+}

components/esp_hw_support/port/esp32h2/rtc_clk_init.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -12,10 +12,11 @@
 #include "esp32h2/rom/rtc.h"
 #include "esp32h2/rom/uart.h"
 #include "soc/rtc.h"
-#include "soc/efuse_periph.h"
-#include "hal/regi2c_ctrl_ll.h"
-#include "esp_hw_log.h"
 #include "esp_cpu.h"
+#include "regi2c_ctrl.h"
+#include "soc/lp_clkrst_reg.h"
+#include "soc/regi2c_pmu.h"
+#include "esp_hw_log.h"
 #include "sdkconfig.h"
 #include "esp_rom_uart.h"
 
@@ -23,36 +24,24 @@ static const char *TAG = "rtc_clk_init";
 
 void rtc_clk_init(rtc_clk_config_t cfg)
 {
-    ESP_HW_LOGW(TAG, "rtc_clk_init() has not been implemented yet");
-#if 0 // ESP32H2-TODO
     rtc_cpu_freq_config_t old_config, new_config;
 
-    /* Set tuning parameters for 8M and 150k clocks.
+    /* Set tuning parameters for RC_FAST, RC_SLOW, and RC32K clocks.
      * Note: this doesn't attempt to set the clocks to precise frequencies.
      * Instead, we calibrate these clocks against XTAL frequency later, when necessary.
-     * - SCK_DCAP value controls tuning of 150k clock.
+     * - SCK_DCAP value controls tuning of RC_SLOW clock.
      *   The higher the value of DCAP is, the lower is the frequency.
-     * - CK8M_DFREQ value controls tuning of 8M clock.
+     * - CK8M_DFREQ value controls tuning of RC_FAST clock.
      *   CLK_8M_DFREQ constant gives the best temperature characteristics.
+     * - RC32K_DFREQ value controls tuning of RC32K clock.
      */
-    REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_SCK_DCAP, cfg.slow_clk_dcap);
-    REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DFREQ, cfg.clk_8m_dfreq);
-
-    /* Configure 150k clock division */
-    rtc_clk_divider_set(cfg.clk_rtc_clk_div);
-
-    /* Configure 8M clock division */
-    rtc_clk_8m_divider_set(cfg.clk_8m_clk_div);
-
-    /* Reset (disable) i2c internal bus for all regi2c registers */
-    regi2c_ctrl_ll_i2c_reset(); // TODO: This should be move out from rtc_clk_init
-    /* Enable the internal bus used to configure BBPLL */
-    regi2c_ctrl_ll_i2c_bbpll_enable(); // TODO: This should be moved to bbpll_set_config
+    REG_SET_FIELD(LP_CLKRST_FOSC_CNTL_REG, LP_CLKRST_FOSC_DFREQ, cfg.clk_8m_dfreq);
+    REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_OC_SCK_DCAP, cfg.slow_clk_dcap);
+    REG_SET_FIELD(LP_CLKRST_RC32K_CNTL_REG, LP_CLKRST_RC32K_DFREQ, cfg.rc32k_dfreq);
 
     rtc_xtal_freq_t xtal_freq = cfg.xtal_freq;
     esp_rom_uart_tx_wait_idle(0);
     rtc_clk_xtal_freq_update(xtal_freq);
-    rtc_clk_apb_freq_update(xtal_freq * MHZ);
 
     /* Set CPU frequency */
     rtc_clk_cpu_freq_get_config(&old_config);
@@ -71,14 +60,14 @@ void rtc_clk_init(rtc_clk_config_t cfg)
     // We will not power off RC_FAST in bootloader stage even if it is not being used as any
     // cpu / rtc_fast / rtc_slow clock sources, this is because RNG always needs it in the bootloader stage.
     bool need_rc_fast_en = true;
-    bool need_rc_fast_d256_en = false;
     if (cfg.slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
         rtc_clk_32k_enable(true);
-    } else if (cfg.slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256) {
-        need_rc_fast_d256_en = true;
+    } else if (cfg.slow_clk_src == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) {
+        rtc_clk_32k_enable_external();
+    } else if (cfg.slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC32K) {
+       rtc_clk_rc32k_enable(true);
     }
-    rtc_clk_8m_enable(need_rc_fast_en, need_rc_fast_d256_en);
+    rtc_clk_8m_enable(need_rc_fast_en);
     rtc_clk_fast_src_set(cfg.fast_clk_src);
     rtc_clk_slow_src_set(cfg.slow_clk_src);
-#endif
 }

components/esp_hw_support/port/esp32h2/rtc_time.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -7,9 +7,13 @@
 #include <stdint.h>
 #include "esp32h2/rom/ets_sys.h"
 #include "soc/rtc.h"
+#include "soc/lp_timer_reg.h"
 #include "hal/clk_tree_ll.h"
 #include "soc/timer_group_reg.h"
 #include "esp_rom_sys.h"
+#include "assert.h"
+
+static const char *TAG = "rtc_time";
 
 /* Calibration of RTC_SLOW_CLK is performed using a special feature of TIMG0.
  * This feature counts the number of XTAL clock cycles within a given number of
@@ -23,80 +27,216 @@
  * enabled using TIMG_RTC_CALI_START bit.
  */
 
-/**
- * @brief Clock calibration function used by rtc_clk_cal and rtc_clk_cal_ratio
- * @param cal_clk which clock to calibrate
- * @param slowclk_cycles number of slow clock cycles to count
- * @return number of XTAL clock cycles within the given number of slow clock cycles
+/* On ESP32H2, TIMG_RTC_CALI_CLK_SEL can config to 0, 1, 2, 3
+ * 0 or 3: calibrate RC_SLOW clock
+ * 1: calibrate RC_FAST clock
+ * 2: calibrate 32K clock, which 32k depends on reg_32k_sel: 0: Internal 32 kHz RC oscillator, 1: External 32 kHz XTAL, 2: External 32kHz clock input by gpio13
  */
-// ESP32H2-TODO
-static const char *TAG = "rtc_time";
+#define TIMG_RTC_CALI_CLK_SEL_RC_SLOW 0
+#define TIMG_RTC_CALI_CLK_SEL_RC_FAST 1
+#define TIMG_RTC_CALI_CLK_SEL_32K     2
 
 uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
 {
-    // ESP32H2-TODO
-    ESP_EARLY_LOGW(TAG, "rtc_clk_cal_internal() has not been implemented yet");
-    return 0;
+    assert(slowclk_cycles < TIMG_RTC_CALI_MAX_V);
+
+    uint32_t cali_clk_sel = 0;
+    soc_rtc_slow_clk_src_t slow_clk_src = rtc_clk_slow_src_get();
+    soc_rtc_slow_clk_src_t old_32k_cal_clk_sel = clk_ll_32k_calibration_get_target();
+    if (cal_clk == RTC_CAL_RTC_MUX) {
+        cal_clk = (rtc_cal_sel_t)slow_clk_src;
+    }
+    if (cal_clk == RTC_CAL_RC_FAST) {
+        cali_clk_sel = TIMG_RTC_CALI_CLK_SEL_RC_FAST;
+    } else if (cal_clk == RTC_CAL_RC_SLOW) {
+        cali_clk_sel = TIMG_RTC_CALI_CLK_SEL_RC_SLOW;
+    } else {
+        cali_clk_sel = TIMG_RTC_CALI_CLK_SEL_32K;
+        clk_ll_32k_calibration_set_target((soc_rtc_slow_clk_src_t)cal_clk);
+    }
+
+
+    /* Enable requested clock (150k clock is always on) */
+    // All clocks on/off takes time to be stable, so we shouldn't frequently enable/disable the clock
+    // Only enable if orignally was disabled, and set back to the disable state after calibration is done
+    // If the clock is already on, then do nothing
+    bool dig_32k_xtal_enabled = clk_ll_xtal32k_digi_is_enabled();
+    if (cal_clk == RTC_CAL_32K_XTAL && !dig_32k_xtal_enabled) {
+            clk_ll_xtal32k_digi_enable();
+    }
+
+    bool rc_fast_enabled = clk_ll_rc_fast_is_enabled();
+    bool dig_rc_fast_enabled = clk_ll_rc_fast_digi_is_enabled();
+    if (cal_clk == RTC_CAL_RC_FAST) {
+        if (!rc_fast_enabled) {
+            rtc_clk_8m_enable(true);
+        }
+        if (!dig_rc_fast_enabled) {
+            rtc_dig_clk8m_enable();
+        }
+    }
+
+    bool rc32k_enabled = clk_ll_rc32k_is_enabled();
+    bool dig_rc32k_enabled = clk_ll_rc32k_digi_is_enabled();
+    if (cal_clk == RTC_CAL_RC32K) {
+        if (!rc32k_enabled) {
+            rtc_clk_rc32k_enable(true);
+        }
+        if (!dig_rc32k_enabled) {
+            clk_ll_rc32k_digi_enable();
+        }
+    }
+
+    /* There may be another calibration process already running during we call this function,
+     * so we should wait the last process is done.
+     */
+    if (GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING)) {
+        /**
+         * Set a small timeout threshold to accelerate the generation of timeout.
+         * The internal circuit will be reset when the timeout occurs and will not affect the next calibration.
+         */
+        REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, 1);
+        while (!GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY)
+               && !GET_PERI_REG_MASK(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT));
+    }
+
+    /* Prepare calibration */
+    REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_CLK_SEL, cali_clk_sel);
+    CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING);
+    REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_MAX, slowclk_cycles);
+    /* Figure out how long to wait for calibration to finish */
+
+    /* Set timeout reg and expect time delay*/
+    uint32_t expected_freq;
+    if (cali_clk_sel == TIMG_RTC_CALI_CLK_SEL_32K) {
+        REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_32K_CAL_TIMEOUT_THRES(slowclk_cycles));
+        expected_freq = SOC_CLK_XTAL32K_FREQ_APPROX;
+    } else if (cali_clk_sel == TIMG_RTC_CALI_CLK_SEL_RC_FAST) {
+        REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_FAST_CLK_8M_CAL_TIMEOUT_THRES(slowclk_cycles));
+        expected_freq = SOC_CLK_RC_FAST_FREQ_APPROX;
+    } else {
+        REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, RTC_SLOW_CLK_150K_CAL_TIMEOUT_THRES(slowclk_cycles));
+        expected_freq = SOC_CLK_RC_SLOW_FREQ_APPROX;
+    }
+    uint32_t us_time_estimate = (uint32_t) (((uint64_t) slowclk_cycles) * MHZ / expected_freq);
+    /* Start calibration */
+    CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START);
+    SET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START);
+
+    /* Wait for calibration to finish up to another us_time_estimate */
+    esp_rom_delay_us(us_time_estimate);
+    uint32_t cal_val;
+    while (true) {
+        if (GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY)) {
+            cal_val = REG_GET_FIELD(TIMG_RTCCALICFG1_REG(0), TIMG_RTC_CALI_VALUE);
+            break;
+        }
+        if (GET_PERI_REG_MASK(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT)) {
+            cal_val = 0;
+            break;
+        }
+    }
+    CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START);
+
+    /* if dig_32k_xtal was originally off and enabled due to calibration, then set back to off state */
+    if (cal_clk == RTC_CAL_32K_XTAL && !dig_32k_xtal_enabled) {
+        clk_ll_xtal32k_digi_disable();
+    }
+
+    if (cal_clk == RTC_CAL_RC_FAST) {
+        if (!dig_rc_fast_enabled) {
+            rtc_dig_clk8m_disable();
+        }
+        if (!rc_fast_enabled) {
+            rtc_clk_8m_enable(false);
+        }
+    }
+
+    if (cal_clk == RTC_CAL_RC32K) {
+        if (!dig_rc32k_enabled) {
+            clk_ll_rc32k_digi_disable();
+        }
+        if (!rc32k_enabled) {
+            rtc_clk_rc32k_enable(false);
+        }
+    }
+
+    // Always set back the calibration 32kHz clock selection
+    if (old_32k_cal_clk_sel != SOC_RTC_SLOW_CLK_SRC_INVALID) {
+        clk_ll_32k_calibration_set_target(old_32k_cal_clk_sel);
+    }
+
+    return cal_val;
 }
 
-uint32_t rtc_clk_cal_ratio(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
+static bool rtc_clk_cal_32k_valid(rtc_xtal_freq_t xtal_freq, uint32_t slowclk_cycles, uint64_t actual_xtal_cycles)
 {
-    // ESP32H2-TODO
-    ESP_EARLY_LOGW(TAG, "rtc_clk_cal_ratio() has not been implemented yet");
-    return 0;
+    uint64_t expected_xtal_cycles = (xtal_freq * 1000000ULL * slowclk_cycles) >> 15; // xtal_freq(hz) * slowclk_cycles / 32768
+    uint64_t delta = expected_xtal_cycles / 2000;                                    // 5/10000 = 0.05% error range
+    return (actual_xtal_cycles >= (expected_xtal_cycles - delta)) && (actual_xtal_cycles <= (expected_xtal_cycles + delta));
 }
 
 uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
 {
-    // ESP32H2-TODO
-    ESP_EARLY_LOGW(TAG, "rtc_clk_cal() has not been implemented yet");
-    return 0;
+    rtc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get();
+    uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk, slowclk_cycles);
+
+    if (cal_clk == RTC_CAL_32K_XTAL && !rtc_clk_cal_32k_valid(xtal_freq, slowclk_cycles, xtal_cycles)) {
+        return 0;
+    }
+
+    uint64_t divider = ((uint64_t)xtal_freq) * slowclk_cycles;
+    uint64_t period_64 = ((xtal_cycles << RTC_CLK_CAL_FRACT) + divider / 2 - 1) / divider;
+    uint32_t period = (uint32_t)(period_64 & UINT32_MAX);
+    return period;
 }
 
 uint64_t rtc_time_us_to_slowclk(uint64_t time_in_us, uint32_t period)
 {
-    // ESP32H2-TODO
-    ESP_EARLY_LOGW(TAG, "rtc_time_us_to_slowclk() has not been implemented yet");
-    return 0;
+    /* Overflow will happen in this function if time_in_us >= 2^45, which is about 400 days.
+     * TODO: fix overflow.
+     */
+    return (time_in_us << RTC_CLK_CAL_FRACT) / period;
 }
 
 uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period)
 {
-    // ESP32H2-TODO
-    ESP_EARLY_LOGW(TAG, "rtc_time_slowclk_to_us() has not been implemented yet");
-    return 0;
+    return (rtc_cycles * period) >> RTC_CLK_CAL_FRACT;
 }
 
 uint64_t rtc_time_get(void)
 {
-    // ESP32H2-TODO
-    ESP_EARLY_LOGW(TAG, "rtc_time_get() has not been implemented yet");
-    return 0;
+    SET_PERI_REG_MASK(LP_TIMER_UPDATE_REG, LP_TIMER_MAIN_TIMER_UPDATE);
+    uint64_t t = READ_PERI_REG(LP_TIMER_MAIN_BUF0_LOW_REG);
+    t |= ((uint64_t) READ_PERI_REG(LP_TIMER_MAIN_BUF0_HIGH_REG)) << 32;
+    return t;
 }
 
 uint64_t rtc_light_slp_time_get(void)
 {
-    // ESP32H2-TODO
+    // TODO: IDF-6267
     ESP_EARLY_LOGW(TAG, "rtc_light_slp_time_get() has not been implemented yet");
     return 0;
 }
 
 uint64_t rtc_deep_slp_time_get(void)
 {
-    // ESP32H2-TODO
-    ESP_EARLY_LOGW(TAG, "rtc_deep_slp_time_get() has not been implemented yet");
-    return 0;
+    uint64_t t_slp = READ_PERI_REG(LP_TIMER_MAIN_BUF1_LOW_REG);
+    t_slp |= ((uint64_t) READ_PERI_REG(LP_TIMER_MAIN_BUF1_HIGH_REG)) << 32;
+    uint64_t t_wake = rtc_time_get();
+    return (t_wake - t_slp);
 }
 
 void rtc_clk_wait_for_slow_cycle(void) //This function may not by useful any more
 {
-    // ESP32H2-TODO
+    // TODO: IDF-6254
     ESP_EARLY_LOGW(TAG, "rtc_clk_wait_for_slow_cycle() has not been implemented yet");
 }
 
 uint32_t rtc_clk_freq_cal(uint32_t cal_val)
 {
-    // ESP32H2-TODO
-    ESP_EARLY_LOGW(TAG, "rtc_clk_freq_cal() has not been implemented yet");
-    return 0;
+    if (cal_val == 0) {
+        return 0;   // cal_val will be denominator, return 0 as the symbol of failure.
+    }
+    return 1000000ULL * (1 << RTC_CLK_CAL_FRACT) / cal_val;
 }

components/esp_rom/esp32h2/ld/esp32h2.rom.api.ld

@@ -55,8 +55,3 @@ PROVIDE ( esp_rom_spiflash_fix_dummylen = spi_dummy_len_fix );
 PROVIDE ( esp_rom_spiflash_set_drvs = SetSpiDrvs);
 PROVIDE ( esp_rom_spiflash_select_padsfunc = SelectSpiFunction );
 PROVIDE ( esp_rom_spiflash_common_cmd = SPI_Common_Command );
-
-PROVIDE ( esp_rom_regi2c_read = rom_i2c_readReg );
-PROVIDE ( esp_rom_regi2c_read_mask = rom_i2c_readReg_Mask );
-PROVIDE ( esp_rom_regi2c_write = rom_i2c_writeReg );
-PROVIDE ( esp_rom_regi2c_write_mask = rom_i2c_writeReg_Mask );

components/esp_rom/patches/esp_rom_regi2c_esp32h2.c

@@ -23,7 +23,7 @@
 #define REGI2C_SAR_I2C_DEVICE_EN  (BIT(7) << 4)
 #define REGI2C_BBPLL_DEVICE_EN    (BIT(5) << 4)
 #define REGI2C_BIAS_DEVICE_EN     (BIT(4) << 4)
-#define REGI2C_DIG_REG_DEVICE_EN  (BIT(8) << 4)
+#define REGI2C_PMU_DEVICE_EN      (BIT(8) << 4)
 
 #define REGI2C_RTC_BUSY           (BIT(25))
 #define REGI2C_RTC_BUSY_M         (BIT(25))
@@ -58,8 +58,8 @@
 #define REGI2C_BIAS               (0x6a)
 #define REGI2C_BIAS_HOSTID        0
 
-#define REGI2C_DIG_REG            (0x6d)
-#define REGI2C_DIG_REG_HOSTID     0
+#define REGI2C_PMU                (0x6d)
+#define REGI2C_PMU_HOSTID         0
 
 #define REGI2C_ULP_CAL            (0x61)
 #define REGI2C_ULP_CAL_HOSTID     0
@@ -82,8 +82,8 @@ static IRAM_ATTR void regi2c_enable_block(uint8_t block)
     case REGI2C_BIAS   :
         REG_SET_BIT(I2C_MST_ANA_CONF2_REG, REGI2C_BIAS_DEVICE_EN);
         break;
-    case REGI2C_DIG_REG:
-        REG_SET_BIT(I2C_MST_ANA_CONF2_REG, REGI2C_DIG_REG_DEVICE_EN);
+    case REGI2C_PMU    :
+        REG_SET_BIT(I2C_MST_ANA_CONF2_REG, REGI2C_PMU_DEVICE_EN);
         break;
     case REGI2C_ULP_CAL:
         REG_SET_BIT(I2C_MST_ANA_CONF2_REG, REGI2C_ULP_CAL_DEVICE_EN);
@@ -105,8 +105,8 @@ static IRAM_ATTR void regi2c_disable_block(uint8_t block)
     case REGI2C_BIAS   :
         REG_SET_BIT(I2C_MST_ANA_CONF2_REG, REGI2C_BIAS_DEVICE_EN);
         break;
-    case REGI2C_DIG_REG:
-        REG_SET_BIT(I2C_MST_ANA_CONF2_REG, REGI2C_DIG_REG_DEVICE_EN);
+    case REGI2C_PMU:
+        REG_SET_BIT(I2C_MST_ANA_CONF2_REG, REGI2C_PMU_DEVICE_EN);
         break;
     case REGI2C_ULP_CAL:
         REG_SET_BIT(I2C_MST_ANA_CONF2_REG, REGI2C_ULP_CAL_DEVICE_EN);

components/esp_system/port/soc/esp32h2/Kconfig.cpu

@@ -7,13 +7,15 @@ choice ESP_DEFAULT_CPU_FREQ_MHZ
 
     config ESP_DEFAULT_CPU_FREQ_MHZ_16
         bool "16 MHz"
-        depends on IDF_ENV_FPGA     #ESP32H2-TODO: IDF-3786
+        depends on IDF_ENV_FPGA
     config ESP_DEFAULT_CPU_FREQ_MHZ_32
         bool "32 MHz"
-        depends on IDF_ENV_FPGA     #ESP32H2-TODO: IDF-3786
+        depends on IDF_ENV_FPGA
+    config ESP_DEFAULT_CPU_FREQ_MHZ_48
+        bool "48 MHz"
+        depends on !IDF_ENV_FPGA
     config ESP_DEFAULT_CPU_FREQ_MHZ_64
         bool "64 MHz"
-        depends on IDF_ENV_FPGA     #ESP32H2-TODO: IDF-3786
     config ESP_DEFAULT_CPU_FREQ_MHZ_96
         bool "96 MHz"
         depends on !IDF_ENV_FPGA
@@ -23,5 +25,6 @@ config ESP_DEFAULT_CPU_FREQ_MHZ
     int
     default 16 if ESP_DEFAULT_CPU_FREQ_MHZ_16
     default 32 if ESP_DEFAULT_CPU_FREQ_MHZ_32
+    default 48 if ESP_DEFAULT_CPU_FREQ_MHZ_48
     default 64 if ESP_DEFAULT_CPU_FREQ_MHZ_64
     default 96 if ESP_DEFAULT_CPU_FREQ_MHZ_96

components/esp_system/port/soc/esp32h2/clk.c

@@ -22,7 +22,7 @@
 #include "hal/wdt_hal.h"
 #include "esp_private/periph_ctrl.h"
 #include "esp_private/esp_clk.h"
-#include "bootloader_clock.h"
+#include "esp_private/esp_pmu.h"
 #include "esp_rom_uart.h"
 #include "esp_rom_sys.h"
 
@@ -42,22 +42,11 @@ static const char *TAG = "clk";
  __attribute__((weak)) void esp_clk_init(void)
 {
 #if !CONFIG_IDF_ENV_FPGA
-    rtc_config_t cfg = RTC_CONFIG_DEFAULT();
-    soc_reset_reason_t rst_reas;
-    rst_reas = esp_rom_get_reset_reason(0);
-    if (rst_reas == RESET_REASON_CHIP_POWER_ON
-#if SOC_EFUSE_HAS_EFUSE_RST_BUG
-        || rst_reas == RESET_REASON_CORE_EFUSE_CRC
-#endif
-        ) {
-        cfg.cali_ocode = 1;
-    }
-    rtc_init(cfg);
+    pmu_init();
 
-    assert(rtc_clk_xtal_freq_get() == RTC_XTAL_FREQ_40M);
+    assert(rtc_clk_xtal_freq_get() == RTC_XTAL_FREQ_32M);
 
-    bool rc_fast_d256_is_enabled = rtc_clk_8md256_enabled();
-    rtc_clk_8m_enable(true, rc_fast_d256_is_enabled);
+    rtc_clk_8m_enable(true);
     rtc_clk_fast_src_set(SOC_RTC_FAST_CLK_SRC_RC_FAST);
 #endif
 
@@ -119,9 +108,6 @@ static const char *TAG = "clk";
 
 static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src)
 {
-    ESP_EARLY_LOGW(TAG, "select_rtc_slow_clk() has not been implemented yet");
-#if 0// ESP32H2-TODO : IDF-5645
-    soc_rtc_slow_clk_src_t rtc_slow_clk_src = slow_clk & RTC_CNTL_ANA_CLK_RTC_SEL_V;
     uint32_t cal_val = 0;
     /* number of times to repeat 32k XTAL calibration
      * before giving up and switching to the internal RC
@@ -129,7 +115,7 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src)
     int retry_32k_xtal = 3;
 
     do {
-        if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
+        if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K || rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) {
             /* 32k XTAL oscillator needs to be enabled and running before it can
              * be used. Hardware doesn't have a direct way of checking if the
              * oscillator is running. Here we use rtc_clk_cal function to count
@@ -138,24 +124,27 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src)
              * will time out, returning 0.
              */
             ESP_EARLY_LOGD(TAG, "waiting for 32k oscillator to start up");
-            if (slow_clk == SLOW_CLK_32K_XTAL) {
+            rtc_cal_sel_t cal_sel = 0;
+            if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
                 rtc_clk_32k_enable(true);
-            } else if (slow_clk == SLOW_CLK_32K_EXT_OSC) {
+                cal_sel = RTC_CAL_32K_XTAL;
+            } else if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) {
                 rtc_clk_32k_enable_external();
+                cal_sel = RTC_CAL_32K_OSC_SLOW;
             }
             // When SLOW_CLK_CAL_CYCLES is set to 0, clock calibration will not be performed at startup.
             if (SLOW_CLK_CAL_CYCLES > 0) {
-                cal_val = rtc_clk_cal(RTC_CAL_32K_XTAL, SLOW_CLK_CAL_CYCLES);
-                if (cal_val == 0 || cal_val < MIN_32K_XTAL_CAL_VAL) {
+                cal_val = rtc_clk_cal(cal_sel, SLOW_CLK_CAL_CYCLES);
+                if (cal_val == 0) {
                     if (retry_32k_xtal-- > 0) {
                         continue;
                     }
-                    ESP_EARLY_LOGW(TAG, "32 kHz XTAL not found, switching to internal 150 kHz oscillator");
+                    ESP_EARLY_LOGW(TAG, "32 kHz clock not found, switching to internal 150 kHz oscillator");
                     rtc_slow_clk_src = SOC_RTC_SLOW_CLK_SRC_RC_SLOW;
                 }
             }
-        } else if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256) {
-            rtc_clk_8m_enable(true, true);
+        } else if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC32K) {
+            rtc_clk_rc32k_enable(true);
         }
         rtc_clk_slow_src_set(rtc_slow_clk_src);
 
@@ -171,7 +160,6 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src)
     } while (cal_val == 0);
     ESP_EARLY_LOGD(TAG, "RTC_SLOW_CLK calibration value: %d", cal_val);
     esp_clk_slowclk_cal_set(cal_val);
-#endif
 }
 
 void rtc_clk_select_rtc_slow_clk(void)

components/esp_system/port/soc/esp32h2/reset_reason.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -18,9 +18,6 @@ static esp_reset_reason_t get_reset_reason(soc_reset_reason_t rtc_reset_reason,
 {
     switch (rtc_reset_reason) {
     case RESET_REASON_CHIP_POWER_ON:
-#if SOC_EFUSE_HAS_EFUSE_RST_BUG
-    case RESET_REASON_CORE_EFUSE_CRC:
-#endif
         return ESP_RST_POWERON;
 
     case RESET_REASON_CPU0_SW:

components/hal/CMakeLists.txt

@@ -239,7 +239,7 @@ if(NOT BOOTLOADER_BUILD)
                 "adc_oneshot_hal.c" # TODO: IDF-6214
                 "adc_hal_common.c" # TODO: IDF-6215
                 "esp32h2/rtc_cntl_hal.c"
-                "esp32h2/clk_tree_hal.c"
+                "esp32h2/pmu_hal.c" # TODO: IDF-6267
                 )
     endif()
 endif()

components/hal/esp32c6/include/hal/clk_tree_ll.h

@@ -18,6 +18,7 @@
 #include "hal/assert.h"
 #include "hal/log.h"
 #include "esp32c6/rom/rtc.h"
+#include "hal/misc.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -65,7 +66,7 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_enable(void)
 {
     SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_HIGH_XPD_BB_I2C |
                       PMU_TIE_HIGH_XPD_BBPLL | PMU_TIE_HIGH_XPD_BBPLL_I2C);
-    SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_HIGH_GLOBAL_BBPLL_ICG) ;
+    SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_HIGH_GLOBAL_BBPLL_ICG);
 }
 
 /**
@@ -372,7 +373,7 @@ static inline __attribute__((always_inline)) void clk_ll_cpu_set_hs_divider(uint
     // HS divider option: 1, 2, 4 (PCR_CPU_HS_DIV_NUM=0, 1, 3)
 
     HAL_ASSERT(divider == 3 || divider == 4 || divider == 6 || divider == 12);
-    PCR.cpu_freq_conf.cpu_hs_div_num = (divider / 3) - 1;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.cpu_freq_conf, cpu_hs_div_num, (divider / 3) - 1);
 
     // 120MHz CPU freq cannot be achieved through divider, need to set force_120m
     // This field is only valid if PCR_CPU_HS_DIV_NUM=0 and PCR_SOC_CLK_SEL=SOC_CPU_CLK_SRC_PLL
@@ -394,7 +395,7 @@ static inline __attribute__((always_inline)) void clk_ll_cpu_set_ls_divider(uint
     // (2) configurable
     // LS divider option: 1, 2, 4, 8, 16, 32 (PCR_CPU_LS_DIV_NUM=0, 1, 3, 7, 15, 31)
     HAL_ASSERT((divider > 0) && ((divider & (divider - 1)) == 0));
-    PCR.cpu_freq_conf.cpu_ls_div_num = divider - 1;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.cpu_freq_conf, cpu_ls_div_num, divider - 1);
 }
 
 /**
@@ -405,11 +406,12 @@ static inline __attribute__((always_inline)) void clk_ll_cpu_set_ls_divider(uint
 static inline __attribute__((always_inline)) uint32_t clk_ll_cpu_get_hs_divider(void)
 {
     uint32_t force_120m = PCR.cpu_freq_conf.cpu_hs_120m_force;
-    uint32_t cpu_hs_div = PCR.cpu_freq_conf.cpu_hs_div_num;
+    uint32_t cpu_hs_div = HAL_FORCE_READ_U32_REG_FIELD(PCR.cpu_freq_conf, cpu_hs_div_num);
     if (cpu_hs_div == 0 && force_120m) {
         return 4;
     }
-    return (PCR.sysclk_conf.hs_div_num + 1) * (cpu_hs_div + 1);
+    uint32_t hp_root_hs_div = HAL_FORCE_READ_U32_REG_FIELD(PCR.sysclk_conf, hs_div_num);
+    return (hp_root_hs_div + 1) * (cpu_hs_div + 1);
 }
 
 /**
@@ -419,7 +421,9 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_cpu_get_hs_divider(
  */
 static inline __attribute__((always_inline)) uint32_t clk_ll_cpu_get_ls_divider(void)
 {
-    return (PCR.sysclk_conf.ls_div_num + 1) * (PCR.cpu_freq_conf.cpu_ls_div_num + 1);
+    uint32_t cpu_ls_div = HAL_FORCE_READ_U32_REG_FIELD(PCR.cpu_freq_conf, cpu_ls_div_num);
+    uint32_t hp_root_ls_div = HAL_FORCE_READ_U32_REG_FIELD(PCR.sysclk_conf, ls_div_num);
+    return (hp_root_ls_div + 1) * (cpu_ls_div + 1);
 }
 
 /**
@@ -436,7 +440,7 @@ static inline __attribute__((always_inline)) void clk_ll_ahb_set_hs_divider(uint
     // (2) configurable
     // HS divider option: 4, 8, 16 (PCR_AHB_HS_DIV_NUM=3, 7, 15)
     HAL_ASSERT(divider == 12 || divider == 24 || divider == 48);
-    PCR.ahb_freq_conf.ahb_hs_div_num = (divider / 3) - 1;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.ahb_freq_conf, ahb_hs_div_num, (divider / 3) - 1);
 }
 
 /**
@@ -453,7 +457,7 @@ static inline __attribute__((always_inline)) void clk_ll_ahb_set_ls_divider(uint
     // (2) configurable
     // LS divider option: 1, 2, 4, 8, 16, 32 (PCR_CPU_LS_DIV_NUM=0, 1, 3, 7, 15, 31)
     HAL_ASSERT((divider > 0) && ((divider & (divider - 1)) == 0));
-    PCR.ahb_freq_conf.ahb_ls_div_num = divider - 1;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.ahb_freq_conf, ahb_ls_div_num, divider - 1);
 }
 
 /**
@@ -463,7 +467,9 @@ static inline __attribute__((always_inline)) void clk_ll_ahb_set_ls_divider(uint
  */
 static inline __attribute__((always_inline)) uint32_t clk_ll_ahb_get_hs_divider(void)
 {
-    return (PCR.sysclk_conf.hs_div_num + 1) * (PCR.ahb_freq_conf.ahb_hs_div_num + 1);
+    uint32_t ahb_hs_div = HAL_FORCE_READ_U32_REG_FIELD(PCR.ahb_freq_conf, ahb_hs_div_num);
+    uint32_t hp_root_hs_div = HAL_FORCE_READ_U32_REG_FIELD(PCR.sysclk_conf, hs_div_num);
+    return (hp_root_hs_div + 1) * (ahb_hs_div + 1);
 }
 
 /**
@@ -473,7 +479,9 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_ahb_get_hs_divider(
  */
 static inline __attribute__((always_inline)) uint32_t clk_ll_ahb_get_ls_divider(void)
 {
-    return (PCR.sysclk_conf.ls_div_num + 1) * (PCR.ahb_freq_conf.ahb_ls_div_num + 1);
+    uint32_t ahb_ls_div = HAL_FORCE_READ_U32_REG_FIELD(PCR.ahb_freq_conf, ahb_ls_div_num);
+    uint32_t hp_root_ls_div = HAL_FORCE_READ_U32_REG_FIELD(PCR.sysclk_conf, ls_div_num);
+    return (hp_root_ls_div + 1) * (ahb_ls_div + 1);
 }
 
 /**
@@ -486,7 +494,7 @@ static inline __attribute__((always_inline)) void clk_ll_apb_set_divider(uint32_
     // AHB ------> APB
     // Divider option: 1, 2, 4 (PCR_APB_DIV_NUM=0, 1, 3)
     HAL_ASSERT(divider == 1 || divider == 2 || divider == 4);
-    PCR.apb_freq_conf.apb_div_num = divider - 1;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.apb_freq_conf, apb_div_num, divider - 1);
 }
 
 /**
@@ -496,7 +504,7 @@ static inline __attribute__((always_inline)) void clk_ll_apb_set_divider(uint32_
  */
 static inline __attribute__((always_inline)) uint32_t clk_ll_apb_get_divider(void)
 {
-    return PCR.apb_freq_conf.apb_div_num + 1;
+    return HAL_FORCE_READ_U32_REG_FIELD(PCR.apb_freq_conf, apb_div_num) + 1;
 }
 
 /**
@@ -508,20 +516,22 @@ static inline __attribute__((always_inline)) void clk_ll_mspi_fast_set_hs_divide
 {
     // SOC_ROOT_CLK ------> MSPI_FAST_CLK
     // HS divider option: 4, 5, 6 (PCR_MSPI_FAST_HS_DIV_NUM=3, 4, 5)
+    uint32_t div_num = 0;
     switch (divider) {
     case 4:
-        PCR.mspi_clk_conf.mspi_fast_hs_div_num = 3;
+       div_num = 3;
         break;
     case 5:
-        PCR.mspi_clk_conf.mspi_fast_hs_div_num = 4;
+        div_num = 4;
         break;
     case 6:
-        PCR.mspi_clk_conf.mspi_fast_hs_div_num = 5;
+        div_num = 5;
         break;
     default:
         // Unsupported HS MSPI_FAST divider
         abort();
     }
+    HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.mspi_clk_conf, mspi_fast_hs_div_num, div_num);
 }
 
 /**
@@ -533,20 +543,22 @@ static inline __attribute__((always_inline)) void clk_ll_mspi_fast_set_ls_divide
 {
     // SOC_ROOT_CLK ------> MSPI_FAST_CLK
     // LS divider option: 1, 2, 4 (PCR_MSPI_FAST_LS_DIV_NUM=0, 1, 2)
+    uint32_t div_num = 0;
     switch (divider) {
     case 1:
-        PCR.mspi_clk_conf.mspi_fast_ls_div_num = 0;
+        div_num = 0;
         break;
     case 2:
-        PCR.mspi_clk_conf.mspi_fast_ls_div_num = 1;
+        div_num = 1;
         break;
     case 4:
-        PCR.mspi_clk_conf.mspi_fast_ls_div_num = 2;
+        div_num = 2;
         break;
     default:
         // Unsupported LS MSPI_FAST divider
         abort();
     }
+    HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.mspi_clk_conf, mspi_fast_ls_div_num, div_num);
 }
 
 /**
@@ -711,7 +723,7 @@ static inline void clk_ll_rc_slow_set_divider(uint32_t divider)
     HAL_ASSERT(divider == 1);
 }
 
-/************************* RTC STORAGE REGISTER STORE/LOAD **************************/
+/************************** LP STORAGE REGISTER STORE/LOAD **************************/
 /**
  * @brief Store XTAL_CLK frequency in RTC storage register
  *

components/hal/esp32c6/include/hal/regi2c_ctrl_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -14,22 +14,6 @@
 extern "C" {
 #endif
 
-// /**
-//  * @brief Reset (Disable) the I2C internal bus for all regi2c registers
-//  */
-// static inline void regi2c_ctrl_ll_i2c_reset(void)
-// {
-//     SET_PERI_REG_BITS(ANA_CONFIG_REG, ANA_CONFIG_M, ANA_CONFIG_M, ANA_CONFIG_S);
-// }
-
-// /**
-//  * @brief Enable the I2C internal bus to do I2C read/write operation to the BBPLL configuration register
-//  */
-// static inline void regi2c_ctrl_ll_i2c_bbpll_enable(void)
-// {
-//     CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, ANA_I2C_BBPLL_M);
-// }
-
 /**
  * @brief Start BBPLL self-calibration
  */

components/hal/esp32h2/clk_tree_hal.c

@@ -21,6 +21,8 @@ uint32_t clk_hal_soc_root_get_freq_mhz(soc_cpu_clk_src_t cpu_clk_src)
         return clk_ll_bbpll_get_freq_mhz();
     case SOC_CPU_CLK_SRC_RC_FAST:
         return SOC_CLK_RC_FAST_FREQ_APPROX / MHZ;
+    case SOC_CPU_CLK_SRC_FLASH_PLL:
+        return clk_ll_flash_pll_get_freq_mhz();
     default:
         // Unknown CPU_CLK mux input
         HAL_ASSERT(false);

components/hal/esp32h2/include/hal/clk_tree_ll.h

@@ -10,13 +10,16 @@
 #include "soc/soc.h"
 #include "soc/clk_tree_defs.h"
 #include "soc/rtc.h"
-#include "soc/pcr_reg.h"
+#include "soc/pcr_struct.h"
 #include "soc/lp_clkrst_struct.h"
+#include "soc/pmu_reg.h"
 #include "hal/regi2c_ctrl.h"
 #include "soc/regi2c_bbpll.h"
+#include "soc/regi2c_pmu.h"
 #include "hal/assert.h"
 #include "hal/log.h"
 #include "esp32h2/rom/rtc.h"
+#include "hal/misc.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -24,11 +27,10 @@ extern "C" {
 
 #define MHZ                 (1000000)
 
-#define CLK_LL_PLL_80M_FREQ_MHZ    (80)
-#define CLK_LL_PLL_160M_FREQ_MHZ   (160)
-
-#define CLK_LL_PLL_320M_FREQ_MHZ   (320)
-#define CLK_LL_PLL_480M_FREQ_MHZ   (480)
+#define CLK_LL_PLL_8M_FREQ_MHZ    (8)
+#define CLK_LL_PLL_48M_FREQ_MHZ   (48)
+#define CLK_LL_PLL_64M_FREQ_MHZ   (64)
+#define CLK_LL_PLL_96M_FREQ_MHZ   (96)
 
 #define CLK_LL_XTAL32K_CONFIG_DEFAULT() { \
     .dac = 3, \
@@ -61,7 +63,9 @@ typedef struct {
  */
 static inline __attribute__((always_inline)) void clk_ll_bbpll_enable(void)
 {
-    // ESP32H2-TODO: IDF-6401
+    SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_HIGH_XPD_BB_I2C |
+                      PMU_TIE_HIGH_XPD_BBPLL | PMU_TIE_HIGH_XPD_BBPLL_I2C);
+    SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_HIGH_GLOBAL_BBPLL_ICG);
 }
 
 /**
@@ -69,7 +73,26 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_enable(void)
  */
 static inline __attribute__((always_inline)) void clk_ll_bbpll_disable(void)
 {
-    // ESP32H2-TODO: IDF-6401
+    SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_LOW_GLOBAL_BBPLL_ICG) ;
+    SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_LOW_XPD_BBPLL | PMU_TIE_LOW_XPD_BBPLL_I2C);
+}
+
+/**
+ * @brief Enable the internal oscillator output for LP_PLL_CLK
+ */
+static inline void clk_ll_lp_pll_enable(void)
+{
+    // Enable lp_pll xpd status
+    SET_PERI_REG_MASK(PMU_HP_SLEEP_LP_CK_POWER_REG, PMU_HP_SLEEP_XPD_LPPLL);
+}
+
+/**
+ * @brief Disable the internal oscillator output for LP_PLL_CLK
+ */
+static inline void clk_ll_lp_pll_disable(void)
+{
+    // Disable lp_pll xpd status
+    CLEAR_PERI_REG_MASK(PMU_HP_SLEEP_LP_CK_POWER_REG, PMU_HP_SLEEP_XPD_LPPLL);
 }
 
 /**
@@ -79,7 +102,18 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_disable(void)
  */
 static inline void clk_ll_xtal32k_enable(clk_ll_xtal32k_enable_mode_t mode)
 {
-    // ESP32H2-TODO: IDF-6401
+    if (mode == CLK_LL_XTAL32K_ENABLE_MODE_EXTERNAL) {
+        // No need to configure anything for OSC_SLOW_CLK
+        return;
+    }
+    // Configure xtal32k
+    clk_ll_xtal32k_config_t cfg = CLK_LL_XTAL32K_CONFIG_DEFAULT();
+    LP_CLKRST.xtal32k.dac_xtal32k = cfg.dac;
+    LP_CLKRST.xtal32k.dres_xtal32k = cfg.dres;
+    LP_CLKRST.xtal32k.dgm_xtal32k = cfg.dgm;
+    LP_CLKRST.xtal32k.dbuf_xtal32k = cfg.dbuf;
+    // Enable xtal32k xpd
+    SET_PERI_REG_MASK(PMU_HP_SLEEP_LP_CK_POWER_REG, PMU_HP_SLEEP_XPD_XTAL32K);
 }
 
 /**
@@ -87,7 +121,8 @@ static inline void clk_ll_xtal32k_enable(clk_ll_xtal32k_enable_mode_t mode)
  */
 static inline void clk_ll_xtal32k_disable(void)
 {
-    // ESP32H2-TODO: IDF-6401
+    // Disable xtal32k xpd
+    CLEAR_PERI_REG_MASK(PMU_HP_SLEEP_LP_CK_POWER_REG, PMU_HP_SLEEP_XPD_XTAL32K);
 }
 
 /**
@@ -97,70 +132,61 @@ static inline void clk_ll_xtal32k_disable(void)
  */
 static inline bool clk_ll_xtal32k_is_enabled(void)
 {
-    // ESP32H2-TODO: IDF-6401
-    return 0;
+    return REG_GET_FIELD(PMU_HP_SLEEP_LP_CK_POWER_REG, PMU_HP_SLEEP_XPD_XTAL32K) == 1;
 }
 
 /**
- * @brief Enable the internal oscillator output for RC_FAST_CLK
+ * @brief Enable the internal oscillator output for RC32K_CLK
  */
-static inline __attribute__((always_inline)) void clk_ll_rc_fast_enable(void)
+static inline void clk_ll_rc32k_enable(void)
 {
-    // ESP32H2-TODO: IDF-6401
+    // Enable rc32k xpd status
+    SET_PERI_REG_MASK(PMU_HP_SLEEP_LP_CK_POWER_REG, PMU_HP_SLEEP_XPD_RC32K);
 }
 
 /**
- * @brief Disable the internal oscillator output for RC_FAST_CLK
+ * @brief Disable the internal oscillator output for RC32K_CLK
  */
-static inline __attribute__((always_inline)) void clk_ll_rc_fast_disable(void)
+static inline void clk_ll_rc32k_disable(void)
 {
-    // ESP32H2-TODO: IDF-6401
+    // Disable rc32k xpd status
+    CLEAR_PERI_REG_MASK(PMU_HP_SLEEP_LP_CK_POWER_REG, PMU_HP_SLEEP_XPD_RC32K);
 }
 
 /**
- * @brief Get the state of the internal oscillator for RC_FAST_CLK
+ * @brief Get the state of the internal oscillator for RC32K_CLK
  *
  * @return True if the oscillator is enabled
  */
-static inline bool clk_ll_rc_fast_is_enabled(void)
+static inline bool clk_ll_rc32k_is_enabled(void)
 {
-    // ESP32H2-TODO: IDF-6401
-    return 1;
+    return REG_GET_FIELD(PMU_HP_SLEEP_LP_CK_POWER_REG, PMU_HP_SLEEP_XPD_RC32K) == 1;
 }
 
 /**
- * @brief Enable the output from the internal oscillator to be passed into a configurable divider,
- * which by default divides the input clock frequency by 256. i.e. RC_FAST_D256_CLK = RC_FAST_CLK / 256
- *
- * Divider values other than 256 may be configured, but this facility is not currently needed,
- * so is not exposed in the code.
- * The output of the divider, RC_FAST_D256_CLK, is referred as 8md256 or simply d256 in reg. descriptions.
+ * @brief Enable the internal oscillator output for RC_FAST_CLK
  */
-static inline void clk_ll_rc_fast_d256_enable(void)
+static inline __attribute__((always_inline)) void clk_ll_rc_fast_enable(void)
 {
-    // ESP32H2-TODO: IDF-6401
+    SET_PERI_REG_MASK(PMU_HP_SLEEP_LP_CK_POWER_REG, PMU_HP_SLEEP_XPD_FOSC_CLK);
 }
 
 /**
- * @brief Disable the output from the internal oscillator to be passed into a configurable divider.
- * i.e. RC_FAST_D256_CLK = RC_FAST_CLK / 256
- *
- * Disabling this divider could reduce power consumption.
+ * @brief Disable the internal oscillator output for RC_FAST_CLK
  */
-static inline void clk_ll_rc_fast_d256_disable(void)
+static inline __attribute__((always_inline)) void clk_ll_rc_fast_disable(void)
 {
-    // ESP32H2-TODO: IDF-6401
+    CLEAR_PERI_REG_MASK(PMU_HP_SLEEP_LP_CK_POWER_REG, PMU_HP_SLEEP_XPD_FOSC_CLK);
 }
 
 /**
- * @brief Get the state of the divider which is applied to the output from the internal oscillator (RC_FAST_CLK)
+ * @brief Get the state of the internal oscillator for RC_FAST_CLK
  *
- * @return True if the divided output is enabled
+ * @return True if the oscillator is enabled
  */
-static inline bool clk_ll_rc_fast_d256_is_enabled(void)
+static inline bool clk_ll_rc_fast_is_enabled(void)
 {
-    // ESP32H2-TODO: IDF-6401
-    return 1;
+    return REG_GET_FIELD(PMU_HP_SLEEP_LP_CK_POWER_REG, PMU_HP_SLEEP_XPD_FOSC_CLK) == 1;
 }
 
 /**
@@ -186,51 +212,59 @@ static inline void clk_ll_rc_fast_digi_disable(void)
  */
 static inline bool clk_ll_rc_fast_digi_is_enabled(void)
 {
-    // ESP32H2-TODO: IDF-6401
-    return 0;
+    return LP_CLKRST.clk_to_hp.icg_hp_fosc;
 }
 
 /**
- * @brief Enable the digital RC_FAST_D256_CLK, which is used to support peripherals.
+ * @brief Enable the digital XTAL32K_CLK, which is used to support peripherals.
  */
-static inline void clk_ll_rc_fast_d256_digi_enable(void)
+static inline void clk_ll_xtal32k_digi_enable(void)
 {
-    // ESP32H2-TODO: IDF-6401
+    LP_CLKRST.clk_to_hp.icg_hp_xtal32k = 1;
 }
 
 /**
- * @brief Disable the digital RC_FAST_D256_CLK, which is used to support peripherals.
+ * @brief Disable the digital XTAL32K_CLK, which is used to support peripherals.
  */
-static inline void clk_ll_rc_fast_d256_digi_disable(void)
+static inline void clk_ll_xtal32k_digi_disable(void)
 {
-    // ESP32H2-TODO: IDF-6401
+    LP_CLKRST.clk_to_hp.icg_hp_xtal32k = 0;
 }
 
 /**
- * @brief Enable the digital XTAL32K_CLK, which is used to support peripherals.
+ * @brief Get the state of the digital XTAL32K_CLK
+ *
+ * @return True if the digital XTAL32K_CLK is enabled
  */
-static inline void clk_ll_xtal32k_digi_enable(void)
+static inline bool clk_ll_xtal32k_digi_is_enabled(void)
 {
-    // ESP32H2-TODO: IDF-6401
+    return LP_CLKRST.clk_to_hp.icg_hp_xtal32k;
 }
 
 /**
- * @brief Disable the digital XTAL32K_CLK, which is used to support peripherals.
+ * @brief Enable the digital RC32K_CLK, which is used to support peripherals.
  */
-static inline void clk_ll_xtal32k_digi_disable(void)
+static inline void clk_ll_rc32k_digi_enable(void)
 {
-    // ESP32H2-TODO: IDF-6401
+    LP_CLKRST.clk_to_hp.icg_hp_osc32k = 1;
 }
 
 /**
- * @brief Get the state of the digital XTAL32K_CLK
+ * @brief Disable the digital RC32K_CLK, which is used to support peripherals.
+ */
+static inline void clk_ll_rc32k_digi_disable(void)
+{
+    LP_CLKRST.clk_to_hp.icg_hp_osc32k = 0;
+}
+
+/**
+ * @brief Get the state of the digital RC32K_CLK
  *
- * @return True if the digital XTAL32K_CLK is enabled
+ * @return True if the digital RC32K_CLK is enabled
  */
-static inline bool clk_ll_xtal32k_digi_is_enabled(void)
+static inline bool clk_ll_rc32k_digi_is_enabled(void)
 {
-    // ESP32H2-TODO: IDF-6401
-    return 0;
+    return LP_CLKRST.clk_to_hp.icg_hp_osc32k;
 }
 
 /**
@@ -240,8 +274,8 @@ static inline bool clk_ll_xtal32k_digi_is_enabled(void)
  */
 static inline __attribute__((always_inline)) uint32_t clk_ll_bbpll_get_freq_mhz(void)
 {
-    // ESP32H2-TODO: IDF-6401
-    return 0;
+    // The target has a fixed 96MHz SPLL
+    return CLK_LL_PLL_96M_FREQ_MHZ;
 }
 
 /**
@@ -251,7 +285,9 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_bbpll_get_freq_mhz(
  */
 static inline __attribute__((always_inline)) void clk_ll_bbpll_set_freq_mhz(uint32_t pll_freq_mhz)
 {
-    // ESP32H2-TODO: IDF-6401
+    // The target SPLL is fixed to 96MHz
+    // Do nothing
+    HAL_ASSERT(pll_freq_mhz == CLK_LL_PLL_96M_FREQ_MHZ);
 }
 
 /**
@@ -262,26 +298,63 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_set_freq_mhz(uint
  */
 static inline __attribute__((always_inline)) void clk_ll_bbpll_set_config(uint32_t pll_freq_mhz, uint32_t xtal_freq_mhz)
 {
-    // ESP32H2-TODO: IDF-6401
+    HAL_ASSERT(xtal_freq_mhz == RTC_XTAL_FREQ_32M);
+    HAL_ASSERT(pll_freq_mhz == CLK_LL_PLL_96M_FREQ_MHZ);
+    uint8_t oc_ref_div;
+    uint8_t oc_div;
+    uint8_t oc_dhref_sel;
+    uint8_t oc_dlref_sel;
+
+    oc_ref_div = 0;
+    oc_div = 1;
+    oc_dhref_sel = 3;
+    oc_dlref_sel = 1;
+
+    REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_REF_DIV, oc_ref_div);
+    REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_DIV, oc_div);
+    REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_DHREF_SEL, oc_dhref_sel);
+    REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_DLREF_SEL, oc_dlref_sel);
 }
 
 /**
- * @brief Select the clock source for CPU_CLK
+ * @brief Get FLASH_PLL_CLK frequency
+ *
+ * @return FLASH_PLL clock frequency, in MHz
+ */
+static inline __attribute__((always_inline)) uint32_t clk_ll_flash_pll_get_freq_mhz(void)
+{
+    // The target has a fixed 64MHz flash PLL, which is directly derived from BBPLL
+    return CLK_LL_PLL_64M_FREQ_MHZ;
+}
+
+/**
+ * @brief To enable the change of soc_clk_sel, cpu_div_num, and ahb_div_num
+ */
+static inline __attribute__((always_inline)) void clk_ll_bus_update(void)
+{
+    PCR.bus_clk_update.bus_clock_update = 1;
+    while (PCR.bus_clk_update.bus_clock_update);
+}
+
+/**
+ * @brief Select the clock source for CPU_CLK (SOC Clock Root)
  *
  * @param in_sel One of the clock sources in soc_cpu_clk_src_t
  */
 static inline __attribute__((always_inline)) void clk_ll_cpu_set_src(soc_cpu_clk_src_t in_sel)
 {
-    // ESP32H2-TODO: IDF-6401
     switch (in_sel) {
     case SOC_CPU_CLK_SRC_XTAL:
-        REG_SET_FIELD(PCR_SYSCLK_CONF_REG, PCR_SOC_CLK_SEL, 0);
+        PCR.sysclk_conf.soc_clk_sel = 0;
         break;
     case SOC_CPU_CLK_SRC_PLL:
-        REG_SET_FIELD(PCR_SYSCLK_CONF_REG, PCR_SOC_CLK_SEL, 1);
+        PCR.sysclk_conf.soc_clk_sel = 1;
+        break;
+    case SOC_CPU_CLK_SRC_RC_FAST:
+        PCR.sysclk_conf.soc_clk_sel = 2;
         break;
-    case SOC_CPU_CLK_SRC_RC_FAST://FOSC
-        REG_SET_FIELD(PCR_SYSCLK_CONF_REG, PCR_SOC_CLK_SEL, 2);
+    case SOC_CPU_CLK_SRC_FLASH_PLL:
+        PCR.sysclk_conf.soc_clk_sel = 3;
         break;
     default:
         // Unsupported CPU_CLK mux input sel
@@ -290,124 +363,134 @@ static inline __attribute__((always_inline)) void clk_ll_cpu_set_src(soc_cpu_clk
 }
 
 /**
- * @brief Get the clock source for CPU_CLK
+ * @brief Get the clock source for CPU_CLK (SOC Clock Root)
  *
  * @return Currently selected clock source (one of soc_cpu_clk_src_t values)
  */
 static inline __attribute__((always_inline)) soc_cpu_clk_src_t clk_ll_cpu_get_src(void)
 {
-    // ESP32H2-TODO: IDF-6401
-    uint32_t clk_sel = REG_GET_FIELD(PCR_SYSCLK_CONF_REG, PCR_SOC_CLK_SEL);
+    uint32_t clk_sel = PCR.sysclk_conf.soc_clk_sel;
     switch (clk_sel) {
     case 0:
         return SOC_CPU_CLK_SRC_XTAL;
     case 1:
         return SOC_CPU_CLK_SRC_PLL;
-    case 2://FOSC
+    case 2:
         return SOC_CPU_CLK_SRC_RC_FAST;
+    case 3:
+        return SOC_CPU_CLK_SRC_FLASH_PLL;
     default:
         // Invalid SOC_CLK_SEL value
         return SOC_CPU_CLK_SRC_INVALID;
     }
 }
 
-#include "hal/uart_types.h"
-static inline __attribute__((always_inline)) void clk_ll_uart_set_sclk(uint32_t uart_num, uart_sclk_t source_clk)
-{
-    // switch (source_clk) {
-    //     default:
-    //     case UART_SCLK_APB:
-    //         REG_SET_FIELD(PCR_UART_SCLK_CONF_REG(uart_num), PCR_UART0_SCLK_SEL, 1);
-    //         break;
-    //     case UART_SCLK_RTC:
-    //         REG_SET_FIELD(PCR_UART_SCLK_CONF_REG(uart_num), PCR_UART0_SCLK_SEL, 2);
-    //         break;
-    //     case UART_SCLK_XTAL:
-    //         REG_SET_FIELD(PCR_UART_SCLK_CONF_REG(uart_num), PCR_UART0_SCLK_SEL, 3);
-    //         break;
-    // }
-}
-
-static inline __attribute__((always_inline)) void clk_ll_uart_get_sclk(uint32_t uart_num, uart_sclk_t *source_clk)
-{
-    // switch (REG_GET_FIELD(PCR_UART_SCLK_CONF_REG(uart_num), PCR_UART0_SCLK_SEL)) {
-    //     default:
-    //     case 1:
-    //         *source_clk = UART_SCLK_APB;
-    //         break;
-    //     case 2:
-    //         *source_clk = UART_SCLK_RTC;
-    //         break;
-    //     case 3:
-    //         *source_clk = UART_SCLK_XTAL;
-    //         break;
-    // }
-}
-
-static inline uint32_t clk_ll_get_uart_sclk_freq(uint32_t uart_num)
-{
-    // switch (REG_GET_FIELD(PCR_UART_SCLK_CONF_REG(uart_num), PCR_UART0_SCLK_SEL)) {
-    //     default:
-    //     case 1:
-    //         return APB_CLK_FREQ;
-    //     case 2:
-    //         return RTC_CLK_FREQ;
-    //     case 3:
-    //         return XTAL_CLK_FREQ;
-    // }
-    return 0;
+/**
+ * @brief Set CPU_CLK divider
+ *
+ * @param divider Divider. PRE_DIV_CNT = divider - 1.
+ */
+static inline __attribute__((always_inline)) void clk_ll_cpu_set_divider(uint32_t divider)
+{
+    HAL_ASSERT(divider >= 1);
+    HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.cpu_freq_conf, cpu_div_num, divider - 1);
 }
 
-static inline __attribute__((always_inline)) void clk_ll_uart_set_sclk_div_num(uint8_t uart_num, uint32_t val)
+/**
+ * @brief Get CPU_CLK divider
+ *
+ * @return Divider. Divider = (PRE_DIV_CNT + 1).
+ */
+static inline __attribute__((always_inline)) uint32_t clk_ll_cpu_get_divider(void)
 {
-    // REG_SET_FIELD(PCR_UART_SCLK_CONF_REG(uart_num), PCR_UART0_SCLK_DIV_NUM, val);
+    return HAL_FORCE_READ_U32_REG_FIELD(PCR.cpu_freq_conf, cpu_div_num) + 1;
 }
 
-static inline __attribute__((always_inline)) uint32_t clk_ll_uart_get_sclk_div_num(uint8_t uart_num)
+/**
+ * @brief Set AHB_CLK divider
+ *
+ * @param divider Divider. PRE_DIV_CNT = divider - 1.
+ */
+static inline __attribute__((always_inline)) void clk_ll_ahb_set_divider(uint32_t divider)
 {
-    return 0;//REG_GET_FIELD(PCR_UART_SCLK_CONF_REG(uart_num), PCR_UART0_SCLK_DIV_NUM);
+    HAL_ASSERT(divider >= 1);
+    HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.ahb_freq_conf, ahb_div_num, divider - 1);
 }
 
 /**
- * @brief Set CPU frequency from PLL clock
+ * @brief Get AHB_CLK divider
  *
- * @param cpu_mhz CPU frequency value, in MHz
+ * @return Divider. Divider = (PRE_DIV_CNT + 1).
  */
-static inline __attribute__((always_inline)) void clk_ll_cpu_set_freq_mhz_from_pll(uint32_t cpu_mhz)
+static inline __attribute__((always_inline)) uint32_t clk_ll_ahb_get_divider(void)
 {
-    // ESP32H2-TODO: IDF-6401
+    return HAL_FORCE_READ_U32_REG_FIELD(PCR.ahb_freq_conf, ahb_div_num) + 1;
 }
 
 /**
- * @brief Get CPU_CLK frequency from PLL_CLK source
+ * @brief Set APB_CLK divider. freq of APB_CLK = freq of AHB_CLK / divider
  *
- * @return CPU clock frequency, in MHz. Returns 0 if register field value is invalid.
+ * @param divider Divider. PCR_APB_DIV_NUM = divider - 1.
  */
-static inline __attribute__((always_inline)) uint32_t clk_ll_cpu_get_freq_mhz_from_pll(void)
+static inline __attribute__((always_inline)) void clk_ll_apb_set_divider(uint32_t divider)
 {
-    // ESP32H2-TODO: IDF-6401
-    return 0;
+    // AHB ------> APB
+    // Divider option: 1, 2, 4 (PCR_APB_DIV_NUM=0, 1, 3)
+    HAL_ASSERT(divider == 1 || divider == 2 || divider == 4);
+    HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.apb_freq_conf, apb_div_num, divider - 1);
 }
 
 /**
- * @brief Set CPU_CLK's XTAL/FAST_RC clock source path divider
+ * @brief Get APB_CLK divider
  *
- * @param divider Divider. Usually this divider is set to 1 in bootloader stage. PRE_DIV_CNT = divider - 1.
+ * @return Divider. Divider = (PCR_APB_DIV_NUM + 1).
  */
-static inline __attribute__((always_inline)) void clk_ll_cpu_set_divider(uint32_t divider)
+static inline __attribute__((always_inline)) uint32_t clk_ll_apb_get_divider(void)
 {
-    // ESP32H2-TODO: IDF-6401: not configurable for 761, fixed at 3 for HS, 1 for LS
+    return HAL_FORCE_READ_U32_REG_FIELD(PCR.apb_freq_conf, apb_div_num) + 1;
 }
 
 /**
- * @brief Get CPU_CLK's XTAL/FAST_RC clock source path divider
+ * @brief Select the calibration 32kHz clock source for timergroup0
  *
- * @return Divider. Divider = (PRE_DIV_CNT + 1).
+ * @param in_sel One of the 32kHz clock sources (RC32K_CLK, XTAL32K_CLK, OSC_SLOW_CLK)
  */
-static inline __attribute__((always_inline)) uint32_t clk_ll_cpu_get_divider(void)
+static inline void clk_ll_32k_calibration_set_target(soc_rtc_slow_clk_src_t in_sel)
 {
-    // ESP32H2-TODO: IDF-6401
-    return 0;
+    switch (in_sel) {
+    case SOC_RTC_SLOW_CLK_SRC_RC32K:
+        PCR.ctrl_32k_conf.clk_32k_sel = 0;
+        break;
+    case SOC_RTC_SLOW_CLK_SRC_XTAL32K:
+        PCR.ctrl_32k_conf.clk_32k_sel = 1;
+        break;
+    case SOC_RTC_SLOW_CLK_SRC_OSC_SLOW:
+        PCR.ctrl_32k_conf.clk_32k_sel = 2;
+        break;
+    default:
+        // Unsupported 32K_SEL mux input
+        abort();
+    }
+}
+
+/**
+ * @brief Get the calibration 32kHz clock source for timergroup0
+ *
+ * @return soc_rtc_slow_clk_src_t Currently selected calibration 32kHz clock (one of the 32kHz clocks)
+ */
+static inline soc_rtc_slow_clk_src_t clk_ll_32k_calibration_get_target(void)
+{
+    uint32_t clk_sel = PCR.ctrl_32k_conf.clk_32k_sel;
+    switch (clk_sel) {
+    case 0:
+        return SOC_RTC_SLOW_CLK_SRC_RC32K;
+    case 1:
+        return SOC_RTC_SLOW_CLK_SRC_XTAL32K;
+    case 2:
+        return SOC_RTC_SLOW_CLK_SRC_OSC_SLOW;
+    default:
+        return SOC_RTC_SLOW_CLK_SRC_INVALID;
+    }
 }
 
 /**
@@ -417,7 +500,23 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_cpu_get_divider(voi
  */
 static inline void clk_ll_rtc_slow_set_src(soc_rtc_slow_clk_src_t in_sel)
 {
-    // ESP32H2-TODO: IDF-6401
+    switch (in_sel) {
+    case SOC_RTC_SLOW_CLK_SRC_RC_SLOW:
+        LP_CLKRST.lp_clk_conf.slow_clk_sel = 0;
+        break;
+    case SOC_RTC_SLOW_CLK_SRC_XTAL32K:
+        LP_CLKRST.lp_clk_conf.slow_clk_sel = 1;
+        break;
+    case SOC_RTC_SLOW_CLK_SRC_RC32K:
+        LP_CLKRST.lp_clk_conf.slow_clk_sel = 2;
+        break;
+    case SOC_RTC_SLOW_CLK_SRC_OSC_SLOW:
+        LP_CLKRST.lp_clk_conf.slow_clk_sel = 3;
+        break;
+    default:
+        // Unsupported RTC_SLOW_CLK mux input sel
+        abort();
+    }
 }
 
 /**
@@ -427,8 +526,70 @@ static inline void clk_ll_rtc_slow_set_src(soc_rtc_slow_clk_src_t in_sel)
  */
 static inline soc_rtc_slow_clk_src_t clk_ll_rtc_slow_get_src(void)
 {
-    // ESP32H2-TODO: IDF-6401
-    return 0;
+    uint32_t clk_sel = LP_CLKRST.lp_clk_conf.slow_clk_sel;
+    switch (clk_sel) {
+    case 0:
+        return SOC_RTC_SLOW_CLK_SRC_RC_SLOW;
+    case 1:
+        return SOC_RTC_SLOW_CLK_SRC_XTAL32K;
+    case 2:
+        return SOC_RTC_SLOW_CLK_SRC_RC32K;
+    case 3:
+        return SOC_RTC_SLOW_CLK_SRC_OSC_SLOW;
+    default:
+        return SOC_RTC_SLOW_CLK_SRC_INVALID;
+    }
+}
+
+/**
+ * @brief Select the clock source for LP_PLL_CLK
+ *
+ * @param in_sel One of the clock sources in soc_lp_pll_clk_src_t
+ */
+static inline void clk_ll_lp_pll_set_src(soc_lp_pll_clk_src_t in_sel)
+{
+    uint32_t field_value;
+    switch (in_sel) {
+    case SOC_LP_PLL_CLK_SRC_RC32K:
+        field_value = 0;
+        break;
+    case SOC_LP_PLL_CLK_SRC_XTAL32K:
+        field_value = 1;
+        break;
+    default:
+        // Unsupported LP_PLL_CLK mux input sel
+        abort();
+    }
+    REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_SEL_PLL8M_REF, field_value);
+}
+
+/**
+ * @brief Get the clock source for LP_PLL_CLK
+ *
+ * @return Currently selected clock source (one of soc_lp_pll_clk_src_t values)
+ */
+static inline soc_lp_pll_clk_src_t clk_ll_lp_pll_get_src(void)
+{
+    uint32_t clk_sel = REGI2C_READ_MASK(I2C_PMU, I2C_PMU_SEL_PLL8M_REF);
+    switch (clk_sel) {
+    case 0:
+        return SOC_LP_PLL_CLK_SRC_RC32K;
+    case 1:
+        return SOC_LP_PLL_CLK_SRC_XTAL32K;
+    default:
+        return SOC_LP_PLL_CLK_SRC_INVALID;
+    }
+}
+
+/**
+ * @brief Get LP_PLL_CLK frequency
+ *
+ * @return LP_PLL clock frequency, in MHz
+ */
+static inline uint32_t clk_ll_lp_pll_get_freq_mhz(void)
+{
+    // The target has a fixed 8MHz LP_PLL
+    return CLK_LL_PLL_8M_FREQ_MHZ;
 }
 
 /**
@@ -438,7 +599,20 @@ static inline soc_rtc_slow_clk_src_t clk_ll_rtc_slow_get_src(void)
  */
 static inline void clk_ll_rtc_fast_set_src(soc_rtc_fast_clk_src_t in_sel)
 {
-    // ESP32H2-TODO: IDF-6401
+    switch (in_sel) {
+    case SOC_RTC_FAST_CLK_SRC_RC_FAST:
+        LP_CLKRST.lp_clk_conf.fast_clk_sel = 0;
+        break;
+    case SOC_RTC_FAST_CLK_SRC_XTAL_D2:
+        LP_CLKRST.lp_clk_conf.fast_clk_sel = 1;
+        break;
+    case SOC_RTC_FAST_CLK_SRC_LP_PLL:
+        LP_CLKRST.lp_clk_conf.fast_clk_sel = 2;
+        break;
+    default:
+        // Unsupported RTC_FAST_CLK mux input sel
+        abort();
+    }
 }
 
 /**
@@ -448,8 +622,17 @@ static inline void clk_ll_rtc_fast_set_src(soc_rtc_fast_clk_src_t in_sel)
  */
 static inline soc_rtc_fast_clk_src_t clk_ll_rtc_fast_get_src(void)
 {
-    // ESP32H2-TODO: IDF-6401
-    return 0;
+    uint32_t clk_sel = LP_CLKRST.lp_clk_conf.fast_clk_sel;
+    switch (clk_sel) {
+    case 0:
+        return SOC_RTC_FAST_CLK_SRC_RC_FAST;
+    case 1:
+        return SOC_RTC_FAST_CLK_SRC_XTAL_D2;
+    case 2:
+        return SOC_RTC_FAST_CLK_SRC_LP_PLL;
+    default:
+        return SOC_RTC_FAST_CLK_SRC_INVALID;
+    }
 }
 
 /**
@@ -459,7 +642,8 @@ static inline soc_rtc_fast_clk_src_t clk_ll_rtc_fast_get_src(void)
  */
 static inline void clk_ll_rc_fast_set_divider(uint32_t divider)
 {
-    // ESP32H2-TODO: IDF-6401
+    // No divider on the target
+    HAL_ASSERT(divider == 1);
 }
 
 /**
@@ -469,8 +653,8 @@ static inline void clk_ll_rc_fast_set_divider(uint32_t divider)
  */
 static inline uint32_t clk_ll_rc_fast_get_divider(void)
 {
-    // ESP32H2-TODO: IDF-6401
-    return 0;
+    // No divider on the target, always return divider = 1
+    return 1;
 }
 
 /**
@@ -480,21 +664,30 @@ static inline uint32_t clk_ll_rc_fast_get_divider(void)
  */
 static inline void clk_ll_rc_slow_set_divider(uint32_t divider)
 {
-    // ESP32H2-TODO: IDF-6401
+    // No divider on the target
+    HAL_ASSERT(divider == 1);
 }
 
-/************************* RTC STORAGE REGISTER STORE/LOAD **************************/
+/************************** LP STORAGE REGISTER STORE/LOAD **************************/
 /**
  * @brief Store XTAL_CLK frequency in RTC storage register
  *
  * Value of RTC_XTAL_FREQ_REG is stored as two copies in lower and upper 16-bit
  * halves. These are the routines to work with that representation.
  *
- * @param xtal_freq_mhz XTAL frequency, in MHz
+ * @param xtal_freq_mhz XTAL frequency, in MHz. The frequency must necessarily be even,
+ * otherwise there will be a conflict with the low bit, which is used to disable logs
+ * in the ROM code.
  */
 static inline void clk_ll_xtal_store_freq_mhz(uint32_t xtal_freq_mhz)
 {
-    // ESP32H2-TODO: IDF-6401
+    // Read the status of whether disabling logging from ROM code
+    uint32_t reg = READ_PERI_REG(RTC_XTAL_FREQ_REG) & RTC_DISABLE_ROM_LOG;
+    // If so, need to write back this setting
+    if (reg == RTC_DISABLE_ROM_LOG) {
+        xtal_freq_mhz |= 1;
+    }
+    WRITE_PERI_REG(RTC_XTAL_FREQ_REG, (xtal_freq_mhz & UINT16_MAX) | ((xtal_freq_mhz & UINT16_MAX) << 16));
 }
 
 /**
@@ -507,34 +700,13 @@ static inline void clk_ll_xtal_store_freq_mhz(uint32_t xtal_freq_mhz)
  */
 static inline __attribute__((always_inline)) uint32_t clk_ll_xtal_load_freq_mhz(void)
 {
-    // ESP32H2-TODO: IDF-6401
-    return 0;
-}
-
-/**
- * @brief Store APB_CLK frequency in RTC storage register
- *
- * Value of RTC_APB_FREQ_REG is stored as two copies in lower and upper 16-bit
- * halves. These are the routines to work with that representation.
- *
- * @param apb_freq_hz APB frequency, in Hz
- */
-static inline __attribute__((always_inline)) void clk_ll_apb_store_freq_hz(uint32_t apb_freq_hz)
-{
-    // ESP32H2-TODO: IDF-6401
-}
-
-/**
- * @brief Load APB_CLK frequency from RTC storage register
- *
- * Value of RTC_APB_FREQ_REG is stored as two copies in lower and upper 16-bit
- * halves. These are the routines to work with that representation.
- *
- * @return The stored APB frequency, in Hz
- */
-static inline uint32_t clk_ll_apb_load_freq_hz(void)
-{
-    // ESP32H2-TODO: IDF-6401
+    // Read from RTC storage register
+    uint32_t xtal_freq_reg = READ_PERI_REG(RTC_XTAL_FREQ_REG);
+    if ((xtal_freq_reg & 0xFFFF) == ((xtal_freq_reg >> 16) & 0xFFFF) &&
+        xtal_freq_reg != 0 && xtal_freq_reg != UINT32_MAX) {
+        return xtal_freq_reg & ~RTC_DISABLE_ROM_LOG & UINT16_MAX;
+    }
+    // If the format in reg is invalid
     return 0;
 }
 
@@ -548,7 +720,7 @@ static inline uint32_t clk_ll_apb_load_freq_hz(void)
  */
 static inline void clk_ll_rtc_slow_store_cal(uint32_t cal_value)
 {
-    // ESP32H2-TODO: IDF-6401
+    REG_WRITE(RTC_SLOW_CLK_CAL_REG, cal_value);
 }
 
 /**
@@ -560,8 +732,7 @@ static inline void clk_ll_rtc_slow_store_cal(uint32_t cal_value)
  */
 static inline uint32_t clk_ll_rtc_slow_load_cal(void)
 {
-    // ESP32H2-TODO: IDF-6401
-    return 0;
+    return REG_READ(RTC_SLOW_CLK_CAL_REG);
 }
 
 #ifdef __cplusplus

components/hal/esp32h2/include/hal/pmu_hal.h

@@ -0,0 +1,25 @@
+/*
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// The HAL layer for PMU
+
+#pragma once
+
+#include "soc/soc_caps.h"
+#include "hal/pmu_ll.h"
+#include "hal/pmu_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct {
+    pmu_dev_t *dev;
+} pmu_hal_context_t;
+
+#ifdef __cplusplus
+}
+#endif

components/hal/esp32h2/include/hal/pmu_ll.h

@@ -0,0 +1,658 @@
+/*
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// The LL layer for ESP32-H2 PMU register operations
+
+//TODO: IDF-6267
+#pragma once
+
+#include <stdlib.h>
+#include <stdbool.h>
+#include "soc/soc.h"
+#include "esp_attr.h"
+#include "hal/assert.h"
+#include "soc/pmu_struct.h"
+#include "hal/pmu_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Set the power domain that needs to be powered down in the digital power
+ *
+ * @param hw Beginning address of the peripheral registers.
+ * @param mode The pmu mode
+ * @param flag Digital power domain flag
+ *
+ * @return None
+ */
+FORCE_INLINE_ATTR void pmu_ll_hp_set_dig_power(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t flag)
+{
+    hw->hp_sys[mode].dig_power.val = flag;
+}
+
+FORCE_INLINE_ATTR void pmu_ll_hp_set_icg_func(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t icg_func)
+{
+    hw->hp_sys[mode].icg_func = icg_func;
+}
+
+FORCE_INLINE_ATTR void pmu_ll_hp_set_icg_apb(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t bitmap)
+{
+    hw->hp_sys[mode].icg_apb = bitmap;
+}
+
+FORCE_INLINE_ATTR void pmu_ll_hp_set_icg_modem(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t code)
+{
+    hw->hp_sys[mode].icg_modem.code = code;
+}
+
+FORCE_INLINE_ATTR void pmu_ll_hp_set_uart_wakeup_enable(pmu_dev_t *hw, pmu_hp_mode_t mode, bool wakeup_en)
+{
+    hw->hp_sys[mode].syscntl.uart_wakeup_en = wakeup_en;
+}
+
+FORCE_INLINE_ATTR void pmu_ll_hp_set_hold_all_lp_pad(pmu_dev_t *hw, pmu_hp_mode_t mode, bool hold_all)
+{
+    hw->hp_sys[mode].syscntl.lp_pad_hold_all = hold_all;
+}
+
+FORCE_INLINE_ATTR void pmu_ll_hp_set_hold_all_hp_pad(pmu_dev_t *hw, pmu_hp_mode_t mode, bool hold_all)
+{
+    hw->hp_sys[mode].syscntl.hp_pad_hold_all = hold_all;
+}
+
+FORCE_INLINE_ATTR void pmu_ll_hp_set_dig_pad_slp_sel(pmu_dev_t *hw, pmu_hp_mode_t mode, bool slp_sel)
+{
+    hw->hp_sys[mode].syscntl.dig_pad_slp_sel = slp_sel;
+}
+
+FORCE_INLINE_ATTR void pmu_ll_hp_set_pause_watchdog(pmu_dev_t *hw, pmu_hp_mode_t mode, bool pause_wdt)
+{
+    hw->hp_sys[mode].syscntl.dig_pause_wdt = pause_wdt;
+}
+
+FORCE_INLINE_ATTR void pmu_ll_hp_set_cpu_stall(pmu_dev_t *hw, pmu_hp_mode_t mode, bool cpu_stall)
+{
+    hw->hp_sys[mode].syscntl.dig_cpu_stall = cpu_stall;
+}
+
+/**
+ * @brief Set the power domain that needs to be powered down in the clock power
+ *
+ * @param hw Beginning address of the peripheral registers.
+ * @param mode The pmu mode
+ * @param flag Clock power domain flag
+ *
+ * @return None
+ */
+FORCE_INLINE_ATTR void pmu_ll_hp_set_clk_power(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t xpd_flag)
+{
+    hw->hp_sys[mode].clk_power.val = xpd_flag;
+}
+
+FORCE_INLINE_ATTR void pmu_ll_hp_set_bias_xpd(pmu_dev_t *hw, pmu_hp_mode_t mode, bool xpd_bias)
+{
+    hw->hp_sys[mode].bias.xpd_bias = xpd_bias;
+}
+
+FORCE_INLINE_ATTR void pmu_ll_hp_set_trx_xpd(pmu_dev_t *hw, pmu_hp_mode_t mode, bool xpd_trx)
+{
+    hw->hp_sys[mode].bias.xpd_trx = xpd_trx;
+}
+
+FORCE_INLINE_ATTR void pmu_ll_hp_set_xtal_xpd(pmu_dev_t *hw, pmu_hp_mode_t mode, bool xpd_xtal)
+{
+    hw->hp_sys[mode].xtal.xpd_xtal = xpd_xtal;
+}
+
+FORCE_INLINE_ATTR void pmu_ll_hp_set_current_power_off(pmu_dev_t *hw, pmu_hp_mode_t mode, bool off)
+{
+    hw->hp_sys[mode].bias.pd_cur = off;
+}
+
+FORCE_INLINE_ATTR void pmu_ll_hp_set_bias_sleep_enable(pmu_dev_t *hw, pmu_hp_mode_t mode, bool en)
+{
+    hw->hp_sys[mode].bias.bias_sleep = en;
+}
+
+FORCE_INLINE_ATTR void pmu_ll_hp_set_retention_param(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t param)
+{
+    hw->hp_sys[mode].backup.val = param;
+}
+
+// FORCE_INLINE_ATTR void pmu_ll_hp_set_sleep_to_active_backup_enable(pmu_dev_t *hw)
+// {
+//     hw->hp_sys[PMU_MODE_HP_ACTIVE].backup.hp_sleep2active_backup_en = 1;
+// }
+
+// FORCE_INLINE_ATTR void pmu_ll_hp_set_sleep_to_active_backup_disable(pmu_dev_t *hw)
+// {
+//     hw->hp_sys[PMU_MODE_HP_ACTIVE].backup.hp_sleep2active_backup_en = 0;
+// }
+
+// FORCE_INLINE_ATTR void pmu_ll_hp_set_modem_to_active_backup_enable(pmu_dev_t *hw)
+// {
+//     hw->hp_sys[PMU_MODE_HP_ACTIVE].backup.hp_modem2active_backup_en = 1;
+// }
+
+// FORCE_INLINE_ATTR void pmu_ll_hp_set_modem_to_active_backup_disable(pmu_dev_t *hw)
+// {
+//     hw->hp_sys[PMU_MODE_HP_ACTIVE].backup.hp_modem2active_backup_en = 0;
+// }
+
+// FORCE_INLINE_ATTR void pmu_ll_hp_set_sleep_to_modem_backup_enable(pmu_dev_t *hw)
+// {
+//     hw->hp_sys[PMU_MODE_HP_MODEM].backup.hp_sleep2modem_backup_en = 1;
+// }
+
+// FORCE_INLINE_ATTR void pmu_ll_hp_set_sleep_to_modem_backup_disable(pmu_dev_t *hw)
+// {
+//     hw->hp_sys[PMU_MODE_HP_MODEM].backup.hp_sleep2modem_backup_en = 0;
+// }
+
+// FORCE_INLINE_ATTR void pmu_ll_hp_set_active_to_sleep_backup_enable(pmu_dev_t *hw)
+// {
+//     hw->hp_sys[PMU_MODE_HP_SLEEP].backup.hp_active2sleep_backup_en = 1;
+// }
+
+// FORCE_INLINE_ATTR void pmu_ll_hp_set_active_to_sleep_backup_disable(pmu_dev_t *hw)
+// {
+//     hw->hp_sys[PMU_MODE_HP_SLEEP].backup.hp_active2sleep_backup_en = 0;
+// }
+
+// FORCE_INLINE_ATTR void pmu_ll_hp_set_modem_to_sleep_backup_enable(pmu_dev_t *hw)
+// {
+//     hw->hp_sys[PMU_MODE_HP_SLEEP].backup.hp_modem2sleep_backup_en = 1;
+// }
+
+// FORCE_INLINE_ATTR void pmu_ll_hp_set_modem_to_sleep_backup_disable(pmu_dev_t *hw)
+// {
+//     hw->hp_sys[PMU_MODE_HP_SLEEP].backup.hp_modem2sleep_backup_en = 0;
+// }
+
+FORCE_INLINE_ATTR void pmu_ll_hp_set_backup_icg_func(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t icg_func)
+{
+    hw->hp_sys[mode].backup_clk = icg_func;
+}
+
+FORCE_INLINE_ATTR void pmu_ll_hp_set_sysclk_nodiv(pmu_dev_t *hw, pmu_hp_mode_t mode, bool sysclk_nodiv)
+{
+    hw->hp_sys[mode].sysclk.dig_sysclk_nodiv = sysclk_nodiv;
+}
+
+FORCE_INLINE_ATTR void pmu_ll_hp_set_icg_sysclk_enable(pmu_dev_t *hw, pmu_hp_mode_t mode, bool icg_sysclk_en)
+{
+    hw->hp_sys[mode].sysclk.icg_sysclk_en = icg_sysclk_en;
+}
+
+FORCE_INLINE_ATTR void pmu_ll_hp_set_sysclk_slp_sel(pmu_dev_t *hw, pmu_hp_mode_t mode, bool slp_sel)
+{
+    hw->hp_sys[mode].sysclk.sysclk_slp_sel = slp_sel;
+}
+
+FORCE_INLINE_ATTR void pmu_ll_hp_set_icg_sysclk_slp_sel(pmu_dev_t *hw, pmu_hp_mode_t mode, bool slp_sel)
+{
+    hw->hp_sys[mode].sysclk.icg_slp_sel = slp_sel;
+}
+
+FORCE_INLINE_ATTR void pmu_ll_hp_set_dig_sysclk(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t sysclk_sel)
+{
+    hw->hp_sys[mode].sysclk.dig_sysclk_sel = sysclk_sel;
+}
+
+FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_sleep_logic_xpd(pmu_dev_t *hw, pmu_hp_mode_t mode, bool slp_xpd)
+{
+    hw->hp_sys[mode].regulator0.slp_logic_xpd = slp_xpd;
+}
+
+FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_sleep_memory_xpd(pmu_dev_t *hw, pmu_hp_mode_t mode, bool slp_xpd)
+{
+    hw->hp_sys[mode].regulator0.slp_mem_xpd = slp_xpd;
+}
+
+FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_xpd(pmu_dev_t *hw, pmu_hp_mode_t mode, bool xpd)
+{
+    hw->hp_sys[mode].regulator0.xpd = xpd;
+}
+
+FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_sleep_logic_dbias(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t slp_dbias)
+{
+    hw->hp_sys[mode].regulator0.slp_logic_dbias = slp_dbias;
+}
+
+FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_sleep_memory_dbias(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t slp_dbias)
+{
+    hw->hp_sys[mode].regulator0.slp_mem_dbias = slp_dbias;
+}
+
+FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_dbias(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t dbias)
+{
+    hw->hp_sys[mode].regulator0.dbias = dbias;
+}
+
+FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_driver_bar(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t drv_b)
+{
+    hw->hp_sys[mode].regulator1.drv_b = drv_b;
+}
+
+FORCE_INLINE_ATTR void pmu_ll_lp_set_regulator_slp_xpd(pmu_dev_t *hw, pmu_lp_mode_t mode, bool slp_xpd)
+{
+    hw->lp_sys[mode].regulator0.slp_xpd = slp_xpd;
+}
+
+FORCE_INLINE_ATTR void pmu_ll_lp_set_regulator_xpd(pmu_dev_t *hw, pmu_lp_mode_t mode, bool xpd)
+{
+    hw->lp_sys[mode].regulator0.xpd = xpd;
+}
+
+FORCE_INLINE_ATTR void pmu_ll_lp_set_regulator_sleep_dbias(pmu_dev_t *hw, pmu_lp_mode_t mode, uint32_t slp_dbias)
+{
+    hw->lp_sys[mode].regulator0.slp_dbias = slp_dbias;
+}
+
+FORCE_INLINE_ATTR void pmu_ll_lp_set_regulator_dbias(pmu_dev_t *hw, pmu_lp_mode_t mode, uint32_t dbias)
+{
+    hw->lp_sys[mode].regulator0.dbias = dbias;
+}
+
+FORCE_INLINE_ATTR void pmu_ll_lp_set_regulator_driver_bar(pmu_dev_t *hw, pmu_lp_mode_t mode, uint32_t drv_b)
+{
+    hw->lp_sys[mode].regulator1.drv_b = drv_b;
+}
+
+FORCE_INLINE_ATTR void pmu_ll_lp_set_xtal_xpd(pmu_dev_t *hw, pmu_lp_mode_t mode, bool slp_xpd)
+{
+    HAL_ASSERT(mode == PMU_MODE_LP_SLEEP);
+    hw->lp_sys[mode].xtal.xpd_xtal = slp_xpd;
+}
+
+FORCE_INLINE_ATTR void pmu_ll_lp_set_dig_power(pmu_dev_t *hw, pmu_lp_mode_t mode, uint32_t flag)
+{
+    hw->lp_sys[mode].dig_power.val = flag;
+}
+
+FORCE_INLINE_ATTR void pmu_ll_lp_set_clk_power(pmu_dev_t *hw, pmu_lp_mode_t mode, uint32_t xpd_flag)
+{
+    hw->lp_sys[mode].clk_power.val = xpd_flag;
+}
+
+FORCE_INLINE_ATTR uint32_t pmu_ll_lp_get_clk_power(pmu_dev_t *hw, pmu_lp_mode_t mode)
+{
+    return hw->lp_sys[mode].clk_power.val;
+}
+
+FORCE_INLINE_ATTR void pmu_ll_lp_set_bias_xpd(pmu_dev_t *hw, pmu_lp_mode_t mode, bool xpd_bias)
+{
+    HAL_ASSERT(mode == PMU_MODE_LP_SLEEP);
+    hw->lp_sys[mode].bias.xpd_bias = xpd_bias;
+}
+
+FORCE_INLINE_ATTR void pmu_ll_lp_set_current_power_off(pmu_dev_t *hw, pmu_lp_mode_t mode, bool off)
+{
+    HAL_ASSERT(mode == PMU_MODE_LP_SLEEP);
+    hw->lp_sys[mode].bias.pd_cur = off;
+}
+
+FORCE_INLINE_ATTR void pmu_ll_lp_set_bias_sleep_enable(pmu_dev_t *hw, pmu_lp_mode_t mode, bool en)
+{
+    HAL_ASSERT(mode == PMU_MODE_LP_SLEEP);
+    hw->lp_sys[mode].bias.bias_sleep = en;
+}
+
+/****/
+FORCE_INLINE_ATTR void pmu_ll_imm_set_clk_power(pmu_dev_t *hw, uint32_t flag)
+{
+    hw->imm.clk_power.val = flag;
+}
+
+FORCE_INLINE_ATTR void pmu_ll_imm_set_icg_slp_sel(pmu_dev_t *hw, bool slp_sel)
+{
+    if (slp_sel) {
+        hw->imm.sleep_sysclk.tie_high_icg_slp_sel = 1;
+    } else {
+        hw->imm.sleep_sysclk.tie_low_icg_slp_sel = 1;
+    }
+}
+
+FORCE_INLINE_ATTR void pmu_ll_imm_update_dig_sysclk_sel(pmu_dev_t *hw, bool update)
+{
+    hw->imm.sleep_sysclk.update_dig_sysclk_sel = update;
+}
+
+// FORCE_INLINE_ATTR void pmu_ll_imm_update_dig_icg_switch(pmu_dev_t *hw, bool update)
+// {
+//     hw->imm.sleep_sysclk.update_dig_icg_switch = update;
+// }
+
+FORCE_INLINE_ATTR void pmu_ll_imm_update_dig_icg_func(pmu_dev_t *hw, bool icg_func_update)
+{
+    hw->imm.hp_func_icg.update_dig_icg_func_en = icg_func_update;
+}
+
+FORCE_INLINE_ATTR void pmu_ll_imm_update_dig_icg_apb(pmu_dev_t *hw, bool icg_apb_update)
+{
+    hw->imm.hp_apb_icg.update_dig_icg_apb_en = icg_apb_update;
+}
+
+FORCE_INLINE_ATTR void pmu_ll_imm_update_dig_icg_modem_code(pmu_dev_t *hw, bool icg_modem_update)
+{
+    hw->imm.modem_icg.update_dig_icg_modem_en = icg_modem_update;
+}
+
+FORCE_INLINE_ATTR void pmu_ll_imm_set_lp_rootclk_sel(pmu_dev_t *hw, bool rootclk_sel)
+{
+    if (rootclk_sel) {
+        hw->imm.lp_icg.tie_high_lp_rootclk_sel = 1;
+    } else {
+        hw->imm.lp_icg.tie_low_lp_rootclk_sel = 1;
+    }
+}
+
+FORCE_INLINE_ATTR void pmu_ll_imm_set_hp_pad_hold_all(pmu_dev_t *hw, bool hold_all)
+{
+    if (hold_all) {
+        hw->imm.pad_hold_all.tie_high_hp_pad_hold_all = 1;
+    } else {
+        hw->imm.pad_hold_all.tie_low_hp_pad_hold_all = 1;
+    }
+}
+
+FORCE_INLINE_ATTR void pmu_ll_imm_set_lp_pad_hold_all(pmu_dev_t *hw, bool hold_all)
+{
+    if (hold_all) {
+        hw->imm.pad_hold_all.tie_high_lp_pad_hold_all = 1;
+    } else {
+        hw->imm.pad_hold_all.tie_low_lp_pad_hold_all = 1;
+    }
+}
+
+/*** */
+FORCE_INLINE_ATTR void pmu_ll_hp_set_power_force_reset(pmu_dev_t *hw, pmu_hp_power_domain_t domain, bool rst)
+{
+    hw->power.hp_pd[domain].force_reset = rst;
+}
+
+FORCE_INLINE_ATTR void pmu_ll_hp_set_power_force_isolate(pmu_dev_t *hw, pmu_hp_power_domain_t domain, bool iso)
+{
+    hw->power.hp_pd[domain].force_iso = iso;
+}
+
+FORCE_INLINE_ATTR void pmu_ll_hp_set_power_force_power_up(pmu_dev_t *hw, pmu_hp_power_domain_t domain, bool fpu)
+{
+    hw->power.hp_pd[domain].force_pu = fpu;
+}
+
+FORCE_INLINE_ATTR void pmu_ll_hp_set_power_force_no_reset(pmu_dev_t *hw, pmu_hp_power_domain_t domain, bool no_rst)
+{
+    hw->power.hp_pd[domain].force_no_reset = no_rst;
+}
+
+FORCE_INLINE_ATTR void pmu_ll_hp_set_power_force_no_isolate(pmu_dev_t *hw, pmu_hp_power_domain_t domain, bool no_iso)
+{
+    hw->power.hp_pd[domain].force_no_iso = no_iso;
+}
+
+FORCE_INLINE_ATTR void pmu_ll_hp_set_power_force_power_down(pmu_dev_t *hw, pmu_hp_power_domain_t domain, bool fpd)
+{
+    hw->power.hp_pd[domain].force_pd = fpd;
+}
+
+FORCE_INLINE_ATTR void pmu_ll_lp_set_power_force_reset(pmu_dev_t *hw, bool rst)
+{
+    hw->power.lp_peri.force_reset = rst;
+}
+
+FORCE_INLINE_ATTR void pmu_ll_lp_set_power_force_isolate(pmu_dev_t *hw, bool iso)
+{
+    hw->power.lp_peri.force_iso = iso;
+}
+
+FORCE_INLINE_ATTR void pmu_ll_lp_set_power_force_power_up(pmu_dev_t *hw, bool fpu)
+{
+    hw->power.lp_peri.force_pu = fpu;
+}
+
+FORCE_INLINE_ATTR void pmu_ll_lp_set_power_force_no_reset(pmu_dev_t *hw, bool no_rst)
+{
+    hw->power.lp_peri.force_no_reset = no_rst;
+}
+
+FORCE_INLINE_ATTR void pmu_ll_lp_set_power_force_no_isolate(pmu_dev_t *hw, bool no_iso)
+{
+    hw->power.lp_peri.force_no_iso = no_iso;
+}
+
+FORCE_INLINE_ATTR void pmu_ll_lp_set_power_force_power_down(pmu_dev_t *hw, bool fpd)
+{
+    hw->power.lp_peri.force_pd = fpd;
+}
+
+FORCE_INLINE_ATTR void pmu_ll_hp_set_memory_isolate(pmu_dev_t *hw, uint32_t iso)
+{
+    hw->power.mem_cntl.force_hp_mem_iso = iso;
+}
+
+FORCE_INLINE_ATTR void pmu_ll_hp_set_memory_power_down(pmu_dev_t *hw, uint32_t fpd)
+{
+    hw->power.mem_cntl.force_hp_mem_pd = fpd;
+}
+
+FORCE_INLINE_ATTR void pmu_ll_hp_set_memory_no_isolate(pmu_dev_t *hw, uint32_t no_iso)
+{
+    hw->power.mem_cntl.force_hp_mem_no_iso = no_iso;
+}
+
+FORCE_INLINE_ATTR void pmu_ll_hp_set_memory_power_up(pmu_dev_t *hw, uint32_t fpu)
+{
+    hw->power.mem_cntl.force_hp_mem_pu = fpu;
+}
+
+/*** */
+FORCE_INLINE_ATTR void pmu_ll_hp_set_sleep_enable(pmu_dev_t *hw)
+{
+    hw->wakeup.cntl0.sleep_req = 1;
+}
+
+FORCE_INLINE_ATTR void pmu_ll_hp_set_reject_enable(pmu_dev_t *hw, uint32_t reject)
+{
+    hw->wakeup.cntl1.sleep_reject_ena = reject;
+    hw->wakeup.cntl1.slp_reject_en = 1;
+}
+
+FORCE_INLINE_ATTR void pmu_ll_hp_set_reject_disable(pmu_dev_t *hw)
+{
+    hw->wakeup.cntl1.slp_reject_en = 0;
+}
+
+FORCE_INLINE_ATTR void pmu_ll_hp_set_wakeup_enable(pmu_dev_t *hw, uint32_t wakeup)
+{
+    hw->wakeup.cntl2 = wakeup;
+}
+
+// FORCE_INLINE_ATTR void pmu_ll_hp_set_sleep_protect_mode(pmu_dev_t *hw, int mode)
+// {
+//     hw->wakeup.cntl3.sleep_prt_sel = mode;
+// }
+
+FORCE_INLINE_ATTR void pmu_ll_hp_set_min_sleep_cycle(pmu_dev_t *hw, uint32_t cycle)
+{
+    hw->wakeup.cntl3.hp_min_slp_val = cycle;
+}
+
+FORCE_INLINE_ATTR void pmu_ll_hp_clear_reject_cause(pmu_dev_t *hw)
+{
+    hw->wakeup.cntl4.slp_reject_cause_clr = 1;
+}
+
+FORCE_INLINE_ATTR bool pmu_ll_hp_is_sleep_wakeup(pmu_dev_t *hw)
+{
+    return (hw->hp_ext.int_raw.wakeup == 1);
+}
+
+FORCE_INLINE_ATTR bool pmu_ll_hp_is_sleep_reject(pmu_dev_t *hw)
+{
+    return (hw->hp_ext.int_raw.reject == 1);
+}
+
+FORCE_INLINE_ATTR void pmu_ll_hp_clear_wakeup_intr_status(pmu_dev_t *hw)
+{
+    hw->hp_ext.int_clr.wakeup = 1;
+}
+
+FORCE_INLINE_ATTR void pmu_ll_hp_clear_reject_intr_status(pmu_dev_t *hw)
+{
+    hw->hp_ext.int_clr.reject = 1;
+}
+
+FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_wakeup_cause(pmu_dev_t *hw)
+{
+    return hw->wakeup.status0;
+}
+
+FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_reject_cause(pmu_dev_t *hw)
+{
+    return hw->wakeup.status1;
+}
+
+// FORCE_INLINE_ATTR void pmu_ll_lp_set_min_sleep_cycle(pmu_dev_t *hw, uint32_t slow_clk_cycle)
+// {
+//     hw->wakeup.cntl3.lp_min_slp_val = slow_clk_cycle;
+// }
+
+// FORCE_INLINE_ATTR void pmu_ll_hp_set_modify_icg_cntl_wait_cycle(pmu_dev_t *hw, uint32_t cycle)
+// {
+//     hw->hp_ext.clk_cntl.modify_icg_cntl_wait = cycle;
+// }
+
+// FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_modify_icg_cntl_wait_cycle(pmu_dev_t *hw)
+// {
+//     return hw->hp_ext.clk_cntl.modify_icg_cntl_wait;
+// }
+
+// FORCE_INLINE_ATTR void pmu_ll_hp_set_switch_icg_cntl_wait_cycle(pmu_dev_t *hw, uint32_t cycle)
+// {
+//     hw->hp_ext.clk_cntl.switch_icg_cntl_wait = cycle;
+// }
+
+// FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_switch_icg_cntl_wait_cycle(pmu_dev_t *hw)
+// {
+//     return hw->hp_ext.clk_cntl.switch_icg_cntl_wait;
+// }
+
+// FORCE_INLINE_ATTR void pmu_ll_hp_set_digital_power_down_wait_cycle(pmu_dev_t *hw, uint32_t cycle)
+// {
+//     hw->power.wait_timer0.powerdown_timer = cycle;
+// }
+
+// FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_digital_power_down_wait_cycle(pmu_dev_t *hw)
+// {
+//     return hw->power.wait_timer0.powerdown_timer;
+// }
+
+// FORCE_INLINE_ATTR void pmu_ll_lp_set_digital_power_down_wait_cycle(pmu_dev_t *hw, uint32_t cycle)
+// {
+//     hw->power.wait_timer1.powerdown_timer = cycle;
+// }
+
+// FORCE_INLINE_ATTR uint32_t pmu_ll_lp_get_digital_power_down_wait_cycle(pmu_dev_t *hw)
+// {
+//     return hw->power.wait_timer1.powerdown_timer;
+// }
+
+// FORCE_INLINE_ATTR void pmu_ll_lp_set_analog_wait_target_cycle(pmu_dev_t *hw, uint32_t slow_clk_cycle)
+// {
+//     hw->wakeup.cntl5.lp_ana_wait_target = slow_clk_cycle;
+// }
+
+// FORCE_INLINE_ATTR uint32_t pmu_ll_lp_get_analog_wait_target_cycle(pmu_dev_t *hw)
+// {
+//     return hw->wakeup.cntl5.lp_ana_wait_target;
+// }
+
+// FORCE_INLINE_ATTR void pmu_ll_set_modem_wait_target_cycle(pmu_dev_t *hw, uint32_t cycle)
+// {
+//     hw->wakeup.cntl5.modem_wait_target = cycle;
+// }
+
+// FORCE_INLINE_ATTR uint32_t pmu_ll_get_modem_wait_target_cycle(pmu_dev_t *hw)
+// {
+//     return hw->wakeup.cntl5.modem_wait_target;
+// }
+
+// FORCE_INLINE_ATTR void pmu_ll_set_xtal_stable_wait_cycle(pmu_dev_t *hw, uint32_t cycle)
+// {
+//     hw->power.clk_wait.wait_xtal_stable = cycle;
+// }
+
+// FORCE_INLINE_ATTR uint32_t pmu_ll_get_xtal_stable_wait_cycle(pmu_dev_t *hw)
+// {
+//     return hw->power.clk_wait.wait_xtal_stable;
+// }
+
+// FORCE_INLINE_ATTR void pmu_ll_set_pll_stable_wait_cycle(pmu_dev_t *hw, uint32_t cycle)
+// {
+//     hw->power.clk_wait.wait_pll_stable = cycle;
+// }
+
+// FORCE_INLINE_ATTR uint32_t pmu_ll_get_pll_stable_wait_cycle(pmu_dev_t *hw)
+// {
+//     return hw->power.clk_wait.wait_pll_stable;
+// }
+
+// FORCE_INLINE_ATTR void pmu_ll_lp_set_digital_power_supply_wait_cycle(pmu_dev_t *hw, uint32_t cycle)
+// {
+//     hw->power.wait_timer1.wait_timer = cycle;
+// }
+
+// FORCE_INLINE_ATTR uint32_t pmu_ll_lp_get_digital_power_supply_wait_cycle(pmu_dev_t *hw)
+// {
+//     return hw->power.wait_timer1.wait_timer;
+// }
+
+// FORCE_INLINE_ATTR void pmu_ll_lp_set_digital_power_up_wait_cycle(pmu_dev_t *hw, uint32_t cycle)
+// {
+//     hw->power.wait_timer1.powerup_timer = cycle;
+// }
+
+// FORCE_INLINE_ATTR uint32_t pmu_ll_lp_get_digital_power_up_wait_cycle(pmu_dev_t *hw)
+// {
+//     return hw->power.wait_timer1.powerup_timer;
+// }
+
+// FORCE_INLINE_ATTR void pmu_ll_hp_set_analog_wait_target_cycle(pmu_dev_t *hw, uint32_t cycle)
+// {
+//     hw->wakeup.cntl7.ana_wait_target = cycle;
+// }
+
+// FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_analog_wait_target_cycle(pmu_dev_t *hw)
+// {
+//     return hw->wakeup.cntl7.ana_wait_target;
+// }
+
+// FORCE_INLINE_ATTR void pmu_ll_hp_set_digital_power_supply_wait_cycle(pmu_dev_t *hw, uint32_t cycle)
+// {
+//     hw->power.wait_timer0.wait_timer = cycle;
+// }
+
+// FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_digital_power_supply_wait_cycle(pmu_dev_t *hw)
+// {
+//     return hw->power.wait_timer0.wait_timer;
+// }
+
+// FORCE_INLINE_ATTR void pmu_ll_hp_set_digital_power_up_wait_cycle(pmu_dev_t *hw, uint32_t cycle)
+// {
+//     hw->power.wait_timer0.powerup_timer = cycle;
+// }
+
+// FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_digital_power_up_wait_cycle(pmu_dev_t *hw)
+// {
+//     return hw->power.wait_timer0.powerup_timer;
+// }
+
+#ifdef __cplusplus
+}
+#endif

components/hal/esp32h2/include/hal/regi2c_ctrl_ll.h

@@ -17,28 +17,31 @@ extern "C" {
 #endif
 
 /**
- * @brief Reset (Disable) the I2C internal bus for all regi2c registers
+ * @brief Start BBPLL self-calibration
  */
-static inline void regi2c_ctrl_ll_i2c_reset(void)
+static inline __attribute__((always_inline)) void regi2c_ctrl_ll_bbpll_calibration_start(void)
 {
-    SET_PERI_REG_BITS(ANA_CONFIG_REG, ANA_CONFIG_M, ANA_CONFIG_M, ANA_CONFIG_S);
+    REG_CLR_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH);
+    REG_SET_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW);
 }
 
 /**
- * @brief Enable the I2C internal bus to do I2C read/write operation to the BBPLL configuration register
+ * @brief Stop BBPLL self-calibration
  */
-static inline void regi2c_ctrl_ll_i2c_bbpll_enable(void)
+static inline __attribute__((always_inline)) void regi2c_ctrl_ll_bbpll_calibration_stop(void)
 {
-    CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, ANA_I2C_BBPLL_M);
+    REG_CLR_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW);
+    REG_SET_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH);
 }
 
 /**
- * @brief Start BBPLL self-calibration
+ * @brief Check whether BBPLL calibration is done
+ *
+ * @return True if calibration is done; otherwise false
  */
-static inline __attribute__((always_inline)) void regi2c_ctrl_ll_bbpll_calibration_start(void)
+static inline __attribute__((always_inline)) bool regi2c_ctrl_ll_bbpll_calibration_is_done(void)
 {
-    REG_CLR_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH);
-    REG_SET_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW);
+    return REG_GET_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_CAL_DONE);
 }
 
 /**
@@ -46,8 +49,8 @@ static inline __attribute__((always_inline)) void regi2c_ctrl_ll_bbpll_calibrati
  */
 static inline void regi2c_ctrl_ll_i2c_saradc_enable(void)
 {
-    CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, ANA_I2C_SAR_FORCE_PD);
-    SET_PERI_REG_MASK(ANA_CONFIG2_REG, ANA_I2C_SAR_FORCE_PU);
+    CLEAR_PERI_REG_MASK(I2C_MST_ANA_CONF1_REG, ANA_I2C_SAR_FORCE_PD);
+    SET_PERI_REG_MASK(I2C_MST_ANA_CONF2_REG, ANA_I2C_SAR_FORCE_PU);
 }
 
 /**
@@ -55,8 +58,8 @@ static inline void regi2c_ctrl_ll_i2c_saradc_enable(void)
  */
 static inline void regi2c_ctrl_ll_i2c_saradc_disable(void)
 {
-    CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, ANA_I2C_SAR_FORCE_PU);
-    SET_PERI_REG_MASK(ANA_CONFIG2_REG, ANA_I2C_SAR_FORCE_PD);
+    CLEAR_PERI_REG_MASK(I2C_MST_ANA_CONF1_REG, ANA_I2C_SAR_FORCE_PU);
+    SET_PERI_REG_MASK(I2C_MST_ANA_CONF2_REG, ANA_I2C_SAR_FORCE_PD);
 }
 
 #ifdef __cplusplus

components/soc/esp32/include/soc/soc.h

@@ -156,6 +156,7 @@
 //Periheral Clock {{
 #define  APB_CLK_FREQ_ROM                            ( 26*1000000 )
 #define  CPU_CLK_FREQ_ROM                            APB_CLK_FREQ_ROM
+#define  CPU_CLK_FREQ_MHZ_BTLD                       (80)               // The cpu clock frequency (in MHz) to set at 2nd stage bootloader system clock configuration
 #define  CPU_CLK_FREQ                                APB_CLK_FREQ       //this may be incorrect, please refer to ESP_DEFAULT_CPU_FREQ_MHZ
 #define  APB_CLK_FREQ                                ( 80*1000000 )       //unit: Hz
 #define  REF_CLK_FREQ                                ( 1000000 )

components/soc/esp32c2/include/soc/soc.h

@@ -143,6 +143,7 @@
 #define  APB_CLK_FREQ_ROM                            ( 40*1000000 )
 #define  CPU_CLK_FREQ_ROM                            APB_CLK_FREQ_ROM
 #define  EFUSE_CLK_FREQ_ROM                          ( 20*1000000)
+#define  CPU_CLK_FREQ_MHZ_BTLD                       (80)           // The cpu clock frequency (in MHz) to set at 2nd stage bootloader system clock configuration
 #define  CPU_CLK_FREQ                                APB_CLK_FREQ
 #define  APB_CLK_FREQ                                ( 40*1000000 )
 #define  REF_CLK_FREQ                                ( 1000000 )

components/soc/esp32c3/include/soc/soc.h

@@ -136,6 +136,7 @@
 #define  APB_CLK_FREQ_ROM                            ( 40*1000000 )
 #define  CPU_CLK_FREQ_ROM                            APB_CLK_FREQ_ROM
 #define  EFUSE_CLK_FREQ_ROM                          ( 20*1000000)
+#define  CPU_CLK_FREQ_MHZ_BTLD                       (80)           // The cpu clock frequency (in MHz) to set at 2nd stage bootloader system clock configuration
 #define  CPU_CLK_FREQ                                APB_CLK_FREQ
 #define  APB_CLK_FREQ                                ( 80*1000000 )
 #define  REF_CLK_FREQ                                ( 1000000 )

components/soc/esp32c6/include/soc/clk_tree_defs.h

@@ -115,9 +115,9 @@ typedef enum {
     SOC_MOD_CLK_RTC_FAST,                      /*!< RTC_FAST_CLK can be sourced from XTAL_D2 or RC_FAST by configuring soc_rtc_fast_clk_src_t */
     SOC_MOD_CLK_RTC_SLOW,                      /*!< RTC_SLOW_CLK can be sourced from RC_SLOW, XTAL32K, RC32K, or OSC_SLOW by configuring soc_rtc_slow_clk_src_t */
     // For digital domain: peripherals, WIFI, BLE
-    SOC_MOD_CLK_PLL_F80M,                      /*!< PLL_F80M_CLK is derived from PLL (w/ CG), and has a fixed frequency of 80MHz */
-    SOC_MOD_CLK_PLL_F160M,                     /*!< PLL_F160M_CLK is derived from PLL (w/ CG), and has a fixed frequency of 160MHz */
-    SOC_MOD_CLK_PLL_F240M,                     /*!< PLL_F240M_CLK is derived from PLL (w/ CG), and has a fixed frequency of 240MHz */
+    SOC_MOD_CLK_PLL_F80M,                      /*!< PLL_F80M_CLK is derived from PLL (clock gating + fixed divider of 6), it has a fixed frequency of 80MHz */
+    SOC_MOD_CLK_PLL_F160M,                     /*!< PLL_F160M_CLK is derived from PLL (clock gating + fixed divider of 3), it has a fixed frequency of 160MHz */
+    SOC_MOD_CLK_PLL_F240M,                     /*!< PLL_F240M_CLK is derived from PLL (clock gating + fixed divider of 2), it has a fixed frequency of 240MHz */
     SOC_MOD_CLK_XTAL32K,                       /*!< XTAL32K_CLK comes from the external 32kHz crystal, passing a clock gating to the peripherals */
     SOC_MOD_CLK_RC_FAST,                       /*!< RC_FAST_CLK comes from the internal 20MHz rc oscillator, passing a clock gating to the peripherals */
     SOC_MOD_CLK_XTAL,                          /*!< XTAL_CLK comes from the external 40MHz crystal */

components/soc/esp32c6/include/soc/pcr_struct.h

@@ -1,5 +1,5 @@
 /**
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
  *
  *  SPDX-License-Identifier: Apache-2.0
  */
@@ -1699,8 +1699,8 @@ typedef union {
 typedef union {
     struct {
         /** clk_32k_sel : R/W; bitpos: [1:0]; default: 0;
-         *  This field indicates which one 32KHz clock will be used by MODEM_SYSTEM and
-         *  timergroup. 0: OSC32K(default), 1: XTAL32K, 2/3: 32KHz from pad GPIO0.
+         *  This field indicates which one 32KHz clock will be used by timergroup.
+         *  0: OSC32K(default), 1: XTAL32K, 2/3: 32KHz from pad GPIO0.
          */
         uint32_t clk_32k_sel:2;
         uint32_t reserved_2:30;

components/soc/esp32c6/include/soc/rtc.h

@@ -40,8 +40,6 @@ extern "C" {
  * The functions are loosely split into the following groups:
  * - rtc_clk: clock switching, calibration
  * - rtc_time: reading RTC counter, conversion between counter values and time
- * - rtc_sleep: entry into sleep modes
- * - rtc_init: initialization
  */
 
 #define MHZ (1000000)
@@ -198,32 +196,6 @@ typedef struct {
     .rc32k_dfreq = RTC_CNTL_RC32K_DFREQ_DEFAULT, \
 }
 
-typedef struct {
-    uint16_t wifi_powerup_cycles : 7;
-    uint16_t wifi_wait_cycles : 9;
-    uint16_t bt_powerup_cycles : 7;
-    uint16_t bt_wait_cycles : 9;
-    uint16_t cpu_top_powerup_cycles : 7;
-    uint16_t cpu_top_wait_cycles : 9;
-    uint16_t dg_wrap_powerup_cycles : 7;
-    uint16_t dg_wrap_wait_cycles : 9;
-    uint16_t dg_peri_powerup_cycles : 7;
-    uint16_t dg_peri_wait_cycles : 9;
-} rtc_init_config_t;
-
-#define RTC_INIT_CONFIG_DEFAULT() { \
-    .wifi_powerup_cycles = OTHER_BLOCKS_POWERUP, \
-    .wifi_wait_cycles = OTHER_BLOCKS_WAIT, \
-    .bt_powerup_cycles = OTHER_BLOCKS_POWERUP, \
-    .bt_wait_cycles = OTHER_BLOCKS_WAIT, \
-    .cpu_top_powerup_cycles = OTHER_BLOCKS_POWERUP, \
-    .cpu_top_wait_cycles = OTHER_BLOCKS_WAIT, \
-    .dg_wrap_powerup_cycles = OTHER_BLOCKS_POWERUP, \
-    .dg_wrap_wait_cycles = OTHER_BLOCKS_WAIT, \
-    .dg_peri_powerup_cycles = OTHER_BLOCKS_POWERUP, \
-    .dg_peri_wait_cycles = OTHER_BLOCKS_WAIT, \
-}
-
 /**
  * Initialize clocks and set CPU frequency
  *
@@ -314,9 +286,10 @@ soc_rtc_slow_clk_src_t rtc_clk_slow_src_get(void);
 /**
  * @brief Get the approximate frequency of RTC_SLOW_CLK, in Hz
  *
- * - if SOC_RTC_SLOW_CLK_SRC_RC_SLOW is selected, returns ~150000
+ * - if SOC_RTC_SLOW_CLK_SRC_RC_SLOW is selected, returns 136000
  * - if SOC_RTC_SLOW_CLK_SRC_XTAL32K is selected, returns 32768
- * - if SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256 is selected, returns ~68000
+ * - if SOC_RTC_SLOW_CLK_SRC_RC32K is selected, returns 32768
+ * - if SOC_RTC_SLOW_CLK_SRC_OSC_SLOW is selected, returns 32768
  *
  * rtc_clk_cal function can be used to get more precise value by comparing
  * RTC_SLOW_CLK frequency to the frequency of main XTAL.
@@ -515,49 +488,6 @@ bool rtc_dig_8m_enabled(void);
 uint32_t rtc_clk_freq_cal(uint32_t cal_val);
 
 
-
-
-/**
- * RTC power and clock control initialization settings
- */
-typedef struct {
-    uint32_t ck8m_wait : 8;         //!< Number of rtc_fast_clk cycles to wait for 8M clock to be ready
-    uint32_t xtal_wait : 8;         //!< Number of rtc_fast_clk cycles to wait for XTAL clock to be ready
-    uint32_t pll_wait : 8;          //!< Number of rtc_fast_clk cycles to wait for PLL to be ready
-    uint32_t clkctl_init : 1;       //!< Perform clock control related initialization
-    uint32_t pwrctl_init : 1;       //!< Perform power control related initialization
-    uint32_t rtc_dboost_fpd : 1;    //!< Force power down RTC_DBOOST
-    uint32_t xtal_fpu : 1;
-    uint32_t bbpll_fpu : 1;
-    uint32_t cpu_waiti_clk_gate : 1;
-    uint32_t cali_ocode : 1;        //!< Calibrate Ocode to make bangap voltage more precise.
-} rtc_config_t;
-
-/**
- * Default initializer of rtc_config_t.
- *
- * This initializer sets all fields to "reasonable" values (e.g. suggested for
- * production use).
- */
-#define RTC_CONFIG_DEFAULT() {\
-    .ck8m_wait = RTC_CNTL_CK8M_WAIT_DEFAULT, \
-    .xtal_wait = RTC_CNTL_XTL_BUF_WAIT_DEFAULT, \
-    .pll_wait  = RTC_CNTL_PLL_BUF_WAIT_DEFAULT, \
-    .clkctl_init = 1, \
-    .pwrctl_init = 1, \
-    .rtc_dboost_fpd = 1, \
-    .xtal_fpu = 0, \
-    .bbpll_fpu = 0, \
-    .cpu_waiti_clk_gate = 1, \
-    .cali_ocode = 0\
-}
-
-/**
- * Initialize RTC clock and power control related functions
- * @param cfg configuration options as rtc_config_t
- */
-void rtc_init(rtc_config_t cfg);
-
 // -------------------------- CLOCK TREE DEFS ALIAS ----------------------------
 // **WARNING**: The following are only for backwards compatibility.
 // Please use the declarations in soc/clk_tree_defs.h instead.

components/soc/esp32c6/include/soc/soc.h

@@ -139,6 +139,7 @@
 #define  APB_CLK_FREQ_ROM                            ( 40*1000000 )
 #define  CPU_CLK_FREQ_ROM                            APB_CLK_FREQ_ROM
 #define  EFUSE_CLK_FREQ_ROM                          ( 20*1000000)
+#define  CPU_CLK_FREQ_MHZ_BTLD                       (80)               // The cpu clock frequency (in MHz) to set at 2nd stage bootloader system clock configuration
 #define  CPU_CLK_FREQ                                APB_CLK_FREQ
 #define  APB_CLK_FREQ                                ( 40*1000000 )
 #define  MODEM_APB_CLK_FREQ                          ( 80*1000000 )

components/soc/esp32h2/include/modem/modem_syscon_reg.h

@@ -0,0 +1,290 @@
+/**
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ *//*description: */
+#pragma once
+
+#include <stdint.h>
+#include "modem/reg_base.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define MODEM_SYSCON_TEST_CONF_REG          (DR_REG_MODEM_SYSCON_BASE + 0x0)
+/* MODEM_SYSCON_CLK_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define MODEM_SYSCON_CLK_EN    (BIT(0))
+#define MODEM_SYSCON_CLK_EN_M  (BIT(0))
+#define MODEM_SYSCON_CLK_EN_V  0x1
+#define MODEM_SYSCON_CLK_EN_S  0
+
+#define MODEM_SYSCON_CLK_CONF_REG          (DR_REG_MODEM_SYSCON_BASE + 0x4)
+/* MODEM_SYSCON_CLK_DATA_DUMP_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: .*/
+#define MODEM_SYSCON_CLK_DATA_DUMP_EN    (BIT(31))
+#define MODEM_SYSCON_CLK_DATA_DUMP_EN_M  (BIT(31))
+#define MODEM_SYSCON_CLK_DATA_DUMP_EN_V  0x1
+#define MODEM_SYSCON_CLK_DATA_DUMP_EN_S  31
+/* MODEM_SYSCON_CLK_BLE_TIMER_EN : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: .*/
+#define MODEM_SYSCON_CLK_BLE_TIMER_EN    (BIT(30))
+#define MODEM_SYSCON_CLK_BLE_TIMER_EN_M  (BIT(30))
+#define MODEM_SYSCON_CLK_BLE_TIMER_EN_V  0x1
+#define MODEM_SYSCON_CLK_BLE_TIMER_EN_S  30
+/* MODEM_SYSCON_CLK_BLE_TIMER_APB_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: .*/
+#define MODEM_SYSCON_CLK_BLE_TIMER_APB_EN    (BIT(29))
+#define MODEM_SYSCON_CLK_BLE_TIMER_APB_EN_M  (BIT(29))
+#define MODEM_SYSCON_CLK_BLE_TIMER_APB_EN_V  0x1
+#define MODEM_SYSCON_CLK_BLE_TIMER_APB_EN_S  29
+/* MODEM_SYSCON_CLK_MODEM_SEC_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: .*/
+#define MODEM_SYSCON_CLK_MODEM_SEC_EN    (BIT(28))
+#define MODEM_SYSCON_CLK_MODEM_SEC_EN_M  (BIT(28))
+#define MODEM_SYSCON_CLK_MODEM_SEC_EN_V  0x1
+#define MODEM_SYSCON_CLK_MODEM_SEC_EN_S  28
+/* MODEM_SYSCON_CLK_MODEM_SEC_APB_EN : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: .*/
+#define MODEM_SYSCON_CLK_MODEM_SEC_APB_EN    (BIT(27))
+#define MODEM_SYSCON_CLK_MODEM_SEC_APB_EN_M  (BIT(27))
+#define MODEM_SYSCON_CLK_MODEM_SEC_APB_EN_V  0x1
+#define MODEM_SYSCON_CLK_MODEM_SEC_APB_EN_S  27
+/* MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: .*/
+#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN    (BIT(26))
+#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN_M  (BIT(26))
+#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN_V  0x1
+#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN_S  26
+/* MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN : R/W ;bitpos:[25] ;default: 1'b0 ; */
+/*description: .*/
+#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN    (BIT(25))
+#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN_M  (BIT(25))
+#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN_V  0x1
+#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN_S  25
+/* MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: .*/
+#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN    (BIT(24))
+#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN_M  (BIT(24))
+#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN_V  0x1
+#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN_S  24
+/* MODEM_SYSCON_CLK_ZB_MAC_EN : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: .*/
+#define MODEM_SYSCON_CLK_ZB_MAC_EN    (BIT(23))
+#define MODEM_SYSCON_CLK_ZB_MAC_EN_M  (BIT(23))
+#define MODEM_SYSCON_CLK_ZB_MAC_EN_V  0x1
+#define MODEM_SYSCON_CLK_ZB_MAC_EN_S  23
+/* MODEM_SYSCON_CLK_ZB_APB_EN : R/W ;bitpos:[22] ;default: 1'b0 ; */
+/*description: .*/
+#define MODEM_SYSCON_CLK_ZB_APB_EN    (BIT(22))
+#define MODEM_SYSCON_CLK_ZB_APB_EN_M  (BIT(22))
+#define MODEM_SYSCON_CLK_ZB_APB_EN_V  0x1
+#define MODEM_SYSCON_CLK_ZB_APB_EN_S  22
+/* MODEM_SYSCON_CLK_ETM_EN : R/W ;bitpos:[21] ;default: 1'b0 ; */
+/*description: .*/
+#define MODEM_SYSCON_CLK_ETM_EN    (BIT(21))
+#define MODEM_SYSCON_CLK_ETM_EN_M  (BIT(21))
+#define MODEM_SYSCON_CLK_ETM_EN_V  0x1
+#define MODEM_SYSCON_CLK_ETM_EN_S  21
+
+#define MODEM_SYSCON_CLK_CONF_FORCE_ON_REG          (DR_REG_MODEM_SYSCON_BASE + 0x8)
+/* MODEM_SYSCON_CLK_DATA_DUMP_FO : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: .*/
+#define MODEM_SYSCON_CLK_DATA_DUMP_FO    (BIT(31))
+#define MODEM_SYSCON_CLK_DATA_DUMP_FO_M  (BIT(31))
+#define MODEM_SYSCON_CLK_DATA_DUMP_FO_V  0x1
+#define MODEM_SYSCON_CLK_DATA_DUMP_FO_S  31
+/* MODEM_SYSCON_CLK_BLE_TIMER_FO : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: .*/
+#define MODEM_SYSCON_CLK_BLE_TIMER_FO    (BIT(30))
+#define MODEM_SYSCON_CLK_BLE_TIMER_FO_M  (BIT(30))
+#define MODEM_SYSCON_CLK_BLE_TIMER_FO_V  0x1
+#define MODEM_SYSCON_CLK_BLE_TIMER_FO_S  30
+/* MODEM_SYSCON_CLK_MODEM_SEC_FO : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: .*/
+#define MODEM_SYSCON_CLK_MODEM_SEC_FO    (BIT(29))
+#define MODEM_SYSCON_CLK_MODEM_SEC_FO_M  (BIT(29))
+#define MODEM_SYSCON_CLK_MODEM_SEC_FO_V  0x1
+#define MODEM_SYSCON_CLK_MODEM_SEC_FO_S  29
+/* MODEM_SYSCON_CLK_ZB_FO : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: .*/
+#define MODEM_SYSCON_CLK_ZB_FO    (BIT(24))
+#define MODEM_SYSCON_CLK_ZB_FO_M  (BIT(24))
+#define MODEM_SYSCON_CLK_ZB_FO_V  0x1
+#define MODEM_SYSCON_CLK_ZB_FO_S  24
+/* MODEM_SYSCON_CLK_ETM_FO : R/W ;bitpos:[22] ;default: 1'b0 ; */
+/*description: .*/
+#define MODEM_SYSCON_CLK_ETM_FO    (BIT(22))
+#define MODEM_SYSCON_CLK_ETM_FO_M  (BIT(22))
+#define MODEM_SYSCON_CLK_ETM_FO_V  0x1
+#define MODEM_SYSCON_CLK_ETM_FO_S  22
+
+#define MODEM_SYSCON_MODEM_RST_CONF_REG          (DR_REG_MODEM_SYSCON_BASE + 0xC)
+/* MODEM_SYSCON_RST_DATA_DUMP : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: .*/
+#define MODEM_SYSCON_RST_DATA_DUMP    (BIT(31))
+#define MODEM_SYSCON_RST_DATA_DUMP_M  (BIT(31))
+#define MODEM_SYSCON_RST_DATA_DUMP_V  0x1
+#define MODEM_SYSCON_RST_DATA_DUMP_S  31
+/* MODEM_SYSCON_RST_BLE_TIMER : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: .*/
+#define MODEM_SYSCON_RST_BLE_TIMER    (BIT(30))
+#define MODEM_SYSCON_RST_BLE_TIMER_M  (BIT(30))
+#define MODEM_SYSCON_RST_BLE_TIMER_V  0x1
+#define MODEM_SYSCON_RST_BLE_TIMER_S  30
+/* MODEM_SYSCON_RST_MODEM_SEC : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: .*/
+#define MODEM_SYSCON_RST_MODEM_SEC    (BIT(29))
+#define MODEM_SYSCON_RST_MODEM_SEC_M  (BIT(29))
+#define MODEM_SYSCON_RST_MODEM_SEC_V  0x1
+#define MODEM_SYSCON_RST_MODEM_SEC_S  29
+/* MODEM_SYSCON_RST_MODEM_BAH : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: .*/
+#define MODEM_SYSCON_RST_MODEM_BAH    (BIT(27))
+#define MODEM_SYSCON_RST_MODEM_BAH_M  (BIT(27))
+#define MODEM_SYSCON_RST_MODEM_BAH_V  0x1
+#define MODEM_SYSCON_RST_MODEM_BAH_S  27
+/* MODEM_SYSCON_RST_MODEM_CCM : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: .*/
+#define MODEM_SYSCON_RST_MODEM_CCM    (BIT(26))
+#define MODEM_SYSCON_RST_MODEM_CCM_M  (BIT(26))
+#define MODEM_SYSCON_RST_MODEM_CCM_V  0x1
+#define MODEM_SYSCON_RST_MODEM_CCM_S  26
+/* MODEM_SYSCON_RST_MODEM_ECB : R/W ;bitpos:[25] ;default: 1'b0 ; */
+/*description: .*/
+#define MODEM_SYSCON_RST_MODEM_ECB    (BIT(25))
+#define MODEM_SYSCON_RST_MODEM_ECB_M  (BIT(25))
+#define MODEM_SYSCON_RST_MODEM_ECB_V  0x1
+#define MODEM_SYSCON_RST_MODEM_ECB_S  25
+/* MODEM_SYSCON_RST_ZBMAC : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: .*/
+#define MODEM_SYSCON_RST_ZBMAC    (BIT(24))
+#define MODEM_SYSCON_RST_ZBMAC_M  (BIT(24))
+#define MODEM_SYSCON_RST_ZBMAC_V  0x1
+#define MODEM_SYSCON_RST_ZBMAC_S  24
+/* MODEM_SYSCON_RST_ETM : R/W ;bitpos:[22] ;default: 1'b0 ; */
+/*description: .*/
+#define MODEM_SYSCON_RST_ETM    (BIT(22))
+#define MODEM_SYSCON_RST_ETM_M  (BIT(22))
+#define MODEM_SYSCON_RST_ETM_V  0x1
+#define MODEM_SYSCON_RST_ETM_S  22
+/* MODEM_SYSCON_RST_BTBB : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: .*/
+#define MODEM_SYSCON_RST_BTBB    (BIT(18))
+#define MODEM_SYSCON_RST_BTBB_M  (BIT(18))
+#define MODEM_SYSCON_RST_BTBB_V  0x1
+#define MODEM_SYSCON_RST_BTBB_S  18
+/* MODEM_SYSCON_RST_BTBB_APB : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: .*/
+#define MODEM_SYSCON_RST_BTBB_APB    (BIT(17))
+#define MODEM_SYSCON_RST_BTBB_APB_M  (BIT(17))
+#define MODEM_SYSCON_RST_BTBB_APB_V  0x1
+#define MODEM_SYSCON_RST_BTBB_APB_S  17
+/* MODEM_SYSCON_RST_BTMAC : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: .*/
+#define MODEM_SYSCON_RST_BTMAC    (BIT(16))
+#define MODEM_SYSCON_RST_BTMAC_M  (BIT(16))
+#define MODEM_SYSCON_RST_BTMAC_V  0x1
+#define MODEM_SYSCON_RST_BTMAC_S  16
+/* MODEM_SYSCON_RST_BTMAC_APB : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: .*/
+#define MODEM_SYSCON_RST_BTMAC_APB    (BIT(15))
+#define MODEM_SYSCON_RST_BTMAC_APB_M  (BIT(15))
+#define MODEM_SYSCON_RST_BTMAC_APB_V  0x1
+#define MODEM_SYSCON_RST_BTMAC_APB_S  15
+/* MODEM_SYSCON_RST_FE : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: .*/
+#define MODEM_SYSCON_RST_FE    (BIT(14))
+#define MODEM_SYSCON_RST_FE_M  (BIT(14))
+#define MODEM_SYSCON_RST_FE_V  0x1
+#define MODEM_SYSCON_RST_FE_S  14
+
+#define MODEM_SYSCON_CLK_CONF1_REG          (DR_REG_MODEM_SYSCON_BASE + 0x10)
+/* MODEM_SYSCON_CLK_BT_EN : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: .*/
+#define MODEM_SYSCON_CLK_BT_EN    (BIT(18))
+#define MODEM_SYSCON_CLK_BT_EN_M  (BIT(18))
+#define MODEM_SYSCON_CLK_BT_EN_V  0x1
+#define MODEM_SYSCON_CLK_BT_EN_S  18
+/* MODEM_SYSCON_CLK_BT_APB_EN : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: .*/
+#define MODEM_SYSCON_CLK_BT_APB_EN    (BIT(17))
+#define MODEM_SYSCON_CLK_BT_APB_EN_M  (BIT(17))
+#define MODEM_SYSCON_CLK_BT_APB_EN_V  0x1
+#define MODEM_SYSCON_CLK_BT_APB_EN_S  17
+/* MODEM_SYSCON_CLK_FE_APB_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: .*/
+#define MODEM_SYSCON_CLK_FE_APB_EN    (BIT(16))
+#define MODEM_SYSCON_CLK_FE_APB_EN_M  (BIT(16))
+#define MODEM_SYSCON_CLK_FE_APB_EN_V  0x1
+#define MODEM_SYSCON_CLK_FE_APB_EN_S  16
+/* MODEM_SYSCON_CLK_FE_ADC_EN : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: .*/
+#define MODEM_SYSCON_CLK_FE_ADC_EN    (BIT(15))
+#define MODEM_SYSCON_CLK_FE_ADC_EN_M  (BIT(15))
+#define MODEM_SYSCON_CLK_FE_ADC_EN_V  0x1
+#define MODEM_SYSCON_CLK_FE_ADC_EN_S  15
+/* MODEM_SYSCON_CLK_FE_SDM_EN : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: .*/
+#define MODEM_SYSCON_CLK_FE_SDM_EN    (BIT(14))
+#define MODEM_SYSCON_CLK_FE_SDM_EN_M  (BIT(14))
+#define MODEM_SYSCON_CLK_FE_SDM_EN_V  0x1
+#define MODEM_SYSCON_CLK_FE_SDM_EN_S  14
+/* MODEM_SYSCON_CLK_FE_32M_EN : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: .*/
+#define MODEM_SYSCON_CLK_FE_32M_EN    (BIT(13))
+#define MODEM_SYSCON_CLK_FE_32M_EN_M  (BIT(13))
+#define MODEM_SYSCON_CLK_FE_32M_EN_V  0x1
+#define MODEM_SYSCON_CLK_FE_32M_EN_S  13
+/* MODEM_SYSCON_CLK_FE_16M_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: .*/
+#define MODEM_SYSCON_CLK_FE_16M_EN    (BIT(12))
+#define MODEM_SYSCON_CLK_FE_16M_EN_M  (BIT(12))
+#define MODEM_SYSCON_CLK_FE_16M_EN_V  0x1
+#define MODEM_SYSCON_CLK_FE_16M_EN_S  12
+
+#define MODEM_SYSCON_CLK_CONF1_FORCE_ON_REG          (DR_REG_MODEM_SYSCON_BASE + 0x14)
+/* MODEM_SYSCON_CLK_BT_FO : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: .*/
+#define MODEM_SYSCON_CLK_BT_FO    (BIT(18))
+#define MODEM_SYSCON_CLK_BT_FO_M  (BIT(18))
+#define MODEM_SYSCON_CLK_BT_FO_V  0x1
+#define MODEM_SYSCON_CLK_BT_FO_S  18
+/* MODEM_SYSCON_CLK_FE_FO : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: .*/
+#define MODEM_SYSCON_CLK_FE_FO    (BIT(16))
+#define MODEM_SYSCON_CLK_FE_FO_M  (BIT(16))
+#define MODEM_SYSCON_CLK_FE_FO_V  0x1
+#define MODEM_SYSCON_CLK_FE_FO_S  16
+
+#define MODEM_SYSCON_MEM_CONF_REG          (DR_REG_MODEM_SYSCON_BASE + 0x18)
+/* MODEM_SYSCON_MODEM_MEM_RA : R/W ;bitpos:[7:6] ;default: 2'h0 ; */
+/*description: .*/
+#define MODEM_SYSCON_MODEM_MEM_RA    0x00000003
+#define MODEM_SYSCON_MODEM_MEM_RA_M  ((MODEM_SYSCON_MODEM_MEM_RA_V)<<(MODEM_SYSCON_MODEM_MEM_RA_S))
+#define MODEM_SYSCON_MODEM_MEM_RA_V  0x3
+#define MODEM_SYSCON_MODEM_MEM_RA_S  6
+/* MODEM_SYSCON_MODEM_MEM_WA : R/W ;bitpos:[5:3] ;default: 3'h4 ; */
+/*description: .*/
+#define MODEM_SYSCON_MODEM_MEM_WA    0x00000007
+#define MODEM_SYSCON_MODEM_MEM_WA_M  ((MODEM_SYSCON_MODEM_MEM_WA_V)<<(MODEM_SYSCON_MODEM_MEM_WA_S))
+#define MODEM_SYSCON_MODEM_MEM_WA_V  0x7
+#define MODEM_SYSCON_MODEM_MEM_WA_S  3
+/* MODEM_SYSCON_MODEM_MEM_WP : R/W ;bitpos:[2:0] ;default: 3'h0 ; */
+/*description: .*/
+#define MODEM_SYSCON_MODEM_MEM_WP    0x00000007
+#define MODEM_SYSCON_MODEM_MEM_WP_M  ((MODEM_SYSCON_MODEM_MEM_WP_V)<<(MODEM_SYSCON_MODEM_MEM_WP_S))
+#define MODEM_SYSCON_MODEM_MEM_WP_V  0x7
+#define MODEM_SYSCON_MODEM_MEM_WP_S  0
+
+#define MODEM_SYSCON_DATE_REG          (DR_REG_MODEM_SYSCON_BASE + 0x1C)
+/* MODEM_SYSCON_DATE : R/W ;bitpos:[27:0] ;default: 28'h2208300 ; */
+/*description: .*/
+#define MODEM_SYSCON_DATE    0x0FFFFFFF
+#define MODEM_SYSCON_DATE_M  ((MODEM_SYSCON_DATE_V)<<(MODEM_SYSCON_DATE_S))
+#define MODEM_SYSCON_DATE_V  0xFFFFFFF
+#define MODEM_SYSCON_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32h2/include/modem/reg_base.h

@@ -1,8 +1,9 @@
-/**
+/*
  * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
  *
- *  SPDX-License-Identifier: Apache-2.0
+ * SPDX-License-Identifier: Apache-2.0
  */
 
 #pragma once
+#define DR_REG_MODEM_SYSCON_BASE  0x600A5400
 #define DR_REG_MODEM_LPCON_BASE   0x600AD000

components/soc/esp32h2/include/soc/Kconfig.soc_caps.in

@@ -51,10 +51,6 @@ config SOC_EFUSE_KEY_PURPOSE_FIELD
     bool
     default y
 
-config SOC_EFUSE_HAS_EFUSE_RST_BUG
-    bool
-    default y
-
 config SOC_RTC_FAST_MEM_SUPPORTED
     bool
     default y
@@ -119,6 +115,10 @@ config SOC_APM_SUPPORTED
     bool
     default y
 
+config SOC_PMU_SUPPORTED
+    bool
+    default y
+
 config SOC_XTAL_SUPPORT_32M
     bool
     default y
@@ -367,6 +367,10 @@ config SOC_I2C_SUPPORT_XTAL
     bool
     default y
 
+config SOC_I2C_SUPPORT_RTC
+    bool
+    default y
+
 config SOC_I2S_NUM
     int
     default 1
@@ -527,6 +531,10 @@ config SOC_RMT_SUPPORT_XTAL
     bool
     default y
 
+config SOC_RMT_SUPPORT_RC_FAST
+    bool
+    default y
+
 config SOC_MCPWM_GROUPS
     int
     default 1
@@ -775,6 +783,10 @@ config SOC_TIMER_GROUP_SUPPORT_XTAL
     bool
     default y
 
+config SOC_TIMER_GROUP_SUPPORT_RC_FAST
+    bool
+    default y
+
 config SOC_TIMER_GROUP_TOTAL_TIMERS
     int
     default 2
@@ -931,6 +943,10 @@ config SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY
     bool
     default y
 
+config SOC_CLK_RC_FAST_SUPPORT_CALIBRATION
+    bool
+    default y
+
 config SOC_CLK_XTAL32K_SUPPORTED
     bool
     default y
@@ -943,6 +959,10 @@ config SOC_CLK_RC32K_SUPPORTED
     bool
     default y
 
+config SOC_CLK_LP_FAST_SUPPORT_LP_PLL
+    bool
+    default y
+
 config SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC
     bool
     default y

components/soc/esp32h2/include/soc/clk_tree_defs.h

@@ -5,8 +5,6 @@
  */
 #pragma once
 
-#include "sdkconfig.h" // ESP32H2 TODO: IDF-5973
-
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -45,8 +43,8 @@ extern "C" {
  *    OSC_SLOW_CLK can also be calibrated to get its exact frequency.
  */
 
-/* With the default value of CK8M_DFREQ = 600, RC_FAST clock frequency is 7 MHz +/- 7% */
-#define SOC_CLK_RC_FAST_FREQ_APPROX         7000000                             /*!< Approximate RC_FAST_CLK frequency in Hz */
+/* With the default value of CK8M_DFREQ = 860, RC_FAST clock frequency is 8.5 MHz +/- 7% */
+#define SOC_CLK_RC_FAST_FREQ_APPROX         8500000                             /*!< Approximate RC_FAST_CLK frequency in Hz */
 #define SOC_CLK_RC_SLOW_FREQ_APPROX         136000                              /*!< Approximate RC_SLOW_CLK frequency in Hz */
 #define SOC_CLK_RC32K_FREQ_APPROX           32768                               /*!< Approximate RC32K_CLK frequency in Hz */
 #define SOC_CLK_XTAL32K_FREQ_APPROX         32768                               /*!< Approximate XTAL32K_CLK frequency in Hz */
@@ -74,9 +72,9 @@ typedef enum {
  */
 typedef enum {
     SOC_CPU_CLK_SRC_XTAL = 0,              /*!< Select XTAL_CLK as CPU_CLK source */
-    SOC_CPU_CLK_SRC_PLL = 1,               /*!< Select PLL_CLK as CPU_CLK source (PLL_CLK is the output of 32MHz crystal oscillator frequency multiplier, 96MHz) */
+    SOC_CPU_CLK_SRC_PLL = 1,               /*!< Select PLL_CLK as CPU_CLK source (PLL_CLK is one of the outputs of 32MHz crystal oscillator frequency multiplier, 96MHz) */
     SOC_CPU_CLK_SRC_RC_FAST = 2,           /*!< Select RC_FAST_CLK as CPU_CLK source */
-    SOC_CPU_CLK_SRC_PLL2 = 3,              /*!< Select PLL2_CLK as CPU_CLK source (PLL2_CLK is the output of 32MHz crystal oscillator frequency multiplier, 64MHz) */
+    SOC_CPU_CLK_SRC_FLASH_PLL = 3,         /*!< Select FLASH_PLL_CLK as CPU_CLK source (FLASH_PLL_CLK is the other output of 32MHz crystal oscillator frequency multiplier, 64MHz) */
     SOC_CPU_CLK_SRC_INVALID,               /*!< Invalid CPU_CLK source */
 } soc_cpu_clk_src_t;
 
@@ -87,8 +85,8 @@ typedef enum {
 typedef enum {
     SOC_RTC_SLOW_CLK_SRC_RC_SLOW = 0,      /*!< Select RC_SLOW_CLK as RTC_SLOW_CLK source */
     SOC_RTC_SLOW_CLK_SRC_XTAL32K = 1,      /*!< Select XTAL32K_CLK as RTC_SLOW_CLK source */
-    SOC_RTC_SLOW_CLK_SRC_OSC_SLOW = 2,     /*!< Select OSC_SLOW_CLK (external slow clock) as RTC_SLOW_CLK source */
-    SOC_RTC_SLOW_CLK_SRC_RC32K = 3,        /*!< Select RC32K_CLK as RTC_SLOW_CLK source */
+    SOC_RTC_SLOW_CLK_SRC_RC32K = 2,        /*!< Select RC32K_CLK as RTC_SLOW_CLK source */
+    SOC_RTC_SLOW_CLK_SRC_OSC_SLOW = 3,     /*!< Select OSC_SLOW_CLK (external slow clock) as RTC_SLOW_CLK source */
     SOC_RTC_SLOW_CLK_SRC_INVALID,          /*!< Invalid RTC_SLOW_CLK source */
 } soc_rtc_slow_clk_src_t;
 
@@ -100,9 +98,20 @@ typedef enum {
     SOC_RTC_FAST_CLK_SRC_RC_FAST = 0,      /*!< Select RC_FAST_CLK as RTC_FAST_CLK source */
     SOC_RTC_FAST_CLK_SRC_XTAL_D2 = 1,      /*!< Select XTAL_D2_CLK (may referred as XTAL_CLK_DIV_2) as RTC_FAST_CLK source */
     SOC_RTC_FAST_CLK_SRC_XTAL_DIV = SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< Alias name for `SOC_RTC_FAST_CLK_SRC_XTAL_D2` */
+    SOC_RTC_FAST_CLK_SRC_LP_PLL = 2,       /*!< Select LP_PLL_CLK as RTC_FAST_CLK source (LP_PLL_CLK is a 8MHz clock sourced from RC32K or XTAL32K)*/
     SOC_RTC_FAST_CLK_SRC_INVALID,          /*!< Invalid RTC_FAST_CLK source */
 } soc_rtc_fast_clk_src_t;
 
+/**
+ * @brief LP_PLL_CLK mux inputs, which are the supported clock sources for the LP_PLL_CLK
+ * @note Enum values are matched with the register field values on purpose
+ */
+typedef enum {
+    SOC_LP_PLL_CLK_SRC_RC32K = 0,          /*!< Select RC32K_CLK as LP_PLL_CLK source */
+    SOC_LP_PLL_CLK_SRC_XTAL32K = 1,        /*!< Select XTAL32K_CLK as LP_PLL_CLK source */
+    SOC_LP_PLL_CLK_SRC_INVALID,            /*!< Invalid LP_PLL_CLK source */
+} soc_lp_pll_clk_src_t;
+
 // Naming convention: SOC_MOD_CLK_{[upstream]clock_name}_[attr]
 // {[upstream]clock_name}: XTAL, (BB)PLL, etc.
 // [attr] - optional: FAST, SLOW, D<divider>, F<freq>
@@ -118,12 +127,12 @@ typedef enum {
     SOC_MOD_CLK_RTC_FAST,                      /*!< RTC_FAST_CLK can be sourced from XTAL_D2 or RC_FAST by configuring soc_rtc_fast_clk_src_t */
     SOC_MOD_CLK_RTC_SLOW,                      /*!< RTC_SLOW_CLK can be sourced from RC_SLOW, XTAL32K, OSC_SLOW, or RC32K by configuring soc_rtc_slow_clk_src_t */
     // For digital domain: peripherals, WIFI, BLE
-    SOC_MOD_CLK_PLL_F48M,                      /*!< PLL_F48M_CLK is derived from PLL (w/ CG), and has a fixed frequency of 48MHz */
-    SOC_MOD_CLK_PLL_F64M,                      /*!< PLL_F64M_CLK is derived from PLL2 (w/ CG), and has a fixed frequency of 64MHz */
-    SOC_MOD_CLK_PLL_F96M,                      /*!< PLL_F96M_CLK is derived from PLL (w/ CG), and has a fixed frequency of 96MHz */
+    SOC_MOD_CLK_PLL_F48M,                      /*!< PLL_F48M_CLK is derived from PLL (clock gating + fixed divider of 2), it has a fixed frequency of 48MHz */
+    SOC_MOD_CLK_PLL_F64M,                      /*!< PLL_F64M_CLK is derived from FLASH_PLL (clock gating), it has a fixed frequency of 64MHz */
+    SOC_MOD_CLK_PLL_F96M,                      /*!< PLL_F96M_CLK is derived from PLL (clock gating), it has a fixed frequency of 96MHz */
     SOC_MOD_CLK_XTAL32K,                       /*!< XTAL32K_CLK comes from the external 32kHz crystal, passing a clock gating to the peripherals */
     SOC_MOD_CLK_RC_FAST,                       /*!< RC_FAST_CLK comes from the internal 8MHz rc oscillator, passing a clock gating to the peripherals */
-    SOC_MOD_CLK_XTAL,                          /*!< XTAL_CLK comes from the external 40MHz crystal */
+    SOC_MOD_CLK_XTAL,                          /*!< XTAL_CLK comes from the external 32MHz crystal */
     SOC_MOD_CLK_INVALID,                       /*!< Indication of the end of the available module clock sources */
 } soc_module_clk_t;
 
@@ -152,11 +161,7 @@ typedef enum {
  * }
  * @endcode
  */
-#if CONFIG_IDF_ENV_FPGA
-#define SOC_GPTIMER_CLKS {SOC_MOD_CLK_XTAL}
-#else
 #define SOC_GPTIMER_CLKS {SOC_MOD_CLK_PLL_F48M, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_XTAL}
-#endif
 
 /**
  * @brief Type of GPTimer clock source
@@ -165,11 +170,7 @@ typedef enum {
     GPTIMER_CLK_SRC_PLL_F48M = SOC_MOD_CLK_PLL_F48M, /*!< Select PLL_F48M as the source clock */
     GPTIMER_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST,   /*!< Select RC_FAST as the source clock */
     GPTIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,         /*!< Select XTAL as the source clock */
-#if CONFIG_IDF_ENV_FPGA
-    GPTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL,      /*!< Select XTAL as the default choice */
-#else
     GPTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F48M,  /*!< Select PLL_F48M as the default choice */
-#endif
 } soc_periph_gptimer_clk_src_t;
 
 /**
@@ -178,11 +179,7 @@ typedef enum {
 typedef enum {
     TIMER_SRC_CLK_PLL_F48M = SOC_MOD_CLK_PLL_F48M,     /*!< Timer group clock source is PLL_F48M */
     TIMER_SRC_CLK_XTAL = SOC_MOD_CLK_XTAL,             /*!< Timer group clock source is XTAL */
-#if CONFIG_IDF_ENV_FPGA
-    TIMER_SRC_CLK_DEFAULT = SOC_MOD_CLK_XTAL,          /*!< Timer group clock source default choice is XTAL */
-#else
     TIMER_SRC_CLK_DEFAULT = SOC_MOD_CLK_PLL_F48M,      /*!< Timer group clock source default choice is PLL_F48M */
-#endif
 } soc_periph_tg_clk_src_legacy_t;
 
 //////////////////////////////////////////////////RMT///////////////////////////////////////////////////////////////////
@@ -190,11 +187,7 @@ typedef enum {
 /**
  * @brief Array initializer for all supported clock sources of RMT
  */
-#if CONFIG_IDF_ENV_FPGA
-#define SOC_RMT_CLKS {SOC_MOD_CLK_XTAL}
-#else
 #define SOC_RMT_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST}
-#endif
 
 /**
  * @brief Type of RMT clock source
@@ -254,11 +247,7 @@ typedef enum {
 typedef enum {
     MCPWM_TIMER_CLK_SRC_PLL96M = SOC_MOD_CLK_PLL_F96M,   /*!< Select PLL_F96M as the source clock */
     MCPWM_TIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,         /*!< Select XTAL as the source clock */
-#if CONFIG_IDF_ENV_FPGA
-    MCPWM_TIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL,      /*!< Select XTAL as the default clock choice */
-#else
     MCPWM_TIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F96M,  /*!< Select PLL_F96M as the default clock choice */
-#endif
 } soc_periph_mcpwm_timer_clk_src_t;
 
 /**
@@ -272,11 +261,7 @@ typedef enum {
 typedef enum {
     MCPWM_CAPTURE_CLK_SRC_PLL96M = SOC_MOD_CLK_PLL_F96M,   /*!< Select PLL_F96M as the source clock */
     MCPWM_CAPTURE_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,         /*!< Select XTAL as the source clock */
-#if CONFIG_IDF_ENV_FPGA
-    MCPWM_CAPTURE_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL,      /*!< Select XTAL as the default clock choice */
-#else
     MCPWM_CAPTURE_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F96M,  /*!< Select PLL_F96M as the default clock choice */
-#endif
 } soc_periph_mcpwm_capture_clk_src_t;
 
 ///////////////////////////////////////////////////// I2S //////////////////////////////////////////////////////////////
@@ -284,21 +269,13 @@ typedef enum {
 /**
  * @brief Array initializer for all supported clock sources of I2S
  */
-#if CONFIG_IDF_ENV_FPGA
-#define SOC_I2S_CLKS {SOC_MOD_CLK_XTAL}
-#else
 #define SOC_I2S_CLKS {SOC_MOD_CLK_PLL_F96M, SOC_MOD_CLK_PLL_F64M, SOC_MOD_CLK_XTAL}
-#endif
 
 /**
  * @brief I2S clock source enum
  */
 typedef enum {
-#if CONFIG_IDF_ENV_FPGA
-    I2S_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL,
-#else
     I2S_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F96M,                 /*!< Select PLL_F96M as the default source clock */
-#endif
     I2S_CLK_SRC_PLL_96M = SOC_MOD_CLK_PLL_F96M,                 /*!< Select PLL_F96M as the source clock */
     I2S_CLK_SRC_PLL_64M = SOC_MOD_CLK_PLL_F64M,                 /*!< Select PLL_F64M as the source clock */
     I2S_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,                        /*!< Select XTAL as the source clock */
@@ -350,11 +327,7 @@ typedef enum {
 typedef enum {
     SDM_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,                        /*!< Select XTAL clock as the source clock */
     SDM_CLK_SRC_PLL_F48M = SOC_MOD_CLK_PLL_F48M,                /*!< Select PLL_F48M clock as the source clock */
-#if CONFIG_IDF_ENV_FPGA
-    SDM_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL,                     /*!< Select XTAL as the default clock choice */
-#else
     SDM_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F48M,                 /*!< Select PLL_F48M as the default clock choice */
-#endif
 } soc_periph_sdm_clk_src_t;
 
 //////////////////////////////////////////////////GPIO Glitch Filter////////////////////////////////////////////////////
@@ -371,11 +344,7 @@ typedef enum {
 typedef enum {
     GLITCH_FILTER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,         /*!< Select XTAL clock as the source clock */
     GLITCH_FILTER_CLK_SRC_PLL_F48M = SOC_MOD_CLK_PLL_F48M, /*!< Select PLL_F48M clock as the source clock */
-#if CONFIG_IDF_ENV_FPGA
-    GLITCH_FILTER_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL,      /*!< Select XTAL as the default clock choice */
-#else
     GLITCH_FILTER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F48M,  /*!< Select PLL_F48M clock as the default clock choice */
-#endif
 } soc_periph_glitch_filter_clk_src_t;
 
 //////////////////////////////////////////////////TWAI/////////////////////////////////////////////////////////////////
@@ -408,11 +377,7 @@ typedef enum {
 typedef enum {
     ADC_DIGI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,           /*!< Select XTAL as the source clock */
     ADC_DIGI_CLK_SRC_PLL_F96M = SOC_MOD_CLK_PLL_F96M,   /*!< Select PLL_F96M as the source clock */
-#if CONFIG_IDF_ENV_FPGA
-    ADC_DIGI_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL,        /*!< Select XTAL as the default clock choice */
-#else
     ADC_DIGI_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F96M,    /*!< Select PLL_F96M as the default clock choice */
-#endif
 } soc_periph_adc_digi_clk_src_t;
 
 //////////////////////////////////////////////////MWDT/////////////////////////////////////////////////////////////////

components/soc/esp32h2/include/soc/io_mux_reg.h

@@ -136,6 +136,8 @@
 #define USB_DM_GPIO_NUM              26
 #define USB_DP_GPIO_NUM              27
 
+#define EXT_OSC_SLOW_GPIO_NUM        13
+
 #define MAX_RTC_GPIO_NUM             14            // GPIO7~14 are the pads with LP function
 #define MAX_PAD_GPIO_NUM             27
 #define MAX_GPIO_NUM                 31

components/soc/esp32h2/include/soc/pmu_struct.h

@@ -1,2867 +1,770 @@
 /**
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
  *
  *  SPDX-License-Identifier: Apache-2.0
  */
 #pragma once
 
 #include <stdint.h>
+#include "soc/pmu_reg.h"
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-/** Group: configure_register */
-/** Type of hp_active_dig_power register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:21;
-        /** hp_active_vdd_spi_pd_en : R/W; bitpos: [21]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_active_vdd_spi_pd_en:1;
-        /** hp_active_hp_mem_dslp : R/W; bitpos: [22]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_active_hp_mem_dslp:1;
-        /** hp_active_pd_hp_mem_pd_en : R/W; bitpos: [26:23]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_active_pd_hp_mem_pd_en:4;
-        /** hp_active_pd_hp_wifi_pd_en : R/W; bitpos: [27]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_active_pd_hp_wifi_pd_en:1;
-        uint32_t reserved_28:1;
-        /** hp_active_pd_hp_cpu_pd_en : R/W; bitpos: [29]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_active_pd_hp_cpu_pd_en:1;
-        /** hp_active_pd_hp_aon_pd_en : R/W; bitpos: [30]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_active_pd_hp_aon_pd_en:1;
-        /** hp_active_pd_top_pd_en : R/W; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_active_pd_top_pd_en:1;
-    };
-    uint32_t val;
-} pmu_hp_active_dig_power_reg_t;
-
-/** Type of hp_active_icg_hp_func register
- *  need_des
- */
-typedef union {
-    struct {
-        /** hp_active_dig_icg_func_en : R/W; bitpos: [31:0]; default: 4294967295;
-         *  need_des
-         */
-        uint32_t hp_active_dig_icg_func_en:32;
-    };
-    uint32_t val;
-} pmu_hp_active_icg_hp_func_reg_t;
-
-/** Type of hp_active_icg_hp_apb register
- *  need_des
- */
-typedef union {
-    struct {
-        /** hp_active_dig_icg_apb_en : R/W; bitpos: [31:0]; default: 4294967295;
-         *  need_des
-         */
-        uint32_t hp_active_dig_icg_apb_en:32;
-    };
-    uint32_t val;
-} pmu_hp_active_icg_hp_apb_reg_t;
-
-/** Type of hp_active_icg_modem register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:30;
-        /** hp_active_dig_icg_modem_code : R/W; bitpos: [31:30]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_active_dig_icg_modem_code:2;
-    };
-    uint32_t val;
-} pmu_hp_active_icg_modem_reg_t;
-
-/** Type of hp_active_hp_sys_cntl register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:24;
-        /** hp_active_uart_wakeup_en : R/W; bitpos: [24]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_active_uart_wakeup_en:1;
-        /** hp_active_lp_pad_hold_all : R/W; bitpos: [25]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_active_lp_pad_hold_all:1;
-        /** hp_active_hp_pad_hold_all : R/W; bitpos: [26]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_active_hp_pad_hold_all:1;
-        /** hp_active_dig_pad_slp_sel : R/W; bitpos: [27]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_active_dig_pad_slp_sel:1;
-        /** hp_active_dig_pause_wdt : R/W; bitpos: [28]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_active_dig_pause_wdt:1;
-        /** hp_active_dig_cpu_stall : R/W; bitpos: [29]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_active_dig_cpu_stall:1;
-        uint32_t reserved_30:2;
-    };
-    uint32_t val;
-} pmu_hp_active_hp_sys_cntl_reg_t;
-
-/** Type of hp_active_hp_ck_power register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:26;
-        /** hp_active_i2c_iso_en : R/W; bitpos: [26]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_active_i2c_iso_en:1;
-        /** hp_active_i2c_retention : R/W; bitpos: [27]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_active_i2c_retention:1;
-        /** hp_active_xpd_bb_i2c : R/W; bitpos: [28]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_active_xpd_bb_i2c:1;
-        /** hp_active_xpd_bbpll_i2c : R/W; bitpos: [29]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_active_xpd_bbpll_i2c:1;
-        /** hp_active_xpd_bbpll : R/W; bitpos: [30]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_active_xpd_bbpll:1;
-        uint32_t reserved_31:1;
-    };
-    uint32_t val;
-} pmu_hp_active_hp_ck_power_reg_t;
-
-/** Type of hp_active_bias register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:24;
-        /** hp_active_xpd_trx : R/W; bitpos: [24]; default: 1;
-         *  need_des
-         */
-        uint32_t hp_active_xpd_trx:1;
-        /** hp_active_xpd_bias : R/W; bitpos: [25]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_active_xpd_bias:1;
-        uint32_t reserved_26:4;
-        /** hp_active_pd_cur : R/W; bitpos: [30]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_active_pd_cur:1;
-        /** hp_active_bias_sleep : R/W; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_active_bias_sleep:1;
-    };
-    uint32_t val;
-} pmu_hp_active_bias_reg_t;
-
-/** Type of hp_active_backup register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:4;
-        /** hp_sleep2active_backup_modem_clk_code : R/W; bitpos: [5:4]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_sleep2active_backup_modem_clk_code:2;
-        /** hp_modem2active_backup_modem_clk_code : R/W; bitpos: [7:6]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_modem2active_backup_modem_clk_code:2;
-        uint32_t reserved_8:2;
-        /** hp_active_retention_mode : R/W; bitpos: [10]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_active_retention_mode:1;
-        /** hp_sleep2active_retention_en : R/W; bitpos: [11]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_sleep2active_retention_en:1;
-        /** hp_modem2active_retention_en : R/W; bitpos: [12]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_modem2active_retention_en:1;
-        uint32_t reserved_13:1;
-        /** hp_sleep2active_backup_clk_sel : R/W; bitpos: [15:14]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_sleep2active_backup_clk_sel:2;
-        /** hp_modem2active_backup_clk_sel : R/W; bitpos: [17:16]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_modem2active_backup_clk_sel:2;
-        uint32_t reserved_18:2;
-        /** hp_sleep2active_backup_mode : R/W; bitpos: [22:20]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_sleep2active_backup_mode:3;
-        /** hp_modem2active_backup_mode : R/W; bitpos: [25:23]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_modem2active_backup_mode:3;
-        uint32_t reserved_26:3;
-        /** hp_sleep2active_backup_en : R/W; bitpos: [29]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_sleep2active_backup_en:1;
-        /** hp_modem2active_backup_en : R/W; bitpos: [30]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_modem2active_backup_en:1;
-        uint32_t reserved_31:1;
-    };
-    uint32_t val;
-} pmu_hp_active_backup_reg_t;
-
-/** Type of hp_active_backup_clk register
- *  need_des
- */
-typedef union {
-    struct {
-        /** hp_active_backup_icg_func_en : R/W; bitpos: [31:0]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_active_backup_icg_func_en:32;
-    };
-    uint32_t val;
-} pmu_hp_active_backup_clk_reg_t;
-
-/** Type of hp_active_sysclk register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:26;
-        /** hp_active_dig_sys_clk_no_div : R/W; bitpos: [26]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_active_dig_sys_clk_no_div:1;
-        /** hp_active_icg_sys_clock_en : R/W; bitpos: [27]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_active_icg_sys_clock_en:1;
-        /** hp_active_sys_clk_slp_sel : R/W; bitpos: [28]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_active_sys_clk_slp_sel:1;
-        /** hp_active_icg_slp_sel : R/W; bitpos: [29]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_active_icg_slp_sel:1;
-        /** hp_active_dig_sys_clk_sel : R/W; bitpos: [31:30]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_active_dig_sys_clk_sel:2;
-    };
-    uint32_t val;
-} pmu_hp_active_sysclk_reg_t;
-
-/** Type of hp_active_hp_regulator0 register
- *  need_des
- */
-typedef union {
-    struct {
-        /** hp_active_hp_power_det_bypass : R/W; bitpos: [0]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_active_hp_power_det_bypass:1;
-        uint32_t reserved_1:3;
-        /** lp_dbias_vol : RO; bitpos: [8:4]; default: 17;
-         *  need_des
-         */
-        uint32_t lp_dbias_vol:5;
-        /** hp_dbias_vol : RO; bitpos: [13:9]; default: 16;
-         *  need_des
-         */
-        uint32_t hp_dbias_vol:5;
-        /** dig_regulator0_dbias_sel : R/W; bitpos: [14]; default: 1;
-         *  need_des
-         */
-        uint32_t dig_regulator0_dbias_sel:1;
-        /** dig_dbias_init : WT; bitpos: [15]; default: 0;
-         *  need_des
-         */
-        uint32_t dig_dbias_init:1;
-        /** hp_active_hp_regulator_slp_mem_xpd : R/W; bitpos: [16]; default: 1;
-         *  need_des
-         */
-        uint32_t hp_active_hp_regulator_slp_mem_xpd:1;
-        /** hp_active_hp_regulator_slp_logic_xpd : R/W; bitpos: [17]; default: 1;
-         *  need_des
-         */
-        uint32_t hp_active_hp_regulator_slp_logic_xpd:1;
-        /** hp_active_hp_regulator_xpd : R/W; bitpos: [18]; default: 1;
-         *  need_des
-         */
-        uint32_t hp_active_hp_regulator_xpd:1;
-        /** hp_active_hp_regulator_slp_mem_dbias : R/W; bitpos: [22:19]; default: 8;
-         *  need_des
-         */
-        uint32_t hp_active_hp_regulator_slp_mem_dbias:4;
-        /** hp_active_hp_regulator_slp_logic_dbias : R/W; bitpos: [26:23]; default: 8;
-         *  need_des
-         */
-        uint32_t hp_active_hp_regulator_slp_logic_dbias:4;
-        /** hp_active_hp_regulator_dbias : R/W; bitpos: [31:27]; default: 16;
-         *  need_des
-         */
-        uint32_t hp_active_hp_regulator_dbias:5;
-    };
-    uint32_t val;
-} pmu_hp_active_hp_regulator0_reg_t;
-
-/** Type of hp_active_hp_regulator1 register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:8;
-        /** hp_active_hp_regulator_drv_b : R/W; bitpos: [31:8]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_active_hp_regulator_drv_b:24;
-    };
-    uint32_t val;
-} pmu_hp_active_hp_regulator1_reg_t;
-
-/** Type of hp_active_xtal register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:31;
-        /** hp_active_xpd_xtal : R/W; bitpos: [31]; default: 1;
-         *  need_des
-         */
-        uint32_t hp_active_xpd_xtal:1;
-    };
-    uint32_t val;
-} pmu_hp_active_xtal_reg_t;
-
-/** Type of hp_modem_dig_power register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:21;
-        /** hp_modem_vdd_spi_pd_en : R/W; bitpos: [21]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_modem_vdd_spi_pd_en:1;
-        /** hp_modem_hp_mem_dslp : R/W; bitpos: [22]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_modem_hp_mem_dslp:1;
-        /** hp_modem_pd_hp_mem_pd_en : R/W; bitpos: [26:23]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_modem_pd_hp_mem_pd_en:4;
-        /** hp_modem_pd_hp_wifi_pd_en : R/W; bitpos: [27]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_modem_pd_hp_wifi_pd_en:1;
-        uint32_t reserved_28:1;
-        /** hp_modem_pd_hp_cpu_pd_en : R/W; bitpos: [29]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_modem_pd_hp_cpu_pd_en:1;
-        /** hp_modem_pd_hp_aon_pd_en : R/W; bitpos: [30]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_modem_pd_hp_aon_pd_en:1;
-        /** hp_modem_pd_top_pd_en : R/W; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_modem_pd_top_pd_en:1;
-    };
-    uint32_t val;
-} pmu_hp_modem_dig_power_reg_t;
-
-/** Type of hp_modem_icg_hp_func register
- *  need_des
- */
-typedef union {
-    struct {
-        /** hp_modem_dig_icg_func_en : R/W; bitpos: [31:0]; default: 4294967295;
-         *  need_des
-         */
-        uint32_t hp_modem_dig_icg_func_en:32;
-    };
-    uint32_t val;
-} pmu_hp_modem_icg_hp_func_reg_t;
-
-/** Type of hp_modem_icg_hp_apb register
- *  need_des
- */
-typedef union {
-    struct {
-        /** hp_modem_dig_icg_apb_en : R/W; bitpos: [31:0]; default: 4294967295;
-         *  need_des
-         */
-        uint32_t hp_modem_dig_icg_apb_en:32;
-    };
-    uint32_t val;
-} pmu_hp_modem_icg_hp_apb_reg_t;
-
-/** Type of hp_modem_icg_modem register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:30;
-        /** hp_modem_dig_icg_modem_code : R/W; bitpos: [31:30]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_modem_dig_icg_modem_code:2;
-    };
-    uint32_t val;
-} pmu_hp_modem_icg_modem_reg_t;
-
-/** Type of hp_modem_hp_sys_cntl register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:24;
-        /** hp_modem_uart_wakeup_en : R/W; bitpos: [24]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_modem_uart_wakeup_en:1;
-        /** hp_modem_lp_pad_hold_all : R/W; bitpos: [25]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_modem_lp_pad_hold_all:1;
-        /** hp_modem_hp_pad_hold_all : R/W; bitpos: [26]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_modem_hp_pad_hold_all:1;
-        /** hp_modem_dig_pad_slp_sel : R/W; bitpos: [27]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_modem_dig_pad_slp_sel:1;
-        /** hp_modem_dig_pause_wdt : R/W; bitpos: [28]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_modem_dig_pause_wdt:1;
-        /** hp_modem_dig_cpu_stall : R/W; bitpos: [29]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_modem_dig_cpu_stall:1;
-        uint32_t reserved_30:2;
-    };
-    uint32_t val;
-} pmu_hp_modem_hp_sys_cntl_reg_t;
-
-/** Type of hp_modem_hp_ck_power register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:26;
-        /** hp_modem_i2c_iso_en : R/W; bitpos: [26]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_modem_i2c_iso_en:1;
-        /** hp_modem_i2c_retention : R/W; bitpos: [27]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_modem_i2c_retention:1;
-        /** hp_modem_xpd_bb_i2c : R/W; bitpos: [28]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_modem_xpd_bb_i2c:1;
-        /** hp_modem_xpd_bbpll_i2c : R/W; bitpos: [29]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_modem_xpd_bbpll_i2c:1;
-        /** hp_modem_xpd_bbpll : R/W; bitpos: [30]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_modem_xpd_bbpll:1;
-        uint32_t reserved_31:1;
-    };
-    uint32_t val;
-} pmu_hp_modem_hp_ck_power_reg_t;
-
-/** Type of hp_modem_bias register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:24;
-        /** hp_modem_xpd_trx : R/W; bitpos: [24]; default: 1;
-         *  need_des
-         */
-        uint32_t hp_modem_xpd_trx:1;
-        /** hp_modem_xpd_bias : R/W; bitpos: [25]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_modem_xpd_bias:1;
-        uint32_t reserved_26:4;
-        /** hp_modem_pd_cur : R/W; bitpos: [30]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_modem_pd_cur:1;
-        /** hp_modem_bias_sleep : R/W; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_modem_bias_sleep:1;
-    };
-    uint32_t val;
-} pmu_hp_modem_bias_reg_t;
-
-/** Type of hp_modem_backup register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:4;
-        /** hp_sleep2modem_backup_modem_clk_code : R/W; bitpos: [5:4]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_sleep2modem_backup_modem_clk_code:2;
-        uint32_t reserved_6:4;
-        /** hp_modem_retention_mode : R/W; bitpos: [10]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_modem_retention_mode:1;
-        /** hp_sleep2modem_retention_en : R/W; bitpos: [11]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_sleep2modem_retention_en:1;
-        uint32_t reserved_12:2;
-        /** hp_sleep2modem_backup_clk_sel : R/W; bitpos: [15:14]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_sleep2modem_backup_clk_sel:2;
-        uint32_t reserved_16:4;
-        /** hp_sleep2modem_backup_mode : R/W; bitpos: [22:20]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_sleep2modem_backup_mode:3;
-        uint32_t reserved_23:6;
-        /** hp_sleep2modem_backup_en : R/W; bitpos: [29]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_sleep2modem_backup_en:1;
-        uint32_t reserved_30:2;
-    };
-    uint32_t val;
-} pmu_hp_modem_backup_reg_t;
-
-/** Type of hp_modem_backup_clk register
- *  need_des
- */
 typedef union {
     struct {
-        /** hp_modem_backup_icg_func_en : R/W; bitpos: [31:0]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_modem_backup_icg_func_en:32;
+        uint32_t reserved0    : 21;
+        uint32_t vdd_spi_pd_en: 1;
+        uint32_t mem_dslp     : 1;
+        uint32_t mem_pd_en    : 4;
+        uint32_t wifi_pd_en   : 1;
+        uint32_t reserved1    : 1;
+        uint32_t cpu_pd_en    : 1;
+        uint32_t aon_pd_en    : 1;
+        uint32_t top_pd_en    : 1;
     };
     uint32_t val;
-} pmu_hp_modem_backup_clk_reg_t;
+} pmu_hp_dig_power_reg_t;
 
-/** Type of hp_modem_sysclk register
- *  need_des
- */
 typedef union {
     struct {
-        uint32_t reserved_0:26;
-        /** hp_modem_dig_sys_clk_no_div : R/W; bitpos: [26]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_modem_dig_sys_clk_no_div:1;
-        /** hp_modem_icg_sys_clock_en : R/W; bitpos: [27]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_modem_icg_sys_clock_en:1;
-        /** hp_modem_sys_clk_slp_sel : R/W; bitpos: [28]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_modem_sys_clk_slp_sel:1;
-        /** hp_modem_icg_slp_sel : R/W; bitpos: [29]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_modem_icg_slp_sel:1;
-        /** hp_modem_dig_sys_clk_sel : R/W; bitpos: [31:30]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_modem_dig_sys_clk_sel:2;
+        uint32_t reserved0: 30;
+        uint32_t code     : 2;
     };
     uint32_t val;
-} pmu_hp_modem_sysclk_reg_t;
+} pmu_hp_icg_modem_reg_t;
 
-/** Type of hp_modem_hp_regulator0 register
- *  need_des
- */
 typedef union {
     struct {
-        /** hp_modem_hp_power_det_bypass : R/W; bitpos: [0]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_modem_hp_power_det_bypass:1;
-        uint32_t reserved_1:15;
-        /** hp_modem_hp_regulator_slp_mem_xpd : R/W; bitpos: [16]; default: 1;
-         *  need_des
-         */
-        uint32_t hp_modem_hp_regulator_slp_mem_xpd:1;
-        /** hp_modem_hp_regulator_slp_logic_xpd : R/W; bitpos: [17]; default: 1;
-         *  need_des
-         */
-        uint32_t hp_modem_hp_regulator_slp_logic_xpd:1;
-        /** hp_modem_hp_regulator_xpd : R/W; bitpos: [18]; default: 1;
-         *  need_des
-         */
-        uint32_t hp_modem_hp_regulator_xpd:1;
-        /** hp_modem_hp_regulator_slp_mem_dbias : R/W; bitpos: [22:19]; default: 8;
-         *  need_des
-         */
-        uint32_t hp_modem_hp_regulator_slp_mem_dbias:4;
-        /** hp_modem_hp_regulator_slp_logic_dbias : R/W; bitpos: [26:23]; default: 8;
-         *  need_des
-         */
-        uint32_t hp_modem_hp_regulator_slp_logic_dbias:4;
-        /** hp_modem_hp_regulator_dbias : R/W; bitpos: [31:27]; default: 16;
-         *  need_des
-         */
-        uint32_t hp_modem_hp_regulator_dbias:5;
+        uint32_t reserved0      : 24;
+        uint32_t uart_wakeup_en : 1;
+        uint32_t lp_pad_hold_all: 1;
+        uint32_t hp_pad_hold_all: 1;
+        uint32_t dig_pad_slp_sel: 1;
+        uint32_t dig_pause_wdt  : 1;
+        uint32_t dig_cpu_stall  : 1;
+        uint32_t reserved1      : 2;
     };
     uint32_t val;
-} pmu_hp_modem_hp_regulator0_reg_t;
+} pmu_hp_sys_cntl_reg_t;
 
-/** Type of hp_modem_hp_regulator1 register
- *  need_des
- */
 typedef union {
     struct {
-        uint32_t reserved_0:8;
-        /** hp_modem_hp_regulator_drv_b : R/W; bitpos: [31:8]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_modem_hp_regulator_drv_b:24;
+        uint32_t reserved0    : 26;
+        uint32_t i2c_iso_en   : 1;
+        uint32_t i2c_retention: 1;
+        uint32_t xpd_bb_i2c   : 1;
+        uint32_t xpd_bbpll_i2c: 1;
+        uint32_t xpd_bbpll    : 1;
+        uint32_t reserved1    : 1;
     };
     uint32_t val;
-} pmu_hp_modem_hp_regulator1_reg_t;
+} pmu_hp_clk_power_reg_t;
 
-/** Type of hp_modem_xtal register
- *  need_des
- */
 typedef union {
     struct {
-        uint32_t reserved_0:31;
-        /** hp_modem_xpd_xtal : R/W; bitpos: [31]; default: 1;
-         *  need_des
-         */
-        uint32_t hp_modem_xpd_xtal:1;
+        uint32_t reserved0 : 24;
+        uint32_t xpd_trx   : 1;
+        uint32_t xpd_bias  : 1;
+        uint32_t reserved1 : 4;
+        uint32_t pd_cur    : 1;
+        uint32_t bias_sleep: 1;
     };
     uint32_t val;
-} pmu_hp_modem_xtal_reg_t;
+} pmu_hp_bias_reg_t;
 
-/** Type of hp_sleep_dig_power register
- *  need_des
- */
 typedef union {
-    struct {
-        uint32_t reserved_0:21;
-        /** hp_sleep_vdd_spi_pd_en : R/W; bitpos: [21]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_sleep_vdd_spi_pd_en:1;
-        /** hp_sleep_hp_mem_dslp : R/W; bitpos: [22]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_sleep_hp_mem_dslp:1;
-        /** hp_sleep_pd_hp_mem_pd_en : R/W; bitpos: [26:23]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_sleep_pd_hp_mem_pd_en:4;
-        /** hp_sleep_pd_hp_wifi_pd_en : R/W; bitpos: [27]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_sleep_pd_hp_wifi_pd_en:1;
-        uint32_t reserved_28:1;
-        /** hp_sleep_pd_hp_cpu_pd_en : R/W; bitpos: [29]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_sleep_pd_hp_cpu_pd_en:1;
-        /** hp_sleep_pd_hp_aon_pd_en : R/W; bitpos: [30]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_sleep_pd_hp_aon_pd_en:1;
-        /** hp_sleep_pd_top_pd_en : R/W; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_sleep_pd_top_pd_en:1;
+    struct {    /* HP: Active State */
+        uint32_t reserved0                            : 4;
+        uint32_t hp_sleep2active_backup_modem_clk_code: 2;
+        uint32_t hp_modem2active_backup_modem_clk_code: 2;
+        uint32_t reserved1                            : 2;
+        uint32_t hp_active_retention_mode             : 1;
+        uint32_t hp_sleep2active_retention_en         : 1;
+        uint32_t hp_modem2active_retention_en         : 1;
+        uint32_t reserved2                            : 1;
+        uint32_t hp_sleep2active_backup_clk_sel       : 2;
+        uint32_t hp_modem2active_backup_clk_sel       : 2;
+        uint32_t reserved3                            : 2;
+        uint32_t hp_sleep2active_backup_mode          : 3;
+        uint32_t hp_modem2active_backup_mode          : 3;
+        uint32_t reserved4                            : 3;
+        uint32_t hp_sleep2active_backup_en            : 1;
+        uint32_t hp_modem2active_backup_en            : 1;
+        uint32_t reserved5                            : 1;
     };
-    uint32_t val;
-} pmu_hp_sleep_dig_power_reg_t;
-
-/** Type of hp_sleep_icg_hp_func register
- *  need_des
- */
-typedef union {
-    struct {
-        /** hp_sleep_dig_icg_func_en : R/W; bitpos: [31:0]; default: 4294967295;
-         *  need_des
-         */
-        uint32_t hp_sleep_dig_icg_func_en:32;
-    };
-    uint32_t val;
-} pmu_hp_sleep_icg_hp_func_reg_t;
-
-/** Type of hp_sleep_icg_hp_apb register
- *  need_des
- */
-typedef union {
-    struct {
-        /** hp_sleep_dig_icg_apb_en : R/W; bitpos: [31:0]; default: 4294967295;
-         *  need_des
-         */
-        uint32_t hp_sleep_dig_icg_apb_en:32;
+    struct {    /* HP: Modem State */
+        uint32_t reserved6                            : 4;
+        uint32_t hp_sleep2modem_backup_modem_clk_code : 2;
+        uint32_t reserved7                            : 4;
+        uint32_t hp_modem_retention_mode              : 1;
+        uint32_t hp_sleep2modem_retention_en          : 1;
+        uint32_t reserved8                            : 2;
+        uint32_t hp_sleep2modem_backup_clk_sel        : 2;
+        uint32_t reserved9                            : 4;
+        uint32_t hp_sleep2modem_backup_mode           : 3;
+        uint32_t reserved10                           : 6;
+        uint32_t hp_sleep2modem_backup_en             : 1;
+        uint32_t reserved11                           : 2;
     };
-    uint32_t val;
-} pmu_hp_sleep_icg_hp_apb_reg_t;
-
-/** Type of hp_sleep_icg_modem register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:30;
-        /** hp_sleep_dig_icg_modem_code : R/W; bitpos: [31:30]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_sleep_dig_icg_modem_code:2;
+    struct {    /* HP: Sleep State */
+        uint32_t reserved12                           : 6;
+        uint32_t hp_modem2sleep_backup_modem_clk_code : 2;
+        uint32_t hp_active2sleep_backup_modem_clk_code: 2;
+        uint32_t hp_sleep_retention_mode              : 1;
+        uint32_t reserved13                           : 1;
+        uint32_t hp_modem2sleep_retention_en          : 1;
+        uint32_t hp_active2sleep_retention_en         : 1;
+        uint32_t reserved14                           : 2;
+        uint32_t hp_modem2sleep_backup_clk_sel        : 2;
+        uint32_t hp_active2sleep_backup_clk_sel       : 2;
+        uint32_t reserved15                           : 3;
+        uint32_t hp_modem2sleep_backup_mode           : 3;
+        uint32_t hp_active2sleep_backup_mode          : 3;
+        uint32_t reserved16                           : 1;
+        uint32_t hp_modem2sleep_backup_en             : 1;
+        uint32_t hp_active2sleep_backup_en            : 1;
     };
     uint32_t val;
-} pmu_hp_sleep_icg_modem_reg_t;
+} pmu_hp_backup_reg_t;
 
-/** Type of hp_sleep_hp_sys_cntl register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:24;
-        /** hp_sleep_uart_wakeup_en : R/W; bitpos: [24]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_sleep_uart_wakeup_en:1;
-        /** hp_sleep_lp_pad_hold_all : R/W; bitpos: [25]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_sleep_lp_pad_hold_all:1;
-        /** hp_sleep_hp_pad_hold_all : R/W; bitpos: [26]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_sleep_hp_pad_hold_all:1;
-        /** hp_sleep_dig_pad_slp_sel : R/W; bitpos: [27]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_sleep_dig_pad_slp_sel:1;
-        /** hp_sleep_dig_pause_wdt : R/W; bitpos: [28]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_sleep_dig_pause_wdt:1;
-        /** hp_sleep_dig_cpu_stall : R/W; bitpos: [29]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_sleep_dig_cpu_stall:1;
-        uint32_t reserved_30:2;
-    };
-    uint32_t val;
-} pmu_hp_sleep_hp_sys_cntl_reg_t;
-
-/** Type of hp_sleep_hp_ck_power register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:26;
-        /** hp_sleep_i2c_iso_en : R/W; bitpos: [26]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_sleep_i2c_iso_en:1;
-        /** hp_sleep_i2c_retention : R/W; bitpos: [27]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_sleep_i2c_retention:1;
-        /** hp_sleep_xpd_bb_i2c : R/W; bitpos: [28]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_sleep_xpd_bb_i2c:1;
-        /** hp_sleep_xpd_bbpll_i2c : R/W; bitpos: [29]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_sleep_xpd_bbpll_i2c:1;
-        /** hp_sleep_xpd_bbpll : R/W; bitpos: [30]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_sleep_xpd_bbpll:1;
-        uint32_t reserved_31:1;
-    };
-    uint32_t val;
-} pmu_hp_sleep_hp_ck_power_reg_t;
-
-/** Type of hp_sleep_bias register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:24;
-        /** hp_sleep_xpd_trx : R/W; bitpos: [24]; default: 1;
-         *  need_des
-         */
-        uint32_t hp_sleep_xpd_trx:1;
-        /** hp_sleep_xpd_bias : R/W; bitpos: [25]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_sleep_xpd_bias:1;
-        uint32_t reserved_26:4;
-        /** hp_sleep_pd_cur : R/W; bitpos: [30]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_sleep_pd_cur:1;
-        /** hp_sleep_bias_sleep : R/W; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_sleep_bias_sleep:1;
-    };
-    uint32_t val;
-} pmu_hp_sleep_bias_reg_t;
-
-/** Type of hp_sleep_backup register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:6;
-        /** hp_modem2sleep_backup_modem_clk_code : R/W; bitpos: [7:6]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_modem2sleep_backup_modem_clk_code:2;
-        /** hp_active2sleep_backup_modem_clk_code : R/W; bitpos: [9:8]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_active2sleep_backup_modem_clk_code:2;
-        /** hp_sleep_retention_mode : R/W; bitpos: [10]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_sleep_retention_mode:1;
-        uint32_t reserved_11:1;
-        /** hp_modem2sleep_retention_en : R/W; bitpos: [12]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_modem2sleep_retention_en:1;
-        /** hp_active2sleep_retention_en : R/W; bitpos: [13]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_active2sleep_retention_en:1;
-        uint32_t reserved_14:2;
-        /** hp_modem2sleep_backup_clk_sel : R/W; bitpos: [17:16]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_modem2sleep_backup_clk_sel:2;
-        /** hp_active2sleep_backup_clk_sel : R/W; bitpos: [19:18]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_active2sleep_backup_clk_sel:2;
-        uint32_t reserved_20:3;
-        /** hp_modem2sleep_backup_mode : R/W; bitpos: [25:23]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_modem2sleep_backup_mode:3;
-        /** hp_active2sleep_backup_mode : R/W; bitpos: [28:26]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_active2sleep_backup_mode:3;
-        uint32_t reserved_29:1;
-        /** hp_modem2sleep_backup_en : R/W; bitpos: [30]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_modem2sleep_backup_en:1;
-        /** hp_active2sleep_backup_en : R/W; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_active2sleep_backup_en:1;
-    };
-    uint32_t val;
-} pmu_hp_sleep_backup_reg_t;
-
-/** Type of hp_sleep_backup_clk register
- *  need_des
- */
-typedef union {
-    struct {
-        /** hp_sleep_backup_icg_func_en : R/W; bitpos: [31:0]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_sleep_backup_icg_func_en:32;
-    };
-    uint32_t val;
-} pmu_hp_sleep_backup_clk_reg_t;
-
-/** Type of hp_sleep_sysclk register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:26;
-        /** hp_sleep_dig_sys_clk_no_div : R/W; bitpos: [26]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_sleep_dig_sys_clk_no_div:1;
-        /** hp_sleep_icg_sys_clock_en : R/W; bitpos: [27]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_sleep_icg_sys_clock_en:1;
-        /** hp_sleep_sys_clk_slp_sel : R/W; bitpos: [28]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_sleep_sys_clk_slp_sel:1;
-        /** hp_sleep_icg_slp_sel : R/W; bitpos: [29]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_sleep_icg_slp_sel:1;
-        /** hp_sleep_dig_sys_clk_sel : R/W; bitpos: [31:30]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_sleep_dig_sys_clk_sel:2;
-    };
-    uint32_t val;
-} pmu_hp_sleep_sysclk_reg_t;
-
-/** Type of hp_sleep_hp_regulator0 register
- *  need_des
- */
-typedef union {
-    struct {
-        /** hp_sleep_hp_power_det_bypass : R/W; bitpos: [0]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_sleep_hp_power_det_bypass:1;
-        uint32_t reserved_1:15;
-        /** hp_sleep_hp_regulator_slp_mem_xpd : R/W; bitpos: [16]; default: 1;
-         *  need_des
-         */
-        uint32_t hp_sleep_hp_regulator_slp_mem_xpd:1;
-        /** hp_sleep_hp_regulator_slp_logic_xpd : R/W; bitpos: [17]; default: 1;
-         *  need_des
-         */
-        uint32_t hp_sleep_hp_regulator_slp_logic_xpd:1;
-        /** hp_sleep_hp_regulator_xpd : R/W; bitpos: [18]; default: 1;
-         *  need_des
-         */
-        uint32_t hp_sleep_hp_regulator_xpd:1;
-        /** hp_sleep_hp_regulator_slp_mem_dbias : R/W; bitpos: [22:19]; default: 8;
-         *  need_des
-         */
-        uint32_t hp_sleep_hp_regulator_slp_mem_dbias:4;
-        /** hp_sleep_hp_regulator_slp_logic_dbias : R/W; bitpos: [26:23]; default: 8;
-         *  need_des
-         */
-        uint32_t hp_sleep_hp_regulator_slp_logic_dbias:4;
-        /** hp_sleep_hp_regulator_dbias : R/W; bitpos: [31:27]; default: 16;
-         *  need_des
-         */
-        uint32_t hp_sleep_hp_regulator_dbias:5;
-    };
-    uint32_t val;
-} pmu_hp_sleep_hp_regulator0_reg_t;
-
-/** Type of hp_sleep_hp_regulator1 register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:8;
-        /** hp_sleep_hp_regulator_drv_b : R/W; bitpos: [31:8]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_sleep_hp_regulator_drv_b:24;
-    };
-    uint32_t val;
-} pmu_hp_sleep_hp_regulator1_reg_t;
-
-/** Type of hp_sleep_xtal register
- *  need_des
- */
 typedef union {
     struct {
-        uint32_t reserved_0:31;
-        /** hp_sleep_xpd_xtal : R/W; bitpos: [31]; default: 1;
-         *  need_des
-         */
-        uint32_t hp_sleep_xpd_xtal:1;
+        uint32_t reserved0       : 26;
+        uint32_t dig_sysclk_nodiv: 1;
+        uint32_t icg_sysclk_en   : 1;
+        uint32_t sysclk_slp_sel  : 1;
+        uint32_t icg_slp_sel     : 1;
+        uint32_t dig_sysclk_sel  : 2;
     };
     uint32_t val;
-} pmu_hp_sleep_xtal_reg_t;
+} pmu_hp_sysclk_reg_t;
 
-/** Type of hp_sleep_lp_regulator0 register
- *  need_des
- */
 typedef union {
     struct {
-        uint32_t reserved_0:21;
-        /** hp_sleep_lp_regulator_slp_xpd : R/W; bitpos: [21]; default: 1;
-         *  need_des
-         */
-        uint32_t hp_sleep_lp_regulator_slp_xpd:1;
-        /** hp_sleep_lp_regulator_xpd : R/W; bitpos: [22]; default: 1;
-         *  need_des
-         */
-        uint32_t hp_sleep_lp_regulator_xpd:1;
-        /** hp_sleep_lp_regulator_slp_dbias : R/W; bitpos: [26:23]; default: 8;
-         *  need_des
-         */
-        uint32_t hp_sleep_lp_regulator_slp_dbias:4;
-        /** hp_sleep_lp_regulator_dbias : R/W; bitpos: [31:27]; default: 17;
-         *  need_des
-         */
-        uint32_t hp_sleep_lp_regulator_dbias:5;
+        uint32_t power_det_bypass : 1;
+        uint32_t reserved0        : 3;    /* Only HP_ACTIVE modem under hp system is valid */
+        uint32_t lp_dbias_vol     : 5;    /* Only HP_ACTIVE modem under hp system is valid */
+        uint32_t hp_dbias_vol     : 5;    /* Only HP_ACTIVE modem under hp system is valid */
+        uint32_t dbias_sel        : 1;    /* Only HP_ACTIVE modem under hp system is valid */
+        uint32_t dbias_init       : 1;    /* Only HP_ACTIVE modem under hp system is valid */
+        uint32_t slp_mem_xpd      : 1;
+        uint32_t slp_logic_xpd    : 1;
+        uint32_t xpd              : 1;
+        uint32_t slp_mem_dbias    : 4;
+        uint32_t slp_logic_dbias  : 4;
+        uint32_t dbias            : 5;
     };
     uint32_t val;
-} pmu_hp_sleep_lp_regulator0_reg_t;
+} pmu_hp_regulator0_reg_t;
 
-/** Type of hp_sleep_lp_regulator1 register
- *  need_des
- */
 typedef union {
     struct {
-        uint32_t reserved_0:28;
-        /** hp_sleep_lp_regulator_drv_b : R/W; bitpos: [31:28]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_sleep_lp_regulator_drv_b:4;
+        uint32_t reserved0: 8;
+        uint32_t drv_b    : 24;
     };
     uint32_t val;
-} pmu_hp_sleep_lp_regulator1_reg_t;
+} pmu_hp_regulator1_reg_t;
 
-/** Type of hp_sleep_lp_dcdc_reserve register
- *  need_des
- */
 typedef union {
     struct {
-        /** hp_sleep_lp_dcdc_reserve : WT; bitpos: [31:0]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_sleep_lp_dcdc_reserve:32;
+        uint32_t reserved0: 31;
+        uint32_t xpd_xtal : 1;
     };
     uint32_t val;
-} pmu_hp_sleep_lp_dcdc_reserve_reg_t;
+} pmu_hp_xtal_reg_t;
 
-/** Type of hp_sleep_lp_dig_power register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:27;
-        /** hp_sleep_bod_source_sel : R/W; bitpos: [27]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_sleep_bod_source_sel:1;
-        /** hp_sleep_vddbat_mode : R/W; bitpos: [29:28]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_sleep_vddbat_mode:2;
-        /** hp_sleep_lp_mem_dslp : R/W; bitpos: [30]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_sleep_lp_mem_dslp:1;
-        /** hp_sleep_pd_lp_peri_pd_en : R/W; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_sleep_pd_lp_peri_pd_en:1;
-    };
-    uint32_t val;
-} pmu_hp_sleep_lp_dig_power_reg_t;
+typedef volatile struct pmu_hp_hw_regmap_t{
+    pmu_hp_dig_power_reg_t     dig_power;
+    uint32_t                   icg_func;
+    uint32_t                   icg_apb;
+    pmu_hp_icg_modem_reg_t     icg_modem;
+    pmu_hp_sys_cntl_reg_t      syscntl;
+    pmu_hp_clk_power_reg_t     clk_power;
+    pmu_hp_bias_reg_t          bias;
+    pmu_hp_backup_reg_t        backup;
+    uint32_t                   backup_clk;
+    pmu_hp_sysclk_reg_t        sysclk;
+    pmu_hp_regulator0_reg_t    regulator0;
+    pmu_hp_regulator1_reg_t    regulator1;
+    pmu_hp_xtal_reg_t          xtal;
+} pmu_hp_hw_regmap_t;
 
-/** Type of hp_sleep_lp_ck_power register
- *  need_des
- */
+/** */
 typedef union {
     struct {
-        uint32_t reserved_0:27;
-        /** hp_sleep_xpd_lppll : R/W; bitpos: [27]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_sleep_xpd_lppll:1;
-        /** hp_sleep_xpd_xtal32k : R/W; bitpos: [28]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_sleep_xpd_xtal32k:1;
-        /** hp_sleep_xpd_rc32k : R/W; bitpos: [29]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_sleep_xpd_rc32k:1;
-        /** hp_sleep_xpd_fosc_clk : R/W; bitpos: [30]; default: 1;
-         *  need_des
-         */
-        uint32_t hp_sleep_xpd_fosc_clk:1;
-        /** hp_sleep_pd_osc_clk : R/W; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_sleep_pd_osc_clk:1;
+        uint32_t reserved0: 21;
+        uint32_t slp_xpd  : 1;
+        uint32_t xpd	  : 1;
+        uint32_t slp_dbias: 4;
+        uint32_t dbias    : 5;
     };
     uint32_t val;
-} pmu_hp_sleep_lp_ck_power_reg_t;
+} pmu_lp_regulator0_reg_t;
 
-/** Type of lp_sleep_lp_bias_reserve register
- *  need_des
- */
 typedef union {
     struct {
-        /** lp_sleep_lp_bias_reserve : WT; bitpos: [31:0]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_sleep_lp_bias_reserve:32;
+        uint32_t reserved0: 28;
+        uint32_t drv_b    : 4;
     };
     uint32_t val;
-} pmu_lp_sleep_lp_bias_reserve_reg_t;
+} pmu_lp_regulator1_reg_t;
 
-/** Type of lp_sleep_lp_regulator0 register
- *  need_des
- */
 typedef union {
     struct {
-        uint32_t reserved_0:21;
-        /** lp_sleep_lp_regulator_slp_xpd : R/W; bitpos: [21]; default: 1;
-         *  need_des
-         */
-        uint32_t lp_sleep_lp_regulator_slp_xpd:1;
-        /** lp_sleep_lp_regulator_xpd : R/W; bitpos: [22]; default: 1;
-         *  need_des
-         */
-        uint32_t lp_sleep_lp_regulator_xpd:1;
-        /** lp_sleep_lp_regulator_slp_dbias : R/W; bitpos: [26:23]; default: 8;
-         *  need_des
-         */
-        uint32_t lp_sleep_lp_regulator_slp_dbias:4;
-        /** lp_sleep_lp_regulator_dbias : R/W; bitpos: [31:27]; default: 17;
-         *  need_des
-         */
-        uint32_t lp_sleep_lp_regulator_dbias:5;
+        uint32_t reserved0: 31;
+        uint32_t xpd_xtal : 1;
     };
     uint32_t val;
-} pmu_lp_sleep_lp_regulator0_reg_t;
+} pmu_lp_xtal_reg_t;
 
-/** Type of lp_sleep_lp_regulator1 register
- *  need_des
- */
 typedef union {
     struct {
-        uint32_t reserved_0:28;
-        /** lp_sleep_lp_regulator_drv_b : R/W; bitpos: [31:28]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_sleep_lp_regulator_drv_b:4;
+        uint32_t reserved0      : 27;
+        uint32_t bod_source_sel : 1;
+        uint32_t vddbat_mode    : 2;
+        uint32_t mem_dslp       : 1;
+        uint32_t peri_pd_en     : 1;
     };
     uint32_t val;
-} pmu_lp_sleep_lp_regulator1_reg_t;
+} pmu_lp_dig_power_reg_t;
 
-/** Type of lp_sleep_xtal register
- *  need_des
- */
 typedef union {
     struct {
-        uint32_t reserved_0:31;
-        /** lp_sleep_xpd_xtal : R/W; bitpos: [31]; default: 1;
-         *  need_des
-         */
-        uint32_t lp_sleep_xpd_xtal:1;
+        uint32_t reserved0  : 27;
+        uint32_t xpd_lppll  : 1;
+        uint32_t xpd_xtal32k: 1;
+        uint32_t xpd_rc32k  : 1;
+        uint32_t xpd_fosc   : 1;
+        uint32_t pd_osc     : 1;
     };
     uint32_t val;
-} pmu_lp_sleep_xtal_reg_t;
+} pmu_lp_clk_power_reg_t;
 
-/** Type of lp_sleep_lp_dig_power register
- *  need_des
- */
 typedef union {
     struct {
-        uint32_t reserved_0:27;
-        /** lp_sleep_bod_source_sel : R/W; bitpos: [27]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_sleep_bod_source_sel:1;
-        /** lp_sleep_vddbat_mode : R/W; bitpos: [29:28]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_sleep_vddbat_mode:2;
-        /** lp_sleep_lp_mem_dslp : R/W; bitpos: [30]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_sleep_lp_mem_dslp:1;
-        /** lp_sleep_pd_lp_peri_pd_en : R/W; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_sleep_pd_lp_peri_pd_en:1;
+        uint32_t reserved0 : 25;
+        uint32_t xpd_bias  : 1;
+        uint32_t reserved1 : 4;
+        uint32_t pd_cur    : 1;
+        uint32_t bias_sleep: 1;
     };
     uint32_t val;
-} pmu_lp_sleep_lp_dig_power_reg_t;
+} pmu_lp_bias_reg_t;
 
-/** Type of lp_sleep_lp_ck_power register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:27;
-        /** lp_sleep_xpd_lppll : R/W; bitpos: [27]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_sleep_xpd_lppll:1;
-        /** lp_sleep_xpd_xtal32k : R/W; bitpos: [28]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_sleep_xpd_xtal32k:1;
-        /** lp_sleep_xpd_rc32k : R/W; bitpos: [29]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_sleep_xpd_rc32k:1;
-        /** lp_sleep_xpd_fosc_clk : R/W; bitpos: [30]; default: 1;
-         *  need_des
-         */
-        uint32_t lp_sleep_xpd_fosc_clk:1;
-        /** lp_sleep_pd_osc_clk : R/W; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_sleep_pd_osc_clk:1;
-    };
-    uint32_t val;
-} pmu_lp_sleep_lp_ck_power_reg_t;
+typedef volatile struct pmu_lp_hw_regmap_t{
+    pmu_lp_regulator0_reg_t    regulator0;
+    pmu_lp_regulator1_reg_t    regulator1;
+    pmu_lp_xtal_reg_t          xtal;   /* Only LP_SLEEP mode under lp system is valid */
+    pmu_lp_dig_power_reg_t     dig_power;
+    pmu_lp_clk_power_reg_t     clk_power;
+    pmu_lp_bias_reg_t          bias;   /* Only LP_SLEEP mode under lp system is valid */
+} pmu_lp_hw_regmap_t;
 
-/** Type of lp_sleep_bias register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:25;
-        /** lp_sleep_xpd_bias : R/W; bitpos: [25]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_sleep_xpd_bias:1;
-        uint32_t reserved_26:4;
-        /** lp_sleep_pd_cur : R/W; bitpos: [30]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_sleep_pd_cur:1;
-        /** lp_sleep_bias_sleep : R/W; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_sleep_bias_sleep:1;
-    };
-    uint32_t val;
-} pmu_lp_sleep_bias_reg_t;
 
-/** Type of imm_hp_ck_power register
- *  need_des
- */
 typedef union {
     struct {
-        /** tie_low_global_bbpll_icg : WT; bitpos: [0]; default: 0;
-         *  need_des
-         */
-        uint32_t tie_low_global_bbpll_icg:1;
-        /** tie_low_global_xtal_icg : WT; bitpos: [1]; default: 0;
-         *  need_des
-         */
-        uint32_t tie_low_global_xtal_icg:1;
-        /** tie_low_i2c_retention : WT; bitpos: [2]; default: 0;
-         *  need_des
-         */
-        uint32_t tie_low_i2c_retention:1;
-        /** tie_low_xpd_bb_i2c : WT; bitpos: [3]; default: 0;
-         *  need_des
-         */
-        uint32_t tie_low_xpd_bb_i2c:1;
-        /** tie_low_xpd_bbpll_i2c : WT; bitpos: [4]; default: 0;
-         *  need_des
-         */
-        uint32_t tie_low_xpd_bbpll_i2c:1;
-        /** tie_low_xpd_bbpll : WT; bitpos: [5]; default: 0;
-         *  need_des
-         */
-        uint32_t tie_low_xpd_bbpll:1;
-        /** tie_low_xpd_xtal : WT; bitpos: [6]; default: 0;
-         *  need_des
-         */
-        uint32_t tie_low_xpd_xtal:1;
-        uint32_t reserved_7:18;
-        /** tie_high_global_bbpll_icg : WT; bitpos: [25]; default: 0;
-         *  need_des
-         */
-        uint32_t tie_high_global_bbpll_icg:1;
-        /** tie_high_global_xtal_icg : WT; bitpos: [26]; default: 0;
-         *  need_des
-         */
-        uint32_t tie_high_global_xtal_icg:1;
-        /** tie_high_i2c_retention : WT; bitpos: [27]; default: 0;
-         *  need_des
-         */
-        uint32_t tie_high_i2c_retention:1;
-        /** tie_high_xpd_bb_i2c : WT; bitpos: [28]; default: 0;
-         *  need_des
-         */
-        uint32_t tie_high_xpd_bb_i2c:1;
-        /** tie_high_xpd_bbpll_i2c : WT; bitpos: [29]; default: 0;
-         *  need_des
-         */
-        uint32_t tie_high_xpd_bbpll_i2c:1;
-        /** tie_high_xpd_bbpll : WT; bitpos: [30]; default: 0;
-         *  need_des
-         */
-        uint32_t tie_high_xpd_bbpll:1;
-        /** tie_high_xpd_xtal : WT; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t tie_high_xpd_xtal:1;
+        uint32_t tie_low_global_bbpll_icg : 1;
+        uint32_t tie_low_global_xtal_icg  : 1;
+        uint32_t tie_low_i2c_retention    : 1;
+        uint32_t tie_low_xpd_bb_i2c       : 1;
+        uint32_t tie_low_xpd_bbpll_i2c    : 1;
+        uint32_t tie_low_xpd_bbpll        : 1;
+        uint32_t tie_low_xpd_xtal         : 1;
+        uint32_t reserved0                : 18;
+        uint32_t tie_high_global_bbpll_icg: 1;
+        uint32_t tie_high_global_xtal_icg : 1;
+        uint32_t tie_high_i2c_retention   : 1;
+        uint32_t tie_high_xpd_bb_i2c      : 1;
+        uint32_t tie_high_xpd_bbpll_i2c   : 1;
+        uint32_t tie_high_xpd_bbpll       : 1;
+        uint32_t tie_high_xpd_xtal        : 1;
     };
     uint32_t val;
-} pmu_imm_hp_ck_power_reg_t;
+} pmu_imm_hp_clk_power_reg_t;
 
-/** Type of imm_sleep_sysclk register
- *  need_des
- */
 typedef union {
     struct {
-        uint32_t reserved_0:28;
-        /** update_dig_icg_switch : WT; bitpos: [28]; default: 0;
-         *  need_des
-         */
-        uint32_t update_dig_icg_switch:1;
-        /** tie_low_icg_slp_sel : WT; bitpos: [29]; default: 0;
-         *  need_des
-         */
-        uint32_t tie_low_icg_slp_sel:1;
-        /** tie_high_icg_slp_sel : WT; bitpos: [30]; default: 0;
-         *  need_des
-         */
-        uint32_t tie_high_icg_slp_sel:1;
-        /** update_dig_sys_clk_sel : WT; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t update_dig_sys_clk_sel:1;
+        uint32_t reserved0            : 28;
+        uint32_t update_dig_icg_switch: 1;
+        uint32_t tie_low_icg_slp_sel  : 1;
+        uint32_t tie_high_icg_slp_sel : 1;
+        uint32_t update_dig_sysclk_sel: 1;
     };
     uint32_t val;
 } pmu_imm_sleep_sysclk_reg_t;
 
-/** Type of imm_hp_func_icg register
- *  need_des
- */
 typedef union {
     struct {
-        uint32_t reserved_0:31;
-        /** update_dig_icg_func_en : WT; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t update_dig_icg_func_en:1;
+        uint32_t reserved0             : 31;
+        uint32_t update_dig_icg_func_en: 1;
     };
     uint32_t val;
 } pmu_imm_hp_func_icg_reg_t;
 
-/** Type of imm_hp_apb_icg register
- *  need_des
- */
 typedef union {
     struct {
-        uint32_t reserved_0:31;
-        /** update_dig_icg_apb_en : WT; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t update_dig_icg_apb_en:1;
+        uint32_t reserved0            : 31;
+        uint32_t update_dig_icg_apb_en: 1;
     };
     uint32_t val;
 } pmu_imm_hp_apb_icg_reg_t;
 
-/** Type of imm_modem_icg register
- *  need_des
- */
 typedef union {
     struct {
-        uint32_t reserved_0:31;
-        /** update_dig_icg_modem_en : WT; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t update_dig_icg_modem_en:1;
+        uint32_t reserved0              : 31;
+        uint32_t update_dig_icg_modem_en: 1;
     };
     uint32_t val;
 } pmu_imm_modem_icg_reg_t;
 
-/** Type of imm_lp_icg register
- *  need_des
- */
 typedef union {
     struct {
-        uint32_t reserved_0:30;
-        /** tie_low_lp_rootclk_sel : WT; bitpos: [30]; default: 0;
-         *  need_des
-         */
-        uint32_t tie_low_lp_rootclk_sel:1;
-        /** tie_high_lp_rootclk_sel : WT; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t tie_high_lp_rootclk_sel:1;
+        uint32_t reserved0              : 30;
+        uint32_t tie_low_lp_rootclk_sel : 1;
+        uint32_t tie_high_lp_rootclk_sel: 1;
     };
     uint32_t val;
 } pmu_imm_lp_icg_reg_t;
 
-/** Type of imm_pad_hold_all register
- *  need_des
- */
 typedef union {
     struct {
-        uint32_t reserved_0:28;
-        /** tie_high_lp_pad_hold_all : WT; bitpos: [28]; default: 0;
-         *  need_des
-         */
-        uint32_t tie_high_lp_pad_hold_all:1;
-        /** tie_low_lp_pad_hold_all : WT; bitpos: [29]; default: 0;
-         *  need_des
-         */
-        uint32_t tie_low_lp_pad_hold_all:1;
-        /** tie_high_hp_pad_hold_all : WT; bitpos: [30]; default: 0;
-         *  need_des
-         */
-        uint32_t tie_high_hp_pad_hold_all:1;
-        /** tie_low_hp_pad_hold_all : WT; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t tie_low_hp_pad_hold_all:1;
+        uint32_t reserved0               : 28;
+        uint32_t tie_high_lp_pad_hold_all: 1;
+        uint32_t tie_low_lp_pad_hold_all : 1;
+        uint32_t tie_high_hp_pad_hold_all: 1;
+        uint32_t tie_low_hp_pad_hold_all : 1;
     };
     uint32_t val;
 } pmu_imm_pad_hold_all_reg_t;
 
-/** Type of imm_i2c_iso register
- *  need_des
- */
 typedef union {
     struct {
-        uint32_t reserved_0:30;
-        /** tie_high_i2c_iso_en : WT; bitpos: [30]; default: 0;
-         *  need_des
-         */
-        uint32_t tie_high_i2c_iso_en:1;
-        /** tie_low_i2c_iso_en : WT; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t tie_low_i2c_iso_en:1;
+        uint32_t reserved0          : 30;
+        uint32_t tie_high_i2c_iso_en: 1;
+        uint32_t tie_low_i2c_iso_en : 1;
     };
     uint32_t val;
-} pmu_imm_i2c_iso_reg_t;
+} pmu_imm_i2c_isolate_reg_t;
+
+typedef volatile struct pmu_imm_hw_regmap_t{
+    pmu_imm_hp_clk_power_reg_t     clk_power;
+    pmu_imm_sleep_sysclk_reg_t     sleep_sysclk;
+    pmu_imm_hp_func_icg_reg_t      hp_func_icg;
+    pmu_imm_hp_apb_icg_reg_t       hp_apb_icg;
+    pmu_imm_modem_icg_reg_t        modem_icg;
+    pmu_imm_lp_icg_reg_t           lp_icg;
+    pmu_imm_pad_hold_all_reg_t     pad_hold_all;
+    pmu_imm_i2c_isolate_reg_t      i2c_iso;
+} pmu_imm_hw_regmap_t;
 
-/** Type of power_wait_timer0 register
- *  need_des
- */
 typedef union {
     struct {
-        uint32_t reserved_0:5;
-        /** dg_hp_powerdown_timer : R/W; bitpos: [13:5]; default: 255;
-         *  need_des
-         */
-        uint32_t dg_hp_powerdown_timer:9;
-        /** dg_hp_powerup_timer : R/W; bitpos: [22:14]; default: 255;
-         *  need_des
-         */
-        uint32_t dg_hp_powerup_timer:9;
-        /** dg_hp_wait_timer : R/W; bitpos: [31:23]; default: 255;
-         *  need_des
-         */
-        uint32_t dg_hp_wait_timer:9;
+        uint32_t reserved0      : 5;
+        uint32_t powerdown_timer: 9;
+        uint32_t powerup_timer  : 9;
+        uint32_t wait_timer     : 9;
     };
     uint32_t val;
 } pmu_power_wait_timer0_reg_t;
 
-/** Type of power_wait_timer1 register
- *  need_des
- */
 typedef union {
     struct {
-        uint32_t reserved_0:9;
-        /** dg_lp_powerdown_timer : R/W; bitpos: [15:9]; default: 255;
-         *  need_des
-         */
-        uint32_t dg_lp_powerdown_timer:7;
-        /** dg_lp_powerup_timer : R/W; bitpos: [22:16]; default: 255;
-         *  need_des
-         */
-        uint32_t dg_lp_powerup_timer:7;
-        /** dg_lp_wait_timer : R/W; bitpos: [31:23]; default: 255;
-         *  need_des
-         */
-        uint32_t dg_lp_wait_timer:9;
+        uint32_t reserved0      : 9;
+        uint32_t powerdown_timer: 7;
+        uint32_t powerup_timer  : 7;
+        uint32_t wait_timer     : 9;
     };
     uint32_t val;
 } pmu_power_wait_timer1_reg_t;
 
-/** Type of power_pd_top_cntl register
- *  need_des
- */
 typedef union {
     struct {
-        /** force_top_reset : R/W; bitpos: [0]; default: 0;
-         *  need_des
-         */
-        uint32_t force_top_reset:1;
-        /** force_top_iso : R/W; bitpos: [1]; default: 0;
-         *  need_des
-         */
-        uint32_t force_top_iso:1;
-        /** force_top_pu : R/W; bitpos: [2]; default: 1;
-         *  need_des
-         */
-        uint32_t force_top_pu:1;
-        /** force_top_no_reset : R/W; bitpos: [3]; default: 1;
-         *  need_des
-         */
-        uint32_t force_top_no_reset:1;
-        /** force_top_no_iso : R/W; bitpos: [4]; default: 1;
-         *  need_des
-         */
-        uint32_t force_top_no_iso:1;
-        /** force_top_pd : R/W; bitpos: [5]; default: 0;
-         *  need_des
-         */
-        uint32_t force_top_pd:1;
-        /** pd_top_mask : R/W; bitpos: [10:6]; default: 0;
-         *  need_des
-         */
-        uint32_t pd_top_mask:5;
-        uint32_t reserved_11:16;
-        /** pd_top_pd_mask : R/W; bitpos: [31:27]; default: 0;
-         *  need_des
-         */
-        uint32_t pd_top_pd_mask:5;
+        uint32_t force_reset   : 1;
+        uint32_t force_iso     : 1;
+        uint32_t force_pu      : 1;
+        uint32_t force_no_reset: 1;
+        uint32_t force_no_iso  : 1;
+        uint32_t force_pd      : 1;
+        uint32_t mask          : 5;     /* Invalid of lp peripherals */
+        uint32_t reserved0     : 16;    /* Invalid of lp peripherals */
+        uint32_t pd_mask       : 5;     /* Invalid of lp peripherals */
     };
     uint32_t val;
-} pmu_power_pd_top_cntl_reg_t;
+} pmu_power_domain_cntl_reg_t;
 
-/** Type of power_pd_hpaon_cntl register
- *  need_des
- */
 typedef union {
     struct {
-        /** force_hp_aon_reset : R/W; bitpos: [0]; default: 0;
-         *  need_des
-         */
-        uint32_t force_hp_aon_reset:1;
-        /** force_hp_aon_iso : R/W; bitpos: [1]; default: 0;
-         *  need_des
-         */
-        uint32_t force_hp_aon_iso:1;
-        /** force_hp_aon_pu : R/W; bitpos: [2]; default: 1;
-         *  need_des
-         */
-        uint32_t force_hp_aon_pu:1;
-        /** force_hp_aon_no_reset : R/W; bitpos: [3]; default: 1;
-         *  need_des
-         */
-        uint32_t force_hp_aon_no_reset:1;
-        /** force_hp_aon_no_iso : R/W; bitpos: [4]; default: 1;
-         *  need_des
-         */
-        uint32_t force_hp_aon_no_iso:1;
-        /** force_hp_aon_pd : R/W; bitpos: [5]; default: 0;
-         *  need_des
-         */
-        uint32_t force_hp_aon_pd:1;
-        /** pd_hp_aon_mask : R/W; bitpos: [10:6]; default: 0;
-         *  need_des
-         */
-        uint32_t pd_hp_aon_mask:5;
-        uint32_t reserved_11:16;
-        /** pd_hp_aon_pd_mask : R/W; bitpos: [31:27]; default: 0;
-         *  need_des
-         */
-        uint32_t pd_hp_aon_pd_mask:5;
+        uint32_t force_hp_mem_iso   : 4;
+        uint32_t force_hp_mem_pd    : 4;
+        uint32_t reserved0          : 16;
+        uint32_t force_hp_mem_no_iso: 4;
+        uint32_t force_hp_mem_pu    : 4;
     };
     uint32_t val;
-} pmu_power_pd_hpaon_cntl_reg_t;
+} pmu_power_memory_cntl_reg_t;
 
-/** Type of power_pd_hpcpu_cntl register
- *  need_des
- */
 typedef union {
     struct {
-        /** force_hp_cpu_reset : R/W; bitpos: [0]; default: 0;
-         *  need_des
-         */
-        uint32_t force_hp_cpu_reset:1;
-        /** force_hp_cpu_iso : R/W; bitpos: [1]; default: 0;
-         *  need_des
-         */
-        uint32_t force_hp_cpu_iso:1;
-        /** force_hp_cpu_pu : R/W; bitpos: [2]; default: 1;
-         *  need_des
-         */
-        uint32_t force_hp_cpu_pu:1;
-        /** force_hp_cpu_no_reset : R/W; bitpos: [3]; default: 1;
-         *  need_des
-         */
-        uint32_t force_hp_cpu_no_reset:1;
-        /** force_hp_cpu_no_iso : R/W; bitpos: [4]; default: 1;
-         *  need_des
-         */
-        uint32_t force_hp_cpu_no_iso:1;
-        /** force_hp_cpu_pd : R/W; bitpos: [5]; default: 0;
-         *  need_des
-         */
-        uint32_t force_hp_cpu_pd:1;
-        /** pd_hp_cpu_mask : R/W; bitpos: [10:6]; default: 0;
-         *  need_des
-         */
-        uint32_t pd_hp_cpu_mask:5;
-        uint32_t reserved_11:16;
-        /** pd_hp_cpu_pd_mask : R/W; bitpos: [31:27]; default: 0;
-         *  need_des
-         */
-        uint32_t pd_hp_cpu_pd_mask:5;
+        uint32_t mem2_pd_mask: 5;
+        uint32_t mem1_pd_mask: 5;
+        uint32_t mem0_pd_mask: 5;
+        uint32_t reserved0   : 2;
+        uint32_t mem2_mask   : 5;
+        uint32_t mem1_mask   : 5;
+        uint32_t mem0_mask   : 5;
     };
     uint32_t val;
-} pmu_power_pd_hpcpu_cntl_reg_t;
+} pmu_power_memory_mask_reg_t;
 
-/** Type of power_pd_hpperi_reserve register
- *  need_des
- */
-typedef union {
-    struct {
-        /** hp_peri_reserve : WT; bitpos: [31:0]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_peri_reserve:32;
-    };
-    uint32_t val;
-} pmu_power_pd_hpperi_reserve_reg_t;
-
-/** Type of power_pd_hpwifi_cntl register
- *  need_des
- */
 typedef union {
     struct {
-        /** force_hp_wifi_reset : R/W; bitpos: [0]; default: 0;
-         *  need_des
-         */
-        uint32_t force_hp_wifi_reset:1;
-        /** force_hp_wifi_iso : R/W; bitpos: [1]; default: 0;
-         *  need_des
-         */
-        uint32_t force_hp_wifi_iso:1;
-        /** force_hp_wifi_pu : R/W; bitpos: [2]; default: 1;
-         *  need_des
-         */
-        uint32_t force_hp_wifi_pu:1;
-        /** force_hp_wifi_no_reset : R/W; bitpos: [3]; default: 1;
-         *  need_des
-         */
-        uint32_t force_hp_wifi_no_reset:1;
-        /** force_hp_wifi_no_iso : R/W; bitpos: [4]; default: 1;
-         *  need_des
-         */
-        uint32_t force_hp_wifi_no_iso:1;
-        /** force_hp_wifi_pd : R/W; bitpos: [5]; default: 0;
-         *  need_des
-         */
-        uint32_t force_hp_wifi_pd:1;
-        /** pd_hp_wifi_mask : R/W; bitpos: [10:6]; default: 0;
-         *  need_des
-         */
-        uint32_t pd_hp_wifi_mask:5;
-        uint32_t reserved_11:16;
-        /** pd_hp_wifi_pd_mask : R/W; bitpos: [31:27]; default: 0;
-         *  need_des
-         */
-        uint32_t pd_hp_wifi_pd_mask:5;
-    };
-    uint32_t val;
-} pmu_power_pd_hpwifi_cntl_reg_t;
-
-/** Type of power_pd_lpperi_cntl register
- *  need_des
- */
-typedef union {
-    struct {
-        /** force_lp_peri_reset : R/W; bitpos: [0]; default: 0;
-         *  need_des
-         */
-        uint32_t force_lp_peri_reset:1;
-        /** force_lp_peri_iso : R/W; bitpos: [1]; default: 0;
-         *  need_des
-         */
-        uint32_t force_lp_peri_iso:1;
-        /** force_lp_peri_pu : R/W; bitpos: [2]; default: 1;
-         *  need_des
-         */
-        uint32_t force_lp_peri_pu:1;
-        /** force_lp_peri_no_reset : R/W; bitpos: [3]; default: 1;
-         *  need_des
-         */
-        uint32_t force_lp_peri_no_reset:1;
-        /** force_lp_peri_no_iso : R/W; bitpos: [4]; default: 1;
-         *  need_des
-         */
-        uint32_t force_lp_peri_no_iso:1;
-        /** force_lp_peri_pd : R/W; bitpos: [5]; default: 0;
-         *  need_des
-         */
-        uint32_t force_lp_peri_pd:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} pmu_power_pd_lpperi_cntl_reg_t;
-
-/** Type of power_pd_mem_cntl register
- *  need_des
- */
-typedef union {
-    struct {
-        /** force_hp_mem_iso : R/W; bitpos: [3:0]; default: 0;
-         *  need_des
-         */
-        uint32_t force_hp_mem_iso:4;
-        /** force_hp_mem_pd : R/W; bitpos: [7:4]; default: 0;
-         *  need_des
-         */
-        uint32_t force_hp_mem_pd:4;
-        uint32_t reserved_8:16;
-        /** force_hp_mem_no_iso : R/W; bitpos: [27:24]; default: 15;
-         *  need_des
-         */
-        uint32_t force_hp_mem_no_iso:4;
-        /** force_hp_mem_pu : R/W; bitpos: [31:28]; default: 15;
-         *  need_des
-         */
-        uint32_t force_hp_mem_pu:4;
-    };
-    uint32_t val;
-} pmu_power_pd_mem_cntl_reg_t;
-
-/** Type of power_pd_mem_mask register
- *  need_des
- */
-typedef union {
-    struct {
-        /** pd_hp_mem2_pd_mask : R/W; bitpos: [4:0]; default: 0;
-         *  need_des
-         */
-        uint32_t pd_hp_mem2_pd_mask:5;
-        /** pd_hp_mem1_pd_mask : R/W; bitpos: [9:5]; default: 0;
-         *  need_des
-         */
-        uint32_t pd_hp_mem1_pd_mask:5;
-        /** pd_hp_mem0_pd_mask : R/W; bitpos: [14:10]; default: 0;
-         *  need_des
-         */
-        uint32_t pd_hp_mem0_pd_mask:5;
-        uint32_t reserved_15:2;
-        /** pd_hp_mem2_mask : R/W; bitpos: [21:17]; default: 0;
-         *  need_des
-         */
-        uint32_t pd_hp_mem2_mask:5;
-        /** pd_hp_mem1_mask : R/W; bitpos: [26:22]; default: 0;
-         *  need_des
-         */
-        uint32_t pd_hp_mem1_mask:5;
-        /** pd_hp_mem0_mask : R/W; bitpos: [31:27]; default: 0;
-         *  need_des
-         */
-        uint32_t pd_hp_mem0_mask:5;
-    };
-    uint32_t val;
-} pmu_power_pd_mem_mask_reg_t;
-
-/** Type of power_hp_pad register
- *  need_des
- */
-typedef union {
-    struct {
-        /** force_hp_pad_no_iso_all : R/W; bitpos: [0]; default: 0;
-         *  need_des
-         */
-        uint32_t force_hp_pad_no_iso_all:1;
-        /** force_hp_pad_iso_all : R/W; bitpos: [1]; default: 0;
-         *  need_des
-         */
-        uint32_t force_hp_pad_iso_all:1;
-        uint32_t reserved_2:30;
+        uint32_t force_hp_pad_no_iso_all: 1;
+        uint32_t force_hp_pad_iso_all   : 1;
+        uint32_t reserved0              : 30;
     };
     uint32_t val;
 } pmu_power_hp_pad_reg_t;
 
-/** Type of power_vdd_spi_cntl register
- *  need_des
- */
 typedef union {
     struct {
-        uint32_t reserved_0:18;
-        /** vdd_spi_pwr_wait : R/W; bitpos: [28:18]; default: 255;
-         *  need_des
-         */
-        uint32_t vdd_spi_pwr_wait:11;
-        /** vdd_spi_pwr_sw : R/W; bitpos: [30:29]; default: 3;
-         *  need_des
-         */
-        uint32_t vdd_spi_pwr_sw:2;
-        /** vdd_spi_pwr_sel_sw : R/W; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t vdd_spi_pwr_sel_sw:1;
+        uint32_t reserved0 : 18;
+        uint32_t pwr_wait  : 11;
+        uint32_t pwr_sw    : 2;
+        uint32_t pwr_sel_sw: 1;
     };
     uint32_t val;
 } pmu_power_vdd_spi_cntl_reg_t;
 
-/** Type of power_ck_wait_cntl register
- *  need_des
- */
 typedef union {
     struct {
-        /** wait_xtl_stable : R/W; bitpos: [15:0]; default: 256;
-         *  need_des
-         */
-        uint32_t wait_xtl_stable:16;
-        /** wait_pll_stable : R/W; bitpos: [31:16]; default: 256;
-         *  need_des
-         */
-        uint32_t wait_pll_stable:16;
+        uint32_t wait_xtal_stable: 16;
+        uint32_t wait_pll_stable : 16;
     };
     uint32_t val;
-} pmu_power_ck_wait_cntl_reg_t;
+} pmu_power_clk_wait_cntl_reg_t;
+
+typedef volatile struct pmu_power_hw_regmap_t{
+    pmu_power_wait_timer0_reg_t    wait_timer0;
+    pmu_power_wait_timer1_reg_t    wait_timer1;
+    pmu_power_domain_cntl_reg_t    hp_pd[5];
+    pmu_power_domain_cntl_reg_t    lp_peri;
+    pmu_power_memory_cntl_reg_t    mem_cntl;
+    pmu_power_memory_mask_reg_t    mem_mask;
+    pmu_power_hp_pad_reg_t         hp_pad;
+    pmu_power_vdd_spi_cntl_reg_t   vdd_spi;
+    pmu_power_clk_wait_cntl_reg_t  clk_wait;
+} pmu_power_hw_regmap_t;
 
-/** Type of slp_wakeup_cntl0 register
- *  need_des
- */
 typedef union {
     struct {
-        uint32_t reserved_0:31;
-        /** sleep_req : WT; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t sleep_req:1;
+        uint32_t reserved0: 31;
+        uint32_t sleep_req: 1;
     };
     uint32_t val;
 } pmu_slp_wakeup_cntl0_reg_t;
 
-/** Type of slp_wakeup_cntl1 register
- *  need_des
- */
 typedef union {
     struct {
-        /** sleep_reject_ena : R/W; bitpos: [30:0]; default: 0;
-         *  need_des
-         */
-        uint32_t sleep_reject_ena:31;
-        /** slp_reject_en : R/W; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t slp_reject_en:1;
+        uint32_t sleep_reject_ena: 31;
+        uint32_t slp_reject_en   : 1;
     };
     uint32_t val;
 } pmu_slp_wakeup_cntl1_reg_t;
 
-/** Type of slp_wakeup_cntl2 register
- *  need_des
- */
 typedef union {
     struct {
-        /** wakeup_ena : R/W; bitpos: [31:0]; default: 0;
-         *  need_des
-         */
-        uint32_t wakeup_ena:32;
-    };
-    uint32_t val;
-} pmu_slp_wakeup_cntl2_reg_t;
-
-/** Type of slp_wakeup_cntl3 register
- *  need_des
- */
-typedef union {
-    struct {
-        /** lp_min_slp_val : R/W; bitpos: [7:0]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_min_slp_val:8;
-        /** hp_min_slp_val : R/W; bitpos: [15:8]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_min_slp_val:8;
-        /** sleep_prt_sel : R/W; bitpos: [17:16]; default: 0;
-         *  need_des
-         */
-        uint32_t sleep_prt_sel:2;
-        uint32_t reserved_18:14;
+        uint32_t lp_min_slp_val: 8;
+        uint32_t hp_min_slp_val: 8;
+        uint32_t sleep_prt_sel : 2;
+        uint32_t reserved0     : 14;
     };
     uint32_t val;
 } pmu_slp_wakeup_cntl3_reg_t;
 
-/** Type of slp_wakeup_cntl4 register
- *  need_des
- */
 typedef union {
     struct {
-        uint32_t reserved_0:31;
-        /** slp_reject_cause_clr : WT; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t slp_reject_cause_clr:1;
+        uint32_t reserved0           : 31;
+        uint32_t slp_reject_cause_clr: 1;
     };
     uint32_t val;
 } pmu_slp_wakeup_cntl4_reg_t;
 
-/** Type of slp_wakeup_cntl5 register
- *  need_des
- */
 typedef union {
     struct {
-        /** modem_wait_target : R/W; bitpos: [19:0]; default: 128;
-         *  need_des
-         */
-        uint32_t modem_wait_target:20;
-        uint32_t reserved_20:4;
-        /** lp_ana_wait_target : R/W; bitpos: [31:24]; default: 1;
-         *  need_des
-         */
-        uint32_t lp_ana_wait_target:8;
+        uint32_t modem_wait_target : 20;
+        uint32_t reserved0         : 4;
+        uint32_t lp_ana_wait_target: 8;
     };
     uint32_t val;
 } pmu_slp_wakeup_cntl5_reg_t;
 
-/** Type of slp_wakeup_cntl6 register
- *  need_des
- */
 typedef union {
     struct {
-        /** soc_wakeup_wait : R/W; bitpos: [19:0]; default: 128;
-         *  need_des
-         */
-        uint32_t soc_wakeup_wait:20;
-        uint32_t reserved_20:10;
-        /** soc_wakeup_wait_cfg : R/W; bitpos: [31:30]; default: 0;
-         *  need_des
-         */
-        uint32_t soc_wakeup_wait_cfg:2;
+        uint32_t soc_wakeup_wait    : 20;
+        uint32_t reserved0          : 10;
+        uint32_t soc_wakeup_wait_cfg: 2;
     };
     uint32_t val;
 } pmu_slp_wakeup_cntl6_reg_t;
 
-/** Type of slp_wakeup_cntl7 register
- *  need_des
- */
 typedef union {
     struct {
-        uint32_t reserved_0:16;
-        /** ana_wait_target : R/W; bitpos: [31:16]; default: 1;
-         *  need_des
-         */
-        uint32_t ana_wait_target:16;
+        uint32_t reserved0      : 16;
+        uint32_t ana_wait_target: 16;
     };
     uint32_t val;
 } pmu_slp_wakeup_cntl7_reg_t;
 
-/** Type of slp_wakeup_status0 register
- *  need_des
- */
-typedef union {
-    struct {
-        /** wakeup_cause : RO; bitpos: [31:0]; default: 0;
-         *  need_des
-         */
-        uint32_t wakeup_cause:32;
-    };
-    uint32_t val;
-} pmu_slp_wakeup_status0_reg_t;
-
-/** Type of slp_wakeup_status1 register
- *  need_des
- */
-typedef union {
-    struct {
-        /** reject_cause : RO; bitpos: [31:0]; default: 0;
-         *  need_des
-         */
-        uint32_t reject_cause:32;
-    };
-    uint32_t val;
-} pmu_slp_wakeup_status1_reg_t;
+typedef volatile struct pmu_wakeup_hw_regmap_t{
+    pmu_slp_wakeup_cntl0_reg_t     cntl0;
+    pmu_slp_wakeup_cntl1_reg_t     cntl1;
+    uint32_t                       cntl2;
+    pmu_slp_wakeup_cntl3_reg_t     cntl3;
+    pmu_slp_wakeup_cntl4_reg_t     cntl4;
+    pmu_slp_wakeup_cntl5_reg_t     cntl5;
+    pmu_slp_wakeup_cntl6_reg_t     cntl6;
+    pmu_slp_wakeup_cntl7_reg_t     cntl7;
+    uint32_t                       status0;
+    uint32_t                       status1;
+} pmu_wakeup_hw_regmap_t;
 
-/** Type of hp_ck_poweron register
- *  need_des
- */
 typedef union {
     struct {
-        /** i2c_por_wait_target : R/W; bitpos: [7:0]; default: 50;
-         *  need_des
-         */
-        uint32_t i2c_por_wait_target:8;
-        uint32_t reserved_8:24;
+        uint32_t i2c_por_wait_target: 8;
+        uint32_t reserved0          : 24;
     };
     uint32_t val;
-} pmu_hp_ck_poweron_reg_t;
+} pmu_hp_clk_poweron_reg_t;
 
-/** Type of hp_ck_cntl register
- *  need_des
- */
 typedef union {
     struct {
-        /** modify_icg_cntl_wait : R/W; bitpos: [7:0]; default: 10;
-         *  need_des
-         */
-        uint32_t modify_icg_cntl_wait:8;
-        /** switch_icg_cntl_wait : R/W; bitpos: [15:8]; default: 10;
-         *  need_des
-         */
-        uint32_t switch_icg_cntl_wait:8;
-        uint32_t reserved_16:16;
+        uint32_t modify_icg_cntl_wait: 8;
+        uint32_t switch_icg_cntl_wait: 8;
+        uint32_t reserved0           : 16;
     };
     uint32_t val;
-} pmu_hp_ck_cntl_reg_t;
+} pmu_hp_clk_cntl_reg_t;
 
-/** Type of por_status register
- *  need_des
- */
 typedef union {
     struct {
-        uint32_t reserved_0:31;
-        /** por_done : RO; bitpos: [31]; default: 1;
-         *  need_des
-         */
-        uint32_t por_done:1;
+        uint32_t reserved0: 31;
+        uint32_t por_done : 1;
     };
     uint32_t val;
 } pmu_por_status_reg_t;
 
-/** Type of rf_pwc register
- *  need_des
- */
 typedef union {
     struct {
-        uint32_t reserved_0:27;
-        /** xpd_perif_i2c : R/W; bitpos: [27]; default: 1;
-         *  need_des
-         */
-        uint32_t xpd_perif_i2c:1;
-        /** xpd_rftx_i2c : R/W; bitpos: [28]; default: 0;
-         *  need_des
-         */
-        uint32_t xpd_rftx_i2c:1;
-        /** xpd_rfrx_i2c : R/W; bitpos: [29]; default: 0;
-         *  need_des
-         */
-        uint32_t xpd_rfrx_i2c:1;
-        /** xpd_rfpll : R/W; bitpos: [30]; default: 0;
-         *  need_des
-         */
-        uint32_t xpd_rfpll:1;
-        /** xpd_force_rfpll : R/W; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t xpd_force_rfpll:1;
+        uint32_t reserved0      : 27;
+        uint32_t xpd_perif_i2c  : 1;
+        uint32_t xpd_rftx_i2c   : 1;
+        uint32_t xpd_rfrx_i2c   : 1;
+        uint32_t xpd_rfpll      : 1;
+        uint32_t xpd_force_rfpll: 1;
     };
     uint32_t val;
 } pmu_rf_pwc_reg_t;
 
-/** Type of vddbat_cfg register
- *  need_des
- */
 typedef union {
     struct {
-        /** vddbat_mode : RO; bitpos: [1:0]; default: 0;
-         *  need_des
-         */
-        uint32_t vddbat_mode:2;
-        uint32_t reserved_2:29;
-        /** vddbat_sw_update : WT; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t vddbat_sw_update:1;
+        uint32_t ana_vddbat_mode  :    2;
+        uint32_t reserved2        :    29;
+        uint32_t vddbat_sw_update :    1;
     };
     uint32_t val;
 } pmu_vddbat_cfg_reg_t;
 
-/** Type of backup_cfg register
- *  need_des
- */
 typedef union {
     struct {
-        uint32_t reserved_0:31;
-        /** backup_sys_clk_no_div : R/W; bitpos: [31]; default: 1;
-         *  need_des
-         */
-        uint32_t backup_sys_clk_no_div:1;
+        uint32_t reserved0          : 31;
+        uint32_t backup_sysclk_nodiv: 1;
     };
     uint32_t val;
 } pmu_backup_cfg_reg_t;
 
-/** Type of int_raw register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:27;
-        /** lp_cpu_exc_int_raw : R/WTC/SS; bitpos: [27]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_cpu_exc_int_raw:1;
-        /** sdio_idle_int_raw : R/WTC/SS; bitpos: [28]; default: 0;
-         *  need_des
-         */
-        uint32_t sdio_idle_int_raw:1;
-        /** sw_int_raw : R/WTC/SS; bitpos: [29]; default: 0;
-         *  need_des
-         */
-        uint32_t sw_int_raw:1;
-        /** soc_sleep_reject_int_raw : R/WTC/SS; bitpos: [30]; default: 0;
-         *  need_des
-         */
-        uint32_t soc_sleep_reject_int_raw:1;
-        /** soc_wakeup_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t soc_wakeup_int_raw:1;
-    };
-    uint32_t val;
-} pmu_int_raw_reg_t;
-
-/** Type of hp_int_st register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:27;
-        /** lp_cpu_exc_int_st : RO; bitpos: [27]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_cpu_exc_int_st:1;
-        /** sdio_idle_int_st : RO; bitpos: [28]; default: 0;
-         *  need_des
-         */
-        uint32_t sdio_idle_int_st:1;
-        /** sw_int_st : RO; bitpos: [29]; default: 0;
-         *  need_des
-         */
-        uint32_t sw_int_st:1;
-        /** soc_sleep_reject_int_st : RO; bitpos: [30]; default: 0;
-         *  need_des
-         */
-        uint32_t soc_sleep_reject_int_st:1;
-        /** soc_wakeup_int_st : RO; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t soc_wakeup_int_st:1;
-    };
-    uint32_t val;
-} pmu_hp_int_st_reg_t;
-
-/** Type of hp_int_ena register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:27;
-        /** lp_cpu_exc_int_ena : R/W; bitpos: [27]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_cpu_exc_int_ena:1;
-        /** sdio_idle_int_ena : R/W; bitpos: [28]; default: 0;
-         *  need_des
-         */
-        uint32_t sdio_idle_int_ena:1;
-        /** sw_int_ena : R/W; bitpos: [29]; default: 0;
-         *  need_des
-         */
-        uint32_t sw_int_ena:1;
-        /** soc_sleep_reject_int_ena : R/W; bitpos: [30]; default: 0;
-         *  need_des
-         */
-        uint32_t soc_sleep_reject_int_ena:1;
-        /** soc_wakeup_int_ena : R/W; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t soc_wakeup_int_ena:1;
-    };
-    uint32_t val;
-} pmu_hp_int_ena_reg_t;
-
-/** Type of hp_int_clr register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:27;
-        /** lp_cpu_exc_int_clr : WT; bitpos: [27]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_cpu_exc_int_clr:1;
-        /** sdio_idle_int_clr : WT; bitpos: [28]; default: 0;
-         *  need_des
-         */
-        uint32_t sdio_idle_int_clr:1;
-        /** sw_int_clr : WT; bitpos: [29]; default: 0;
-         *  need_des
-         */
-        uint32_t sw_int_clr:1;
-        /** soc_sleep_reject_int_clr : WT; bitpos: [30]; default: 0;
-         *  need_des
-         */
-        uint32_t soc_sleep_reject_int_clr:1;
-        /** soc_wakeup_int_clr : WT; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t soc_wakeup_int_clr:1;
-    };
-    uint32_t val;
-} pmu_hp_int_clr_reg_t;
-
-/** Type of lp_int_raw register
- *  need_des
- */
 typedef union {
     struct {
-        uint32_t reserved_0:20;
-        /** lp_cpu_wakeup_int_raw : R/WTC/SS; bitpos: [20]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_cpu_wakeup_int_raw:1;
-        /** modem_switch_active_end_int_raw : R/WTC/SS; bitpos: [21]; default: 0;
-         *  need_des
-         */
-        uint32_t modem_switch_active_end_int_raw:1;
-        /** sleep_switch_active_end_int_raw : R/WTC/SS; bitpos: [22]; default: 0;
-         *  need_des
-         */
-        uint32_t sleep_switch_active_end_int_raw:1;
-        /** sleep_switch_modem_end_int_raw : R/WTC/SS; bitpos: [23]; default: 0;
-         *  need_des
-         */
-        uint32_t sleep_switch_modem_end_int_raw:1;
-        /** modem_switch_sleep_end_int_raw : R/WTC/SS; bitpos: [24]; default: 0;
-         *  need_des
-         */
-        uint32_t modem_switch_sleep_end_int_raw:1;
-        /** active_switch_sleep_end_int_raw : R/WTC/SS; bitpos: [25]; default: 0;
-         *  need_des
-         */
-        uint32_t active_switch_sleep_end_int_raw:1;
-        /** modem_switch_active_start_int_raw : R/WTC/SS; bitpos: [26]; default: 0;
-         *  need_des
-         */
-        uint32_t modem_switch_active_start_int_raw:1;
-        /** sleep_switch_active_start_int_raw : R/WTC/SS; bitpos: [27]; default: 0;
-         *  need_des
-         */
-        uint32_t sleep_switch_active_start_int_raw:1;
-        /** sleep_switch_modem_start_int_raw : R/WTC/SS; bitpos: [28]; default: 0;
-         *  need_des
-         */
-        uint32_t sleep_switch_modem_start_int_raw:1;
-        /** modem_switch_sleep_start_int_raw : R/WTC/SS; bitpos: [29]; default: 0;
-         *  need_des
-         */
-        uint32_t modem_switch_sleep_start_int_raw:1;
-        /** active_switch_sleep_start_int_raw : R/WTC/SS; bitpos: [30]; default: 0;
-         *  need_des
-         */
-        uint32_t active_switch_sleep_start_int_raw:1;
-        /** hp_sw_trigger_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_sw_trigger_int_raw:1;
+        uint32_t reserved0   : 27;
+        uint32_t lp_exception: 1;
+        uint32_t sdio_idle: 1;
+        uint32_t sw       : 1;
+        uint32_t reject   : 1;
+        uint32_t wakeup   : 1;
     };
     uint32_t val;
-} pmu_lp_int_raw_reg_t;
+} pmu_hp_intr_reg_t;
 
-/** Type of lp_int_st register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:20;
-        /** lp_cpu_wakeup_int_st : RO; bitpos: [20]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_cpu_wakeup_int_st:1;
-        /** modem_switch_active_end_int_st : RO; bitpos: [21]; default: 0;
-         *  need_des
-         */
-        uint32_t modem_switch_active_end_int_st:1;
-        /** sleep_switch_active_end_int_st : RO; bitpos: [22]; default: 0;
-         *  need_des
-         */
-        uint32_t sleep_switch_active_end_int_st:1;
-        /** sleep_switch_modem_end_int_st : RO; bitpos: [23]; default: 0;
-         *  need_des
-         */
-        uint32_t sleep_switch_modem_end_int_st:1;
-        /** modem_switch_sleep_end_int_st : RO; bitpos: [24]; default: 0;
-         *  need_des
-         */
-        uint32_t modem_switch_sleep_end_int_st:1;
-        /** active_switch_sleep_end_int_st : RO; bitpos: [25]; default: 0;
-         *  need_des
-         */
-        uint32_t active_switch_sleep_end_int_st:1;
-        /** modem_switch_active_start_int_st : RO; bitpos: [26]; default: 0;
-         *  need_des
-         */
-        uint32_t modem_switch_active_start_int_st:1;
-        /** sleep_switch_active_start_int_st : RO; bitpos: [27]; default: 0;
-         *  need_des
-         */
-        uint32_t sleep_switch_active_start_int_st:1;
-        /** sleep_switch_modem_start_int_st : RO; bitpos: [28]; default: 0;
-         *  need_des
-         */
-        uint32_t sleep_switch_modem_start_int_st:1;
-        /** modem_switch_sleep_start_int_st : RO; bitpos: [29]; default: 0;
-         *  need_des
-         */
-        uint32_t modem_switch_sleep_start_int_st:1;
-        /** active_switch_sleep_start_int_st : RO; bitpos: [30]; default: 0;
-         *  need_des
-         */
-        uint32_t active_switch_sleep_start_int_st:1;
-        /** hp_sw_trigger_int_st : RO; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_sw_trigger_int_st:1;
-    };
-    uint32_t val;
-} pmu_lp_int_st_reg_t;
+typedef volatile struct pmu_hp_ext_hw_regmap_t{
+    pmu_hp_clk_poweron_reg_t   clk_poweron;
+    pmu_hp_clk_cntl_reg_t      clk_cntl;
+    pmu_por_status_reg_t       por_status;
+    pmu_rf_pwc_reg_t           rf_pwc;
+    pmu_vddbat_cfg_reg_t       vddbat_cfg;
+    pmu_backup_cfg_reg_t       backup_cfg;
+    pmu_hp_intr_reg_t          int_raw;
+    pmu_hp_intr_reg_t          int_st;
+    pmu_hp_intr_reg_t          int_ena;
+    pmu_hp_intr_reg_t          int_clr;
+} pmu_hp_ext_hw_regmap_t;
 
-/** Type of lp_int_ena register
- *  need_des
- */
 typedef union {
     struct {
-        uint32_t reserved_0:20;
-        /** lp_cpu_wakeup_int_ena : R/W; bitpos: [20]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_cpu_wakeup_int_ena:1;
-        /** modem_switch_active_end_int_ena : R/W; bitpos: [21]; default: 0;
-         *  need_des
-         */
-        uint32_t modem_switch_active_end_int_ena:1;
-        /** sleep_switch_active_end_int_ena : R/W; bitpos: [22]; default: 0;
-         *  need_des
-         */
-        uint32_t sleep_switch_active_end_int_ena:1;
-        /** sleep_switch_modem_end_int_ena : R/W; bitpos: [23]; default: 0;
-         *  need_des
-         */
-        uint32_t sleep_switch_modem_end_int_ena:1;
-        /** modem_switch_sleep_end_int_ena : R/W; bitpos: [24]; default: 0;
-         *  need_des
-         */
-        uint32_t modem_switch_sleep_end_int_ena:1;
-        /** active_switch_sleep_end_int_ena : R/W; bitpos: [25]; default: 0;
-         *  need_des
-         */
-        uint32_t active_switch_sleep_end_int_ena:1;
-        /** modem_switch_active_start_int_ena : R/W; bitpos: [26]; default: 0;
-         *  need_des
-         */
-        uint32_t modem_switch_active_start_int_ena:1;
-        /** sleep_switch_active_start_int_ena : R/W; bitpos: [27]; default: 0;
-         *  need_des
-         */
-        uint32_t sleep_switch_active_start_int_ena:1;
-        /** sleep_switch_modem_start_int_ena : R/W; bitpos: [28]; default: 0;
-         *  need_des
-         */
-        uint32_t sleep_switch_modem_start_int_ena:1;
-        /** modem_switch_sleep_start_int_ena : R/W; bitpos: [29]; default: 0;
-         *  need_des
-         */
-        uint32_t modem_switch_sleep_start_int_ena:1;
-        /** active_switch_sleep_start_int_ena : R/W; bitpos: [30]; default: 0;
-         *  need_des
-         */
-        uint32_t active_switch_sleep_start_int_ena:1;
-        /** hp_sw_trigger_int_ena : R/W; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_sw_trigger_int_ena:1;
+        uint32_t reserved0                : 20;
+        uint32_t lp_wakeup                : 1;
+        uint32_t modem_switch_active_end  : 1;
+        uint32_t sleep_switch_active_end  : 1;
+        uint32_t sleep_switch_modem_end   : 1;
+        uint32_t modem_switch_sleep_end   : 1;
+        uint32_t active_switch_sleep_end  : 1;
+        uint32_t modem_switch_active_start: 1;
+        uint32_t sleep_switch_active_start: 1;
+        uint32_t sleep_switch_modem_start : 1;
+        uint32_t modem_switch_sleep_start : 1;
+        uint32_t active_switch_sleep_start: 1;
+        uint32_t hp_sw_trigger            : 1;
     };
     uint32_t val;
-} pmu_lp_int_ena_reg_t;
+} pmu_lp_intr_reg_t;
 
-/** Type of lp_int_clr register
- *  need_des
- */
 typedef union {
     struct {
-        uint32_t reserved_0:20;
-        /** lp_cpu_wakeup_int_clr : WT; bitpos: [20]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_cpu_wakeup_int_clr:1;
-        /** modem_switch_active_end_int_clr : WT; bitpos: [21]; default: 0;
-         *  need_des
-         */
-        uint32_t modem_switch_active_end_int_clr:1;
-        /** sleep_switch_active_end_int_clr : WT; bitpos: [22]; default: 0;
-         *  need_des
-         */
-        uint32_t sleep_switch_active_end_int_clr:1;
-        /** sleep_switch_modem_end_int_clr : WT; bitpos: [23]; default: 0;
-         *  need_des
-         */
-        uint32_t sleep_switch_modem_end_int_clr:1;
-        /** modem_switch_sleep_end_int_clr : WT; bitpos: [24]; default: 0;
-         *  need_des
-         */
-        uint32_t modem_switch_sleep_end_int_clr:1;
-        /** active_switch_sleep_end_int_clr : WT; bitpos: [25]; default: 0;
-         *  need_des
-         */
-        uint32_t active_switch_sleep_end_int_clr:1;
-        /** modem_switch_active_start_int_clr : WT; bitpos: [26]; default: 0;
-         *  need_des
-         */
-        uint32_t modem_switch_active_start_int_clr:1;
-        /** sleep_switch_active_start_int_clr : WT; bitpos: [27]; default: 0;
-         *  need_des
-         */
-        uint32_t sleep_switch_active_start_int_clr:1;
-        /** sleep_switch_modem_start_int_clr : WT; bitpos: [28]; default: 0;
-         *  need_des
-         */
-        uint32_t sleep_switch_modem_start_int_clr:1;
-        /** modem_switch_sleep_start_int_clr : WT; bitpos: [29]; default: 0;
-         *  need_des
-         */
-        uint32_t modem_switch_sleep_start_int_clr:1;
-        /** active_switch_sleep_start_int_clr : WT; bitpos: [30]; default: 0;
-         *  need_des
-         */
-        uint32_t active_switch_sleep_start_int_clr:1;
-        /** hp_sw_trigger_int_clr : WT; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_sw_trigger_int_clr:1;
-    };
-    uint32_t val;
-} pmu_lp_int_clr_reg_t;
-
-/** Type of lp_cpu_pwr0 register
- *  need_des
- */
-typedef union {
-    struct {
-        /** lp_cpu_waiti_rdy : RO; bitpos: [0]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_cpu_waiti_rdy:1;
-        /** lp_cpu_stall_rdy : RO; bitpos: [1]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_cpu_stall_rdy:1;
-        uint32_t reserved_2:16;
-        /** lp_cpu_force_stall : R/W; bitpos: [18]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_cpu_force_stall:1;
-        /** lp_cpu_slp_waiti_flag_en : R/W; bitpos: [19]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_cpu_slp_waiti_flag_en:1;
-        /** lp_cpu_slp_stall_flag_en : R/W; bitpos: [20]; default: 1;
-         *  need_des
-         */
-        uint32_t lp_cpu_slp_stall_flag_en:1;
-        /** lp_cpu_slp_stall_wait : R/W; bitpos: [28:21]; default: 255;
-         *  need_des
-         */
-        uint32_t lp_cpu_slp_stall_wait:8;
-        /** lp_cpu_slp_stall_en : R/W; bitpos: [29]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_cpu_slp_stall_en:1;
-        /** lp_cpu_slp_reset_en : R/W; bitpos: [30]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_cpu_slp_reset_en:1;
-        /** lp_cpu_slp_bypass_intr_en : R/W; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_cpu_slp_bypass_intr_en:1;
+        uint32_t waiti_rdy         : 1;
+        uint32_t stall_rdy         : 1;
+        uint32_t reserved0         : 16;
+        uint32_t force_stall       : 1;
+        uint32_t slp_waiti_flag_en : 1;
+        uint32_t slp_stall_flag_en : 1;
+        uint32_t slp_stall_wait    : 8;
+        uint32_t slp_stall_en      : 1;
+        uint32_t slp_reset_en      : 1;
+        uint32_t slp_bypass_intr_en: 1;
     };
     uint32_t val;
 } pmu_lp_cpu_pwr0_reg_t;
 
-/** Type of lp_cpu_pwr1 register
- *  need_des
- */
 typedef union {
     struct {
-        /** lp_cpu_wakeup_en : R/W; bitpos: [15:0]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_cpu_wakeup_en:16;
-        uint32_t reserved_16:15;
-        /** lp_cpu_sleep_req : WT; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_cpu_sleep_req:1;
+        uint32_t wakeup_en: 16;
+        uint32_t reserved0: 15;
+        uint32_t sleep_req: 1;
     };
     uint32_t val;
 } pmu_lp_cpu_pwr1_reg_t;
 
-/** Type of hp_lp_cpu_comm register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:30;
-        /** lp_trigger_hp : WT; bitpos: [30]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_trigger_hp:1;
-        /** hp_trigger_lp : WT; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t hp_trigger_lp:1;
-    };
-    uint32_t val;
-} pmu_hp_lp_cpu_comm_reg_t;
-
-/** Type of hp_regulator_cfg register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:31;
-        /** dig_regulator_en_cal : R/W; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t dig_regulator_en_cal:1;
-    };
-    uint32_t val;
-} pmu_hp_regulator_cfg_reg_t;
-
-/** Type of main_state register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:11;
-        /** main_last_st_state : RO; bitpos: [17:11]; default: 1;
-         *  need_des
-         */
-        uint32_t main_last_st_state:7;
-        /** main_tar_st_state : RO; bitpos: [24:18]; default: 4;
-         *  need_des
-         */
-        uint32_t main_tar_st_state:7;
-        /** main_cur_st_state : RO; bitpos: [31:25]; default: 4;
-         *  need_des
-         */
-        uint32_t main_cur_st_state:7;
-    };
-    uint32_t val;
-} pmu_main_state_reg_t;
-
-/** Type of pwr_state register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:13;
-        /** backup_st_state : RO; bitpos: [17:13]; default: 1;
-         *  need_des
-         */
-        uint32_t backup_st_state:5;
-        /** lp_pwr_st_state : RO; bitpos: [22:18]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_pwr_st_state:5;
-        /** hp_pwr_st_state : RO; bitpos: [31:23]; default: 1;
-         *  need_des
-         */
-        uint32_t hp_pwr_st_state:9;
-    };
-    uint32_t val;
-} pmu_pwr_state_reg_t;
-
-/** Type of date register
- *  need_des
- */
-typedef union {
-    struct {
-        /** pmu_date : R/W; bitpos: [30:0]; default: 35688960;
-         *  need_des
-         */
-        uint32_t pmu_date:31;
-        /** clk_en : R/W; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t clk_en:1;
-    };
-    uint32_t val;
-} pmu_date_reg_t;
-
-
-/** Group: status_register */
-/** Type of clk_state0 register
- *  need_des
- */
-typedef union {
-    struct {
-        /** stable_xpd_bbpll_state : RO; bitpos: [0]; default: 1;
-         *  need_des
-         */
-        uint32_t stable_xpd_bbpll_state:1;
-        /** stable_xpd_xtal_state : RO; bitpos: [1]; default: 1;
-         *  need_des
-         */
-        uint32_t stable_xpd_xtal_state:1;
-        uint32_t reserved_2:13;
-        /** sys_clk_slp_sel_state : RO; bitpos: [15]; default: 0;
-         *  need_des
-         */
-        uint32_t sys_clk_slp_sel_state:1;
-        /** sys_clk_sel_state : RO; bitpos: [17:16]; default: 0;
-         *  need_des
-         */
-        uint32_t sys_clk_sel_state:2;
-        /** sys_clk_no_div_state : RO; bitpos: [18]; default: 0;
-         *  need_des
-         */
-        uint32_t sys_clk_no_div_state:1;
-        /** icg_sys_clk_en_state : RO; bitpos: [19]; default: 0;
-         *  need_des
-         */
-        uint32_t icg_sys_clk_en_state:1;
-        /** icg_modem_switch_state : RO; bitpos: [20]; default: 0;
-         *  need_des
-         */
-        uint32_t icg_modem_switch_state:1;
-        /** icg_modem_code_state : RO; bitpos: [22:21]; default: 0;
-         *  need_des
-         */
-        uint32_t icg_modem_code_state:2;
-        /** icg_slp_sel_state : RO; bitpos: [23]; default: 0;
-         *  need_des
-         */
-        uint32_t icg_slp_sel_state:1;
-        /** icg_global_xtal_state : RO; bitpos: [24]; default: 0;
-         *  need_des
-         */
-        uint32_t icg_global_xtal_state:1;
-        /** icg_global_pll_state : RO; bitpos: [25]; default: 0;
-         *  need_des
-         */
-        uint32_t icg_global_pll_state:1;
-        /** ana_i2c_iso_en_state : RO; bitpos: [26]; default: 0;
-         *  need_des
-         */
-        uint32_t ana_i2c_iso_en_state:1;
-        /** ana_i2c_retention_state : RO; bitpos: [27]; default: 0;
-         *  need_des
-         */
-        uint32_t ana_i2c_retention_state:1;
-        /** ana_xpd_bb_i2c_state : RO; bitpos: [28]; default: 0;
-         *  need_des
-         */
-        uint32_t ana_xpd_bb_i2c_state:1;
-        /** ana_xpd_bbpll_i2c_state : RO; bitpos: [29]; default: 0;
-         *  need_des
-         */
-        uint32_t ana_xpd_bbpll_i2c_state:1;
-        /** ana_xpd_bbpll_state : RO; bitpos: [30]; default: 0;
-         *  need_des
-         */
-        uint32_t ana_xpd_bbpll_state:1;
-        /** ana_xpd_xtal_state : RO; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t ana_xpd_xtal_state:1;
-    };
-    uint32_t val;
-} pmu_clk_state0_reg_t;
-
-/** Type of clk_state1 register
- *  need_des
- */
-typedef union {
-    struct {
-        /** icg_func_en_state : RO; bitpos: [31:0]; default: 4294967295;
-         *  need_des
-         */
-        uint32_t icg_func_en_state:32;
-    };
-    uint32_t val;
-} pmu_clk_state1_reg_t;
-
-/** Type of clk_state2 register
- *  need_des
- */
-typedef union {
-    struct {
-        /** icg_apb_en_state : RO; bitpos: [31:0]; default: 4294967295;
-         *  need_des
-         */
-        uint32_t icg_apb_en_state:32;
-    };
-    uint32_t val;
-} pmu_clk_state2_reg_t;
-
-/** Type of vdd_spi_status register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:31;
-        /** stable_vdd_spi_pwr_drv : RO; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t stable_vdd_spi_pwr_drv:1;
-    };
-    uint32_t val;
-} pmu_vdd_spi_status_reg_t;
-
+typedef volatile struct pmu_lp_ext_hw_regmap_t{
+    pmu_lp_intr_reg_t          int_raw;
+    pmu_lp_intr_reg_t          int_st;
+    pmu_lp_intr_reg_t          int_ena;
+    pmu_lp_intr_reg_t          int_clr;
+    pmu_lp_cpu_pwr0_reg_t      pwr0;
+    pmu_lp_cpu_pwr1_reg_t      pwr1;
+} pmu_lp_ext_hw_regmap_t;
 
 typedef struct {
-    volatile pmu_hp_active_dig_power_reg_t hp_active_dig_power;
-    volatile pmu_hp_active_icg_hp_func_reg_t hp_active_icg_hp_func;
-    volatile pmu_hp_active_icg_hp_apb_reg_t hp_active_icg_hp_apb;
-    volatile pmu_hp_active_icg_modem_reg_t hp_active_icg_modem;
-    volatile pmu_hp_active_hp_sys_cntl_reg_t hp_active_hp_sys_cntl;
-    volatile pmu_hp_active_hp_ck_power_reg_t hp_active_hp_ck_power;
-    volatile pmu_hp_active_bias_reg_t hp_active_bias;
-    volatile pmu_hp_active_backup_reg_t hp_active_backup;
-    volatile pmu_hp_active_backup_clk_reg_t hp_active_backup_clk;
-    volatile pmu_hp_active_sysclk_reg_t hp_active_sysclk;
-    volatile pmu_hp_active_hp_regulator0_reg_t hp_active_hp_regulator0;
-    volatile pmu_hp_active_hp_regulator1_reg_t hp_active_hp_regulator1;
-    volatile pmu_hp_active_xtal_reg_t hp_active_xtal;
-    volatile pmu_hp_modem_dig_power_reg_t hp_modem_dig_power;
-    volatile pmu_hp_modem_icg_hp_func_reg_t hp_modem_icg_hp_func;
-    volatile pmu_hp_modem_icg_hp_apb_reg_t hp_modem_icg_hp_apb;
-    volatile pmu_hp_modem_icg_modem_reg_t hp_modem_icg_modem;
-    volatile pmu_hp_modem_hp_sys_cntl_reg_t hp_modem_hp_sys_cntl;
-    volatile pmu_hp_modem_hp_ck_power_reg_t hp_modem_hp_ck_power;
-    volatile pmu_hp_modem_bias_reg_t hp_modem_bias;
-    volatile pmu_hp_modem_backup_reg_t hp_modem_backup;
-    volatile pmu_hp_modem_backup_clk_reg_t hp_modem_backup_clk;
-    volatile pmu_hp_modem_sysclk_reg_t hp_modem_sysclk;
-    volatile pmu_hp_modem_hp_regulator0_reg_t hp_modem_hp_regulator0;
-    volatile pmu_hp_modem_hp_regulator1_reg_t hp_modem_hp_regulator1;
-    volatile pmu_hp_modem_xtal_reg_t hp_modem_xtal;
-    volatile pmu_hp_sleep_dig_power_reg_t hp_sleep_dig_power;
-    volatile pmu_hp_sleep_icg_hp_func_reg_t hp_sleep_icg_hp_func;
-    volatile pmu_hp_sleep_icg_hp_apb_reg_t hp_sleep_icg_hp_apb;
-    volatile pmu_hp_sleep_icg_modem_reg_t hp_sleep_icg_modem;
-    volatile pmu_hp_sleep_hp_sys_cntl_reg_t hp_sleep_hp_sys_cntl;
-    volatile pmu_hp_sleep_hp_ck_power_reg_t hp_sleep_hp_ck_power;
-    volatile pmu_hp_sleep_bias_reg_t hp_sleep_bias;
-    volatile pmu_hp_sleep_backup_reg_t hp_sleep_backup;
-    volatile pmu_hp_sleep_backup_clk_reg_t hp_sleep_backup_clk;
-    volatile pmu_hp_sleep_sysclk_reg_t hp_sleep_sysclk;
-    volatile pmu_hp_sleep_hp_regulator0_reg_t hp_sleep_hp_regulator0;
-    volatile pmu_hp_sleep_hp_regulator1_reg_t hp_sleep_hp_regulator1;
-    volatile pmu_hp_sleep_xtal_reg_t hp_sleep_xtal;
-    volatile pmu_hp_sleep_lp_regulator0_reg_t hp_sleep_lp_regulator0;
-    volatile pmu_hp_sleep_lp_regulator1_reg_t hp_sleep_lp_regulator1;
-    volatile pmu_hp_sleep_lp_dcdc_reserve_reg_t hp_sleep_lp_dcdc_reserve;
-    volatile pmu_hp_sleep_lp_dig_power_reg_t hp_sleep_lp_dig_power;
-    volatile pmu_hp_sleep_lp_ck_power_reg_t hp_sleep_lp_ck_power;
-    volatile pmu_lp_sleep_lp_bias_reserve_reg_t lp_sleep_lp_bias_reserve;
-    volatile pmu_lp_sleep_lp_regulator0_reg_t lp_sleep_lp_regulator0;
-    volatile pmu_lp_sleep_lp_regulator1_reg_t lp_sleep_lp_regulator1;
-    volatile pmu_lp_sleep_xtal_reg_t lp_sleep_xtal;
-    volatile pmu_lp_sleep_lp_dig_power_reg_t lp_sleep_lp_dig_power;
-    volatile pmu_lp_sleep_lp_ck_power_reg_t lp_sleep_lp_ck_power;
-    volatile pmu_lp_sleep_bias_reg_t lp_sleep_bias;
-    volatile pmu_imm_hp_ck_power_reg_t imm_hp_ck_power;
-    volatile pmu_imm_sleep_sysclk_reg_t imm_sleep_sysclk;
-    volatile pmu_imm_hp_func_icg_reg_t imm_hp_func_icg;
-    volatile pmu_imm_hp_apb_icg_reg_t imm_hp_apb_icg;
-    volatile pmu_imm_modem_icg_reg_t imm_modem_icg;
-    volatile pmu_imm_lp_icg_reg_t imm_lp_icg;
-    volatile pmu_imm_pad_hold_all_reg_t imm_pad_hold_all;
-    volatile pmu_imm_i2c_iso_reg_t imm_i2c_iso;
-    volatile pmu_power_wait_timer0_reg_t power_wait_timer0;
-    volatile pmu_power_wait_timer1_reg_t power_wait_timer1;
-    volatile pmu_power_pd_top_cntl_reg_t power_pd_top_cntl;
-    volatile pmu_power_pd_hpaon_cntl_reg_t power_pd_hpaon_cntl;
-    volatile pmu_power_pd_hpcpu_cntl_reg_t power_pd_hpcpu_cntl;
-    volatile pmu_power_pd_hpperi_reserve_reg_t power_pd_hpperi_reserve;
-    volatile pmu_power_pd_hpwifi_cntl_reg_t power_pd_hpwifi_cntl;
-    volatile pmu_power_pd_lpperi_cntl_reg_t power_pd_lpperi_cntl;
-    volatile pmu_power_pd_mem_cntl_reg_t power_pd_mem_cntl;
-    volatile pmu_power_pd_mem_mask_reg_t power_pd_mem_mask;
-    volatile pmu_power_hp_pad_reg_t power_hp_pad;
-    volatile pmu_power_vdd_spi_cntl_reg_t power_vdd_spi_cntl;
-    volatile pmu_power_ck_wait_cntl_reg_t power_ck_wait_cntl;
-    volatile pmu_slp_wakeup_cntl0_reg_t slp_wakeup_cntl0;
-    volatile pmu_slp_wakeup_cntl1_reg_t slp_wakeup_cntl1;
-    volatile pmu_slp_wakeup_cntl2_reg_t slp_wakeup_cntl2;
-    volatile pmu_slp_wakeup_cntl3_reg_t slp_wakeup_cntl3;
-    volatile pmu_slp_wakeup_cntl4_reg_t slp_wakeup_cntl4;
-    volatile pmu_slp_wakeup_cntl5_reg_t slp_wakeup_cntl5;
-    volatile pmu_slp_wakeup_cntl6_reg_t slp_wakeup_cntl6;
-    volatile pmu_slp_wakeup_cntl7_reg_t slp_wakeup_cntl7;
-    volatile pmu_slp_wakeup_status0_reg_t slp_wakeup_status0;
-    volatile pmu_slp_wakeup_status1_reg_t slp_wakeup_status1;
-    volatile pmu_hp_ck_poweron_reg_t hp_ck_poweron;
-    volatile pmu_hp_ck_cntl_reg_t hp_ck_cntl;
-    volatile pmu_por_status_reg_t por_status;
-    volatile pmu_rf_pwc_reg_t rf_pwc;
-    volatile pmu_vddbat_cfg_reg_t vddbat_cfg;
-    volatile pmu_backup_cfg_reg_t backup_cfg;
-    volatile pmu_int_raw_reg_t int_raw;
-    volatile pmu_hp_int_st_reg_t hp_int_st;
-    volatile pmu_hp_int_ena_reg_t hp_int_ena;
-    volatile pmu_hp_int_clr_reg_t hp_int_clr;
-    volatile pmu_lp_int_raw_reg_t lp_int_raw;
-    volatile pmu_lp_int_st_reg_t lp_int_st;
-    volatile pmu_lp_int_ena_reg_t lp_int_ena;
-    volatile pmu_lp_int_clr_reg_t lp_int_clr;
-    volatile pmu_lp_cpu_pwr0_reg_t lp_cpu_pwr0;
-    volatile pmu_lp_cpu_pwr1_reg_t lp_cpu_pwr1;
-    volatile pmu_hp_lp_cpu_comm_reg_t hp_lp_cpu_comm;
-    volatile pmu_hp_regulator_cfg_reg_t hp_regulator_cfg;
-    volatile pmu_main_state_reg_t main_state;
-    volatile pmu_pwr_state_reg_t pwr_state;
-    volatile pmu_clk_state0_reg_t clk_state0;
-    volatile pmu_clk_state1_reg_t clk_state1;
-    volatile pmu_clk_state2_reg_t clk_state2;
-    volatile pmu_vdd_spi_status_reg_t vdd_spi_status;
-    uint32_t reserved_1a8[149];
-    volatile pmu_date_reg_t date;
+    volatile struct {
+    } common;
+} pmu_hp_lp_hw_regmap_t;
+
+typedef volatile struct pmu_dev_t{
+    pmu_hp_hw_regmap_t     hp_sys[3];
+    pmu_lp_hw_regmap_t     lp_sys[2];
+    pmu_imm_hw_regmap_t    imm;
+    pmu_power_hw_regmap_t  power;
+    pmu_wakeup_hw_regmap_t wakeup;
+    pmu_hp_ext_hw_regmap_t hp_ext;
+    pmu_lp_ext_hw_regmap_t lp_ext;
+
+    union {
+        struct {
+            uint32_t reserved0    : 30;
+            uint32_t lp_trigger_hp: 1;
+            uint32_t hp_trigger_lp: 1;
+        };
+        uint32_t val;
+    } hp_lp_cpu_comm;
+
+    union {
+        struct {
+            uint32_t reserved0           : 31;
+            uint32_t dig_regulator_en_cal: 1;
+        };
+        uint32_t val;
+    } hp_regulator_cfg;
+
+    union {
+        struct {
+            uint32_t reserved0 : 11;
+            uint32_t last_st   : 7;
+            uint32_t target_st : 7;
+            uint32_t current_st: 7;
+        };
+        uint32_t val;
+    } main_state;
+
+    union {
+        struct {
+            uint32_t reserved0: 13;
+            uint32_t backup_st: 5;
+            uint32_t lp_pwr_st: 5;
+            uint32_t hp_pwr_st: 9;
+        };
+        uint32_t val;
+    } pwr_state;
+
+    union {
+        struct {
+            uint32_t stable_xpd_bbpll : 1;
+            uint32_t stable_xpd_xtal  : 1;
+            uint32_t reserved0        : 13;
+            uint32_t sysclk_slp_sel   : 1;
+            uint32_t sysclk_sel       : 2;
+            uint32_t sysclk_nodiv     : 1;
+            uint32_t icg_sysclk_en    : 1;
+            uint32_t icg_modem_switch : 1;
+            uint32_t icg_modem_code   : 2;
+            uint32_t icg_slp_sel      : 1;
+            uint32_t icg_global_xtal  : 1;
+            uint32_t icg_global_pll   : 1;
+            uint32_t ana_i2c_iso_en   : 1;
+            uint32_t ana_i2c_retention: 1;
+            uint32_t ana_xpd_bb_i2c   : 1;
+            uint32_t ana_xpd_bbpll_i2c: 1;
+            uint32_t ana_xpd_bbpll    : 1;
+            uint32_t ana_xpd_xtal     : 1;
+        };
+        uint32_t val;
+    } clk_state0;
+
+    uint32_t clk_state1;
+    uint32_t clk_state2;
+
+    union {
+        struct {
+            uint32_t reserved0             : 31;
+            uint32_t stable_vdd_spi_pwr_drv: 1;
+        };
+        uint32_t val;
+    } vdd_spi_status;
+
+    uint32_t reserved[149];
+
+    union {
+        struct {
+            uint32_t pmu_date: 31;
+            uint32_t clk_en  : 1;
+        };
+        uint32_t val;
+    } date;
 } pmu_dev_t;
 
 extern pmu_dev_t PMU;
 
 #ifndef __cplusplus
 _Static_assert(sizeof(pmu_dev_t) == 0x400, "Invalid size of pmu_dev_t structure");
+
+_Static_assert(offsetof(pmu_dev_t, reserved) == (PMU_VDD_SPI_STATUS_REG - DR_REG_PMU_BASE) + 4, "Invalid size of pmu_dev_t structure");
+
 #endif
 
 #ifdef __cplusplus

components/soc/esp32h2/include/soc/regi2c_bbpll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -18,158 +18,18 @@
 #define I2C_BBPLL           0x66
 #define I2C_BBPLL_HOSTID    0
 
-#define I2C_BBPLL_IR_CAL_DELAY        0
-#define I2C_BBPLL_IR_CAL_DELAY_MSB    3
-#define I2C_BBPLL_IR_CAL_DELAY_LSB    0
-
-#define I2C_BBPLL_IR_CAL_CK_DIV        0
-#define I2C_BBPLL_IR_CAL_CK_DIV_MSB    7
-#define I2C_BBPLL_IR_CAL_CK_DIV_LSB    4
-
-#define I2C_BBPLL_IR_CAL_EXT_CAP        1
-#define I2C_BBPLL_IR_CAL_EXT_CAP_MSB    3
-#define I2C_BBPLL_IR_CAL_EXT_CAP_LSB    0
-
-#define I2C_BBPLL_IR_CAL_ENX_CAP        1
-#define I2C_BBPLL_IR_CAL_ENX_CAP_MSB    4
-#define I2C_BBPLL_IR_CAL_ENX_CAP_LSB    4
-
-#define I2C_BBPLL_IR_CAL_RSTB        1
-#define I2C_BBPLL_IR_CAL_RSTB_MSB    5
-#define I2C_BBPLL_IR_CAL_RSTB_LSB    5
-
-#define I2C_BBPLL_IR_CAL_START        1
-#define I2C_BBPLL_IR_CAL_START_MSB    6
-#define I2C_BBPLL_IR_CAL_START_LSB    6
-
-#define I2C_BBPLL_IR_CAL_UNSTOP        1
-#define I2C_BBPLL_IR_CAL_UNSTOP_MSB    7
-#define I2C_BBPLL_IR_CAL_UNSTOP_LSB    7
-
 #define I2C_BBPLL_OC_REF_DIV        2
 #define I2C_BBPLL_OC_REF_DIV_MSB    3
 #define I2C_BBPLL_OC_REF_DIV_LSB    0
 
-#define I2C_BBPLL_OC_DCHGP        2
-#define I2C_BBPLL_OC_DCHGP_MSB    6
-#define I2C_BBPLL_OC_DCHGP_LSB    4
-
-#define I2C_BBPLL_OC_ENB_FCAL        2
-#define I2C_BBPLL_OC_ENB_FCAL_MSB    7
-#define I2C_BBPLL_OC_ENB_FCAL_LSB    7
-
-#define I2C_BBPLL_OC_DIV_7_0        3
-#define I2C_BBPLL_OC_DIV_7_0_MSB    7
-#define I2C_BBPLL_OC_DIV_7_0_LSB    0
-
-#define I2C_BBPLL_RSTB_DIV_ADC        4
-#define I2C_BBPLL_RSTB_DIV_ADC_MSB    0
-#define I2C_BBPLL_RSTB_DIV_ADC_LSB    0
-
-#define I2C_BBPLL_MODE_HF        4
-#define I2C_BBPLL_MODE_HF_MSB    1
-#define I2C_BBPLL_MODE_HF_LSB    1
-
-#define I2C_BBPLL_DIV_ADC        4
-#define I2C_BBPLL_DIV_ADC_MSB    3
-#define I2C_BBPLL_DIV_ADC_LSB    2
-
-#define I2C_BBPLL_DIV_DAC        4
-#define I2C_BBPLL_DIV_DAC_MSB    4
-#define I2C_BBPLL_DIV_DAC_LSB    4
-
-#define I2C_BBPLL_DIV_CPU        4
-#define I2C_BBPLL_DIV_CPU_MSB    5
-#define I2C_BBPLL_DIV_CPU_LSB    5
-
-#define I2C_BBPLL_OC_ENB_VCON        4
-#define I2C_BBPLL_OC_ENB_VCON_MSB    6
-#define I2C_BBPLL_OC_ENB_VCON_LSB    6
-
-#define I2C_BBPLL_OC_TSCHGP        4
-#define I2C_BBPLL_OC_TSCHGP_MSB    7
-#define I2C_BBPLL_OC_TSCHGP_LSB    7
-
-#define I2C_BBPLL_OC_DR1        5
-#define I2C_BBPLL_OC_DR1_MSB    2
-#define I2C_BBPLL_OC_DR1_LSB    0
-
-#define I2C_BBPLL_OC_DR3        5
-#define I2C_BBPLL_OC_DR3_MSB    6
-#define I2C_BBPLL_OC_DR3_LSB    4
+#define I2C_BBPLL_OC_DIV        3
+#define I2C_BBPLL_OC_DIV_MSB    5
+#define I2C_BBPLL_OC_DIV_LSB    0
 
-#define I2C_BBPLL_EN_USB        5
-#define I2C_BBPLL_EN_USB_MSB    7
-#define I2C_BBPLL_EN_USB_LSB    7
-
-#define I2C_BBPLL_OC_DCUR        6
-#define I2C_BBPLL_OC_DCUR_MSB    2
-#define I2C_BBPLL_OC_DCUR_LSB    0
-
-#define I2C_BBPLL_INC_CUR        6
-#define I2C_BBPLL_INC_CUR_MSB    3
-#define I2C_BBPLL_INC_CUR_LSB    3
-
-#define I2C_BBPLL_OC_DHREF_SEL        6
+#define I2C_BBPLL_OC_DHREF_SEL        5
 #define I2C_BBPLL_OC_DHREF_SEL_MSB    5
 #define I2C_BBPLL_OC_DHREF_SEL_LSB    4
 
-#define I2C_BBPLL_OC_DLREF_SEL        6
+#define I2C_BBPLL_OC_DLREF_SEL        5
 #define I2C_BBPLL_OC_DLREF_SEL_MSB    7
 #define I2C_BBPLL_OC_DLREF_SEL_LSB    6
-
-#define I2C_BBPLL_OR_CAL_CAP        8
-#define I2C_BBPLL_OR_CAL_CAP_MSB    3
-#define I2C_BBPLL_OR_CAL_CAP_LSB    0
-
-#define I2C_BBPLL_OR_CAL_UDF        8
-#define I2C_BBPLL_OR_CAL_UDF_MSB    4
-#define I2C_BBPLL_OR_CAL_UDF_LSB    4
-
-#define I2C_BBPLL_OR_CAL_OVF        8
-#define I2C_BBPLL_OR_CAL_OVF_MSB    5
-#define I2C_BBPLL_OR_CAL_OVF_LSB    5
-
-#define I2C_BBPLL_OR_CAL_END        8
-#define I2C_BBPLL_OR_CAL_END_MSB    6
-#define I2C_BBPLL_OR_CAL_END_LSB    6
-
-#define I2C_BBPLL_OR_LOCK        8
-#define I2C_BBPLL_OR_LOCK_MSB    7
-#define I2C_BBPLL_OR_LOCK_LSB    7
-
-#define I2C_BBPLL_OC_VCO_DBIAS        9
-#define I2C_BBPLL_OC_VCO_DBIAS_MSB    1
-#define I2C_BBPLL_OC_VCO_DBIAS_LSB    0
-
-#define I2C_BBPLL_BBADC_DELAY2        9
-#define I2C_BBPLL_BBADC_DELAY2_MSB    3
-#define I2C_BBPLL_BBADC_DELAY2_LSB    2
-
-#define I2C_BBPLL_BBADC_DVDD        9
-#define I2C_BBPLL_BBADC_DVDD_MSB    5
-#define I2C_BBPLL_BBADC_DVDD_LSB    4
-
-#define I2C_BBPLL_BBADC_DREF        9
-#define I2C_BBPLL_BBADC_DREF_MSB    7
-#define I2C_BBPLL_BBADC_DREF_LSB    6
-
-#define I2C_BBPLL_BBADC_DCUR        10
-#define I2C_BBPLL_BBADC_DCUR_MSB    1
-#define I2C_BBPLL_BBADC_DCUR_LSB    0
-
-#define I2C_BBPLL_BBADC_INPUT_SHORT        10
-#define I2C_BBPLL_BBADC_INPUT_SHORT_MSB    2
-#define I2C_BBPLL_BBADC_INPUT_SHORT_LSB    2
-
-#define I2C_BBPLL_ENT_PLL        10
-#define I2C_BBPLL_ENT_PLL_MSB    3
-#define I2C_BBPLL_ENT_PLL_LSB    3
-
-#define I2C_BBPLL_DTEST        10
-#define I2C_BBPLL_DTEST_MSB    5
-#define I2C_BBPLL_DTEST_LSB    4
-
-#define I2C_BBPLL_ENT_ADC        10
-#define I2C_BBPLL_ENT_ADC_MSB    7
-#define I2C_BBPLL_ENT_ADC_LSB    6

components/soc/esp32h2/include/soc/regi2c_brownout.h

@@ -1,11 +1,13 @@
 /*
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
 #pragma once
 
+#include "regi2c_pmu.h"
+
 /**
  * @file regi2c_brownout.h
  * @brief Register definitions for brownout detector
@@ -14,9 +16,34 @@
  * bus. These definitions are used via macros defined in regi2c_ctrl.h.
  */
 
-#define I2C_BOD            0x61
-#define I2C_BOD_HOSTID     0
+#define I2C_BOD            I2C_PMU
+#define I2C_BOD_HOSTID     I2C_PMU_HOSTID
+
+#define I2C_PMU_OR_DREFL_VBAT       17
+#define I2C_PMU_OR_DREFL_VBAT_MSB   4
+#define I2C_PMU_OR_DREFL_VBAT_LSB   2
+#define I2C_PMU_OR_DREFH_VBAT       17
+#define I2C_PMU_OR_DREFH_VBAT_MSB   7
+#define I2C_PMU_OR_DREFH_VBAT_LSB   5
+
+#define I2C_PMU_OR_XPD_DIGDET       18
+#define I2C_PMU_OR_XPD_DIGDET_MSB   0
+#define I2C_PMU_OR_XPD_DIGDET_MSB   0
+
+#define I2C_PMU_OR_DREFL_DIGDET       18
+#define I2C_PMU_OR_DREFL_DIGDET_MSB   4
+#define I2C_PMU_OR_DREFL_DIGDET_LSB   2
+#define I2C_PMU_OR_DREFH_DIGDET       18
+#define I2C_PMU_OR_DREFH_DIGDET_MSB   7
+#define I2C_PMU_OR_DREFH_DIGDET_LSB   5
+
+#define I2C_PMU_OR_DREFL_VDDA         19
+#define I2C_PMU_OR_DREFL_VDDA_MSB     4
+#define I2C_PMU_OR_DREFL_VDDA_LSB     2
+#define I2C_PMU_OR_DREFH_VDDA         19
+#define I2C_PMU_OR_DREFH_VDDA_MSB     7
+#define I2C_PMU_OR_DREFH_VDDA_LSB     5
 
-#define I2C_BOD_THRESHOLD           0x5
-#define I2C_BOD_THRESHOLD_MSB       2
-#define I2C_BOD_THRESHOLD_LSB       0
+#define I2C_BOD_THRESHOLD           I2C_PMU_OR_DREFL_VDDA
+#define I2C_BOD_THRESHOLD_MSB       I2C_PMU_OR_DREFL_VDDA_MSB
+#define I2C_BOD_THRESHOLD_LSB       I2C_PMU_OR_DREFL_VDDA_LSB

components/soc/esp32h2/include/soc/regi2c_defs.h

@@ -9,10 +9,12 @@
 #include "esp_bit_defs.h"
 
 /* Analog function control register */
+// I2C_MST_ANA_CONF0_REG
 #define I2C_MST_BBPLL_STOP_FORCE_HIGH  (BIT(2))
-#define I2C_MST_BBPLL_STOP_FORCE_LOW  (BIT(3))
+#define I2C_MST_BBPLL_STOP_FORCE_LOW   (BIT(3))
+#define I2C_MST_BBPLL_CAL_DONE         (BIT(24))
 
-#define ANA_CONFIG_REG  0x6000E044
+// I2C_MST_ANA_CONF1_REG
 #define ANA_CONFIG_S    (8)
 #define ANA_CONFIG_M    (0x3FF)
 
@@ -20,7 +22,7 @@
 #define ANA_I2C_BBPLL_M      BIT(17) /* Clear to enable BBPLL */
 
 
-#define ANA_CONFIG2_REG  0x6000E048
+// I2C_MST_ANA_CONF2_REG
 #define ANA_CONFIG2_M    BIT(18)
 
 #define ANA_I2C_SAR_FORCE_PU BIT(16)

components/soc/esp32h2/include/soc/regi2c_lp_bias.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -21,35 +21,3 @@
 #define I2C_ULP_IR_RESETB 0
 #define I2C_ULP_IR_RESETB_MSB 0
 #define I2C_ULP_IR_RESETB_LSB 0
-
-#define I2C_ULP_IR_FORCE_XPD_CK 0
-#define I2C_ULP_IR_FORCE_XPD_CK_MSB 2
-#define I2C_ULP_IR_FORCE_XPD_CK_LSB 2
-
-#define I2C_ULP_IR_FORCE_XPD_IPH 0
-#define I2C_ULP_IR_FORCE_XPD_IPH_MSB 4
-#define I2C_ULP_IR_FORCE_XPD_IPH_LSB 4
-
-#define I2C_ULP_IR_DISABLE_WATCHDOG_CK 0
-#define I2C_ULP_IR_DISABLE_WATCHDOG_CK_MSB 6
-#define I2C_ULP_IR_DISABLE_WATCHDOG_CK_LSB 6
-
-#define I2C_ULP_O_DONE_FLAG 3
-#define I2C_ULP_O_DONE_FLAG_MSB 0
-#define I2C_ULP_O_DONE_FLAG_LSB 0
-
-#define I2C_ULP_BG_O_DONE_FLAG 3
-#define I2C_ULP_BG_O_DONE_FLAG_MSB 3
-#define I2C_ULP_BG_O_DONE_FLAG_LSB 3
-
-#define I2C_ULP_OCODE 4
-#define I2C_ULP_OCODE_MSB 7
-#define I2C_ULP_OCODE_LSB 0
-
-#define I2C_ULP_IR_FORCE_CODE 5
-#define I2C_ULP_IR_FORCE_CODE_MSB 6
-#define I2C_ULP_IR_FORCE_CODE_LSB 6
-
-#define I2C_ULP_EXT_CODE 6
-#define I2C_ULP_EXT_CODE_MSB 7
-#define I2C_ULP_EXT_CODE_LSB 0

components/soc/esp32h2/include/soc/regi2c_pmu.h

@@ -0,0 +1,52 @@
+/*
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+/**
+ * @file regi2c_pmu.h
+ * @brief Register definitions for digital to get rtc voltage & digital voltage
+ *        by setting rtc_dbias_Wak & dig_dbias_wak or by analog self-calibration.
+ */
+
+#define I2C_PMU           0x6d
+#define I2C_PMU_HOSTID    0
+
+#define I2C_PMU_EN_I2C_RTC_DREG        8
+#define I2C_PMU_EN_I2C_RTC_DREG_MSB    0
+#define I2C_PMU_EN_I2C_RTC_DREG_LSB    0
+
+#define I2C_PMU_EN_I2C_DIG_DREG        8
+#define I2C_PMU_EN_I2C_DIG_DREG_MSB    1
+#define I2C_PMU_EN_I2C_DIG_DREG_LSB    1
+
+#define I2C_PMU_EN_I2C_RTC_DREG_SLP        8
+#define I2C_PMU_EN_I2C_RTC_DREG_SLP_MSB    2
+#define I2C_PMU_EN_I2C_RTC_DREG_SLP_LSB    2
+
+#define I2C_PMU_EN_I2C_DIG_DREG_SLP        8
+#define I2C_PMU_EN_I2C_DIG_DREG_SLP_MSB    3
+#define I2C_PMU_EN_I2C_DIG_DREG_SLP_LSB    3
+
+#define I2C_PMU_OR_XPD_RTC_REG            9
+#define I2C_PMU_OR_XPD_RTC_REG_MSB        4
+#define I2C_PMU_OR_XPD_RTC_REG_LSB        4
+
+#define I2C_PMU_OR_XPD_DIG_REG            9
+#define I2C_PMU_OR_XPD_DIG_REG_MSB        5
+#define I2C_PMU_OR_XPD_DIG_REG_LSB        5
+
+#define I2C_PMU_OC_SCK_DCAP        14
+#define I2C_PMU_OC_SCK_DCAP_MSB    7
+#define I2C_PMU_OC_SCK_DCAP_LSB    0
+
+#define I2C_PMU_OR_XPD_TRX        15
+#define I2C_PMU_OR_XPD_TRX_MSB    2
+#define I2C_PMU_OR_XPD_TRX_LSB    2
+
+#define I2C_PMU_SEL_PLL8M_REF        21
+#define I2C_PMU_SEL_PLL8M_REF_MSB    6
+#define I2C_PMU_SEL_PLL8M_REF_LSB    6

components/soc/esp32h2/include/soc/regi2c_saradc.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -18,29 +18,9 @@
 #define I2C_SAR_ADC            0X69
 #define I2C_SAR_ADC_HOSTID     0
 
-#define ADC_SAR1_ENCAL_GND_ADDR 0x7
-#define ADC_SAR1_ENCAL_GND_ADDR_MSB 5
-#define ADC_SAR1_ENCAL_GND_ADDR_LSB 5
-
-#define ADC_SAR2_ENCAL_GND_ADDR 0x7
-#define ADC_SAR2_ENCAL_GND_ADDR_MSB 7
-#define ADC_SAR2_ENCAL_GND_ADDR_LSB 7
-
-#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR 0x1
-#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR_MSB 0x3
-#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR_LSB 0x0
-
-#define ADC_SAR1_INITIAL_CODE_LOW_ADDR  0x0
-#define ADC_SAR1_INITIAL_CODE_LOW_ADDR_MSB  0x7
-#define ADC_SAR1_INITIAL_CODE_LOW_ADDR_LSB  0x0
-
-#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR 0x4
-#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_MSB 0x3
-#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_LSB 0x0
-
-#define ADC_SAR2_INITIAL_CODE_LOW_ADDR  0x3
-#define ADC_SAR2_INITIAL_CODE_LOW_ADDR_MSB  0x7
-#define ADC_SAR2_INITIAL_CODE_LOW_ADDR_LSB  0x0
+#define ADC_SAR1_SAMPLE_CYCLE_ADDR 0x2
+#define ADC_SAR1_SAMPLE_CYCLE_ADDR_MSB 0x2
+#define ADC_SAR1_SAMPLE_CYCLE_ADDR_LSB 0x0
 
 #define ADC_SAR1_DREF_ADDR  0x2
 #define ADC_SAR1_DREF_ADDR_MSB  0x6
@@ -50,30 +30,6 @@
 #define ADC_SAR2_DREF_ADDR_MSB  0x6
 #define ADC_SAR2_DREF_ADDR_LSB  0x4
 
-#define ADC_SAR1_SAMPLE_CYCLE_ADDR 0x2
-#define ADC_SAR1_SAMPLE_CYCLE_ADDR_MSB 0x2
-#define ADC_SAR1_SAMPLE_CYCLE_ADDR_LSB 0x0
-
-#define ADC_SARADC_DTEST_RTC_ADDR 0x7
-#define ADC_SARADC_DTEST_RTC_ADDR_MSB 1
-#define ADC_SARADC_DTEST_RTC_ADDR_LSB 0
-
-#define ADC_SARADC_ENT_TSENS_ADDR 0x7
-#define ADC_SARADC_ENT_TSENS_ADDR_MSB 2
-#define ADC_SARADC_ENT_TSENS_ADDR_LSB 2
-
-#define ADC_SARADC_ENT_RTC_ADDR 0x7
-#define ADC_SARADC_ENT_RTC_ADDR_MSB 3
-#define ADC_SARADC_ENT_RTC_ADDR_LSB 3
-
-#define ADC_SARADC1_ENCAL_REF_ADDR 0x7
-#define ADC_SARADC1_ENCAL_REF_ADDR_MSB 4
-#define ADC_SARADC1_ENCAL_REF_ADDR_LSB 4
-
-#define ADC_SARADC2_ENCAL_REF_ADDR 0x7
-#define ADC_SARADC2_ENCAL_REF_ADDR_MSB 6
-#define ADC_SARADC2_ENCAL_REF_ADDR_LSB 6
-
 #define I2C_SARADC_TSENS_DAC 0x6
 #define I2C_SARADC_TSENS_DAC_MSB 3
-#define I2C_SARADC_TSENS_DAC_LSB 0
+#define I2C_SARADC_TSENS_DAC_LSB 3

components/soc/esp32h2/include/soc/rtc.h

@@ -41,7 +41,6 @@ extern "C" {
  * - rtc_clk: clock switching, calibration
  * - rtc_time: reading RTC counter, conversion between counter values and time
  * - rtc_sleep: entry into sleep modes
- * - rtc_init: initialization
  */
 
 #define MHZ (1000000)
@@ -76,6 +75,8 @@ extern "C" {
 #define SOC_DELAY_RC_FAST_ENABLE            50
 #define SOC_DELAY_RC_FAST_DIGI_SWITCH       5
 #define SOC_DELAY_RC32K_ENABLE              300
+#define SOC_DELAY_LP_PLL_SWITCH             3
+#define SOC_DELAY_LP_PLL_ENABLE             50
 
 /* Core voltage: //TODO: IDF-6254
  * Currently, ESP32H2 never adjust its wake voltage in runtime
@@ -91,8 +92,8 @@ extern "C" {
 #define RTC_CNTL_CK8M_WAIT_DEFAULT  20
 #define RTC_CK8M_ENABLE_WAIT_DEFAULT 5
 
-#define RTC_CNTL_CK8M_DFREQ_DEFAULT  600
-#define RTC_CNTL_SCK_DCAP_DEFAULT    128
+#define RTC_CNTL_CK8M_DFREQ_DEFAULT  860
+#define RTC_CNTL_SCK_DCAP_DEFAULT    85
 #define RTC_CNTL_RC32K_DFREQ_DEFAULT 700
 
 /* Various delays to be programmed into power control state machines */
@@ -198,36 +199,6 @@ typedef struct {
     .rc32k_dfreq = RTC_CNTL_RC32K_DFREQ_DEFAULT, \
 }
 
-typedef struct {
-    uint16_t wifi_powerup_cycles : 7;
-    uint16_t wifi_wait_cycles : 9;
-    uint16_t bt_powerup_cycles : 7;
-    uint16_t bt_wait_cycles : 9;
-    uint16_t cpu_top_powerup_cycles : 7;
-    uint16_t cpu_top_wait_cycles : 9;
-    uint16_t dg_wrap_powerup_cycles : 7;
-    uint16_t dg_wrap_wait_cycles : 9;
-    uint16_t dg_peri_powerup_cycles : 7;
-    uint16_t dg_peri_wait_cycles : 9;
-} rtc_init_config_t;
-
-#define RTC_INIT_CONFIG_DEFAULT() { \
-    .wifi_powerup_cycles = OTHER_BLOCKS_POWERUP, \
-    .wifi_wait_cycles = OTHER_BLOCKS_WAIT, \
-    .bt_powerup_cycles = OTHER_BLOCKS_POWERUP, \
-    .bt_wait_cycles = OTHER_BLOCKS_WAIT, \
-    .cpu_top_powerup_cycles = OTHER_BLOCKS_POWERUP, \
-    .cpu_top_wait_cycles = OTHER_BLOCKS_WAIT, \
-    .dg_wrap_powerup_cycles = OTHER_BLOCKS_POWERUP, \
-    .dg_wrap_wait_cycles = OTHER_BLOCKS_WAIT, \
-    .dg_peri_powerup_cycles = OTHER_BLOCKS_POWERUP, \
-    .dg_peri_wait_cycles = OTHER_BLOCKS_WAIT, \
-}
-
-void rtc_clk_divider_set(uint32_t div);
-
-void rtc_clk_8m_divider_set(uint32_t div);
-
 /**
  * Initialize clocks and set CPU frequency
  *
@@ -284,23 +255,18 @@ bool rtc_clk_32k_enabled(void);
  */
 void rtc_clk_32k_bootstrap(uint32_t cycle);
 
+/**
+ * @brief Enable or disable 32 kHz internal rc oscillator
+ * @param en  true to enable, false to disable
+ */
+void rtc_clk_rc32k_enable(bool enable);
+
 /**
  * @brief Enable or disable 8 MHz internal oscillator
  *
- * Output from 8 MHz internal oscillator is passed into a configurable
- * divider, which by default divides the input clock frequency by 256.
- * Output of the divider may be used as RTC_SLOW_CLK source.
- * Output of the divider is referred to in register descriptions and code as
- * 8md256 or simply d256. Divider values other than 256 may be configured, but
- * this facility is not currently needed, so is not exposed in the code.
- *
- * When 8MHz/256 divided output is not needed, the divider should be disabled
- * to reduce power consumption.
- *
  * @param clk_8m_en true to enable 8MHz generator
- * @param d256_en true to enable /256 divider
  */
-void rtc_clk_8m_enable(bool clk_8m_en, bool d256_en);
+void rtc_clk_8m_enable(bool clk_8m_en);
 
 /**
  * @brief Get the state of 8 MHz internal oscillator
@@ -309,10 +275,16 @@ void rtc_clk_8m_enable(bool clk_8m_en, bool d256_en);
 bool rtc_clk_8m_enabled(void);
 
 /**
- * @brief Get the state of /256 divider which is applied to 8MHz clock
- * @return true if the divided output is enabled
+ * @brief Enable or disable LP_PLL_CLK
+ * @param enable true to enable, false to disable
  */
-bool rtc_clk_8md256_enabled(void);
+void rtc_clk_lp_pll_enable(bool enable);
+
+/**
+ * @brief Select clock source for LP_PLL_CLK
+ * @param clk_src clock source (one of soc_lp_pll_clk_src_t values)
+ */
+void rtc_clk_lp_pll_src_set(soc_lp_pll_clk_src_t clk_src);
 
 /**
  * @brief Select source for RTC_SLOW_CLK
@@ -329,9 +301,10 @@ soc_rtc_slow_clk_src_t rtc_clk_slow_src_get(void);
 /**
  * @brief Get the approximate frequency of RTC_SLOW_CLK, in Hz
  *
- * - if SOC_RTC_SLOW_CLK_SRC_RC_SLOW is selected, returns ~150000
+ * - if SOC_RTC_SLOW_CLK_SRC_RC_SLOW is selected, returns 136000
  * - if SOC_RTC_SLOW_CLK_SRC_XTAL32K is selected, returns 32768
- * - if SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256 is selected, returns ~68000
+ * - if SOC_RTC_SLOW_CLK_SRC_RC32K is selected, returns 32768
+ * - if SOC_RTC_SLOW_CLK_SRC_OSC_SLOW is selected, returns 32768
  *
  * rtc_clk_cal function can be used to get more precise value by comparing
  * RTC_SLOW_CLK frequency to the frequency of main XTAL.
@@ -411,26 +384,30 @@ void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t *out_config);
  */
 void rtc_clk_cpu_freq_set_xtal(void);
 
-/**
- * @brief Store new APB frequency value into RTC_APB_FREQ_REG
- *
- * This function doesn't change any hardware clocks.
- *
- * Functions which perform frequency switching and change APB frequency call
- * this function to update the value of APB frequency stored in RTC_APB_FREQ_REG
- * (one of RTC general purpose retention registers). This should not normally
- * be called from application code.
- *
- * @param apb_freq  new APB frequency, in Hz
- */
-void rtc_clk_apb_freq_update(uint32_t apb_freq);
-
 /**
  * @brief Get the current stored APB frequency.
  * @return The APB frequency value as last set via rtc_clk_apb_freq_update(), in Hz.
  */
 uint32_t rtc_clk_apb_freq_get(void);
 
+/**
+ * @brief Clock calibration function used by rtc_clk_cal
+ *
+ * Calibration of RTC_SLOW_CLK is performed using a special feature of TIMG0.
+ * This feature counts the number of XTAL clock cycles within a given number of
+ * RTC_SLOW_CLK cycles.
+ *
+ * Slow clock calibration feature has two modes of operation: one-off and cycling.
+ * In cycling mode (which is enabled by default on SoC reset), counting of XTAL
+ * cycles within RTC_SLOW_CLK cycle is done continuously. Cycling mode is enabled
+ * using TIMG_RTC_CALI_START_CYCLING bit. In one-off mode counting is performed
+ * once, and TIMG_RTC_CALI_RDY bit is set when counting is done. One-off mode is
+ * enabled using TIMG_RTC_CALI_START bit.
+ *
+ * @param cal_clk which clock to calibrate
+ * @param slowclk_cycles number of slow clock cycles to count
+ * @return number of XTAL clock cycles within the given number of slow clock cycles
+ */
 uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles);
 
 /**
@@ -448,15 +425,6 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles);
  */
 uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slow_clk_cycles);
 
-/**
- * @brief Measure ratio between XTAL frequency and RTC slow clock frequency
- * @param cal_clk slow clock to be measured
- * @param slow_clk_cycles number of slow clock cycles to average
- * @return average ratio between XTAL frequency and slow clock frequency,
- *         Q13.19 fixed point format, or 0 if calibration has timed out.
- */
-uint32_t rtc_clk_cal_ratio(rtc_cal_sel_t cal_clk, uint32_t slow_clk_cycles);
-
 /**
  * @brief Convert time interval from microseconds to RTC_SLOW_CLK cycles
  * @param time_in_us Time interval in microseconds
@@ -529,245 +497,6 @@ bool rtc_dig_8m_enabled(void);
  */
 uint32_t rtc_clk_freq_cal(uint32_t cal_val);
 
-/**
- * @brief Power down flags for rtc_sleep_pd function
- */
-typedef struct {
-    uint32_t dig_fpu : 1;    //!< Set to 1 to power UP digital part in sleep
-    uint32_t rtc_fpu : 1;    //!< Set to 1 to power UP RTC memories in sleep
-    uint32_t cpu_fpu : 1;    //!< Set to 1 to power UP digital memories and CPU in sleep
-    uint32_t i2s_fpu : 1;    //!< Set to 1 to power UP I2S in sleep
-    uint32_t bb_fpu : 1;     //!< Set to 1 to power UP WiFi in sleep
-    uint32_t nrx_fpu : 1;    //!< Set to 1 to power UP WiFi in sleep
-    uint32_t fe_fpu : 1;     //!< Set to 1 to power UP WiFi in sleep
-    uint32_t sram_fpu : 1;    //!< Set to 1 to power UP SRAM in sleep
-    uint32_t rom_ram_fpu : 1; //!< Set to 1 to power UP ROM/IRAM0_DRAM0 in sleep
-} rtc_sleep_pu_config_t;
-
-/**
- * Initializer for rtc_sleep_pu_config_t which sets all flags to the same value
- */
-#define RTC_SLEEP_PU_CONFIG_ALL(val) {\
-    .dig_fpu = (val), \
-    .rtc_fpu = (val), \
-    .cpu_fpu = (val), \
-    .i2s_fpu = (val), \
-    .bb_fpu = (val), \
-    .nrx_fpu = (val), \
-    .fe_fpu = (val), \
-    .sram_fpu = (val), \
-    .rom_ram_fpu = (val), \
-}
-
-void rtc_sleep_pu(rtc_sleep_pu_config_t cfg);
-
-/**
- * @brief sleep configuration for rtc_sleep_init function
- */
-typedef struct {
-    uint32_t lslp_mem_inf_fpu : 1;      //!< force normal voltage in sleep mode (digital domain memory)
-    uint32_t rtc_mem_inf_follow_cpu : 1;//!< keep low voltage in sleep mode (even if ULP/touch is used)
-    uint32_t rtc_fastmem_pd_en : 1;     //!< power down RTC fast memory
-    uint32_t rtc_slowmem_pd_en : 1;     //!< power down RTC slow memory
-    uint32_t rtc_peri_pd_en : 1;        //!< power down RTC peripherals
-    uint32_t wifi_pd_en : 1;            //!< power down WiFi
-    uint32_t bt_pd_en : 1;              //!< power down BT
-    uint32_t cpu_pd_en : 1;             //!< power down CPU, but not restart when lightsleep.
-    uint32_t int_8m_pd_en : 1;          //!< Power down Internal 8M oscillator
-    uint32_t dig_peri_pd_en : 1;        //!< power down digital peripherals
-    uint32_t deep_slp : 1;              //!< power down digital domain
-    uint32_t wdt_flashboot_mod_en : 1;  //!< enable WDT flashboot mode
-    uint32_t dig_dbias_wak : 5;         //!< set bias for digital domain, in active mode
-    uint32_t dig_dbias_slp : 5;         //!< set bias for digital domain, in sleep mode
-    uint32_t rtc_dbias_wak : 5;         //!< set bias for RTC domain, in active mode
-    uint32_t rtc_dbias_slp : 5;         //!< set bias for RTC domain, in sleep mode
-    uint32_t dbg_atten_monitor : 4;     //!< voltage parameter, in monitor mode
-    uint32_t bias_sleep_monitor : 1;    //!< circuit control parameter, in monitor mode
-    uint32_t dbg_atten_slp : 4;         //!< voltage parameter, in sleep mode
-    uint32_t bias_sleep_slp : 1;        //!< circuit control parameter, in sleep mode
-    uint32_t pd_cur_monitor : 1;        //!< circuit control parameter, in monitor mode
-    uint32_t pd_cur_slp : 1;            //!< circuit control parameter, in sleep mode
-    uint32_t vddsdio_pd_en : 1;         //!< power down VDDSDIO regulator
-    uint32_t xtal_fpu : 1;              //!< keep main XTAL powered up in sleep
-    uint32_t deep_slp_reject : 1;       //!< enable deep sleep reject
-    uint32_t light_slp_reject : 1;      //!< enable light sleep reject
-} rtc_sleep_config_t;
-
-#define RTC_SLEEP_PD_DIG                BIT(0)  //!< Deep sleep (power down digital domain)
-#define RTC_SLEEP_PD_RTC_PERIPH         BIT(1)  //!< Power down RTC peripherals
-#define RTC_SLEEP_PD_RTC_SLOW_MEM       BIT(2)  //!< Power down RTC SLOW memory
-#define RTC_SLEEP_PD_RTC_FAST_MEM       BIT(3)  //!< Power down RTC FAST memory
-#define RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU BIT(4)  //!< RTC FAST and SLOW memories are automatically powered up and down along with the CPU
-#define RTC_SLEEP_PD_VDDSDIO            BIT(5)  //!< Power down VDDSDIO regulator
-#define RTC_SLEEP_PD_WIFI               BIT(6)  //!< Power down WIFI
-#define RTC_SLEEP_PD_BT                 BIT(7)  //!< Power down BT
-#define RTC_SLEEP_PD_CPU                BIT(8)  //!< Power down CPU when in lightsleep, but not restart
-#define RTC_SLEEP_PD_DIG_PERIPH         BIT(9)  //!< Power down DIG peripherals
-#define RTC_SLEEP_PD_INT_8M             BIT(10) //!< Power down Internal 8M oscillator
-#define RTC_SLEEP_PD_XTAL               BIT(11) //!< Power down main XTAL
-
-//These flags are not power domains, but will affect some sleep parameters
-#define RTC_SLEEP_DIG_USE_8M            BIT(16)
-#define RTC_SLEEP_USE_ADC_TESEN_MONITOR BIT(17)
-#define RTC_SLEEP_NO_ULTRA_LOW          BIT(18) //!< Avoid using ultra low power in deep sleep, in which RTCIO cannot be used as input, and RTCMEM can't work under high temperature
-
-/**
- * Default initializer for rtc_sleep_config_t
- *
- * This initializer sets all fields to "reasonable" values (e.g. suggested for
- * production use) based on a combination of RTC_SLEEP_PD_x flags.
- *
- * @param RTC_SLEEP_PD_x flags combined using bitwise OR
- */
-void rtc_sleep_get_default_config(uint32_t sleep_flags, rtc_sleep_config_t *out_config);
-
-/**
- * @brief Prepare the chip to enter sleep mode
- *
- * This function configures various power control state machines to handle
- * entry into light sleep or deep sleep mode, switches APB and CPU clock source
- * (usually to XTAL), and sets bias voltages for digital and RTC power domains.
- *
- * This function does not actually enter sleep mode; this is done using
- * rtc_sleep_start function. Software may do some other actions between
- * rtc_sleep_init and rtc_sleep_start, such as set wakeup timer and configure
- * wakeup sources.
- * @param cfg sleep mode configuration
- */
-void rtc_sleep_init(rtc_sleep_config_t cfg);
-
-/**
- * @brief Low level initialize for rtc state machine waiting cycles after waking up
- *
- * This function configures the cycles chip need to wait for internal 8MHz
- * oscillator and external 40MHz crystal. As we configure fixed time for waiting
- * crystal, we need to pass period to calculate cycles. Now this function only
- * used in lightsleep mode.
- *
- * @param slowclk_period re-calibrated slow clock period
- */
-void rtc_sleep_low_init(uint32_t slowclk_period);
-
-/**
- * @brief Set target value of RTC counter for RTC_TIMER_TRIG_EN wakeup source
- * @param t value of RTC counter at which wakeup from sleep will happen;
- *          only the lower 48 bits are used
- */
-void rtc_sleep_set_wakeup_time(uint64_t t);
-
-#define RTC_GPIO_TRIG_EN            BIT(2)  //!< GPIO wakeup
-#define RTC_TIMER_TRIG_EN           BIT(3)  //!< Timer wakeup
-#define RTC_WIFI_TRIG_EN            BIT(5)  //!< WIFI wakeup (light sleep only)
-#define RTC_UART0_TRIG_EN           BIT(6)  //!< UART0 wakeup (light sleep only)
-#define RTC_UART1_TRIG_EN           BIT(7)  //!< UART1 wakeup (light sleep only)
-#define RTC_BT_TRIG_EN              BIT(10) //!< BT wakeup (light sleep only)
-#define RTC_XTAL32K_DEAD_TRIG_EN    BIT(12)
-#define RTC_USB_TRIG_EN             BIT(14)
-#define RTC_BROWNOUT_DET_TRIG_EN    BIT(16)
-
-/**
- * RTC_SLEEP_REJECT_MASK records sleep reject sources supported by chip
- */
-#define RTC_SLEEP_REJECT_MASK (RTC_GPIO_TRIG_EN         | \
-                               RTC_TIMER_TRIG_EN        | \
-                               RTC_WIFI_TRIG_EN         | \
-                               RTC_UART0_TRIG_EN        | \
-                               RTC_UART1_TRIG_EN        | \
-                               RTC_BT_TRIG_EN           | \
-                               RTC_XTAL32K_DEAD_TRIG_EN | \
-                               RTC_USB_TRIG_EN          | \
-                               RTC_BROWNOUT_DET_TRIG_EN)
-
-/**
- * @brief Enter deep or light sleep mode
- *
- * This function enters the sleep mode previously configured using rtc_sleep_init
- * function. Before entering sleep, software should configure wake up sources
- * appropriately (set up GPIO wakeup registers, timer wakeup registers,
- * and so on).
- *
- * If deep sleep mode was configured using rtc_sleep_init, and sleep is not
- * rejected by hardware (based on reject_opt flags), this function never returns.
- * When the chip wakes up from deep sleep, CPU is reset and execution starts
- * from ROM bootloader.
- *
- * If light sleep mode was configured using rtc_sleep_init, this function
- * returns on wakeup, or if sleep is rejected by hardware.
- *
- * @param wakeup_opt  bit mask wake up reasons to enable (RTC_xxx_TRIG_EN flags
- *                    combined with OR)
- * @param reject_opt  bit mask of sleep reject reasons:
- *                      - RTC_CNTL_GPIO_REJECT_EN
- *                      - RTC_CNTL_SDIO_REJECT_EN
- *                    These flags are used to prevent entering sleep when e.g.
- *                    an external host is communicating via SDIO slave
- * @return non-zero if sleep was rejected by hardware
- */
-uint32_t rtc_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt, uint32_t lslp_mem_inf_fpu);
-
-/**
- * @brief Enter deep sleep mode
- *
- * Similar to rtc_sleep_start(), but additionally uses hardware to calculate the CRC value
- * of RTC FAST memory. On wake, this CRC is used to determine if a deep sleep wake
- * stub is valid to execute (if a wake address is set).
- *
- * No RAM is accessed while calculating the CRC and going into deep sleep, which makes
- * this function safe to use even if the caller's stack is in RTC FAST memory.
- *
- * @note If no deep sleep wake stub address is set then calling rtc_sleep_start() will
- * have the same effect and takes less time as CRC calculation is skipped.
- *
- * @note This function should only be called after rtc_sleep_init() has been called to
- * configure the system for deep sleep.
- *
- * @param wakeup_opt - same as for rtc_sleep_start
- * @param reject_opt - same as for rtc_sleep_start
- *
- * @return non-zero if sleep was rejected by hardware
- */
-uint32_t rtc_deep_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt);
-
-/**
- * RTC power and clock control initialization settings
- */
-typedef struct {
-    uint32_t ck8m_wait : 8;         //!< Number of rtc_fast_clk cycles to wait for 8M clock to be ready
-    uint32_t xtal_wait : 8;         //!< Number of rtc_fast_clk cycles to wait for XTAL clock to be ready
-    uint32_t pll_wait : 8;          //!< Number of rtc_fast_clk cycles to wait for PLL to be ready
-    uint32_t clkctl_init : 1;       //!< Perform clock control related initialization
-    uint32_t pwrctl_init : 1;       //!< Perform power control related initialization
-    uint32_t rtc_dboost_fpd : 1;    //!< Force power down RTC_DBOOST
-    uint32_t xtal_fpu : 1;
-    uint32_t bbpll_fpu : 1;
-    uint32_t cpu_waiti_clk_gate : 1;
-    uint32_t cali_ocode : 1;        //!< Calibrate Ocode to make bangap voltage more precise.
-} rtc_config_t;
-
-/**
- * Default initializer of rtc_config_t.
- *
- * This initializer sets all fields to "reasonable" values (e.g. suggested for
- * production use).
- */
-#define RTC_CONFIG_DEFAULT() {\
-    .ck8m_wait = RTC_CNTL_CK8M_WAIT_DEFAULT, \
-    .xtal_wait = RTC_CNTL_XTL_BUF_WAIT_DEFAULT, \
-    .pll_wait  = RTC_CNTL_PLL_BUF_WAIT_DEFAULT, \
-    .clkctl_init = 1, \
-    .pwrctl_init = 1, \
-    .rtc_dboost_fpd = 1, \
-    .xtal_fpu = 0, \
-    .bbpll_fpu = 0, \
-    .cpu_waiti_clk_gate = 1, \
-    .cali_ocode = 0\
-}
-
-/**
- * Initialize RTC clock and power control related functions
- * @param cfg configuration options as rtc_config_t
- */
-void rtc_init(rtc_config_t cfg);
 
 // -------------------------- CLOCK TREE DEFS ALIAS ----------------------------
 // **WARNING**: The following are only for backwards compatibility.

components/soc/esp32h2/include/soc/soc.h

@@ -137,15 +137,11 @@
 #define  APB_CLK_FREQ_ROM                            ( 32*1000000 )
 #define  CPU_CLK_FREQ_ROM                            APB_CLK_FREQ_ROM
 #define  EFUSE_CLK_FREQ_ROM                          ( 20*1000000)
+#define  CPU_CLK_FREQ_MHZ_BTLD                       (96)               // The cpu clock frequency (in MHz) to set at 2nd stage bootloader system clock configuration
 #define  CPU_CLK_FREQ                                APB_CLK_FREQ
 #define  APB_CLK_FREQ                                ( 32*1000000 )
 #define  REF_CLK_FREQ                                ( 1000000 )
 #define  XTAL_CLK_FREQ                               (32*1000000)
-#define  UART_CLK_FREQ                               APB_CLK_FREQ
-#define  WDT_CLK_FREQ                                APB_CLK_FREQ
-#define  TIMER_CLK_FREQ                              (80000000>>4) //80MHz divided by 16
-#define  SPI_CLK_DIV                                 4
-#define  TICKS_PER_US_ROM                            32
 #define  GPIO_MATRIX_DELAY_NS                        0
 //}}
 

components/soc/esp32h2/include/soc/soc_caps.h

@@ -42,7 +42,6 @@
 // #define SOC_SUPPORTS_SECURE_DL_MODE     1 // TODO: IDF-6281
 //#define SOC_RISCV_COPROC_SUPPORTED       1 // TODO: IDF-6272
 #define SOC_EFUSE_KEY_PURPOSE_FIELD     1
-#define SOC_EFUSE_HAS_EFUSE_RST_BUG     1
 #define SOC_RTC_FAST_MEM_SUPPORTED      1
 #define SOC_RTC_MEM_SUPPORTED           1
 #define SOC_I2S_SUPPORTED               1
@@ -63,6 +62,7 @@
 // #define SOC_SECURE_BOOT_SUPPORTED       1 // TODO: IDF-6281
 #define SOC_BOD_SUPPORTED               1
 #define SOC_APM_SUPPORTED               1
+#define SOC_PMU_SUPPORTED               1
 
 /*-------------------------- XTAL CAPS ---------------------------------------*/
 #define SOC_XTAL_SUPPORT_32M            1
@@ -191,7 +191,7 @@
 #define SOC_I2C_SUPPORT_HW_CLR_BUS  (1)
 
 #define SOC_I2C_SUPPORT_XTAL        (1)
-// #define SOC_I2C_SUPPORT_RTC         (1)  // TODO: IDF-6254
+#define SOC_I2C_SUPPORT_RTC         (1)
 
 /*-------------------------- I2S CAPS ----------------------------------------*/
 #define SOC_I2S_NUM                 (1U)
@@ -243,7 +243,7 @@
 #define SOC_RMT_SUPPORT_TX_SYNCHRO            1  /*!< Support coordinate a group of TX channels to start simultaneously */
 #define SOC_RMT_SUPPORT_TX_CARRIER_DATA_ONLY  1  /*!< TX carrier can be modulated to data phase only */
 #define SOC_RMT_SUPPORT_XTAL                  1  /*!< Support set XTAL clock as the RMT clock source */
-// #define SOC_RMT_SUPPORT_RC_FAST               1  /*!< Support set RC_FAST as the RMT clock source */
+#define SOC_RMT_SUPPORT_RC_FAST               1  /*!< Support set RC_FAST as the RMT clock source */
 
 /*-------------------------- MCPWM CAPS --------------------------------------*/
 #define SOC_MCPWM_GROUPS                     (1U)   ///< 1 MCPWM groups on the chip (i.e., the number of independent MCPWM peripherals)
@@ -355,7 +355,7 @@
 #define SOC_TIMER_GROUP_TIMERS_PER_GROUP  (1U)
 #define SOC_TIMER_GROUP_COUNTER_BIT_WIDTH (54)
 #define SOC_TIMER_GROUP_SUPPORT_XTAL      (1)
-// #define SOC_TIMER_GROUP_SUPPORT_RC_FAST   (1) // TODO: IDF-6265
+#define SOC_TIMER_GROUP_SUPPORT_RC_FAST   (1)
 #define SOC_TIMER_GROUP_TOTAL_TIMERS      (2)
 #define SOC_TIMER_SUPPORT_ETM             (1)
 
@@ -429,12 +429,14 @@
 #define SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY   (1) /*!<Supports CRC only the stub code in RTC memory */
 
 /*-------------------------- CLOCK SUBSYSTEM CAPS ----------------------------------------*/
-// #define SOC_CLK_RC_FAST_SUPPORT_CALIBRATION       (1) // TODO: IDF-6265
+#define SOC_CLK_RC_FAST_SUPPORT_CALIBRATION       (1)
 
 #define SOC_CLK_XTAL32K_SUPPORTED                 (1)     /*!< Support to connect an external low frequency crystal */
 #define SOC_CLK_OSC_SLOW_SUPPORTED                (1)     /*!< Support to connect an external oscillator, not a crystal */
 #define SOC_CLK_RC32K_SUPPORTED                   (1)     /*!< Support an internal 32kHz RC oscillator */
 
+#define SOC_CLK_LP_FAST_SUPPORT_LP_PLL           (1)      /*!< Support LP_PLL clock as the LP_FAST clock source */
+
 // TODO: IDF-6229 (Copy from esp32c6, need check)
 /*-------------------------- Temperature Sensor CAPS -------------------------------------*/
 #define SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC                (1)

components/soc/esp32h4/include/soc/soc.h

@@ -136,6 +136,7 @@
 #define  APB_CLK_FREQ_ROM                            ( 32*1000000 )
 #define  CPU_CLK_FREQ_ROM                            APB_CLK_FREQ_ROM
 #define  EFUSE_CLK_FREQ_ROM                          ( 20*1000000)
+#define  CPU_CLK_FREQ_MHZ_BTLD                       (64)               // The cpu clock frequency (in MHz) to set at 2nd stage bootloader system clock configuration
 #define  CPU_CLK_FREQ                                APB_CLK_FREQ
 #if CONFIG_IDF_ENV_FPGA
 #define  APB_CLK_FREQ                                ( 32*1000000 )

components/soc/esp32s2/include/soc/soc.h

@@ -142,6 +142,7 @@
 //Periheral Clock {{
 #define  APB_CLK_FREQ_ROM                            ( 40*1000000 )
 #define  CPU_CLK_FREQ_ROM                            APB_CLK_FREQ_ROM
+#define  CPU_CLK_FREQ_MHZ_BTLD                       (80)                 // The cpu clock frequency (in MHz) to set at 2nd stage bootloader system clock configuration
 #define  CPU_CLK_FREQ                                APB_CLK_FREQ
 #define  APB_CLK_FREQ                                ( 80*1000000 )       //unit: Hz
 #define  REF_CLK_FREQ                                ( 1000000 )

components/soc/esp32s3/include/soc/soc.h

@@ -152,6 +152,7 @@
 #define  APB_CLK_FREQ_ROM                            (40*1000000)
 #define  CPU_CLK_FREQ_ROM                            APB_CLK_FREQ_ROM
 #define  EFUSE_CLK_FREQ_ROM                          (20*1000000)
+#define  CPU_CLK_FREQ_MHZ_BTLD                       (80)               // The cpu clock frequency (in MHz) to set at 2nd stage bootloader system clock configuration
 #define  CPU_CLK_FREQ                                APB_CLK_FREQ
 #define  APB_CLK_FREQ                                (80*1000000)
 #define  REF_CLK_FREQ                                (1000000)

docs/docs_not_updated/esp32h2.txt

@@ -53,7 +53,6 @@ api-reference/peripherals/i2s
 api-reference/peripherals/temp_sensor
 api-reference/peripherals/spi_features
 api-reference/peripherals/sdio_slave
-api-reference/peripherals/clk_tree
 api-reference/peripherals/spi_flash/xip_from_psram.inc
 api-reference/peripherals/spi_flash/spi_flash_concurrency
 api-reference/peripherals/spi_flash/spi_flash_override_driver

docs/en/api-reference/peripherals/clk_tree.rst

@@ -1,11 +1,11 @@
 Clock Tree
 ==========
 
-{IDF_TARGET_RC_FAST_VAGUE_FREQ: default="8", esp32="8", esp32s2="8", esp32c3="17.5", esp32s3="17.5", esp32c2="17.5", esp32c6="17.5", esp32h4="8"}
+{IDF_TARGET_RC_FAST_VAGUE_FREQ: default="8", esp32c3="17.5", esp32s3="17.5", esp32c2="17.5", esp32c6="17.5"}
 
-{IDF_TARGET_RC_FAST_ADJUSTED_FREQ: default="8.5", esp32="8.5", esp32s2="8.5", esp32c3="17.5", esp32s3="17.5", esp32c2="17.5", esp32c6="17.5", esp32h4="8.5"}
+{IDF_TARGET_RC_FAST_ADJUSTED_FREQ: default="8.5", esp32c3="17.5", esp32s3="17.5", esp32c2="17.5", esp32c6="17.5"}
 
-{IDF_TARGET_XTAL_FREQ: default="40", esp32="2~40", esp32c2="40/26", esp32h4="32"}
+{IDF_TARGET_XTAL_FREQ: default="40", esp32="2~40", esp32c2="40/26", esp32h4="32", esp32h2="32"}
 
 {IDF_TARGET_RC_SLOW_VAGUE_FREQ: default="136", esp32="150", esp32s2="90"}