pcnt: update pcnt soc data for all targets

components/soc/esp32/include/soc/soc_caps.h

@@ -173,10 +173,10 @@
 #define SOC_MPU_REGION_WO_SUPPORTED               0
 
 /*-------------------------- PCNT CAPS ---------------------------------------*/
-// ESP32 have 1 PCNT peripheral
-#define SOC_PCNT_PORT_NUM      (1)
-#define SOC_PCNT_UNIT_NUM      (8)
-#define SOC_PCNT_UNIT_CHANNEL_NUM (2)
+#define SOC_PCNT_GROUPS                  (1)
+#define SOC_PCNT_UNITS_PER_GROUP         (8)
+#define SOC_PCNT_CHANNELS_PER_UNIT       (2)
+#define SOC_PCNT_THRES_POINT_PER_UNIT    (2)
 
 /*-------------------------- RMT CAPS ----------------------------------------*/
 #define SOC_RMT_GROUPS                  (1)  /*!< One RMT group */

components/soc/esp32/pcnt_periph.c

@@ -16,102 +16,106 @@
 #include "soc/gpio_sig_map.h"
 
 const pcnt_signal_conn_t pcnt_periph_signals = {
-    .module = PERIPH_PCNT_MODULE,
-    .irq = ETS_PCNT_INTR_SOURCE,
-    .units = {
+    .groups = {
         [0] = {
-            .channels = {
+            .module = PERIPH_PCNT_MODULE,
+            .irq = ETS_PCNT_INTR_SOURCE,
+            .units = {
                 [0] = {
-                    .control_sig = PCNT_CTRL_CH0_IN0_IDX,
-                    .pulse_sig = PCNT_SIG_CH0_IN0_IDX
+                    .channels = {
+                        [0] = {
+                            .control_sig = PCNT_CTRL_CH0_IN0_IDX,
+                            .pulse_sig = PCNT_SIG_CH0_IN0_IDX
+                        },
+                        [1] = {
+                            .control_sig = PCNT_CTRL_CH1_IN0_IDX,
+                            .pulse_sig = PCNT_SIG_CH1_IN0_IDX
+                        }
+                    }
                 },
                 [1] = {
-                    .control_sig = PCNT_CTRL_CH1_IN0_IDX,
-                    .pulse_sig = PCNT_SIG_CH1_IN0_IDX
-                }
-            }
-        },
-        [1] = {
-            .channels = {
-                [0] = {
-                    .control_sig = PCNT_CTRL_CH0_IN1_IDX,
-                    .pulse_sig = PCNT_SIG_CH0_IN1_IDX
+                    .channels = {
+                        [0] = {
+                            .control_sig = PCNT_CTRL_CH0_IN1_IDX,
+                            .pulse_sig = PCNT_SIG_CH0_IN1_IDX
+                        },
+                        [1] = {
+                            .control_sig = PCNT_CTRL_CH1_IN1_IDX,
+                            .pulse_sig = PCNT_SIG_CH1_IN1_IDX
+                        }
+                    }
                 },
-                [1] = {
-                    .control_sig = PCNT_CTRL_CH1_IN1_IDX,
-                    .pulse_sig = PCNT_SIG_CH1_IN1_IDX
-                }
-            }
-        },
-        [2] = {
-            .channels = {
-                [0] = {
-                    .control_sig = PCNT_CTRL_CH0_IN2_IDX,
-                    .pulse_sig = PCNT_SIG_CH0_IN2_IDX
+                [2] = {
+                    .channels = {
+                        [0] = {
+                            .control_sig = PCNT_CTRL_CH0_IN2_IDX,
+                            .pulse_sig = PCNT_SIG_CH0_IN2_IDX
+                        },
+                        [1] = {
+                            .control_sig = PCNT_CTRL_CH1_IN2_IDX,
+                            .pulse_sig = PCNT_SIG_CH1_IN2_IDX
+                        }
+                    }
                 },
-                [1] = {
-                    .control_sig = PCNT_CTRL_CH1_IN2_IDX,
-                    .pulse_sig = PCNT_SIG_CH1_IN2_IDX
-                }
-            }
-        },
-        [3] = {
-            .channels = {
-                [0] = {
-                    .control_sig = PCNT_CTRL_CH0_IN3_IDX,
-                    .pulse_sig = PCNT_SIG_CH0_IN3_IDX
+                [3] = {
+                    .channels = {
+                        [0] = {
+                            .control_sig = PCNT_CTRL_CH0_IN3_IDX,
+                            .pulse_sig = PCNT_SIG_CH0_IN3_IDX
+                        },
+                        [1] = {
+                            .control_sig = PCNT_CTRL_CH1_IN3_IDX,
+                            .pulse_sig = PCNT_SIG_CH1_IN3_IDX
+                        }
+                    }
                 },
-                [1] = {
-                    .control_sig = PCNT_CTRL_CH1_IN3_IDX,
-                    .pulse_sig = PCNT_SIG_CH1_IN3_IDX
-                }
-            }
-        },
-        [4] = {
-            .channels = {
-                [0] = {
-                    .control_sig = PCNT_CTRL_CH0_IN4_IDX,
-                    .pulse_sig = PCNT_SIG_CH0_IN4_IDX
+                [4] = {
+                    .channels = {
+                        [0] = {
+                            .control_sig = PCNT_CTRL_CH0_IN4_IDX,
+                            .pulse_sig = PCNT_SIG_CH0_IN4_IDX
+                        },
+                        [1] = {
+                            .control_sig = PCNT_CTRL_CH1_IN4_IDX,
+                            .pulse_sig = PCNT_SIG_CH1_IN4_IDX
+                        }
+                    }
                 },
-                [1] = {
-                    .control_sig = PCNT_CTRL_CH1_IN4_IDX,
-                    .pulse_sig = PCNT_SIG_CH1_IN4_IDX
-                }
-            }
-        },
-        [5] = {
-            .channels = {
-                [0] = {
-                    .control_sig = PCNT_CTRL_CH0_IN5_IDX,
-                    .pulse_sig = PCNT_SIG_CH0_IN5_IDX
-                },
-                [1] = {
-                    .control_sig = PCNT_CTRL_CH1_IN5_IDX,
-                    .pulse_sig = PCNT_SIG_CH1_IN5_IDX
-                }
-            }
-        },
-        [6] = {
-            .channels = {
-                [0] = {
-                    .control_sig = PCNT_CTRL_CH0_IN6_IDX,
-                    .pulse_sig = PCNT_SIG_CH0_IN6_IDX
+                [5] = {
+                    .channels = {
+                        [0] = {
+                            .control_sig = PCNT_CTRL_CH0_IN5_IDX,
+                            .pulse_sig = PCNT_SIG_CH0_IN5_IDX
+                        },
+                        [1] = {
+                            .control_sig = PCNT_CTRL_CH1_IN5_IDX,
+                            .pulse_sig = PCNT_SIG_CH1_IN5_IDX
+                        }
+                    }
                 },
-                [1] = {
-                    .control_sig = PCNT_CTRL_CH1_IN6_IDX,
-                    .pulse_sig = PCNT_SIG_CH1_IN6_IDX
-                }
-            }
-        },
-        [7] = {
-            .channels = {
-                [0] = {
-                    .control_sig = PCNT_CTRL_CH0_IN7_IDX,
-                    .pulse_sig = PCNT_SIG_CH0_IN7_IDX
+                [6] = {
+                    .channels = {
+                        [0] = {
+                            .control_sig = PCNT_CTRL_CH0_IN6_IDX,
+                            .pulse_sig = PCNT_SIG_CH0_IN6_IDX
+                        },
+                        [1] = {
+                            .control_sig = PCNT_CTRL_CH1_IN6_IDX,
+                            .pulse_sig = PCNT_SIG_CH1_IN6_IDX
+                        }
+                    }
                 },
-                [1] = {
-                    .control_sig = PCNT_CTRL_CH1_IN7_IDX,
-                    .pulse_sig = PCNT_SIG_CH1_IN7_IDX
+                [7] = {
+                    .channels = {
+                        [0] = {
+                            .control_sig = PCNT_CTRL_CH0_IN7_IDX,
+                            .pulse_sig = PCNT_SIG_CH0_IN7_IDX
+                        },
+                        [1] = {
+                            .control_sig = PCNT_CTRL_CH1_IN7_IDX,
+                            .pulse_sig = PCNT_SIG_CH1_IN7_IDX
+                        }
+                    }
                 }
             }
         }

components/soc/esp32h2/include/soc/soc.h

@@ -66,7 +66,6 @@
 #define DR_REG_UHCI0_BASE                       0x60014000
 #define DR_REG_SLCHOST_BASE                     0x60019000
 #define DR_REG_RMT_BASE                         0x60016000
-#define DR_REG_PCNT_BASE                        0x60017000
 #define DR_REG_SLC_BASE                         0x6002D000
 #define DR_REG_LEDC_BASE                        0x60019000
 #define DR_REG_EFUSE_BASE                       0x6001A000

components/soc/esp32s2/include/soc/pcnt_reg.h

@@ -1,860 +1,1236 @@
-// Copyright 2017-2019 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _SOC_PCNT_REG_H_
-#define _SOC_PCNT_REG_H_
+/** Copyright 2021 Espressif Systems (Shanghai) PTE LTD
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License");
+ *  you may not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS,
+ *  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ */
+#pragma once
 
+#include <stdint.h>
+#include "soc/soc.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
-#include "soc.h"
-#define PCNT_U0_CONF0_REG          (DR_REG_PCNT_BASE + 0x0000)
-/* PCNT_CH1_LCTRL_MODE_U0 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */
-/*description: */
-#define PCNT_CH1_LCTRL_MODE_U0  0x00000003
-#define PCNT_CH1_LCTRL_MODE_U0_M  ((PCNT_CH1_LCTRL_MODE_U0_V)<<(PCNT_CH1_LCTRL_MODE_U0_S))
-#define PCNT_CH1_LCTRL_MODE_U0_V  0x3
-#define PCNT_CH1_LCTRL_MODE_U0_S  30
-/* PCNT_CH1_HCTRL_MODE_U0 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */
-/*description: */
-#define PCNT_CH1_HCTRL_MODE_U0  0x00000003
-#define PCNT_CH1_HCTRL_MODE_U0_M  ((PCNT_CH1_HCTRL_MODE_U0_V)<<(PCNT_CH1_HCTRL_MODE_U0_S))
-#define PCNT_CH1_HCTRL_MODE_U0_V  0x3
-#define PCNT_CH1_HCTRL_MODE_U0_S  28
-/* PCNT_CH1_POS_MODE_U0 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */
-/*description: */
-#define PCNT_CH1_POS_MODE_U0  0x00000003
-#define PCNT_CH1_POS_MODE_U0_M  ((PCNT_CH1_POS_MODE_U0_V)<<(PCNT_CH1_POS_MODE_U0_S))
-#define PCNT_CH1_POS_MODE_U0_V  0x3
-#define PCNT_CH1_POS_MODE_U0_S  26
-/* PCNT_CH1_NEG_MODE_U0 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */
-/*description: */
-#define PCNT_CH1_NEG_MODE_U0  0x00000003
-#define PCNT_CH1_NEG_MODE_U0_M  ((PCNT_CH1_NEG_MODE_U0_V)<<(PCNT_CH1_NEG_MODE_U0_S))
-#define PCNT_CH1_NEG_MODE_U0_V  0x3
-#define PCNT_CH1_NEG_MODE_U0_S  24
-/* PCNT_CH0_LCTRL_MODE_U0 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */
-/*description: */
-#define PCNT_CH0_LCTRL_MODE_U0  0x00000003
-#define PCNT_CH0_LCTRL_MODE_U0_M  ((PCNT_CH0_LCTRL_MODE_U0_V)<<(PCNT_CH0_LCTRL_MODE_U0_S))
-#define PCNT_CH0_LCTRL_MODE_U0_V  0x3
-#define PCNT_CH0_LCTRL_MODE_U0_S  22
-/* PCNT_CH0_HCTRL_MODE_U0 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */
-/*description: */
-#define PCNT_CH0_HCTRL_MODE_U0  0x00000003
-#define PCNT_CH0_HCTRL_MODE_U0_M  ((PCNT_CH0_HCTRL_MODE_U0_V)<<(PCNT_CH0_HCTRL_MODE_U0_S))
-#define PCNT_CH0_HCTRL_MODE_U0_V  0x3
-#define PCNT_CH0_HCTRL_MODE_U0_S  20
-/* PCNT_CH0_POS_MODE_U0 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */
-/*description: */
-#define PCNT_CH0_POS_MODE_U0  0x00000003
-#define PCNT_CH0_POS_MODE_U0_M  ((PCNT_CH0_POS_MODE_U0_V)<<(PCNT_CH0_POS_MODE_U0_S))
-#define PCNT_CH0_POS_MODE_U0_V  0x3
-#define PCNT_CH0_POS_MODE_U0_S  18
-/* PCNT_CH0_NEG_MODE_U0 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */
-/*description: */
-#define PCNT_CH0_NEG_MODE_U0  0x00000003
-#define PCNT_CH0_NEG_MODE_U0_M  ((PCNT_CH0_NEG_MODE_U0_V)<<(PCNT_CH0_NEG_MODE_U0_S))
-#define PCNT_CH0_NEG_MODE_U0_V  0x3
-#define PCNT_CH0_NEG_MODE_U0_S  16
-/* PCNT_THR_THRES1_EN_U0 : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: */
-#define PCNT_THR_THRES1_EN_U0  (BIT(15))
-#define PCNT_THR_THRES1_EN_U0_M  (BIT(15))
-#define PCNT_THR_THRES1_EN_U0_V  0x1
-#define PCNT_THR_THRES1_EN_U0_S  15
-/* PCNT_THR_THRES0_EN_U0 : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: */
-#define PCNT_THR_THRES0_EN_U0  (BIT(14))
-#define PCNT_THR_THRES0_EN_U0_M  (BIT(14))
-#define PCNT_THR_THRES0_EN_U0_V  0x1
-#define PCNT_THR_THRES0_EN_U0_S  14
-/* PCNT_THR_L_LIM_EN_U0 : R/W ;bitpos:[13] ;default: 1'b1 ; */
-/*description: */
-#define PCNT_THR_L_LIM_EN_U0  (BIT(13))
-#define PCNT_THR_L_LIM_EN_U0_M  (BIT(13))
-#define PCNT_THR_L_LIM_EN_U0_V  0x1
-#define PCNT_THR_L_LIM_EN_U0_S  13
-/* PCNT_THR_H_LIM_EN_U0 : R/W ;bitpos:[12] ;default: 1'b1 ; */
-/*description: */
-#define PCNT_THR_H_LIM_EN_U0  (BIT(12))
-#define PCNT_THR_H_LIM_EN_U0_M  (BIT(12))
-#define PCNT_THR_H_LIM_EN_U0_V  0x1
-#define PCNT_THR_H_LIM_EN_U0_S  12
-/* PCNT_THR_ZERO_EN_U0 : R/W ;bitpos:[11] ;default: 1'b1 ; */
-/*description: */
-#define PCNT_THR_ZERO_EN_U0  (BIT(11))
-#define PCNT_THR_ZERO_EN_U0_M  (BIT(11))
-#define PCNT_THR_ZERO_EN_U0_V  0x1
-#define PCNT_THR_ZERO_EN_U0_S  11
-/* PCNT_FILTER_EN_U0 : R/W ;bitpos:[10] ;default: 1'b1 ; */
-/*description: */
-#define PCNT_FILTER_EN_U0  (BIT(10))
-#define PCNT_FILTER_EN_U0_M  (BIT(10))
-#define PCNT_FILTER_EN_U0_V  0x1
-#define PCNT_FILTER_EN_U0_S  10
-/* PCNT_FILTER_THRES_U0 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */
-/*description: */
-#define PCNT_FILTER_THRES_U0  0x000003FF
-#define PCNT_FILTER_THRES_U0_M  ((PCNT_FILTER_THRES_U0_V)<<(PCNT_FILTER_THRES_U0_S))
-#define PCNT_FILTER_THRES_U0_V  0x3FF
+
+/** PCNT_U0_CONF0_REG register
+ *  Configuration register 0 for unit 0
+ */
+#define PCNT_U0_CONF0_REG (DR_REG_PCNT_BASE + 0x0)
+/** PCNT_FILTER_THRES_U0 : R/W; bitpos: [9:0]; default: 16;
+ *  This sets the maximum threshold, in APB_CLK cycles, for the filter.
+ *
+ *  Any pulses with width less than this will be ignored when the filter is enabled.
+ */
+#define PCNT_FILTER_THRES_U0    0x000003FFU
+#define PCNT_FILTER_THRES_U0_M  (PCNT_FILTER_THRES_U0_V << PCNT_FILTER_THRES_U0_S)
+#define PCNT_FILTER_THRES_U0_V  0x000003FFU
 #define PCNT_FILTER_THRES_U0_S  0
+/** PCNT_FILTER_EN_U0 : R/W; bitpos: [10]; default: 1;
+ *  This is the enable bit for unit 0's input filter.
+ */
+#define PCNT_FILTER_EN_U0    (BIT(10))
+#define PCNT_FILTER_EN_U0_M  (PCNT_FILTER_EN_U0_V << PCNT_FILTER_EN_U0_S)
+#define PCNT_FILTER_EN_U0_V  0x00000001U
+#define PCNT_FILTER_EN_U0_S  10
+/** PCNT_THR_ZERO_EN_U0 : R/W; bitpos: [11]; default: 1;
+ *  This is the enable bit for unit 0's zero comparator.
+ */
+#define PCNT_THR_ZERO_EN_U0    (BIT(11))
+#define PCNT_THR_ZERO_EN_U0_M  (PCNT_THR_ZERO_EN_U0_V << PCNT_THR_ZERO_EN_U0_S)
+#define PCNT_THR_ZERO_EN_U0_V  0x00000001U
+#define PCNT_THR_ZERO_EN_U0_S  11
+/** PCNT_THR_H_LIM_EN_U0 : R/W; bitpos: [12]; default: 1;
+ *  This is the enable bit for unit 0's thr_h_lim comparator.
+ */
+#define PCNT_THR_H_LIM_EN_U0    (BIT(12))
+#define PCNT_THR_H_LIM_EN_U0_M  (PCNT_THR_H_LIM_EN_U0_V << PCNT_THR_H_LIM_EN_U0_S)
+#define PCNT_THR_H_LIM_EN_U0_V  0x00000001U
+#define PCNT_THR_H_LIM_EN_U0_S  12
+/** PCNT_THR_L_LIM_EN_U0 : R/W; bitpos: [13]; default: 1;
+ *  This is the enable bit for unit 0's thr_l_lim comparator.
+ */
+#define PCNT_THR_L_LIM_EN_U0    (BIT(13))
+#define PCNT_THR_L_LIM_EN_U0_M  (PCNT_THR_L_LIM_EN_U0_V << PCNT_THR_L_LIM_EN_U0_S)
+#define PCNT_THR_L_LIM_EN_U0_V  0x00000001U
+#define PCNT_THR_L_LIM_EN_U0_S  13
+/** PCNT_THR_THRES0_EN_U0 : R/W; bitpos: [14]; default: 0;
+ *  This is the enable bit for unit 0's thres0 comparator.
+ */
+#define PCNT_THR_THRES0_EN_U0    (BIT(14))
+#define PCNT_THR_THRES0_EN_U0_M  (PCNT_THR_THRES0_EN_U0_V << PCNT_THR_THRES0_EN_U0_S)
+#define PCNT_THR_THRES0_EN_U0_V  0x00000001U
+#define PCNT_THR_THRES0_EN_U0_S  14
+/** PCNT_THR_THRES1_EN_U0 : R/W; bitpos: [15]; default: 0;
+ *  This is the enable bit for unit 0's thres1 comparator.
+ */
+#define PCNT_THR_THRES1_EN_U0    (BIT(15))
+#define PCNT_THR_THRES1_EN_U0_M  (PCNT_THR_THRES1_EN_U0_V << PCNT_THR_THRES1_EN_U0_S)
+#define PCNT_THR_THRES1_EN_U0_V  0x00000001U
+#define PCNT_THR_THRES1_EN_U0_S  15
+/** PCNT_CH0_NEG_MODE_U0 : R/W; bitpos: [17:16]; default: 0;
+ *  This register sets the behavior when the signal input of channel 0 detects a
+ *  negative edge.
+ *
+ *  1: Increase the counter;2: Decrease the counter;0, 3: No effect on counter
+ */
+#define PCNT_CH0_NEG_MODE_U0    0x00000003U
+#define PCNT_CH0_NEG_MODE_U0_M  (PCNT_CH0_NEG_MODE_U0_V << PCNT_CH0_NEG_MODE_U0_S)
+#define PCNT_CH0_NEG_MODE_U0_V  0x00000003U
+#define PCNT_CH0_NEG_MODE_U0_S  16
+/** PCNT_CH0_POS_MODE_U0 : R/W; bitpos: [19:18]; default: 0;
+ *  This register sets the behavior when the signal input of channel 0 detects a
+ *  positive edge.
+ *
+ *  1: Increase the counter;2: Decrease the counter;0, 3: No effect on counter
+ */
+#define PCNT_CH0_POS_MODE_U0    0x00000003U
+#define PCNT_CH0_POS_MODE_U0_M  (PCNT_CH0_POS_MODE_U0_V << PCNT_CH0_POS_MODE_U0_S)
+#define PCNT_CH0_POS_MODE_U0_V  0x00000003U
+#define PCNT_CH0_POS_MODE_U0_S  18
+/** PCNT_CH0_HCTRL_MODE_U0 : R/W; bitpos: [21:20]; default: 0;
+ *  This register configures how the CH0_POS_MODE/CH0_NEG_MODE settings will be
+ *  modified when the control signal is high.
+ *
+ *  0: No modification;1: Invert behavior (increase -> decrease, decrease ->
+ *  increase);2, 3: Inhibit counter modification
+ */
+#define PCNT_CH0_HCTRL_MODE_U0    0x00000003U
+#define PCNT_CH0_HCTRL_MODE_U0_M  (PCNT_CH0_HCTRL_MODE_U0_V << PCNT_CH0_HCTRL_MODE_U0_S)
+#define PCNT_CH0_HCTRL_MODE_U0_V  0x00000003U
+#define PCNT_CH0_HCTRL_MODE_U0_S  20
+/** PCNT_CH0_LCTRL_MODE_U0 : R/W; bitpos: [23:22]; default: 0;
+ *  This register configures how the CH0_POS_MODE/CH0_NEG_MODE settings will be
+ *  modified when the control signal is low.
+ *
+ *  0: No modification;1: Invert behavior (increase -> decrease, decrease ->
+ *  increase);2, 3: Inhibit counter modification
+ */
+#define PCNT_CH0_LCTRL_MODE_U0    0x00000003U
+#define PCNT_CH0_LCTRL_MODE_U0_M  (PCNT_CH0_LCTRL_MODE_U0_V << PCNT_CH0_LCTRL_MODE_U0_S)
+#define PCNT_CH0_LCTRL_MODE_U0_V  0x00000003U
+#define PCNT_CH0_LCTRL_MODE_U0_S  22
+/** PCNT_CH1_NEG_MODE_U0 : R/W; bitpos: [25:24]; default: 0;
+ *  This register sets the behavior when the signal input of channel 1 detects a
+ *  negative edge.
+ *
+ *  1: Increment the counter;2: Decrement the counter;0, 3: No effect on counter
+ */
+#define PCNT_CH1_NEG_MODE_U0    0x00000003U
+#define PCNT_CH1_NEG_MODE_U0_M  (PCNT_CH1_NEG_MODE_U0_V << PCNT_CH1_NEG_MODE_U0_S)
+#define PCNT_CH1_NEG_MODE_U0_V  0x00000003U
+#define PCNT_CH1_NEG_MODE_U0_S  24
+/** PCNT_CH1_POS_MODE_U0 : R/W; bitpos: [27:26]; default: 0;
+ *  This register sets the behavior when the signal input of channel 1 detects a
+ *  positive edge.
+ *
+ *  1: Increment the counter;2: Decrement the counter;0, 3: No effect on counter
+ */
+#define PCNT_CH1_POS_MODE_U0    0x00000003U
+#define PCNT_CH1_POS_MODE_U0_M  (PCNT_CH1_POS_MODE_U0_V << PCNT_CH1_POS_MODE_U0_S)
+#define PCNT_CH1_POS_MODE_U0_V  0x00000003U
+#define PCNT_CH1_POS_MODE_U0_S  26
+/** PCNT_CH1_HCTRL_MODE_U0 : R/W; bitpos: [29:28]; default: 0;
+ *  This register configures how the CH0_POS_MODE/CH0_NEG_MODE settings will be
+ *  modified when the control signal is high.
+ *
+ *  0: No modification;1: Invert behavior (increase -> decrease, decrease ->
+ *  increase);2, 3: Inhibit counter modification
+ */
+#define PCNT_CH1_HCTRL_MODE_U0    0x00000003U
+#define PCNT_CH1_HCTRL_MODE_U0_M  (PCNT_CH1_HCTRL_MODE_U0_V << PCNT_CH1_HCTRL_MODE_U0_S)
+#define PCNT_CH1_HCTRL_MODE_U0_V  0x00000003U
+#define PCNT_CH1_HCTRL_MODE_U0_S  28
+/** PCNT_CH1_LCTRL_MODE_U0 : R/W; bitpos: [31:30]; default: 0;
+ *  This register configures how the CH0_POS_MODE/CH0_NEG_MODE settings will be
+ *  modified when the control signal is low.
+ *
+ *  0: No modification;1: Invert behavior (increase -> decrease, decrease ->
+ *  increase);2, 3: Inhibit counter modification
+ */
+#define PCNT_CH1_LCTRL_MODE_U0    0x00000003U
+#define PCNT_CH1_LCTRL_MODE_U0_M  (PCNT_CH1_LCTRL_MODE_U0_V << PCNT_CH1_LCTRL_MODE_U0_S)
+#define PCNT_CH1_LCTRL_MODE_U0_V  0x00000003U
+#define PCNT_CH1_LCTRL_MODE_U0_S  30
 
-#define PCNT_U0_CONF1_REG          (DR_REG_PCNT_BASE + 0x0004)
-/* PCNT_CNT_THRES1_U0 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */
-/*description: */
-#define PCNT_CNT_THRES1_U0  0x0000FFFF
-#define PCNT_CNT_THRES1_U0_M  ((PCNT_CNT_THRES1_U0_V)<<(PCNT_CNT_THRES1_U0_S))
-#define PCNT_CNT_THRES1_U0_V  0xFFFF
-#define PCNT_CNT_THRES1_U0_S  16
-/* PCNT_CNT_THRES0_U0 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */
-/*description: */
-#define PCNT_CNT_THRES0_U0  0x0000FFFF
-#define PCNT_CNT_THRES0_U0_M  ((PCNT_CNT_THRES0_U0_V)<<(PCNT_CNT_THRES0_U0_S))
-#define PCNT_CNT_THRES0_U0_V  0xFFFF
+/** PCNT_U0_CONF1_REG register
+ *  Configuration register 1 for unit 0
+ */
+#define PCNT_U0_CONF1_REG (DR_REG_PCNT_BASE + 0x4)
+/** PCNT_CNT_THRES0_U0 : R/W; bitpos: [15:0]; default: 0;
+ *  This register is used to configure the thres0 value for unit 0.
+ */
+#define PCNT_CNT_THRES0_U0    0x0000FFFFU
+#define PCNT_CNT_THRES0_U0_M  (PCNT_CNT_THRES0_U0_V << PCNT_CNT_THRES0_U0_S)
+#define PCNT_CNT_THRES0_U0_V  0x0000FFFFU
 #define PCNT_CNT_THRES0_U0_S  0
+/** PCNT_CNT_THRES1_U0 : R/W; bitpos: [31:16]; default: 0;
+ *  This register is used to configure the thres1 value for unit 0.
+ */
+#define PCNT_CNT_THRES1_U0    0x0000FFFFU
+#define PCNT_CNT_THRES1_U0_M  (PCNT_CNT_THRES1_U0_V << PCNT_CNT_THRES1_U0_S)
+#define PCNT_CNT_THRES1_U0_V  0x0000FFFFU
+#define PCNT_CNT_THRES1_U0_S  16
 
-#define PCNT_U0_CONF2_REG          (DR_REG_PCNT_BASE + 0x0008)
-/* PCNT_CNT_L_LIM_U0 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */
-/*description: */
-#define PCNT_CNT_L_LIM_U0  0x0000FFFF
-#define PCNT_CNT_L_LIM_U0_M  ((PCNT_CNT_L_LIM_U0_V)<<(PCNT_CNT_L_LIM_U0_S))
-#define PCNT_CNT_L_LIM_U0_V  0xFFFF
-#define PCNT_CNT_L_LIM_U0_S  16
-/* PCNT_CNT_H_LIM_U0 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */
-/*description: */
-#define PCNT_CNT_H_LIM_U0  0x0000FFFF
-#define PCNT_CNT_H_LIM_U0_M  ((PCNT_CNT_H_LIM_U0_V)<<(PCNT_CNT_H_LIM_U0_S))
-#define PCNT_CNT_H_LIM_U0_V  0xFFFF
+/** PCNT_U0_CONF2_REG register
+ *  Configuration register 2 for unit 0
+ */
+#define PCNT_U0_CONF2_REG (DR_REG_PCNT_BASE + 0x8)
+/** PCNT_CNT_H_LIM_U0 : R/W; bitpos: [15:0]; default: 0;
+ *  This register is used to configure the thr_h_lim value for unit 0.
+ */
+#define PCNT_CNT_H_LIM_U0    0x0000FFFFU
+#define PCNT_CNT_H_LIM_U0_M  (PCNT_CNT_H_LIM_U0_V << PCNT_CNT_H_LIM_U0_S)
+#define PCNT_CNT_H_LIM_U0_V  0x0000FFFFU
 #define PCNT_CNT_H_LIM_U0_S  0
+/** PCNT_CNT_L_LIM_U0 : R/W; bitpos: [31:16]; default: 0;
+ *  This register is used to configure the thr_l_lim value for unit 0.
+ */
+#define PCNT_CNT_L_LIM_U0    0x0000FFFFU
+#define PCNT_CNT_L_LIM_U0_M  (PCNT_CNT_L_LIM_U0_V << PCNT_CNT_L_LIM_U0_S)
+#define PCNT_CNT_L_LIM_U0_V  0x0000FFFFU
+#define PCNT_CNT_L_LIM_U0_S  16
 
-#define PCNT_U1_CONF0_REG          (DR_REG_PCNT_BASE + 0x000c)
-/* PCNT_CH1_LCTRL_MODE_U1 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */
-/*description: */
-#define PCNT_CH1_LCTRL_MODE_U1  0x00000003
-#define PCNT_CH1_LCTRL_MODE_U1_M  ((PCNT_CH1_LCTRL_MODE_U1_V)<<(PCNT_CH1_LCTRL_MODE_U1_S))
-#define PCNT_CH1_LCTRL_MODE_U1_V  0x3
-#define PCNT_CH1_LCTRL_MODE_U1_S  30
-/* PCNT_CH1_HCTRL_MODE_U1 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */
-/*description: */
-#define PCNT_CH1_HCTRL_MODE_U1  0x00000003
-#define PCNT_CH1_HCTRL_MODE_U1_M  ((PCNT_CH1_HCTRL_MODE_U1_V)<<(PCNT_CH1_HCTRL_MODE_U1_S))
-#define PCNT_CH1_HCTRL_MODE_U1_V  0x3
-#define PCNT_CH1_HCTRL_MODE_U1_S  28
-/* PCNT_CH1_POS_MODE_U1 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */
-/*description: */
-#define PCNT_CH1_POS_MODE_U1  0x00000003
-#define PCNT_CH1_POS_MODE_U1_M  ((PCNT_CH1_POS_MODE_U1_V)<<(PCNT_CH1_POS_MODE_U1_S))
-#define PCNT_CH1_POS_MODE_U1_V  0x3
-#define PCNT_CH1_POS_MODE_U1_S  26
-/* PCNT_CH1_NEG_MODE_U1 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */
-/*description: */
-#define PCNT_CH1_NEG_MODE_U1  0x00000003
-#define PCNT_CH1_NEG_MODE_U1_M  ((PCNT_CH1_NEG_MODE_U1_V)<<(PCNT_CH1_NEG_MODE_U1_S))
-#define PCNT_CH1_NEG_MODE_U1_V  0x3
-#define PCNT_CH1_NEG_MODE_U1_S  24
-/* PCNT_CH0_LCTRL_MODE_U1 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */
-/*description: */
-#define PCNT_CH0_LCTRL_MODE_U1  0x00000003
-#define PCNT_CH0_LCTRL_MODE_U1_M  ((PCNT_CH0_LCTRL_MODE_U1_V)<<(PCNT_CH0_LCTRL_MODE_U1_S))
-#define PCNT_CH0_LCTRL_MODE_U1_V  0x3
-#define PCNT_CH0_LCTRL_MODE_U1_S  22
-/* PCNT_CH0_HCTRL_MODE_U1 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */
-/*description: */
-#define PCNT_CH0_HCTRL_MODE_U1  0x00000003
-#define PCNT_CH0_HCTRL_MODE_U1_M  ((PCNT_CH0_HCTRL_MODE_U1_V)<<(PCNT_CH0_HCTRL_MODE_U1_S))
-#define PCNT_CH0_HCTRL_MODE_U1_V  0x3
-#define PCNT_CH0_HCTRL_MODE_U1_S  20
-/* PCNT_CH0_POS_MODE_U1 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */
-/*description: */
-#define PCNT_CH0_POS_MODE_U1  0x00000003
-#define PCNT_CH0_POS_MODE_U1_M  ((PCNT_CH0_POS_MODE_U1_V)<<(PCNT_CH0_POS_MODE_U1_S))
-#define PCNT_CH0_POS_MODE_U1_V  0x3
-#define PCNT_CH0_POS_MODE_U1_S  18
-/* PCNT_CH0_NEG_MODE_U1 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */
-/*description: */
-#define PCNT_CH0_NEG_MODE_U1  0x00000003
-#define PCNT_CH0_NEG_MODE_U1_M  ((PCNT_CH0_NEG_MODE_U1_V)<<(PCNT_CH0_NEG_MODE_U1_S))
-#define PCNT_CH0_NEG_MODE_U1_V  0x3
-#define PCNT_CH0_NEG_MODE_U1_S  16
-/* PCNT_THR_THRES1_EN_U1 : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: */
-#define PCNT_THR_THRES1_EN_U1  (BIT(15))
-#define PCNT_THR_THRES1_EN_U1_M  (BIT(15))
-#define PCNT_THR_THRES1_EN_U1_V  0x1
-#define PCNT_THR_THRES1_EN_U1_S  15
-/* PCNT_THR_THRES0_EN_U1 : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: */
-#define PCNT_THR_THRES0_EN_U1  (BIT(14))
-#define PCNT_THR_THRES0_EN_U1_M  (BIT(14))
-#define PCNT_THR_THRES0_EN_U1_V  0x1
-#define PCNT_THR_THRES0_EN_U1_S  14
-/* PCNT_THR_L_LIM_EN_U1 : R/W ;bitpos:[13] ;default: 1'b1 ; */
-/*description: */
-#define PCNT_THR_L_LIM_EN_U1  (BIT(13))
-#define PCNT_THR_L_LIM_EN_U1_M  (BIT(13))
-#define PCNT_THR_L_LIM_EN_U1_V  0x1
-#define PCNT_THR_L_LIM_EN_U1_S  13
-/* PCNT_THR_H_LIM_EN_U1 : R/W ;bitpos:[12] ;default: 1'b1 ; */
-/*description: */
-#define PCNT_THR_H_LIM_EN_U1  (BIT(12))
-#define PCNT_THR_H_LIM_EN_U1_M  (BIT(12))
-#define PCNT_THR_H_LIM_EN_U1_V  0x1
-#define PCNT_THR_H_LIM_EN_U1_S  12
-/* PCNT_THR_ZERO_EN_U1 : R/W ;bitpos:[11] ;default: 1'b1 ; */
-/*description: */
-#define PCNT_THR_ZERO_EN_U1  (BIT(11))
-#define PCNT_THR_ZERO_EN_U1_M  (BIT(11))
-#define PCNT_THR_ZERO_EN_U1_V  0x1
-#define PCNT_THR_ZERO_EN_U1_S  11
-/* PCNT_FILTER_EN_U1 : R/W ;bitpos:[10] ;default: 1'b1 ; */
-/*description: */
-#define PCNT_FILTER_EN_U1  (BIT(10))
-#define PCNT_FILTER_EN_U1_M  (BIT(10))
-#define PCNT_FILTER_EN_U1_V  0x1
-#define PCNT_FILTER_EN_U1_S  10
-/* PCNT_FILTER_THRES_U1 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */
-/*description: */
-#define PCNT_FILTER_THRES_U1  0x000003FF
-#define PCNT_FILTER_THRES_U1_M  ((PCNT_FILTER_THRES_U1_V)<<(PCNT_FILTER_THRES_U1_S))
-#define PCNT_FILTER_THRES_U1_V  0x3FF
+/** PCNT_U1_CONF0_REG register
+ *  Configuration register 0 for unit 1
+ */
+#define PCNT_U1_CONF0_REG (DR_REG_PCNT_BASE + 0xc)
+/** PCNT_FILTER_THRES_U1 : R/W; bitpos: [9:0]; default: 16;
+ *  This sets the maximum threshold, in APB_CLK cycles, for the filter.
+ *
+ *  Any pulses with width less than this will be ignored when the filter is enabled.
+ */
+#define PCNT_FILTER_THRES_U1    0x000003FFU
+#define PCNT_FILTER_THRES_U1_M  (PCNT_FILTER_THRES_U1_V << PCNT_FILTER_THRES_U1_S)
+#define PCNT_FILTER_THRES_U1_V  0x000003FFU
 #define PCNT_FILTER_THRES_U1_S  0
+/** PCNT_FILTER_EN_U1 : R/W; bitpos: [10]; default: 1;
+ *  This is the enable bit for unit 1's input filter.
+ */
+#define PCNT_FILTER_EN_U1    (BIT(10))
+#define PCNT_FILTER_EN_U1_M  (PCNT_FILTER_EN_U1_V << PCNT_FILTER_EN_U1_S)
+#define PCNT_FILTER_EN_U1_V  0x00000001U
+#define PCNT_FILTER_EN_U1_S  10
+/** PCNT_THR_ZERO_EN_U1 : R/W; bitpos: [11]; default: 1;
+ *  This is the enable bit for unit 1's zero comparator.
+ */
+#define PCNT_THR_ZERO_EN_U1    (BIT(11))
+#define PCNT_THR_ZERO_EN_U1_M  (PCNT_THR_ZERO_EN_U1_V << PCNT_THR_ZERO_EN_U1_S)
+#define PCNT_THR_ZERO_EN_U1_V  0x00000001U
+#define PCNT_THR_ZERO_EN_U1_S  11
+/** PCNT_THR_H_LIM_EN_U1 : R/W; bitpos: [12]; default: 1;
+ *  This is the enable bit for unit 1's thr_h_lim comparator.
+ */
+#define PCNT_THR_H_LIM_EN_U1    (BIT(12))
+#define PCNT_THR_H_LIM_EN_U1_M  (PCNT_THR_H_LIM_EN_U1_V << PCNT_THR_H_LIM_EN_U1_S)
+#define PCNT_THR_H_LIM_EN_U1_V  0x00000001U
+#define PCNT_THR_H_LIM_EN_U1_S  12
+/** PCNT_THR_L_LIM_EN_U1 : R/W; bitpos: [13]; default: 1;
+ *  This is the enable bit for unit 1's thr_l_lim comparator.
+ */
+#define PCNT_THR_L_LIM_EN_U1    (BIT(13))
+#define PCNT_THR_L_LIM_EN_U1_M  (PCNT_THR_L_LIM_EN_U1_V << PCNT_THR_L_LIM_EN_U1_S)
+#define PCNT_THR_L_LIM_EN_U1_V  0x00000001U
+#define PCNT_THR_L_LIM_EN_U1_S  13
+/** PCNT_THR_THRES0_EN_U1 : R/W; bitpos: [14]; default: 0;
+ *  This is the enable bit for unit 1's thres0 comparator.
+ */
+#define PCNT_THR_THRES0_EN_U1    (BIT(14))
+#define PCNT_THR_THRES0_EN_U1_M  (PCNT_THR_THRES0_EN_U1_V << PCNT_THR_THRES0_EN_U1_S)
+#define PCNT_THR_THRES0_EN_U1_V  0x00000001U
+#define PCNT_THR_THRES0_EN_U1_S  14
+/** PCNT_THR_THRES1_EN_U1 : R/W; bitpos: [15]; default: 0;
+ *  This is the enable bit for unit 1's thres1 comparator.
+ */
+#define PCNT_THR_THRES1_EN_U1    (BIT(15))
+#define PCNT_THR_THRES1_EN_U1_M  (PCNT_THR_THRES1_EN_U1_V << PCNT_THR_THRES1_EN_U1_S)
+#define PCNT_THR_THRES1_EN_U1_V  0x00000001U
+#define PCNT_THR_THRES1_EN_U1_S  15
+/** PCNT_CH0_NEG_MODE_U1 : R/W; bitpos: [17:16]; default: 0;
+ *  This register sets the behavior when the signal input of channel 0 detects a
+ *  negative edge.
+ *
+ *  1: Increase the counter;2: Decrease the counter;0, 3: No effect on counter
+ */
+#define PCNT_CH0_NEG_MODE_U1    0x00000003U
+#define PCNT_CH0_NEG_MODE_U1_M  (PCNT_CH0_NEG_MODE_U1_V << PCNT_CH0_NEG_MODE_U1_S)
+#define PCNT_CH0_NEG_MODE_U1_V  0x00000003U
+#define PCNT_CH0_NEG_MODE_U1_S  16
+/** PCNT_CH0_POS_MODE_U1 : R/W; bitpos: [19:18]; default: 0;
+ *  This register sets the behavior when the signal input of channel 0 detects a
+ *  positive edge.
+ *
+ *  1: Increase the counter;2: Decrease the counter;0, 3: No effect on counter
+ */
+#define PCNT_CH0_POS_MODE_U1    0x00000003U
+#define PCNT_CH0_POS_MODE_U1_M  (PCNT_CH0_POS_MODE_U1_V << PCNT_CH0_POS_MODE_U1_S)
+#define PCNT_CH0_POS_MODE_U1_V  0x00000003U
+#define PCNT_CH0_POS_MODE_U1_S  18
+/** PCNT_CH0_HCTRL_MODE_U1 : R/W; bitpos: [21:20]; default: 0;
+ *  This register configures how the CH1_POS_MODE/CH1_NEG_MODE settings will be
+ *  modified when the control signal is high.
+ *
+ *  0: No modification;1: Invert behavior (increase -> decrease, decrease ->
+ *  increase);2, 3: Inhibit counter modification
+ */
+#define PCNT_CH0_HCTRL_MODE_U1    0x00000003U
+#define PCNT_CH0_HCTRL_MODE_U1_M  (PCNT_CH0_HCTRL_MODE_U1_V << PCNT_CH0_HCTRL_MODE_U1_S)
+#define PCNT_CH0_HCTRL_MODE_U1_V  0x00000003U
+#define PCNT_CH0_HCTRL_MODE_U1_S  20
+/** PCNT_CH0_LCTRL_MODE_U1 : R/W; bitpos: [23:22]; default: 0;
+ *  This register configures how the CH1_POS_MODE/CH1_NEG_MODE settings will be
+ *  modified when the control signal is low.
+ *
+ *  0: No modification;1: Invert behavior (increase -> decrease, decrease ->
+ *  increase);2, 3: Inhibit counter modification
+ */
+#define PCNT_CH0_LCTRL_MODE_U1    0x00000003U
+#define PCNT_CH0_LCTRL_MODE_U1_M  (PCNT_CH0_LCTRL_MODE_U1_V << PCNT_CH0_LCTRL_MODE_U1_S)
+#define PCNT_CH0_LCTRL_MODE_U1_V  0x00000003U
+#define PCNT_CH0_LCTRL_MODE_U1_S  22
+/** PCNT_CH1_NEG_MODE_U1 : R/W; bitpos: [25:24]; default: 0;
+ *  This register sets the behavior when the signal input of channel 1 detects a
+ *  negative edge.
+ *
+ *  1: Increment the counter;2: Decrement the counter;0, 3: No effect on counter
+ */
+#define PCNT_CH1_NEG_MODE_U1    0x00000003U
+#define PCNT_CH1_NEG_MODE_U1_M  (PCNT_CH1_NEG_MODE_U1_V << PCNT_CH1_NEG_MODE_U1_S)
+#define PCNT_CH1_NEG_MODE_U1_V  0x00000003U
+#define PCNT_CH1_NEG_MODE_U1_S  24
+/** PCNT_CH1_POS_MODE_U1 : R/W; bitpos: [27:26]; default: 0;
+ *  This register sets the behavior when the signal input of channel 1 detects a
+ *  positive edge.
+ *
+ *  1: Increment the counter;2: Decrement the counter;0, 3: No effect on counter
+ */
+#define PCNT_CH1_POS_MODE_U1    0x00000003U
+#define PCNT_CH1_POS_MODE_U1_M  (PCNT_CH1_POS_MODE_U1_V << PCNT_CH1_POS_MODE_U1_S)
+#define PCNT_CH1_POS_MODE_U1_V  0x00000003U
+#define PCNT_CH1_POS_MODE_U1_S  26
+/** PCNT_CH1_HCTRL_MODE_U1 : R/W; bitpos: [29:28]; default: 0;
+ *  This register configures how the CH1_POS_MODE/CH1_NEG_MODE settings will be
+ *  modified when the control signal is high.
+ *
+ *  0: No modification;1: Invert behavior (increase -> decrease, decrease ->
+ *  increase);2, 3: Inhibit counter modification
+ */
+#define PCNT_CH1_HCTRL_MODE_U1    0x00000003U
+#define PCNT_CH1_HCTRL_MODE_U1_M  (PCNT_CH1_HCTRL_MODE_U1_V << PCNT_CH1_HCTRL_MODE_U1_S)
+#define PCNT_CH1_HCTRL_MODE_U1_V  0x00000003U
+#define PCNT_CH1_HCTRL_MODE_U1_S  28
+/** PCNT_CH1_LCTRL_MODE_U1 : R/W; bitpos: [31:30]; default: 0;
+ *  This register configures how the CH1_POS_MODE/CH1_NEG_MODE settings will be
+ *  modified when the control signal is low.
+ *
+ *  0: No modification;1: Invert behavior (increase -> decrease, decrease ->
+ *  increase);2, 3: Inhibit counter modification
+ */
+#define PCNT_CH1_LCTRL_MODE_U1    0x00000003U
+#define PCNT_CH1_LCTRL_MODE_U1_M  (PCNT_CH1_LCTRL_MODE_U1_V << PCNT_CH1_LCTRL_MODE_U1_S)
+#define PCNT_CH1_LCTRL_MODE_U1_V  0x00000003U
+#define PCNT_CH1_LCTRL_MODE_U1_S  30
 
-#define PCNT_U1_CONF1_REG          (DR_REG_PCNT_BASE + 0x0010)
-/* PCNT_CNT_THRES1_U1 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */
-/*description: */
-#define PCNT_CNT_THRES1_U1  0x0000FFFF
-#define PCNT_CNT_THRES1_U1_M  ((PCNT_CNT_THRES1_U1_V)<<(PCNT_CNT_THRES1_U1_S))
-#define PCNT_CNT_THRES1_U1_V  0xFFFF
-#define PCNT_CNT_THRES1_U1_S  16
-/* PCNT_CNT_THRES0_U1 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */
-/*description: */
-#define PCNT_CNT_THRES0_U1  0x0000FFFF
-#define PCNT_CNT_THRES0_U1_M  ((PCNT_CNT_THRES0_U1_V)<<(PCNT_CNT_THRES0_U1_S))
-#define PCNT_CNT_THRES0_U1_V  0xFFFF
+/** PCNT_U1_CONF1_REG register
+ *  Configuration register 1 for unit 1
+ */
+#define PCNT_U1_CONF1_REG (DR_REG_PCNT_BASE + 0x10)
+/** PCNT_CNT_THRES0_U1 : R/W; bitpos: [15:0]; default: 0;
+ *  This register is used to configure the thres0 value for unit 1.
+ */
+#define PCNT_CNT_THRES0_U1    0x0000FFFFU
+#define PCNT_CNT_THRES0_U1_M  (PCNT_CNT_THRES0_U1_V << PCNT_CNT_THRES0_U1_S)
+#define PCNT_CNT_THRES0_U1_V  0x0000FFFFU
 #define PCNT_CNT_THRES0_U1_S  0
+/** PCNT_CNT_THRES1_U1 : R/W; bitpos: [31:16]; default: 0;
+ *  This register is used to configure the thres1 value for unit 1.
+ */
+#define PCNT_CNT_THRES1_U1    0x0000FFFFU
+#define PCNT_CNT_THRES1_U1_M  (PCNT_CNT_THRES1_U1_V << PCNT_CNT_THRES1_U1_S)
+#define PCNT_CNT_THRES1_U1_V  0x0000FFFFU
+#define PCNT_CNT_THRES1_U1_S  16
 
-#define PCNT_U1_CONF2_REG          (DR_REG_PCNT_BASE + 0x0014)
-/* PCNT_CNT_L_LIM_U1 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */
-/*description: */
-#define PCNT_CNT_L_LIM_U1  0x0000FFFF
-#define PCNT_CNT_L_LIM_U1_M  ((PCNT_CNT_L_LIM_U1_V)<<(PCNT_CNT_L_LIM_U1_S))
-#define PCNT_CNT_L_LIM_U1_V  0xFFFF
-#define PCNT_CNT_L_LIM_U1_S  16
-/* PCNT_CNT_H_LIM_U1 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */
-/*description: */
-#define PCNT_CNT_H_LIM_U1  0x0000FFFF
-#define PCNT_CNT_H_LIM_U1_M  ((PCNT_CNT_H_LIM_U1_V)<<(PCNT_CNT_H_LIM_U1_S))
-#define PCNT_CNT_H_LIM_U1_V  0xFFFF
+/** PCNT_U1_CONF2_REG register
+ *  Configuration register 2 for unit 1
+ */
+#define PCNT_U1_CONF2_REG (DR_REG_PCNT_BASE + 0x14)
+/** PCNT_CNT_H_LIM_U1 : R/W; bitpos: [15:0]; default: 0;
+ *  This register is used to configure the thr_h_lim value for unit 1.
+ */
+#define PCNT_CNT_H_LIM_U1    0x0000FFFFU
+#define PCNT_CNT_H_LIM_U1_M  (PCNT_CNT_H_LIM_U1_V << PCNT_CNT_H_LIM_U1_S)
+#define PCNT_CNT_H_LIM_U1_V  0x0000FFFFU
 #define PCNT_CNT_H_LIM_U1_S  0
+/** PCNT_CNT_L_LIM_U1 : R/W; bitpos: [31:16]; default: 0;
+ *  This register is used to configure the thr_l_lim value for unit 1.
+ */
+#define PCNT_CNT_L_LIM_U1    0x0000FFFFU
+#define PCNT_CNT_L_LIM_U1_M  (PCNT_CNT_L_LIM_U1_V << PCNT_CNT_L_LIM_U1_S)
+#define PCNT_CNT_L_LIM_U1_V  0x0000FFFFU
+#define PCNT_CNT_L_LIM_U1_S  16
 
-#define PCNT_U2_CONF0_REG          (DR_REG_PCNT_BASE + 0x0018)
-/* PCNT_CH1_LCTRL_MODE_U2 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */
-/*description: */
-#define PCNT_CH1_LCTRL_MODE_U2  0x00000003
-#define PCNT_CH1_LCTRL_MODE_U2_M  ((PCNT_CH1_LCTRL_MODE_U2_V)<<(PCNT_CH1_LCTRL_MODE_U2_S))
-#define PCNT_CH1_LCTRL_MODE_U2_V  0x3
-#define PCNT_CH1_LCTRL_MODE_U2_S  30
-/* PCNT_CH1_HCTRL_MODE_U2 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */
-/*description: */
-#define PCNT_CH1_HCTRL_MODE_U2  0x00000003
-#define PCNT_CH1_HCTRL_MODE_U2_M  ((PCNT_CH1_HCTRL_MODE_U2_V)<<(PCNT_CH1_HCTRL_MODE_U2_S))
-#define PCNT_CH1_HCTRL_MODE_U2_V  0x3
-#define PCNT_CH1_HCTRL_MODE_U2_S  28
-/* PCNT_CH1_POS_MODE_U2 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */
-/*description: */
-#define PCNT_CH1_POS_MODE_U2  0x00000003
-#define PCNT_CH1_POS_MODE_U2_M  ((PCNT_CH1_POS_MODE_U2_V)<<(PCNT_CH1_POS_MODE_U2_S))
-#define PCNT_CH1_POS_MODE_U2_V  0x3
-#define PCNT_CH1_POS_MODE_U2_S  26
-/* PCNT_CH1_NEG_MODE_U2 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */
-/*description: */
-#define PCNT_CH1_NEG_MODE_U2  0x00000003
-#define PCNT_CH1_NEG_MODE_U2_M  ((PCNT_CH1_NEG_MODE_U2_V)<<(PCNT_CH1_NEG_MODE_U2_S))
-#define PCNT_CH1_NEG_MODE_U2_V  0x3
-#define PCNT_CH1_NEG_MODE_U2_S  24
-/* PCNT_CH0_LCTRL_MODE_U2 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */
-/*description: */
-#define PCNT_CH0_LCTRL_MODE_U2  0x00000003
-#define PCNT_CH0_LCTRL_MODE_U2_M  ((PCNT_CH0_LCTRL_MODE_U2_V)<<(PCNT_CH0_LCTRL_MODE_U2_S))
-#define PCNT_CH0_LCTRL_MODE_U2_V  0x3
-#define PCNT_CH0_LCTRL_MODE_U2_S  22
-/* PCNT_CH0_HCTRL_MODE_U2 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */
-/*description: */
-#define PCNT_CH0_HCTRL_MODE_U2  0x00000003
-#define PCNT_CH0_HCTRL_MODE_U2_M  ((PCNT_CH0_HCTRL_MODE_U2_V)<<(PCNT_CH0_HCTRL_MODE_U2_S))
-#define PCNT_CH0_HCTRL_MODE_U2_V  0x3
-#define PCNT_CH0_HCTRL_MODE_U2_S  20
-/* PCNT_CH0_POS_MODE_U2 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */
-/*description: */
-#define PCNT_CH0_POS_MODE_U2  0x00000003
-#define PCNT_CH0_POS_MODE_U2_M  ((PCNT_CH0_POS_MODE_U2_V)<<(PCNT_CH0_POS_MODE_U2_S))
-#define PCNT_CH0_POS_MODE_U2_V  0x3
-#define PCNT_CH0_POS_MODE_U2_S  18
-/* PCNT_CH0_NEG_MODE_U2 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */
-/*description: */
-#define PCNT_CH0_NEG_MODE_U2  0x00000003
-#define PCNT_CH0_NEG_MODE_U2_M  ((PCNT_CH0_NEG_MODE_U2_V)<<(PCNT_CH0_NEG_MODE_U2_S))
-#define PCNT_CH0_NEG_MODE_U2_V  0x3
-#define PCNT_CH0_NEG_MODE_U2_S  16
-/* PCNT_THR_THRES1_EN_U2 : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: */
-#define PCNT_THR_THRES1_EN_U2  (BIT(15))
-#define PCNT_THR_THRES1_EN_U2_M  (BIT(15))
-#define PCNT_THR_THRES1_EN_U2_V  0x1
-#define PCNT_THR_THRES1_EN_U2_S  15
-/* PCNT_THR_THRES0_EN_U2 : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: */
-#define PCNT_THR_THRES0_EN_U2  (BIT(14))
-#define PCNT_THR_THRES0_EN_U2_M  (BIT(14))
-#define PCNT_THR_THRES0_EN_U2_V  0x1
-#define PCNT_THR_THRES0_EN_U2_S  14
-/* PCNT_THR_L_LIM_EN_U2 : R/W ;bitpos:[13] ;default: 1'b1 ; */
-/*description: */
-#define PCNT_THR_L_LIM_EN_U2  (BIT(13))
-#define PCNT_THR_L_LIM_EN_U2_M  (BIT(13))
-#define PCNT_THR_L_LIM_EN_U2_V  0x1
-#define PCNT_THR_L_LIM_EN_U2_S  13
-/* PCNT_THR_H_LIM_EN_U2 : R/W ;bitpos:[12] ;default: 1'b1 ; */
-/*description: */
-#define PCNT_THR_H_LIM_EN_U2  (BIT(12))
-#define PCNT_THR_H_LIM_EN_U2_M  (BIT(12))
-#define PCNT_THR_H_LIM_EN_U2_V  0x1
-#define PCNT_THR_H_LIM_EN_U2_S  12
-/* PCNT_THR_ZERO_EN_U2 : R/W ;bitpos:[11] ;default: 1'b1 ; */
-/*description: */
-#define PCNT_THR_ZERO_EN_U2  (BIT(11))
-#define PCNT_THR_ZERO_EN_U2_M  (BIT(11))
-#define PCNT_THR_ZERO_EN_U2_V  0x1
-#define PCNT_THR_ZERO_EN_U2_S  11
-/* PCNT_FILTER_EN_U2 : R/W ;bitpos:[10] ;default: 1'b1 ; */
-/*description: */
-#define PCNT_FILTER_EN_U2  (BIT(10))
-#define PCNT_FILTER_EN_U2_M  (BIT(10))
-#define PCNT_FILTER_EN_U2_V  0x1
-#define PCNT_FILTER_EN_U2_S  10
-/* PCNT_FILTER_THRES_U2 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */
-/*description: */
-#define PCNT_FILTER_THRES_U2  0x000003FF
-#define PCNT_FILTER_THRES_U2_M  ((PCNT_FILTER_THRES_U2_V)<<(PCNT_FILTER_THRES_U2_S))
-#define PCNT_FILTER_THRES_U2_V  0x3FF
+/** PCNT_U2_CONF0_REG register
+ *  Configuration register 0 for unit 2
+ */
+#define PCNT_U2_CONF0_REG (DR_REG_PCNT_BASE + 0x18)
+/** PCNT_FILTER_THRES_U2 : R/W; bitpos: [9:0]; default: 16;
+ *  This sets the maximum threshold, in APB_CLK cycles, for the filter.
+ *
+ *  Any pulses with width less than this will be ignored when the filter is enabled.
+ */
+#define PCNT_FILTER_THRES_U2    0x000003FFU
+#define PCNT_FILTER_THRES_U2_M  (PCNT_FILTER_THRES_U2_V << PCNT_FILTER_THRES_U2_S)
+#define PCNT_FILTER_THRES_U2_V  0x000003FFU
 #define PCNT_FILTER_THRES_U2_S  0
+/** PCNT_FILTER_EN_U2 : R/W; bitpos: [10]; default: 1;
+ *  This is the enable bit for unit 2's input filter.
+ */
+#define PCNT_FILTER_EN_U2    (BIT(10))
+#define PCNT_FILTER_EN_U2_M  (PCNT_FILTER_EN_U2_V << PCNT_FILTER_EN_U2_S)
+#define PCNT_FILTER_EN_U2_V  0x00000001U
+#define PCNT_FILTER_EN_U2_S  10
+/** PCNT_THR_ZERO_EN_U2 : R/W; bitpos: [11]; default: 1;
+ *  This is the enable bit for unit 2's zero comparator.
+ */
+#define PCNT_THR_ZERO_EN_U2    (BIT(11))
+#define PCNT_THR_ZERO_EN_U2_M  (PCNT_THR_ZERO_EN_U2_V << PCNT_THR_ZERO_EN_U2_S)
+#define PCNT_THR_ZERO_EN_U2_V  0x00000001U
+#define PCNT_THR_ZERO_EN_U2_S  11
+/** PCNT_THR_H_LIM_EN_U2 : R/W; bitpos: [12]; default: 1;
+ *  This is the enable bit for unit 2's thr_h_lim comparator.
+ */
+#define PCNT_THR_H_LIM_EN_U2    (BIT(12))
+#define PCNT_THR_H_LIM_EN_U2_M  (PCNT_THR_H_LIM_EN_U2_V << PCNT_THR_H_LIM_EN_U2_S)
+#define PCNT_THR_H_LIM_EN_U2_V  0x00000001U
+#define PCNT_THR_H_LIM_EN_U2_S  12
+/** PCNT_THR_L_LIM_EN_U2 : R/W; bitpos: [13]; default: 1;
+ *  This is the enable bit for unit 2's thr_l_lim comparator.
+ */
+#define PCNT_THR_L_LIM_EN_U2    (BIT(13))
+#define PCNT_THR_L_LIM_EN_U2_M  (PCNT_THR_L_LIM_EN_U2_V << PCNT_THR_L_LIM_EN_U2_S)
+#define PCNT_THR_L_LIM_EN_U2_V  0x00000001U
+#define PCNT_THR_L_LIM_EN_U2_S  13
+/** PCNT_THR_THRES0_EN_U2 : R/W; bitpos: [14]; default: 0;
+ *  This is the enable bit for unit 2's thres0 comparator.
+ */
+#define PCNT_THR_THRES0_EN_U2    (BIT(14))
+#define PCNT_THR_THRES0_EN_U2_M  (PCNT_THR_THRES0_EN_U2_V << PCNT_THR_THRES0_EN_U2_S)
+#define PCNT_THR_THRES0_EN_U2_V  0x00000001U
+#define PCNT_THR_THRES0_EN_U2_S  14
+/** PCNT_THR_THRES1_EN_U2 : R/W; bitpos: [15]; default: 0;
+ *  This is the enable bit for unit 2's thres1 comparator.
+ */
+#define PCNT_THR_THRES1_EN_U2    (BIT(15))
+#define PCNT_THR_THRES1_EN_U2_M  (PCNT_THR_THRES1_EN_U2_V << PCNT_THR_THRES1_EN_U2_S)
+#define PCNT_THR_THRES1_EN_U2_V  0x00000001U
+#define PCNT_THR_THRES1_EN_U2_S  15
+/** PCNT_CH0_NEG_MODE_U2 : R/W; bitpos: [17:16]; default: 0;
+ *  This register sets the behavior when the signal input of channel 0 detects a
+ *  negative edge.
+ *
+ *  1: Increase the counter;2: Decrease the counter;0, 3: No effect on counter
+ */
+#define PCNT_CH0_NEG_MODE_U2    0x00000003U
+#define PCNT_CH0_NEG_MODE_U2_M  (PCNT_CH0_NEG_MODE_U2_V << PCNT_CH0_NEG_MODE_U2_S)
+#define PCNT_CH0_NEG_MODE_U2_V  0x00000003U
+#define PCNT_CH0_NEG_MODE_U2_S  16
+/** PCNT_CH0_POS_MODE_U2 : R/W; bitpos: [19:18]; default: 0;
+ *  This register sets the behavior when the signal input of channel 0 detects a
+ *  positive edge.
+ *
+ *  1: Increase the counter;2: Decrease the counter;0, 3: No effect on counter
+ */
+#define PCNT_CH0_POS_MODE_U2    0x00000003U
+#define PCNT_CH0_POS_MODE_U2_M  (PCNT_CH0_POS_MODE_U2_V << PCNT_CH0_POS_MODE_U2_S)
+#define PCNT_CH0_POS_MODE_U2_V  0x00000003U
+#define PCNT_CH0_POS_MODE_U2_S  18
+/** PCNT_CH0_HCTRL_MODE_U2 : R/W; bitpos: [21:20]; default: 0;
+ *  This register configures how the CH2_POS_MODE/CH2_NEG_MODE settings will be
+ *  modified when the control signal is high.
+ *
+ *  0: No modification;1: Invert behavior (increase -> decrease, decrease ->
+ *  increase);2, 3: Inhibit counter modification
+ */
+#define PCNT_CH0_HCTRL_MODE_U2    0x00000003U
+#define PCNT_CH0_HCTRL_MODE_U2_M  (PCNT_CH0_HCTRL_MODE_U2_V << PCNT_CH0_HCTRL_MODE_U2_S)
+#define PCNT_CH0_HCTRL_MODE_U2_V  0x00000003U
+#define PCNT_CH0_HCTRL_MODE_U2_S  20
+/** PCNT_CH0_LCTRL_MODE_U2 : R/W; bitpos: [23:22]; default: 0;
+ *  This register configures how the CH2_POS_MODE/CH2_NEG_MODE settings will be
+ *  modified when the control signal is low.
+ *
+ *  0: No modification;1: Invert behavior (increase -> decrease, decrease ->
+ *  increase);2, 3: Inhibit counter modification
+ */
+#define PCNT_CH0_LCTRL_MODE_U2    0x00000003U
+#define PCNT_CH0_LCTRL_MODE_U2_M  (PCNT_CH0_LCTRL_MODE_U2_V << PCNT_CH0_LCTRL_MODE_U2_S)
+#define PCNT_CH0_LCTRL_MODE_U2_V  0x00000003U
+#define PCNT_CH0_LCTRL_MODE_U2_S  22
+/** PCNT_CH1_NEG_MODE_U2 : R/W; bitpos: [25:24]; default: 0;
+ *  This register sets the behavior when the signal input of channel 1 detects a
+ *  negative edge.
+ *
+ *  1: Increment the counter;2: Decrement the counter;0, 3: No effect on counter
+ */
+#define PCNT_CH1_NEG_MODE_U2    0x00000003U
+#define PCNT_CH1_NEG_MODE_U2_M  (PCNT_CH1_NEG_MODE_U2_V << PCNT_CH1_NEG_MODE_U2_S)
+#define PCNT_CH1_NEG_MODE_U2_V  0x00000003U
+#define PCNT_CH1_NEG_MODE_U2_S  24
+/** PCNT_CH1_POS_MODE_U2 : R/W; bitpos: [27:26]; default: 0;
+ *  This register sets the behavior when the signal input of channel 1 detects a
+ *  positive edge.
+ *
+ *  1: Increment the counter;2: Decrement the counter;0, 3: No effect on counter
+ */
+#define PCNT_CH1_POS_MODE_U2    0x00000003U
+#define PCNT_CH1_POS_MODE_U2_M  (PCNT_CH1_POS_MODE_U2_V << PCNT_CH1_POS_MODE_U2_S)
+#define PCNT_CH1_POS_MODE_U2_V  0x00000003U
+#define PCNT_CH1_POS_MODE_U2_S  26
+/** PCNT_CH1_HCTRL_MODE_U2 : R/W; bitpos: [29:28]; default: 0;
+ *  This register configures how the CH2_POS_MODE/CH2_NEG_MODE settings will be
+ *  modified when the control signal is high.
+ *
+ *  0: No modification;1: Invert behavior (increase -> decrease, decrease ->
+ *  increase);2, 3: Inhibit counter modification
+ */
+#define PCNT_CH1_HCTRL_MODE_U2    0x00000003U
+#define PCNT_CH1_HCTRL_MODE_U2_M  (PCNT_CH1_HCTRL_MODE_U2_V << PCNT_CH1_HCTRL_MODE_U2_S)
+#define PCNT_CH1_HCTRL_MODE_U2_V  0x00000003U
+#define PCNT_CH1_HCTRL_MODE_U2_S  28
+/** PCNT_CH1_LCTRL_MODE_U2 : R/W; bitpos: [31:30]; default: 0;
+ *  This register configures how the CH2_POS_MODE/CH2_NEG_MODE settings will be
+ *  modified when the control signal is low.
+ *
+ *  0: No modification;1: Invert behavior (increase -> decrease, decrease ->
+ *  increase);2, 3: Inhibit counter modification
+ */
+#define PCNT_CH1_LCTRL_MODE_U2    0x00000003U
+#define PCNT_CH1_LCTRL_MODE_U2_M  (PCNT_CH1_LCTRL_MODE_U2_V << PCNT_CH1_LCTRL_MODE_U2_S)
+#define PCNT_CH1_LCTRL_MODE_U2_V  0x00000003U
+#define PCNT_CH1_LCTRL_MODE_U2_S  30
 
-#define PCNT_U2_CONF1_REG          (DR_REG_PCNT_BASE + 0x001c)
-/* PCNT_CNT_THRES1_U2 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */
-/*description: */
-#define PCNT_CNT_THRES1_U2  0x0000FFFF
-#define PCNT_CNT_THRES1_U2_M  ((PCNT_CNT_THRES1_U2_V)<<(PCNT_CNT_THRES1_U2_S))
-#define PCNT_CNT_THRES1_U2_V  0xFFFF
-#define PCNT_CNT_THRES1_U2_S  16
-/* PCNT_CNT_THRES0_U2 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */
-/*description: */
-#define PCNT_CNT_THRES0_U2  0x0000FFFF
-#define PCNT_CNT_THRES0_U2_M  ((PCNT_CNT_THRES0_U2_V)<<(PCNT_CNT_THRES0_U2_S))
-#define PCNT_CNT_THRES0_U2_V  0xFFFF
+/** PCNT_U2_CONF1_REG register
+ *  Configuration register 1 for unit 2
+ */
+#define PCNT_U2_CONF1_REG (DR_REG_PCNT_BASE + 0x1c)
+/** PCNT_CNT_THRES0_U2 : R/W; bitpos: [15:0]; default: 0;
+ *  This register is used to configure the thres0 value for unit 2.
+ */
+#define PCNT_CNT_THRES0_U2    0x0000FFFFU
+#define PCNT_CNT_THRES0_U2_M  (PCNT_CNT_THRES0_U2_V << PCNT_CNT_THRES0_U2_S)
+#define PCNT_CNT_THRES0_U2_V  0x0000FFFFU
 #define PCNT_CNT_THRES0_U2_S  0
+/** PCNT_CNT_THRES1_U2 : R/W; bitpos: [31:16]; default: 0;
+ *  This register is used to configure the thres1 value for unit 2.
+ */
+#define PCNT_CNT_THRES1_U2    0x0000FFFFU
+#define PCNT_CNT_THRES1_U2_M  (PCNT_CNT_THRES1_U2_V << PCNT_CNT_THRES1_U2_S)
+#define PCNT_CNT_THRES1_U2_V  0x0000FFFFU
+#define PCNT_CNT_THRES1_U2_S  16
 
-#define PCNT_U2_CONF2_REG          (DR_REG_PCNT_BASE + 0x0020)
-/* PCNT_CNT_L_LIM_U2 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */
-/*description: */
-#define PCNT_CNT_L_LIM_U2  0x0000FFFF
-#define PCNT_CNT_L_LIM_U2_M  ((PCNT_CNT_L_LIM_U2_V)<<(PCNT_CNT_L_LIM_U2_S))
-#define PCNT_CNT_L_LIM_U2_V  0xFFFF
-#define PCNT_CNT_L_LIM_U2_S  16
-/* PCNT_CNT_H_LIM_U2 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */
-/*description: */
-#define PCNT_CNT_H_LIM_U2  0x0000FFFF
-#define PCNT_CNT_H_LIM_U2_M  ((PCNT_CNT_H_LIM_U2_V)<<(PCNT_CNT_H_LIM_U2_S))
-#define PCNT_CNT_H_LIM_U2_V  0xFFFF
+/** PCNT_U2_CONF2_REG register
+ *  Configuration register 2 for unit 2
+ */
+#define PCNT_U2_CONF2_REG (DR_REG_PCNT_BASE + 0x20)
+/** PCNT_CNT_H_LIM_U2 : R/W; bitpos: [15:0]; default: 0;
+ *  This register is used to configure the thr_h_lim value for unit 2.
+ */
+#define PCNT_CNT_H_LIM_U2    0x0000FFFFU
+#define PCNT_CNT_H_LIM_U2_M  (PCNT_CNT_H_LIM_U2_V << PCNT_CNT_H_LIM_U2_S)
+#define PCNT_CNT_H_LIM_U2_V  0x0000FFFFU
 #define PCNT_CNT_H_LIM_U2_S  0
+/** PCNT_CNT_L_LIM_U2 : R/W; bitpos: [31:16]; default: 0;
+ *  This register is used to configure the thr_l_lim value for unit 2.
+ */
+#define PCNT_CNT_L_LIM_U2    0x0000FFFFU
+#define PCNT_CNT_L_LIM_U2_M  (PCNT_CNT_L_LIM_U2_V << PCNT_CNT_L_LIM_U2_S)
+#define PCNT_CNT_L_LIM_U2_V  0x0000FFFFU
+#define PCNT_CNT_L_LIM_U2_S  16
 
-#define PCNT_U3_CONF0_REG          (DR_REG_PCNT_BASE + 0x0024)
-/* PCNT_CH1_LCTRL_MODE_U3 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */
-/*description: */
-#define PCNT_CH1_LCTRL_MODE_U3  0x00000003
-#define PCNT_CH1_LCTRL_MODE_U3_M  ((PCNT_CH1_LCTRL_MODE_U3_V)<<(PCNT_CH1_LCTRL_MODE_U3_S))
-#define PCNT_CH1_LCTRL_MODE_U3_V  0x3
-#define PCNT_CH1_LCTRL_MODE_U3_S  30
-/* PCNT_CH1_HCTRL_MODE_U3 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */
-/*description: */
-#define PCNT_CH1_HCTRL_MODE_U3  0x00000003
-#define PCNT_CH1_HCTRL_MODE_U3_M  ((PCNT_CH1_HCTRL_MODE_U3_V)<<(PCNT_CH1_HCTRL_MODE_U3_S))
-#define PCNT_CH1_HCTRL_MODE_U3_V  0x3
-#define PCNT_CH1_HCTRL_MODE_U3_S  28
-/* PCNT_CH1_POS_MODE_U3 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */
-/*description: */
-#define PCNT_CH1_POS_MODE_U3  0x00000003
-#define PCNT_CH1_POS_MODE_U3_M  ((PCNT_CH1_POS_MODE_U3_V)<<(PCNT_CH1_POS_MODE_U3_S))
-#define PCNT_CH1_POS_MODE_U3_V  0x3
-#define PCNT_CH1_POS_MODE_U3_S  26
-/* PCNT_CH1_NEG_MODE_U3 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */
-/*description: */
-#define PCNT_CH1_NEG_MODE_U3  0x00000003
-#define PCNT_CH1_NEG_MODE_U3_M  ((PCNT_CH1_NEG_MODE_U3_V)<<(PCNT_CH1_NEG_MODE_U3_S))
-#define PCNT_CH1_NEG_MODE_U3_V  0x3
-#define PCNT_CH1_NEG_MODE_U3_S  24
-/* PCNT_CH0_LCTRL_MODE_U3 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */
-/*description: */
-#define PCNT_CH0_LCTRL_MODE_U3  0x00000003
-#define PCNT_CH0_LCTRL_MODE_U3_M  ((PCNT_CH0_LCTRL_MODE_U3_V)<<(PCNT_CH0_LCTRL_MODE_U3_S))
-#define PCNT_CH0_LCTRL_MODE_U3_V  0x3
-#define PCNT_CH0_LCTRL_MODE_U3_S  22
-/* PCNT_CH0_HCTRL_MODE_U3 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */
-/*description: */
-#define PCNT_CH0_HCTRL_MODE_U3  0x00000003
-#define PCNT_CH0_HCTRL_MODE_U3_M  ((PCNT_CH0_HCTRL_MODE_U3_V)<<(PCNT_CH0_HCTRL_MODE_U3_S))
-#define PCNT_CH0_HCTRL_MODE_U3_V  0x3
-#define PCNT_CH0_HCTRL_MODE_U3_S  20
-/* PCNT_CH0_POS_MODE_U3 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */
-/*description: */
-#define PCNT_CH0_POS_MODE_U3  0x00000003
-#define PCNT_CH0_POS_MODE_U3_M  ((PCNT_CH0_POS_MODE_U3_V)<<(PCNT_CH0_POS_MODE_U3_S))
-#define PCNT_CH0_POS_MODE_U3_V  0x3
-#define PCNT_CH0_POS_MODE_U3_S  18
-/* PCNT_CH0_NEG_MODE_U3 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */
-/*description: */
-#define PCNT_CH0_NEG_MODE_U3  0x00000003
-#define PCNT_CH0_NEG_MODE_U3_M  ((PCNT_CH0_NEG_MODE_U3_V)<<(PCNT_CH0_NEG_MODE_U3_S))
-#define PCNT_CH0_NEG_MODE_U3_V  0x3
-#define PCNT_CH0_NEG_MODE_U3_S  16
-/* PCNT_THR_THRES1_EN_U3 : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: */
-#define PCNT_THR_THRES1_EN_U3  (BIT(15))
-#define PCNT_THR_THRES1_EN_U3_M  (BIT(15))
-#define PCNT_THR_THRES1_EN_U3_V  0x1
-#define PCNT_THR_THRES1_EN_U3_S  15
-/* PCNT_THR_THRES0_EN_U3 : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: */
-#define PCNT_THR_THRES0_EN_U3  (BIT(14))
-#define PCNT_THR_THRES0_EN_U3_M  (BIT(14))
-#define PCNT_THR_THRES0_EN_U3_V  0x1
-#define PCNT_THR_THRES0_EN_U3_S  14
-/* PCNT_THR_L_LIM_EN_U3 : R/W ;bitpos:[13] ;default: 1'b1 ; */
-/*description: */
-#define PCNT_THR_L_LIM_EN_U3  (BIT(13))
-#define PCNT_THR_L_LIM_EN_U3_M  (BIT(13))
-#define PCNT_THR_L_LIM_EN_U3_V  0x1
-#define PCNT_THR_L_LIM_EN_U3_S  13
-/* PCNT_THR_H_LIM_EN_U3 : R/W ;bitpos:[12] ;default: 1'b1 ; */
-/*description: */
-#define PCNT_THR_H_LIM_EN_U3  (BIT(12))
-#define PCNT_THR_H_LIM_EN_U3_M  (BIT(12))
-#define PCNT_THR_H_LIM_EN_U3_V  0x1
-#define PCNT_THR_H_LIM_EN_U3_S  12
-/* PCNT_THR_ZERO_EN_U3 : R/W ;bitpos:[11] ;default: 1'b1 ; */
-/*description: */
-#define PCNT_THR_ZERO_EN_U3  (BIT(11))
-#define PCNT_THR_ZERO_EN_U3_M  (BIT(11))
-#define PCNT_THR_ZERO_EN_U3_V  0x1
-#define PCNT_THR_ZERO_EN_U3_S  11
-/* PCNT_FILTER_EN_U3 : R/W ;bitpos:[10] ;default: 1'b1 ; */
-/*description: */
-#define PCNT_FILTER_EN_U3  (BIT(10))
-#define PCNT_FILTER_EN_U3_M  (BIT(10))
-#define PCNT_FILTER_EN_U3_V  0x1
-#define PCNT_FILTER_EN_U3_S  10
-/* PCNT_FILTER_THRES_U3 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */
-/*description: */
-#define PCNT_FILTER_THRES_U3  0x000003FF
-#define PCNT_FILTER_THRES_U3_M  ((PCNT_FILTER_THRES_U3_V)<<(PCNT_FILTER_THRES_U3_S))
-#define PCNT_FILTER_THRES_U3_V  0x3FF
+/** PCNT_U3_CONF0_REG register
+ *  Configuration register 0 for unit 3
+ */
+#define PCNT_U3_CONF0_REG (DR_REG_PCNT_BASE + 0x24)
+/** PCNT_FILTER_THRES_U3 : R/W; bitpos: [9:0]; default: 16;
+ *  This sets the maximum threshold, in APB_CLK cycles, for the filter.
+ *
+ *  Any pulses with width less than this will be ignored when the filter is enabled.
+ */
+#define PCNT_FILTER_THRES_U3    0x000003FFU
+#define PCNT_FILTER_THRES_U3_M  (PCNT_FILTER_THRES_U3_V << PCNT_FILTER_THRES_U3_S)
+#define PCNT_FILTER_THRES_U3_V  0x000003FFU
 #define PCNT_FILTER_THRES_U3_S  0
+/** PCNT_FILTER_EN_U3 : R/W; bitpos: [10]; default: 1;
+ *  This is the enable bit for unit 3's input filter.
+ */
+#define PCNT_FILTER_EN_U3    (BIT(10))
+#define PCNT_FILTER_EN_U3_M  (PCNT_FILTER_EN_U3_V << PCNT_FILTER_EN_U3_S)
+#define PCNT_FILTER_EN_U3_V  0x00000001U
+#define PCNT_FILTER_EN_U3_S  10
+/** PCNT_THR_ZERO_EN_U3 : R/W; bitpos: [11]; default: 1;
+ *  This is the enable bit for unit 3's zero comparator.
+ */
+#define PCNT_THR_ZERO_EN_U3    (BIT(11))
+#define PCNT_THR_ZERO_EN_U3_M  (PCNT_THR_ZERO_EN_U3_V << PCNT_THR_ZERO_EN_U3_S)
+#define PCNT_THR_ZERO_EN_U3_V  0x00000001U
+#define PCNT_THR_ZERO_EN_U3_S  11
+/** PCNT_THR_H_LIM_EN_U3 : R/W; bitpos: [12]; default: 1;
+ *  This is the enable bit for unit 3's thr_h_lim comparator.
+ */
+#define PCNT_THR_H_LIM_EN_U3    (BIT(12))
+#define PCNT_THR_H_LIM_EN_U3_M  (PCNT_THR_H_LIM_EN_U3_V << PCNT_THR_H_LIM_EN_U3_S)
+#define PCNT_THR_H_LIM_EN_U3_V  0x00000001U
+#define PCNT_THR_H_LIM_EN_U3_S  12
+/** PCNT_THR_L_LIM_EN_U3 : R/W; bitpos: [13]; default: 1;
+ *  This is the enable bit for unit 3's thr_l_lim comparator.
+ */
+#define PCNT_THR_L_LIM_EN_U3    (BIT(13))
+#define PCNT_THR_L_LIM_EN_U3_M  (PCNT_THR_L_LIM_EN_U3_V << PCNT_THR_L_LIM_EN_U3_S)
+#define PCNT_THR_L_LIM_EN_U3_V  0x00000001U
+#define PCNT_THR_L_LIM_EN_U3_S  13
+/** PCNT_THR_THRES0_EN_U3 : R/W; bitpos: [14]; default: 0;
+ *  This is the enable bit for unit 3's thres0 comparator.
+ */
+#define PCNT_THR_THRES0_EN_U3    (BIT(14))
+#define PCNT_THR_THRES0_EN_U3_M  (PCNT_THR_THRES0_EN_U3_V << PCNT_THR_THRES0_EN_U3_S)
+#define PCNT_THR_THRES0_EN_U3_V  0x00000001U
+#define PCNT_THR_THRES0_EN_U3_S  14
+/** PCNT_THR_THRES1_EN_U3 : R/W; bitpos: [15]; default: 0;
+ *  This is the enable bit for unit 3's thres1 comparator.
+ */
+#define PCNT_THR_THRES1_EN_U3    (BIT(15))
+#define PCNT_THR_THRES1_EN_U3_M  (PCNT_THR_THRES1_EN_U3_V << PCNT_THR_THRES1_EN_U3_S)
+#define PCNT_THR_THRES1_EN_U3_V  0x00000001U
+#define PCNT_THR_THRES1_EN_U3_S  15
+/** PCNT_CH0_NEG_MODE_U3 : R/W; bitpos: [17:16]; default: 0;
+ *  This register sets the behavior when the signal input of channel 0 detects a
+ *  negative edge.
+ *
+ *  1: Increase the counter;2: Decrease the counter;0, 3: No effect on counter
+ */
+#define PCNT_CH0_NEG_MODE_U3    0x00000003U
+#define PCNT_CH0_NEG_MODE_U3_M  (PCNT_CH0_NEG_MODE_U3_V << PCNT_CH0_NEG_MODE_U3_S)
+#define PCNT_CH0_NEG_MODE_U3_V  0x00000003U
+#define PCNT_CH0_NEG_MODE_U3_S  16
+/** PCNT_CH0_POS_MODE_U3 : R/W; bitpos: [19:18]; default: 0;
+ *  This register sets the behavior when the signal input of channel 0 detects a
+ *  positive edge.
+ *
+ *  1: Increase the counter;2: Decrease the counter;0, 3: No effect on counter
+ */
+#define PCNT_CH0_POS_MODE_U3    0x00000003U
+#define PCNT_CH0_POS_MODE_U3_M  (PCNT_CH0_POS_MODE_U3_V << PCNT_CH0_POS_MODE_U3_S)
+#define PCNT_CH0_POS_MODE_U3_V  0x00000003U
+#define PCNT_CH0_POS_MODE_U3_S  18
+/** PCNT_CH0_HCTRL_MODE_U3 : R/W; bitpos: [21:20]; default: 0;
+ *  This register configures how the CH3_POS_MODE/CH3_NEG_MODE settings will be
+ *  modified when the control signal is high.
+ *
+ *  0: No modification;1: Invert behavior (increase -> decrease, decrease ->
+ *  increase);2, 3: Inhibit counter modification
+ */
+#define PCNT_CH0_HCTRL_MODE_U3    0x00000003U
+#define PCNT_CH0_HCTRL_MODE_U3_M  (PCNT_CH0_HCTRL_MODE_U3_V << PCNT_CH0_HCTRL_MODE_U3_S)
+#define PCNT_CH0_HCTRL_MODE_U3_V  0x00000003U
+#define PCNT_CH0_HCTRL_MODE_U3_S  20
+/** PCNT_CH0_LCTRL_MODE_U3 : R/W; bitpos: [23:22]; default: 0;
+ *  This register configures how the CH3_POS_MODE/CH3_NEG_MODE settings will be
+ *  modified when the control signal is low.
+ *
+ *  0: No modification;1: Invert behavior (increase -> decrease, decrease ->
+ *  increase);2, 3: Inhibit counter modification
+ */
+#define PCNT_CH0_LCTRL_MODE_U3    0x00000003U
+#define PCNT_CH0_LCTRL_MODE_U3_M  (PCNT_CH0_LCTRL_MODE_U3_V << PCNT_CH0_LCTRL_MODE_U3_S)
+#define PCNT_CH0_LCTRL_MODE_U3_V  0x00000003U
+#define PCNT_CH0_LCTRL_MODE_U3_S  22
+/** PCNT_CH1_NEG_MODE_U3 : R/W; bitpos: [25:24]; default: 0;
+ *  This register sets the behavior when the signal input of channel 1 detects a
+ *  negative edge.
+ *
+ *  1: Increment the counter;2: Decrement the counter;0, 3: No effect on counter
+ */
+#define PCNT_CH1_NEG_MODE_U3    0x00000003U
+#define PCNT_CH1_NEG_MODE_U3_M  (PCNT_CH1_NEG_MODE_U3_V << PCNT_CH1_NEG_MODE_U3_S)
+#define PCNT_CH1_NEG_MODE_U3_V  0x00000003U
+#define PCNT_CH1_NEG_MODE_U3_S  24
+/** PCNT_CH1_POS_MODE_U3 : R/W; bitpos: [27:26]; default: 0;
+ *  This register sets the behavior when the signal input of channel 1 detects a
+ *  positive edge.
+ *
+ *  1: Increment the counter;2: Decrement the counter;0, 3: No effect on counter
+ */
+#define PCNT_CH1_POS_MODE_U3    0x00000003U
+#define PCNT_CH1_POS_MODE_U3_M  (PCNT_CH1_POS_MODE_U3_V << PCNT_CH1_POS_MODE_U3_S)
+#define PCNT_CH1_POS_MODE_U3_V  0x00000003U
+#define PCNT_CH1_POS_MODE_U3_S  26
+/** PCNT_CH1_HCTRL_MODE_U3 : R/W; bitpos: [29:28]; default: 0;
+ *  This register configures how the CH3_POS_MODE/CH3_NEG_MODE settings will be
+ *  modified when the control signal is high.
+ *
+ *  0: No modification;1: Invert behavior (increase -> decrease, decrease ->
+ *  increase);2, 3: Inhibit counter modification
+ */
+#define PCNT_CH1_HCTRL_MODE_U3    0x00000003U
+#define PCNT_CH1_HCTRL_MODE_U3_M  (PCNT_CH1_HCTRL_MODE_U3_V << PCNT_CH1_HCTRL_MODE_U3_S)
+#define PCNT_CH1_HCTRL_MODE_U3_V  0x00000003U
+#define PCNT_CH1_HCTRL_MODE_U3_S  28
+/** PCNT_CH1_LCTRL_MODE_U3 : R/W; bitpos: [31:30]; default: 0;
+ *  This register configures how the CH3_POS_MODE/CH3_NEG_MODE settings will be
+ *  modified when the control signal is low.
+ *
+ *  0: No modification;1: Invert behavior (increase -> decrease, decrease ->
+ *  increase);2, 3: Inhibit counter modification
+ */
+#define PCNT_CH1_LCTRL_MODE_U3    0x00000003U
+#define PCNT_CH1_LCTRL_MODE_U3_M  (PCNT_CH1_LCTRL_MODE_U3_V << PCNT_CH1_LCTRL_MODE_U3_S)
+#define PCNT_CH1_LCTRL_MODE_U3_V  0x00000003U
+#define PCNT_CH1_LCTRL_MODE_U3_S  30
 
-#define PCNT_U3_CONF1_REG          (DR_REG_PCNT_BASE + 0x0028)
-/* PCNT_CNT_THRES1_U3 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */
-/*description: */
-#define PCNT_CNT_THRES1_U3  0x0000FFFF
-#define PCNT_CNT_THRES1_U3_M  ((PCNT_CNT_THRES1_U3_V)<<(PCNT_CNT_THRES1_U3_S))
-#define PCNT_CNT_THRES1_U3_V  0xFFFF
-#define PCNT_CNT_THRES1_U3_S  16
-/* PCNT_CNT_THRES0_U3 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */
-/*description: */
-#define PCNT_CNT_THRES0_U3  0x0000FFFF
-#define PCNT_CNT_THRES0_U3_M  ((PCNT_CNT_THRES0_U3_V)<<(PCNT_CNT_THRES0_U3_S))
-#define PCNT_CNT_THRES0_U3_V  0xFFFF
+/** PCNT_U3_CONF1_REG register
+ *  Configuration register 1 for unit 3
+ */
+#define PCNT_U3_CONF1_REG (DR_REG_PCNT_BASE + 0x28)
+/** PCNT_CNT_THRES0_U3 : R/W; bitpos: [15:0]; default: 0;
+ *  This register is used to configure the thres0 value for unit 3.
+ */
+#define PCNT_CNT_THRES0_U3    0x0000FFFFU
+#define PCNT_CNT_THRES0_U3_M  (PCNT_CNT_THRES0_U3_V << PCNT_CNT_THRES0_U3_S)
+#define PCNT_CNT_THRES0_U3_V  0x0000FFFFU
 #define PCNT_CNT_THRES0_U3_S  0
+/** PCNT_CNT_THRES1_U3 : R/W; bitpos: [31:16]; default: 0;
+ *  This register is used to configure the thres1 value for unit 3.
+ */
+#define PCNT_CNT_THRES1_U3    0x0000FFFFU
+#define PCNT_CNT_THRES1_U3_M  (PCNT_CNT_THRES1_U3_V << PCNT_CNT_THRES1_U3_S)
+#define PCNT_CNT_THRES1_U3_V  0x0000FFFFU
+#define PCNT_CNT_THRES1_U3_S  16
 
-#define PCNT_U3_CONF2_REG          (DR_REG_PCNT_BASE + 0x002c)
-/* PCNT_CNT_L_LIM_U3 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */
-/*description: */
-#define PCNT_CNT_L_LIM_U3  0x0000FFFF
-#define PCNT_CNT_L_LIM_U3_M  ((PCNT_CNT_L_LIM_U3_V)<<(PCNT_CNT_L_LIM_U3_S))
-#define PCNT_CNT_L_LIM_U3_V  0xFFFF
-#define PCNT_CNT_L_LIM_U3_S  16
-/* PCNT_CNT_H_LIM_U3 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */
-/*description: */
-#define PCNT_CNT_H_LIM_U3  0x0000FFFF
-#define PCNT_CNT_H_LIM_U3_M  ((PCNT_CNT_H_LIM_U3_V)<<(PCNT_CNT_H_LIM_U3_S))
-#define PCNT_CNT_H_LIM_U3_V  0xFFFF
+/** PCNT_U3_CONF2_REG register
+ *  Configuration register 2 for unit 3
+ */
+#define PCNT_U3_CONF2_REG (DR_REG_PCNT_BASE + 0x2c)
+/** PCNT_CNT_H_LIM_U3 : R/W; bitpos: [15:0]; default: 0;
+ *  This register is used to configure the thr_h_lim value for unit 3.
+ */
+#define PCNT_CNT_H_LIM_U3    0x0000FFFFU
+#define PCNT_CNT_H_LIM_U3_M  (PCNT_CNT_H_LIM_U3_V << PCNT_CNT_H_LIM_U3_S)
+#define PCNT_CNT_H_LIM_U3_V  0x0000FFFFU
 #define PCNT_CNT_H_LIM_U3_S  0
+/** PCNT_CNT_L_LIM_U3 : R/W; bitpos: [31:16]; default: 0;
+ *  This register is used to configure the thr_l_lim value for unit 3.
+ */
+#define PCNT_CNT_L_LIM_U3    0x0000FFFFU
+#define PCNT_CNT_L_LIM_U3_M  (PCNT_CNT_L_LIM_U3_V << PCNT_CNT_L_LIM_U3_S)
+#define PCNT_CNT_L_LIM_U3_V  0x0000FFFFU
+#define PCNT_CNT_L_LIM_U3_S  16
 
-#define PCNT_U0_CNT_REG          (DR_REG_PCNT_BASE + 0x0030)
-/* PCNT_PULSE_CNT_U0 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: */
-#define PCNT_PULSE_CNT_U0  0x0000FFFF
-#define PCNT_PULSE_CNT_U0_M  ((PCNT_PULSE_CNT_U0_V)<<(PCNT_PULSE_CNT_U0_S))
-#define PCNT_PULSE_CNT_U0_V  0xFFFF
+/** PCNT_U0_CNT_REG register
+ *  Counter value for unit 0
+ */
+#define PCNT_U0_CNT_REG (DR_REG_PCNT_BASE + 0x30)
+/** PCNT_PULSE_CNT_U0 : RO; bitpos: [15:0]; default: 0;
+ *  This register stores the current pulse count value for unit 0.
+ */
+#define PCNT_PULSE_CNT_U0    0x0000FFFFU
+#define PCNT_PULSE_CNT_U0_M  (PCNT_PULSE_CNT_U0_V << PCNT_PULSE_CNT_U0_S)
+#define PCNT_PULSE_CNT_U0_V  0x0000FFFFU
 #define PCNT_PULSE_CNT_U0_S  0
 
-#define PCNT_U1_CNT_REG          (DR_REG_PCNT_BASE + 0x0034)
-/* PCNT_PULSE_CNT_U1 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: */
-#define PCNT_PULSE_CNT_U1  0x0000FFFF
-#define PCNT_PULSE_CNT_U1_M  ((PCNT_PULSE_CNT_U1_V)<<(PCNT_PULSE_CNT_U1_S))
-#define PCNT_PULSE_CNT_U1_V  0xFFFF
+/** PCNT_U1_CNT_REG register
+ *  Counter value for unit 1
+ */
+#define PCNT_U1_CNT_REG (DR_REG_PCNT_BASE + 0x34)
+/** PCNT_PULSE_CNT_U1 : RO; bitpos: [15:0]; default: 0;
+ *  This register stores the current pulse count value for unit 1.
+ */
+#define PCNT_PULSE_CNT_U1    0x0000FFFFU
+#define PCNT_PULSE_CNT_U1_M  (PCNT_PULSE_CNT_U1_V << PCNT_PULSE_CNT_U1_S)
+#define PCNT_PULSE_CNT_U1_V  0x0000FFFFU
 #define PCNT_PULSE_CNT_U1_S  0
 
-#define PCNT_U2_CNT_REG          (DR_REG_PCNT_BASE + 0x0038)
-/* PCNT_PULSE_CNT_U2 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: */
-#define PCNT_PULSE_CNT_U2  0x0000FFFF
-#define PCNT_PULSE_CNT_U2_M  ((PCNT_PULSE_CNT_U2_V)<<(PCNT_PULSE_CNT_U2_S))
-#define PCNT_PULSE_CNT_U2_V  0xFFFF
+/** PCNT_U2_CNT_REG register
+ *  Counter value for unit 2
+ */
+#define PCNT_U2_CNT_REG (DR_REG_PCNT_BASE + 0x38)
+/** PCNT_PULSE_CNT_U2 : RO; bitpos: [15:0]; default: 0;
+ *  This register stores the current pulse count value for unit 2.
+ */
+#define PCNT_PULSE_CNT_U2    0x0000FFFFU
+#define PCNT_PULSE_CNT_U2_M  (PCNT_PULSE_CNT_U2_V << PCNT_PULSE_CNT_U2_S)
+#define PCNT_PULSE_CNT_U2_V  0x0000FFFFU
 #define PCNT_PULSE_CNT_U2_S  0
 
-#define PCNT_U3_CNT_REG          (DR_REG_PCNT_BASE + 0x003c)
-/* PCNT_PULSE_CNT_U3 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: */
-#define PCNT_PULSE_CNT_U3  0x0000FFFF
-#define PCNT_PULSE_CNT_U3_M  ((PCNT_PULSE_CNT_U3_V)<<(PCNT_PULSE_CNT_U3_S))
-#define PCNT_PULSE_CNT_U3_V  0xFFFF
+/** PCNT_U3_CNT_REG register
+ *  Counter value for unit 3
+ */
+#define PCNT_U3_CNT_REG (DR_REG_PCNT_BASE + 0x3c)
+/** PCNT_PULSE_CNT_U3 : RO; bitpos: [15:0]; default: 0;
+ *  This register stores the current pulse count value for unit 3.
+ */
+#define PCNT_PULSE_CNT_U3    0x0000FFFFU
+#define PCNT_PULSE_CNT_U3_M  (PCNT_PULSE_CNT_U3_V << PCNT_PULSE_CNT_U3_S)
+#define PCNT_PULSE_CNT_U3_V  0x0000FFFFU
 #define PCNT_PULSE_CNT_U3_S  0
 
-#define PCNT_INT_RAW_REG          (DR_REG_PCNT_BASE + 0x0040)
-/* PCNT_CNT_THR_EVENT_U3_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define PCNT_CNT_THR_EVENT_U3_INT_RAW  (BIT(3))
-#define PCNT_CNT_THR_EVENT_U3_INT_RAW_M  (BIT(3))
-#define PCNT_CNT_THR_EVENT_U3_INT_RAW_V  0x1
-#define PCNT_CNT_THR_EVENT_U3_INT_RAW_S  3
-/* PCNT_CNT_THR_EVENT_U2_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define PCNT_CNT_THR_EVENT_U2_INT_RAW  (BIT(2))
-#define PCNT_CNT_THR_EVENT_U2_INT_RAW_M  (BIT(2))
-#define PCNT_CNT_THR_EVENT_U2_INT_RAW_V  0x1
-#define PCNT_CNT_THR_EVENT_U2_INT_RAW_S  2
-/* PCNT_CNT_THR_EVENT_U1_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define PCNT_CNT_THR_EVENT_U1_INT_RAW  (BIT(1))
-#define PCNT_CNT_THR_EVENT_U1_INT_RAW_M  (BIT(1))
-#define PCNT_CNT_THR_EVENT_U1_INT_RAW_V  0x1
-#define PCNT_CNT_THR_EVENT_U1_INT_RAW_S  1
-/* PCNT_CNT_THR_EVENT_U0_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define PCNT_CNT_THR_EVENT_U0_INT_RAW  (BIT(0))
-#define PCNT_CNT_THR_EVENT_U0_INT_RAW_M  (BIT(0))
-#define PCNT_CNT_THR_EVENT_U0_INT_RAW_V  0x1
+/** PCNT_INT_RAW_REG register
+ *  Interrupt raw status register
+ */
+#define PCNT_INT_RAW_REG (DR_REG_PCNT_BASE + 0x40)
+/** PCNT_CNT_THR_EVENT_U0_INT_RAW : RO; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt.
+ */
+#define PCNT_CNT_THR_EVENT_U0_INT_RAW    (BIT(0))
+#define PCNT_CNT_THR_EVENT_U0_INT_RAW_M  (PCNT_CNT_THR_EVENT_U0_INT_RAW_V << PCNT_CNT_THR_EVENT_U0_INT_RAW_S)
+#define PCNT_CNT_THR_EVENT_U0_INT_RAW_V  0x00000001U
 #define PCNT_CNT_THR_EVENT_U0_INT_RAW_S  0
+/** PCNT_CNT_THR_EVENT_U1_INT_RAW : RO; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt.
+ */
+#define PCNT_CNT_THR_EVENT_U1_INT_RAW    (BIT(1))
+#define PCNT_CNT_THR_EVENT_U1_INT_RAW_M  (PCNT_CNT_THR_EVENT_U1_INT_RAW_V << PCNT_CNT_THR_EVENT_U1_INT_RAW_S)
+#define PCNT_CNT_THR_EVENT_U1_INT_RAW_V  0x00000001U
+#define PCNT_CNT_THR_EVENT_U1_INT_RAW_S  1
+/** PCNT_CNT_THR_EVENT_U2_INT_RAW : RO; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt.
+ */
+#define PCNT_CNT_THR_EVENT_U2_INT_RAW    (BIT(2))
+#define PCNT_CNT_THR_EVENT_U2_INT_RAW_M  (PCNT_CNT_THR_EVENT_U2_INT_RAW_V << PCNT_CNT_THR_EVENT_U2_INT_RAW_S)
+#define PCNT_CNT_THR_EVENT_U2_INT_RAW_V  0x00000001U
+#define PCNT_CNT_THR_EVENT_U2_INT_RAW_S  2
+/** PCNT_CNT_THR_EVENT_U3_INT_RAW : RO; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt.
+ */
+#define PCNT_CNT_THR_EVENT_U3_INT_RAW    (BIT(3))
+#define PCNT_CNT_THR_EVENT_U3_INT_RAW_M  (PCNT_CNT_THR_EVENT_U3_INT_RAW_V << PCNT_CNT_THR_EVENT_U3_INT_RAW_S)
+#define PCNT_CNT_THR_EVENT_U3_INT_RAW_V  0x00000001U
+#define PCNT_CNT_THR_EVENT_U3_INT_RAW_S  3
 
-#define PCNT_INT_ST_REG          (DR_REG_PCNT_BASE + 0x0044)
-/* PCNT_CNT_THR_EVENT_U3_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define PCNT_CNT_THR_EVENT_U3_INT_ST  (BIT(3))
-#define PCNT_CNT_THR_EVENT_U3_INT_ST_M  (BIT(3))
-#define PCNT_CNT_THR_EVENT_U3_INT_ST_V  0x1
-#define PCNT_CNT_THR_EVENT_U3_INT_ST_S  3
-/* PCNT_CNT_THR_EVENT_U2_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define PCNT_CNT_THR_EVENT_U2_INT_ST  (BIT(2))
-#define PCNT_CNT_THR_EVENT_U2_INT_ST_M  (BIT(2))
-#define PCNT_CNT_THR_EVENT_U2_INT_ST_V  0x1
-#define PCNT_CNT_THR_EVENT_U2_INT_ST_S  2
-/* PCNT_CNT_THR_EVENT_U1_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define PCNT_CNT_THR_EVENT_U1_INT_ST  (BIT(1))
-#define PCNT_CNT_THR_EVENT_U1_INT_ST_M  (BIT(1))
-#define PCNT_CNT_THR_EVENT_U1_INT_ST_V  0x1
-#define PCNT_CNT_THR_EVENT_U1_INT_ST_S  1
-/* PCNT_CNT_THR_EVENT_U0_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define PCNT_CNT_THR_EVENT_U0_INT_ST  (BIT(0))
-#define PCNT_CNT_THR_EVENT_U0_INT_ST_M  (BIT(0))
-#define PCNT_CNT_THR_EVENT_U0_INT_ST_V  0x1
+/** PCNT_INT_ST_REG register
+ *  Interrupt status register
+ */
+#define PCNT_INT_ST_REG (DR_REG_PCNT_BASE + 0x44)
+/** PCNT_CNT_THR_EVENT_U0_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt.
+ */
+#define PCNT_CNT_THR_EVENT_U0_INT_ST    (BIT(0))
+#define PCNT_CNT_THR_EVENT_U0_INT_ST_M  (PCNT_CNT_THR_EVENT_U0_INT_ST_V << PCNT_CNT_THR_EVENT_U0_INT_ST_S)
+#define PCNT_CNT_THR_EVENT_U0_INT_ST_V  0x00000001U
 #define PCNT_CNT_THR_EVENT_U0_INT_ST_S  0
+/** PCNT_CNT_THR_EVENT_U1_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt.
+ */
+#define PCNT_CNT_THR_EVENT_U1_INT_ST    (BIT(1))
+#define PCNT_CNT_THR_EVENT_U1_INT_ST_M  (PCNT_CNT_THR_EVENT_U1_INT_ST_V << PCNT_CNT_THR_EVENT_U1_INT_ST_S)
+#define PCNT_CNT_THR_EVENT_U1_INT_ST_V  0x00000001U
+#define PCNT_CNT_THR_EVENT_U1_INT_ST_S  1
+/** PCNT_CNT_THR_EVENT_U2_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt.
+ */
+#define PCNT_CNT_THR_EVENT_U2_INT_ST    (BIT(2))
+#define PCNT_CNT_THR_EVENT_U2_INT_ST_M  (PCNT_CNT_THR_EVENT_U2_INT_ST_V << PCNT_CNT_THR_EVENT_U2_INT_ST_S)
+#define PCNT_CNT_THR_EVENT_U2_INT_ST_V  0x00000001U
+#define PCNT_CNT_THR_EVENT_U2_INT_ST_S  2
+/** PCNT_CNT_THR_EVENT_U3_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt.
+ */
+#define PCNT_CNT_THR_EVENT_U3_INT_ST    (BIT(3))
+#define PCNT_CNT_THR_EVENT_U3_INT_ST_M  (PCNT_CNT_THR_EVENT_U3_INT_ST_V << PCNT_CNT_THR_EVENT_U3_INT_ST_S)
+#define PCNT_CNT_THR_EVENT_U3_INT_ST_V  0x00000001U
+#define PCNT_CNT_THR_EVENT_U3_INT_ST_S  3
 
-#define PCNT_INT_ENA_REG          (DR_REG_PCNT_BASE + 0x0048)
-/* PCNT_CNT_THR_EVENT_U3_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define PCNT_CNT_THR_EVENT_U3_INT_ENA  (BIT(3))
-#define PCNT_CNT_THR_EVENT_U3_INT_ENA_M  (BIT(3))
-#define PCNT_CNT_THR_EVENT_U3_INT_ENA_V  0x1
-#define PCNT_CNT_THR_EVENT_U3_INT_ENA_S  3
-/* PCNT_CNT_THR_EVENT_U2_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define PCNT_CNT_THR_EVENT_U2_INT_ENA  (BIT(2))
-#define PCNT_CNT_THR_EVENT_U2_INT_ENA_M  (BIT(2))
-#define PCNT_CNT_THR_EVENT_U2_INT_ENA_V  0x1
-#define PCNT_CNT_THR_EVENT_U2_INT_ENA_S  2
-/* PCNT_CNT_THR_EVENT_U1_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define PCNT_CNT_THR_EVENT_U1_INT_ENA  (BIT(1))
-#define PCNT_CNT_THR_EVENT_U1_INT_ENA_M  (BIT(1))
-#define PCNT_CNT_THR_EVENT_U1_INT_ENA_V  0x1
-#define PCNT_CNT_THR_EVENT_U1_INT_ENA_S  1
-/* PCNT_CNT_THR_EVENT_U0_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define PCNT_CNT_THR_EVENT_U0_INT_ENA  (BIT(0))
-#define PCNT_CNT_THR_EVENT_U0_INT_ENA_M  (BIT(0))
-#define PCNT_CNT_THR_EVENT_U0_INT_ENA_V  0x1
+/** PCNT_INT_ENA_REG register
+ *  Interrupt enable register
+ */
+#define PCNT_INT_ENA_REG (DR_REG_PCNT_BASE + 0x48)
+/** PCNT_CNT_THR_EVENT_U0_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt.
+ */
+#define PCNT_CNT_THR_EVENT_U0_INT_ENA    (BIT(0))
+#define PCNT_CNT_THR_EVENT_U0_INT_ENA_M  (PCNT_CNT_THR_EVENT_U0_INT_ENA_V << PCNT_CNT_THR_EVENT_U0_INT_ENA_S)
+#define PCNT_CNT_THR_EVENT_U0_INT_ENA_V  0x00000001U
 #define PCNT_CNT_THR_EVENT_U0_INT_ENA_S  0
+/** PCNT_CNT_THR_EVENT_U1_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt.
+ */
+#define PCNT_CNT_THR_EVENT_U1_INT_ENA    (BIT(1))
+#define PCNT_CNT_THR_EVENT_U1_INT_ENA_M  (PCNT_CNT_THR_EVENT_U1_INT_ENA_V << PCNT_CNT_THR_EVENT_U1_INT_ENA_S)
+#define PCNT_CNT_THR_EVENT_U1_INT_ENA_V  0x00000001U
+#define PCNT_CNT_THR_EVENT_U1_INT_ENA_S  1
+/** PCNT_CNT_THR_EVENT_U2_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt.
+ */
+#define PCNT_CNT_THR_EVENT_U2_INT_ENA    (BIT(2))
+#define PCNT_CNT_THR_EVENT_U2_INT_ENA_M  (PCNT_CNT_THR_EVENT_U2_INT_ENA_V << PCNT_CNT_THR_EVENT_U2_INT_ENA_S)
+#define PCNT_CNT_THR_EVENT_U2_INT_ENA_V  0x00000001U
+#define PCNT_CNT_THR_EVENT_U2_INT_ENA_S  2
+/** PCNT_CNT_THR_EVENT_U3_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt.
+ */
+#define PCNT_CNT_THR_EVENT_U3_INT_ENA    (BIT(3))
+#define PCNT_CNT_THR_EVENT_U3_INT_ENA_M  (PCNT_CNT_THR_EVENT_U3_INT_ENA_V << PCNT_CNT_THR_EVENT_U3_INT_ENA_S)
+#define PCNT_CNT_THR_EVENT_U3_INT_ENA_V  0x00000001U
+#define PCNT_CNT_THR_EVENT_U3_INT_ENA_S  3
 
-#define PCNT_INT_CLR_REG          (DR_REG_PCNT_BASE + 0x004c)
-/* PCNT_CNT_THR_EVENT_U3_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define PCNT_CNT_THR_EVENT_U3_INT_CLR  (BIT(3))
-#define PCNT_CNT_THR_EVENT_U3_INT_CLR_M  (BIT(3))
-#define PCNT_CNT_THR_EVENT_U3_INT_CLR_V  0x1
-#define PCNT_CNT_THR_EVENT_U3_INT_CLR_S  3
-/* PCNT_CNT_THR_EVENT_U2_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define PCNT_CNT_THR_EVENT_U2_INT_CLR  (BIT(2))
-#define PCNT_CNT_THR_EVENT_U2_INT_CLR_M  (BIT(2))
-#define PCNT_CNT_THR_EVENT_U2_INT_CLR_V  0x1
-#define PCNT_CNT_THR_EVENT_U2_INT_CLR_S  2
-/* PCNT_CNT_THR_EVENT_U1_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define PCNT_CNT_THR_EVENT_U1_INT_CLR  (BIT(1))
-#define PCNT_CNT_THR_EVENT_U1_INT_CLR_M  (BIT(1))
-#define PCNT_CNT_THR_EVENT_U1_INT_CLR_V  0x1
-#define PCNT_CNT_THR_EVENT_U1_INT_CLR_S  1
-/* PCNT_CNT_THR_EVENT_U0_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define PCNT_CNT_THR_EVENT_U0_INT_CLR  (BIT(0))
-#define PCNT_CNT_THR_EVENT_U0_INT_CLR_M  (BIT(0))
-#define PCNT_CNT_THR_EVENT_U0_INT_CLR_V  0x1
+/** PCNT_INT_CLR_REG register
+ *  Interrupt clear register
+ */
+#define PCNT_INT_CLR_REG (DR_REG_PCNT_BASE + 0x4c)
+/** PCNT_CNT_THR_EVENT_U0_INT_CLR : WO; bitpos: [0]; default: 0;
+ *  Set this bit to clear the PCNT_CNT_THR_EVENT_U0_INT interrupt.
+ */
+#define PCNT_CNT_THR_EVENT_U0_INT_CLR    (BIT(0))
+#define PCNT_CNT_THR_EVENT_U0_INT_CLR_M  (PCNT_CNT_THR_EVENT_U0_INT_CLR_V << PCNT_CNT_THR_EVENT_U0_INT_CLR_S)
+#define PCNT_CNT_THR_EVENT_U0_INT_CLR_V  0x00000001U
 #define PCNT_CNT_THR_EVENT_U0_INT_CLR_S  0
+/** PCNT_CNT_THR_EVENT_U1_INT_CLR : WO; bitpos: [1]; default: 0;
+ *  Set this bit to clear the PCNT_CNT_THR_EVENT_U1_INT interrupt.
+ */
+#define PCNT_CNT_THR_EVENT_U1_INT_CLR    (BIT(1))
+#define PCNT_CNT_THR_EVENT_U1_INT_CLR_M  (PCNT_CNT_THR_EVENT_U1_INT_CLR_V << PCNT_CNT_THR_EVENT_U1_INT_CLR_S)
+#define PCNT_CNT_THR_EVENT_U1_INT_CLR_V  0x00000001U
+#define PCNT_CNT_THR_EVENT_U1_INT_CLR_S  1
+/** PCNT_CNT_THR_EVENT_U2_INT_CLR : WO; bitpos: [2]; default: 0;
+ *  Set this bit to clear the PCNT_CNT_THR_EVENT_U2_INT interrupt.
+ */
+#define PCNT_CNT_THR_EVENT_U2_INT_CLR    (BIT(2))
+#define PCNT_CNT_THR_EVENT_U2_INT_CLR_M  (PCNT_CNT_THR_EVENT_U2_INT_CLR_V << PCNT_CNT_THR_EVENT_U2_INT_CLR_S)
+#define PCNT_CNT_THR_EVENT_U2_INT_CLR_V  0x00000001U
+#define PCNT_CNT_THR_EVENT_U2_INT_CLR_S  2
+/** PCNT_CNT_THR_EVENT_U3_INT_CLR : WO; bitpos: [3]; default: 0;
+ *  Set this bit to clear the PCNT_CNT_THR_EVENT_U3_INT interrupt.
+ */
+#define PCNT_CNT_THR_EVENT_U3_INT_CLR    (BIT(3))
+#define PCNT_CNT_THR_EVENT_U3_INT_CLR_M  (PCNT_CNT_THR_EVENT_U3_INT_CLR_V << PCNT_CNT_THR_EVENT_U3_INT_CLR_S)
+#define PCNT_CNT_THR_EVENT_U3_INT_CLR_V  0x00000001U
+#define PCNT_CNT_THR_EVENT_U3_INT_CLR_S  3
 
-#define PCNT_U0_STATUS_REG          (DR_REG_PCNT_BASE + 0x0050)
-/* PCNT_CNT_THR_ZERO_LAT_U0 : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define PCNT_CNT_THR_ZERO_LAT_U0  (BIT(6))
-#define PCNT_CNT_THR_ZERO_LAT_U0_M  (BIT(6))
-#define PCNT_CNT_THR_ZERO_LAT_U0_V  0x1
-#define PCNT_CNT_THR_ZERO_LAT_U0_S  6
-/* PCNT_CNT_THR_H_LIM_LAT_U0 : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define PCNT_CNT_THR_H_LIM_LAT_U0  (BIT(5))
-#define PCNT_CNT_THR_H_LIM_LAT_U0_M  (BIT(5))
-#define PCNT_CNT_THR_H_LIM_LAT_U0_V  0x1
-#define PCNT_CNT_THR_H_LIM_LAT_U0_S  5
-/* PCNT_CNT_THR_L_LIM_LAT_U0 : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define PCNT_CNT_THR_L_LIM_LAT_U0  (BIT(4))
-#define PCNT_CNT_THR_L_LIM_LAT_U0_M  (BIT(4))
-#define PCNT_CNT_THR_L_LIM_LAT_U0_V  0x1
-#define PCNT_CNT_THR_L_LIM_LAT_U0_S  4
-/* PCNT_CNT_THR_THRES0_LAT_U0 : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define PCNT_CNT_THR_THRES0_LAT_U0  (BIT(3))
-#define PCNT_CNT_THR_THRES0_LAT_U0_M  (BIT(3))
-#define PCNT_CNT_THR_THRES0_LAT_U0_V  0x1
-#define PCNT_CNT_THR_THRES0_LAT_U0_S  3
-/* PCNT_CNT_THR_THRES1_LAT_U0 : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define PCNT_CNT_THR_THRES1_LAT_U0  (BIT(2))
-#define PCNT_CNT_THR_THRES1_LAT_U0_M  (BIT(2))
-#define PCNT_CNT_THR_THRES1_LAT_U0_V  0x1
-#define PCNT_CNT_THR_THRES1_LAT_U0_S  2
-/* PCNT_CNT_THR_ZERO_MODE_U0 : RO ;bitpos:[1:0] ;default: 2'b0 ; */
-/*description: */
-#define PCNT_CNT_THR_ZERO_MODE_U0  0x00000003
-#define PCNT_CNT_THR_ZERO_MODE_U0_M  ((PCNT_CNT_THR_ZERO_MODE_U0_V)<<(PCNT_CNT_THR_ZERO_MODE_U0_S))
-#define PCNT_CNT_THR_ZERO_MODE_U0_V  0x3
+/** PCNT_U0_STATUS_REG register
+ *  PNCT UNIT0 status register
+ */
+#define PCNT_U0_STATUS_REG (DR_REG_PCNT_BASE + 0x50)
+/** PCNT_CNT_THR_ZERO_MODE_U0 : RO; bitpos: [1:0]; default: 0;
+ *  The pulse counter status of PCNT_U0 corresponding to 0. 0: pulse counter decreases
+ *  from positive to 0. 1: pulse counter increases from negative to 0. 2: pulse counter
+ *  is negative. 3: pulse counter is positive.
+ */
+#define PCNT_CNT_THR_ZERO_MODE_U0    0x00000003U
+#define PCNT_CNT_THR_ZERO_MODE_U0_M  (PCNT_CNT_THR_ZERO_MODE_U0_V << PCNT_CNT_THR_ZERO_MODE_U0_S)
+#define PCNT_CNT_THR_ZERO_MODE_U0_V  0x00000003U
 #define PCNT_CNT_THR_ZERO_MODE_U0_S  0
+/** PCNT_CNT_THR_THRES1_LAT_U0 : RO; bitpos: [2]; default: 0;
+ *  The latched value of thres1 event of PCNT_U0 when threshold event interrupt is
+ *  valid. 1: the current pulse counter equals to thres1 and thres1 event is valid. 0:
+ *  others
+ */
+#define PCNT_CNT_THR_THRES1_LAT_U0    (BIT(2))
+#define PCNT_CNT_THR_THRES1_LAT_U0_M  (PCNT_CNT_THR_THRES1_LAT_U0_V << PCNT_CNT_THR_THRES1_LAT_U0_S)
+#define PCNT_CNT_THR_THRES1_LAT_U0_V  0x00000001U
+#define PCNT_CNT_THR_THRES1_LAT_U0_S  2
+/** PCNT_CNT_THR_THRES0_LAT_U0 : RO; bitpos: [3]; default: 0;
+ *  The latched value of thres0 event of PCNT_U0 when threshold event interrupt is
+ *  valid. 1: the current pulse counter equals to thres0 and thres0 event is valid. 0:
+ *  others
+ */
+#define PCNT_CNT_THR_THRES0_LAT_U0    (BIT(3))
+#define PCNT_CNT_THR_THRES0_LAT_U0_M  (PCNT_CNT_THR_THRES0_LAT_U0_V << PCNT_CNT_THR_THRES0_LAT_U0_S)
+#define PCNT_CNT_THR_THRES0_LAT_U0_V  0x00000001U
+#define PCNT_CNT_THR_THRES0_LAT_U0_S  3
+/** PCNT_CNT_THR_L_LIM_LAT_U0 : RO; bitpos: [4]; default: 0;
+ *  The latched value of low limit event of PCNT_U0 when threshold event interrupt is
+ *  valid. 1: the current pulse counter equals to thr_l_lim and low limit event is
+ *  valid. 0: others
+ */
+#define PCNT_CNT_THR_L_LIM_LAT_U0    (BIT(4))
+#define PCNT_CNT_THR_L_LIM_LAT_U0_M  (PCNT_CNT_THR_L_LIM_LAT_U0_V << PCNT_CNT_THR_L_LIM_LAT_U0_S)
+#define PCNT_CNT_THR_L_LIM_LAT_U0_V  0x00000001U
+#define PCNT_CNT_THR_L_LIM_LAT_U0_S  4
+/** PCNT_CNT_THR_H_LIM_LAT_U0 : RO; bitpos: [5]; default: 0;
+ *  The latched value of high limit event of PCNT_U0 when threshold event interrupt is
+ *  valid. 1: the current pulse counter equals to thr_h_lim and high limit event is
+ *  valid. 0: others
+ */
+#define PCNT_CNT_THR_H_LIM_LAT_U0    (BIT(5))
+#define PCNT_CNT_THR_H_LIM_LAT_U0_M  (PCNT_CNT_THR_H_LIM_LAT_U0_V << PCNT_CNT_THR_H_LIM_LAT_U0_S)
+#define PCNT_CNT_THR_H_LIM_LAT_U0_V  0x00000001U
+#define PCNT_CNT_THR_H_LIM_LAT_U0_S  5
+/** PCNT_CNT_THR_ZERO_LAT_U0 : RO; bitpos: [6]; default: 0;
+ *  The latched value of zero threshold event of PCNT_U0 when threshold event interrupt
+ *  is valid. 1: the current pulse counter equals to 0 and zero threshold event is
+ *  valid. 0: others
+ */
+#define PCNT_CNT_THR_ZERO_LAT_U0    (BIT(6))
+#define PCNT_CNT_THR_ZERO_LAT_U0_M  (PCNT_CNT_THR_ZERO_LAT_U0_V << PCNT_CNT_THR_ZERO_LAT_U0_S)
+#define PCNT_CNT_THR_ZERO_LAT_U0_V  0x00000001U
+#define PCNT_CNT_THR_ZERO_LAT_U0_S  6
 
-#define PCNT_U1_STATUS_REG          (DR_REG_PCNT_BASE + 0x0054)
-/* PCNT_CNT_THR_ZERO_LAT_U1 : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define PCNT_CNT_THR_ZERO_LAT_U1  (BIT(6))
-#define PCNT_CNT_THR_ZERO_LAT_U1_M  (BIT(6))
-#define PCNT_CNT_THR_ZERO_LAT_U1_V  0x1
-#define PCNT_CNT_THR_ZERO_LAT_U1_S  6
-/* PCNT_CNT_THR_H_LIM_LAT_U1 : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define PCNT_CNT_THR_H_LIM_LAT_U1  (BIT(5))
-#define PCNT_CNT_THR_H_LIM_LAT_U1_M  (BIT(5))
-#define PCNT_CNT_THR_H_LIM_LAT_U1_V  0x1
-#define PCNT_CNT_THR_H_LIM_LAT_U1_S  5
-/* PCNT_CNT_THR_L_LIM_LAT_U1 : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define PCNT_CNT_THR_L_LIM_LAT_U1  (BIT(4))
-#define PCNT_CNT_THR_L_LIM_LAT_U1_M  (BIT(4))
-#define PCNT_CNT_THR_L_LIM_LAT_U1_V  0x1
-#define PCNT_CNT_THR_L_LIM_LAT_U1_S  4
-/* PCNT_CNT_THR_THRES0_LAT_U1 : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define PCNT_CNT_THR_THRES0_LAT_U1  (BIT(3))
-#define PCNT_CNT_THR_THRES0_LAT_U1_M  (BIT(3))
-#define PCNT_CNT_THR_THRES0_LAT_U1_V  0x1
-#define PCNT_CNT_THR_THRES0_LAT_U1_S  3
-/* PCNT_CNT_THR_THRES1_LAT_U1 : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define PCNT_CNT_THR_THRES1_LAT_U1  (BIT(2))
-#define PCNT_CNT_THR_THRES1_LAT_U1_M  (BIT(2))
-#define PCNT_CNT_THR_THRES1_LAT_U1_V  0x1
-#define PCNT_CNT_THR_THRES1_LAT_U1_S  2
-/* PCNT_CNT_THR_ZERO_MODE_U1 : RO ;bitpos:[1:0] ;default: 2'b0 ; */
-/*description: */
-#define PCNT_CNT_THR_ZERO_MODE_U1  0x00000003
-#define PCNT_CNT_THR_ZERO_MODE_U1_M  ((PCNT_CNT_THR_ZERO_MODE_U1_V)<<(PCNT_CNT_THR_ZERO_MODE_U1_S))
-#define PCNT_CNT_THR_ZERO_MODE_U1_V  0x3
+/** PCNT_U1_STATUS_REG register
+ *  PNCT UNIT1 status register
+ */
+#define PCNT_U1_STATUS_REG (DR_REG_PCNT_BASE + 0x54)
+/** PCNT_CNT_THR_ZERO_MODE_U1 : RO; bitpos: [1:0]; default: 0;
+ *  The pulse counter status of PCNT_U1 corresponding to 0. 0: pulse counter decreases
+ *  from positive to 0. 1: pulse counter increases from negative to 0. 2: pulse counter
+ *  is negative. 3: pulse counter is positive.
+ */
+#define PCNT_CNT_THR_ZERO_MODE_U1    0x00000003U
+#define PCNT_CNT_THR_ZERO_MODE_U1_M  (PCNT_CNT_THR_ZERO_MODE_U1_V << PCNT_CNT_THR_ZERO_MODE_U1_S)
+#define PCNT_CNT_THR_ZERO_MODE_U1_V  0x00000003U
 #define PCNT_CNT_THR_ZERO_MODE_U1_S  0
+/** PCNT_CNT_THR_THRES1_LAT_U1 : RO; bitpos: [2]; default: 0;
+ *  The latched value of thres1 event of PCNT_U1 when threshold event interrupt is
+ *  valid. 1: the current pulse counter equals to thres1 and thres1 event is valid. 0:
+ *  others
+ */
+#define PCNT_CNT_THR_THRES1_LAT_U1    (BIT(2))
+#define PCNT_CNT_THR_THRES1_LAT_U1_M  (PCNT_CNT_THR_THRES1_LAT_U1_V << PCNT_CNT_THR_THRES1_LAT_U1_S)
+#define PCNT_CNT_THR_THRES1_LAT_U1_V  0x00000001U
+#define PCNT_CNT_THR_THRES1_LAT_U1_S  2
+/** PCNT_CNT_THR_THRES0_LAT_U1 : RO; bitpos: [3]; default: 0;
+ *  The latched value of thres0 event of PCNT_U1 when threshold event interrupt is
+ *  valid. 1: the current pulse counter equals to thres0 and thres0 event is valid. 0:
+ *  others
+ */
+#define PCNT_CNT_THR_THRES0_LAT_U1    (BIT(3))
+#define PCNT_CNT_THR_THRES0_LAT_U1_M  (PCNT_CNT_THR_THRES0_LAT_U1_V << PCNT_CNT_THR_THRES0_LAT_U1_S)
+#define PCNT_CNT_THR_THRES0_LAT_U1_V  0x00000001U
+#define PCNT_CNT_THR_THRES0_LAT_U1_S  3
+/** PCNT_CNT_THR_L_LIM_LAT_U1 : RO; bitpos: [4]; default: 0;
+ *  The latched value of low limit event of PCNT_U1 when threshold event interrupt is
+ *  valid. 1: the current pulse counter equals to thr_l_lim and low limit event is
+ *  valid. 0: others
+ */
+#define PCNT_CNT_THR_L_LIM_LAT_U1    (BIT(4))
+#define PCNT_CNT_THR_L_LIM_LAT_U1_M  (PCNT_CNT_THR_L_LIM_LAT_U1_V << PCNT_CNT_THR_L_LIM_LAT_U1_S)
+#define PCNT_CNT_THR_L_LIM_LAT_U1_V  0x00000001U
+#define PCNT_CNT_THR_L_LIM_LAT_U1_S  4
+/** PCNT_CNT_THR_H_LIM_LAT_U1 : RO; bitpos: [5]; default: 0;
+ *  The latched value of high limit event of PCNT_U1 when threshold event interrupt is
+ *  valid. 1: the current pulse counter equals to thr_h_lim and high limit event is
+ *  valid. 0: others
+ */
+#define PCNT_CNT_THR_H_LIM_LAT_U1    (BIT(5))
+#define PCNT_CNT_THR_H_LIM_LAT_U1_M  (PCNT_CNT_THR_H_LIM_LAT_U1_V << PCNT_CNT_THR_H_LIM_LAT_U1_S)
+#define PCNT_CNT_THR_H_LIM_LAT_U1_V  0x00000001U
+#define PCNT_CNT_THR_H_LIM_LAT_U1_S  5
+/** PCNT_CNT_THR_ZERO_LAT_U1 : RO; bitpos: [6]; default: 0;
+ *  The latched value of zero threshold event of PCNT_U1 when threshold event interrupt
+ *  is valid. 1: the current pulse counter equals to 0 and zero threshold event is
+ *  valid. 0: others
+ */
+#define PCNT_CNT_THR_ZERO_LAT_U1    (BIT(6))
+#define PCNT_CNT_THR_ZERO_LAT_U1_M  (PCNT_CNT_THR_ZERO_LAT_U1_V << PCNT_CNT_THR_ZERO_LAT_U1_S)
+#define PCNT_CNT_THR_ZERO_LAT_U1_V  0x00000001U
+#define PCNT_CNT_THR_ZERO_LAT_U1_S  6
 
-#define PCNT_U2_STATUS_REG          (DR_REG_PCNT_BASE + 0x0058)
-/* PCNT_CNT_THR_ZERO_LAT_U2 : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define PCNT_CNT_THR_ZERO_LAT_U2  (BIT(6))
-#define PCNT_CNT_THR_ZERO_LAT_U2_M  (BIT(6))
-#define PCNT_CNT_THR_ZERO_LAT_U2_V  0x1
-#define PCNT_CNT_THR_ZERO_LAT_U2_S  6
-/* PCNT_CNT_THR_H_LIM_LAT_U2 : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define PCNT_CNT_THR_H_LIM_LAT_U2  (BIT(5))
-#define PCNT_CNT_THR_H_LIM_LAT_U2_M  (BIT(5))
-#define PCNT_CNT_THR_H_LIM_LAT_U2_V  0x1
-#define PCNT_CNT_THR_H_LIM_LAT_U2_S  5
-/* PCNT_CNT_THR_L_LIM_LAT_U2 : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define PCNT_CNT_THR_L_LIM_LAT_U2  (BIT(4))
-#define PCNT_CNT_THR_L_LIM_LAT_U2_M  (BIT(4))
-#define PCNT_CNT_THR_L_LIM_LAT_U2_V  0x1
-#define PCNT_CNT_THR_L_LIM_LAT_U2_S  4
-/* PCNT_CNT_THR_THRES0_LAT_U2 : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define PCNT_CNT_THR_THRES0_LAT_U2  (BIT(3))
-#define PCNT_CNT_THR_THRES0_LAT_U2_M  (BIT(3))
-#define PCNT_CNT_THR_THRES0_LAT_U2_V  0x1
-#define PCNT_CNT_THR_THRES0_LAT_U2_S  3
-/* PCNT_CNT_THR_THRES1_LAT_U2 : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define PCNT_CNT_THR_THRES1_LAT_U2  (BIT(2))
-#define PCNT_CNT_THR_THRES1_LAT_U2_M  (BIT(2))
-#define PCNT_CNT_THR_THRES1_LAT_U2_V  0x1
-#define PCNT_CNT_THR_THRES1_LAT_U2_S  2
-/* PCNT_CNT_THR_ZERO_MODE_U2 : RO ;bitpos:[1:0] ;default: 2'b0 ; */
-/*description: */
-#define PCNT_CNT_THR_ZERO_MODE_U2  0x00000003
-#define PCNT_CNT_THR_ZERO_MODE_U2_M  ((PCNT_CNT_THR_ZERO_MODE_U2_V)<<(PCNT_CNT_THR_ZERO_MODE_U2_S))
-#define PCNT_CNT_THR_ZERO_MODE_U2_V  0x3
+/** PCNT_U2_STATUS_REG register
+ *  PNCT UNIT2 status register
+ */
+#define PCNT_U2_STATUS_REG (DR_REG_PCNT_BASE + 0x58)
+/** PCNT_CNT_THR_ZERO_MODE_U2 : RO; bitpos: [1:0]; default: 0;
+ *  The pulse counter status of PCNT_U2 corresponding to 0. 0: pulse counter decreases
+ *  from positive to 0. 1: pulse counter increases from negative to 0. 2: pulse counter
+ *  is negative. 3: pulse counter is positive.
+ */
+#define PCNT_CNT_THR_ZERO_MODE_U2    0x00000003U
+#define PCNT_CNT_THR_ZERO_MODE_U2_M  (PCNT_CNT_THR_ZERO_MODE_U2_V << PCNT_CNT_THR_ZERO_MODE_U2_S)
+#define PCNT_CNT_THR_ZERO_MODE_U2_V  0x00000003U
 #define PCNT_CNT_THR_ZERO_MODE_U2_S  0
+/** PCNT_CNT_THR_THRES1_LAT_U2 : RO; bitpos: [2]; default: 0;
+ *  The latched value of thres1 event of PCNT_U2 when threshold event interrupt is
+ *  valid. 1: the current pulse counter equals to thres1 and thres1 event is valid. 0:
+ *  others
+ */
+#define PCNT_CNT_THR_THRES1_LAT_U2    (BIT(2))
+#define PCNT_CNT_THR_THRES1_LAT_U2_M  (PCNT_CNT_THR_THRES1_LAT_U2_V << PCNT_CNT_THR_THRES1_LAT_U2_S)
+#define PCNT_CNT_THR_THRES1_LAT_U2_V  0x00000001U
+#define PCNT_CNT_THR_THRES1_LAT_U2_S  2
+/** PCNT_CNT_THR_THRES0_LAT_U2 : RO; bitpos: [3]; default: 0;
+ *  The latched value of thres0 event of PCNT_U2 when threshold event interrupt is
+ *  valid. 1: the current pulse counter equals to thres0 and thres0 event is valid. 0:
+ *  others
+ */
+#define PCNT_CNT_THR_THRES0_LAT_U2    (BIT(3))
+#define PCNT_CNT_THR_THRES0_LAT_U2_M  (PCNT_CNT_THR_THRES0_LAT_U2_V << PCNT_CNT_THR_THRES0_LAT_U2_S)
+#define PCNT_CNT_THR_THRES0_LAT_U2_V  0x00000001U
+#define PCNT_CNT_THR_THRES0_LAT_U2_S  3
+/** PCNT_CNT_THR_L_LIM_LAT_U2 : RO; bitpos: [4]; default: 0;
+ *  The latched value of low limit event of PCNT_U2 when threshold event interrupt is
+ *  valid. 1: the current pulse counter equals to thr_l_lim and low limit event is
+ *  valid. 0: others
+ */
+#define PCNT_CNT_THR_L_LIM_LAT_U2    (BIT(4))
+#define PCNT_CNT_THR_L_LIM_LAT_U2_M  (PCNT_CNT_THR_L_LIM_LAT_U2_V << PCNT_CNT_THR_L_LIM_LAT_U2_S)
+#define PCNT_CNT_THR_L_LIM_LAT_U2_V  0x00000001U
+#define PCNT_CNT_THR_L_LIM_LAT_U2_S  4
+/** PCNT_CNT_THR_H_LIM_LAT_U2 : RO; bitpos: [5]; default: 0;
+ *  The latched value of high limit event of PCNT_U2 when threshold event interrupt is
+ *  valid. 1: the current pulse counter equals to thr_h_lim and high limit event is
+ *  valid. 0: others
+ */
+#define PCNT_CNT_THR_H_LIM_LAT_U2    (BIT(5))
+#define PCNT_CNT_THR_H_LIM_LAT_U2_M  (PCNT_CNT_THR_H_LIM_LAT_U2_V << PCNT_CNT_THR_H_LIM_LAT_U2_S)
+#define PCNT_CNT_THR_H_LIM_LAT_U2_V  0x00000001U
+#define PCNT_CNT_THR_H_LIM_LAT_U2_S  5
+/** PCNT_CNT_THR_ZERO_LAT_U2 : RO; bitpos: [6]; default: 0;
+ *  The latched value of zero threshold event of PCNT_U2 when threshold event interrupt
+ *  is valid. 1: the current pulse counter equals to 0 and zero threshold event is
+ *  valid. 0: others
+ */
+#define PCNT_CNT_THR_ZERO_LAT_U2    (BIT(6))
+#define PCNT_CNT_THR_ZERO_LAT_U2_M  (PCNT_CNT_THR_ZERO_LAT_U2_V << PCNT_CNT_THR_ZERO_LAT_U2_S)
+#define PCNT_CNT_THR_ZERO_LAT_U2_V  0x00000001U
+#define PCNT_CNT_THR_ZERO_LAT_U2_S  6
 
-#define PCNT_U3_STATUS_REG          (DR_REG_PCNT_BASE + 0x005c)
-/* PCNT_CNT_THR_ZERO_LAT_U3 : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define PCNT_CNT_THR_ZERO_LAT_U3  (BIT(6))
-#define PCNT_CNT_THR_ZERO_LAT_U3_M  (BIT(6))
-#define PCNT_CNT_THR_ZERO_LAT_U3_V  0x1
-#define PCNT_CNT_THR_ZERO_LAT_U3_S  6
-/* PCNT_CNT_THR_H_LIM_LAT_U3 : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define PCNT_CNT_THR_H_LIM_LAT_U3  (BIT(5))
-#define PCNT_CNT_THR_H_LIM_LAT_U3_M  (BIT(5))
-#define PCNT_CNT_THR_H_LIM_LAT_U3_V  0x1
-#define PCNT_CNT_THR_H_LIM_LAT_U3_S  5
-/* PCNT_CNT_THR_L_LIM_LAT_U3 : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define PCNT_CNT_THR_L_LIM_LAT_U3  (BIT(4))
-#define PCNT_CNT_THR_L_LIM_LAT_U3_M  (BIT(4))
-#define PCNT_CNT_THR_L_LIM_LAT_U3_V  0x1
-#define PCNT_CNT_THR_L_LIM_LAT_U3_S  4
-/* PCNT_CNT_THR_THRES0_LAT_U3 : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define PCNT_CNT_THR_THRES0_LAT_U3  (BIT(3))
-#define PCNT_CNT_THR_THRES0_LAT_U3_M  (BIT(3))
-#define PCNT_CNT_THR_THRES0_LAT_U3_V  0x1
-#define PCNT_CNT_THR_THRES0_LAT_U3_S  3
-/* PCNT_CNT_THR_THRES1_LAT_U3 : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define PCNT_CNT_THR_THRES1_LAT_U3  (BIT(2))
-#define PCNT_CNT_THR_THRES1_LAT_U3_M  (BIT(2))
-#define PCNT_CNT_THR_THRES1_LAT_U3_V  0x1
-#define PCNT_CNT_THR_THRES1_LAT_U3_S  2
-/* PCNT_CNT_THR_ZERO_MODE_U3 : RO ;bitpos:[1:0] ;default: 2'b0 ; */
-/*description: */
-#define PCNT_CNT_THR_ZERO_MODE_U3  0x00000003
-#define PCNT_CNT_THR_ZERO_MODE_U3_M  ((PCNT_CNT_THR_ZERO_MODE_U3_V)<<(PCNT_CNT_THR_ZERO_MODE_U3_S))
-#define PCNT_CNT_THR_ZERO_MODE_U3_V  0x3
+/** PCNT_U3_STATUS_REG register
+ *  PNCT UNIT3 status register
+ */
+#define PCNT_U3_STATUS_REG (DR_REG_PCNT_BASE + 0x5c)
+/** PCNT_CNT_THR_ZERO_MODE_U3 : RO; bitpos: [1:0]; default: 0;
+ *  The pulse counter status of PCNT_U3 corresponding to 0. 0: pulse counter decreases
+ *  from positive to 0. 1: pulse counter increases from negative to 0. 2: pulse counter
+ *  is negative. 3: pulse counter is positive.
+ */
+#define PCNT_CNT_THR_ZERO_MODE_U3    0x00000003U
+#define PCNT_CNT_THR_ZERO_MODE_U3_M  (PCNT_CNT_THR_ZERO_MODE_U3_V << PCNT_CNT_THR_ZERO_MODE_U3_S)
+#define PCNT_CNT_THR_ZERO_MODE_U3_V  0x00000003U
 #define PCNT_CNT_THR_ZERO_MODE_U3_S  0
+/** PCNT_CNT_THR_THRES1_LAT_U3 : RO; bitpos: [2]; default: 0;
+ *  The latched value of thres1 event of PCNT_U3 when threshold event interrupt is
+ *  valid. 1: the current pulse counter equals to thres1 and thres1 event is valid. 0:
+ *  others
+ */
+#define PCNT_CNT_THR_THRES1_LAT_U3    (BIT(2))
+#define PCNT_CNT_THR_THRES1_LAT_U3_M  (PCNT_CNT_THR_THRES1_LAT_U3_V << PCNT_CNT_THR_THRES1_LAT_U3_S)
+#define PCNT_CNT_THR_THRES1_LAT_U3_V  0x00000001U
+#define PCNT_CNT_THR_THRES1_LAT_U3_S  2
+/** PCNT_CNT_THR_THRES0_LAT_U3 : RO; bitpos: [3]; default: 0;
+ *  The latched value of thres0 event of PCNT_U3 when threshold event interrupt is
+ *  valid. 1: the current pulse counter equals to thres0 and thres0 event is valid. 0:
+ *  others
+ */
+#define PCNT_CNT_THR_THRES0_LAT_U3    (BIT(3))
+#define PCNT_CNT_THR_THRES0_LAT_U3_M  (PCNT_CNT_THR_THRES0_LAT_U3_V << PCNT_CNT_THR_THRES0_LAT_U3_S)
+#define PCNT_CNT_THR_THRES0_LAT_U3_V  0x00000001U
+#define PCNT_CNT_THR_THRES0_LAT_U3_S  3
+/** PCNT_CNT_THR_L_LIM_LAT_U3 : RO; bitpos: [4]; default: 0;
+ *  The latched value of low limit event of PCNT_U3 when threshold event interrupt is
+ *  valid. 1: the current pulse counter equals to thr_l_lim and low limit event is
+ *  valid. 0: others
+ */
+#define PCNT_CNT_THR_L_LIM_LAT_U3    (BIT(4))
+#define PCNT_CNT_THR_L_LIM_LAT_U3_M  (PCNT_CNT_THR_L_LIM_LAT_U3_V << PCNT_CNT_THR_L_LIM_LAT_U3_S)
+#define PCNT_CNT_THR_L_LIM_LAT_U3_V  0x00000001U
+#define PCNT_CNT_THR_L_LIM_LAT_U3_S  4
+/** PCNT_CNT_THR_H_LIM_LAT_U3 : RO; bitpos: [5]; default: 0;
+ *  The latched value of high limit event of PCNT_U3 when threshold event interrupt is
+ *  valid. 1: the current pulse counter equals to thr_h_lim and high limit event is
+ *  valid. 0: others
+ */
+#define PCNT_CNT_THR_H_LIM_LAT_U3    (BIT(5))
+#define PCNT_CNT_THR_H_LIM_LAT_U3_M  (PCNT_CNT_THR_H_LIM_LAT_U3_V << PCNT_CNT_THR_H_LIM_LAT_U3_S)
+#define PCNT_CNT_THR_H_LIM_LAT_U3_V  0x00000001U
+#define PCNT_CNT_THR_H_LIM_LAT_U3_S  5
+/** PCNT_CNT_THR_ZERO_LAT_U3 : RO; bitpos: [6]; default: 0;
+ *  The latched value of zero threshold event of PCNT_U3 when threshold event interrupt
+ *  is valid. 1: the current pulse counter equals to 0 and zero threshold event is
+ *  valid. 0: others
+ */
+#define PCNT_CNT_THR_ZERO_LAT_U3    (BIT(6))
+#define PCNT_CNT_THR_ZERO_LAT_U3_M  (PCNT_CNT_THR_ZERO_LAT_U3_V << PCNT_CNT_THR_ZERO_LAT_U3_S)
+#define PCNT_CNT_THR_ZERO_LAT_U3_V  0x00000001U
+#define PCNT_CNT_THR_ZERO_LAT_U3_S  6
 
-#define PCNT_CTRL_REG          (DR_REG_PCNT_BASE + 0x0060)
-/* PCNT_CLK_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */
-/*description: */
-#define PCNT_CLK_EN  (BIT(16))
-#define PCNT_CLK_EN_M  (BIT(16))
-#define PCNT_CLK_EN_V  0x1
-#define PCNT_CLK_EN_S  16
-/* PCNT_CNT_PAUSE_U3 : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: */
-#define PCNT_CNT_PAUSE_U3  (BIT(7))
-#define PCNT_CNT_PAUSE_U3_M  (BIT(7))
-#define PCNT_CNT_PAUSE_U3_V  0x1
-#define PCNT_CNT_PAUSE_U3_S  7
-/* PCNT_PULSE_CNT_RST_U3 : R/W ;bitpos:[6] ;default: 1'b1 ; */
-/*description: */
-#define PCNT_PULSE_CNT_RST_U3  (BIT(6))
-#define PCNT_PULSE_CNT_RST_U3_M  (BIT(6))
-#define PCNT_PULSE_CNT_RST_U3_V  0x1
-#define PCNT_PULSE_CNT_RST_U3_S  6
-/* PCNT_CNT_PAUSE_U2 : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define PCNT_CNT_PAUSE_U2  (BIT(5))
-#define PCNT_CNT_PAUSE_U2_M  (BIT(5))
-#define PCNT_CNT_PAUSE_U2_V  0x1
-#define PCNT_CNT_PAUSE_U2_S  5
-/* PCNT_PULSE_CNT_RST_U2 : R/W ;bitpos:[4] ;default: 1'b1 ; */
-/*description: */
-#define PCNT_PULSE_CNT_RST_U2  (BIT(4))
-#define PCNT_PULSE_CNT_RST_U2_M  (BIT(4))
-#define PCNT_PULSE_CNT_RST_U2_V  0x1
-#define PCNT_PULSE_CNT_RST_U2_S  4
-/* PCNT_CNT_PAUSE_U1 : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define PCNT_CNT_PAUSE_U1  (BIT(3))
-#define PCNT_CNT_PAUSE_U1_M  (BIT(3))
-#define PCNT_CNT_PAUSE_U1_V  0x1
-#define PCNT_CNT_PAUSE_U1_S  3
-/* PCNT_PULSE_CNT_RST_U1 : R/W ;bitpos:[2] ;default: 1'b1 ; */
-/*description: */
-#define PCNT_PULSE_CNT_RST_U1  (BIT(2))
-#define PCNT_PULSE_CNT_RST_U1_M  (BIT(2))
-#define PCNT_PULSE_CNT_RST_U1_V  0x1
-#define PCNT_PULSE_CNT_RST_U1_S  2
-/* PCNT_CNT_PAUSE_U0 : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define PCNT_CNT_PAUSE_U0  (BIT(1))
-#define PCNT_CNT_PAUSE_U0_M  (BIT(1))
-#define PCNT_CNT_PAUSE_U0_V  0x1
-#define PCNT_CNT_PAUSE_U0_S  1
-/* PCNT_PULSE_CNT_RST_U0 : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: */
-#define PCNT_PULSE_CNT_RST_U0  (BIT(0))
-#define PCNT_PULSE_CNT_RST_U0_M  (BIT(0))
-#define PCNT_PULSE_CNT_RST_U0_V  0x1
+/** PCNT_CTRL_REG register
+ *  Control register for all counters
+ */
+#define PCNT_CTRL_REG (DR_REG_PCNT_BASE + 0x60)
+/** PCNT_PULSE_CNT_RST_U0 : R/W; bitpos: [0]; default: 1;
+ *  Set this bit to clear unit 0's counter.
+ */
+#define PCNT_PULSE_CNT_RST_U0    (BIT(0))
+#define PCNT_PULSE_CNT_RST_U0_M  (PCNT_PULSE_CNT_RST_U0_V << PCNT_PULSE_CNT_RST_U0_S)
+#define PCNT_PULSE_CNT_RST_U0_V  0x00000001U
 #define PCNT_PULSE_CNT_RST_U0_S  0
+/** PCNT_CNT_PAUSE_U0 : R/W; bitpos: [1]; default: 0;
+ *  Set this bit to freeze unit 0's counter.
+ */
+#define PCNT_CNT_PAUSE_U0    (BIT(1))
+#define PCNT_CNT_PAUSE_U0_M  (PCNT_CNT_PAUSE_U0_V << PCNT_CNT_PAUSE_U0_S)
+#define PCNT_CNT_PAUSE_U0_V  0x00000001U
+#define PCNT_CNT_PAUSE_U0_S  1
+/** PCNT_PULSE_CNT_RST_U1 : R/W; bitpos: [2]; default: 1;
+ *  Set this bit to clear unit 1's counter.
+ */
+#define PCNT_PULSE_CNT_RST_U1    (BIT(2))
+#define PCNT_PULSE_CNT_RST_U1_M  (PCNT_PULSE_CNT_RST_U1_V << PCNT_PULSE_CNT_RST_U1_S)
+#define PCNT_PULSE_CNT_RST_U1_V  0x00000001U
+#define PCNT_PULSE_CNT_RST_U1_S  2
+/** PCNT_CNT_PAUSE_U1 : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to freeze unit 1's counter.
+ */
+#define PCNT_CNT_PAUSE_U1    (BIT(3))
+#define PCNT_CNT_PAUSE_U1_M  (PCNT_CNT_PAUSE_U1_V << PCNT_CNT_PAUSE_U1_S)
+#define PCNT_CNT_PAUSE_U1_V  0x00000001U
+#define PCNT_CNT_PAUSE_U1_S  3
+/** PCNT_PULSE_CNT_RST_U2 : R/W; bitpos: [4]; default: 1;
+ *  Set this bit to clear unit 2's counter.
+ */
+#define PCNT_PULSE_CNT_RST_U2    (BIT(4))
+#define PCNT_PULSE_CNT_RST_U2_M  (PCNT_PULSE_CNT_RST_U2_V << PCNT_PULSE_CNT_RST_U2_S)
+#define PCNT_PULSE_CNT_RST_U2_V  0x00000001U
+#define PCNT_PULSE_CNT_RST_U2_S  4
+/** PCNT_CNT_PAUSE_U2 : R/W; bitpos: [5]; default: 0;
+ *  Set this bit to freeze unit 2's counter.
+ */
+#define PCNT_CNT_PAUSE_U2    (BIT(5))
+#define PCNT_CNT_PAUSE_U2_M  (PCNT_CNT_PAUSE_U2_V << PCNT_CNT_PAUSE_U2_S)
+#define PCNT_CNT_PAUSE_U2_V  0x00000001U
+#define PCNT_CNT_PAUSE_U2_S  5
+/** PCNT_PULSE_CNT_RST_U3 : R/W; bitpos: [6]; default: 1;
+ *  Set this bit to clear unit 3's counter.
+ */
+#define PCNT_PULSE_CNT_RST_U3    (BIT(6))
+#define PCNT_PULSE_CNT_RST_U3_M  (PCNT_PULSE_CNT_RST_U3_V << PCNT_PULSE_CNT_RST_U3_S)
+#define PCNT_PULSE_CNT_RST_U3_V  0x00000001U
+#define PCNT_PULSE_CNT_RST_U3_S  6
+/** PCNT_CNT_PAUSE_U3 : R/W; bitpos: [7]; default: 0;
+ *  Set this bit to freeze unit 3's counter.
+ */
+#define PCNT_CNT_PAUSE_U3    (BIT(7))
+#define PCNT_CNT_PAUSE_U3_M  (PCNT_CNT_PAUSE_U3_V << PCNT_CNT_PAUSE_U3_S)
+#define PCNT_CNT_PAUSE_U3_V  0x00000001U
+#define PCNT_CNT_PAUSE_U3_S  7
+/** PCNT_CLK_EN : R/W; bitpos: [16]; default: 0;
+ *  The registers clock gate enable signal of PCNT module. 1: the registers can be read
+ *  and written by application. 0: the registers can not be read or written by
+ *  application
+ */
+#define PCNT_CLK_EN    (BIT(16))
+#define PCNT_CLK_EN_M  (PCNT_CLK_EN_V << PCNT_CLK_EN_S)
+#define PCNT_CLK_EN_V  0x00000001U
+#define PCNT_CLK_EN_S  16
 
-#define PCNT_DATE_REG          (DR_REG_PCNT_BASE + 0x00fc)
-/* PCNT_DATE : R/W ;bitpos:[31:0] ;default: 32'h18072600 ; */
-/*description: */
-#define PCNT_DATE  0xFFFFFFFF
-#define PCNT_DATE_M  ((PCNT_DATE_V)<<(PCNT_DATE_S))
-#define PCNT_DATE_V  0xFFFFFFFF
+/** PCNT_DATE_REG register
+ *  PCNT version control register
+ */
+#define PCNT_DATE_REG (DR_REG_PCNT_BASE + 0xfc)
+/** PCNT_DATE : R/W; bitpos: [31:0]; default: 419898881;
+ *  This is the PCNT version control register.
+ */
+#define PCNT_DATE    0xFFFFFFFFU
+#define PCNT_DATE_M  (PCNT_DATE_V << PCNT_DATE_S)
+#define PCNT_DATE_V  0xFFFFFFFFU
 #define PCNT_DATE_S  0
 
 #ifdef __cplusplus
 }
 #endif
-
-
-
-#endif /*_SOC_PCNT_REG_H_ */

components/soc/esp32s2/include/soc/pcnt_struct.h

@@ -1,177 +1,416 @@
-// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _SOC_PCNT_STRUCT_H_
-#define _SOC_PCNT_STRUCT_H_
+/** Copyright 2021 Espressif Systems (Shanghai) PTE LTD
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License");
+ *  you may not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS,
+ *  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ */
+#pragma once
+
+#include <stdint.h>
+
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-typedef volatile struct {
+/** Group: Configuration Register */
+/** Type of un_conf0 register
+ *  Configuration register 0 for unit n
+ */
+typedef union {
+    struct {
+        /** filter_thres_un : R/W; bitpos: [9:0]; default: 16;
+         *  This sets the maximum threshold, in APB_CLK cycles, for the filter.
+         *
+         *  Any pulses with width less than this will be ignored when the filter is enabled.
+         */
+        uint32_t filter_thres_un: 10;
+        /** filter_en_un : R/W; bitpos: [10]; default: 1;
+         *  This is the enable bit for unit n's input filter.
+         */
+        uint32_t filter_en_un: 1;
+        /** thr_zero_en_un : R/W; bitpos: [11]; default: 1;
+         *  This is the enable bit for unit n's zero comparator.
+         */
+        uint32_t thr_zero_en_un: 1;
+        /** thr_h_lim_en_un : R/W; bitpos: [12]; default: 1;
+         *  This is the enable bit for unit n's thr_h_lim comparator.
+         */
+        uint32_t thr_h_lim_en_un: 1;
+        /** thr_l_lim_en_un : R/W; bitpos: [13]; default: 1;
+         *  This is the enable bit for unit n's thr_l_lim comparator.
+         */
+        uint32_t thr_l_lim_en_un: 1;
+        /** thr_thres0_en_un : R/W; bitpos: [14]; default: 0;
+         *  This is the enable bit for unit n's thres0 comparator.
+         */
+        uint32_t thr_thres0_en_un: 1;
+        /** thr_thres1_en_un : R/W; bitpos: [15]; default: 0;
+         *  This is the enable bit for unit n's thres1 comparator.
+         */
+        uint32_t thr_thres1_en_un: 1;
+        /** ch0_neg_mode_un : R/W; bitpos: [17:16]; default: 0;
+         *  This register sets the behavior when the signal input of channel 0 detects a
+         *  negative edge.
+         *
+         *  1: Increase the counter;2: Decrease the counter;0, 3: No effect on counter
+         */
+        uint32_t ch0_neg_mode_un: 2;
+        /** ch0_pos_mode_un : R/W; bitpos: [19:18]; default: 0;
+         *  This register sets the behavior when the signal input of channel 0 detects a
+         *  positive edge.
+         *
+         *  1: Increase the counter;2: Decrease the counter;0, 3: No effect on counter
+         */
+        uint32_t ch0_pos_mode_un: 2;
+        /** ch0_hctrl_mode_un : R/W; bitpos: [21:20]; default: 0;
+         *  This register configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be
+         *  modified when the control signal is high.
+         *
+         *  0: No modification;1: Invert behavior (increase -> decrease, decrease ->
+         *  increase);2, 3: Inhibit counter modification
+         */
+        uint32_t ch0_hctrl_mode_un: 2;
+        /** ch0_lctrl_mode_un : R/W; bitpos: [23:22]; default: 0;
+         *  This register configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be
+         *  modified when the control signal is low.
+         *
+         *  0: No modification;1: Invert behavior (increase -> decrease, decrease ->
+         *  increase);2, 3: Inhibit counter modification
+         */
+        uint32_t ch0_lctrl_mode_un: 2;
+        /** ch1_neg_mode_un : R/W; bitpos: [25:24]; default: 0;
+         *  This register sets the behavior when the signal input of channel 1 detects a
+         *  negative edge.
+         *
+         *  1: Increment the counter;2: Decrement the counter;0, 3: No effect on counter
+         */
+        uint32_t ch1_neg_mode_un: 2;
+        /** ch1_pos_mode_un : R/W; bitpos: [27:26]; default: 0;
+         *  This register sets the behavior when the signal input of channel 1 detects a
+         *  positive edge.
+         *
+         *  1: Increment the counter;2: Decrement the counter;0, 3: No effect on counter
+         */
+        uint32_t ch1_pos_mode_un: 2;
+        /** ch1_hctrl_mode_un : R/W; bitpos: [29:28]; default: 0;
+         *  This register configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be
+         *  modified when the control signal is high.
+         *
+         *  0: No modification;1: Invert behavior (increase -> decrease, decrease ->
+         *  increase);2, 3: Inhibit counter modification
+         */
+        uint32_t ch1_hctrl_mode_un: 2;
+        /** ch1_lctrl_mode_un : R/W; bitpos: [31:30]; default: 0;
+         *  This register configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be
+         *  modified when the control signal is low.
+         *
+         *  0: No modification;1: Invert behavior (increase -> decrease, decrease ->
+         *  increase);2, 3: Inhibit counter modification
+         */
+        uint32_t ch1_lctrl_mode_un: 2;
+    };
+    uint32_t val;
+} pcnt_un_conf0_reg_t;
+
+/** Type of un_conf1 register
+ *  Configuration register 1 for unit n
+ */
+typedef union {
+    struct {
+        /** cnt_thres0_un : R/W; bitpos: [15:0]; default: 0;
+         *  This register is used to configure the thres0 value for unit n.
+         */
+        uint32_t cnt_thres0_un: 16;
+        /** cnt_thres1_un : R/W; bitpos: [31:16]; default: 0;
+         *  This register is used to configure the thres1 value for unit n.
+         */
+        uint32_t cnt_thres1_un: 16;
+    };
+    uint32_t val;
+} pcnt_un_conf1_reg_t;
+
+/** Type of un_conf2 register
+ *  Configuration register 2 for unit n
+ */
+typedef union {
+    struct {
+        /** cnt_h_lim_un : R/W; bitpos: [15:0]; default: 0;
+         *  This register is used to configure the thr_h_lim value for unit n.
+         */
+        uint32_t cnt_h_lim_un: 16;
+        /** cnt_l_lim_un : R/W; bitpos: [31:16]; default: 0;
+         *  This register is used to configure the thr_l_lim value for unit n.
+         */
+        uint32_t cnt_l_lim_un: 16;
+    };
+    uint32_t val;
+} pcnt_un_conf2_reg_t;
+
+
+/** Type of ctrl register
+ *  Control register for all counters
+ */
+typedef union {
+    struct {
+        /** pulse_cnt_rst_u0 : R/W; bitpos: [0]; default: 1;
+         *  Set this bit to clear unit 0's counter.
+         */
+        uint32_t pulse_cnt_rst_u0: 1;
+        /** cnt_pause_u0 : R/W; bitpos: [1]; default: 0;
+         *  Set this bit to freeze unit 0's counter.
+         */
+        uint32_t cnt_pause_u0: 1;
+        /** pulse_cnt_rst_u1 : R/W; bitpos: [2]; default: 1;
+         *  Set this bit to clear unit 1's counter.
+         */
+        uint32_t pulse_cnt_rst_u1: 1;
+        /** cnt_pause_u1 : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to freeze unit 1's counter.
+         */
+        uint32_t cnt_pause_u1: 1;
+        /** pulse_cnt_rst_u2 : R/W; bitpos: [4]; default: 1;
+         *  Set this bit to clear unit 2's counter.
+         */
+        uint32_t pulse_cnt_rst_u2: 1;
+        /** cnt_pause_u2 : R/W; bitpos: [5]; default: 0;
+         *  Set this bit to freeze unit 2's counter.
+         */
+        uint32_t cnt_pause_u2: 1;
+        /** pulse_cnt_rst_u3 : R/W; bitpos: [6]; default: 1;
+         *  Set this bit to clear unit 3's counter.
+         */
+        uint32_t pulse_cnt_rst_u3: 1;
+        /** cnt_pause_u3 : R/W; bitpos: [7]; default: 0;
+         *  Set this bit to freeze unit 3's counter.
+         */
+        uint32_t cnt_pause_u3: 1;
+        uint32_t reserved_8: 8;
+        /** clk_en : R/W; bitpos: [16]; default: 0;
+         *  The registers clock gate enable signal of PCNT module. 1: the registers can be read
+         *  and written by application. 0: the registers can not be read or written by
+         *  application
+         */
+        uint32_t clk_en: 1;
+        uint32_t reserved_17: 15;
+    };
+    uint32_t val;
+} pcnt_ctrl_reg_t;
+
+
+/** Group: Status Register */
+/** Type of un_cnt register
+ *  Counter value for unit n
+ */
+typedef union {
+    struct {
+        /** pulse_cnt_un : RO; bitpos: [15:0]; default: 0;
+         *  This register stores the current pulse count value for unit n.
+         */
+        uint32_t pulse_cnt_un: 16;
+        uint32_t reserved_16: 16;
+    };
+    uint32_t val;
+} pcnt_un_cnt_reg_t;
+
+/** Type of un_status register
+ *  PNCT UNITn status register
+ */
+typedef union {
+    struct {
+        /** cnt_thr_zero_mode_un : RO; bitpos: [1:0]; default: 0;
+         *  The pulse counter status of PCNT_Un corresponding to 0. 0: pulse counter decreases
+         *  from positive to 0. 1: pulse counter increases from negative to 0. 2: pulse counter
+         *  is negative. 3: pulse counter is positive.
+         */
+        uint32_t cnt_thr_zero_mode_un: 2;
+        /** cnt_thr_thres1_lat_un : RO; bitpos: [2]; default: 0;
+         *  The latched value of thres1 event of PCNT_Un when threshold event interrupt is
+         *  valid. 1: the current pulse counter equals to thres1 and thres1 event is valid. 0:
+         *  others
+         */
+        uint32_t cnt_thr_thres1_lat_un: 1;
+        /** cnt_thr_thres0_lat_un : RO; bitpos: [3]; default: 0;
+         *  The latched value of thres0 event of PCNT_Un when threshold event interrupt is
+         *  valid. 1: the current pulse counter equals to thres0 and thres0 event is valid. 0:
+         *  others
+         */
+        uint32_t cnt_thr_thres0_lat_un: 1;
+        /** cnt_thr_l_lim_lat_un : RO; bitpos: [4]; default: 0;
+         *  The latched value of low limit event of PCNT_Un when threshold event interrupt is
+         *  valid. 1: the current pulse counter equals to thr_l_lim and low limit event is
+         *  valid. 0: others
+         */
+        uint32_t cnt_thr_l_lim_lat_un: 1;
+        /** cnt_thr_h_lim_lat_un : RO; bitpos: [5]; default: 0;
+         *  The latched value of high limit event of PCNT_Un when threshold event interrupt is
+         *  valid. 1: the current pulse counter equals to thr_h_lim and high limit event is
+         *  valid. 0: others
+         */
+        uint32_t cnt_thr_h_lim_lat_un: 1;
+        /** cnt_thr_zero_lat_un : RO; bitpos: [6]; default: 0;
+         *  The latched value of zero threshold event of PCNT_Un when threshold event interrupt
+         *  is valid. 1: the current pulse counter equals to 0 and zero threshold event is
+         *  valid. 0: others
+         */
+        uint32_t cnt_thr_zero_lat_un: 1;
+        uint32_t reserved_7: 25;
+    };
+    uint32_t val;
+} pcnt_un_status_reg_t;
+
+
+/** Group: Interrupt Register */
+/** Type of int_raw register
+ *  Interrupt raw status register
+ */
+typedef union {
     struct {
-        union {
-            struct {
-                uint32_t filter_thres:     10;
-                uint32_t filter_en:         1;
-                uint32_t thr_zero_en:       1;
-                uint32_t thr_h_lim_en:      1;
-                uint32_t thr_l_lim_en:      1;
-                uint32_t thr_thres0_en:     1;
-                uint32_t thr_thres1_en:     1;
-                uint32_t ch0_neg_mode:      2;
-                uint32_t ch0_pos_mode:      2;
-                uint32_t ch0_hctrl_mode:    2;
-                uint32_t ch0_lctrl_mode:    2;
-                uint32_t ch1_neg_mode:      2;
-                uint32_t ch1_pos_mode:      2;
-                uint32_t ch1_hctrl_mode:    2;
-                uint32_t ch1_lctrl_mode:    2;
-            };
-            uint32_t val;
-        } conf0;
-        union {
-            struct {
-                uint32_t cnt_thres0:   16;
-                uint32_t cnt_thres1:   16;
-            };
-            uint32_t val;
-        } conf1;
-        union {
-            struct {
-                uint32_t cnt_h_lim:   16;
-                uint32_t cnt_l_lim:   16;
-            };
-            uint32_t val;
-        } conf2;
+        /** cnt_thr_event_u0_int_raw : RO; bitpos: [0]; default: 0;
+         *  The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt.
+         */
+        uint32_t cnt_thr_event_u0_int_raw: 1;
+        /** cnt_thr_event_u1_int_raw : RO; bitpos: [1]; default: 0;
+         *  The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt.
+         */
+        uint32_t cnt_thr_event_u1_int_raw: 1;
+        /** cnt_thr_event_u2_int_raw : RO; bitpos: [2]; default: 0;
+         *  The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt.
+         */
+        uint32_t cnt_thr_event_u2_int_raw: 1;
+        /** cnt_thr_event_u3_int_raw : RO; bitpos: [3]; default: 0;
+         *  The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt.
+         */
+        uint32_t cnt_thr_event_u3_int_raw: 1;
+        uint32_t reserved_4: 28;
+    };
+    uint32_t val;
+} pcnt_int_raw_reg_t;
+
+/** Type of int_st register
+ *  Interrupt status register
+ */
+typedef union {
+    struct {
+        /** cnt_thr_event_u0_int_st : RO; bitpos: [0]; default: 0;
+         *  The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt.
+         */
+        uint32_t cnt_thr_event_u0_int_st: 1;
+        /** cnt_thr_event_u1_int_st : RO; bitpos: [1]; default: 0;
+         *  The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt.
+         */
+        uint32_t cnt_thr_event_u1_int_st: 1;
+        /** cnt_thr_event_u2_int_st : RO; bitpos: [2]; default: 0;
+         *  The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt.
+         */
+        uint32_t cnt_thr_event_u2_int_st: 1;
+        /** cnt_thr_event_u3_int_st : RO; bitpos: [3]; default: 0;
+         *  The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt.
+         */
+        uint32_t cnt_thr_event_u3_int_st: 1;
+        uint32_t reserved_4: 28;
+    };
+    uint32_t val;
+} pcnt_int_st_reg_t;
+
+/** Type of int_ena register
+ *  Interrupt enable register
+ */
+typedef union {
+    struct {
+        /** cnt_thr_event_u0_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt.
+         */
+        uint32_t cnt_thr_event_u0_int_ena: 1;
+        /** cnt_thr_event_u1_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The interrupt enable bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt.
+         */
+        uint32_t cnt_thr_event_u1_int_ena: 1;
+        /** cnt_thr_event_u2_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The interrupt enable bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt.
+         */
+        uint32_t cnt_thr_event_u2_int_ena: 1;
+        /** cnt_thr_event_u3_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The interrupt enable bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt.
+         */
+        uint32_t cnt_thr_event_u3_int_ena: 1;
+        uint32_t reserved_4: 28;
+    };
+    uint32_t val;
+} pcnt_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  Interrupt clear register
+ */
+typedef union {
+    struct {
+        /** cnt_thr_event_u0_int_clr : WO; bitpos: [0]; default: 0;
+         *  Set this bit to clear the PCNT_CNT_THR_EVENT_U0_INT interrupt.
+         */
+        uint32_t cnt_thr_event_u0_int_clr: 1;
+        /** cnt_thr_event_u1_int_clr : WO; bitpos: [1]; default: 0;
+         *  Set this bit to clear the PCNT_CNT_THR_EVENT_U1_INT interrupt.
+         */
+        uint32_t cnt_thr_event_u1_int_clr: 1;
+        /** cnt_thr_event_u2_int_clr : WO; bitpos: [2]; default: 0;
+         *  Set this bit to clear the PCNT_CNT_THR_EVENT_U2_INT interrupt.
+         */
+        uint32_t cnt_thr_event_u2_int_clr: 1;
+        /** cnt_thr_event_u3_int_clr : WO; bitpos: [3]; default: 0;
+         *  Set this bit to clear the PCNT_CNT_THR_EVENT_U3_INT interrupt.
+         */
+        uint32_t cnt_thr_event_u3_int_clr: 1;
+        uint32_t reserved_4: 28;
+    };
+    uint32_t val;
+} pcnt_int_clr_reg_t;
+
+
+/** Group: Version Register */
+/** Type of date register
+ *  PCNT version control register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [31:0]; default: 419898881;
+         *  This is the PCNT version control register.
+         */
+        uint32_t date: 32;
+    };
+    uint32_t val;
+} pcnt_date_reg_t;
+
+
+typedef struct {
+    volatile struct {
+        pcnt_un_conf0_reg_t conf0;
+        pcnt_un_conf1_reg_t conf1;
+        pcnt_un_conf2_reg_t conf2;
     } conf_unit[4];
-    union {
-        struct {
-            uint32_t cnt_val:     16;
-            uint32_t reserved16:  16;
-        };
-        uint32_t val;
-    } cnt_unit[4];
-    union {
-        struct {
-            uint32_t cnt_thr_event_u0:         1;
-            uint32_t cnt_thr_event_u1:         1;
-            uint32_t cnt_thr_event_u2:         1;
-            uint32_t cnt_thr_event_u3:         1;
-            uint32_t reserved4:               28;
-        };
-        uint32_t val;
-    } int_raw;
-    union {
-        struct {
-            uint32_t cnt_thr_event_u0:        1;
-            uint32_t cnt_thr_event_u1:        1;
-            uint32_t cnt_thr_event_u2:        1;
-            uint32_t cnt_thr_event_u3:        1;
-            uint32_t reserved4:              28;
-        };
-        uint32_t val;
-    } int_st;
-    union {
-        struct {
-            uint32_t cnt_thr_event_u0:         1;
-            uint32_t cnt_thr_event_u1:         1;
-            uint32_t cnt_thr_event_u2:         1;
-            uint32_t cnt_thr_event_u3:         1;
-            uint32_t reserved4:               28;
-        };
-        uint32_t val;
-    } int_ena;
-    union {
-        struct {
-            uint32_t cnt_thr_event_u0:         1;
-            uint32_t cnt_thr_event_u1:         1;
-            uint32_t cnt_thr_event_u2:         1;
-            uint32_t cnt_thr_event_u3:         1;
-            uint32_t reserved4:               28;
-        };
-        uint32_t val;
-    } int_clr;
-    union {
-        struct {
-            uint32_t cnt_mode:              2;
-            uint32_t thres1_lat:            1;
-            uint32_t thres0_lat:            1;
-            uint32_t l_lim_lat:             1;
-            uint32_t h_lim_lat:             1;
-            uint32_t zero_lat:              1;
-            uint32_t reserved7:            25;
-        };
-        uint32_t val;
-    } status_unit[4];
-    union {
-        struct {
-            uint32_t cnt_rst_u0:       1;
-            uint32_t cnt_pause_u0:     1;
-            uint32_t cnt_rst_u1:       1;
-            uint32_t cnt_pause_u1:     1;
-            uint32_t cnt_rst_u2:       1;
-            uint32_t cnt_pause_u2:     1;
-            uint32_t cnt_rst_u3:       1;
-            uint32_t cnt_pause_u3:     1;
-            uint32_t reserved8:        8;
-            uint32_t clk_en:           1;
-            uint32_t reserved17:      15;
-        };
-        uint32_t val;
-    } ctrl;
-    uint32_t reserved_64;
-    uint32_t reserved_68;
-    uint32_t reserved_6c;
-    uint32_t reserved_70;
-    uint32_t reserved_74;
-    uint32_t reserved_78;
-    uint32_t reserved_7c;
-    uint32_t reserved_80;
-    uint32_t reserved_84;
-    uint32_t reserved_88;
-    uint32_t reserved_8c;
-    uint32_t reserved_90;
-    uint32_t reserved_94;
-    uint32_t reserved_98;
-    uint32_t reserved_9c;
-    uint32_t reserved_a0;
-    uint32_t reserved_a4;
-    uint32_t reserved_a8;
-    uint32_t reserved_ac;
-    uint32_t reserved_b0;
-    uint32_t reserved_b4;
-    uint32_t reserved_b8;
-    uint32_t reserved_bc;
-    uint32_t reserved_c0;
-    uint32_t reserved_c4;
-    uint32_t reserved_c8;
-    uint32_t reserved_cc;
-    uint32_t reserved_d0;
-    uint32_t reserved_d4;
-    uint32_t reserved_d8;
-    uint32_t reserved_dc;
-    uint32_t reserved_e0;
-    uint32_t reserved_e4;
-    uint32_t reserved_e8;
-    uint32_t reserved_ec;
-    uint32_t reserved_f0;
-    uint32_t reserved_f4;
-    uint32_t reserved_f8;
-    uint32_t date;                                  /**/
+    volatile pcnt_un_cnt_reg_t cnt_unit[4];
+    volatile pcnt_int_raw_reg_t int_raw;
+    volatile pcnt_int_st_reg_t int_st;
+    volatile pcnt_int_ena_reg_t int_ena;
+    volatile pcnt_int_clr_reg_t int_clr;
+    volatile pcnt_un_status_reg_t status_unit[4];
+    volatile pcnt_ctrl_reg_t ctrl;
+    uint32_t reserved_064[38];
+    volatile pcnt_date_reg_t date;
 } pcnt_dev_t;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(pcnt_dev_t) == 0x100, "Invalid size of pcnt_dev_t structure");
+#endif
+
 extern pcnt_dev_t PCNT;
+
 #ifdef __cplusplus
 }
 #endif
-
-#endif  /* _SOC_PCNT_STRUCT_H_ */

components/soc/esp32s2/include/soc/soc_caps.h

@@ -156,10 +156,10 @@
 #define SOC_MPU_REGION_WO_SUPPORTED               0
 
 /*-------------------------- PCNT CAPS ---------------------------------------*/
-// ESP32-S2 have 1 PCNT peripheral
-#define SOC_PCNT_PORT_NUM      (1)
-#define SOC_PCNT_UNIT_NUM      (4) // ESP32-S2 only have 4 unit
-#define SOC_PCNT_UNIT_CHANNEL_NUM (2)
+#define SOC_PCNT_GROUPS               (1)
+#define SOC_PCNT_UNITS_PER_GROUP      (4)
+#define SOC_PCNT_CHANNELS_PER_UNIT    (2)
+#define SOC_PCNT_THRES_POINT_PER_UNIT (2)
 
 /*-------------------------- RMT CAPS ----------------------------------------*/
 #define SOC_RMT_GROUPS                  (1)  /*!< One RMT group */

components/soc/esp32s2/pcnt_periph.c

@@ -16,54 +16,58 @@
 #include "soc/gpio_sig_map.h"
 
 const pcnt_signal_conn_t pcnt_periph_signals = {
-    .module = PERIPH_PCNT_MODULE,
-    .irq = ETS_PCNT_INTR_SOURCE,
-    .units = {
+    .groups = {
         [0] = {
-            .channels = {
+            .module = PERIPH_PCNT_MODULE,
+            .irq = ETS_PCNT_INTR_SOURCE,
+            .units = {
                 [0] = {
-                    .control_sig = PCNT_CTRL_CH0_IN0_IDX,
-                    .pulse_sig = PCNT_SIG_CH0_IN0_IDX
+                    .channels = {
+                        [0] = {
+                            .control_sig = PCNT_CTRL_CH0_IN0_IDX,
+                            .pulse_sig = PCNT_SIG_CH0_IN0_IDX
+                        },
+                        [1] = {
+                            .control_sig = PCNT_CTRL_CH1_IN0_IDX,
+                            .pulse_sig = PCNT_SIG_CH1_IN0_IDX
+                        }
+                    }
                 },
                 [1] = {
-                    .control_sig = PCNT_CTRL_CH1_IN0_IDX,
-                    .pulse_sig = PCNT_SIG_CH1_IN0_IDX
-                }
-            }
-        },
-        [1] = {
-            .channels = {
-                [0] = {
-                    .control_sig = PCNT_CTRL_CH0_IN1_IDX,
-                    .pulse_sig = PCNT_SIG_CH0_IN1_IDX
+                    .channels = {
+                        [0] = {
+                            .control_sig = PCNT_CTRL_CH0_IN1_IDX,
+                            .pulse_sig = PCNT_SIG_CH0_IN1_IDX
+                        },
+                        [1] = {
+                            .control_sig = PCNT_CTRL_CH1_IN1_IDX,
+                            .pulse_sig = PCNT_SIG_CH1_IN1_IDX
+                        }
+                    }
                 },
-                [1] = {
-                    .control_sig = PCNT_CTRL_CH1_IN1_IDX,
-                    .pulse_sig = PCNT_SIG_CH1_IN1_IDX
-                }
-            }
-        },
-        [2] = {
-            .channels = {
-                [0] = {
-                    .control_sig = PCNT_CTRL_CH0_IN2_IDX,
-                    .pulse_sig = PCNT_SIG_CH0_IN2_IDX
+                [2] = {
+                    .channels = {
+                        [0] = {
+                            .control_sig = PCNT_CTRL_CH0_IN2_IDX,
+                            .pulse_sig = PCNT_SIG_CH0_IN2_IDX
+                        },
+                        [1] = {
+                            .control_sig = PCNT_CTRL_CH1_IN2_IDX,
+                            .pulse_sig = PCNT_SIG_CH1_IN2_IDX
+                        }
+                    }
                 },
-                [1] = {
-                    .control_sig = PCNT_CTRL_CH1_IN2_IDX,
-                    .pulse_sig = PCNT_SIG_CH1_IN2_IDX
-                }
-            }
-        },
-        [3] = {
-            .channels = {
-                [0] = {
-                    .control_sig = PCNT_CTRL_CH0_IN3_IDX,
-                    .pulse_sig = PCNT_SIG_CH0_IN3_IDX
-                },
-                [1] = {
-                    .control_sig = PCNT_CTRL_CH1_IN3_IDX,
-                    .pulse_sig = PCNT_SIG_CH1_IN3_IDX
+                [3] = {
+                    .channels = {
+                        [0] = {
+                            .control_sig = PCNT_CTRL_CH0_IN3_IDX,
+                            .pulse_sig = PCNT_SIG_CH0_IN3_IDX
+                        },
+                        [1] = {
+                            .control_sig = PCNT_CTRL_CH1_IN3_IDX,
+                            .pulse_sig = PCNT_SIG_CH1_IN3_IDX
+                        }
+                    }
                 }
             }
         }

components/soc/esp32s3/include/soc/pcnt_reg.h

@@ -1,862 +1,1236 @@
-// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _SOC_PCNT_REG_H_
-#define _SOC_PCNT_REG_H_
+/** Copyright 2021 Espressif Systems (Shanghai) PTE LTD
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License");
+ *  you may not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS,
+ *  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ */
+#pragma once
 
+#include <stdint.h>
+#include "soc/soc.h"
 
-#include "soc.h"
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-#define PCNT_U0_CONF0_REG          (DR_REG_PCNT_BASE + 0x0)
-/* PCNT_CH1_LCTRL_MODE_U0 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */
-/*description: .*/
-#define PCNT_CH1_LCTRL_MODE_U0    0x00000003
-#define PCNT_CH1_LCTRL_MODE_U0_M  ((PCNT_CH1_LCTRL_MODE_U0_V)<<(PCNT_CH1_LCTRL_MODE_U0_S))
-#define PCNT_CH1_LCTRL_MODE_U0_V  0x3
-#define PCNT_CH1_LCTRL_MODE_U0_S  30
-/* PCNT_CH1_HCTRL_MODE_U0 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */
-/*description: .*/
-#define PCNT_CH1_HCTRL_MODE_U0    0x00000003
-#define PCNT_CH1_HCTRL_MODE_U0_M  ((PCNT_CH1_HCTRL_MODE_U0_V)<<(PCNT_CH1_HCTRL_MODE_U0_S))
-#define PCNT_CH1_HCTRL_MODE_U0_V  0x3
-#define PCNT_CH1_HCTRL_MODE_U0_S  28
-/* PCNT_CH1_POS_MODE_U0 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */
-/*description: .*/
-#define PCNT_CH1_POS_MODE_U0    0x00000003
-#define PCNT_CH1_POS_MODE_U0_M  ((PCNT_CH1_POS_MODE_U0_V)<<(PCNT_CH1_POS_MODE_U0_S))
-#define PCNT_CH1_POS_MODE_U0_V  0x3
-#define PCNT_CH1_POS_MODE_U0_S  26
-/* PCNT_CH1_NEG_MODE_U0 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */
-/*description: .*/
-#define PCNT_CH1_NEG_MODE_U0    0x00000003
-#define PCNT_CH1_NEG_MODE_U0_M  ((PCNT_CH1_NEG_MODE_U0_V)<<(PCNT_CH1_NEG_MODE_U0_S))
-#define PCNT_CH1_NEG_MODE_U0_V  0x3
-#define PCNT_CH1_NEG_MODE_U0_S  24
-/* PCNT_CH0_LCTRL_MODE_U0 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */
-/*description: .*/
-#define PCNT_CH0_LCTRL_MODE_U0    0x00000003
-#define PCNT_CH0_LCTRL_MODE_U0_M  ((PCNT_CH0_LCTRL_MODE_U0_V)<<(PCNT_CH0_LCTRL_MODE_U0_S))
-#define PCNT_CH0_LCTRL_MODE_U0_V  0x3
-#define PCNT_CH0_LCTRL_MODE_U0_S  22
-/* PCNT_CH0_HCTRL_MODE_U0 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */
-/*description: .*/
-#define PCNT_CH0_HCTRL_MODE_U0    0x00000003
-#define PCNT_CH0_HCTRL_MODE_U0_M  ((PCNT_CH0_HCTRL_MODE_U0_V)<<(PCNT_CH0_HCTRL_MODE_U0_S))
-#define PCNT_CH0_HCTRL_MODE_U0_V  0x3
-#define PCNT_CH0_HCTRL_MODE_U0_S  20
-/* PCNT_CH0_POS_MODE_U0 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */
-/*description: .*/
-#define PCNT_CH0_POS_MODE_U0    0x00000003
-#define PCNT_CH0_POS_MODE_U0_M  ((PCNT_CH0_POS_MODE_U0_V)<<(PCNT_CH0_POS_MODE_U0_S))
-#define PCNT_CH0_POS_MODE_U0_V  0x3
-#define PCNT_CH0_POS_MODE_U0_S  18
-/* PCNT_CH0_NEG_MODE_U0 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */
-/*description: .*/
-#define PCNT_CH0_NEG_MODE_U0    0x00000003
-#define PCNT_CH0_NEG_MODE_U0_M  ((PCNT_CH0_NEG_MODE_U0_V)<<(PCNT_CH0_NEG_MODE_U0_S))
-#define PCNT_CH0_NEG_MODE_U0_V  0x3
-#define PCNT_CH0_NEG_MODE_U0_S  16
-/* PCNT_THR_THRES1_EN_U0 : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: .*/
-#define PCNT_THR_THRES1_EN_U0    (BIT(15))
-#define PCNT_THR_THRES1_EN_U0_M  (BIT(15))
-#define PCNT_THR_THRES1_EN_U0_V  0x1
-#define PCNT_THR_THRES1_EN_U0_S  15
-/* PCNT_THR_THRES0_EN_U0 : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: .*/
-#define PCNT_THR_THRES0_EN_U0    (BIT(14))
-#define PCNT_THR_THRES0_EN_U0_M  (BIT(14))
-#define PCNT_THR_THRES0_EN_U0_V  0x1
-#define PCNT_THR_THRES0_EN_U0_S  14
-/* PCNT_THR_L_LIM_EN_U0 : R/W ;bitpos:[13] ;default: 1'b1 ; */
-/*description: .*/
-#define PCNT_THR_L_LIM_EN_U0    (BIT(13))
-#define PCNT_THR_L_LIM_EN_U0_M  (BIT(13))
-#define PCNT_THR_L_LIM_EN_U0_V  0x1
-#define PCNT_THR_L_LIM_EN_U0_S  13
-/* PCNT_THR_H_LIM_EN_U0 : R/W ;bitpos:[12] ;default: 1'b1 ; */
-/*description: .*/
-#define PCNT_THR_H_LIM_EN_U0    (BIT(12))
-#define PCNT_THR_H_LIM_EN_U0_M  (BIT(12))
-#define PCNT_THR_H_LIM_EN_U0_V  0x1
-#define PCNT_THR_H_LIM_EN_U0_S  12
-/* PCNT_THR_ZERO_EN_U0 : R/W ;bitpos:[11] ;default: 1'b1 ; */
-/*description: .*/
-#define PCNT_THR_ZERO_EN_U0    (BIT(11))
-#define PCNT_THR_ZERO_EN_U0_M  (BIT(11))
-#define PCNT_THR_ZERO_EN_U0_V  0x1
-#define PCNT_THR_ZERO_EN_U0_S  11
-/* PCNT_FILTER_EN_U0 : R/W ;bitpos:[10] ;default: 1'b1 ; */
-/*description: .*/
+/** PCNT_U0_CONF0_REG register
+ *  Configuration register 0 for unit 0
+ */
+#define PCNT_U0_CONF0_REG (DR_REG_PCNT_BASE + 0x0)
+/** PCNT_FILTER_THRES_U0 : R/W; bitpos: [9:0]; default: 16;
+ *  This sets the maximum threshold, in APB_CLK cycles, for the filter.
+ *
+ *  Any pulses with width less than this will be ignored when the filter is enabled.
+ */
+#define PCNT_FILTER_THRES_U0    0x000003FFU
+#define PCNT_FILTER_THRES_U0_M  (PCNT_FILTER_THRES_U0_V << PCNT_FILTER_THRES_U0_S)
+#define PCNT_FILTER_THRES_U0_V  0x000003FFU
+#define PCNT_FILTER_THRES_U0_S  0
+/** PCNT_FILTER_EN_U0 : R/W; bitpos: [10]; default: 1;
+ *  This is the enable bit for unit 0's input filter.
+ */
 #define PCNT_FILTER_EN_U0    (BIT(10))
-#define PCNT_FILTER_EN_U0_M  (BIT(10))
-#define PCNT_FILTER_EN_U0_V  0x1
+#define PCNT_FILTER_EN_U0_M  (PCNT_FILTER_EN_U0_V << PCNT_FILTER_EN_U0_S)
+#define PCNT_FILTER_EN_U0_V  0x00000001U
 #define PCNT_FILTER_EN_U0_S  10
-/* PCNT_FILTER_THRES_U0 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */
-/*description: .*/
-#define PCNT_FILTER_THRES_U0    0x000003FF
-#define PCNT_FILTER_THRES_U0_M  ((PCNT_FILTER_THRES_U0_V)<<(PCNT_FILTER_THRES_U0_S))
-#define PCNT_FILTER_THRES_U0_V  0x3FF
-#define PCNT_FILTER_THRES_U0_S  0
+/** PCNT_THR_ZERO_EN_U0 : R/W; bitpos: [11]; default: 1;
+ *  This is the enable bit for unit 0's zero comparator.
+ */
+#define PCNT_THR_ZERO_EN_U0    (BIT(11))
+#define PCNT_THR_ZERO_EN_U0_M  (PCNT_THR_ZERO_EN_U0_V << PCNT_THR_ZERO_EN_U0_S)
+#define PCNT_THR_ZERO_EN_U0_V  0x00000001U
+#define PCNT_THR_ZERO_EN_U0_S  11
+/** PCNT_THR_H_LIM_EN_U0 : R/W; bitpos: [12]; default: 1;
+ *  This is the enable bit for unit 0's thr_h_lim comparator.
+ */
+#define PCNT_THR_H_LIM_EN_U0    (BIT(12))
+#define PCNT_THR_H_LIM_EN_U0_M  (PCNT_THR_H_LIM_EN_U0_V << PCNT_THR_H_LIM_EN_U0_S)
+#define PCNT_THR_H_LIM_EN_U0_V  0x00000001U
+#define PCNT_THR_H_LIM_EN_U0_S  12
+/** PCNT_THR_L_LIM_EN_U0 : R/W; bitpos: [13]; default: 1;
+ *  This is the enable bit for unit 0's thr_l_lim comparator.
+ */
+#define PCNT_THR_L_LIM_EN_U0    (BIT(13))
+#define PCNT_THR_L_LIM_EN_U0_M  (PCNT_THR_L_LIM_EN_U0_V << PCNT_THR_L_LIM_EN_U0_S)
+#define PCNT_THR_L_LIM_EN_U0_V  0x00000001U
+#define PCNT_THR_L_LIM_EN_U0_S  13
+/** PCNT_THR_THRES0_EN_U0 : R/W; bitpos: [14]; default: 0;
+ *  This is the enable bit for unit 0's thres0 comparator.
+ */
+#define PCNT_THR_THRES0_EN_U0    (BIT(14))
+#define PCNT_THR_THRES0_EN_U0_M  (PCNT_THR_THRES0_EN_U0_V << PCNT_THR_THRES0_EN_U0_S)
+#define PCNT_THR_THRES0_EN_U0_V  0x00000001U
+#define PCNT_THR_THRES0_EN_U0_S  14
+/** PCNT_THR_THRES1_EN_U0 : R/W; bitpos: [15]; default: 0;
+ *  This is the enable bit for unit 0's thres1 comparator.
+ */
+#define PCNT_THR_THRES1_EN_U0    (BIT(15))
+#define PCNT_THR_THRES1_EN_U0_M  (PCNT_THR_THRES1_EN_U0_V << PCNT_THR_THRES1_EN_U0_S)
+#define PCNT_THR_THRES1_EN_U0_V  0x00000001U
+#define PCNT_THR_THRES1_EN_U0_S  15
+/** PCNT_CH0_NEG_MODE_U0 : R/W; bitpos: [17:16]; default: 0;
+ *  This register sets the behavior when the signal input of channel 0 detects a
+ *  negative edge.
+ *
+ *  1: Increase the counter;2: Decrease the counter;0, 3: No effect on counter
+ */
+#define PCNT_CH0_NEG_MODE_U0    0x00000003U
+#define PCNT_CH0_NEG_MODE_U0_M  (PCNT_CH0_NEG_MODE_U0_V << PCNT_CH0_NEG_MODE_U0_S)
+#define PCNT_CH0_NEG_MODE_U0_V  0x00000003U
+#define PCNT_CH0_NEG_MODE_U0_S  16
+/** PCNT_CH0_POS_MODE_U0 : R/W; bitpos: [19:18]; default: 0;
+ *  This register sets the behavior when the signal input of channel 0 detects a
+ *  positive edge.
+ *
+ *  1: Increase the counter;2: Decrease the counter;0, 3: No effect on counter
+ */
+#define PCNT_CH0_POS_MODE_U0    0x00000003U
+#define PCNT_CH0_POS_MODE_U0_M  (PCNT_CH0_POS_MODE_U0_V << PCNT_CH0_POS_MODE_U0_S)
+#define PCNT_CH0_POS_MODE_U0_V  0x00000003U
+#define PCNT_CH0_POS_MODE_U0_S  18
+/** PCNT_CH0_HCTRL_MODE_U0 : R/W; bitpos: [21:20]; default: 0;
+ *  This register configures how the CH0_POS_MODE/CH0_NEG_MODE settings will be
+ *  modified when the control signal is high.
+ *
+ *  0: No modification;1: Invert behavior (increase -> decrease, decrease ->
+ *  increase);2, 3: Inhibit counter modification
+ */
+#define PCNT_CH0_HCTRL_MODE_U0    0x00000003U
+#define PCNT_CH0_HCTRL_MODE_U0_M  (PCNT_CH0_HCTRL_MODE_U0_V << PCNT_CH0_HCTRL_MODE_U0_S)
+#define PCNT_CH0_HCTRL_MODE_U0_V  0x00000003U
+#define PCNT_CH0_HCTRL_MODE_U0_S  20
+/** PCNT_CH0_LCTRL_MODE_U0 : R/W; bitpos: [23:22]; default: 0;
+ *  This register configures how the CH0_POS_MODE/CH0_NEG_MODE settings will be
+ *  modified when the control signal is low.
+ *
+ *  0: No modification;1: Invert behavior (increase -> decrease, decrease ->
+ *  increase);2, 3: Inhibit counter modification
+ */
+#define PCNT_CH0_LCTRL_MODE_U0    0x00000003U
+#define PCNT_CH0_LCTRL_MODE_U0_M  (PCNT_CH0_LCTRL_MODE_U0_V << PCNT_CH0_LCTRL_MODE_U0_S)
+#define PCNT_CH0_LCTRL_MODE_U0_V  0x00000003U
+#define PCNT_CH0_LCTRL_MODE_U0_S  22
+/** PCNT_CH1_NEG_MODE_U0 : R/W; bitpos: [25:24]; default: 0;
+ *  This register sets the behavior when the signal input of channel 1 detects a
+ *  negative edge.
+ *
+ *  1: Increment the counter;2: Decrement the counter;0, 3: No effect on counter
+ */
+#define PCNT_CH1_NEG_MODE_U0    0x00000003U
+#define PCNT_CH1_NEG_MODE_U0_M  (PCNT_CH1_NEG_MODE_U0_V << PCNT_CH1_NEG_MODE_U0_S)
+#define PCNT_CH1_NEG_MODE_U0_V  0x00000003U
+#define PCNT_CH1_NEG_MODE_U0_S  24
+/** PCNT_CH1_POS_MODE_U0 : R/W; bitpos: [27:26]; default: 0;
+ *  This register sets the behavior when the signal input of channel 1 detects a
+ *  positive edge.
+ *
+ *  1: Increment the counter;2: Decrement the counter;0, 3: No effect on counter
+ */
+#define PCNT_CH1_POS_MODE_U0    0x00000003U
+#define PCNT_CH1_POS_MODE_U0_M  (PCNT_CH1_POS_MODE_U0_V << PCNT_CH1_POS_MODE_U0_S)
+#define PCNT_CH1_POS_MODE_U0_V  0x00000003U
+#define PCNT_CH1_POS_MODE_U0_S  26
+/** PCNT_CH1_HCTRL_MODE_U0 : R/W; bitpos: [29:28]; default: 0;
+ *  This register configures how the CH0_POS_MODE/CH0_NEG_MODE settings will be
+ *  modified when the control signal is high.
+ *
+ *  0: No modification;1: Invert behavior (increase -> decrease, decrease ->
+ *  increase);2, 3: Inhibit counter modification
+ */
+#define PCNT_CH1_HCTRL_MODE_U0    0x00000003U
+#define PCNT_CH1_HCTRL_MODE_U0_M  (PCNT_CH1_HCTRL_MODE_U0_V << PCNT_CH1_HCTRL_MODE_U0_S)
+#define PCNT_CH1_HCTRL_MODE_U0_V  0x00000003U
+#define PCNT_CH1_HCTRL_MODE_U0_S  28
+/** PCNT_CH1_LCTRL_MODE_U0 : R/W; bitpos: [31:30]; default: 0;
+ *  This register configures how the CH0_POS_MODE/CH0_NEG_MODE settings will be
+ *  modified when the control signal is low.
+ *
+ *  0: No modification;1: Invert behavior (increase -> decrease, decrease ->
+ *  increase);2, 3: Inhibit counter modification
+ */
+#define PCNT_CH1_LCTRL_MODE_U0    0x00000003U
+#define PCNT_CH1_LCTRL_MODE_U0_M  (PCNT_CH1_LCTRL_MODE_U0_V << PCNT_CH1_LCTRL_MODE_U0_S)
+#define PCNT_CH1_LCTRL_MODE_U0_V  0x00000003U
+#define PCNT_CH1_LCTRL_MODE_U0_S  30
 
-#define PCNT_U0_CONF1_REG          (DR_REG_PCNT_BASE + 0x4)
-/* PCNT_CNT_THRES1_U0 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */
-/*description: .*/
-#define PCNT_CNT_THRES1_U0    0x0000FFFF
-#define PCNT_CNT_THRES1_U0_M  ((PCNT_CNT_THRES1_U0_V)<<(PCNT_CNT_THRES1_U0_S))
-#define PCNT_CNT_THRES1_U0_V  0xFFFF
-#define PCNT_CNT_THRES1_U0_S  16
-/* PCNT_CNT_THRES0_U0 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */
-/*description: .*/
-#define PCNT_CNT_THRES0_U0    0x0000FFFF
-#define PCNT_CNT_THRES0_U0_M  ((PCNT_CNT_THRES0_U0_V)<<(PCNT_CNT_THRES0_U0_S))
-#define PCNT_CNT_THRES0_U0_V  0xFFFF
+/** PCNT_U0_CONF1_REG register
+ *  Configuration register 1 for unit 0
+ */
+#define PCNT_U0_CONF1_REG (DR_REG_PCNT_BASE + 0x4)
+/** PCNT_CNT_THRES0_U0 : R/W; bitpos: [15:0]; default: 0;
+ *  This register is used to configure the thres0 value for unit 0.
+ */
+#define PCNT_CNT_THRES0_U0    0x0000FFFFU
+#define PCNT_CNT_THRES0_U0_M  (PCNT_CNT_THRES0_U0_V << PCNT_CNT_THRES0_U0_S)
+#define PCNT_CNT_THRES0_U0_V  0x0000FFFFU
 #define PCNT_CNT_THRES0_U0_S  0
+/** PCNT_CNT_THRES1_U0 : R/W; bitpos: [31:16]; default: 0;
+ *  This register is used to configure the thres1 value for unit 0.
+ */
+#define PCNT_CNT_THRES1_U0    0x0000FFFFU
+#define PCNT_CNT_THRES1_U0_M  (PCNT_CNT_THRES1_U0_V << PCNT_CNT_THRES1_U0_S)
+#define PCNT_CNT_THRES1_U0_V  0x0000FFFFU
+#define PCNT_CNT_THRES1_U0_S  16
 
-#define PCNT_U0_CONF2_REG          (DR_REG_PCNT_BASE + 0x8)
-/* PCNT_CNT_L_LIM_U0 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */
-/*description: .*/
-#define PCNT_CNT_L_LIM_U0    0x0000FFFF
-#define PCNT_CNT_L_LIM_U0_M  ((PCNT_CNT_L_LIM_U0_V)<<(PCNT_CNT_L_LIM_U0_S))
-#define PCNT_CNT_L_LIM_U0_V  0xFFFF
-#define PCNT_CNT_L_LIM_U0_S  16
-/* PCNT_CNT_H_LIM_U0 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */
-/*description: .*/
-#define PCNT_CNT_H_LIM_U0    0x0000FFFF
-#define PCNT_CNT_H_LIM_U0_M  ((PCNT_CNT_H_LIM_U0_V)<<(PCNT_CNT_H_LIM_U0_S))
-#define PCNT_CNT_H_LIM_U0_V  0xFFFF
+/** PCNT_U0_CONF2_REG register
+ *  Configuration register 2 for unit 0
+ */
+#define PCNT_U0_CONF2_REG (DR_REG_PCNT_BASE + 0x8)
+/** PCNT_CNT_H_LIM_U0 : R/W; bitpos: [15:0]; default: 0;
+ *  This register is used to configure the thr_h_lim value for unit 0.
+ */
+#define PCNT_CNT_H_LIM_U0    0x0000FFFFU
+#define PCNT_CNT_H_LIM_U0_M  (PCNT_CNT_H_LIM_U0_V << PCNT_CNT_H_LIM_U0_S)
+#define PCNT_CNT_H_LIM_U0_V  0x0000FFFFU
 #define PCNT_CNT_H_LIM_U0_S  0
+/** PCNT_CNT_L_LIM_U0 : R/W; bitpos: [31:16]; default: 0;
+ *  This register is used to configure the thr_l_lim value for unit 0.
+ */
+#define PCNT_CNT_L_LIM_U0    0x0000FFFFU
+#define PCNT_CNT_L_LIM_U0_M  (PCNT_CNT_L_LIM_U0_V << PCNT_CNT_L_LIM_U0_S)
+#define PCNT_CNT_L_LIM_U0_V  0x0000FFFFU
+#define PCNT_CNT_L_LIM_U0_S  16
 
-#define PCNT_U1_CONF0_REG          (DR_REG_PCNT_BASE + 0xC)
-/* PCNT_CH1_LCTRL_MODE_U1 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */
-/*description: .*/
-#define PCNT_CH1_LCTRL_MODE_U1    0x00000003
-#define PCNT_CH1_LCTRL_MODE_U1_M  ((PCNT_CH1_LCTRL_MODE_U1_V)<<(PCNT_CH1_LCTRL_MODE_U1_S))
-#define PCNT_CH1_LCTRL_MODE_U1_V  0x3
-#define PCNT_CH1_LCTRL_MODE_U1_S  30
-/* PCNT_CH1_HCTRL_MODE_U1 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */
-/*description: .*/
-#define PCNT_CH1_HCTRL_MODE_U1    0x00000003
-#define PCNT_CH1_HCTRL_MODE_U1_M  ((PCNT_CH1_HCTRL_MODE_U1_V)<<(PCNT_CH1_HCTRL_MODE_U1_S))
-#define PCNT_CH1_HCTRL_MODE_U1_V  0x3
-#define PCNT_CH1_HCTRL_MODE_U1_S  28
-/* PCNT_CH1_POS_MODE_U1 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */
-/*description: .*/
-#define PCNT_CH1_POS_MODE_U1    0x00000003
-#define PCNT_CH1_POS_MODE_U1_M  ((PCNT_CH1_POS_MODE_U1_V)<<(PCNT_CH1_POS_MODE_U1_S))
-#define PCNT_CH1_POS_MODE_U1_V  0x3
-#define PCNT_CH1_POS_MODE_U1_S  26
-/* PCNT_CH1_NEG_MODE_U1 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */
-/*description: .*/
-#define PCNT_CH1_NEG_MODE_U1    0x00000003
-#define PCNT_CH1_NEG_MODE_U1_M  ((PCNT_CH1_NEG_MODE_U1_V)<<(PCNT_CH1_NEG_MODE_U1_S))
-#define PCNT_CH1_NEG_MODE_U1_V  0x3
-#define PCNT_CH1_NEG_MODE_U1_S  24
-/* PCNT_CH0_LCTRL_MODE_U1 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */
-/*description: .*/
-#define PCNT_CH0_LCTRL_MODE_U1    0x00000003
-#define PCNT_CH0_LCTRL_MODE_U1_M  ((PCNT_CH0_LCTRL_MODE_U1_V)<<(PCNT_CH0_LCTRL_MODE_U1_S))
-#define PCNT_CH0_LCTRL_MODE_U1_V  0x3
-#define PCNT_CH0_LCTRL_MODE_U1_S  22
-/* PCNT_CH0_HCTRL_MODE_U1 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */
-/*description: .*/
-#define PCNT_CH0_HCTRL_MODE_U1    0x00000003
-#define PCNT_CH0_HCTRL_MODE_U1_M  ((PCNT_CH0_HCTRL_MODE_U1_V)<<(PCNT_CH0_HCTRL_MODE_U1_S))
-#define PCNT_CH0_HCTRL_MODE_U1_V  0x3
-#define PCNT_CH0_HCTRL_MODE_U1_S  20
-/* PCNT_CH0_POS_MODE_U1 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */
-/*description: .*/
-#define PCNT_CH0_POS_MODE_U1    0x00000003
-#define PCNT_CH0_POS_MODE_U1_M  ((PCNT_CH0_POS_MODE_U1_V)<<(PCNT_CH0_POS_MODE_U1_S))
-#define PCNT_CH0_POS_MODE_U1_V  0x3
-#define PCNT_CH0_POS_MODE_U1_S  18
-/* PCNT_CH0_NEG_MODE_U1 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */
-/*description: .*/
-#define PCNT_CH0_NEG_MODE_U1    0x00000003
-#define PCNT_CH0_NEG_MODE_U1_M  ((PCNT_CH0_NEG_MODE_U1_V)<<(PCNT_CH0_NEG_MODE_U1_S))
-#define PCNT_CH0_NEG_MODE_U1_V  0x3
-#define PCNT_CH0_NEG_MODE_U1_S  16
-/* PCNT_THR_THRES1_EN_U1 : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: .*/
-#define PCNT_THR_THRES1_EN_U1    (BIT(15))
-#define PCNT_THR_THRES1_EN_U1_M  (BIT(15))
-#define PCNT_THR_THRES1_EN_U1_V  0x1
-#define PCNT_THR_THRES1_EN_U1_S  15
-/* PCNT_THR_THRES0_EN_U1 : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: .*/
-#define PCNT_THR_THRES0_EN_U1    (BIT(14))
-#define PCNT_THR_THRES0_EN_U1_M  (BIT(14))
-#define PCNT_THR_THRES0_EN_U1_V  0x1
-#define PCNT_THR_THRES0_EN_U1_S  14
-/* PCNT_THR_L_LIM_EN_U1 : R/W ;bitpos:[13] ;default: 1'b1 ; */
-/*description: .*/
-#define PCNT_THR_L_LIM_EN_U1    (BIT(13))
-#define PCNT_THR_L_LIM_EN_U1_M  (BIT(13))
-#define PCNT_THR_L_LIM_EN_U1_V  0x1
-#define PCNT_THR_L_LIM_EN_U1_S  13
-/* PCNT_THR_H_LIM_EN_U1 : R/W ;bitpos:[12] ;default: 1'b1 ; */
-/*description: .*/
-#define PCNT_THR_H_LIM_EN_U1    (BIT(12))
-#define PCNT_THR_H_LIM_EN_U1_M  (BIT(12))
-#define PCNT_THR_H_LIM_EN_U1_V  0x1
-#define PCNT_THR_H_LIM_EN_U1_S  12
-/* PCNT_THR_ZERO_EN_U1 : R/W ;bitpos:[11] ;default: 1'b1 ; */
-/*description: .*/
-#define PCNT_THR_ZERO_EN_U1    (BIT(11))
-#define PCNT_THR_ZERO_EN_U1_M  (BIT(11))
-#define PCNT_THR_ZERO_EN_U1_V  0x1
-#define PCNT_THR_ZERO_EN_U1_S  11
-/* PCNT_FILTER_EN_U1 : R/W ;bitpos:[10] ;default: 1'b1 ; */
-/*description: .*/
+/** PCNT_U1_CONF0_REG register
+ *  Configuration register 0 for unit 1
+ */
+#define PCNT_U1_CONF0_REG (DR_REG_PCNT_BASE + 0xc)
+/** PCNT_FILTER_THRES_U1 : R/W; bitpos: [9:0]; default: 16;
+ *  This sets the maximum threshold, in APB_CLK cycles, for the filter.
+ *
+ *  Any pulses with width less than this will be ignored when the filter is enabled.
+ */
+#define PCNT_FILTER_THRES_U1    0x000003FFU
+#define PCNT_FILTER_THRES_U1_M  (PCNT_FILTER_THRES_U1_V << PCNT_FILTER_THRES_U1_S)
+#define PCNT_FILTER_THRES_U1_V  0x000003FFU
+#define PCNT_FILTER_THRES_U1_S  0
+/** PCNT_FILTER_EN_U1 : R/W; bitpos: [10]; default: 1;
+ *  This is the enable bit for unit 1's input filter.
+ */
 #define PCNT_FILTER_EN_U1    (BIT(10))
-#define PCNT_FILTER_EN_U1_M  (BIT(10))
-#define PCNT_FILTER_EN_U1_V  0x1
+#define PCNT_FILTER_EN_U1_M  (PCNT_FILTER_EN_U1_V << PCNT_FILTER_EN_U1_S)
+#define PCNT_FILTER_EN_U1_V  0x00000001U
 #define PCNT_FILTER_EN_U1_S  10
-/* PCNT_FILTER_THRES_U1 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */
-/*description: .*/
-#define PCNT_FILTER_THRES_U1    0x000003FF
-#define PCNT_FILTER_THRES_U1_M  ((PCNT_FILTER_THRES_U1_V)<<(PCNT_FILTER_THRES_U1_S))
-#define PCNT_FILTER_THRES_U1_V  0x3FF
-#define PCNT_FILTER_THRES_U1_S  0
+/** PCNT_THR_ZERO_EN_U1 : R/W; bitpos: [11]; default: 1;
+ *  This is the enable bit for unit 1's zero comparator.
+ */
+#define PCNT_THR_ZERO_EN_U1    (BIT(11))
+#define PCNT_THR_ZERO_EN_U1_M  (PCNT_THR_ZERO_EN_U1_V << PCNT_THR_ZERO_EN_U1_S)
+#define PCNT_THR_ZERO_EN_U1_V  0x00000001U
+#define PCNT_THR_ZERO_EN_U1_S  11
+/** PCNT_THR_H_LIM_EN_U1 : R/W; bitpos: [12]; default: 1;
+ *  This is the enable bit for unit 1's thr_h_lim comparator.
+ */
+#define PCNT_THR_H_LIM_EN_U1    (BIT(12))
+#define PCNT_THR_H_LIM_EN_U1_M  (PCNT_THR_H_LIM_EN_U1_V << PCNT_THR_H_LIM_EN_U1_S)
+#define PCNT_THR_H_LIM_EN_U1_V  0x00000001U
+#define PCNT_THR_H_LIM_EN_U1_S  12
+/** PCNT_THR_L_LIM_EN_U1 : R/W; bitpos: [13]; default: 1;
+ *  This is the enable bit for unit 1's thr_l_lim comparator.
+ */
+#define PCNT_THR_L_LIM_EN_U1    (BIT(13))
+#define PCNT_THR_L_LIM_EN_U1_M  (PCNT_THR_L_LIM_EN_U1_V << PCNT_THR_L_LIM_EN_U1_S)
+#define PCNT_THR_L_LIM_EN_U1_V  0x00000001U
+#define PCNT_THR_L_LIM_EN_U1_S  13
+/** PCNT_THR_THRES0_EN_U1 : R/W; bitpos: [14]; default: 0;
+ *  This is the enable bit for unit 1's thres0 comparator.
+ */
+#define PCNT_THR_THRES0_EN_U1    (BIT(14))
+#define PCNT_THR_THRES0_EN_U1_M  (PCNT_THR_THRES0_EN_U1_V << PCNT_THR_THRES0_EN_U1_S)
+#define PCNT_THR_THRES0_EN_U1_V  0x00000001U
+#define PCNT_THR_THRES0_EN_U1_S  14
+/** PCNT_THR_THRES1_EN_U1 : R/W; bitpos: [15]; default: 0;
+ *  This is the enable bit for unit 1's thres1 comparator.
+ */
+#define PCNT_THR_THRES1_EN_U1    (BIT(15))
+#define PCNT_THR_THRES1_EN_U1_M  (PCNT_THR_THRES1_EN_U1_V << PCNT_THR_THRES1_EN_U1_S)
+#define PCNT_THR_THRES1_EN_U1_V  0x00000001U
+#define PCNT_THR_THRES1_EN_U1_S  15
+/** PCNT_CH0_NEG_MODE_U1 : R/W; bitpos: [17:16]; default: 0;
+ *  This register sets the behavior when the signal input of channel 0 detects a
+ *  negative edge.
+ *
+ *  1: Increase the counter;2: Decrease the counter;0, 3: No effect on counter
+ */
+#define PCNT_CH0_NEG_MODE_U1    0x00000003U
+#define PCNT_CH0_NEG_MODE_U1_M  (PCNT_CH0_NEG_MODE_U1_V << PCNT_CH0_NEG_MODE_U1_S)
+#define PCNT_CH0_NEG_MODE_U1_V  0x00000003U
+#define PCNT_CH0_NEG_MODE_U1_S  16
+/** PCNT_CH0_POS_MODE_U1 : R/W; bitpos: [19:18]; default: 0;
+ *  This register sets the behavior when the signal input of channel 0 detects a
+ *  positive edge.
+ *
+ *  1: Increase the counter;2: Decrease the counter;0, 3: No effect on counter
+ */
+#define PCNT_CH0_POS_MODE_U1    0x00000003U
+#define PCNT_CH0_POS_MODE_U1_M  (PCNT_CH0_POS_MODE_U1_V << PCNT_CH0_POS_MODE_U1_S)
+#define PCNT_CH0_POS_MODE_U1_V  0x00000003U
+#define PCNT_CH0_POS_MODE_U1_S  18
+/** PCNT_CH0_HCTRL_MODE_U1 : R/W; bitpos: [21:20]; default: 0;
+ *  This register configures how the CH1_POS_MODE/CH1_NEG_MODE settings will be
+ *  modified when the control signal is high.
+ *
+ *  0: No modification;1: Invert behavior (increase -> decrease, decrease ->
+ *  increase);2, 3: Inhibit counter modification
+ */
+#define PCNT_CH0_HCTRL_MODE_U1    0x00000003U
+#define PCNT_CH0_HCTRL_MODE_U1_M  (PCNT_CH0_HCTRL_MODE_U1_V << PCNT_CH0_HCTRL_MODE_U1_S)
+#define PCNT_CH0_HCTRL_MODE_U1_V  0x00000003U
+#define PCNT_CH0_HCTRL_MODE_U1_S  20
+/** PCNT_CH0_LCTRL_MODE_U1 : R/W; bitpos: [23:22]; default: 0;
+ *  This register configures how the CH1_POS_MODE/CH1_NEG_MODE settings will be
+ *  modified when the control signal is low.
+ *
+ *  0: No modification;1: Invert behavior (increase -> decrease, decrease ->
+ *  increase);2, 3: Inhibit counter modification
+ */
+#define PCNT_CH0_LCTRL_MODE_U1    0x00000003U
+#define PCNT_CH0_LCTRL_MODE_U1_M  (PCNT_CH0_LCTRL_MODE_U1_V << PCNT_CH0_LCTRL_MODE_U1_S)
+#define PCNT_CH0_LCTRL_MODE_U1_V  0x00000003U
+#define PCNT_CH0_LCTRL_MODE_U1_S  22
+/** PCNT_CH1_NEG_MODE_U1 : R/W; bitpos: [25:24]; default: 0;
+ *  This register sets the behavior when the signal input of channel 1 detects a
+ *  negative edge.
+ *
+ *  1: Increment the counter;2: Decrement the counter;0, 3: No effect on counter
+ */
+#define PCNT_CH1_NEG_MODE_U1    0x00000003U
+#define PCNT_CH1_NEG_MODE_U1_M  (PCNT_CH1_NEG_MODE_U1_V << PCNT_CH1_NEG_MODE_U1_S)
+#define PCNT_CH1_NEG_MODE_U1_V  0x00000003U
+#define PCNT_CH1_NEG_MODE_U1_S  24
+/** PCNT_CH1_POS_MODE_U1 : R/W; bitpos: [27:26]; default: 0;
+ *  This register sets the behavior when the signal input of channel 1 detects a
+ *  positive edge.
+ *
+ *  1: Increment the counter;2: Decrement the counter;0, 3: No effect on counter
+ */
+#define PCNT_CH1_POS_MODE_U1    0x00000003U
+#define PCNT_CH1_POS_MODE_U1_M  (PCNT_CH1_POS_MODE_U1_V << PCNT_CH1_POS_MODE_U1_S)
+#define PCNT_CH1_POS_MODE_U1_V  0x00000003U
+#define PCNT_CH1_POS_MODE_U1_S  26
+/** PCNT_CH1_HCTRL_MODE_U1 : R/W; bitpos: [29:28]; default: 0;
+ *  This register configures how the CH1_POS_MODE/CH1_NEG_MODE settings will be
+ *  modified when the control signal is high.
+ *
+ *  0: No modification;1: Invert behavior (increase -> decrease, decrease ->
+ *  increase);2, 3: Inhibit counter modification
+ */
+#define PCNT_CH1_HCTRL_MODE_U1    0x00000003U
+#define PCNT_CH1_HCTRL_MODE_U1_M  (PCNT_CH1_HCTRL_MODE_U1_V << PCNT_CH1_HCTRL_MODE_U1_S)
+#define PCNT_CH1_HCTRL_MODE_U1_V  0x00000003U
+#define PCNT_CH1_HCTRL_MODE_U1_S  28
+/** PCNT_CH1_LCTRL_MODE_U1 : R/W; bitpos: [31:30]; default: 0;
+ *  This register configures how the CH1_POS_MODE/CH1_NEG_MODE settings will be
+ *  modified when the control signal is low.
+ *
+ *  0: No modification;1: Invert behavior (increase -> decrease, decrease ->
+ *  increase);2, 3: Inhibit counter modification
+ */
+#define PCNT_CH1_LCTRL_MODE_U1    0x00000003U
+#define PCNT_CH1_LCTRL_MODE_U1_M  (PCNT_CH1_LCTRL_MODE_U1_V << PCNT_CH1_LCTRL_MODE_U1_S)
+#define PCNT_CH1_LCTRL_MODE_U1_V  0x00000003U
+#define PCNT_CH1_LCTRL_MODE_U1_S  30
 
-#define PCNT_U1_CONF1_REG          (DR_REG_PCNT_BASE + 0x10)
-/* PCNT_CNT_THRES1_U1 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */
-/*description: .*/
-#define PCNT_CNT_THRES1_U1    0x0000FFFF
-#define PCNT_CNT_THRES1_U1_M  ((PCNT_CNT_THRES1_U1_V)<<(PCNT_CNT_THRES1_U1_S))
-#define PCNT_CNT_THRES1_U1_V  0xFFFF
-#define PCNT_CNT_THRES1_U1_S  16
-/* PCNT_CNT_THRES0_U1 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */
-/*description: .*/
-#define PCNT_CNT_THRES0_U1    0x0000FFFF
-#define PCNT_CNT_THRES0_U1_M  ((PCNT_CNT_THRES0_U1_V)<<(PCNT_CNT_THRES0_U1_S))
-#define PCNT_CNT_THRES0_U1_V  0xFFFF
+/** PCNT_U1_CONF1_REG register
+ *  Configuration register 1 for unit 1
+ */
+#define PCNT_U1_CONF1_REG (DR_REG_PCNT_BASE + 0x10)
+/** PCNT_CNT_THRES0_U1 : R/W; bitpos: [15:0]; default: 0;
+ *  This register is used to configure the thres0 value for unit 1.
+ */
+#define PCNT_CNT_THRES0_U1    0x0000FFFFU
+#define PCNT_CNT_THRES0_U1_M  (PCNT_CNT_THRES0_U1_V << PCNT_CNT_THRES0_U1_S)
+#define PCNT_CNT_THRES0_U1_V  0x0000FFFFU
 #define PCNT_CNT_THRES0_U1_S  0
+/** PCNT_CNT_THRES1_U1 : R/W; bitpos: [31:16]; default: 0;
+ *  This register is used to configure the thres1 value for unit 1.
+ */
+#define PCNT_CNT_THRES1_U1    0x0000FFFFU
+#define PCNT_CNT_THRES1_U1_M  (PCNT_CNT_THRES1_U1_V << PCNT_CNT_THRES1_U1_S)
+#define PCNT_CNT_THRES1_U1_V  0x0000FFFFU
+#define PCNT_CNT_THRES1_U1_S  16
 
-#define PCNT_U1_CONF2_REG          (DR_REG_PCNT_BASE + 0x14)
-/* PCNT_CNT_L_LIM_U1 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */
-/*description: .*/
-#define PCNT_CNT_L_LIM_U1    0x0000FFFF
-#define PCNT_CNT_L_LIM_U1_M  ((PCNT_CNT_L_LIM_U1_V)<<(PCNT_CNT_L_LIM_U1_S))
-#define PCNT_CNT_L_LIM_U1_V  0xFFFF
-#define PCNT_CNT_L_LIM_U1_S  16
-/* PCNT_CNT_H_LIM_U1 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */
-/*description: .*/
-#define PCNT_CNT_H_LIM_U1    0x0000FFFF
-#define PCNT_CNT_H_LIM_U1_M  ((PCNT_CNT_H_LIM_U1_V)<<(PCNT_CNT_H_LIM_U1_S))
-#define PCNT_CNT_H_LIM_U1_V  0xFFFF
+/** PCNT_U1_CONF2_REG register
+ *  Configuration register 2 for unit 1
+ */
+#define PCNT_U1_CONF2_REG (DR_REG_PCNT_BASE + 0x14)
+/** PCNT_CNT_H_LIM_U1 : R/W; bitpos: [15:0]; default: 0;
+ *  This register is used to configure the thr_h_lim value for unit 1.
+ */
+#define PCNT_CNT_H_LIM_U1    0x0000FFFFU
+#define PCNT_CNT_H_LIM_U1_M  (PCNT_CNT_H_LIM_U1_V << PCNT_CNT_H_LIM_U1_S)
+#define PCNT_CNT_H_LIM_U1_V  0x0000FFFFU
 #define PCNT_CNT_H_LIM_U1_S  0
+/** PCNT_CNT_L_LIM_U1 : R/W; bitpos: [31:16]; default: 0;
+ *  This register is used to configure the thr_l_lim value for unit 1.
+ */
+#define PCNT_CNT_L_LIM_U1    0x0000FFFFU
+#define PCNT_CNT_L_LIM_U1_M  (PCNT_CNT_L_LIM_U1_V << PCNT_CNT_L_LIM_U1_S)
+#define PCNT_CNT_L_LIM_U1_V  0x0000FFFFU
+#define PCNT_CNT_L_LIM_U1_S  16
 
-#define PCNT_U2_CONF0_REG          (DR_REG_PCNT_BASE + 0x18)
-/* PCNT_CH1_LCTRL_MODE_U2 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */
-/*description: .*/
-#define PCNT_CH1_LCTRL_MODE_U2    0x00000003
-#define PCNT_CH1_LCTRL_MODE_U2_M  ((PCNT_CH1_LCTRL_MODE_U2_V)<<(PCNT_CH1_LCTRL_MODE_U2_S))
-#define PCNT_CH1_LCTRL_MODE_U2_V  0x3
-#define PCNT_CH1_LCTRL_MODE_U2_S  30
-/* PCNT_CH1_HCTRL_MODE_U2 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */
-/*description: .*/
-#define PCNT_CH1_HCTRL_MODE_U2    0x00000003
-#define PCNT_CH1_HCTRL_MODE_U2_M  ((PCNT_CH1_HCTRL_MODE_U2_V)<<(PCNT_CH1_HCTRL_MODE_U2_S))
-#define PCNT_CH1_HCTRL_MODE_U2_V  0x3
-#define PCNT_CH1_HCTRL_MODE_U2_S  28
-/* PCNT_CH1_POS_MODE_U2 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */
-/*description: .*/
-#define PCNT_CH1_POS_MODE_U2    0x00000003
-#define PCNT_CH1_POS_MODE_U2_M  ((PCNT_CH1_POS_MODE_U2_V)<<(PCNT_CH1_POS_MODE_U2_S))
-#define PCNT_CH1_POS_MODE_U2_V  0x3
-#define PCNT_CH1_POS_MODE_U2_S  26
-/* PCNT_CH1_NEG_MODE_U2 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */
-/*description: .*/
-#define PCNT_CH1_NEG_MODE_U2    0x00000003
-#define PCNT_CH1_NEG_MODE_U2_M  ((PCNT_CH1_NEG_MODE_U2_V)<<(PCNT_CH1_NEG_MODE_U2_S))
-#define PCNT_CH1_NEG_MODE_U2_V  0x3
-#define PCNT_CH1_NEG_MODE_U2_S  24
-/* PCNT_CH0_LCTRL_MODE_U2 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */
-/*description: .*/
-#define PCNT_CH0_LCTRL_MODE_U2    0x00000003
-#define PCNT_CH0_LCTRL_MODE_U2_M  ((PCNT_CH0_LCTRL_MODE_U2_V)<<(PCNT_CH0_LCTRL_MODE_U2_S))
-#define PCNT_CH0_LCTRL_MODE_U2_V  0x3
-#define PCNT_CH0_LCTRL_MODE_U2_S  22
-/* PCNT_CH0_HCTRL_MODE_U2 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */
-/*description: .*/
-#define PCNT_CH0_HCTRL_MODE_U2    0x00000003
-#define PCNT_CH0_HCTRL_MODE_U2_M  ((PCNT_CH0_HCTRL_MODE_U2_V)<<(PCNT_CH0_HCTRL_MODE_U2_S))
-#define PCNT_CH0_HCTRL_MODE_U2_V  0x3
-#define PCNT_CH0_HCTRL_MODE_U2_S  20
-/* PCNT_CH0_POS_MODE_U2 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */
-/*description: .*/
-#define PCNT_CH0_POS_MODE_U2    0x00000003
-#define PCNT_CH0_POS_MODE_U2_M  ((PCNT_CH0_POS_MODE_U2_V)<<(PCNT_CH0_POS_MODE_U2_S))
-#define PCNT_CH0_POS_MODE_U2_V  0x3
-#define PCNT_CH0_POS_MODE_U2_S  18
-/* PCNT_CH0_NEG_MODE_U2 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */
-/*description: .*/
-#define PCNT_CH0_NEG_MODE_U2    0x00000003
-#define PCNT_CH0_NEG_MODE_U2_M  ((PCNT_CH0_NEG_MODE_U2_V)<<(PCNT_CH0_NEG_MODE_U2_S))
-#define PCNT_CH0_NEG_MODE_U2_V  0x3
-#define PCNT_CH0_NEG_MODE_U2_S  16
-/* PCNT_THR_THRES1_EN_U2 : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: .*/
-#define PCNT_THR_THRES1_EN_U2    (BIT(15))
-#define PCNT_THR_THRES1_EN_U2_M  (BIT(15))
-#define PCNT_THR_THRES1_EN_U2_V  0x1
-#define PCNT_THR_THRES1_EN_U2_S  15
-/* PCNT_THR_THRES0_EN_U2 : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: .*/
-#define PCNT_THR_THRES0_EN_U2    (BIT(14))
-#define PCNT_THR_THRES0_EN_U2_M  (BIT(14))
-#define PCNT_THR_THRES0_EN_U2_V  0x1
-#define PCNT_THR_THRES0_EN_U2_S  14
-/* PCNT_THR_L_LIM_EN_U2 : R/W ;bitpos:[13] ;default: 1'b1 ; */
-/*description: .*/
-#define PCNT_THR_L_LIM_EN_U2    (BIT(13))
-#define PCNT_THR_L_LIM_EN_U2_M  (BIT(13))
-#define PCNT_THR_L_LIM_EN_U2_V  0x1
-#define PCNT_THR_L_LIM_EN_U2_S  13
-/* PCNT_THR_H_LIM_EN_U2 : R/W ;bitpos:[12] ;default: 1'b1 ; */
-/*description: .*/
-#define PCNT_THR_H_LIM_EN_U2    (BIT(12))
-#define PCNT_THR_H_LIM_EN_U2_M  (BIT(12))
-#define PCNT_THR_H_LIM_EN_U2_V  0x1
-#define PCNT_THR_H_LIM_EN_U2_S  12
-/* PCNT_THR_ZERO_EN_U2 : R/W ;bitpos:[11] ;default: 1'b1 ; */
-/*description: .*/
-#define PCNT_THR_ZERO_EN_U2    (BIT(11))
-#define PCNT_THR_ZERO_EN_U2_M  (BIT(11))
-#define PCNT_THR_ZERO_EN_U2_V  0x1
-#define PCNT_THR_ZERO_EN_U2_S  11
-/* PCNT_FILTER_EN_U2 : R/W ;bitpos:[10] ;default: 1'b1 ; */
-/*description: .*/
+/** PCNT_U2_CONF0_REG register
+ *  Configuration register 0 for unit 2
+ */
+#define PCNT_U2_CONF0_REG (DR_REG_PCNT_BASE + 0x18)
+/** PCNT_FILTER_THRES_U2 : R/W; bitpos: [9:0]; default: 16;
+ *  This sets the maximum threshold, in APB_CLK cycles, for the filter.
+ *
+ *  Any pulses with width less than this will be ignored when the filter is enabled.
+ */
+#define PCNT_FILTER_THRES_U2    0x000003FFU
+#define PCNT_FILTER_THRES_U2_M  (PCNT_FILTER_THRES_U2_V << PCNT_FILTER_THRES_U2_S)
+#define PCNT_FILTER_THRES_U2_V  0x000003FFU
+#define PCNT_FILTER_THRES_U2_S  0
+/** PCNT_FILTER_EN_U2 : R/W; bitpos: [10]; default: 1;
+ *  This is the enable bit for unit 2's input filter.
+ */
 #define PCNT_FILTER_EN_U2    (BIT(10))
-#define PCNT_FILTER_EN_U2_M  (BIT(10))
-#define PCNT_FILTER_EN_U2_V  0x1
+#define PCNT_FILTER_EN_U2_M  (PCNT_FILTER_EN_U2_V << PCNT_FILTER_EN_U2_S)
+#define PCNT_FILTER_EN_U2_V  0x00000001U
 #define PCNT_FILTER_EN_U2_S  10
-/* PCNT_FILTER_THRES_U2 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */
-/*description: .*/
-#define PCNT_FILTER_THRES_U2    0x000003FF
-#define PCNT_FILTER_THRES_U2_M  ((PCNT_FILTER_THRES_U2_V)<<(PCNT_FILTER_THRES_U2_S))
-#define PCNT_FILTER_THRES_U2_V  0x3FF
-#define PCNT_FILTER_THRES_U2_S  0
+/** PCNT_THR_ZERO_EN_U2 : R/W; bitpos: [11]; default: 1;
+ *  This is the enable bit for unit 2's zero comparator.
+ */
+#define PCNT_THR_ZERO_EN_U2    (BIT(11))
+#define PCNT_THR_ZERO_EN_U2_M  (PCNT_THR_ZERO_EN_U2_V << PCNT_THR_ZERO_EN_U2_S)
+#define PCNT_THR_ZERO_EN_U2_V  0x00000001U
+#define PCNT_THR_ZERO_EN_U2_S  11
+/** PCNT_THR_H_LIM_EN_U2 : R/W; bitpos: [12]; default: 1;
+ *  This is the enable bit for unit 2's thr_h_lim comparator.
+ */
+#define PCNT_THR_H_LIM_EN_U2    (BIT(12))
+#define PCNT_THR_H_LIM_EN_U2_M  (PCNT_THR_H_LIM_EN_U2_V << PCNT_THR_H_LIM_EN_U2_S)
+#define PCNT_THR_H_LIM_EN_U2_V  0x00000001U
+#define PCNT_THR_H_LIM_EN_U2_S  12
+/** PCNT_THR_L_LIM_EN_U2 : R/W; bitpos: [13]; default: 1;
+ *  This is the enable bit for unit 2's thr_l_lim comparator.
+ */
+#define PCNT_THR_L_LIM_EN_U2    (BIT(13))
+#define PCNT_THR_L_LIM_EN_U2_M  (PCNT_THR_L_LIM_EN_U2_V << PCNT_THR_L_LIM_EN_U2_S)
+#define PCNT_THR_L_LIM_EN_U2_V  0x00000001U
+#define PCNT_THR_L_LIM_EN_U2_S  13
+/** PCNT_THR_THRES0_EN_U2 : R/W; bitpos: [14]; default: 0;
+ *  This is the enable bit for unit 2's thres0 comparator.
+ */
+#define PCNT_THR_THRES0_EN_U2    (BIT(14))
+#define PCNT_THR_THRES0_EN_U2_M  (PCNT_THR_THRES0_EN_U2_V << PCNT_THR_THRES0_EN_U2_S)
+#define PCNT_THR_THRES0_EN_U2_V  0x00000001U
+#define PCNT_THR_THRES0_EN_U2_S  14
+/** PCNT_THR_THRES1_EN_U2 : R/W; bitpos: [15]; default: 0;
+ *  This is the enable bit for unit 2's thres1 comparator.
+ */
+#define PCNT_THR_THRES1_EN_U2    (BIT(15))
+#define PCNT_THR_THRES1_EN_U2_M  (PCNT_THR_THRES1_EN_U2_V << PCNT_THR_THRES1_EN_U2_S)
+#define PCNT_THR_THRES1_EN_U2_V  0x00000001U
+#define PCNT_THR_THRES1_EN_U2_S  15
+/** PCNT_CH0_NEG_MODE_U2 : R/W; bitpos: [17:16]; default: 0;
+ *  This register sets the behavior when the signal input of channel 0 detects a
+ *  negative edge.
+ *
+ *  1: Increase the counter;2: Decrease the counter;0, 3: No effect on counter
+ */
+#define PCNT_CH0_NEG_MODE_U2    0x00000003U
+#define PCNT_CH0_NEG_MODE_U2_M  (PCNT_CH0_NEG_MODE_U2_V << PCNT_CH0_NEG_MODE_U2_S)
+#define PCNT_CH0_NEG_MODE_U2_V  0x00000003U
+#define PCNT_CH0_NEG_MODE_U2_S  16
+/** PCNT_CH0_POS_MODE_U2 : R/W; bitpos: [19:18]; default: 0;
+ *  This register sets the behavior when the signal input of channel 0 detects a
+ *  positive edge.
+ *
+ *  1: Increase the counter;2: Decrease the counter;0, 3: No effect on counter
+ */
+#define PCNT_CH0_POS_MODE_U2    0x00000003U
+#define PCNT_CH0_POS_MODE_U2_M  (PCNT_CH0_POS_MODE_U2_V << PCNT_CH0_POS_MODE_U2_S)
+#define PCNT_CH0_POS_MODE_U2_V  0x00000003U
+#define PCNT_CH0_POS_MODE_U2_S  18
+/** PCNT_CH0_HCTRL_MODE_U2 : R/W; bitpos: [21:20]; default: 0;
+ *  This register configures how the CH2_POS_MODE/CH2_NEG_MODE settings will be
+ *  modified when the control signal is high.
+ *
+ *  0: No modification;1: Invert behavior (increase -> decrease, decrease ->
+ *  increase);2, 3: Inhibit counter modification
+ */
+#define PCNT_CH0_HCTRL_MODE_U2    0x00000003U
+#define PCNT_CH0_HCTRL_MODE_U2_M  (PCNT_CH0_HCTRL_MODE_U2_V << PCNT_CH0_HCTRL_MODE_U2_S)
+#define PCNT_CH0_HCTRL_MODE_U2_V  0x00000003U
+#define PCNT_CH0_HCTRL_MODE_U2_S  20
+/** PCNT_CH0_LCTRL_MODE_U2 : R/W; bitpos: [23:22]; default: 0;
+ *  This register configures how the CH2_POS_MODE/CH2_NEG_MODE settings will be
+ *  modified when the control signal is low.
+ *
+ *  0: No modification;1: Invert behavior (increase -> decrease, decrease ->
+ *  increase);2, 3: Inhibit counter modification
+ */
+#define PCNT_CH0_LCTRL_MODE_U2    0x00000003U
+#define PCNT_CH0_LCTRL_MODE_U2_M  (PCNT_CH0_LCTRL_MODE_U2_V << PCNT_CH0_LCTRL_MODE_U2_S)
+#define PCNT_CH0_LCTRL_MODE_U2_V  0x00000003U
+#define PCNT_CH0_LCTRL_MODE_U2_S  22
+/** PCNT_CH1_NEG_MODE_U2 : R/W; bitpos: [25:24]; default: 0;
+ *  This register sets the behavior when the signal input of channel 1 detects a
+ *  negative edge.
+ *
+ *  1: Increment the counter;2: Decrement the counter;0, 3: No effect on counter
+ */
+#define PCNT_CH1_NEG_MODE_U2    0x00000003U
+#define PCNT_CH1_NEG_MODE_U2_M  (PCNT_CH1_NEG_MODE_U2_V << PCNT_CH1_NEG_MODE_U2_S)
+#define PCNT_CH1_NEG_MODE_U2_V  0x00000003U
+#define PCNT_CH1_NEG_MODE_U2_S  24
+/** PCNT_CH1_POS_MODE_U2 : R/W; bitpos: [27:26]; default: 0;
+ *  This register sets the behavior when the signal input of channel 1 detects a
+ *  positive edge.
+ *
+ *  1: Increment the counter;2: Decrement the counter;0, 3: No effect on counter
+ */
+#define PCNT_CH1_POS_MODE_U2    0x00000003U
+#define PCNT_CH1_POS_MODE_U2_M  (PCNT_CH1_POS_MODE_U2_V << PCNT_CH1_POS_MODE_U2_S)
+#define PCNT_CH1_POS_MODE_U2_V  0x00000003U
+#define PCNT_CH1_POS_MODE_U2_S  26
+/** PCNT_CH1_HCTRL_MODE_U2 : R/W; bitpos: [29:28]; default: 0;
+ *  This register configures how the CH2_POS_MODE/CH2_NEG_MODE settings will be
+ *  modified when the control signal is high.
+ *
+ *  0: No modification;1: Invert behavior (increase -> decrease, decrease ->
+ *  increase);2, 3: Inhibit counter modification
+ */
+#define PCNT_CH1_HCTRL_MODE_U2    0x00000003U
+#define PCNT_CH1_HCTRL_MODE_U2_M  (PCNT_CH1_HCTRL_MODE_U2_V << PCNT_CH1_HCTRL_MODE_U2_S)
+#define PCNT_CH1_HCTRL_MODE_U2_V  0x00000003U
+#define PCNT_CH1_HCTRL_MODE_U2_S  28
+/** PCNT_CH1_LCTRL_MODE_U2 : R/W; bitpos: [31:30]; default: 0;
+ *  This register configures how the CH2_POS_MODE/CH2_NEG_MODE settings will be
+ *  modified when the control signal is low.
+ *
+ *  0: No modification;1: Invert behavior (increase -> decrease, decrease ->
+ *  increase);2, 3: Inhibit counter modification
+ */
+#define PCNT_CH1_LCTRL_MODE_U2    0x00000003U
+#define PCNT_CH1_LCTRL_MODE_U2_M  (PCNT_CH1_LCTRL_MODE_U2_V << PCNT_CH1_LCTRL_MODE_U2_S)
+#define PCNT_CH1_LCTRL_MODE_U2_V  0x00000003U
+#define PCNT_CH1_LCTRL_MODE_U2_S  30
 
-#define PCNT_U2_CONF1_REG          (DR_REG_PCNT_BASE + 0x1C)
-/* PCNT_CNT_THRES1_U2 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */
-/*description: .*/
-#define PCNT_CNT_THRES1_U2    0x0000FFFF
-#define PCNT_CNT_THRES1_U2_M  ((PCNT_CNT_THRES1_U2_V)<<(PCNT_CNT_THRES1_U2_S))
-#define PCNT_CNT_THRES1_U2_V  0xFFFF
-#define PCNT_CNT_THRES1_U2_S  16
-/* PCNT_CNT_THRES0_U2 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */
-/*description: .*/
-#define PCNT_CNT_THRES0_U2    0x0000FFFF
-#define PCNT_CNT_THRES0_U2_M  ((PCNT_CNT_THRES0_U2_V)<<(PCNT_CNT_THRES0_U2_S))
-#define PCNT_CNT_THRES0_U2_V  0xFFFF
+/** PCNT_U2_CONF1_REG register
+ *  Configuration register 1 for unit 2
+ */
+#define PCNT_U2_CONF1_REG (DR_REG_PCNT_BASE + 0x1c)
+/** PCNT_CNT_THRES0_U2 : R/W; bitpos: [15:0]; default: 0;
+ *  This register is used to configure the thres0 value for unit 2.
+ */
+#define PCNT_CNT_THRES0_U2    0x0000FFFFU
+#define PCNT_CNT_THRES0_U2_M  (PCNT_CNT_THRES0_U2_V << PCNT_CNT_THRES0_U2_S)
+#define PCNT_CNT_THRES0_U2_V  0x0000FFFFU
 #define PCNT_CNT_THRES0_U2_S  0
+/** PCNT_CNT_THRES1_U2 : R/W; bitpos: [31:16]; default: 0;
+ *  This register is used to configure the thres1 value for unit 2.
+ */
+#define PCNT_CNT_THRES1_U2    0x0000FFFFU
+#define PCNT_CNT_THRES1_U2_M  (PCNT_CNT_THRES1_U2_V << PCNT_CNT_THRES1_U2_S)
+#define PCNT_CNT_THRES1_U2_V  0x0000FFFFU
+#define PCNT_CNT_THRES1_U2_S  16
 
-#define PCNT_U2_CONF2_REG          (DR_REG_PCNT_BASE + 0x20)
-/* PCNT_CNT_L_LIM_U2 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */
-/*description: .*/
-#define PCNT_CNT_L_LIM_U2    0x0000FFFF
-#define PCNT_CNT_L_LIM_U2_M  ((PCNT_CNT_L_LIM_U2_V)<<(PCNT_CNT_L_LIM_U2_S))
-#define PCNT_CNT_L_LIM_U2_V  0xFFFF
-#define PCNT_CNT_L_LIM_U2_S  16
-/* PCNT_CNT_H_LIM_U2 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */
-/*description: .*/
-#define PCNT_CNT_H_LIM_U2    0x0000FFFF
-#define PCNT_CNT_H_LIM_U2_M  ((PCNT_CNT_H_LIM_U2_V)<<(PCNT_CNT_H_LIM_U2_S))
-#define PCNT_CNT_H_LIM_U2_V  0xFFFF
+/** PCNT_U2_CONF2_REG register
+ *  Configuration register 2 for unit 2
+ */
+#define PCNT_U2_CONF2_REG (DR_REG_PCNT_BASE + 0x20)
+/** PCNT_CNT_H_LIM_U2 : R/W; bitpos: [15:0]; default: 0;
+ *  This register is used to configure the thr_h_lim value for unit 2.
+ */
+#define PCNT_CNT_H_LIM_U2    0x0000FFFFU
+#define PCNT_CNT_H_LIM_U2_M  (PCNT_CNT_H_LIM_U2_V << PCNT_CNT_H_LIM_U2_S)
+#define PCNT_CNT_H_LIM_U2_V  0x0000FFFFU
 #define PCNT_CNT_H_LIM_U2_S  0
+/** PCNT_CNT_L_LIM_U2 : R/W; bitpos: [31:16]; default: 0;
+ *  This register is used to configure the thr_l_lim value for unit 2.
+ */
+#define PCNT_CNT_L_LIM_U2    0x0000FFFFU
+#define PCNT_CNT_L_LIM_U2_M  (PCNT_CNT_L_LIM_U2_V << PCNT_CNT_L_LIM_U2_S)
+#define PCNT_CNT_L_LIM_U2_V  0x0000FFFFU
+#define PCNT_CNT_L_LIM_U2_S  16
 
-#define PCNT_U3_CONF0_REG          (DR_REG_PCNT_BASE + 0x24)
-/* PCNT_CH1_LCTRL_MODE_U3 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */
-/*description: .*/
-#define PCNT_CH1_LCTRL_MODE_U3    0x00000003
-#define PCNT_CH1_LCTRL_MODE_U3_M  ((PCNT_CH1_LCTRL_MODE_U3_V)<<(PCNT_CH1_LCTRL_MODE_U3_S))
-#define PCNT_CH1_LCTRL_MODE_U3_V  0x3
-#define PCNT_CH1_LCTRL_MODE_U3_S  30
-/* PCNT_CH1_HCTRL_MODE_U3 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */
-/*description: .*/
-#define PCNT_CH1_HCTRL_MODE_U3    0x00000003
-#define PCNT_CH1_HCTRL_MODE_U3_M  ((PCNT_CH1_HCTRL_MODE_U3_V)<<(PCNT_CH1_HCTRL_MODE_U3_S))
-#define PCNT_CH1_HCTRL_MODE_U3_V  0x3
-#define PCNT_CH1_HCTRL_MODE_U3_S  28
-/* PCNT_CH1_POS_MODE_U3 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */
-/*description: .*/
-#define PCNT_CH1_POS_MODE_U3    0x00000003
-#define PCNT_CH1_POS_MODE_U3_M  ((PCNT_CH1_POS_MODE_U3_V)<<(PCNT_CH1_POS_MODE_U3_S))
-#define PCNT_CH1_POS_MODE_U3_V  0x3
-#define PCNT_CH1_POS_MODE_U3_S  26
-/* PCNT_CH1_NEG_MODE_U3 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */
-/*description: .*/
-#define PCNT_CH1_NEG_MODE_U3    0x00000003
-#define PCNT_CH1_NEG_MODE_U3_M  ((PCNT_CH1_NEG_MODE_U3_V)<<(PCNT_CH1_NEG_MODE_U3_S))
-#define PCNT_CH1_NEG_MODE_U3_V  0x3
-#define PCNT_CH1_NEG_MODE_U3_S  24
-/* PCNT_CH0_LCTRL_MODE_U3 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */
-/*description: .*/
-#define PCNT_CH0_LCTRL_MODE_U3    0x00000003
-#define PCNT_CH0_LCTRL_MODE_U3_M  ((PCNT_CH0_LCTRL_MODE_U3_V)<<(PCNT_CH0_LCTRL_MODE_U3_S))
-#define PCNT_CH0_LCTRL_MODE_U3_V  0x3
-#define PCNT_CH0_LCTRL_MODE_U3_S  22
-/* PCNT_CH0_HCTRL_MODE_U3 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */
-/*description: .*/
-#define PCNT_CH0_HCTRL_MODE_U3    0x00000003
-#define PCNT_CH0_HCTRL_MODE_U3_M  ((PCNT_CH0_HCTRL_MODE_U3_V)<<(PCNT_CH0_HCTRL_MODE_U3_S))
-#define PCNT_CH0_HCTRL_MODE_U3_V  0x3
-#define PCNT_CH0_HCTRL_MODE_U3_S  20
-/* PCNT_CH0_POS_MODE_U3 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */
-/*description: .*/
-#define PCNT_CH0_POS_MODE_U3    0x00000003
-#define PCNT_CH0_POS_MODE_U3_M  ((PCNT_CH0_POS_MODE_U3_V)<<(PCNT_CH0_POS_MODE_U3_S))
-#define PCNT_CH0_POS_MODE_U3_V  0x3
-#define PCNT_CH0_POS_MODE_U3_S  18
-/* PCNT_CH0_NEG_MODE_U3 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */
-/*description: .*/
-#define PCNT_CH0_NEG_MODE_U3    0x00000003
-#define PCNT_CH0_NEG_MODE_U3_M  ((PCNT_CH0_NEG_MODE_U3_V)<<(PCNT_CH0_NEG_MODE_U3_S))
-#define PCNT_CH0_NEG_MODE_U3_V  0x3
-#define PCNT_CH0_NEG_MODE_U3_S  16
-/* PCNT_THR_THRES1_EN_U3 : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: .*/
-#define PCNT_THR_THRES1_EN_U3    (BIT(15))
-#define PCNT_THR_THRES1_EN_U3_M  (BIT(15))
-#define PCNT_THR_THRES1_EN_U3_V  0x1
-#define PCNT_THR_THRES1_EN_U3_S  15
-/* PCNT_THR_THRES0_EN_U3 : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: .*/
-#define PCNT_THR_THRES0_EN_U3    (BIT(14))
-#define PCNT_THR_THRES0_EN_U3_M  (BIT(14))
-#define PCNT_THR_THRES0_EN_U3_V  0x1
-#define PCNT_THR_THRES0_EN_U3_S  14
-/* PCNT_THR_L_LIM_EN_U3 : R/W ;bitpos:[13] ;default: 1'b1 ; */
-/*description: .*/
-#define PCNT_THR_L_LIM_EN_U3    (BIT(13))
-#define PCNT_THR_L_LIM_EN_U3_M  (BIT(13))
-#define PCNT_THR_L_LIM_EN_U3_V  0x1
-#define PCNT_THR_L_LIM_EN_U3_S  13
-/* PCNT_THR_H_LIM_EN_U3 : R/W ;bitpos:[12] ;default: 1'b1 ; */
-/*description: .*/
-#define PCNT_THR_H_LIM_EN_U3    (BIT(12))
-#define PCNT_THR_H_LIM_EN_U3_M  (BIT(12))
-#define PCNT_THR_H_LIM_EN_U3_V  0x1
-#define PCNT_THR_H_LIM_EN_U3_S  12
-/* PCNT_THR_ZERO_EN_U3 : R/W ;bitpos:[11] ;default: 1'b1 ; */
-/*description: .*/
-#define PCNT_THR_ZERO_EN_U3    (BIT(11))
-#define PCNT_THR_ZERO_EN_U3_M  (BIT(11))
-#define PCNT_THR_ZERO_EN_U3_V  0x1
-#define PCNT_THR_ZERO_EN_U3_S  11
-/* PCNT_FILTER_EN_U3 : R/W ;bitpos:[10] ;default: 1'b1 ; */
-/*description: .*/
+/** PCNT_U3_CONF0_REG register
+ *  Configuration register 0 for unit 3
+ */
+#define PCNT_U3_CONF0_REG (DR_REG_PCNT_BASE + 0x24)
+/** PCNT_FILTER_THRES_U3 : R/W; bitpos: [9:0]; default: 16;
+ *  This sets the maximum threshold, in APB_CLK cycles, for the filter.
+ *
+ *  Any pulses with width less than this will be ignored when the filter is enabled.
+ */
+#define PCNT_FILTER_THRES_U3    0x000003FFU
+#define PCNT_FILTER_THRES_U3_M  (PCNT_FILTER_THRES_U3_V << PCNT_FILTER_THRES_U3_S)
+#define PCNT_FILTER_THRES_U3_V  0x000003FFU
+#define PCNT_FILTER_THRES_U3_S  0
+/** PCNT_FILTER_EN_U3 : R/W; bitpos: [10]; default: 1;
+ *  This is the enable bit for unit 3's input filter.
+ */
 #define PCNT_FILTER_EN_U3    (BIT(10))
-#define PCNT_FILTER_EN_U3_M  (BIT(10))
-#define PCNT_FILTER_EN_U3_V  0x1
+#define PCNT_FILTER_EN_U3_M  (PCNT_FILTER_EN_U3_V << PCNT_FILTER_EN_U3_S)
+#define PCNT_FILTER_EN_U3_V  0x00000001U
 #define PCNT_FILTER_EN_U3_S  10
-/* PCNT_FILTER_THRES_U3 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */
-/*description: .*/
-#define PCNT_FILTER_THRES_U3    0x000003FF
-#define PCNT_FILTER_THRES_U3_M  ((PCNT_FILTER_THRES_U3_V)<<(PCNT_FILTER_THRES_U3_S))
-#define PCNT_FILTER_THRES_U3_V  0x3FF
-#define PCNT_FILTER_THRES_U3_S  0
+/** PCNT_THR_ZERO_EN_U3 : R/W; bitpos: [11]; default: 1;
+ *  This is the enable bit for unit 3's zero comparator.
+ */
+#define PCNT_THR_ZERO_EN_U3    (BIT(11))
+#define PCNT_THR_ZERO_EN_U3_M  (PCNT_THR_ZERO_EN_U3_V << PCNT_THR_ZERO_EN_U3_S)
+#define PCNT_THR_ZERO_EN_U3_V  0x00000001U
+#define PCNT_THR_ZERO_EN_U3_S  11
+/** PCNT_THR_H_LIM_EN_U3 : R/W; bitpos: [12]; default: 1;
+ *  This is the enable bit for unit 3's thr_h_lim comparator.
+ */
+#define PCNT_THR_H_LIM_EN_U3    (BIT(12))
+#define PCNT_THR_H_LIM_EN_U3_M  (PCNT_THR_H_LIM_EN_U3_V << PCNT_THR_H_LIM_EN_U3_S)
+#define PCNT_THR_H_LIM_EN_U3_V  0x00000001U
+#define PCNT_THR_H_LIM_EN_U3_S  12
+/** PCNT_THR_L_LIM_EN_U3 : R/W; bitpos: [13]; default: 1;
+ *  This is the enable bit for unit 3's thr_l_lim comparator.
+ */
+#define PCNT_THR_L_LIM_EN_U3    (BIT(13))
+#define PCNT_THR_L_LIM_EN_U3_M  (PCNT_THR_L_LIM_EN_U3_V << PCNT_THR_L_LIM_EN_U3_S)
+#define PCNT_THR_L_LIM_EN_U3_V  0x00000001U
+#define PCNT_THR_L_LIM_EN_U3_S  13
+/** PCNT_THR_THRES0_EN_U3 : R/W; bitpos: [14]; default: 0;
+ *  This is the enable bit for unit 3's thres0 comparator.
+ */
+#define PCNT_THR_THRES0_EN_U3    (BIT(14))
+#define PCNT_THR_THRES0_EN_U3_M  (PCNT_THR_THRES0_EN_U3_V << PCNT_THR_THRES0_EN_U3_S)
+#define PCNT_THR_THRES0_EN_U3_V  0x00000001U
+#define PCNT_THR_THRES0_EN_U3_S  14
+/** PCNT_THR_THRES1_EN_U3 : R/W; bitpos: [15]; default: 0;
+ *  This is the enable bit for unit 3's thres1 comparator.
+ */
+#define PCNT_THR_THRES1_EN_U3    (BIT(15))
+#define PCNT_THR_THRES1_EN_U3_M  (PCNT_THR_THRES1_EN_U3_V << PCNT_THR_THRES1_EN_U3_S)
+#define PCNT_THR_THRES1_EN_U3_V  0x00000001U
+#define PCNT_THR_THRES1_EN_U3_S  15
+/** PCNT_CH0_NEG_MODE_U3 : R/W; bitpos: [17:16]; default: 0;
+ *  This register sets the behavior when the signal input of channel 0 detects a
+ *  negative edge.
+ *
+ *  1: Increase the counter;2: Decrease the counter;0, 3: No effect on counter
+ */
+#define PCNT_CH0_NEG_MODE_U3    0x00000003U
+#define PCNT_CH0_NEG_MODE_U3_M  (PCNT_CH0_NEG_MODE_U3_V << PCNT_CH0_NEG_MODE_U3_S)
+#define PCNT_CH0_NEG_MODE_U3_V  0x00000003U
+#define PCNT_CH0_NEG_MODE_U3_S  16
+/** PCNT_CH0_POS_MODE_U3 : R/W; bitpos: [19:18]; default: 0;
+ *  This register sets the behavior when the signal input of channel 0 detects a
+ *  positive edge.
+ *
+ *  1: Increase the counter;2: Decrease the counter;0, 3: No effect on counter
+ */
+#define PCNT_CH0_POS_MODE_U3    0x00000003U
+#define PCNT_CH0_POS_MODE_U3_M  (PCNT_CH0_POS_MODE_U3_V << PCNT_CH0_POS_MODE_U3_S)
+#define PCNT_CH0_POS_MODE_U3_V  0x00000003U
+#define PCNT_CH0_POS_MODE_U3_S  18
+/** PCNT_CH0_HCTRL_MODE_U3 : R/W; bitpos: [21:20]; default: 0;
+ *  This register configures how the CH3_POS_MODE/CH3_NEG_MODE settings will be
+ *  modified when the control signal is high.
+ *
+ *  0: No modification;1: Invert behavior (increase -> decrease, decrease ->
+ *  increase);2, 3: Inhibit counter modification
+ */
+#define PCNT_CH0_HCTRL_MODE_U3    0x00000003U
+#define PCNT_CH0_HCTRL_MODE_U3_M  (PCNT_CH0_HCTRL_MODE_U3_V << PCNT_CH0_HCTRL_MODE_U3_S)
+#define PCNT_CH0_HCTRL_MODE_U3_V  0x00000003U
+#define PCNT_CH0_HCTRL_MODE_U3_S  20
+/** PCNT_CH0_LCTRL_MODE_U3 : R/W; bitpos: [23:22]; default: 0;
+ *  This register configures how the CH3_POS_MODE/CH3_NEG_MODE settings will be
+ *  modified when the control signal is low.
+ *
+ *  0: No modification;1: Invert behavior (increase -> decrease, decrease ->
+ *  increase);2, 3: Inhibit counter modification
+ */
+#define PCNT_CH0_LCTRL_MODE_U3    0x00000003U
+#define PCNT_CH0_LCTRL_MODE_U3_M  (PCNT_CH0_LCTRL_MODE_U3_V << PCNT_CH0_LCTRL_MODE_U3_S)
+#define PCNT_CH0_LCTRL_MODE_U3_V  0x00000003U
+#define PCNT_CH0_LCTRL_MODE_U3_S  22
+/** PCNT_CH1_NEG_MODE_U3 : R/W; bitpos: [25:24]; default: 0;
+ *  This register sets the behavior when the signal input of channel 1 detects a
+ *  negative edge.
+ *
+ *  1: Increment the counter;2: Decrement the counter;0, 3: No effect on counter
+ */
+#define PCNT_CH1_NEG_MODE_U3    0x00000003U
+#define PCNT_CH1_NEG_MODE_U3_M  (PCNT_CH1_NEG_MODE_U3_V << PCNT_CH1_NEG_MODE_U3_S)
+#define PCNT_CH1_NEG_MODE_U3_V  0x00000003U
+#define PCNT_CH1_NEG_MODE_U3_S  24
+/** PCNT_CH1_POS_MODE_U3 : R/W; bitpos: [27:26]; default: 0;
+ *  This register sets the behavior when the signal input of channel 1 detects a
+ *  positive edge.
+ *
+ *  1: Increment the counter;2: Decrement the counter;0, 3: No effect on counter
+ */
+#define PCNT_CH1_POS_MODE_U3    0x00000003U
+#define PCNT_CH1_POS_MODE_U3_M  (PCNT_CH1_POS_MODE_U3_V << PCNT_CH1_POS_MODE_U3_S)
+#define PCNT_CH1_POS_MODE_U3_V  0x00000003U
+#define PCNT_CH1_POS_MODE_U3_S  26
+/** PCNT_CH1_HCTRL_MODE_U3 : R/W; bitpos: [29:28]; default: 0;
+ *  This register configures how the CH3_POS_MODE/CH3_NEG_MODE settings will be
+ *  modified when the control signal is high.
+ *
+ *  0: No modification;1: Invert behavior (increase -> decrease, decrease ->
+ *  increase);2, 3: Inhibit counter modification
+ */
+#define PCNT_CH1_HCTRL_MODE_U3    0x00000003U
+#define PCNT_CH1_HCTRL_MODE_U3_M  (PCNT_CH1_HCTRL_MODE_U3_V << PCNT_CH1_HCTRL_MODE_U3_S)
+#define PCNT_CH1_HCTRL_MODE_U3_V  0x00000003U
+#define PCNT_CH1_HCTRL_MODE_U3_S  28
+/** PCNT_CH1_LCTRL_MODE_U3 : R/W; bitpos: [31:30]; default: 0;
+ *  This register configures how the CH3_POS_MODE/CH3_NEG_MODE settings will be
+ *  modified when the control signal is low.
+ *
+ *  0: No modification;1: Invert behavior (increase -> decrease, decrease ->
+ *  increase);2, 3: Inhibit counter modification
+ */
+#define PCNT_CH1_LCTRL_MODE_U3    0x00000003U
+#define PCNT_CH1_LCTRL_MODE_U3_M  (PCNT_CH1_LCTRL_MODE_U3_V << PCNT_CH1_LCTRL_MODE_U3_S)
+#define PCNT_CH1_LCTRL_MODE_U3_V  0x00000003U
+#define PCNT_CH1_LCTRL_MODE_U3_S  30
 
-#define PCNT_U3_CONF1_REG          (DR_REG_PCNT_BASE + 0x28)
-/* PCNT_CNT_THRES1_U3 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */
-/*description: .*/
-#define PCNT_CNT_THRES1_U3    0x0000FFFF
-#define PCNT_CNT_THRES1_U3_M  ((PCNT_CNT_THRES1_U3_V)<<(PCNT_CNT_THRES1_U3_S))
-#define PCNT_CNT_THRES1_U3_V  0xFFFF
-#define PCNT_CNT_THRES1_U3_S  16
-/* PCNT_CNT_THRES0_U3 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */
-/*description: .*/
-#define PCNT_CNT_THRES0_U3    0x0000FFFF
-#define PCNT_CNT_THRES0_U3_M  ((PCNT_CNT_THRES0_U3_V)<<(PCNT_CNT_THRES0_U3_S))
-#define PCNT_CNT_THRES0_U3_V  0xFFFF
+/** PCNT_U3_CONF1_REG register
+ *  Configuration register 1 for unit 3
+ */
+#define PCNT_U3_CONF1_REG (DR_REG_PCNT_BASE + 0x28)
+/** PCNT_CNT_THRES0_U3 : R/W; bitpos: [15:0]; default: 0;
+ *  This register is used to configure the thres0 value for unit 3.
+ */
+#define PCNT_CNT_THRES0_U3    0x0000FFFFU
+#define PCNT_CNT_THRES0_U3_M  (PCNT_CNT_THRES0_U3_V << PCNT_CNT_THRES0_U3_S)
+#define PCNT_CNT_THRES0_U3_V  0x0000FFFFU
 #define PCNT_CNT_THRES0_U3_S  0
+/** PCNT_CNT_THRES1_U3 : R/W; bitpos: [31:16]; default: 0;
+ *  This register is used to configure the thres1 value for unit 3.
+ */
+#define PCNT_CNT_THRES1_U3    0x0000FFFFU
+#define PCNT_CNT_THRES1_U3_M  (PCNT_CNT_THRES1_U3_V << PCNT_CNT_THRES1_U3_S)
+#define PCNT_CNT_THRES1_U3_V  0x0000FFFFU
+#define PCNT_CNT_THRES1_U3_S  16
 
-#define PCNT_U3_CONF2_REG          (DR_REG_PCNT_BASE + 0x2C)
-/* PCNT_CNT_L_LIM_U3 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */
-/*description: .*/
-#define PCNT_CNT_L_LIM_U3    0x0000FFFF
-#define PCNT_CNT_L_LIM_U3_M  ((PCNT_CNT_L_LIM_U3_V)<<(PCNT_CNT_L_LIM_U3_S))
-#define PCNT_CNT_L_LIM_U3_V  0xFFFF
-#define PCNT_CNT_L_LIM_U3_S  16
-/* PCNT_CNT_H_LIM_U3 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */
-/*description: .*/
-#define PCNT_CNT_H_LIM_U3    0x0000FFFF
-#define PCNT_CNT_H_LIM_U3_M  ((PCNT_CNT_H_LIM_U3_V)<<(PCNT_CNT_H_LIM_U3_S))
-#define PCNT_CNT_H_LIM_U3_V  0xFFFF
+/** PCNT_U3_CONF2_REG register
+ *  Configuration register 2 for unit 3
+ */
+#define PCNT_U3_CONF2_REG (DR_REG_PCNT_BASE + 0x2c)
+/** PCNT_CNT_H_LIM_U3 : R/W; bitpos: [15:0]; default: 0;
+ *  This register is used to configure the thr_h_lim value for unit 3.
+ */
+#define PCNT_CNT_H_LIM_U3    0x0000FFFFU
+#define PCNT_CNT_H_LIM_U3_M  (PCNT_CNT_H_LIM_U3_V << PCNT_CNT_H_LIM_U3_S)
+#define PCNT_CNT_H_LIM_U3_V  0x0000FFFFU
 #define PCNT_CNT_H_LIM_U3_S  0
+/** PCNT_CNT_L_LIM_U3 : R/W; bitpos: [31:16]; default: 0;
+ *  This register is used to configure the thr_l_lim value for unit 3.
+ */
+#define PCNT_CNT_L_LIM_U3    0x0000FFFFU
+#define PCNT_CNT_L_LIM_U3_M  (PCNT_CNT_L_LIM_U3_V << PCNT_CNT_L_LIM_U3_S)
+#define PCNT_CNT_L_LIM_U3_V  0x0000FFFFU
+#define PCNT_CNT_L_LIM_U3_S  16
 
-#define PCNT_U0_CNT_REG          (DR_REG_PCNT_BASE + 0x30)
-/* PCNT_PULSE_CNT_U0 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: .*/
-#define PCNT_PULSE_CNT_U0    0x0000FFFF
-#define PCNT_PULSE_CNT_U0_M  ((PCNT_PULSE_CNT_U0_V)<<(PCNT_PULSE_CNT_U0_S))
-#define PCNT_PULSE_CNT_U0_V  0xFFFF
+/** PCNT_U0_CNT_REG register
+ *  Counter value for unit 0
+ */
+#define PCNT_U0_CNT_REG (DR_REG_PCNT_BASE + 0x30)
+/** PCNT_PULSE_CNT_U0 : RO; bitpos: [15:0]; default: 0;
+ *  This register stores the current pulse count value for unit 0.
+ */
+#define PCNT_PULSE_CNT_U0    0x0000FFFFU
+#define PCNT_PULSE_CNT_U0_M  (PCNT_PULSE_CNT_U0_V << PCNT_PULSE_CNT_U0_S)
+#define PCNT_PULSE_CNT_U0_V  0x0000FFFFU
 #define PCNT_PULSE_CNT_U0_S  0
 
-#define PCNT_U1_CNT_REG          (DR_REG_PCNT_BASE + 0x34)
-/* PCNT_PULSE_CNT_U1 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: .*/
-#define PCNT_PULSE_CNT_U1    0x0000FFFF
-#define PCNT_PULSE_CNT_U1_M  ((PCNT_PULSE_CNT_U1_V)<<(PCNT_PULSE_CNT_U1_S))
-#define PCNT_PULSE_CNT_U1_V  0xFFFF
+/** PCNT_U1_CNT_REG register
+ *  Counter value for unit 1
+ */
+#define PCNT_U1_CNT_REG (DR_REG_PCNT_BASE + 0x34)
+/** PCNT_PULSE_CNT_U1 : RO; bitpos: [15:0]; default: 0;
+ *  This register stores the current pulse count value for unit 1.
+ */
+#define PCNT_PULSE_CNT_U1    0x0000FFFFU
+#define PCNT_PULSE_CNT_U1_M  (PCNT_PULSE_CNT_U1_V << PCNT_PULSE_CNT_U1_S)
+#define PCNT_PULSE_CNT_U1_V  0x0000FFFFU
 #define PCNT_PULSE_CNT_U1_S  0
 
-#define PCNT_U2_CNT_REG          (DR_REG_PCNT_BASE + 0x38)
-/* PCNT_PULSE_CNT_U2 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: .*/
-#define PCNT_PULSE_CNT_U2    0x0000FFFF
-#define PCNT_PULSE_CNT_U2_M  ((PCNT_PULSE_CNT_U2_V)<<(PCNT_PULSE_CNT_U2_S))
-#define PCNT_PULSE_CNT_U2_V  0xFFFF
+/** PCNT_U2_CNT_REG register
+ *  Counter value for unit 2
+ */
+#define PCNT_U2_CNT_REG (DR_REG_PCNT_BASE + 0x38)
+/** PCNT_PULSE_CNT_U2 : RO; bitpos: [15:0]; default: 0;
+ *  This register stores the current pulse count value for unit 2.
+ */
+#define PCNT_PULSE_CNT_U2    0x0000FFFFU
+#define PCNT_PULSE_CNT_U2_M  (PCNT_PULSE_CNT_U2_V << PCNT_PULSE_CNT_U2_S)
+#define PCNT_PULSE_CNT_U2_V  0x0000FFFFU
 #define PCNT_PULSE_CNT_U2_S  0
 
-#define PCNT_U3_CNT_REG          (DR_REG_PCNT_BASE + 0x3C)
-/* PCNT_PULSE_CNT_U3 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: .*/
-#define PCNT_PULSE_CNT_U3    0x0000FFFF
-#define PCNT_PULSE_CNT_U3_M  ((PCNT_PULSE_CNT_U3_V)<<(PCNT_PULSE_CNT_U3_S))
-#define PCNT_PULSE_CNT_U3_V  0xFFFF
+/** PCNT_U3_CNT_REG register
+ *  Counter value for unit 3
+ */
+#define PCNT_U3_CNT_REG (DR_REG_PCNT_BASE + 0x3c)
+/** PCNT_PULSE_CNT_U3 : RO; bitpos: [15:0]; default: 0;
+ *  This register stores the current pulse count value for unit 3.
+ */
+#define PCNT_PULSE_CNT_U3    0x0000FFFFU
+#define PCNT_PULSE_CNT_U3_M  (PCNT_PULSE_CNT_U3_V << PCNT_PULSE_CNT_U3_S)
+#define PCNT_PULSE_CNT_U3_V  0x0000FFFFU
 #define PCNT_PULSE_CNT_U3_S  0
 
-#define PCNT_INT_RAW_REG          (DR_REG_PCNT_BASE + 0x40)
-/* PCNT_CNT_THR_EVENT_U3_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: .*/
-#define PCNT_CNT_THR_EVENT_U3_INT_RAW    (BIT(3))
-#define PCNT_CNT_THR_EVENT_U3_INT_RAW_M  (BIT(3))
-#define PCNT_CNT_THR_EVENT_U3_INT_RAW_V  0x1
-#define PCNT_CNT_THR_EVENT_U3_INT_RAW_S  3
-/* PCNT_CNT_THR_EVENT_U2_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: .*/
-#define PCNT_CNT_THR_EVENT_U2_INT_RAW    (BIT(2))
-#define PCNT_CNT_THR_EVENT_U2_INT_RAW_M  (BIT(2))
-#define PCNT_CNT_THR_EVENT_U2_INT_RAW_V  0x1
-#define PCNT_CNT_THR_EVENT_U2_INT_RAW_S  2
-/* PCNT_CNT_THR_EVENT_U1_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: .*/
-#define PCNT_CNT_THR_EVENT_U1_INT_RAW    (BIT(1))
-#define PCNT_CNT_THR_EVENT_U1_INT_RAW_M  (BIT(1))
-#define PCNT_CNT_THR_EVENT_U1_INT_RAW_V  0x1
-#define PCNT_CNT_THR_EVENT_U1_INT_RAW_S  1
-/* PCNT_CNT_THR_EVENT_U0_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
+/** PCNT_INT_RAW_REG register
+ *  Interrupt raw status register
+ */
+#define PCNT_INT_RAW_REG (DR_REG_PCNT_BASE + 0x40)
+/** PCNT_CNT_THR_EVENT_U0_INT_RAW : RO; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt.
+ */
 #define PCNT_CNT_THR_EVENT_U0_INT_RAW    (BIT(0))
-#define PCNT_CNT_THR_EVENT_U0_INT_RAW_M  (BIT(0))
-#define PCNT_CNT_THR_EVENT_U0_INT_RAW_V  0x1
+#define PCNT_CNT_THR_EVENT_U0_INT_RAW_M  (PCNT_CNT_THR_EVENT_U0_INT_RAW_V << PCNT_CNT_THR_EVENT_U0_INT_RAW_S)
+#define PCNT_CNT_THR_EVENT_U0_INT_RAW_V  0x00000001U
 #define PCNT_CNT_THR_EVENT_U0_INT_RAW_S  0
+/** PCNT_CNT_THR_EVENT_U1_INT_RAW : RO; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt.
+ */
+#define PCNT_CNT_THR_EVENT_U1_INT_RAW    (BIT(1))
+#define PCNT_CNT_THR_EVENT_U1_INT_RAW_M  (PCNT_CNT_THR_EVENT_U1_INT_RAW_V << PCNT_CNT_THR_EVENT_U1_INT_RAW_S)
+#define PCNT_CNT_THR_EVENT_U1_INT_RAW_V  0x00000001U
+#define PCNT_CNT_THR_EVENT_U1_INT_RAW_S  1
+/** PCNT_CNT_THR_EVENT_U2_INT_RAW : RO; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt.
+ */
+#define PCNT_CNT_THR_EVENT_U2_INT_RAW    (BIT(2))
+#define PCNT_CNT_THR_EVENT_U2_INT_RAW_M  (PCNT_CNT_THR_EVENT_U2_INT_RAW_V << PCNT_CNT_THR_EVENT_U2_INT_RAW_S)
+#define PCNT_CNT_THR_EVENT_U2_INT_RAW_V  0x00000001U
+#define PCNT_CNT_THR_EVENT_U2_INT_RAW_S  2
+/** PCNT_CNT_THR_EVENT_U3_INT_RAW : RO; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt.
+ */
+#define PCNT_CNT_THR_EVENT_U3_INT_RAW    (BIT(3))
+#define PCNT_CNT_THR_EVENT_U3_INT_RAW_M  (PCNT_CNT_THR_EVENT_U3_INT_RAW_V << PCNT_CNT_THR_EVENT_U3_INT_RAW_S)
+#define PCNT_CNT_THR_EVENT_U3_INT_RAW_V  0x00000001U
+#define PCNT_CNT_THR_EVENT_U3_INT_RAW_S  3
 
-#define PCNT_INT_ST_REG          (DR_REG_PCNT_BASE + 0x44)
-/* PCNT_CNT_THR_EVENT_U3_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: .*/
-#define PCNT_CNT_THR_EVENT_U3_INT_ST    (BIT(3))
-#define PCNT_CNT_THR_EVENT_U3_INT_ST_M  (BIT(3))
-#define PCNT_CNT_THR_EVENT_U3_INT_ST_V  0x1
-#define PCNT_CNT_THR_EVENT_U3_INT_ST_S  3
-/* PCNT_CNT_THR_EVENT_U2_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: .*/
-#define PCNT_CNT_THR_EVENT_U2_INT_ST    (BIT(2))
-#define PCNT_CNT_THR_EVENT_U2_INT_ST_M  (BIT(2))
-#define PCNT_CNT_THR_EVENT_U2_INT_ST_V  0x1
-#define PCNT_CNT_THR_EVENT_U2_INT_ST_S  2
-/* PCNT_CNT_THR_EVENT_U1_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: .*/
-#define PCNT_CNT_THR_EVENT_U1_INT_ST    (BIT(1))
-#define PCNT_CNT_THR_EVENT_U1_INT_ST_M  (BIT(1))
-#define PCNT_CNT_THR_EVENT_U1_INT_ST_V  0x1
-#define PCNT_CNT_THR_EVENT_U1_INT_ST_S  1
-/* PCNT_CNT_THR_EVENT_U0_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
+/** PCNT_INT_ST_REG register
+ *  Interrupt status register
+ */
+#define PCNT_INT_ST_REG (DR_REG_PCNT_BASE + 0x44)
+/** PCNT_CNT_THR_EVENT_U0_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt.
+ */
 #define PCNT_CNT_THR_EVENT_U0_INT_ST    (BIT(0))
-#define PCNT_CNT_THR_EVENT_U0_INT_ST_M  (BIT(0))
-#define PCNT_CNT_THR_EVENT_U0_INT_ST_V  0x1
+#define PCNT_CNT_THR_EVENT_U0_INT_ST_M  (PCNT_CNT_THR_EVENT_U0_INT_ST_V << PCNT_CNT_THR_EVENT_U0_INT_ST_S)
+#define PCNT_CNT_THR_EVENT_U0_INT_ST_V  0x00000001U
 #define PCNT_CNT_THR_EVENT_U0_INT_ST_S  0
+/** PCNT_CNT_THR_EVENT_U1_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt.
+ */
+#define PCNT_CNT_THR_EVENT_U1_INT_ST    (BIT(1))
+#define PCNT_CNT_THR_EVENT_U1_INT_ST_M  (PCNT_CNT_THR_EVENT_U1_INT_ST_V << PCNT_CNT_THR_EVENT_U1_INT_ST_S)
+#define PCNT_CNT_THR_EVENT_U1_INT_ST_V  0x00000001U
+#define PCNT_CNT_THR_EVENT_U1_INT_ST_S  1
+/** PCNT_CNT_THR_EVENT_U2_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt.
+ */
+#define PCNT_CNT_THR_EVENT_U2_INT_ST    (BIT(2))
+#define PCNT_CNT_THR_EVENT_U2_INT_ST_M  (PCNT_CNT_THR_EVENT_U2_INT_ST_V << PCNT_CNT_THR_EVENT_U2_INT_ST_S)
+#define PCNT_CNT_THR_EVENT_U2_INT_ST_V  0x00000001U
+#define PCNT_CNT_THR_EVENT_U2_INT_ST_S  2
+/** PCNT_CNT_THR_EVENT_U3_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt.
+ */
+#define PCNT_CNT_THR_EVENT_U3_INT_ST    (BIT(3))
+#define PCNT_CNT_THR_EVENT_U3_INT_ST_M  (PCNT_CNT_THR_EVENT_U3_INT_ST_V << PCNT_CNT_THR_EVENT_U3_INT_ST_S)
+#define PCNT_CNT_THR_EVENT_U3_INT_ST_V  0x00000001U
+#define PCNT_CNT_THR_EVENT_U3_INT_ST_S  3
 
-#define PCNT_INT_ENA_REG          (DR_REG_PCNT_BASE + 0x48)
-/* PCNT_CNT_THR_EVENT_U3_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: .*/
-#define PCNT_CNT_THR_EVENT_U3_INT_ENA    (BIT(3))
-#define PCNT_CNT_THR_EVENT_U3_INT_ENA_M  (BIT(3))
-#define PCNT_CNT_THR_EVENT_U3_INT_ENA_V  0x1
-#define PCNT_CNT_THR_EVENT_U3_INT_ENA_S  3
-/* PCNT_CNT_THR_EVENT_U2_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: .*/
-#define PCNT_CNT_THR_EVENT_U2_INT_ENA    (BIT(2))
-#define PCNT_CNT_THR_EVENT_U2_INT_ENA_M  (BIT(2))
-#define PCNT_CNT_THR_EVENT_U2_INT_ENA_V  0x1
-#define PCNT_CNT_THR_EVENT_U2_INT_ENA_S  2
-/* PCNT_CNT_THR_EVENT_U1_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: .*/
-#define PCNT_CNT_THR_EVENT_U1_INT_ENA    (BIT(1))
-#define PCNT_CNT_THR_EVENT_U1_INT_ENA_M  (BIT(1))
-#define PCNT_CNT_THR_EVENT_U1_INT_ENA_V  0x1
-#define PCNT_CNT_THR_EVENT_U1_INT_ENA_S  1
-/* PCNT_CNT_THR_EVENT_U0_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
+/** PCNT_INT_ENA_REG register
+ *  Interrupt enable register
+ */
+#define PCNT_INT_ENA_REG (DR_REG_PCNT_BASE + 0x48)
+/** PCNT_CNT_THR_EVENT_U0_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt.
+ */
 #define PCNT_CNT_THR_EVENT_U0_INT_ENA    (BIT(0))
-#define PCNT_CNT_THR_EVENT_U0_INT_ENA_M  (BIT(0))
-#define PCNT_CNT_THR_EVENT_U0_INT_ENA_V  0x1
+#define PCNT_CNT_THR_EVENT_U0_INT_ENA_M  (PCNT_CNT_THR_EVENT_U0_INT_ENA_V << PCNT_CNT_THR_EVENT_U0_INT_ENA_S)
+#define PCNT_CNT_THR_EVENT_U0_INT_ENA_V  0x00000001U
 #define PCNT_CNT_THR_EVENT_U0_INT_ENA_S  0
+/** PCNT_CNT_THR_EVENT_U1_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt.
+ */
+#define PCNT_CNT_THR_EVENT_U1_INT_ENA    (BIT(1))
+#define PCNT_CNT_THR_EVENT_U1_INT_ENA_M  (PCNT_CNT_THR_EVENT_U1_INT_ENA_V << PCNT_CNT_THR_EVENT_U1_INT_ENA_S)
+#define PCNT_CNT_THR_EVENT_U1_INT_ENA_V  0x00000001U
+#define PCNT_CNT_THR_EVENT_U1_INT_ENA_S  1
+/** PCNT_CNT_THR_EVENT_U2_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt.
+ */
+#define PCNT_CNT_THR_EVENT_U2_INT_ENA    (BIT(2))
+#define PCNT_CNT_THR_EVENT_U2_INT_ENA_M  (PCNT_CNT_THR_EVENT_U2_INT_ENA_V << PCNT_CNT_THR_EVENT_U2_INT_ENA_S)
+#define PCNT_CNT_THR_EVENT_U2_INT_ENA_V  0x00000001U
+#define PCNT_CNT_THR_EVENT_U2_INT_ENA_S  2
+/** PCNT_CNT_THR_EVENT_U3_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt.
+ */
+#define PCNT_CNT_THR_EVENT_U3_INT_ENA    (BIT(3))
+#define PCNT_CNT_THR_EVENT_U3_INT_ENA_M  (PCNT_CNT_THR_EVENT_U3_INT_ENA_V << PCNT_CNT_THR_EVENT_U3_INT_ENA_S)
+#define PCNT_CNT_THR_EVENT_U3_INT_ENA_V  0x00000001U
+#define PCNT_CNT_THR_EVENT_U3_INT_ENA_S  3
 
-#define PCNT_INT_CLR_REG          (DR_REG_PCNT_BASE + 0x4C)
-/* PCNT_CNT_THR_EVENT_U3_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: .*/
-#define PCNT_CNT_THR_EVENT_U3_INT_CLR    (BIT(3))
-#define PCNT_CNT_THR_EVENT_U3_INT_CLR_M  (BIT(3))
-#define PCNT_CNT_THR_EVENT_U3_INT_CLR_V  0x1
-#define PCNT_CNT_THR_EVENT_U3_INT_CLR_S  3
-/* PCNT_CNT_THR_EVENT_U2_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: .*/
-#define PCNT_CNT_THR_EVENT_U2_INT_CLR    (BIT(2))
-#define PCNT_CNT_THR_EVENT_U2_INT_CLR_M  (BIT(2))
-#define PCNT_CNT_THR_EVENT_U2_INT_CLR_V  0x1
-#define PCNT_CNT_THR_EVENT_U2_INT_CLR_S  2
-/* PCNT_CNT_THR_EVENT_U1_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: .*/
-#define PCNT_CNT_THR_EVENT_U1_INT_CLR    (BIT(1))
-#define PCNT_CNT_THR_EVENT_U1_INT_CLR_M  (BIT(1))
-#define PCNT_CNT_THR_EVENT_U1_INT_CLR_V  0x1
-#define PCNT_CNT_THR_EVENT_U1_INT_CLR_S  1
-/* PCNT_CNT_THR_EVENT_U0_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
+/** PCNT_INT_CLR_REG register
+ *  Interrupt clear register
+ */
+#define PCNT_INT_CLR_REG (DR_REG_PCNT_BASE + 0x4c)
+/** PCNT_CNT_THR_EVENT_U0_INT_CLR : WO; bitpos: [0]; default: 0;
+ *  Set this bit to clear the PCNT_CNT_THR_EVENT_U0_INT interrupt.
+ */
 #define PCNT_CNT_THR_EVENT_U0_INT_CLR    (BIT(0))
-#define PCNT_CNT_THR_EVENT_U0_INT_CLR_M  (BIT(0))
-#define PCNT_CNT_THR_EVENT_U0_INT_CLR_V  0x1
+#define PCNT_CNT_THR_EVENT_U0_INT_CLR_M  (PCNT_CNT_THR_EVENT_U0_INT_CLR_V << PCNT_CNT_THR_EVENT_U0_INT_CLR_S)
+#define PCNT_CNT_THR_EVENT_U0_INT_CLR_V  0x00000001U
 #define PCNT_CNT_THR_EVENT_U0_INT_CLR_S  0
+/** PCNT_CNT_THR_EVENT_U1_INT_CLR : WO; bitpos: [1]; default: 0;
+ *  Set this bit to clear the PCNT_CNT_THR_EVENT_U1_INT interrupt.
+ */
+#define PCNT_CNT_THR_EVENT_U1_INT_CLR    (BIT(1))
+#define PCNT_CNT_THR_EVENT_U1_INT_CLR_M  (PCNT_CNT_THR_EVENT_U1_INT_CLR_V << PCNT_CNT_THR_EVENT_U1_INT_CLR_S)
+#define PCNT_CNT_THR_EVENT_U1_INT_CLR_V  0x00000001U
+#define PCNT_CNT_THR_EVENT_U1_INT_CLR_S  1
+/** PCNT_CNT_THR_EVENT_U2_INT_CLR : WO; bitpos: [2]; default: 0;
+ *  Set this bit to clear the PCNT_CNT_THR_EVENT_U2_INT interrupt.
+ */
+#define PCNT_CNT_THR_EVENT_U2_INT_CLR    (BIT(2))
+#define PCNT_CNT_THR_EVENT_U2_INT_CLR_M  (PCNT_CNT_THR_EVENT_U2_INT_CLR_V << PCNT_CNT_THR_EVENT_U2_INT_CLR_S)
+#define PCNT_CNT_THR_EVENT_U2_INT_CLR_V  0x00000001U
+#define PCNT_CNT_THR_EVENT_U2_INT_CLR_S  2
+/** PCNT_CNT_THR_EVENT_U3_INT_CLR : WO; bitpos: [3]; default: 0;
+ *  Set this bit to clear the PCNT_CNT_THR_EVENT_U3_INT interrupt.
+ */
+#define PCNT_CNT_THR_EVENT_U3_INT_CLR    (BIT(3))
+#define PCNT_CNT_THR_EVENT_U3_INT_CLR_M  (PCNT_CNT_THR_EVENT_U3_INT_CLR_V << PCNT_CNT_THR_EVENT_U3_INT_CLR_S)
+#define PCNT_CNT_THR_EVENT_U3_INT_CLR_V  0x00000001U
+#define PCNT_CNT_THR_EVENT_U3_INT_CLR_S  3
 
-#define PCNT_U0_STATUS_REG          (DR_REG_PCNT_BASE + 0x50)
-/* PCNT_CNT_THR_ZERO_LAT_U0 : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: .*/
-#define PCNT_CNT_THR_ZERO_LAT_U0    (BIT(6))
-#define PCNT_CNT_THR_ZERO_LAT_U0_M  (BIT(6))
-#define PCNT_CNT_THR_ZERO_LAT_U0_V  0x1
-#define PCNT_CNT_THR_ZERO_LAT_U0_S  6
-/* PCNT_CNT_THR_H_LIM_LAT_U0 : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: .*/
-#define PCNT_CNT_THR_H_LIM_LAT_U0    (BIT(5))
-#define PCNT_CNT_THR_H_LIM_LAT_U0_M  (BIT(5))
-#define PCNT_CNT_THR_H_LIM_LAT_U0_V  0x1
-#define PCNT_CNT_THR_H_LIM_LAT_U0_S  5
-/* PCNT_CNT_THR_L_LIM_LAT_U0 : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: .*/
-#define PCNT_CNT_THR_L_LIM_LAT_U0    (BIT(4))
-#define PCNT_CNT_THR_L_LIM_LAT_U0_M  (BIT(4))
-#define PCNT_CNT_THR_L_LIM_LAT_U0_V  0x1
-#define PCNT_CNT_THR_L_LIM_LAT_U0_S  4
-/* PCNT_CNT_THR_THRES0_LAT_U0 : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: .*/
-#define PCNT_CNT_THR_THRES0_LAT_U0    (BIT(3))
-#define PCNT_CNT_THR_THRES0_LAT_U0_M  (BIT(3))
-#define PCNT_CNT_THR_THRES0_LAT_U0_V  0x1
-#define PCNT_CNT_THR_THRES0_LAT_U0_S  3
-/* PCNT_CNT_THR_THRES1_LAT_U0 : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: .*/
+/** PCNT_U0_STATUS_REG register
+ *  PNCT UNIT0 status register
+ */
+#define PCNT_U0_STATUS_REG (DR_REG_PCNT_BASE + 0x50)
+/** PCNT_CNT_THR_ZERO_MODE_U0 : RO; bitpos: [1:0]; default: 0;
+ *  The pulse counter status of PCNT_U0 corresponding to 0. 0: pulse counter decreases
+ *  from positive to 0. 1: pulse counter increases from negative to 0. 2: pulse counter
+ *  is negative. 3: pulse counter is positive.
+ */
+#define PCNT_CNT_THR_ZERO_MODE_U0    0x00000003U
+#define PCNT_CNT_THR_ZERO_MODE_U0_M  (PCNT_CNT_THR_ZERO_MODE_U0_V << PCNT_CNT_THR_ZERO_MODE_U0_S)
+#define PCNT_CNT_THR_ZERO_MODE_U0_V  0x00000003U
+#define PCNT_CNT_THR_ZERO_MODE_U0_S  0
+/** PCNT_CNT_THR_THRES1_LAT_U0 : RO; bitpos: [2]; default: 0;
+ *  The latched value of thres1 event of PCNT_U0 when threshold event interrupt is
+ *  valid. 1: the current pulse counter equals to thres1 and thres1 event is valid. 0:
+ *  others
+ */
 #define PCNT_CNT_THR_THRES1_LAT_U0    (BIT(2))
-#define PCNT_CNT_THR_THRES1_LAT_U0_M  (BIT(2))
-#define PCNT_CNT_THR_THRES1_LAT_U0_V  0x1
+#define PCNT_CNT_THR_THRES1_LAT_U0_M  (PCNT_CNT_THR_THRES1_LAT_U0_V << PCNT_CNT_THR_THRES1_LAT_U0_S)
+#define PCNT_CNT_THR_THRES1_LAT_U0_V  0x00000001U
 #define PCNT_CNT_THR_THRES1_LAT_U0_S  2
-/* PCNT_CNT_THR_ZERO_MODE_U0 : RO ;bitpos:[1:0] ;default: 2'b0 ; */
-/*description: .*/
-#define PCNT_CNT_THR_ZERO_MODE_U0    0x00000003
-#define PCNT_CNT_THR_ZERO_MODE_U0_M  ((PCNT_CNT_THR_ZERO_MODE_U0_V)<<(PCNT_CNT_THR_ZERO_MODE_U0_S))
-#define PCNT_CNT_THR_ZERO_MODE_U0_V  0x3
-#define PCNT_CNT_THR_ZERO_MODE_U0_S  0
+/** PCNT_CNT_THR_THRES0_LAT_U0 : RO; bitpos: [3]; default: 0;
+ *  The latched value of thres0 event of PCNT_U0 when threshold event interrupt is
+ *  valid. 1: the current pulse counter equals to thres0 and thres0 event is valid. 0:
+ *  others
+ */
+#define PCNT_CNT_THR_THRES0_LAT_U0    (BIT(3))
+#define PCNT_CNT_THR_THRES0_LAT_U0_M  (PCNT_CNT_THR_THRES0_LAT_U0_V << PCNT_CNT_THR_THRES0_LAT_U0_S)
+#define PCNT_CNT_THR_THRES0_LAT_U0_V  0x00000001U
+#define PCNT_CNT_THR_THRES0_LAT_U0_S  3
+/** PCNT_CNT_THR_L_LIM_LAT_U0 : RO; bitpos: [4]; default: 0;
+ *  The latched value of low limit event of PCNT_U0 when threshold event interrupt is
+ *  valid. 1: the current pulse counter equals to thr_l_lim and low limit event is
+ *  valid. 0: others
+ */
+#define PCNT_CNT_THR_L_LIM_LAT_U0    (BIT(4))
+#define PCNT_CNT_THR_L_LIM_LAT_U0_M  (PCNT_CNT_THR_L_LIM_LAT_U0_V << PCNT_CNT_THR_L_LIM_LAT_U0_S)
+#define PCNT_CNT_THR_L_LIM_LAT_U0_V  0x00000001U
+#define PCNT_CNT_THR_L_LIM_LAT_U0_S  4
+/** PCNT_CNT_THR_H_LIM_LAT_U0 : RO; bitpos: [5]; default: 0;
+ *  The latched value of high limit event of PCNT_U0 when threshold event interrupt is
+ *  valid. 1: the current pulse counter equals to thr_h_lim and high limit event is
+ *  valid. 0: others
+ */
+#define PCNT_CNT_THR_H_LIM_LAT_U0    (BIT(5))
+#define PCNT_CNT_THR_H_LIM_LAT_U0_M  (PCNT_CNT_THR_H_LIM_LAT_U0_V << PCNT_CNT_THR_H_LIM_LAT_U0_S)
+#define PCNT_CNT_THR_H_LIM_LAT_U0_V  0x00000001U
+#define PCNT_CNT_THR_H_LIM_LAT_U0_S  5
+/** PCNT_CNT_THR_ZERO_LAT_U0 : RO; bitpos: [6]; default: 0;
+ *  The latched value of zero threshold event of PCNT_U0 when threshold event interrupt
+ *  is valid. 1: the current pulse counter equals to 0 and zero threshold event is
+ *  valid. 0: others
+ */
+#define PCNT_CNT_THR_ZERO_LAT_U0    (BIT(6))
+#define PCNT_CNT_THR_ZERO_LAT_U0_M  (PCNT_CNT_THR_ZERO_LAT_U0_V << PCNT_CNT_THR_ZERO_LAT_U0_S)
+#define PCNT_CNT_THR_ZERO_LAT_U0_V  0x00000001U
+#define PCNT_CNT_THR_ZERO_LAT_U0_S  6
 
-#define PCNT_U1_STATUS_REG          (DR_REG_PCNT_BASE + 0x54)
-/* PCNT_CNT_THR_ZERO_LAT_U1 : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: .*/
-#define PCNT_CNT_THR_ZERO_LAT_U1    (BIT(6))
-#define PCNT_CNT_THR_ZERO_LAT_U1_M  (BIT(6))
-#define PCNT_CNT_THR_ZERO_LAT_U1_V  0x1
-#define PCNT_CNT_THR_ZERO_LAT_U1_S  6
-/* PCNT_CNT_THR_H_LIM_LAT_U1 : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: .*/
-#define PCNT_CNT_THR_H_LIM_LAT_U1    (BIT(5))
-#define PCNT_CNT_THR_H_LIM_LAT_U1_M  (BIT(5))
-#define PCNT_CNT_THR_H_LIM_LAT_U1_V  0x1
-#define PCNT_CNT_THR_H_LIM_LAT_U1_S  5
-/* PCNT_CNT_THR_L_LIM_LAT_U1 : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: .*/
-#define PCNT_CNT_THR_L_LIM_LAT_U1    (BIT(4))
-#define PCNT_CNT_THR_L_LIM_LAT_U1_M  (BIT(4))
-#define PCNT_CNT_THR_L_LIM_LAT_U1_V  0x1
-#define PCNT_CNT_THR_L_LIM_LAT_U1_S  4
-/* PCNT_CNT_THR_THRES0_LAT_U1 : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: .*/
-#define PCNT_CNT_THR_THRES0_LAT_U1    (BIT(3))
-#define PCNT_CNT_THR_THRES0_LAT_U1_M  (BIT(3))
-#define PCNT_CNT_THR_THRES0_LAT_U1_V  0x1
-#define PCNT_CNT_THR_THRES0_LAT_U1_S  3
-/* PCNT_CNT_THR_THRES1_LAT_U1 : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: .*/
+/** PCNT_U1_STATUS_REG register
+ *  PNCT UNIT1 status register
+ */
+#define PCNT_U1_STATUS_REG (DR_REG_PCNT_BASE + 0x54)
+/** PCNT_CNT_THR_ZERO_MODE_U1 : RO; bitpos: [1:0]; default: 0;
+ *  The pulse counter status of PCNT_U1 corresponding to 0. 0: pulse counter decreases
+ *  from positive to 0. 1: pulse counter increases from negative to 0. 2: pulse counter
+ *  is negative. 3: pulse counter is positive.
+ */
+#define PCNT_CNT_THR_ZERO_MODE_U1    0x00000003U
+#define PCNT_CNT_THR_ZERO_MODE_U1_M  (PCNT_CNT_THR_ZERO_MODE_U1_V << PCNT_CNT_THR_ZERO_MODE_U1_S)
+#define PCNT_CNT_THR_ZERO_MODE_U1_V  0x00000003U
+#define PCNT_CNT_THR_ZERO_MODE_U1_S  0
+/** PCNT_CNT_THR_THRES1_LAT_U1 : RO; bitpos: [2]; default: 0;
+ *  The latched value of thres1 event of PCNT_U1 when threshold event interrupt is
+ *  valid. 1: the current pulse counter equals to thres1 and thres1 event is valid. 0:
+ *  others
+ */
 #define PCNT_CNT_THR_THRES1_LAT_U1    (BIT(2))
-#define PCNT_CNT_THR_THRES1_LAT_U1_M  (BIT(2))
-#define PCNT_CNT_THR_THRES1_LAT_U1_V  0x1
+#define PCNT_CNT_THR_THRES1_LAT_U1_M  (PCNT_CNT_THR_THRES1_LAT_U1_V << PCNT_CNT_THR_THRES1_LAT_U1_S)
+#define PCNT_CNT_THR_THRES1_LAT_U1_V  0x00000001U
 #define PCNT_CNT_THR_THRES1_LAT_U1_S  2
-/* PCNT_CNT_THR_ZERO_MODE_U1 : RO ;bitpos:[1:0] ;default: 2'b0 ; */
-/*description: .*/
-#define PCNT_CNT_THR_ZERO_MODE_U1    0x00000003
-#define PCNT_CNT_THR_ZERO_MODE_U1_M  ((PCNT_CNT_THR_ZERO_MODE_U1_V)<<(PCNT_CNT_THR_ZERO_MODE_U1_S))
-#define PCNT_CNT_THR_ZERO_MODE_U1_V  0x3
-#define PCNT_CNT_THR_ZERO_MODE_U1_S  0
+/** PCNT_CNT_THR_THRES0_LAT_U1 : RO; bitpos: [3]; default: 0;
+ *  The latched value of thres0 event of PCNT_U1 when threshold event interrupt is
+ *  valid. 1: the current pulse counter equals to thres0 and thres0 event is valid. 0:
+ *  others
+ */
+#define PCNT_CNT_THR_THRES0_LAT_U1    (BIT(3))
+#define PCNT_CNT_THR_THRES0_LAT_U1_M  (PCNT_CNT_THR_THRES0_LAT_U1_V << PCNT_CNT_THR_THRES0_LAT_U1_S)
+#define PCNT_CNT_THR_THRES0_LAT_U1_V  0x00000001U
+#define PCNT_CNT_THR_THRES0_LAT_U1_S  3
+/** PCNT_CNT_THR_L_LIM_LAT_U1 : RO; bitpos: [4]; default: 0;
+ *  The latched value of low limit event of PCNT_U1 when threshold event interrupt is
+ *  valid. 1: the current pulse counter equals to thr_l_lim and low limit event is
+ *  valid. 0: others
+ */
+#define PCNT_CNT_THR_L_LIM_LAT_U1    (BIT(4))
+#define PCNT_CNT_THR_L_LIM_LAT_U1_M  (PCNT_CNT_THR_L_LIM_LAT_U1_V << PCNT_CNT_THR_L_LIM_LAT_U1_S)
+#define PCNT_CNT_THR_L_LIM_LAT_U1_V  0x00000001U
+#define PCNT_CNT_THR_L_LIM_LAT_U1_S  4
+/** PCNT_CNT_THR_H_LIM_LAT_U1 : RO; bitpos: [5]; default: 0;
+ *  The latched value of high limit event of PCNT_U1 when threshold event interrupt is
+ *  valid. 1: the current pulse counter equals to thr_h_lim and high limit event is
+ *  valid. 0: others
+ */
+#define PCNT_CNT_THR_H_LIM_LAT_U1    (BIT(5))
+#define PCNT_CNT_THR_H_LIM_LAT_U1_M  (PCNT_CNT_THR_H_LIM_LAT_U1_V << PCNT_CNT_THR_H_LIM_LAT_U1_S)
+#define PCNT_CNT_THR_H_LIM_LAT_U1_V  0x00000001U
+#define PCNT_CNT_THR_H_LIM_LAT_U1_S  5
+/** PCNT_CNT_THR_ZERO_LAT_U1 : RO; bitpos: [6]; default: 0;
+ *  The latched value of zero threshold event of PCNT_U1 when threshold event interrupt
+ *  is valid. 1: the current pulse counter equals to 0 and zero threshold event is
+ *  valid. 0: others
+ */
+#define PCNT_CNT_THR_ZERO_LAT_U1    (BIT(6))
+#define PCNT_CNT_THR_ZERO_LAT_U1_M  (PCNT_CNT_THR_ZERO_LAT_U1_V << PCNT_CNT_THR_ZERO_LAT_U1_S)
+#define PCNT_CNT_THR_ZERO_LAT_U1_V  0x00000001U
+#define PCNT_CNT_THR_ZERO_LAT_U1_S  6
 
-#define PCNT_U2_STATUS_REG          (DR_REG_PCNT_BASE + 0x58)
-/* PCNT_CNT_THR_ZERO_LAT_U2 : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: .*/
-#define PCNT_CNT_THR_ZERO_LAT_U2    (BIT(6))
-#define PCNT_CNT_THR_ZERO_LAT_U2_M  (BIT(6))
-#define PCNT_CNT_THR_ZERO_LAT_U2_V  0x1
-#define PCNT_CNT_THR_ZERO_LAT_U2_S  6
-/* PCNT_CNT_THR_H_LIM_LAT_U2 : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: .*/
-#define PCNT_CNT_THR_H_LIM_LAT_U2    (BIT(5))
-#define PCNT_CNT_THR_H_LIM_LAT_U2_M  (BIT(5))
-#define PCNT_CNT_THR_H_LIM_LAT_U2_V  0x1
-#define PCNT_CNT_THR_H_LIM_LAT_U2_S  5
-/* PCNT_CNT_THR_L_LIM_LAT_U2 : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: .*/
-#define PCNT_CNT_THR_L_LIM_LAT_U2    (BIT(4))
-#define PCNT_CNT_THR_L_LIM_LAT_U2_M  (BIT(4))
-#define PCNT_CNT_THR_L_LIM_LAT_U2_V  0x1
-#define PCNT_CNT_THR_L_LIM_LAT_U2_S  4
-/* PCNT_CNT_THR_THRES0_LAT_U2 : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: .*/
-#define PCNT_CNT_THR_THRES0_LAT_U2    (BIT(3))
-#define PCNT_CNT_THR_THRES0_LAT_U2_M  (BIT(3))
-#define PCNT_CNT_THR_THRES0_LAT_U2_V  0x1
-#define PCNT_CNT_THR_THRES0_LAT_U2_S  3
-/* PCNT_CNT_THR_THRES1_LAT_U2 : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: .*/
+/** PCNT_U2_STATUS_REG register
+ *  PNCT UNIT2 status register
+ */
+#define PCNT_U2_STATUS_REG (DR_REG_PCNT_BASE + 0x58)
+/** PCNT_CNT_THR_ZERO_MODE_U2 : RO; bitpos: [1:0]; default: 0;
+ *  The pulse counter status of PCNT_U2 corresponding to 0. 0: pulse counter decreases
+ *  from positive to 0. 1: pulse counter increases from negative to 0. 2: pulse counter
+ *  is negative. 3: pulse counter is positive.
+ */
+#define PCNT_CNT_THR_ZERO_MODE_U2    0x00000003U
+#define PCNT_CNT_THR_ZERO_MODE_U2_M  (PCNT_CNT_THR_ZERO_MODE_U2_V << PCNT_CNT_THR_ZERO_MODE_U2_S)
+#define PCNT_CNT_THR_ZERO_MODE_U2_V  0x00000003U
+#define PCNT_CNT_THR_ZERO_MODE_U2_S  0
+/** PCNT_CNT_THR_THRES1_LAT_U2 : RO; bitpos: [2]; default: 0;
+ *  The latched value of thres1 event of PCNT_U2 when threshold event interrupt is
+ *  valid. 1: the current pulse counter equals to thres1 and thres1 event is valid. 0:
+ *  others
+ */
 #define PCNT_CNT_THR_THRES1_LAT_U2    (BIT(2))
-#define PCNT_CNT_THR_THRES1_LAT_U2_M  (BIT(2))
-#define PCNT_CNT_THR_THRES1_LAT_U2_V  0x1
+#define PCNT_CNT_THR_THRES1_LAT_U2_M  (PCNT_CNT_THR_THRES1_LAT_U2_V << PCNT_CNT_THR_THRES1_LAT_U2_S)
+#define PCNT_CNT_THR_THRES1_LAT_U2_V  0x00000001U
 #define PCNT_CNT_THR_THRES1_LAT_U2_S  2
-/* PCNT_CNT_THR_ZERO_MODE_U2 : RO ;bitpos:[1:0] ;default: 2'b0 ; */
-/*description: .*/
-#define PCNT_CNT_THR_ZERO_MODE_U2    0x00000003
-#define PCNT_CNT_THR_ZERO_MODE_U2_M  ((PCNT_CNT_THR_ZERO_MODE_U2_V)<<(PCNT_CNT_THR_ZERO_MODE_U2_S))
-#define PCNT_CNT_THR_ZERO_MODE_U2_V  0x3
-#define PCNT_CNT_THR_ZERO_MODE_U2_S  0
+/** PCNT_CNT_THR_THRES0_LAT_U2 : RO; bitpos: [3]; default: 0;
+ *  The latched value of thres0 event of PCNT_U2 when threshold event interrupt is
+ *  valid. 1: the current pulse counter equals to thres0 and thres0 event is valid. 0:
+ *  others
+ */
+#define PCNT_CNT_THR_THRES0_LAT_U2    (BIT(3))
+#define PCNT_CNT_THR_THRES0_LAT_U2_M  (PCNT_CNT_THR_THRES0_LAT_U2_V << PCNT_CNT_THR_THRES0_LAT_U2_S)
+#define PCNT_CNT_THR_THRES0_LAT_U2_V  0x00000001U
+#define PCNT_CNT_THR_THRES0_LAT_U2_S  3
+/** PCNT_CNT_THR_L_LIM_LAT_U2 : RO; bitpos: [4]; default: 0;
+ *  The latched value of low limit event of PCNT_U2 when threshold event interrupt is
+ *  valid. 1: the current pulse counter equals to thr_l_lim and low limit event is
+ *  valid. 0: others
+ */
+#define PCNT_CNT_THR_L_LIM_LAT_U2    (BIT(4))
+#define PCNT_CNT_THR_L_LIM_LAT_U2_M  (PCNT_CNT_THR_L_LIM_LAT_U2_V << PCNT_CNT_THR_L_LIM_LAT_U2_S)
+#define PCNT_CNT_THR_L_LIM_LAT_U2_V  0x00000001U
+#define PCNT_CNT_THR_L_LIM_LAT_U2_S  4
+/** PCNT_CNT_THR_H_LIM_LAT_U2 : RO; bitpos: [5]; default: 0;
+ *  The latched value of high limit event of PCNT_U2 when threshold event interrupt is
+ *  valid. 1: the current pulse counter equals to thr_h_lim and high limit event is
+ *  valid. 0: others
+ */
+#define PCNT_CNT_THR_H_LIM_LAT_U2    (BIT(5))
+#define PCNT_CNT_THR_H_LIM_LAT_U2_M  (PCNT_CNT_THR_H_LIM_LAT_U2_V << PCNT_CNT_THR_H_LIM_LAT_U2_S)
+#define PCNT_CNT_THR_H_LIM_LAT_U2_V  0x00000001U
+#define PCNT_CNT_THR_H_LIM_LAT_U2_S  5
+/** PCNT_CNT_THR_ZERO_LAT_U2 : RO; bitpos: [6]; default: 0;
+ *  The latched value of zero threshold event of PCNT_U2 when threshold event interrupt
+ *  is valid. 1: the current pulse counter equals to 0 and zero threshold event is
+ *  valid. 0: others
+ */
+#define PCNT_CNT_THR_ZERO_LAT_U2    (BIT(6))
+#define PCNT_CNT_THR_ZERO_LAT_U2_M  (PCNT_CNT_THR_ZERO_LAT_U2_V << PCNT_CNT_THR_ZERO_LAT_U2_S)
+#define PCNT_CNT_THR_ZERO_LAT_U2_V  0x00000001U
+#define PCNT_CNT_THR_ZERO_LAT_U2_S  6
 
-#define PCNT_U3_STATUS_REG          (DR_REG_PCNT_BASE + 0x5C)
-/* PCNT_CNT_THR_ZERO_LAT_U3 : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: .*/
-#define PCNT_CNT_THR_ZERO_LAT_U3    (BIT(6))
-#define PCNT_CNT_THR_ZERO_LAT_U3_M  (BIT(6))
-#define PCNT_CNT_THR_ZERO_LAT_U3_V  0x1
-#define PCNT_CNT_THR_ZERO_LAT_U3_S  6
-/* PCNT_CNT_THR_H_LIM_LAT_U3 : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: .*/
-#define PCNT_CNT_THR_H_LIM_LAT_U3    (BIT(5))
-#define PCNT_CNT_THR_H_LIM_LAT_U3_M  (BIT(5))
-#define PCNT_CNT_THR_H_LIM_LAT_U3_V  0x1
-#define PCNT_CNT_THR_H_LIM_LAT_U3_S  5
-/* PCNT_CNT_THR_L_LIM_LAT_U3 : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: .*/
-#define PCNT_CNT_THR_L_LIM_LAT_U3    (BIT(4))
-#define PCNT_CNT_THR_L_LIM_LAT_U3_M  (BIT(4))
-#define PCNT_CNT_THR_L_LIM_LAT_U3_V  0x1
-#define PCNT_CNT_THR_L_LIM_LAT_U3_S  4
-/* PCNT_CNT_THR_THRES0_LAT_U3 : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: .*/
-#define PCNT_CNT_THR_THRES0_LAT_U3    (BIT(3))
-#define PCNT_CNT_THR_THRES0_LAT_U3_M  (BIT(3))
-#define PCNT_CNT_THR_THRES0_LAT_U3_V  0x1
-#define PCNT_CNT_THR_THRES0_LAT_U3_S  3
-/* PCNT_CNT_THR_THRES1_LAT_U3 : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: .*/
+/** PCNT_U3_STATUS_REG register
+ *  PNCT UNIT3 status register
+ */
+#define PCNT_U3_STATUS_REG (DR_REG_PCNT_BASE + 0x5c)
+/** PCNT_CNT_THR_ZERO_MODE_U3 : RO; bitpos: [1:0]; default: 0;
+ *  The pulse counter status of PCNT_U3 corresponding to 0. 0: pulse counter decreases
+ *  from positive to 0. 1: pulse counter increases from negative to 0. 2: pulse counter
+ *  is negative. 3: pulse counter is positive.
+ */
+#define PCNT_CNT_THR_ZERO_MODE_U3    0x00000003U
+#define PCNT_CNT_THR_ZERO_MODE_U3_M  (PCNT_CNT_THR_ZERO_MODE_U3_V << PCNT_CNT_THR_ZERO_MODE_U3_S)
+#define PCNT_CNT_THR_ZERO_MODE_U3_V  0x00000003U
+#define PCNT_CNT_THR_ZERO_MODE_U3_S  0
+/** PCNT_CNT_THR_THRES1_LAT_U3 : RO; bitpos: [2]; default: 0;
+ *  The latched value of thres1 event of PCNT_U3 when threshold event interrupt is
+ *  valid. 1: the current pulse counter equals to thres1 and thres1 event is valid. 0:
+ *  others
+ */
 #define PCNT_CNT_THR_THRES1_LAT_U3    (BIT(2))
-#define PCNT_CNT_THR_THRES1_LAT_U3_M  (BIT(2))
-#define PCNT_CNT_THR_THRES1_LAT_U3_V  0x1
+#define PCNT_CNT_THR_THRES1_LAT_U3_M  (PCNT_CNT_THR_THRES1_LAT_U3_V << PCNT_CNT_THR_THRES1_LAT_U3_S)
+#define PCNT_CNT_THR_THRES1_LAT_U3_V  0x00000001U
 #define PCNT_CNT_THR_THRES1_LAT_U3_S  2
-/* PCNT_CNT_THR_ZERO_MODE_U3 : RO ;bitpos:[1:0] ;default: 2'b0 ; */
-/*description: .*/
-#define PCNT_CNT_THR_ZERO_MODE_U3    0x00000003
-#define PCNT_CNT_THR_ZERO_MODE_U3_M  ((PCNT_CNT_THR_ZERO_MODE_U3_V)<<(PCNT_CNT_THR_ZERO_MODE_U3_S))
-#define PCNT_CNT_THR_ZERO_MODE_U3_V  0x3
-#define PCNT_CNT_THR_ZERO_MODE_U3_S  0
+/** PCNT_CNT_THR_THRES0_LAT_U3 : RO; bitpos: [3]; default: 0;
+ *  The latched value of thres0 event of PCNT_U3 when threshold event interrupt is
+ *  valid. 1: the current pulse counter equals to thres0 and thres0 event is valid. 0:
+ *  others
+ */
+#define PCNT_CNT_THR_THRES0_LAT_U3    (BIT(3))
+#define PCNT_CNT_THR_THRES0_LAT_U3_M  (PCNT_CNT_THR_THRES0_LAT_U3_V << PCNT_CNT_THR_THRES0_LAT_U3_S)
+#define PCNT_CNT_THR_THRES0_LAT_U3_V  0x00000001U
+#define PCNT_CNT_THR_THRES0_LAT_U3_S  3
+/** PCNT_CNT_THR_L_LIM_LAT_U3 : RO; bitpos: [4]; default: 0;
+ *  The latched value of low limit event of PCNT_U3 when threshold event interrupt is
+ *  valid. 1: the current pulse counter equals to thr_l_lim and low limit event is
+ *  valid. 0: others
+ */
+#define PCNT_CNT_THR_L_LIM_LAT_U3    (BIT(4))
+#define PCNT_CNT_THR_L_LIM_LAT_U3_M  (PCNT_CNT_THR_L_LIM_LAT_U3_V << PCNT_CNT_THR_L_LIM_LAT_U3_S)
+#define PCNT_CNT_THR_L_LIM_LAT_U3_V  0x00000001U
+#define PCNT_CNT_THR_L_LIM_LAT_U3_S  4
+/** PCNT_CNT_THR_H_LIM_LAT_U3 : RO; bitpos: [5]; default: 0;
+ *  The latched value of high limit event of PCNT_U3 when threshold event interrupt is
+ *  valid. 1: the current pulse counter equals to thr_h_lim and high limit event is
+ *  valid. 0: others
+ */
+#define PCNT_CNT_THR_H_LIM_LAT_U3    (BIT(5))
+#define PCNT_CNT_THR_H_LIM_LAT_U3_M  (PCNT_CNT_THR_H_LIM_LAT_U3_V << PCNT_CNT_THR_H_LIM_LAT_U3_S)
+#define PCNT_CNT_THR_H_LIM_LAT_U3_V  0x00000001U
+#define PCNT_CNT_THR_H_LIM_LAT_U3_S  5
+/** PCNT_CNT_THR_ZERO_LAT_U3 : RO; bitpos: [6]; default: 0;
+ *  The latched value of zero threshold event of PCNT_U3 when threshold event interrupt
+ *  is valid. 1: the current pulse counter equals to 0 and zero threshold event is
+ *  valid. 0: others
+ */
+#define PCNT_CNT_THR_ZERO_LAT_U3    (BIT(6))
+#define PCNT_CNT_THR_ZERO_LAT_U3_M  (PCNT_CNT_THR_ZERO_LAT_U3_V << PCNT_CNT_THR_ZERO_LAT_U3_S)
+#define PCNT_CNT_THR_ZERO_LAT_U3_V  0x00000001U
+#define PCNT_CNT_THR_ZERO_LAT_U3_S  6
 
-#define PCNT_CTRL_REG          (DR_REG_PCNT_BASE + 0x60)
-/* PCNT_CLK_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */
-/*description: .*/
-#define PCNT_CLK_EN    (BIT(16))
-#define PCNT_CLK_EN_M  (BIT(16))
-#define PCNT_CLK_EN_V  0x1
-#define PCNT_CLK_EN_S  16
-/* PCNT_CNT_PAUSE_U3 : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: .*/
-#define PCNT_CNT_PAUSE_U3    (BIT(7))
-#define PCNT_CNT_PAUSE_U3_M  (BIT(7))
-#define PCNT_CNT_PAUSE_U3_V  0x1
-#define PCNT_CNT_PAUSE_U3_S  7
-/* PCNT_PULSE_CNT_RST_U3 : R/W ;bitpos:[6] ;default: 1'b1 ; */
-/*description: .*/
-#define PCNT_PULSE_CNT_RST_U3    (BIT(6))
-#define PCNT_PULSE_CNT_RST_U3_M  (BIT(6))
-#define PCNT_PULSE_CNT_RST_U3_V  0x1
-#define PCNT_PULSE_CNT_RST_U3_S  6
-/* PCNT_CNT_PAUSE_U2 : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: .*/
-#define PCNT_CNT_PAUSE_U2    (BIT(5))
-#define PCNT_CNT_PAUSE_U2_M  (BIT(5))
-#define PCNT_CNT_PAUSE_U2_V  0x1
-#define PCNT_CNT_PAUSE_U2_S  5
-/* PCNT_PULSE_CNT_RST_U2 : R/W ;bitpos:[4] ;default: 1'b1 ; */
-/*description: .*/
-#define PCNT_PULSE_CNT_RST_U2    (BIT(4))
-#define PCNT_PULSE_CNT_RST_U2_M  (BIT(4))
-#define PCNT_PULSE_CNT_RST_U2_V  0x1
-#define PCNT_PULSE_CNT_RST_U2_S  4
-/* PCNT_CNT_PAUSE_U1 : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: .*/
-#define PCNT_CNT_PAUSE_U1    (BIT(3))
-#define PCNT_CNT_PAUSE_U1_M  (BIT(3))
-#define PCNT_CNT_PAUSE_U1_V  0x1
-#define PCNT_CNT_PAUSE_U1_S  3
-/* PCNT_PULSE_CNT_RST_U1 : R/W ;bitpos:[2] ;default: 1'b1 ; */
-/*description: .*/
-#define PCNT_PULSE_CNT_RST_U1    (BIT(2))
-#define PCNT_PULSE_CNT_RST_U1_M  (BIT(2))
-#define PCNT_PULSE_CNT_RST_U1_V  0x1
-#define PCNT_PULSE_CNT_RST_U1_S  2
-/* PCNT_CNT_PAUSE_U0 : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: .*/
-#define PCNT_CNT_PAUSE_U0    (BIT(1))
-#define PCNT_CNT_PAUSE_U0_M  (BIT(1))
-#define PCNT_CNT_PAUSE_U0_V  0x1
-#define PCNT_CNT_PAUSE_U0_S  1
-/* PCNT_PULSE_CNT_RST_U0 : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: .*/
+/** PCNT_CTRL_REG register
+ *  Control register for all counters
+ */
+#define PCNT_CTRL_REG (DR_REG_PCNT_BASE + 0x60)
+/** PCNT_PULSE_CNT_RST_U0 : R/W; bitpos: [0]; default: 1;
+ *  Set this bit to clear unit 0's counter.
+ */
 #define PCNT_PULSE_CNT_RST_U0    (BIT(0))
-#define PCNT_PULSE_CNT_RST_U0_M  (BIT(0))
-#define PCNT_PULSE_CNT_RST_U0_V  0x1
+#define PCNT_PULSE_CNT_RST_U0_M  (PCNT_PULSE_CNT_RST_U0_V << PCNT_PULSE_CNT_RST_U0_S)
+#define PCNT_PULSE_CNT_RST_U0_V  0x00000001U
 #define PCNT_PULSE_CNT_RST_U0_S  0
+/** PCNT_CNT_PAUSE_U0 : R/W; bitpos: [1]; default: 0;
+ *  Set this bit to freeze unit 0's counter.
+ */
+#define PCNT_CNT_PAUSE_U0    (BIT(1))
+#define PCNT_CNT_PAUSE_U0_M  (PCNT_CNT_PAUSE_U0_V << PCNT_CNT_PAUSE_U0_S)
+#define PCNT_CNT_PAUSE_U0_V  0x00000001U
+#define PCNT_CNT_PAUSE_U0_S  1
+/** PCNT_PULSE_CNT_RST_U1 : R/W; bitpos: [2]; default: 1;
+ *  Set this bit to clear unit 1's counter.
+ */
+#define PCNT_PULSE_CNT_RST_U1    (BIT(2))
+#define PCNT_PULSE_CNT_RST_U1_M  (PCNT_PULSE_CNT_RST_U1_V << PCNT_PULSE_CNT_RST_U1_S)
+#define PCNT_PULSE_CNT_RST_U1_V  0x00000001U
+#define PCNT_PULSE_CNT_RST_U1_S  2
+/** PCNT_CNT_PAUSE_U1 : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to freeze unit 1's counter.
+ */
+#define PCNT_CNT_PAUSE_U1    (BIT(3))
+#define PCNT_CNT_PAUSE_U1_M  (PCNT_CNT_PAUSE_U1_V << PCNT_CNT_PAUSE_U1_S)
+#define PCNT_CNT_PAUSE_U1_V  0x00000001U
+#define PCNT_CNT_PAUSE_U1_S  3
+/** PCNT_PULSE_CNT_RST_U2 : R/W; bitpos: [4]; default: 1;
+ *  Set this bit to clear unit 2's counter.
+ */
+#define PCNT_PULSE_CNT_RST_U2    (BIT(4))
+#define PCNT_PULSE_CNT_RST_U2_M  (PCNT_PULSE_CNT_RST_U2_V << PCNT_PULSE_CNT_RST_U2_S)
+#define PCNT_PULSE_CNT_RST_U2_V  0x00000001U
+#define PCNT_PULSE_CNT_RST_U2_S  4
+/** PCNT_CNT_PAUSE_U2 : R/W; bitpos: [5]; default: 0;
+ *  Set this bit to freeze unit 2's counter.
+ */
+#define PCNT_CNT_PAUSE_U2    (BIT(5))
+#define PCNT_CNT_PAUSE_U2_M  (PCNT_CNT_PAUSE_U2_V << PCNT_CNT_PAUSE_U2_S)
+#define PCNT_CNT_PAUSE_U2_V  0x00000001U
+#define PCNT_CNT_PAUSE_U2_S  5
+/** PCNT_PULSE_CNT_RST_U3 : R/W; bitpos: [6]; default: 1;
+ *  Set this bit to clear unit 3's counter.
+ */
+#define PCNT_PULSE_CNT_RST_U3    (BIT(6))
+#define PCNT_PULSE_CNT_RST_U3_M  (PCNT_PULSE_CNT_RST_U3_V << PCNT_PULSE_CNT_RST_U3_S)
+#define PCNT_PULSE_CNT_RST_U3_V  0x00000001U
+#define PCNT_PULSE_CNT_RST_U3_S  6
+/** PCNT_CNT_PAUSE_U3 : R/W; bitpos: [7]; default: 0;
+ *  Set this bit to freeze unit 3's counter.
+ */
+#define PCNT_CNT_PAUSE_U3    (BIT(7))
+#define PCNT_CNT_PAUSE_U3_M  (PCNT_CNT_PAUSE_U3_V << PCNT_CNT_PAUSE_U3_S)
+#define PCNT_CNT_PAUSE_U3_V  0x00000001U
+#define PCNT_CNT_PAUSE_U3_S  7
+/** PCNT_CLK_EN : R/W; bitpos: [16]; default: 0;
+ *  The registers clock gate enable signal of PCNT module. 1: the registers can be read
+ *  and written by application. 0: the registers can not be read or written by
+ *  application
+ */
+#define PCNT_CLK_EN    (BIT(16))
+#define PCNT_CLK_EN_M  (PCNT_CLK_EN_V << PCNT_CLK_EN_S)
+#define PCNT_CLK_EN_V  0x00000001U
+#define PCNT_CLK_EN_S  16
 
-#define PCNT_DATE_REG          (DR_REG_PCNT_BASE + 0xFC)
-/* PCNT_DATE : R/W ;bitpos:[31:0] ;default: 32'h18072600 ; */
-/*description: .*/
-#define PCNT_DATE    0xFFFFFFFF
-#define PCNT_DATE_M  ((PCNT_DATE_V)<<(PCNT_DATE_S))
-#define PCNT_DATE_V  0xFFFFFFFF
+/** PCNT_DATE_REG register
+ *  PCNT version control register
+ */
+#define PCNT_DATE_REG (DR_REG_PCNT_BASE + 0xfc)
+/** PCNT_DATE : R/W; bitpos: [31:0]; default: 419898881;
+ *  This is the PCNT version control register.
+ */
+#define PCNT_DATE    0xFFFFFFFFU
+#define PCNT_DATE_M  (PCNT_DATE_V << PCNT_DATE_S)
+#define PCNT_DATE_V  0xFFFFFFFFU
 #define PCNT_DATE_S  0
 
-
 #ifdef __cplusplus
 }
 #endif
-
-
-
-#endif /*_SOC_PCNT_REG_H_ */

components/soc/esp32s3/include/soc/pcnt_struct.h

@@ -1,182 +1,416 @@
-// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _SOC_PCNT_STRUCT_H_
-#define _SOC_PCNT_STRUCT_H_
-
+/** Copyright 2021 Espressif Systems (Shanghai) PTE LTD
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License");
+ *  you may not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS,
+ *  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ */
+#pragma once
 
 #include <stdint.h>
+
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-typedef volatile struct {
+/** Group: Configuration Register */
+/** Type of un_conf0 register
+ *  Configuration register 0 for unit n
+ */
+typedef union {
+    struct {
+        /** filter_thres_un : R/W; bitpos: [9:0]; default: 16;
+         *  This sets the maximum threshold, in APB_CLK cycles, for the filter.
+         *
+         *  Any pulses with width less than this will be ignored when the filter is enabled.
+         */
+        uint32_t filter_thres_un: 10;
+        /** filter_en_un : R/W; bitpos: [10]; default: 1;
+         *  This is the enable bit for unit n's input filter.
+         */
+        uint32_t filter_en_un: 1;
+        /** thr_zero_en_un : R/W; bitpos: [11]; default: 1;
+         *  This is the enable bit for unit n's zero comparator.
+         */
+        uint32_t thr_zero_en_un: 1;
+        /** thr_h_lim_en_un : R/W; bitpos: [12]; default: 1;
+         *  This is the enable bit for unit n's thr_h_lim comparator.
+         */
+        uint32_t thr_h_lim_en_un: 1;
+        /** thr_l_lim_en_un : R/W; bitpos: [13]; default: 1;
+         *  This is the enable bit for unit n's thr_l_lim comparator.
+         */
+        uint32_t thr_l_lim_en_un: 1;
+        /** thr_thres0_en_un : R/W; bitpos: [14]; default: 0;
+         *  This is the enable bit for unit n's thres0 comparator.
+         */
+        uint32_t thr_thres0_en_un: 1;
+        /** thr_thres1_en_un : R/W; bitpos: [15]; default: 0;
+         *  This is the enable bit for unit n's thres1 comparator.
+         */
+        uint32_t thr_thres1_en_un: 1;
+        /** ch0_neg_mode_un : R/W; bitpos: [17:16]; default: 0;
+         *  This register sets the behavior when the signal input of channel 0 detects a
+         *  negative edge.
+         *
+         *  1: Increase the counter;2: Decrease the counter;0, 3: No effect on counter
+         */
+        uint32_t ch0_neg_mode_un: 2;
+        /** ch0_pos_mode_un : R/W; bitpos: [19:18]; default: 0;
+         *  This register sets the behavior when the signal input of channel 0 detects a
+         *  positive edge.
+         *
+         *  1: Increase the counter;2: Decrease the counter;0, 3: No effect on counter
+         */
+        uint32_t ch0_pos_mode_un: 2;
+        /** ch0_hctrl_mode_un : R/W; bitpos: [21:20]; default: 0;
+         *  This register configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be
+         *  modified when the control signal is high.
+         *
+         *  0: No modification;1: Invert behavior (increase -> decrease, decrease ->
+         *  increase);2, 3: Inhibit counter modification
+         */
+        uint32_t ch0_hctrl_mode_un: 2;
+        /** ch0_lctrl_mode_un : R/W; bitpos: [23:22]; default: 0;
+         *  This register configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be
+         *  modified when the control signal is low.
+         *
+         *  0: No modification;1: Invert behavior (increase -> decrease, decrease ->
+         *  increase);2, 3: Inhibit counter modification
+         */
+        uint32_t ch0_lctrl_mode_un: 2;
+        /** ch1_neg_mode_un : R/W; bitpos: [25:24]; default: 0;
+         *  This register sets the behavior when the signal input of channel 1 detects a
+         *  negative edge.
+         *
+         *  1: Increment the counter;2: Decrement the counter;0, 3: No effect on counter
+         */
+        uint32_t ch1_neg_mode_un: 2;
+        /** ch1_pos_mode_un : R/W; bitpos: [27:26]; default: 0;
+         *  This register sets the behavior when the signal input of channel 1 detects a
+         *  positive edge.
+         *
+         *  1: Increment the counter;2: Decrement the counter;0, 3: No effect on counter
+         */
+        uint32_t ch1_pos_mode_un: 2;
+        /** ch1_hctrl_mode_un : R/W; bitpos: [29:28]; default: 0;
+         *  This register configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be
+         *  modified when the control signal is high.
+         *
+         *  0: No modification;1: Invert behavior (increase -> decrease, decrease ->
+         *  increase);2, 3: Inhibit counter modification
+         */
+        uint32_t ch1_hctrl_mode_un: 2;
+        /** ch1_lctrl_mode_un : R/W; bitpos: [31:30]; default: 0;
+         *  This register configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be
+         *  modified when the control signal is low.
+         *
+         *  0: No modification;1: Invert behavior (increase -> decrease, decrease ->
+         *  increase);2, 3: Inhibit counter modification
+         */
+        uint32_t ch1_lctrl_mode_un: 2;
+    };
+    uint32_t val;
+} pcnt_un_conf0_reg_t;
+
+/** Type of un_conf1 register
+ *  Configuration register 1 for unit n
+ */
+typedef union {
+    struct {
+        /** cnt_thres0_un : R/W; bitpos: [15:0]; default: 0;
+         *  This register is used to configure the thres0 value for unit n.
+         */
+        uint32_t cnt_thres0_un: 16;
+        /** cnt_thres1_un : R/W; bitpos: [31:16]; default: 0;
+         *  This register is used to configure the thres1 value for unit n.
+         */
+        uint32_t cnt_thres1_un: 16;
+    };
+    uint32_t val;
+} pcnt_un_conf1_reg_t;
+
+/** Type of un_conf2 register
+ *  Configuration register 2 for unit n
+ */
+typedef union {
+    struct {
+        /** cnt_h_lim_un : R/W; bitpos: [15:0]; default: 0;
+         *  This register is used to configure the thr_h_lim value for unit n.
+         */
+        uint32_t cnt_h_lim_un: 16;
+        /** cnt_l_lim_un : R/W; bitpos: [31:16]; default: 0;
+         *  This register is used to configure the thr_l_lim value for unit n.
+         */
+        uint32_t cnt_l_lim_un: 16;
+    };
+    uint32_t val;
+} pcnt_un_conf2_reg_t;
+
+
+/** Type of ctrl register
+ *  Control register for all counters
+ */
+typedef union {
     struct {
-        union {
-            struct {
-                uint32_t filter_thres                  :    10;
-                uint32_t filter_en                     :    1;
-                uint32_t thr_zero_en                   :    1;
-                uint32_t thr_h_lim_en                  :    1;
-                uint32_t thr_l_lim_en                  :    1;
-                uint32_t thr_thres0_en                 :    1;
-                uint32_t thr_thres1_en                 :    1;
-                uint32_t ch0_neg_mode                  :    2;
-                uint32_t ch0_pos_mode                  :    2;
-                uint32_t ch0_hctrl_mode                :    2;
-                uint32_t ch0_lctrl_mode                :    2;
-                uint32_t ch1_neg_mode                  :    2;
-                uint32_t ch1_pos_mode                  :    2;
-                uint32_t ch1_hctrl_mode                :    2;
-                uint32_t ch1_lctrl_mode                :    2;
-            };
-            uint32_t val;
-        } conf0;
-        union {
-            struct {
-                uint32_t cnt_thres0                    :    16;
-                uint32_t cnt_thres1                    :    16;
-            };
-            uint32_t val;
-        } conf1;
-        union {
-            struct {
-                uint32_t cnt_h_lim                     :    16;
-                uint32_t cnt_l_lim                     :    16;
-            };
-            uint32_t val;
-        } conf2;
+        /** pulse_cnt_rst_u0 : R/W; bitpos: [0]; default: 1;
+         *  Set this bit to clear unit 0's counter.
+         */
+        uint32_t pulse_cnt_rst_u0: 1;
+        /** cnt_pause_u0 : R/W; bitpos: [1]; default: 0;
+         *  Set this bit to freeze unit 0's counter.
+         */
+        uint32_t cnt_pause_u0: 1;
+        /** pulse_cnt_rst_u1 : R/W; bitpos: [2]; default: 1;
+         *  Set this bit to clear unit 1's counter.
+         */
+        uint32_t pulse_cnt_rst_u1: 1;
+        /** cnt_pause_u1 : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to freeze unit 1's counter.
+         */
+        uint32_t cnt_pause_u1: 1;
+        /** pulse_cnt_rst_u2 : R/W; bitpos: [4]; default: 1;
+         *  Set this bit to clear unit 2's counter.
+         */
+        uint32_t pulse_cnt_rst_u2: 1;
+        /** cnt_pause_u2 : R/W; bitpos: [5]; default: 0;
+         *  Set this bit to freeze unit 2's counter.
+         */
+        uint32_t cnt_pause_u2: 1;
+        /** pulse_cnt_rst_u3 : R/W; bitpos: [6]; default: 1;
+         *  Set this bit to clear unit 3's counter.
+         */
+        uint32_t pulse_cnt_rst_u3: 1;
+        /** cnt_pause_u3 : R/W; bitpos: [7]; default: 0;
+         *  Set this bit to freeze unit 3's counter.
+         */
+        uint32_t cnt_pause_u3: 1;
+        uint32_t reserved_8: 8;
+        /** clk_en : R/W; bitpos: [16]; default: 0;
+         *  The registers clock gate enable signal of PCNT module. 1: the registers can be read
+         *  and written by application. 0: the registers can not be read or written by
+         *  application
+         */
+        uint32_t clk_en: 1;
+        uint32_t reserved_17: 15;
+    };
+    uint32_t val;
+} pcnt_ctrl_reg_t;
+
+
+/** Group: Status Register */
+/** Type of un_cnt register
+ *  Counter value for unit n
+ */
+typedef union {
+    struct {
+        /** pulse_cnt_un : RO; bitpos: [15:0]; default: 0;
+         *  This register stores the current pulse count value for unit n.
+         */
+        uint32_t pulse_cnt_un: 16;
+        uint32_t reserved_16: 16;
+    };
+    uint32_t val;
+} pcnt_un_cnt_reg_t;
+
+/** Type of un_status register
+ *  PNCT UNITn status register
+ */
+typedef union {
+    struct {
+        /** cnt_thr_zero_mode_un : RO; bitpos: [1:0]; default: 0;
+         *  The pulse counter status of PCNT_Un corresponding to 0. 0: pulse counter decreases
+         *  from positive to 0. 1: pulse counter increases from negative to 0. 2: pulse counter
+         *  is negative. 3: pulse counter is positive.
+         */
+        uint32_t cnt_thr_zero_mode_un: 2;
+        /** cnt_thr_thres1_lat_un : RO; bitpos: [2]; default: 0;
+         *  The latched value of thres1 event of PCNT_Un when threshold event interrupt is
+         *  valid. 1: the current pulse counter equals to thres1 and thres1 event is valid. 0:
+         *  others
+         */
+        uint32_t cnt_thr_thres1_lat_un: 1;
+        /** cnt_thr_thres0_lat_un : RO; bitpos: [3]; default: 0;
+         *  The latched value of thres0 event of PCNT_Un when threshold event interrupt is
+         *  valid. 1: the current pulse counter equals to thres0 and thres0 event is valid. 0:
+         *  others
+         */
+        uint32_t cnt_thr_thres0_lat_un: 1;
+        /** cnt_thr_l_lim_lat_un : RO; bitpos: [4]; default: 0;
+         *  The latched value of low limit event of PCNT_Un when threshold event interrupt is
+         *  valid. 1: the current pulse counter equals to thr_l_lim and low limit event is
+         *  valid. 0: others
+         */
+        uint32_t cnt_thr_l_lim_lat_un: 1;
+        /** cnt_thr_h_lim_lat_un : RO; bitpos: [5]; default: 0;
+         *  The latched value of high limit event of PCNT_Un when threshold event interrupt is
+         *  valid. 1: the current pulse counter equals to thr_h_lim and high limit event is
+         *  valid. 0: others
+         */
+        uint32_t cnt_thr_h_lim_lat_un: 1;
+        /** cnt_thr_zero_lat_un : RO; bitpos: [6]; default: 0;
+         *  The latched value of zero threshold event of PCNT_Un when threshold event interrupt
+         *  is valid. 1: the current pulse counter equals to 0 and zero threshold event is
+         *  valid. 0: others
+         */
+        uint32_t cnt_thr_zero_lat_un: 1;
+        uint32_t reserved_7: 25;
+    };
+    uint32_t val;
+} pcnt_un_status_reg_t;
+
+
+/** Group: Interrupt Register */
+/** Type of int_raw register
+ *  Interrupt raw status register
+ */
+typedef union {
+    struct {
+        /** cnt_thr_event_u0_int_raw : RO; bitpos: [0]; default: 0;
+         *  The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt.
+         */
+        uint32_t cnt_thr_event_u0_int_raw: 1;
+        /** cnt_thr_event_u1_int_raw : RO; bitpos: [1]; default: 0;
+         *  The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt.
+         */
+        uint32_t cnt_thr_event_u1_int_raw: 1;
+        /** cnt_thr_event_u2_int_raw : RO; bitpos: [2]; default: 0;
+         *  The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt.
+         */
+        uint32_t cnt_thr_event_u2_int_raw: 1;
+        /** cnt_thr_event_u3_int_raw : RO; bitpos: [3]; default: 0;
+         *  The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt.
+         */
+        uint32_t cnt_thr_event_u3_int_raw: 1;
+        uint32_t reserved_4: 28;
+    };
+    uint32_t val;
+} pcnt_int_raw_reg_t;
+
+/** Type of int_st register
+ *  Interrupt status register
+ */
+typedef union {
+    struct {
+        /** cnt_thr_event_u0_int_st : RO; bitpos: [0]; default: 0;
+         *  The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt.
+         */
+        uint32_t cnt_thr_event_u0_int_st: 1;
+        /** cnt_thr_event_u1_int_st : RO; bitpos: [1]; default: 0;
+         *  The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt.
+         */
+        uint32_t cnt_thr_event_u1_int_st: 1;
+        /** cnt_thr_event_u2_int_st : RO; bitpos: [2]; default: 0;
+         *  The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt.
+         */
+        uint32_t cnt_thr_event_u2_int_st: 1;
+        /** cnt_thr_event_u3_int_st : RO; bitpos: [3]; default: 0;
+         *  The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt.
+         */
+        uint32_t cnt_thr_event_u3_int_st: 1;
+        uint32_t reserved_4: 28;
+    };
+    uint32_t val;
+} pcnt_int_st_reg_t;
+
+/** Type of int_ena register
+ *  Interrupt enable register
+ */
+typedef union {
+    struct {
+        /** cnt_thr_event_u0_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt.
+         */
+        uint32_t cnt_thr_event_u0_int_ena: 1;
+        /** cnt_thr_event_u1_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The interrupt enable bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt.
+         */
+        uint32_t cnt_thr_event_u1_int_ena: 1;
+        /** cnt_thr_event_u2_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The interrupt enable bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt.
+         */
+        uint32_t cnt_thr_event_u2_int_ena: 1;
+        /** cnt_thr_event_u3_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The interrupt enable bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt.
+         */
+        uint32_t cnt_thr_event_u3_int_ena: 1;
+        uint32_t reserved_4: 28;
+    };
+    uint32_t val;
+} pcnt_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  Interrupt clear register
+ */
+typedef union {
+    struct {
+        /** cnt_thr_event_u0_int_clr : WO; bitpos: [0]; default: 0;
+         *  Set this bit to clear the PCNT_CNT_THR_EVENT_U0_INT interrupt.
+         */
+        uint32_t cnt_thr_event_u0_int_clr: 1;
+        /** cnt_thr_event_u1_int_clr : WO; bitpos: [1]; default: 0;
+         *  Set this bit to clear the PCNT_CNT_THR_EVENT_U1_INT interrupt.
+         */
+        uint32_t cnt_thr_event_u1_int_clr: 1;
+        /** cnt_thr_event_u2_int_clr : WO; bitpos: [2]; default: 0;
+         *  Set this bit to clear the PCNT_CNT_THR_EVENT_U2_INT interrupt.
+         */
+        uint32_t cnt_thr_event_u2_int_clr: 1;
+        /** cnt_thr_event_u3_int_clr : WO; bitpos: [3]; default: 0;
+         *  Set this bit to clear the PCNT_CNT_THR_EVENT_U3_INT interrupt.
+         */
+        uint32_t cnt_thr_event_u3_int_clr: 1;
+        uint32_t reserved_4: 28;
+    };
+    uint32_t val;
+} pcnt_int_clr_reg_t;
+
+
+/** Group: Version Register */
+/** Type of date register
+ *  PCNT version control register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [31:0]; default: 419898881;
+         *  This is the PCNT version control register.
+         */
+        uint32_t date: 32;
+    };
+    uint32_t val;
+} pcnt_date_reg_t;
+
+
+typedef struct {
+    volatile struct {
+        pcnt_un_conf0_reg_t conf0;
+        pcnt_un_conf1_reg_t conf1;
+        pcnt_un_conf2_reg_t conf2;
     } conf_unit[4];
-    union {
-        struct {
-            uint32_t cnt_val                       :    16;
-            uint32_t reserved16                    :    16;
-        };
-        uint32_t val;
-    } cnt_unit[4];
-    union {
-        struct {
-            uint32_t cnt_thr_event_u0              :    1;
-            uint32_t cnt_thr_event_u1              :    1;
-            uint32_t cnt_thr_event_u2              :    1;
-            uint32_t cnt_thr_event_u3              :    1;
-            uint32_t reserved4                     :    28;
-        };
-        uint32_t val;
-    } int_raw;
-    union {
-        struct {
-            uint32_t cnt_thr_event_u0              :    1;
-            uint32_t cnt_thr_event_u1              :    1;
-            uint32_t cnt_thr_event_u2              :    1;
-            uint32_t cnt_thr_event_u3              :    1;
-            uint32_t reserved4                     :    28;
-        };
-        uint32_t val;
-    } int_st;
-    union {
-        struct {
-            uint32_t cnt_thr_event_u0              :    1;
-            uint32_t cnt_thr_event_u1              :    1;
-            uint32_t cnt_thr_event_u2              :    1;
-            uint32_t cnt_thr_event_u3              :    1;
-            uint32_t reserved4                     :    28;
-        };
-        uint32_t val;
-    } int_ena;
-    union {
-        struct {
-            uint32_t cnt_thr_event_u0              :    1;
-            uint32_t cnt_thr_event_u1              :    1;
-            uint32_t cnt_thr_event_u2              :    1;
-            uint32_t cnt_thr_event_u3              :    1;
-            uint32_t reserved4                     :    28;
-        };
-        uint32_t val;
-    } int_clr;
-    union {
-        struct {
-            uint32_t zero_mode                     :    2;
-            uint32_t thres1_lat                    :    1;
-            uint32_t thres0_lat                    :    1;
-            uint32_t l_lim_lat                     :    1;
-            uint32_t h_lim_lat                     :    1;
-            uint32_t zero_lat                      :    1;
-            uint32_t reserved7                     :    25;
-        };
-        uint32_t val;
-    } status_unit[4];
-    union {
-        struct {
-            uint32_t cnt_rst_u0                    :    1;
-            uint32_t cnt_pause_u0                  :    1;
-            uint32_t cnt_rst_u1                    :    1;
-            uint32_t cnt_pause_u1                  :    1;
-            uint32_t cnt_rst_u2                    :    1;
-            uint32_t cnt_pause_u2                  :    1;
-            uint32_t cnt_rst_u3                    :    1;
-            uint32_t cnt_pause_u3                  :    1;
-            uint32_t reserved8                     :    8;
-            uint32_t clk_en                        :    1;
-            uint32_t reserved17                    :    15;
-        };
-        uint32_t val;
-    } ctrl;
-    uint32_t reserved_64;
-    uint32_t reserved_68;
-    uint32_t reserved_6c;
-    uint32_t reserved_70;
-    uint32_t reserved_74;
-    uint32_t reserved_78;
-    uint32_t reserved_7c;
-    uint32_t reserved_80;
-    uint32_t reserved_84;
-    uint32_t reserved_88;
-    uint32_t reserved_8c;
-    uint32_t reserved_90;
-    uint32_t reserved_94;
-    uint32_t reserved_98;
-    uint32_t reserved_9c;
-    uint32_t reserved_a0;
-    uint32_t reserved_a4;
-    uint32_t reserved_a8;
-    uint32_t reserved_ac;
-    uint32_t reserved_b0;
-    uint32_t reserved_b4;
-    uint32_t reserved_b8;
-    uint32_t reserved_bc;
-    uint32_t reserved_c0;
-    uint32_t reserved_c4;
-    uint32_t reserved_c8;
-    uint32_t reserved_cc;
-    uint32_t reserved_d0;
-    uint32_t reserved_d4;
-    uint32_t reserved_d8;
-    uint32_t reserved_dc;
-    uint32_t reserved_e0;
-    uint32_t reserved_e4;
-    uint32_t reserved_e8;
-    uint32_t reserved_ec;
-    uint32_t reserved_f0;
-    uint32_t reserved_f4;
-    uint32_t reserved_f8;
-    uint32_t date;
+    volatile pcnt_un_cnt_reg_t cnt_unit[4];
+    volatile pcnt_int_raw_reg_t int_raw;
+    volatile pcnt_int_st_reg_t int_st;
+    volatile pcnt_int_ena_reg_t int_ena;
+    volatile pcnt_int_clr_reg_t int_clr;
+    volatile pcnt_un_status_reg_t status_unit[4];
+    volatile pcnt_ctrl_reg_t ctrl;
+    uint32_t reserved_064[38];
+    volatile pcnt_date_reg_t date;
 } pcnt_dev_t;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(pcnt_dev_t) == 0x100, "Invalid size of pcnt_dev_t structure");
+#endif
+
 extern pcnt_dev_t PCNT;
+
 #ifdef __cplusplus
 }
 #endif
-
-
-
-#endif /*_SOC_PCNT_STRUCT_H_ */

components/soc/esp32s3/include/soc/soc_caps.h

@@ -92,9 +92,10 @@
 #include "mpu_caps.h"
 
 /*-------------------------- PCNT CAPS ---------------------------------------*/
-#define SOC_PCNT_PORT_NUM         (1)
-#define SOC_PCNT_UNIT_NUM         (4)
-#define SOC_PCNT_UNIT_CHANNEL_NUM (2)
+#define SOC_PCNT_GROUPS               (1)
+#define SOC_PCNT_UNITS_PER_GROUP      (4)
+#define SOC_PCNT_CHANNELS_PER_UNIT    (2)
+#define SOC_PCNT_THRES_POINT_PER_UNIT (2)
 
 /*-------------------------- RMT CAPS ----------------------------------------*/
 #define SOC_RMT_GROUPS                  (1)  /*!< One RMT group */

components/soc/esp32s3/pcnt_periph.c

@@ -16,54 +16,58 @@
 #include "soc/gpio_sig_map.h"
 
 const pcnt_signal_conn_t pcnt_periph_signals = {
-    .module = PERIPH_PCNT_MODULE,
-    .irq = ETS_PCNT_INTR_SOURCE,
-    .units = {
+    .groups = {
         [0] = {
-            .channels = {
+            .module = PERIPH_PCNT_MODULE,
+            .irq = ETS_PCNT_INTR_SOURCE,
+            .units = {
                 [0] = {
-                    .control_sig = PCNT_CTRL_CH0_IN0_IDX,
-                    .pulse_sig = PCNT_SIG_CH0_IN0_IDX
+                    .channels = {
+                        [0] = {
+                            .control_sig = PCNT_CTRL_CH0_IN0_IDX,
+                            .pulse_sig = PCNT_SIG_CH0_IN0_IDX
+                        },
+                        [1] = {
+                            .control_sig = PCNT_CTRL_CH1_IN0_IDX,
+                            .pulse_sig = PCNT_SIG_CH1_IN0_IDX
+                        }
+                    }
                 },
                 [1] = {
-                    .control_sig = PCNT_CTRL_CH1_IN0_IDX,
-                    .pulse_sig = PCNT_SIG_CH1_IN0_IDX
-                }
-            }
-        },
-        [1] = {
-            .channels = {
-                [0] = {
-                    .control_sig = PCNT_CTRL_CH0_IN1_IDX,
-                    .pulse_sig = PCNT_SIG_CH0_IN1_IDX
+                    .channels = {
+                        [0] = {
+                            .control_sig = PCNT_CTRL_CH0_IN1_IDX,
+                            .pulse_sig = PCNT_SIG_CH0_IN1_IDX
+                        },
+                        [1] = {
+                            .control_sig = PCNT_CTRL_CH1_IN1_IDX,
+                            .pulse_sig = PCNT_SIG_CH1_IN1_IDX
+                        }
+                    }
                 },
-                [1] = {
-                    .control_sig = PCNT_CTRL_CH1_IN1_IDX,
-                    .pulse_sig = PCNT_SIG_CH1_IN1_IDX
-                }
-            }
-        },
-        [2] = {
-            .channels = {
-                [0] = {
-                    .control_sig = PCNT_CTRL_CH0_IN2_IDX,
-                    .pulse_sig = PCNT_SIG_CH0_IN2_IDX
+                [2] = {
+                    .channels = {
+                        [0] = {
+                            .control_sig = PCNT_CTRL_CH0_IN2_IDX,
+                            .pulse_sig = PCNT_SIG_CH0_IN2_IDX
+                        },
+                        [1] = {
+                            .control_sig = PCNT_CTRL_CH1_IN2_IDX,
+                            .pulse_sig = PCNT_SIG_CH1_IN2_IDX
+                        }
+                    }
                 },
-                [1] = {
-                    .control_sig = PCNT_CTRL_CH1_IN2_IDX,
-                    .pulse_sig = PCNT_SIG_CH1_IN2_IDX
-                }
-            }
-        },
-        [3] = {
-            .channels = {
-                [0] = {
-                    .control_sig = PCNT_CTRL_CH0_IN3_IDX,
-                    .pulse_sig = PCNT_SIG_CH0_IN3_IDX
-                },
-                [1] = {
-                    .control_sig = PCNT_CTRL_CH1_IN3_IDX,
-                    .pulse_sig = PCNT_SIG_CH1_IN3_IDX
+                [3] = {
+                    .channels = {
+                        [0] = {
+                            .control_sig = PCNT_CTRL_CH0_IN3_IDX,
+                            .pulse_sig = PCNT_SIG_CH0_IN3_IDX
+                        },
+                        [1] = {
+                            .control_sig = PCNT_CTRL_CH1_IN3_IDX,
+                            .pulse_sig = PCNT_SIG_CH1_IN3_IDX
+                        }
+                    }
                 }
             }
         }

components/soc/include/soc/pcnt_periph.h

@@ -1,4 +1,4 @@
-// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
+// Copyright 2019-2020 Espressif Systems (Shanghai) PTE LTD
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
@@ -27,12 +27,14 @@ extern "C" {
 typedef struct {
     struct {
         struct {
-            const uint32_t pulse_sig;
-            const uint32_t control_sig;
-        } channels[SOC_PCNT_UNIT_CHANNEL_NUM];
-    } units[SOC_PCNT_UNIT_NUM];
-    const uint32_t irq;
-    const periph_module_t module;
+            struct {
+                const uint32_t pulse_sig;
+                const uint32_t control_sig;
+            } channels[SOC_PCNT_CHANNELS_PER_UNIT];
+        } units[SOC_PCNT_UNITS_PER_GROUP];
+        const uint32_t irq;
+        const periph_module_t module;
+    } groups[SOC_PCNT_GROUPS];
 } pcnt_signal_conn_t;
 
 extern const pcnt_signal_conn_t pcnt_periph_signals;