Merge branch 'feature/esp32h2_gpio_support' into 'master'

gpio: Add support for esp32h2

Closes IDF-6227, IDF-6388, IDF-6403, and IDF-6676

See merge request espressif/esp-idf!21986

components/driver/test_apps/gpio/main/test_gpio.c

@@ -844,7 +844,7 @@ TEST_CASE("GPIO_USB_DP_pin_pullup_disable_test", "[gpio]")
 }
 #endif //SOC_USB_SERIAL_JTAG_SUPPORTED
 
-#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32C6, ESP32H2) // TODO: IDF-5348 Remove when light sleep is supported on ESP32C6
+#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32C6, ESP32H2) // TODO: IDF-5348, IDF-6267 Remove when light sleep is supported
 // Ignored in CI because it needs manually connect TEST_GPIO_INPUT_LEVEL_LOW_PIN to 3.3v to wake up from light sleep
 TEST_CASE("GPIO_light_sleep_wake_up_test", "[gpio][ignore]")
 {
@@ -861,4 +861,4 @@ TEST_CASE("GPIO_light_sleep_wake_up_test", "[gpio][ignore]")
     printf("Waked up from light sleep\n");
     TEST_ASSERT(esp_sleep_get_wakeup_cause() == ESP_SLEEP_WAKEUP_GPIO);
 }
-#endif //!TEMPORARY_DISABLED_FOR_TARGETS(ESP32C6, ESP32H2)
+#endif //!TEMPORARY_DISABLED_FOR_TARGETS(...)

components/driver/test_apps/gpio/main/test_gpio.h

@@ -31,16 +31,11 @@ extern "C" {
 #define TEST_GPIO_EXT_IN_IO                (21)
 #define TEST_GPIO_INPUT_LEVEL_LOW_PIN      (1)
 #define TEST_GPIO_SIGNAL_IDX               (SIG_IN_FUNC208_IDX)
-#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2
+#else
 #define TEST_GPIO_EXT_OUT_IO               (2)
 #define TEST_GPIO_EXT_IN_IO                (3)
 #define TEST_GPIO_INPUT_LEVEL_LOW_PIN      (1)
 #define TEST_GPIO_SIGNAL_IDX               (SIG_IN_FUNC97_IDX)
-#elif CONFIG_IDF_TARGET_ESP32H4
-#define TEST_GPIO_EXT_OUT_IO               (6)
-#define TEST_GPIO_EXT_IN_IO                (7)
-#define TEST_GPIO_INPUT_LEVEL_LOW_PIN      (1)
-#define TEST_GPIO_SIGNAL_IDX               (SIG_IN_FUNC97_IDX)
 #endif
 
 #ifdef __cplusplus

components/driver/test_apps/gpio/pytest_gpio.py

@@ -20,6 +20,7 @@ def test_gpio(dut: IdfDut) -> None:
 @pytest.mark.esp32
 @pytest.mark.esp32c3
 @pytest.mark.esp32c6
+@pytest.mark.esp32h2
 @pytest.mark.esp32s2
 @pytest.mark.esp32s3
 @pytest.mark.generic
@@ -31,6 +32,7 @@ def test_legacy_sigma_delta(dut: IdfDut) -> None:
 @pytest.mark.esp32
 @pytest.mark.esp32s2
 @pytest.mark.esp32s3
+@pytest.mark.esp32c6
 @pytest.mark.generic
 @pytest.mark.parametrize('config', CONFIGS, indirect=True)
 def test_rtc_io(dut: IdfDut) -> None:

components/esp_hw_support/sleep_modes.c

@@ -1013,7 +1013,7 @@ touch_pad_t esp_sleep_get_touchpad_wakeup_status(void)
 
 bool esp_sleep_is_valid_wakeup_gpio(gpio_num_t gpio_num)
 {
-#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED || CONFIG_IDF_TARGET_ESP32C6 // TODO: IDF-6027 C6 IO0-7 meet both conditions here
+#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
     return RTC_GPIO_IS_VALID_GPIO(gpio_num);
 #else
     return GPIO_IS_DEEP_SLEEP_WAKEUP_VALID_GPIO(gpio_num);

components/hal/esp32c6/include/hal/gpio_ll.h

@@ -19,13 +19,13 @@
 #include "soc/soc.h"
 #include "soc/gpio_periph.h"
 #include "soc/gpio_struct.h"
-#include "soc/lp_aon_reg.h"
-#include "soc/lp_io_struct.h"
+#include "soc/lp_aon_struct.h"
 #include "soc/pmu_reg.h"
 #include "soc/usb_serial_jtag_reg.h"
 #include "soc/pcr_struct.h"
 #include "soc/clk_tree_defs.h"
 #include "hal/gpio_types.h"
+#include "hal/misc.h"
 #include "hal/assert.h"
 
 #ifdef __cplusplus
@@ -84,6 +84,7 @@ static inline void gpio_ll_pulldown_dis(gpio_dev_t *hw, uint32_t gpio_num)
     // USB DP pin is default to PU enabled
     // Note that esp32c6 has supported USB_EXCHG_PINS feature. If this efuse is burnt, the gpio pin
     // which should be checked is USB_DM_GPIO_NUM instead.
+    // TODO: read the specific efuse with efuse_ll.h
     if (gpio_num == USB_DP_GPIO_NUM) {
         SET_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_PAD_PULL_OVERRIDE);
         CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_DP_PULLUP);
@@ -381,7 +382,7 @@ static inline void gpio_ll_deep_sleep_hold_dis(gpio_dev_t *hw)
   */
 static inline void gpio_ll_hold_en(gpio_dev_t *hw, uint32_t gpio_num)
 {
-    SET_PERI_REG_MASK(LP_AON_GPIO_HOLD0_REG, GPIO_HOLD_MASK[gpio_num]);
+    LP_AON.gpio_hold0.gpio_hold0 |= GPIO_HOLD_MASK[gpio_num];
 }
 
 /**
@@ -392,7 +393,7 @@ static inline void gpio_ll_hold_en(gpio_dev_t *hw, uint32_t gpio_num)
   */
 static inline void gpio_ll_hold_dis(gpio_dev_t *hw, uint32_t gpio_num)
 {
-    CLEAR_PERI_REG_MASK(LP_AON_GPIO_HOLD0_REG, GPIO_HOLD_MASK[gpio_num]);
+    LP_AON.gpio_hold0.gpio_hold0 &= ~GPIO_HOLD_MASK[gpio_num];
 }
 
 /**
@@ -598,9 +599,21 @@ static inline void gpio_ll_sleep_output_enable(gpio_dev_t *hw, uint32_t gpio_num
 static inline void gpio_ll_deepsleep_wakeup_enable(gpio_dev_t *hw, uint32_t gpio_num, gpio_int_type_t intr_type)
 {
     HAL_ASSERT(gpio_num <= GPIO_NUM_7 && "gpio larger than 7 does not support deep sleep wake-up function");
-    // On ESP32-C6, (lp_io pin number) == (gpio pin number)
-    LP_IO.pin[gpio_num].wakeup_enable = 1;
-    LP_IO.pin[gpio_num].int_type = intr_type;
+
+    LP_AON.ext_wakeup_cntl.ext_wakeup_filter = 1;
+
+    uint32_t wakeup_sel_mask = HAL_FORCE_READ_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_sel);
+    wakeup_sel_mask |= BIT(gpio_num);
+    HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_sel, wakeup_sel_mask);
+
+    bool trigger_level = (intr_type == GPIO_INTR_LOW_LEVEL) ? 0 : 1;
+    uint32_t wakeup_level_mask = HAL_FORCE_READ_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_lv);
+    if (trigger_level) {
+        wakeup_level_mask |= BIT(gpio_num);
+    } else {
+        wakeup_level_mask &= ~BIT(gpio_num);
+    }
+    HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_lv, wakeup_level_mask);
 }
 
 /**
@@ -612,9 +625,10 @@ static inline void gpio_ll_deepsleep_wakeup_enable(gpio_dev_t *hw, uint32_t gpio
 static inline void gpio_ll_deepsleep_wakeup_disable(gpio_dev_t *hw, uint32_t gpio_num)
 {
     HAL_ASSERT(gpio_num <= GPIO_NUM_7 && "gpio larger than 7 does not support deep sleep wake-up function");
-    // On ESP32-C6, (lp_io pin number) == (gpio pin number)
-    LP_IO.pin[gpio_num].wakeup_enable = 0;
-    LP_IO.pin[gpio_num].int_type = 0; // Disable io interrupt
+
+    uint32_t wakeup_sel_mask = HAL_FORCE_READ_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_sel);
+    wakeup_sel_mask &= ~BIT(gpio_num);
+    HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_sel, wakeup_sel_mask);
 }
 
 /**
@@ -627,8 +641,9 @@ static inline void gpio_ll_deepsleep_wakeup_disable(gpio_dev_t *hw, uint32_t gpi
 static inline bool gpio_ll_deepsleep_wakeup_is_enabled(gpio_dev_t *hw, uint32_t gpio_num)
 {
     HAL_ASSERT(gpio_num <= GPIO_NUM_7 && "gpio larger than 7 does not support deep sleep wake-up function");
-    // On ESP32-C6, (lp_io pin number) == (gpio pin number)
-    return LP_IO.pin[gpio_num].wakeup_enable;
+
+    uint32_t wakeup_sel_mask = HAL_FORCE_READ_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_sel);
+    return wakeup_sel_mask & BIT(gpio_num);
 }
 
 #ifdef __cplusplus

components/hal/esp32c6/include/hal/rtc_io_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -366,27 +366,6 @@ static inline void rtcio_ll_disable_sleep_setting(gpio_num_t gpio_num)
     LP_IO.gpio[gpio_num].slp_sel = 0;
 }
 
-/**
- * Set specific logic level on an RTC IO pin as a wakeup trigger.
- *
- * @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
- * @param level Logic level (0)
- */
-static inline void rtcio_ll_ext0_set_wakeup_pin(int rtcio_num, int level)
-{
-    uint32_t wakeup_sel_mask = HAL_FORCE_READ_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_sel);
-    wakeup_sel_mask |= BIT(rtcio_num);
-    HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_sel, wakeup_sel_mask);
-
-    uint32_t wakeup_level_mask = HAL_FORCE_READ_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_lv);
-    if (level) {
-        wakeup_level_mask |= BIT(rtcio_num);
-    } else {
-        wakeup_level_mask &= ~BIT(rtcio_num);
-    }
-    HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_lv, wakeup_level_mask);
-}
-
 #ifdef __cplusplus
 }
 #endif

components/hal/esp32h2/include/hal/gpio_ll.h

@@ -14,32 +14,24 @@
 
 #pragma once
 
+#include <stdlib.h>
+#include <stdbool.h>
 #include "soc/soc.h"
 #include "soc/gpio_periph.h"
 #include "soc/gpio_struct.h"
-#include "soc/lp_aon_reg.h"
+#include "soc/lp_aon_struct.h"
 #include "soc/pmu_reg.h"
+#include "soc/usb_serial_jtag_reg.h"
+#include "soc/pcr_struct.h"
+#include "soc/clk_tree_defs.h"
 #include "hal/gpio_types.h"
-#include <stdlib.h>
-#include <stdbool.h>
+#include "hal/misc.h"
+#include "hal/assert.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-// ESP32H2-TODO: comment some code, please add support on gpio, IDF-6227
-
-/*
- * The following defines are used to disable USB JTAG when pins 18 and pins 19
- * are set to be used as GPIO.
- * See gpio_pad_select_gpio() below.
- *
- * TODO: Delete these definitions once the USB device registers definition is
- * merged.
- */
-#define USB_DEVICE_CONF0_REG        (0x60043018)
-#define USB_DEVICE_USB_PAD_ENABLE   (BIT(14))
-
 // Get GPIO hardware instance with giving gpio num
 #define GPIO_LL_GET_HW(num) (((num) == 0) ? (&GPIO) : NULL)
 
@@ -53,7 +45,7 @@ extern "C" {
   */
 static inline void gpio_ll_pullup_en(gpio_dev_t *hw, gpio_num_t gpio_num)
 {
-    REG_SET_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PU);
+    REG_SET_BIT(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_PU);
 }
 
 /**
@@ -62,9 +54,10 @@ static inline void gpio_ll_pullup_en(gpio_dev_t *hw, gpio_num_t gpio_num)
   * @param hw Peripheral GPIO hardware instance address.
   * @param gpio_num GPIO number
   */
+__attribute__((always_inline))
 static inline void gpio_ll_pullup_dis(gpio_dev_t *hw, gpio_num_t gpio_num)
 {
-    REG_CLR_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PU);
+    REG_CLR_BIT(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_PU);
 }
 
 /**
@@ -75,7 +68,7 @@ static inline void gpio_ll_pullup_dis(gpio_dev_t *hw, gpio_num_t gpio_num)
   */
 static inline void gpio_ll_pulldown_en(gpio_dev_t *hw, gpio_num_t gpio_num)
 {
-    REG_SET_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PD);
+    REG_SET_BIT(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_PD);
 }
 
 /**
@@ -84,9 +77,19 @@ static inline void gpio_ll_pulldown_en(gpio_dev_t *hw, gpio_num_t gpio_num)
   * @param hw Peripheral GPIO hardware instance address.
   * @param gpio_num GPIO number
   */
+__attribute__((always_inline))
 static inline void gpio_ll_pulldown_dis(gpio_dev_t *hw, gpio_num_t gpio_num)
 {
-    REG_CLR_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PD);
+    // The pull-up value of the USB pins are controlled by the pins’ pull-up value together with USB pull-up value
+    // USB DP pin is default to PU enabled
+    // Note that esp32h2 has supported USB_EXCHG_PINS feature. If this efuse is burnt, the gpio pin
+    // which should be checked is USB_DM_GPIO_NUM instead.
+    // TODO: read the specific efuse with efuse_ll.h
+    if (gpio_num == USB_DP_GPIO_NUM) {
+        SET_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_PAD_PULL_OVERRIDE);
+        CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_DP_PULLUP);
+    }
+    REG_CLR_BIT(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_PD);
 }
 
 /**
@@ -98,8 +101,7 @@ static inline void gpio_ll_pulldown_dis(gpio_dev_t *hw, gpio_num_t gpio_num)
  */
 static inline void gpio_ll_set_intr_type(gpio_dev_t *hw, gpio_num_t gpio_num, gpio_int_type_t intr_type)
 {
-    // hw->pin[gpio_num].int_type = intr_type;
-    // ESP32H2-TODO: IDF-6227 updated struct file not support yet
+    hw->pin[gpio_num].int_type = intr_type;
 }
 
 /**
@@ -112,7 +114,8 @@ static inline void gpio_ll_set_intr_type(gpio_dev_t *hw, gpio_num_t gpio_num, gp
 __attribute__((always_inline))
 static inline void gpio_ll_get_intr_status(gpio_dev_t *hw, uint32_t core_id, uint32_t *status)
 {
-    *status = hw->pcpu_int.val;
+    (void)core_id;
+    *status = hw->pcpu_int.procpu_int;
 }
 
 /**
@@ -137,7 +140,7 @@ static inline void gpio_ll_get_intr_status_high(gpio_dev_t *hw, uint32_t core_id
 __attribute__((always_inline))
 static inline void gpio_ll_clear_intr_status(gpio_dev_t *hw, uint32_t mask)
 {
-    // hw->status_w1tc = mask;
+    hw->status_w1tc.status_w1tc = mask;
 }
 
 /**
@@ -149,7 +152,7 @@ static inline void gpio_ll_clear_intr_status(gpio_dev_t *hw, uint32_t mask)
 __attribute__((always_inline))
 static inline void gpio_ll_clear_intr_status_high(gpio_dev_t *hw, uint32_t mask)
 {
-    // Not supported on H2
+    // Less than 32 GPIOs on ESP32-H2 Do nothing.
 }
 
 /**
@@ -159,16 +162,11 @@ static inline void gpio_ll_clear_intr_status_high(gpio_dev_t *hw, uint32_t mask)
  * @param  core_id Interrupt enabled CPU to corresponding ID
  * @param  gpio_num GPIO number. If you want to enable the interrupt of e.g. GPIO16, gpio_num should be GPIO_NUM_16 (16);
  */
+__attribute__((always_inline))
 static inline void gpio_ll_intr_enable_on_core(gpio_dev_t *hw, uint32_t core_id, gpio_num_t gpio_num)
 {
-// ESP32H2-TODO: IDF-6227 updated struct file not support yet
-#if 0
-    if (core_id == 0) {
-        GPIO.pin[gpio_num].int_ena = GPIO_LL_PRO_CPU_INTR_ENA;     //enable pro cpu intr
-    } else {
-        // GPIO.pin[gpio_num].int_ena = GPIO_APP_CPU_INTR_ENA;     //enable pro cpu intr
-    }
-#endif
+    HAL_ASSERT(core_id == 0 && "target SoC only has a single core");
+    GPIO.pin[gpio_num].int_ena = GPIO_LL_PRO_CPU_INTR_ENA;     //enable pro cpu intr
 }
 
 /**
@@ -177,10 +175,10 @@ static inline void gpio_ll_intr_enable_on_core(gpio_dev_t *hw, uint32_t core_id,
  * @param  hw Peripheral GPIO hardware instance address.
  * @param  gpio_num GPIO number. If you want to disable the interrupt of e.g. GPIO16, gpio_num should be GPIO_NUM_16 (16);
  */
+__attribute__((always_inline))
 static inline void gpio_ll_intr_disable(gpio_dev_t *hw, gpio_num_t gpio_num)
 {
-    // ESP32H2-TODO: IDF-6227 updated struct file not support yet
-    // hw->pin[gpio_num].int_ena = 0;                             //disable GPIO intr
+    hw->pin[gpio_num].int_ena = 0;                             //disable GPIO intr
 }
 
 /**
@@ -189,9 +187,10 @@ static inline void gpio_ll_intr_disable(gpio_dev_t *hw, gpio_num_t gpio_num)
   * @param hw Peripheral GPIO hardware instance address.
   * @param gpio_num GPIO number
   */
+__attribute__((always_inline))
 static inline void gpio_ll_input_disable(gpio_dev_t *hw, gpio_num_t gpio_num)
 {
-    PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[gpio_num]);
+    PIN_INPUT_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
 }
 
 /**
@@ -202,7 +201,29 @@ static inline void gpio_ll_input_disable(gpio_dev_t *hw, gpio_num_t gpio_num)
   */
 static inline void gpio_ll_input_enable(gpio_dev_t *hw, gpio_num_t gpio_num)
 {
-    PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[gpio_num]);
+    PIN_INPUT_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
+}
+
+/**
+ * @brief Enable GPIO pin filter
+ *
+ * @param hw Peripheral GPIO hardware instance address.
+ * @param gpio_num GPIO number of the pad.
+ */
+static inline void gpio_ll_pin_filter_enable(gpio_dev_t *hw, uint32_t gpio_num)
+{
+    PIN_FILTER_EN(IO_MUX_GPIO0_REG + (gpio_num * 4));
+}
+
+/**
+ * @brief Disable GPIO pin filter
+ *
+ * @param hw Peripheral GPIO hardware instance address.
+ * @param gpio_num GPIO number of the pad.
+ */
+static inline void gpio_ll_pin_filter_disable(gpio_dev_t *hw, uint32_t gpio_num)
+{
+    PIN_FILTER_DIS(IO_MUX_GPIO0_REG + (gpio_num * 4));
 }
 
 /**
@@ -211,12 +232,12 @@ static inline void gpio_ll_input_enable(gpio_dev_t *hw, gpio_num_t gpio_num)
   * @param hw Peripheral GPIO hardware instance address.
   * @param gpio_num GPIO number
   */
+__attribute__((always_inline))
 static inline void gpio_ll_output_disable(gpio_dev_t *hw, gpio_num_t gpio_num)
 {
-    // hw->enable_w1tc = (0x1 << gpio_num);
-    // // Ensure no other output signal is routed via GPIO matrix to this pin
-    // REG_WRITE(GPIO_FUNC0_OUT_SEL_CFG_REG + (gpio_num * 4),
-    //           SIG_GPIO_OUT_IDX);
+    hw->enable_w1tc.enable_w1tc = (0x1 << gpio_num);
+    // Ensure no other output signal is routed via GPIO matrix to this pin
+    REG_WRITE(GPIO_FUNC0_OUT_SEL_CFG_REG + (gpio_num * 4), SIG_GPIO_OUT_IDX);
 }
 
 /**
@@ -227,7 +248,7 @@ static inline void gpio_ll_output_disable(gpio_dev_t *hw, gpio_num_t gpio_num)
   */
 static inline void gpio_ll_output_enable(gpio_dev_t *hw, gpio_num_t gpio_num)
 {
-    // hw->enable_w1ts = (0x1 << gpio_num);
+    hw->enable_w1ts.enable_w1ts = (0x1 << gpio_num);
 }
 
 /**
@@ -238,8 +259,7 @@ static inline void gpio_ll_output_enable(gpio_dev_t *hw, gpio_num_t gpio_num)
   */
 static inline void gpio_ll_od_disable(gpio_dev_t *hw, gpio_num_t gpio_num)
 {
-    // ESP32H2-TODO: IDF-6227 updated struct file not support yet
-    // hw->pin[gpio_num].pad_driver = 0;
+    hw->pin[gpio_num].pad_driver = 0;
 }
 
 /**
@@ -250,8 +270,7 @@ static inline void gpio_ll_od_disable(gpio_dev_t *hw, gpio_num_t gpio_num)
   */
 static inline void gpio_ll_od_enable(gpio_dev_t *hw, gpio_num_t gpio_num)
 {
-    // ESP32H2-TODO: IDF-6227 updated struct file not support yet
-    // hw->pin[gpio_num].pad_driver = 1;
+    hw->pin[gpio_num].pad_driver = 1;
 }
 
 /**
@@ -264,11 +283,11 @@ static inline void gpio_ll_od_enable(gpio_dev_t *hw, gpio_num_t gpio_num)
 __attribute__((always_inline))
 static inline void gpio_ll_set_level(gpio_dev_t *hw, gpio_num_t gpio_num, uint32_t level)
 {
-    // if (level) {
-    //     hw->out_w1ts = (1 << gpio_num);
-    // } else {
-    //     hw->out_w1tc = (1 << gpio_num);
-    // }
+    if (level) {
+        hw->out_w1ts.out_w1ts = (1 << gpio_num);
+    } else {
+        hw->out_w1tc.out_w1tc = (1 << gpio_num);
+    }
 }
 
 /**
@@ -285,7 +304,7 @@ static inline void gpio_ll_set_level(gpio_dev_t *hw, gpio_num_t gpio_num, uint32
  */
 static inline int gpio_ll_get_level(gpio_dev_t *hw, gpio_num_t gpio_num)
 {
-    return 0;//(hw->in >> gpio_num) & 0x1;
+    return (hw->in.in_data_next >> gpio_num) & 0x1;
 }
 
 /**
@@ -297,11 +316,7 @@ static inline int gpio_ll_get_level(gpio_dev_t *hw, gpio_num_t gpio_num)
  */
 static inline void gpio_ll_wakeup_enable(gpio_dev_t *hw, gpio_num_t gpio_num)
 {
-// ESP32H2-TODO: IDF-6227 updated struct file not support yet
-#if 0
-    hw->pin[gpio_num].int_type = intr_type;
     hw->pin[gpio_num].wakeup_enable = 0x1;
-#endif
 }
 
 /**
@@ -312,8 +327,7 @@ static inline void gpio_ll_wakeup_enable(gpio_dev_t *hw, gpio_num_t gpio_num)
  */
 static inline void gpio_ll_wakeup_disable(gpio_dev_t *hw, gpio_num_t gpio_num)
 {
-    // ESP32H2-TODO: IDF-6227 updated struct file not support yet
-    // hw->pin[gpio_num].wakeup_enable = 0;
+    hw->pin[gpio_num].wakeup_enable = 0;
 }
 
 /**
@@ -325,7 +339,7 @@ static inline void gpio_ll_wakeup_disable(gpio_dev_t *hw, gpio_num_t gpio_num)
   */
 static inline void gpio_ll_set_drive_capability(gpio_dev_t *hw, gpio_num_t gpio_num, gpio_drive_cap_t strength)
 {
-    SET_PERI_REG_BITS(GPIO_PIN_MUX_REG[gpio_num], FUN_DRV_V, strength, FUN_DRV_S);
+    SET_PERI_REG_BITS(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_DRV_V, strength, FUN_DRV_S);
 }
 
 /**
@@ -337,7 +351,7 @@ static inline void gpio_ll_set_drive_capability(gpio_dev_t *hw, gpio_num_t gpio_
   */
 static inline void gpio_ll_get_drive_capability(gpio_dev_t *hw, gpio_num_t gpio_num, gpio_drive_cap_t *strength)
 {
-    *strength = (gpio_drive_cap_t)GET_PERI_REG_BITS2(GPIO_PIN_MUX_REG[gpio_num], FUN_DRV_V, FUN_DRV_S);
+    *strength = (gpio_drive_cap_t)GET_PERI_REG_BITS2(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_DRV_V, FUN_DRV_S);
 }
 
 /**
@@ -347,7 +361,7 @@ static inline void gpio_ll_get_drive_capability(gpio_dev_t *hw, gpio_num_t gpio_
   */
 static inline void gpio_ll_deep_sleep_hold_en(gpio_dev_t *hw)
 {
-    // ESP32H2 has removed deepsleep and replace with software backup sleep
+    REG_SET_BIT(PMU_IMM_PAD_HOLD_ALL_REG, PMU_TIE_HIGH_HP_PAD_HOLD_ALL);
 }
 
 /**
@@ -357,7 +371,7 @@ static inline void gpio_ll_deep_sleep_hold_en(gpio_dev_t *hw)
   */
 static inline void gpio_ll_deep_sleep_hold_dis(gpio_dev_t *hw)
 {
-    // ESP32H2 has removed deepsleep and replace with software backup sleep
+    REG_SET_BIT(PMU_IMM_PAD_HOLD_ALL_REG, PMU_TIE_LOW_HP_PAD_HOLD_ALL);
 }
 
 /**
@@ -368,11 +382,7 @@ static inline void gpio_ll_deep_sleep_hold_dis(gpio_dev_t *hw)
   */
 static inline void gpio_ll_hold_en(gpio_dev_t *hw, gpio_num_t gpio_num)
 {
-    if (gpio_num <32){
-        SET_PERI_REG_MASK(LP_AON_GPIO_HOLD0_REG, GPIO_HOLD_MASK[gpio_num]);
-    } else if (gpio_num <= MAX_PAD_GPIO_NUM){
-        SET_PERI_REG_MASK(LP_AON_GPIO_HOLD1_REG, GPIO_HOLD_MASK[gpio_num]);
-    }
+    LP_AON.gpio_hold0.gpio_hold0 |= GPIO_HOLD_MASK[gpio_num];
 }
 
 /**
@@ -383,11 +393,7 @@ static inline void gpio_ll_hold_en(gpio_dev_t *hw, gpio_num_t gpio_num)
   */
 static inline void gpio_ll_hold_dis(gpio_dev_t *hw, gpio_num_t gpio_num)
 {
-    if (gpio_num <32){
-        CLEAR_PERI_REG_MASK(LP_AON_GPIO_HOLD0_REG, GPIO_HOLD_MASK[gpio_num]);
-    } else if (gpio_num <= MAX_PAD_GPIO_NUM){
-        CLEAR_PERI_REG_MASK(LP_AON_GPIO_HOLD1_REG, GPIO_HOLD_MASK[gpio_num]);
-    }
+    LP_AON.gpio_hold0.gpio_hold0 &= ~GPIO_HOLD_MASK[gpio_num];
 }
 
 /**
@@ -397,10 +403,11 @@ static inline void gpio_ll_hold_dis(gpio_dev_t *hw, gpio_num_t gpio_num)
   * @param gpio_num GPIO number of the pad.
   * @param signal_idx Peripheral signal id to input. One of the ``*_IN_IDX`` signals in ``soc/gpio_sig_map.h``.
   */
+__attribute__((always_inline))
 static inline void gpio_ll_iomux_in(gpio_dev_t *hw, uint32_t gpio, uint32_t signal_idx)
 {
     hw->func_in_sel_cfg[signal_idx].sig_in_sel = 0;
-    PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[gpio]);
+    PIN_INPUT_ENABLE(IO_MUX_GPIO0_REG + (gpio * 4));
 }
 
 /**
@@ -411,12 +418,30 @@ static inline void gpio_ll_iomux_in(gpio_dev_t *hw, uint32_t gpio, uint32_t sign
  */
 static inline void gpio_ll_iomux_func_sel(uint32_t pin_name, uint32_t func)
 {
-    if (pin_name == IO_MUX_GPIO18_REG || pin_name == IO_MUX_GPIO19_REG) {
-        CLEAR_PERI_REG_MASK(USB_DEVICE_CONF0_REG, USB_DEVICE_USB_PAD_ENABLE);
+    // Disable USB Serial JTAG if pins 26 or pins 27 needs to select an IOMUX function
+    if (pin_name == IO_MUX_GPIO26_REG || pin_name == IO_MUX_GPIO27_REG) {
+        CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_USB_PAD_ENABLE);
     }
     PIN_FUNC_SELECT(pin_name, func);
 }
 
+/**
+ * @brief  Select a function for the pin in the IOMUX
+ *
+ * @param  hw Peripheral GPIO hardware instance address.
+ * @param  gpio_num GPIO number
+ * @param  func Function to assign to the pin
+ */
+__attribute__((always_inline))
+static inline void gpio_ll_func_sel(gpio_dev_t *hw, uint8_t gpio_num, uint32_t func)
+{
+    // Disable USB Serial JTAG if pins 26 or pins 27 needs to select an IOMUX function
+    if (gpio_num == USB_DM_GPIO_NUM || gpio_num == USB_DP_GPIO_NUM) {
+        CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_USB_PAD_ENABLE);
+    }
+    PIN_FUNC_SELECT(IO_MUX_GPIO0_REG + (gpio_num * 4), func);
+}
+
 /**
   * @brief Set peripheral output to an GPIO pad through the IOMUX.
   *
@@ -428,47 +453,52 @@ static inline void gpio_ll_iomux_func_sel(uint32_t pin_name, uint32_t func)
   */
 static inline void gpio_ll_iomux_out(gpio_dev_t *hw, uint8_t gpio_num, int func, uint32_t oen_inv)
 {
-#if 0
     hw->func_out_sel_cfg[gpio_num].oen_sel = 0;
     hw->func_out_sel_cfg[gpio_num].oen_inv_sel = oen_inv;
-    gpio_ll_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_num], func);
-#endif
+    gpio_ll_iomux_func_sel(IO_MUX_GPIO0_REG + (gpio_num * 4), func);
 }
 
-static inline void gpio_ll_force_hold_all(void)
-{
-    REG_SET_BIT(PMU_IMM_PAD_HOLD_ALL_REG, PMU_TIE_HIGH_HP_PAD_HOLD_ALL);
-    REG_SET_BIT(PMU_IMM_PAD_HOLD_ALL_REG, PMU_TIE_HIGH_LP_PAD_HOLD_ALL);
-}
-
-static inline void gpio_ll_force_unhold_all(void)
-{
-    REG_SET_BIT(PMU_IMM_PAD_HOLD_ALL_REG, PMU_TIE_LOW_HP_PAD_HOLD_ALL);
-    REG_SET_BIT(PMU_IMM_PAD_HOLD_ALL_REG, PMU_TIE_LOW_LP_PAD_HOLD_ALL);
+/**
+ * @brief Set clock source of IO MUX module
+ *
+ * @param src IO MUX clock source (only a subset of soc_module_clk_t values are valid)
+ */
+static inline void gpio_ll_iomux_set_clk_src(soc_module_clk_t src)
+{
+    switch (src) {
+    case SOC_MOD_CLK_XTAL:
+        PCR.iomux_clk_conf.iomux_func_clk_sel = 0;
+        break;
+    case SOC_MOD_CLK_PLL_F48M:
+        PCR.iomux_clk_conf.iomux_func_clk_sel = 2;
+        break;
+    default:
+        // Unsupported IO_MUX clock source
+        HAL_ASSERT(false);
+    }
 }
 
 /**
-  * @brief Enable GPIO pin used for wakeup from sleep.
+  * @brief Enable GPIO pin to use sleep mode pin functions during light sleep.
   *
   * @param hw Peripheral GPIO hardware instance address.
   * @param gpio_num GPIO number
   */
 static inline void gpio_ll_sleep_sel_en(gpio_dev_t *hw, gpio_num_t gpio_num)
 {
-    // ESP32H2-TODO: IDF-6227
-    // PIN_SLP_SEL_ENABLE(GPIO_PIN_MUX_REG[gpio_num]);
+    PIN_SLP_SEL_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
 }
 
 /**
-  * @brief Disable GPIO pin used for wakeup from sleep.
+  * @brief Disable GPIO pin to use sleep mode pin functions during light sleep.
+  * Pin functions remains the same in both normal execution and in light-sleep mode.
   *
   * @param hw Peripheral GPIO hardware instance address.
   * @param gpio_num GPIO number
   */
 static inline void gpio_ll_sleep_sel_dis(gpio_dev_t *hw, gpio_num_t gpio_num)
 {
-    // ESP32H2-TODO: IDF-6227
-    // PIN_SLP_SEL_DISABLE(GPIO_PIN_MUX_REG[gpio_num]);
+    PIN_SLP_SEL_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
 }
 
 /**
@@ -479,8 +509,7 @@ static inline void gpio_ll_sleep_sel_dis(gpio_dev_t *hw, gpio_num_t gpio_num)
   */
 static inline void gpio_ll_sleep_pullup_dis(gpio_dev_t *hw, gpio_num_t gpio_num)
 {
-    // ESP32H2-TODO: IDF-6227
-    // PIN_SLP_PULLUP_DISABLE(GPIO_PIN_MUX_REG[gpio_num]);
+    PIN_SLP_PULLUP_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
 }
 
 /**
@@ -491,8 +520,7 @@ static inline void gpio_ll_sleep_pullup_dis(gpio_dev_t *hw, gpio_num_t gpio_num)
   */
 static inline void gpio_ll_sleep_pullup_en(gpio_dev_t *hw, gpio_num_t gpio_num)
 {
-    // ESP32H2-TODO: IDF-6227
-    // PIN_SLP_PULLUP_ENABLE(GPIO_PIN_MUX_REG[gpio_num]);
+    PIN_SLP_PULLUP_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
 }
 
 /**
@@ -503,8 +531,7 @@ static inline void gpio_ll_sleep_pullup_en(gpio_dev_t *hw, gpio_num_t gpio_num)
   */
 static inline void gpio_ll_sleep_pulldown_en(gpio_dev_t *hw, gpio_num_t gpio_num)
 {
-    // ESP32H2-TODO: IDF-6227
-    // PIN_SLP_PULLDOWN_ENABLE(GPIO_PIN_MUX_REG[gpio_num]);
+    PIN_SLP_PULLDOWN_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
 }
 
 /**
@@ -515,8 +542,7 @@ static inline void gpio_ll_sleep_pulldown_en(gpio_dev_t *hw, gpio_num_t gpio_num
   */
 static inline void gpio_ll_sleep_pulldown_dis(gpio_dev_t *hw, gpio_num_t gpio_num)
 {
-    // ESP32H2-TODO: IDF-6227
-    // PIN_SLP_PULLDOWN_DISABLE(GPIO_PIN_MUX_REG[gpio_num]);
+    PIN_SLP_PULLDOWN_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
 }
 
 /**
@@ -527,8 +553,7 @@ static inline void gpio_ll_sleep_pulldown_dis(gpio_dev_t *hw, gpio_num_t gpio_nu
   */
 static inline void gpio_ll_sleep_input_disable(gpio_dev_t *hw, gpio_num_t gpio_num)
 {
-    // ESP32H2-TODO: IDF-6227
-    // PIN_SLP_INPUT_DISABLE(GPIO_PIN_MUX_REG[gpio_num]);
+    PIN_SLP_INPUT_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
 }
 
 /**
@@ -539,8 +564,7 @@ static inline void gpio_ll_sleep_input_disable(gpio_dev_t *hw, gpio_num_t gpio_n
   */
 static inline void gpio_ll_sleep_input_enable(gpio_dev_t *hw, gpio_num_t gpio_num)
 {
-    // ESP32H2-TODO: IDF-6227
-    // PIN_SLP_INPUT_ENABLE(GPIO_PIN_MUX_REG[gpio_num]);
+    PIN_SLP_INPUT_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
 }
 
 /**
@@ -551,8 +575,7 @@ static inline void gpio_ll_sleep_input_enable(gpio_dev_t *hw, gpio_num_t gpio_nu
   */
 static inline void gpio_ll_sleep_output_disable(gpio_dev_t *hw, gpio_num_t gpio_num)
 {
-    // ESP32H2-TODO: IDF-6227
-    // PIN_SLP_OUTPUT_DISABLE(GPIO_PIN_MUX_REG[gpio_num]);
+    PIN_SLP_OUTPUT_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
 }
 
 /**
@@ -563,8 +586,7 @@ static inline void gpio_ll_sleep_output_disable(gpio_dev_t *hw, gpio_num_t gpio_
   */
 static inline void gpio_ll_sleep_output_enable(gpio_dev_t *hw, gpio_num_t gpio_num)
 {
-    // ESP32H2-TODO: IDF-6227
-    // PIN_SLP_OUTPUT_ENABLE(GPIO_PIN_MUX_REG[gpio_num]);
+    PIN_SLP_OUTPUT_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
 }
 
 /**
@@ -576,11 +598,23 @@ static inline void gpio_ll_sleep_output_enable(gpio_dev_t *hw, gpio_num_t gpio_n
  */
 static inline void gpio_ll_deepsleep_wakeup_enable(gpio_dev_t *hw, gpio_num_t gpio_num, gpio_int_type_t intr_type)
 {
-    if (gpio_num > GPIO_NUM_5) {
-        abort(); // gpio lager than 5 doesn't support.
+    HAL_ASSERT((gpio_num >= GPIO_NUM_7 && gpio_num <= GPIO_NUM_14) &&
+               "only gpio7~14 support deep sleep wake-up function");
+
+    LP_AON.ext_wakeup_cntl.ext_wakeup_filter = 1;
+
+    uint32_t wakeup_sel_mask = HAL_FORCE_READ_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_sel);
+    wakeup_sel_mask |= BIT(gpio_num - 7);
+    HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_sel, wakeup_sel_mask);
+
+    bool trigger_level = (intr_type == GPIO_INTR_LOW_LEVEL) ? 0 : 1;
+    uint32_t wakeup_level_mask = HAL_FORCE_READ_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_lv);
+    if (trigger_level) {
+        wakeup_level_mask |= BIT(gpio_num - 7);
+    } else {
+        wakeup_level_mask &= ~BIT(gpio_num - 7);
     }
-    // SET_PERI_REG_MASK( LP_IO_PIN0_REG + 0x4 * gpio_num, LP_IO_LP_GPIO0_WAKEUP_ENABLE);
-    // REG_SET_FIELD( LP_IO_PIN0_REG + 0x4 * gpio_num, LP_IO_LP_GPIO0_INT_TYPE, intr_type);
+    HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_lv, wakeup_level_mask);
 }
 
 /**
@@ -591,12 +625,12 @@ static inline void gpio_ll_deepsleep_wakeup_enable(gpio_dev_t *hw, gpio_num_t gp
  */
 static inline void gpio_ll_deepsleep_wakeup_disable(gpio_dev_t *hw, gpio_num_t gpio_num)
 {
-    if (gpio_num > GPIO_NUM_5) {
-        abort(); // gpio lager than 5 doesn't support.
-    }
-    // ESP32H2 LP_IO check: IDF-6403
-    // CLEAR_PERI_REG_MASK(LP_IO_PIN0_REG + 0x4 * gpio_num, LP_IO_LP_GPIO0_WAKEUP_ENABLE);
-    // CLEAR_PERI_REG_MASK(LP_IO_PIN0_REG + 0x4 * gpio_num, LP_IO_LP_GPIO0_INT_TYPE);
+    HAL_ASSERT((gpio_num >= GPIO_NUM_7 && gpio_num <= GPIO_NUM_14) &&
+               "only gpio7~14 support deep sleep wake-up function");
+
+    uint32_t wakeup_sel_mask = HAL_FORCE_READ_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_sel);
+    wakeup_sel_mask &= ~BIT(gpio_num - 7);
+    HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_sel, wakeup_sel_mask);
 }
 
 /**
@@ -608,12 +642,12 @@ static inline void gpio_ll_deepsleep_wakeup_disable(gpio_dev_t *hw, gpio_num_t g
  */
 static inline bool gpio_ll_deepsleep_wakeup_is_enabled(gpio_dev_t *hw, uint32_t gpio_num)
 {
-    // ESP32H2 LP_IO check: IDF-6403
-    // HAL_ASSERT(gpio_num <= GPIO_NUM_7 && "gpio larger than 7 does not support deep sleep wake-up function");
-    // On ESP32-H2, (lp_io pin number) == (gpio pin number)
-    return true;//LP_IO.pin[gpio_num].wakeup_enable;
-}
+    HAL_ASSERT((gpio_num >= GPIO_NUM_7 && gpio_num <= GPIO_NUM_14) &&
+               "only gpio7~14 support deep sleep wake-up function");
 
+    uint32_t wakeup_sel_mask = HAL_FORCE_READ_U32_REG_FIELD(LP_AON.ext_wakeup_cntl, ext_wakeup_sel);
+    return wakeup_sel_mask & BIT(gpio_num - 7);
+}
 
 #ifdef __cplusplus
 }

components/soc/esp32c2/include/soc/Kconfig.soc_caps.in

@@ -227,10 +227,6 @@ config SOC_GPIO_FILTER_CLK_SUPPORT_APB
     bool
     default y
 
-config SOC_GPIO_SUPPORTS_RTC_INDEPENDENT
-    bool
-    default y
-
 config SOC_GPIO_SUPPORT_FORCE_HOLD
     bool
     default y

components/soc/esp32c2/include/soc/soc_caps.h

@@ -111,9 +111,8 @@
 #define SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER 1
 #define SOC_GPIO_FILTER_CLK_SUPPORT_APB    1
 
-// Target has no full RTC IO subsystem, so GPIO is 100% "independent" of RTC
-// On ESP32-C2, Digital IOs have their own registers to control pullup/down capability, independent of RTC registers.
-#define SOC_GPIO_SUPPORTS_RTC_INDEPENDENT   (1)
+// Target has no full RTC IO subsystem, GPIO0~5 remain RTC function (powered by VDD3V3_RTC, and can be used as deep-sleep wakeup pins)
+
 // Force hold is a new function of ESP32-C2
 #define SOC_GPIO_SUPPORT_FORCE_HOLD         (1)
 // GPIO0~5 on ESP32-C2 can support chip deep sleep wakeup

components/soc/esp32c3/include/soc/Kconfig.soc_caps.in

@@ -319,10 +319,6 @@ config SOC_GPIO_FILTER_CLK_SUPPORT_APB
     bool
     default y
 
-config SOC_GPIO_SUPPORTS_RTC_INDEPENDENT
-    bool
-    default y
-
 config SOC_GPIO_SUPPORT_FORCE_HOLD
     bool
     default y

components/soc/esp32c3/include/soc/soc_caps.h

@@ -149,9 +149,8 @@
 #define SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER 1
 #define SOC_GPIO_FILTER_CLK_SUPPORT_APB 1
 
-// Target has no full RTC IO subsystem, so GPIO is 100% "independent" of RTC
-// On ESP32-C3, Digital IOs have their own registers to control pullup/down capability, independent of RTC registers.
-#define SOC_GPIO_SUPPORTS_RTC_INDEPENDENT       (1)
+// Target has no full RTC IO subsystem, GPIO0~5 remain RTC function (powered by VDD3V3_RTC, and can be used as deep-sleep wakeup pins)
+
 // Force hold is a new function of ESP32-C3
 #define SOC_GPIO_SUPPORT_FORCE_HOLD         (1)
 // GPIO0~5 on ESP32C3 can support chip deep sleep wakeup

components/soc/esp32c6/include/soc/clkout_channel.h

@@ -1,12 +1,8 @@
 /*
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
-
-#ifndef _SOC_CLKOUT_CHANNEL_H
-#define _SOC_CLKOUT_CHANNEL_H
+#pragma once
 
 // ESP32C6 CLKOUT signals has no corresponding iomux pins
-
-#endif

components/soc/esp32h2/gpio_periph.c

@@ -1,12 +1,12 @@
 /*
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
 #include "soc/gpio_periph.h"
 
-const uint32_t GPIO_PIN_MUX_REG[SOC_GPIO_PIN_COUNT] = {
+const uint32_t GPIO_PIN_MUX_REG[] = {
     IO_MUX_GPIO0_REG,
     IO_MUX_GPIO1_REG,
     IO_MUX_GPIO2_REG,
@@ -37,7 +37,9 @@ const uint32_t GPIO_PIN_MUX_REG[SOC_GPIO_PIN_COUNT] = {
     IO_MUX_GPIO27_REG
 };
 
-const uint32_t GPIO_HOLD_MASK[SOC_GPIO_PIN_COUNT] = {
+_Static_assert(sizeof(GPIO_PIN_MUX_REG) == SOC_GPIO_PIN_COUNT * sizeof(uint32_t), "Invalid size of GPIO_PIN_MUX_REG");
+
+const uint32_t GPIO_HOLD_MASK[] = {
     BIT(0),          //GPIO0   // LP_AON_GPIO_HOLD0_REG
     BIT(1),          //GPIO1
     BIT(2),          //GPIO2
@@ -67,3 +69,5 @@ const uint32_t GPIO_HOLD_MASK[SOC_GPIO_PIN_COUNT] = {
     BIT(26),         //GPIO26
     BIT(27),         //GPIO27
 };
+
+_Static_assert(sizeof(GPIO_HOLD_MASK) == SOC_GPIO_PIN_COUNT * sizeof(uint32_t), "Invalid size of GPIO_HOLD_MASK");

components/soc/esp32h2/include/soc/Kconfig.soc_caps.in

@@ -221,11 +221,7 @@ config SOC_GPIO_PORT
 
 config SOC_GPIO_PIN_COUNT
     int
-    default 31
-
-config SOC_GPIO_SUPPORT_RTC_INDEPENDENT
-    bool
-    default y
+    default 28
 
 config SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP
     bool
@@ -237,7 +233,7 @@ config SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK
 
 config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK
     hex
-    default 0x000000007FFFFF00
+    default 0x000000000FFF807F
 
 config SOC_GPIO_SUPPORT_SLP_SWITCH
     bool

components/soc/esp32h2/include/soc/clkout_channel.h

@@ -1,15 +1,8 @@
 /*
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 #pragma once
 
-//CLKOUT channels
-// ESP32H2-TODO: IDF-6388 please check
-#define CLKOUT_GPIO20_DIRECT_CHANNEL         CLKOUT_CHANNEL_1
-#define CLKOUT_CHANNEL_1_DIRECT_GPIO_NUM     20
-#define CLKOUT_GPIO19_DIRECT_CHANNEL         CLKOUT_CHANNEL_2
-#define CLKOUT_CHANNEL_2_DIRECT_GPIO_NUM     19
-#define CLKOUT_GPIO18_DIRECT_CHANNEL         CLKOUT_CHANNEL_3
-#define CLKOUT_CHANNEL_3_DIRECT_GPIO_NUM     18
+// ESP32H2 CLKOUT signals has no corresponding iomux pins

components/soc/esp32h2/include/soc/gpio_pins.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -11,8 +11,9 @@
 extern "C" {
 #endif
 
-#define GPIO_MATRIX_CONST_ONE_INPUT   (0x1E)
-#define GPIO_MATRIX_CONST_ZERO_INPUT  (0x1F)
+#define GPIO_MATRIX_CONST_ONE_INPUT   (0x38)
+#define GPIO_MATRIX_CONST_ZERO_INPUT  (0x3C)
+#define GPIO_MATRIX_INVALID           (0x3A)
 
 #ifdef __cplusplus
 }

components/soc/esp32h2/include/soc/io_mux_reg.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -63,15 +63,33 @@
 #define MCU_SEL_M (MCU_SEL_V << MCU_SEL_S)
 #define MCU_SEL_V 0x7
 #define MCU_SEL_S 12
-
-#define PIN_INPUT_ENABLE(PIN_NAME)               SET_PERI_REG_MASK(PIN_NAME,FUN_IE)
-#define PIN_INPUT_DISABLE(PIN_NAME)              CLEAR_PERI_REG_MASK(PIN_NAME,FUN_IE)
-#define PIN_SET_DRV(PIN_NAME, drv)            REG_SET_FIELD(PIN_NAME, FUN_DRV, (drv));
-#define PIN_PULLUP_DIS(PIN_NAME)                 REG_CLR_BIT(PIN_NAME, FUN_PU)
-#define PIN_PULLUP_EN(PIN_NAME)                  REG_SET_BIT(PIN_NAME, FUN_PU)
-#define PIN_PULLDWN_DIS(PIN_NAME)             REG_CLR_BIT(PIN_NAME, FUN_PD)
-#define PIN_PULLDWN_EN(PIN_NAME)              REG_SET_BIT(PIN_NAME, FUN_PD)
-#define PIN_FUNC_SELECT(PIN_NAME, FUNC)      REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC)
+/* Pin filter (Pulse width shorter than 2 clock cycles will be filtered out) */
+#define FILTER_EN (BIT(15))
+#define FILTER_EN_M (FILTER_EN_V << FILTER_EN_S)
+#define FILTER_EN_V 1
+#define FILTER_EN_S 15
+
+#define PIN_SLP_INPUT_ENABLE(PIN_NAME)      SET_PERI_REG_MASK(PIN_NAME,SLP_IE)
+#define PIN_SLP_INPUT_DISABLE(PIN_NAME)     CLEAR_PERI_REG_MASK(PIN_NAME,SLP_IE)
+#define PIN_SLP_OUTPUT_ENABLE(PIN_NAME)     SET_PERI_REG_MASK(PIN_NAME,SLP_OE)
+#define PIN_SLP_OUTPUT_DISABLE(PIN_NAME)    CLEAR_PERI_REG_MASK(PIN_NAME,SLP_OE)
+#define PIN_SLP_PULLUP_ENABLE(PIN_NAME)     SET_PERI_REG_MASK(PIN_NAME,SLP_PU)
+#define PIN_SLP_PULLUP_DISABLE(PIN_NAME)    CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PU)
+#define PIN_SLP_PULLDOWN_ENABLE(PIN_NAME)   SET_PERI_REG_MASK(PIN_NAME,SLP_PD)
+#define PIN_SLP_PULLDOWN_DISABLE(PIN_NAME)  CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PD)
+#define PIN_SLP_SEL_ENABLE(PIN_NAME)        SET_PERI_REG_MASK(PIN_NAME,SLP_SEL)
+#define PIN_SLP_SEL_DISABLE(PIN_NAME)       CLEAR_PERI_REG_MASK(PIN_NAME,SLP_SEL)
+
+#define PIN_INPUT_ENABLE(PIN_NAME)          SET_PERI_REG_MASK(PIN_NAME,FUN_IE)
+#define PIN_INPUT_DISABLE(PIN_NAME)         CLEAR_PERI_REG_MASK(PIN_NAME,FUN_IE)
+#define PIN_SET_DRV(PIN_NAME, drv)          REG_SET_FIELD(PIN_NAME, FUN_DRV, (drv));
+#define PIN_PULLUP_DIS(PIN_NAME)            REG_CLR_BIT(PIN_NAME, FUN_PU)
+#define PIN_PULLUP_EN(PIN_NAME)             REG_SET_BIT(PIN_NAME, FUN_PU)
+#define PIN_PULLDWN_DIS(PIN_NAME)           REG_CLR_BIT(PIN_NAME, FUN_PD)
+#define PIN_PULLDWN_EN(PIN_NAME)            REG_SET_BIT(PIN_NAME, FUN_PD)
+#define PIN_FUNC_SELECT(PIN_NAME, FUNC)     REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC)
+#define PIN_FILTER_EN(PIN_NAME)             REG_SET_BIT(PIN_NAME, FILTER_EN)
+#define PIN_FILTER_DIS(PIN_NAME)            REG_CLR_BIT(PIN_NAME, FILTER_EN)
 
 #define IO_MUX_GPIO0_REG               PERIPHS_IO_MUX_GPIO0_U
 #define IO_MUX_GPIO1_REG               PERIPHS_IO_MUX_GPIO1_U
@@ -102,7 +120,6 @@
 #define IO_MUX_GPIO26_REG              PERIPHS_IO_MUX_GPIO26_U
 #define IO_MUX_GPIO27_REG              PERIPHS_IO_MUX_GPIO27_U
 
-#define FUNC_GPIO_GPIO                              1
 #define PIN_FUNC_GPIO								1
 
 #define GPIO_PAD_PULLUP(num) do{PIN_PULLDWN_DIS(IOMUX_REG_GPIO##num);PIN_PULLUP_EN(IOMUX_REG_GPIO##num);}while(0)
@@ -116,25 +133,17 @@
 #define SPI_D_GPIO_NUM               20
 #define SPI_Q_GPIO_NUM               16
 
-#define MAX_RTC_GPIO_NUM              7
+#define USB_DM_GPIO_NUM              26
+#define USB_DP_GPIO_NUM              27
+
+#define MAX_RTC_GPIO_NUM             14            // GPIO7~14 are the pads with LP function
 #define MAX_PAD_GPIO_NUM             27
 #define MAX_GPIO_NUM                 31
 #define HIGH_IO_HOLD_BIT_SHIFT       32
-#define GPIO_NUM_IN_FORCE_0          0x3c
-#define GPIO_NUM_IN_FORCE_1          0x38
-#define GPIO_NUM_IN_INVALID          0x3a
+
 
 #define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
 #define PIN_CTRL                          (REG_IO_MUX_BASE +0x00)
-#define PAD_POWER_SEL                               BIT(15)
-#define PAD_POWER_SEL_V                             0x1
-#define PAD_POWER_SEL_M                             BIT(15)
-#define PAD_POWER_SEL_S                             15
-
-#define PAD_POWER_SWITCH_DELAY                      0x7
-#define PAD_POWER_SWITCH_DELAY_V                    0x7
-#define PAD_POWER_SWITCH_DELAY_M                    (PAD_POWER_SWITCH_DELAY_V << PAD_POWER_SWITCH_DELAY_S)
-#define PAD_POWER_SWITCH_DELAY_S                    12
 
 #define CLK_OUT3                                    IO_MUX_CLK_OUT3
 #define CLK_OUT3_V                                  IO_MUX_CLK_OUT3_V
@@ -274,40 +283,64 @@
 #define FUNC_GPIO27_GPIO27                                          1
 #define FUNC_GPIO27_GPIO27_0                                        0
 
-#define IO_MUX_PIN_CTRL_REG          (REG_IO_MUX_BASE + 0x0)
-/* IO_MUX_CLK_OUT3 : R/W ;bitpos:[14:10] ;default: 5'h7 ; */
-/*description: If you want to output clock for I2S to CLK_OUT_out3, set this register to 0x0. C
-LK_OUT_out3 can be found in peripheral output signals..*/
-#define IO_MUX_CLK_OUT3    0x0000001F
-#define IO_MUX_CLK_OUT3_M  ((IO_MUX_CLK_OUT3_V)<<(IO_MUX_CLK_OUT3_S))
-#define IO_MUX_CLK_OUT3_V  0x1F
-#define IO_MUX_CLK_OUT3_S  10
-/* IO_MUX_CLK_OUT2 : R/W ;bitpos:[9:5] ;default: 5'hf ; */
-/*description: If you want to output clock for I2S to CLK_OUT_out2, set this register to 0x0. C
-LK_OUT_out2 can be found in peripheral output signals..*/
-#define IO_MUX_CLK_OUT2    0x0000001F
-#define IO_MUX_CLK_OUT2_M  ((IO_MUX_CLK_OUT2_V)<<(IO_MUX_CLK_OUT2_S))
-#define IO_MUX_CLK_OUT2_V  0x1F
-#define IO_MUX_CLK_OUT2_S  5
-/* IO_MUX_CLK_OUT1 : R/W ;bitpos:[4:0] ;default: 5'hf ; */
-/*description: If you want to output clock for I2S to CLK_OUT_out1, set this register to 0x0. C
-LK_OUT_out1 can be found in peripheral output signals..*/
+/** IO_MUX_PIN_CTRL_REG register
+ *  Clock Output Configuration
+ *  Register
+ */
+#define IO_MUX_PIN_CTRL_REG (REG_IO_MUX_BASE + 0x0)
+/* IO_MUX_CLK_OUT1 : R/W; bitpos: [5:0]; default: 15;
+ * If you want to output clock for I2S to CLK_OUT_out1, set this register
+ * to 0x0. CLK_OUT_out1 can be found in peripheral output
+ * signals.
+ */
 #define IO_MUX_CLK_OUT1    0x0000001F
-#define IO_MUX_CLK_OUT1_M  ((IO_MUX_CLK_OUT1_V)<<(IO_MUX_CLK_OUT1_S))
-#define IO_MUX_CLK_OUT1_V  0x1F
+#define IO_MUX_CLK_OUT1_M  (IO_MUX_CLK_OUT1_V << IO_MUX_CLK_OUT1_S)
+#define IO_MUX_CLK_OUT1_V  0x0000001F
 #define IO_MUX_CLK_OUT1_S  0
-#define IO_MUX_MODEM_DIAG_EN_REG          (REG_IO_MUX_BASE + 0xBC)
-/* IO_MUX_MODEM_DIAG_EN : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: bit i to enable modem_diag[i] into gpio matrix. 1:enable modem_diag[i] into gpio
- matrix. 0:enable other signals into gpio matrix.*/
+/* IO_MUX_CLK_OUT2 : R/W; bitpos: [10:5]; default: 15;
+ * If you want to output clock for I2S to CLK_OUT_out2, set this register
+ * to 0x0. CLK_OUT_out2 can be found in peripheral output
+ * signals.
+ */
+#define IO_MUX_CLK_OUT2    0x0000001F
+#define IO_MUX_CLK_OUT2_M  (IO_MUX_CLK_OUT2_V << IO_MUX_CLK_OUT2_S)
+#define IO_MUX_CLK_OUT2_V  0x0000001F
+#define IO_MUX_CLK_OUT2_S  5
+/* IO_MUX_CLK_OUT3 : R/W; bitpos: [15:10]; default: 7;
+ * If you want to output clock for I2S to CLK_OUT_out3, set this register
+ * to 0x0. CLK_OUT_out3 can be found in peripheral output
+ * signals.
+ */
+#define IO_MUX_CLK_OUT3    0x0000001F
+#define IO_MUX_CLK_OUT3_M  (IO_MUX_CLK_OUT3_V << IO_MUX_CLK_OUT3_S)
+#define IO_MUX_CLK_OUT3_V  0x0000001F
+#define IO_MUX_CLK_OUT3_S  10
+
+/** IO_MUX_MODEM_DIAG_EN_REG register
+ *  GPIO MATRIX Configure Register for modem
+ *  diag
+ */
+#define IO_MUX_MODEM_DIAG_EN_REG (REG_IO_MUX_BASE + 0xbc)
+/* IO_MUX_MODEM_DIAG_EN : R/W; bitpos: [32:0]; default: 0;
+ * bit i to enable modem_diag[i] into gpio matrix. 1:enable modem_diag[i]
+ * into gpio matrix. 0:enable other signals into gpio
+ * matrix
+ */
 #define IO_MUX_MODEM_DIAG_EN    0xFFFFFFFF
-#define IO_MUX_MODEM_DIAG_EN_M  ((IO_MUX_MODEM_DIAG_EN_V)<<(IO_MUX_MODEM_DIAG_EN_S))
+#define IO_MUX_MODEM_DIAG_EN_M  (IO_MUX_MODEM_DIAG_EN_V << IO_MUX_MODEM_DIAG_EN_S)
 #define IO_MUX_MODEM_DIAG_EN_V  0xFFFFFFFF
 #define IO_MUX_MODEM_DIAG_EN_S  0
-#define IO_MUX_DATE_REG          (REG_IO_MUX_BASE + 0xFC)
-/* IO_MUX_REG_DATE : R/W ;bitpos:[27:0] ;default: 28'h2207270 ; */
-/*description: Version control register.*/
+
+/** IO_MUX_DATE_REG register
+ *  IO MUX Version Control
+ *  Register
+ */
+#define IO_MUX_DATE_REG (REG_IO_MUX_BASE + 0xfc)
+/* IO_MUX_REG_DATE : R/W; bitpos: [28:0]; default: 35680880;
+ * Version control
+ * register
+ */
 #define IO_MUX_REG_DATE    0x0FFFFFFF
-#define IO_MUX_REG_DATE_M  ((IO_MUX_REG_DATE_V)<<(IO_MUX_REG_DATE_S))
-#define IO_MUX_REG_DATE_V  0xFFFFFFF
+#define IO_MUX_REG_DATE_M  (IO_MUX_REG_DATE_V << IO_MUX_REG_DATE_S)
+#define IO_MUX_REG_DATE_V  0x0FFFFFFF
 #define IO_MUX_REG_DATE_S  0

components/soc/esp32h2/include/soc/soc_caps.h

@@ -144,22 +144,21 @@
 #define SOC_GDMA_SUPPORT_ETM            (1)  // Support ETM submodule
 
 /*-------------------------- GPIO CAPS ---------------------------------------*/
-// ESP32-C6 has 1 GPIO peripheral
+// ESP32-H2 has 1 GPIO peripheral
 #define SOC_GPIO_PORT               (1U)
-#define SOC_GPIO_PIN_COUNT          (31)
+#define SOC_GPIO_PIN_COUNT          (28)
 
-// Target has the full LP IO subsystem
-// On ESP32-C6, Digital IOs have their own registers to control pullup/down capability, independent of LP registers.
-#define SOC_GPIO_SUPPORT_RTC_INDEPENDENT    (1)
-// GPIO0~7 on ESP32C6 can support chip deep sleep wakeup
+// Target has no full LP IO subsystem, GPIO7~14 remain LP function (powered by VDD3V3_LP, and can be used as deep-sleep wakeup pins)
+
+// GPIO7~14 on ESP32H2 can support chip deep sleep wakeup
 #define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP   (1)
 
 #define SOC_GPIO_VALID_GPIO_MASK        ((1U<<SOC_GPIO_PIN_COUNT) - 1)
 #define SOC_GPIO_VALID_OUTPUT_GPIO_MASK SOC_GPIO_VALID_GPIO_MASK
-#define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK        (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7)
+#define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK        (0ULL | BIT7 | BIT8 | BIT9 | BIT10 | BIT11 | BIT12 | BIT13 | BIT14)
 
-// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_8~GPIO_NUM_30)
-#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x000000007FFFFF00ULL
+// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_0~6. GPIO_NUM_15~27)
+#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x000000000FFF807FULL
 
 // Support to configure sleep status
 #define SOC_GPIO_SUPPORT_SLP_SWITCH  (1)

components/soc/esp32h4/include/soc/Kconfig.soc_caps.in

@@ -299,10 +299,6 @@ config SOC_GPIO_PIN_COUNT
     int
     default 41
 
-config SOC_GPIO_SUPPORTS_RTC_INDEPENDENT
-    bool
-    default y
-
 config SOC_GPIO_SUPPORT_FORCE_HOLD
     bool
     default y

components/soc/esp32h4/include/soc/soc_caps.h

@@ -152,9 +152,8 @@
 #define SOC_GPIO_PIN_COUNT          (26)
 #endif
 
-// Target has no full RTC IO subsystem, so GPIO is 100% "independent" of RTC
-// On ESP32-H4, Digital IOs have their own registers to control pullup/down capability, independent of RTC registers.
-#define SOC_GPIO_SUPPORTS_RTC_INDEPENDENT       (1)
+// Target has no full RTC IO subsystem, GPIO0~5(7~12) remain RTC function (powered by VDD3V3_RTC, and can be used as deep-sleep wakeup pins)
+
 // Force hold is a new function of ESP32-H4
 #define SOC_GPIO_SUPPORT_FORCE_HOLD         (1)
 // GPIO0~5 on ESP32H4Beta1 / GPIO7~12 on ESP32H4Beta2 can support chip deep sleep wakeup

docs/docs_not_updated/esp32h2.txt

@@ -100,14 +100,12 @@ api-reference/storage/mass_mfg
 api-reference/storage/index
 api-reference/storage/nvs_partition_parse
 api-reference/peripherals/sdspi_share
-api-reference/peripherals/gpio/esp32h2.inc
 api-reference/peripherals/adc_continuous
 api-reference/peripherals/adc_oneshot
 api-reference/peripherals/usb_host
 api-reference/peripherals/twai
 api-reference/peripherals/hmac
 api-reference/peripherals/usb_device
-api-reference/peripherals/gpio
 api-reference/peripherals/sdspi_host
 api-reference/peripherals/dac
 api-reference/peripherals/spi_slave

docs/en/api-reference/peripherals/gpio/esp32h2.inc

@@ -9,22 +9,135 @@
 
 .. gpio-summary
 
-The {IDF_TARGET_NAME} chip features X physical GPIO pins (GPIOX ~ GPIOX). Each pin can be used as a general-purpose I/O, or to be connected to an internal peripheral signal. Through GPIO matrix and IO MUX, peripheral input signals can be from any IO pins, and peripheral output signals can be routed to any IO pins. Together these modules provide highly configurable I/O. For more details, see *{IDF_TARGET_NAME} Technical Reference Manual* > *IO MUX and GPIO Matrix (GPIO, IO_MUX)* [`PDF <{IDF_TARGET_TRM_EN_URL}#iomuxgpio>`__].
+The {IDF_TARGET_NAME} chip features 28 physical GPIO pins (GPIO0 ~ GPIO27). Each pin can be used as a general-purpose I/O, or to be connected to an internal peripheral signal. Through GPIO matrix and IO MUX, peripheral input signals can be from any IO pins, and peripheral output signals can be routed to any IO pins. Together these modules provide highly configurable I/O. For more details, see *{IDF_TARGET_NAME} Technical Reference Manual* > *IO MUX and GPIO Matrix (GPIO, IO_MUX)* [`PDF <{IDF_TARGET_TRM_EN_URL}#iomuxgpio>`__].
 
 The table below provides more information on pin usage, and please note the comments in the table for GPIOs with restrictions.
 
 .. list-table::
     :header-rows: 1
-    :widths: 8 12 12 20
+    :widths: 8 12 20
 
     * - GPIO
       - Analog Function
-      - LP GPIO
       - Comments
 
     * - GPIO0
       -
       -
+
+    * - GPIO1
+      - ADC1_CH0
+      -
+
+    * - GPIO2
+      - ADC1_CH1
+      - Strapping pin
+
+    * - GPIO3
+      - ADC1_CH2
+      - Strapping pin
+
+    * - GPIO4
+      - ADC1_CH3
+      -
+
+    * - GPIO5
+      - ADC1_CH4
+      -
+
+    * - GPIO6
+      -
+      -
+
+    * - GPIO7
+      -
+      -
+
+    * - GPIO8
+      -
+      - Strapping pin
+
+    * - GPIO9
+      -
+      - Strapping pin
+
+    * - GPIO10
+      -
+      -
+
+    * - GPIO11
+      -
+      -
+
+    * - GPIO12
+      -
+      -
+
+    * - GPIO13
+      -
+      -
+
+    * - GPIO14
+      -
       -
 
+    * - GPIO15
+      -
+      - SPI0/1
+
+    * - GPIO16
+      -
+      - SPI0/1
+
+    * - GPIO17
+      -
+      - SPI0/1
+
+    * - GPIO18
+      -
+      - SPI0/1
+
+    * - GPIO19
+      -
+      - SPI0/1
+
+    * - GPIO20
+      -
+      - SPI0/1
+
+    * - GPIO21
+      -
+      - SPI0/1
+
+    * - GPIO22
+      -
+      -
+
+    * - GPIO23
+      -
+      -
+
+    * - GPIO24
+      -
+      -
+
+    * - GPIO25
+      -
+      - Strapping pin
+
+    * - GPIO26
+      -
+      - USB-JTAG
+
+    * - GPIO27
+      -
+      - USB-JTAG
+
+.. note::
+
+    - Strapping pin: GPIO2, GPIO3, GPIO8, GPIO9, and GPIO25 are strapping pins. For more infomation, please refer to `ESP32H2 datasheet <https://www.espressif.com/sites/default/files/documentation/esp32h2_datasheet_en.pdf>`_.
+	  - SPI0/1: GPIO15-21 are usually used for SPI flash and not recommended for other uses.
+	  - USB-JTAG: GPIO 26 and 27 are used by USB-JTAG by default. In order to use them as GPIOs, USB-JTAG will be disabled by the drivers.
+    - For chip variants with an SiP flash built in, GPIO15 ~ GPIO21 are dedicated to connecting the SiP flash; therefore, only the remaining 21 GPIO pins are available.
+
 ---

docs/zh_CN/api-reference/peripherals/gpio/esp32h2.inc

@@ -9,22 +9,137 @@
 
 .. gpio-summary
 
-The {IDF_TARGET_NAME} chip features X physical GPIO pins (GPIOX ~ GPIOX). Each pin can be used as a general-purpose I/O, or to be connected to an internal peripheral signal. Through GPIO matrix and IO MUX, peripheral input signals can be from any IO pins, and peripheral output signals can be routed to any IO pins. Together these modules provide highly configurable I/O. For more details, see *{IDF_TARGET_NAME} Technical Reference Manual* > *IO MUX and GPIO Matrix (GPIO, IO_MUX)* [`PDF <{IDF_TARGET_TRM_EN_URL}#iomuxgpio>`__].
+{IDF_TARGET_NAME} 芯片具有 28 个物理 GPIO 管脚（GPIO0 ~ GPIO27）。
 
-The table below provides more information on pin usage, and please note the comments in the table for GPIOs with restrictions.
+每个管脚都可用作一个通用 IO，或连接一个内部的外设信号。通过 GPIO 交换矩阵和 IO MUX，可配置外设模块的输入信号来源于任何的 IO 管脚，并且外设模块的输出信号也可连接到任意 IO 管脚。这些模块共同组成了芯片的 IO 控制。更多详细信息，请参阅 *{IDF_TARGET_NAME} 技术参考手册* > *IO MUX 和 GPIO 矩阵（GPIO、IO_MUX）* [`PDF <{IDF_TARGET_TRM_CN_URL}#iomuxgpio>`__]。
+
+下表提供了各管脚的详细信息，部分 GPIO 具有特殊的使用限制，具体可参考表中的注释列。
 
 .. list-table::
     :header-rows: 1
-    :widths: 8 12 12 20
+    :widths: 8 12 20
 
     * - GPIO
-      - Analog Function
-      - LP GPIO
-      - Comments
+      - 模拟功能
+      - 注释
 
     * - GPIO0
       -
       -
+
+    * - GPIO1
+      - ADC1_CH0
+      -
+
+    * - GPIO2
+      - ADC1_CH1
+      - Strapping 管脚
+
+    * - GPIO3
+      - ADC1_CH2
+      - Strapping 管脚
+
+    * - GPIO4
+      - ADC1_CH3
+      -
+
+    * - GPIO5
+      - ADC1_CH4
+      -
+
+    * - GPIO6
+      -
+      -
+
+    * - GPIO7
+      -
+      -
+
+    * - GPIO8
+      -
+      - Strapping 管脚
+
+    * - GPIO9
+      -
+      - Strapping 管脚
+
+    * - GPIO10
+      -
+      -
+
+    * - GPIO11
+      -
+      -
+
+    * - GPIO12
+      -
+      -
+
+    * - GPIO13
+      -
+      -
+
+    * - GPIO14
+      -
+      -
+
+    * - GPIO15
+      -
+      - SPI0/1
+
+    * - GPIO16
+      -
+      - SPI0/1
+
+    * - GPIO17
+      -
+      - SPI0/1
+
+    * - GPIO18
+      -
+      - SPI0/1
+
+    * - GPIO19
+      -
+      - SPI0/1
+
+    * - GPIO20
+      -
+      - SPI0/1
+
+    * - GPIO21
+      -
+      - SPI0/1
+
+    * - GPIO22
+      -
+      -
+
+    * - GPIO23
+      -
+      -
+
+    * - GPIO24
+      -
       -
 
+    * - GPIO25
+      -
+      - Strapping 管脚
+
+    * - GPIO26
+      -
+      - USB-JTAG
+
+    * - GPIO27
+      -
+      - USB-JTAG
+
+.. note::
+
+    - Strapping 管脚：GPIO2、GPIO3、GPIO8、GPIO9 和 GPIO25 是 Strapping 管脚。更多信息请参考 `ESP32-H2 技术规格书 <https://www.espressif.com/sites/default/files/documentation/esp32-h2_datasheet_cn.pdf>`_。
+    - SPI0/1：GPIO15-21 通常用于 SPI flash，不推荐用于其他用途。
+    - USB-JTAG：GPIO26 和 GPIO27 默认用于 USB-JTAG。用做 GPIO 时驱动程序将禁用 USB-JTAG。
+    - 对于内置 SiP flash 的芯片型号，GPIO15 ~ GPIO21 专门用于连接 SiP flash; 因此，对于这类芯片只有 21 个 GPIO 管脚可用。
+
 ---

examples/peripherals/gpio/generic_gpio/README.md

@@ -23,10 +23,10 @@ This test code shows how to configure GPIO and how to use it with interruption.
 
  **Note:** The following pin assignments are used by default, you can change them by `idf.py menuconfig` > `Example Configuration`.
 
-|                 | CONFIG_GPIO_OUTPUT_0 | CONFIG_GPIO_OUTPUT_1 | CONFIG_GPIO_INPUT_0 | CONFIG_GPIO_INPUT_1 |
-| --------------- | -------------------- | -------------------- | ------------------- | ------------------- |
-| ESP32-C2/ESP32H4| 8                    | 9                    | 4                   | 5                   |
-| All other chips | 18                   | 19                   | 4                   | 5                   |
+|                        | CONFIG_GPIO_OUTPUT_0 | CONFIG_GPIO_OUTPUT_1 | CONFIG_GPIO_INPUT_0 | CONFIG_GPIO_INPUT_1 |
+| ---------------------- | -------------------- | -------------------- | ------------------- | ------------------- |
+| ESP32C2/ESP32H2/ESP32H4| 8                    | 9                    | 4                   | 5                   |
+| All other chips        | 18                   | 19                   | 4                   | 5                   |
 
 ## How to use example
 

examples/peripherals/gpio/generic_gpio/main/Kconfig.projbuild

@@ -5,7 +5,7 @@ menu "Example Configuration"
     config GPIO_OUTPUT_0
         int "GPIO output pin 0"
         range ENV_GPIO_RANGE_MIN ENV_GPIO_OUT_RANGE_MAX
-        default 8 if IDF_TARGET_ESP32C2 || IDF_TARGET_ESP32H4
+        default 8 if IDF_TARGET_ESP32C2 || IDF_TARGET_ESP32H4 || IDF_TARGET_ESP32H2
         default 18
         help
             GPIO pin number to be used as GPIO_OUTPUT_IO_0.
@@ -13,7 +13,7 @@ menu "Example Configuration"
     config GPIO_OUTPUT_1
         int "GPIO output pin 1"
         range ENV_GPIO_RANGE_MIN ENV_GPIO_OUT_RANGE_MAX
-        default 9 if IDF_TARGET_ESP32C2 || IDF_TARGET_ESP32H4
+        default 9 if IDF_TARGET_ESP32C2 || IDF_TARGET_ESP32H4 || IDF_TARGET_ESP32H2
         default 19
         help
             GPIO pin number to be used as GPIO_OUTPUT_IO_1.

examples/peripherals/gpio/generic_gpio/main/gpio_example_main.c

@@ -20,8 +20,8 @@
  * This test code shows how to configure gpio and how to use gpio interrupt.
  *
  * GPIO status:
- * GPIO18: output (ESP32C2/ESP32H4 uses GPIO8 as the second output pin)
- * GPIO19: output (ESP32C2/ESP32H4 uses GPIO9 as the second output pin)
+ * GPIO18: output (ESP32C2/ESP32H2/ESP32H4 uses GPIO8 as the second output pin)
+ * GPIO19: output (ESP32C2/ESP32H2/ESP32H4 uses GPIO9 as the second output pin)
  * GPIO4:  input, pulled up, interrupt from rising edge and falling edge
  * GPIO5:  input, pulled up, interrupt from rising edge.
  *