register changes

components/soc/esp32p4/include/soc/i2c_reg.h

@@ -14,7 +14,7 @@ extern "C" {
 /** I2C_SCL_LOW_PERIOD_REG register
  *  Configures the low level width of the SCL Clock.
  */
-#define I2C_SCL_LOW_PERIOD_REG (DR_REG_I2C_BASE + 0x0)
+#define I2C_SCL_LOW_PERIOD_REG(i) (REG_I2C_BASE(i) + 0x0)
 /** I2C_SCL_LOW_PERIOD : R/W; bitpos: [8:0]; default: 0;
  *  Configures the low level width of the SCL Clock.
  *  Measurement unit: i2c_sclk.
@@ -27,7 +27,7 @@ extern "C" {
 /** I2C_CTR_REG register
  *  Transmission setting
  */
-#define I2C_CTR_REG (DR_REG_I2C_BASE + 0x4)
+#define I2C_CTR_REG(i) (REG_I2C_BASE(i) + 0x4)
 /** I2C_SDA_FORCE_OUT : R/W; bitpos: [0]; default: 0;
  *  Configures the SDA output mode
  *  1: Direct output,
@@ -181,7 +181,7 @@ extern "C" {
 /** I2C_SR_REG register
  *  Describe I2C work status.
  */
-#define I2C_SR_REG (DR_REG_I2C_BASE + 0x8)
+#define I2C_SR_REG(i) (REG_I2C_BASE(i) + 0x8)
 /** I2C_RESP_REC : RO; bitpos: [0]; default: 0;
  *  Represents the received ACK value in master mode or slave mode.
  *  0: ACK,
@@ -304,7 +304,7 @@ extern "C" {
 /** I2C_TO_REG register
  *  Setting time out control for receiving data.
  */
-#define I2C_TO_REG (DR_REG_I2C_BASE + 0xc)
+#define I2C_TO_REG(i) (REG_I2C_BASE(i) + 0xc)
 /** I2C_TIME_OUT_VALUE : R/W; bitpos: [4:0]; default: 16;
  *  Configures the timeout threshold period for SCL stucking at high or low level. The
  *  actual period is 2^(reg_time_out_value).
@@ -328,7 +328,7 @@ extern "C" {
 /** I2C_SLAVE_ADDR_REG register
  *  Local slave address setting
  */
-#define I2C_SLAVE_ADDR_REG (DR_REG_I2C_BASE + 0x10)
+#define I2C_SLAVE_ADDR_REG(i) (REG_I2C_BASE(i) + 0x10)
 /** I2C_SLAVE_ADDR : R/W; bitpos: [14:0]; default: 0;
  *  Configure the slave address of I2C Slave.
  */
@@ -350,7 +350,7 @@ extern "C" {
 /** I2C_FIFO_ST_REG register
  *  FIFO status register.
  */
-#define I2C_FIFO_ST_REG (DR_REG_I2C_BASE + 0x14)
+#define I2C_FIFO_ST_REG(i) (REG_I2C_BASE(i) + 0x14)
 /** I2C_RXFIFO_RADDR : RO; bitpos: [4:0]; default: 0;
  *  Represents the offset address of the APB reading from RXFIFO
  */
@@ -391,7 +391,7 @@ extern "C" {
 /** I2C_FIFO_CONF_REG register
  *  FIFO configuration register.
  */
-#define I2C_FIFO_CONF_REG (DR_REG_I2C_BASE + 0x18)
+#define I2C_FIFO_CONF_REG(i) (REG_I2C_BASE(i) + 0x18)
 /** I2C_RXFIFO_WM_THRHD : R/W; bitpos: [4:0]; default: 11;
  *  Configures the water mark threshold of RXFIFO in nonfifo access mode. When
  *  reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than
@@ -464,7 +464,7 @@ extern "C" {
 /** I2C_DATA_REG register
  *  Rx FIFO read data.
  */
-#define I2C_DATA_REG (DR_REG_I2C_BASE + 0x1c)
+#define I2C_DATA_REG(i) (REG_I2C_BASE(i) + 0x1c)
 /** I2C_FIFO_RDATA : HRO; bitpos: [7:0]; default: 0;
  *  Represents the value of RXFIFO read data.
  */
@@ -476,7 +476,7 @@ extern "C" {
 /** I2C_INT_RAW_REG register
  *  Raw interrupt status
  */
-#define I2C_INT_RAW_REG (DR_REG_I2C_BASE + 0x20)
+#define I2C_INT_RAW_REG(i) (REG_I2C_BASE(i) + 0x20)
 /** I2C_RXFIFO_WM_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0;
  *  The raw interrupt status of I2C_RXFIFO_WM_INT interrupt.
  */
@@ -614,7 +614,7 @@ extern "C" {
 /** I2C_INT_CLR_REG register
  *  Interrupt clear bits
  */
-#define I2C_INT_CLR_REG (DR_REG_I2C_BASE + 0x24)
+#define I2C_INT_CLR_REG(i) (REG_I2C_BASE(i) + 0x24)
 /** I2C_RXFIFO_WM_INT_CLR : WT; bitpos: [0]; default: 0;
  *  Write 1 to clear I2C_RXFIFO_WM_INT interrupt.
  */
@@ -752,7 +752,7 @@ extern "C" {
 /** I2C_INT_ENA_REG register
  *  Interrupt enable bits
  */
-#define I2C_INT_ENA_REG (DR_REG_I2C_BASE + 0x28)
+#define I2C_INT_ENA_REG(i) (REG_I2C_BASE(i) + 0x28)
 /** I2C_RXFIFO_WM_INT_ENA : R/W; bitpos: [0]; default: 0;
  *  Write 1 to enable I2C_RXFIFO_WM_INT interrupt.
  */
@@ -890,7 +890,7 @@ extern "C" {
 /** I2C_INT_STATUS_REG register
  *  Status of captured I2C communication events
  */
-#define I2C_INT_STATUS_REG (DR_REG_I2C_BASE + 0x2c)
+#define I2C_INT_STATUS_REG(i) (REG_I2C_BASE(i) + 0x2c)
 /** I2C_RXFIFO_WM_INT_ST : RO; bitpos: [0]; default: 0;
  *  The masked interrupt status status of I2C_RXFIFO_WM_INT interrupt.
  */
@@ -1028,7 +1028,7 @@ extern "C" {
 /** I2C_SDA_HOLD_REG register
  *  Configures the hold time after a negative SCL edge.
  */
-#define I2C_SDA_HOLD_REG (DR_REG_I2C_BASE + 0x30)
+#define I2C_SDA_HOLD_REG(i) (REG_I2C_BASE(i) + 0x30)
 /** I2C_SDA_HOLD_TIME : R/W; bitpos: [8:0]; default: 0;
  *  Configures the time to hold the data after the falling edge of SCL.
  *  Measurement unit: i2c_sclk
@@ -1041,7 +1041,7 @@ extern "C" {
 /** I2C_SDA_SAMPLE_REG register
  *  Configures the sample time after a positive SCL edge.
  */
-#define I2C_SDA_SAMPLE_REG (DR_REG_I2C_BASE + 0x34)
+#define I2C_SDA_SAMPLE_REG(i) (REG_I2C_BASE(i) + 0x34)
 /** I2C_SDA_SAMPLE_TIME : R/W; bitpos: [8:0]; default: 0;
  *  Configures the sample time after a positive SCL edge.
  *  Measurement unit: i2c_sclk
@@ -1054,7 +1054,7 @@ extern "C" {
 /** I2C_SCL_HIGH_PERIOD_REG register
  *  Configures the high level width of SCL
  */
-#define I2C_SCL_HIGH_PERIOD_REG (DR_REG_I2C_BASE + 0x38)
+#define I2C_SCL_HIGH_PERIOD_REG(i) (REG_I2C_BASE(i) + 0x38)
 /** I2C_SCL_HIGH_PERIOD : R/W; bitpos: [8:0]; default: 0;
  *  Configures for how long SCL remains high in master mode.
  *  Measurement unit: i2c_sclk
@@ -1075,7 +1075,7 @@ extern "C" {
 /** I2C_SCL_START_HOLD_REG register
  *  Configures the delay between the SDA and SCL negative edge for a start condition
  */
-#define I2C_SCL_START_HOLD_REG (DR_REG_I2C_BASE + 0x40)
+#define I2C_SCL_START_HOLD_REG(i) (REG_I2C_BASE(i) + 0x40)
 /** I2C_SCL_START_HOLD_TIME : R/W; bitpos: [8:0]; default: 8;
  *  Configures the time between the falling edge of SDA and the falling edge of SCL for
  *  a START condition.
@@ -1089,7 +1089,7 @@ extern "C" {
 /** I2C_SCL_RSTART_SETUP_REG register
  *  Configures the delay between the positive edge of SCL and the negative edge of SDA
  */
-#define I2C_SCL_RSTART_SETUP_REG (DR_REG_I2C_BASE + 0x44)
+#define I2C_SCL_RSTART_SETUP_REG(i) (REG_I2C_BASE(i) + 0x44)
 /** I2C_SCL_RSTART_SETUP_TIME : R/W; bitpos: [8:0]; default: 8;
  *  Configures the time between the positive edge of SCL and the negative edge of SDA
  *  for a RESTART condition.
@@ -1103,7 +1103,7 @@ extern "C" {
 /** I2C_SCL_STOP_HOLD_REG register
  *  Configures the delay after the SCL clock edge for a stop condition
  */
-#define I2C_SCL_STOP_HOLD_REG (DR_REG_I2C_BASE + 0x48)
+#define I2C_SCL_STOP_HOLD_REG(i) (REG_I2C_BASE(i) + 0x48)
 /** I2C_SCL_STOP_HOLD_TIME : R/W; bitpos: [8:0]; default: 8;
  *  Configures the delay after the STOP condition.
  *  Measurement unit: i2c_sclk
@@ -1117,7 +1117,7 @@ extern "C" {
  *  Configures the delay between the SDA and SCL rising edge for a stop condition.
  *  Measurement unit: i2c_sclk
  */
-#define I2C_SCL_STOP_SETUP_REG (DR_REG_I2C_BASE + 0x4c)
+#define I2C_SCL_STOP_SETUP_REG(i) (REG_I2C_BASE(i) + 0x4c)
 /** I2C_SCL_STOP_SETUP_TIME : R/W; bitpos: [8:0]; default: 8;
  *  Configures the time between the rising edge of SCL and the rising edge of SDA.
  *  Measurement unit: i2c_sclk
@@ -1130,7 +1130,7 @@ extern "C" {
 /** I2C_FILTER_CFG_REG register
  *  SCL and SDA filter configuration register
  */
-#define I2C_FILTER_CFG_REG (DR_REG_I2C_BASE + 0x50)
+#define I2C_FILTER_CFG_REG(i) (REG_I2C_BASE(i) + 0x50)
 /** I2C_SCL_FILTER_THRES : R/W; bitpos: [3:0]; default: 0;
  *  Configures the threshold pulse width to be filtered on SCL. When a pulse on the SCL
  *  input has smaller width than this register value, the I2C controller will ignore
@@ -1169,7 +1169,7 @@ extern "C" {
 /** I2C_COMD0_REG register
  *  I2C command register 0
  */
-#define I2C_COMD0_REG (DR_REG_I2C_BASE + 0x58)
+#define I2C_COMD0_REG(i) (REG_I2C_BASE(i) + 0x58)
 /** I2C_COMMAND0 : R/W; bitpos: [13:0]; default: 0;
  *  Configures command 0. It consists of three parts:
  *  op_code is the command,
@@ -1201,7 +1201,7 @@ extern "C" {
 /** I2C_COMD1_REG register
  *  I2C command register 1
  */
-#define I2C_COMD1_REG (DR_REG_I2C_BASE + 0x5c)
+#define I2C_COMD1_REG(i) (REG_I2C_BASE(i) + 0x5c)
 /** I2C_COMMAND1 : R/W; bitpos: [13:0]; default: 0;
  *  Configures command 1. See details in I2C_CMD0_REG[13:0].
  */
@@ -1223,7 +1223,7 @@ extern "C" {
 /** I2C_COMD2_REG register
  *  I2C command register 2
  */
-#define I2C_COMD2_REG (DR_REG_I2C_BASE + 0x60)
+#define I2C_COMD2_REG(i) (REG_I2C_BASE(i) + 0x60)
 /** I2C_COMMAND2 : R/W; bitpos: [13:0]; default: 0;
  *  Configures command 2. See details in I2C_CMD0_REG[13:0].
  */
@@ -1245,7 +1245,7 @@ extern "C" {
 /** I2C_COMD3_REG register
  *  I2C command register 3
  */
-#define I2C_COMD3_REG (DR_REG_I2C_BASE + 0x64)
+#define I2C_COMD3_REG(i) (REG_I2C_BASE(i) + 0x64)
 /** I2C_COMMAND3 : R/W; bitpos: [13:0]; default: 0;
  *  Configures command 3. See details in I2C_CMD0_REG[13:0].
  */
@@ -1267,7 +1267,7 @@ extern "C" {
 /** I2C_COMD4_REG register
  *  I2C command register 4
  */
-#define I2C_COMD4_REG (DR_REG_I2C_BASE + 0x68)
+#define I2C_COMD4_REG(i) (REG_I2C_BASE(i) + 0x68)
 /** I2C_COMMAND4 : R/W; bitpos: [13:0]; default: 0;
  *  Configures command 4. See details in I2C_CMD0_REG[13:0].
  */
@@ -1289,7 +1289,7 @@ extern "C" {
 /** I2C_COMD5_REG register
  *  I2C command register 5
  */
-#define I2C_COMD5_REG (DR_REG_I2C_BASE + 0x6c)
+#define I2C_COMD5_REG(i) (REG_I2C_BASE(i) + 0x6c)
 /** I2C_COMMAND5 : R/W; bitpos: [13:0]; default: 0;
  *  Configures command 5. See details in I2C_CMD0_REG[13:0].
  */
@@ -1311,7 +1311,7 @@ extern "C" {
 /** I2C_COMD6_REG register
  *  I2C command register 6
  */
-#define I2C_COMD6_REG (DR_REG_I2C_BASE + 0x70)
+#define I2C_COMD6_REG(i) (REG_I2C_BASE(i) + 0x70)
 /** I2C_COMMAND6 : R/W; bitpos: [13:0]; default: 0;
  *  Configures command 6. See details in I2C_CMD0_REG[13:0].
  */
@@ -1333,7 +1333,7 @@ extern "C" {
 /** I2C_COMD7_REG register
  *  I2C command register 7
  */
-#define I2C_COMD7_REG (DR_REG_I2C_BASE + 0x74)
+#define I2C_COMD7_REG(i) (REG_I2C_BASE(i) + 0x74)
 /** I2C_COMMAND7 : R/W; bitpos: [13:0]; default: 0;
  *  Configures command 7. See details in I2C_CMD0_REG[13:0].
  */
@@ -1355,7 +1355,7 @@ extern "C" {
 /** I2C_SCL_ST_TIME_OUT_REG register
  *  SCL status time out register
  */
-#define I2C_SCL_ST_TIME_OUT_REG (DR_REG_I2C_BASE + 0x78)
+#define I2C_SCL_ST_TIME_OUT_REG(i) (REG_I2C_BASE(i) + 0x78)
 /** I2C_SCL_ST_TO_I2C : R/W; bitpos: [4:0]; default: 16;
  *  Configures the threshold value of SCL_FSM state unchanged period. It should be no
  *  more than 23.
@@ -1369,7 +1369,7 @@ extern "C" {
 /** I2C_SCL_MAIN_ST_TIME_OUT_REG register
  *  SCL main status time out register
  */
-#define I2C_SCL_MAIN_ST_TIME_OUT_REG (DR_REG_I2C_BASE + 0x7c)
+#define I2C_SCL_MAIN_ST_TIME_OUT_REG(i) (REG_I2C_BASE(i) + 0x7c)
 /** I2C_SCL_MAIN_ST_TO_I2C : R/W; bitpos: [4:0]; default: 16;
  *  Configures the threshold value of SCL_MAIN_FSM state unchanged period.nIt should be
  *  no more than 23.
@@ -1383,7 +1383,7 @@ extern "C" {
 /** I2C_SCL_SP_CONF_REG register
  *  Power configuration register
  */
-#define I2C_SCL_SP_CONF_REG (DR_REG_I2C_BASE + 0x80)
+#define I2C_SCL_SP_CONF_REG(i) (REG_I2C_BASE(i) + 0x80)
 /** I2C_SCL_RST_SLV_EN : R/W/SC; bitpos: [0]; default: 0;
  *  Configures to send out SCL pulses when I2C master is IDLE. The number of pulses
  *  equals to reg_scl_rst_slv_num[4:0].
@@ -1427,7 +1427,7 @@ extern "C" {
 /** I2C_SCL_STRETCH_CONF_REG register
  *  Set SCL stretch of I2C slave
  */
-#define I2C_SCL_STRETCH_CONF_REG (DR_REG_I2C_BASE + 0x84)
+#define I2C_SCL_STRETCH_CONF_REG(i) (REG_I2C_BASE(i) + 0x84)
 /** I2C_STRETCH_PROTECT_NUM : R/W; bitpos: [9:0]; default: 0;
  *  Configures the time period to release the SCL line from stretching to avoid timing
  *  violation. Usually it should be larger than the SDA setup time.
@@ -1483,7 +1483,7 @@ extern "C" {
 /** I2C_DATE_REG register
  *  Version register
  */
-#define I2C_DATE_REG (DR_REG_I2C_BASE + 0xf8)
+#define I2C_DATE_REG(i) (REG_I2C_BASE(i) + 0xf8)
 /** I2C_DATE : R/W; bitpos: [31:0]; default: 35656050;
  *  Version control register.
  */
@@ -1495,7 +1495,7 @@ extern "C" {
 /** I2C_TXFIFO_START_ADDR_REG register
  *  I2C TXFIFO base address register
  */
-#define I2C_TXFIFO_START_ADDR_REG (DR_REG_I2C_BASE + 0x100)
+#define I2C_TXFIFO_START_ADDR_REG(i) (REG_I2C_BASE(i) + 0x100)
 /** I2C_TXFIFO_START_ADDR : HRO; bitpos: [31:0]; default: 0;
  *  Represents the I2C txfifo first address.
  */
@@ -1507,7 +1507,7 @@ extern "C" {
 /** I2C_RXFIFO_START_ADDR_REG register
  *  I2C RXFIFO base address register
  */
-#define I2C_RXFIFO_START_ADDR_REG (DR_REG_I2C_BASE + 0x180)
+#define I2C_RXFIFO_START_ADDR_REG(i) (REG_I2C_BASE(i) + 0x180)
 /** I2C_RXFIFO_START_ADDR : HRO; bitpos: [31:0]; default: 0;
  *  Represents the I2C rxfifo first address.
  */

components/soc/esp32p4/include/soc/i2s_reg.h

@@ -14,7 +14,7 @@ extern "C" {
 /** I2S_INT_RAW_REG register
  *  I2S interrupt raw register, valid in level.
  */
-#define I2S_INT_RAW_REG (DR_REG_I2S_BASE + 0xc)
+#define I2S_INT_RAW_REG(i) (REG_I2S_BASE(i) + 0xc)
 /** I2S_RX_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
  *  The raw interrupt status bit  for the i2s_rx_done_int interrupt
  */
@@ -47,7 +47,7 @@ extern "C" {
 /** I2S_INT_ST_REG register
  *  I2S interrupt status register.
  */
-#define I2S_INT_ST_REG (DR_REG_I2S_BASE + 0x10)
+#define I2S_INT_ST_REG(i) (REG_I2S_BASE(i) + 0x10)
 /** I2S_RX_DONE_INT_ST : RO; bitpos: [0]; default: 0;
  *  The masked interrupt status bit  for the i2s_rx_done_int interrupt
  */
@@ -80,7 +80,7 @@ extern "C" {
 /** I2S_INT_ENA_REG register
  *  I2S interrupt enable register.
  */
-#define I2S_INT_ENA_REG (DR_REG_I2S_BASE + 0x14)
+#define I2S_INT_ENA_REG(i) (REG_I2S_BASE(i) + 0x14)
 /** I2S_RX_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
  *  The interrupt enable bit  for the i2s_rx_done_int interrupt
  */
@@ -113,7 +113,7 @@ extern "C" {
 /** I2S_INT_CLR_REG register
  *  I2S interrupt clear register.
  */
-#define I2S_INT_CLR_REG (DR_REG_I2S_BASE + 0x18)
+#define I2S_INT_CLR_REG(i) (REG_I2S_BASE(i) + 0x18)
 /** I2S_RX_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
  *  Set this bit to clear the i2s_rx_done_int interrupt
  */
@@ -146,7 +146,7 @@ extern "C" {
 /** I2S_RX_CONF_REG register
  *  I2S RX configure register
  */
-#define I2S_RX_CONF_REG (DR_REG_I2S_BASE + 0x20)
+#define I2S_RX_CONF_REG(i) (REG_I2S_BASE(i) + 0x20)
 /** I2S_RX_RESET : WT; bitpos: [0]; default: 0;
  *  Set this bit to reset receiver
  */
@@ -290,7 +290,7 @@ extern "C" {
 /** I2S_TX_CONF_REG register
  *  I2S TX configure register
  */
-#define I2S_TX_CONF_REG (DR_REG_I2S_BASE + 0x24)
+#define I2S_TX_CONF_REG(i) (REG_I2S_BASE(i) + 0x24)
 /** I2S_TX_RESET : WT; bitpos: [0]; default: 0;
  *  Set this bit to reset transmitter
  */
@@ -466,7 +466,7 @@ extern "C" {
 /** I2S_RX_CONF1_REG register
  *  I2S RX configure register 1
  */
-#define I2S_RX_CONF1_REG (DR_REG_I2S_BASE + 0x28)
+#define I2S_RX_CONF1_REG(i) (REG_I2S_BASE(i) + 0x28)
 /** I2S_RX_TDM_WS_WIDTH : R/W; bitpos: [8:0]; default: 0;
  *  The width of rx_ws_out at idle level in TDM mode is (I2S_RX_TDM_WS_WIDTH[8:0] +1) *
  *  T_bck
@@ -503,7 +503,7 @@ extern "C" {
 /** I2S_TX_CONF1_REG register
  *  I2S TX configure register 1
  */
-#define I2S_TX_CONF1_REG (DR_REG_I2S_BASE + 0x2c)
+#define I2S_TX_CONF1_REG(i) (REG_I2S_BASE(i) + 0x2c)
 /** I2S_TX_TDM_WS_WIDTH : R/W; bitpos: [8:0]; default: 0;
  *  The width of tx_ws_out at idle level in TDM mode is (I2S_TX_TDM_WS_WIDTH[8:0] +1) *
  *  T_bck
@@ -540,7 +540,7 @@ extern "C" {
 /** I2S_TX_PCM2PDM_CONF_REG register
  *  I2S TX PCM2PDM configuration register
  */
-#define I2S_TX_PCM2PDM_CONF_REG (DR_REG_I2S_BASE + 0x40)
+#define I2S_TX_PCM2PDM_CONF_REG(i) (REG_I2S_BASE(i) + 0x40)
 /** I2S_TX_PDM_SINC_OSR2 : R/W; bitpos: [4:1]; default: 2;
  *  I2S TX PDM OSR2 value
  */
@@ -622,7 +622,7 @@ extern "C" {
 /** I2S_TX_PCM2PDM_CONF1_REG register
  *  I2S TX PCM2PDM configuration register
  */
-#define I2S_TX_PCM2PDM_CONF1_REG (DR_REG_I2S_BASE + 0x44)
+#define I2S_TX_PCM2PDM_CONF1_REG(i) (REG_I2S_BASE(i) + 0x44)
 /** I2S_TX_PDM_FP : R/W; bitpos: [9:0]; default: 960;
  *  I2S TX PDM Fp
  */
@@ -657,7 +657,7 @@ extern "C" {
 /** I2S_RX_PDM2PCM_CONF_REG register
  *  I2S RX configure register
  */
-#define I2S_RX_PDM2PCM_CONF_REG (DR_REG_I2S_BASE + 0x48)
+#define I2S_RX_PDM2PCM_CONF_REG(i) (REG_I2S_BASE(i) + 0x48)
 /** I2S_RX_PDM2PCM_EN : R/W; bitpos: [19]; default: 0;
  *  1: Enable PDM2PCM RX mode. 0: DIsable.
  */
@@ -707,7 +707,7 @@ extern "C" {
 /** I2S_RX_TDM_CTRL_REG register
  *  I2S TX TDM mode control register
  */
-#define I2S_RX_TDM_CTRL_REG (DR_REG_I2S_BASE + 0x50)
+#define I2S_RX_TDM_CTRL_REG(i) (REG_I2S_BASE(i) + 0x50)
 /** I2S_RX_TDM_PDM_CHAN0_EN : R/W; bitpos: [0]; default: 1;
  *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
  *  input 0 in this channel.
@@ -847,7 +847,7 @@ extern "C" {
 /** I2S_TX_TDM_CTRL_REG register
  *  I2S TX TDM mode control register
  */
-#define I2S_TX_TDM_CTRL_REG (DR_REG_I2S_BASE + 0x54)
+#define I2S_TX_TDM_CTRL_REG(i) (REG_I2S_BASE(i) + 0x54)
 /** I2S_TX_TDM_CHAN0_EN : R/W; bitpos: [0]; default: 1;
  *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
  *  0 in this channel.
@@ -996,7 +996,7 @@ extern "C" {
 /** I2S_RX_TIMING_REG register
  *  I2S RX timing control register
  */
-#define I2S_RX_TIMING_REG (DR_REG_I2S_BASE + 0x58)
+#define I2S_RX_TIMING_REG(i) (REG_I2S_BASE(i) + 0x58)
 /** I2S_RX_SD_IN_DM : R/W; bitpos: [1:0]; default: 0;
  *  The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge.  2:
  *  delay by neg edge. 3: not used.
@@ -1065,7 +1065,7 @@ extern "C" {
 /** I2S_TX_TIMING_REG register
  *  I2S TX timing control register
  */
-#define I2S_TX_TIMING_REG (DR_REG_I2S_BASE + 0x5c)
+#define I2S_TX_TIMING_REG(i) (REG_I2S_BASE(i) + 0x5c)
 /** I2S_TX_SD_OUT_DM : R/W; bitpos: [1:0]; default: 0;
  *  The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge.  2:
  *  delay by neg edge. 3: not used.
@@ -1118,7 +1118,7 @@ extern "C" {
 /** I2S_LC_HUNG_CONF_REG register
  *  I2S HUNG configure register.
  */
-#define I2S_LC_HUNG_CONF_REG (DR_REG_I2S_BASE + 0x60)
+#define I2S_LC_HUNG_CONF_REG(i) (REG_I2S_BASE(i) + 0x60)
 /** I2S_LC_FIFO_TIMEOUT : R/W; bitpos: [7:0]; default: 16;
  *  the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered
  *  when fifo hung counter is equal to this value
@@ -1146,7 +1146,7 @@ extern "C" {
 /** I2S_RXEOF_NUM_REG register
  *  I2S RX data number control register.
  */
-#define I2S_RXEOF_NUM_REG (DR_REG_I2S_BASE + 0x64)
+#define I2S_RXEOF_NUM_REG(i) (REG_I2S_BASE(i) + 0x64)
 /** I2S_RX_EOF_NUM : R/W; bitpos: [11:0]; default: 64;
  *  The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] +
  *  1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel.
@@ -1159,7 +1159,7 @@ extern "C" {
 /** I2S_CONF_SIGLE_DATA_REG register
  *  I2S signal data register
  */
-#define I2S_CONF_SIGLE_DATA_REG (DR_REG_I2S_BASE + 0x68)
+#define I2S_CONF_SIGLE_DATA_REG(i) (REG_I2S_BASE(i) + 0x68)
 /** I2S_SINGLE_DATA : R/W; bitpos: [31:0]; default: 0;
  *  The configured constant channel data to be sent out.
  */
@@ -1171,7 +1171,7 @@ extern "C" {
 /** I2S_STATE_REG register
  *  I2S TX status register
  */
-#define I2S_STATE_REG (DR_REG_I2S_BASE + 0x6c)
+#define I2S_STATE_REG(i) (REG_I2S_BASE(i) + 0x6c)
 /** I2S_TX_IDLE : RO; bitpos: [0]; default: 1;
  *  1: i2s_tx is idle state. 0: i2s_tx is working.
  */
@@ -1183,7 +1183,7 @@ extern "C" {
 /** I2S_ETM_CONF_REG register
  *  I2S ETM configure register
  */
-#define I2S_ETM_CONF_REG (DR_REG_I2S_BASE + 0x70)
+#define I2S_ETM_CONF_REG(i) (REG_I2S_BASE(i) + 0x70)
 /** I2S_ETM_TX_SEND_WORD_NUM : R/W; bitpos: [9:0]; default: 64;
  *  I2S ETM send x words event. When sending word number of
  *  reg_etm_tx_send_word_num[9:0], i2s will trigger an etm event.
@@ -1204,7 +1204,7 @@ extern "C" {
 /** I2S_FIFO_CNT_REG register
  *  I2S sync counter register
  */
-#define I2S_FIFO_CNT_REG (DR_REG_I2S_BASE + 0x74)
+#define I2S_FIFO_CNT_REG(i) (REG_I2S_BASE(i) + 0x74)
 /** I2S_TX_FIFO_CNT : RO; bitpos: [30:0]; default: 0;
  *  tx fifo counter value.
  */
@@ -1223,7 +1223,7 @@ extern "C" {
 /** I2S_BCK_CNT_REG register
  *  I2S sync counter register
  */
-#define I2S_BCK_CNT_REG (DR_REG_I2S_BASE + 0x78)
+#define I2S_BCK_CNT_REG(i) (REG_I2S_BASE(i) + 0x78)
 /** I2S_TX_BCK_CNT : RO; bitpos: [30:0]; default: 0;
  *  tx bck counter value.
  */
@@ -1242,7 +1242,7 @@ extern "C" {
 /** I2S_CLK_GATE_REG register
  *  Clock gate register
  */
-#define I2S_CLK_GATE_REG (DR_REG_I2S_BASE + 0x7c)
+#define I2S_CLK_GATE_REG(i) (REG_I2S_BASE(i) + 0x7c)
 /** I2S_CLK_EN : R/W; bitpos: [0]; default: 0;
  *  set this bit to enable clock gate
  */
@@ -1254,7 +1254,7 @@ extern "C" {
 /** I2S_DATE_REG register
  *  Version control register
  */
-#define I2S_DATE_REG (DR_REG_I2S_BASE + 0x80)
+#define I2S_DATE_REG(i) (REG_I2S_BASE(i) + 0x80)
 /** I2S_DATE : R/W; bitpos: [27:0]; default: 36713024;
  *  I2S version control register
  */

components/soc/esp32p4/include/soc/lp_analog_peri_reg.h

@@ -11,1616 +11,1616 @@
 extern "C" {
 #endif
 
-/** LP_ANA_BOD_MODE0_CNTL_REG register
+/** LP_ANALOG_PERI_BOD_MODE0_CNTL_REG register
  *  need_des
  */
-#define LP_ANA_BOD_MODE0_CNTL_REG (DR_REG_LP_ANA_BASE + 0x0)
-/** LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA : R/W; bitpos: [6]; default: 0;
+#define LP_ANALOG_PERI_BOD_MODE0_CNTL_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x0)
+/** LP_ANALOG_PERI_BOD_MODE0_CLOSE_FLASH_ENA : R/W; bitpos: [6]; default: 0;
  *  need_des
  */
-#define LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA    (BIT(6))
-#define LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_M  (LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_V << LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_S)
-#define LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_V  0x00000001U
-#define LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_S  6
-/** LP_ANA_BOD_MODE0_PD_RF_ENA : R/W; bitpos: [7]; default: 0;
+#define LP_ANALOG_PERI_BOD_MODE0_CLOSE_FLASH_ENA    (BIT(6))
+#define LP_ANALOG_PERI_BOD_MODE0_CLOSE_FLASH_ENA_M  (LP_ANALOG_PERI_BOD_MODE0_CLOSE_FLASH_ENA_V << LP_ANALOG_PERI_BOD_MODE0_CLOSE_FLASH_ENA_S)
+#define LP_ANALOG_PERI_BOD_MODE0_CLOSE_FLASH_ENA_V  0x00000001U
+#define LP_ANALOG_PERI_BOD_MODE0_CLOSE_FLASH_ENA_S  6
+/** LP_ANALOG_PERI_BOD_MODE0_PD_RF_ENA : R/W; bitpos: [7]; default: 0;
  *  need_des
  */
-#define LP_ANA_BOD_MODE0_PD_RF_ENA    (BIT(7))
-#define LP_ANA_BOD_MODE0_PD_RF_ENA_M  (LP_ANA_BOD_MODE0_PD_RF_ENA_V << LP_ANA_BOD_MODE0_PD_RF_ENA_S)
-#define LP_ANA_BOD_MODE0_PD_RF_ENA_V  0x00000001U
-#define LP_ANA_BOD_MODE0_PD_RF_ENA_S  7
-/** LP_ANA_BOD_MODE0_INTR_WAIT : R/W; bitpos: [17:8]; default: 1;
+#define LP_ANALOG_PERI_BOD_MODE0_PD_RF_ENA    (BIT(7))
+#define LP_ANALOG_PERI_BOD_MODE0_PD_RF_ENA_M  (LP_ANALOG_PERI_BOD_MODE0_PD_RF_ENA_V << LP_ANALOG_PERI_BOD_MODE0_PD_RF_ENA_S)
+#define LP_ANALOG_PERI_BOD_MODE0_PD_RF_ENA_V  0x00000001U
+#define LP_ANALOG_PERI_BOD_MODE0_PD_RF_ENA_S  7
+/** LP_ANALOG_PERI_BOD_MODE0_INTR_WAIT : R/W; bitpos: [17:8]; default: 1;
  *  need_des
  */
-#define LP_ANA_BOD_MODE0_INTR_WAIT    0x000003FFU
-#define LP_ANA_BOD_MODE0_INTR_WAIT_M  (LP_ANA_BOD_MODE0_INTR_WAIT_V << LP_ANA_BOD_MODE0_INTR_WAIT_S)
-#define LP_ANA_BOD_MODE0_INTR_WAIT_V  0x000003FFU
-#define LP_ANA_BOD_MODE0_INTR_WAIT_S  8
-/** LP_ANA_BOD_MODE0_RESET_WAIT : R/W; bitpos: [27:18]; default: 1023;
+#define LP_ANALOG_PERI_BOD_MODE0_INTR_WAIT    0x000003FFU
+#define LP_ANALOG_PERI_BOD_MODE0_INTR_WAIT_M  (LP_ANALOG_PERI_BOD_MODE0_INTR_WAIT_V << LP_ANALOG_PERI_BOD_MODE0_INTR_WAIT_S)
+#define LP_ANALOG_PERI_BOD_MODE0_INTR_WAIT_V  0x000003FFU
+#define LP_ANALOG_PERI_BOD_MODE0_INTR_WAIT_S  8
+/** LP_ANALOG_PERI_BOD_MODE0_RESET_WAIT : R/W; bitpos: [27:18]; default: 1023;
  *  need_des
  */
-#define LP_ANA_BOD_MODE0_RESET_WAIT    0x000003FFU
-#define LP_ANA_BOD_MODE0_RESET_WAIT_M  (LP_ANA_BOD_MODE0_RESET_WAIT_V << LP_ANA_BOD_MODE0_RESET_WAIT_S)
-#define LP_ANA_BOD_MODE0_RESET_WAIT_V  0x000003FFU
-#define LP_ANA_BOD_MODE0_RESET_WAIT_S  18
-/** LP_ANA_BOD_MODE0_CNT_CLR : R/W; bitpos: [28]; default: 0;
+#define LP_ANALOG_PERI_BOD_MODE0_RESET_WAIT    0x000003FFU
+#define LP_ANALOG_PERI_BOD_MODE0_RESET_WAIT_M  (LP_ANALOG_PERI_BOD_MODE0_RESET_WAIT_V << LP_ANALOG_PERI_BOD_MODE0_RESET_WAIT_S)
+#define LP_ANALOG_PERI_BOD_MODE0_RESET_WAIT_V  0x000003FFU
+#define LP_ANALOG_PERI_BOD_MODE0_RESET_WAIT_S  18
+/** LP_ANALOG_PERI_BOD_MODE0_CNT_CLR : R/W; bitpos: [28]; default: 0;
  *  need_des
  */
-#define LP_ANA_BOD_MODE0_CNT_CLR    (BIT(28))
-#define LP_ANA_BOD_MODE0_CNT_CLR_M  (LP_ANA_BOD_MODE0_CNT_CLR_V << LP_ANA_BOD_MODE0_CNT_CLR_S)
-#define LP_ANA_BOD_MODE0_CNT_CLR_V  0x00000001U
-#define LP_ANA_BOD_MODE0_CNT_CLR_S  28
-/** LP_ANA_BOD_MODE0_INTR_ENA : R/W; bitpos: [29]; default: 0;
+#define LP_ANALOG_PERI_BOD_MODE0_CNT_CLR    (BIT(28))
+#define LP_ANALOG_PERI_BOD_MODE0_CNT_CLR_M  (LP_ANALOG_PERI_BOD_MODE0_CNT_CLR_V << LP_ANALOG_PERI_BOD_MODE0_CNT_CLR_S)
+#define LP_ANALOG_PERI_BOD_MODE0_CNT_CLR_V  0x00000001U
+#define LP_ANALOG_PERI_BOD_MODE0_CNT_CLR_S  28
+/** LP_ANALOG_PERI_BOD_MODE0_INTR_ENA : R/W; bitpos: [29]; default: 0;
  *  need_des
  */
-#define LP_ANA_BOD_MODE0_INTR_ENA    (BIT(29))
-#define LP_ANA_BOD_MODE0_INTR_ENA_M  (LP_ANA_BOD_MODE0_INTR_ENA_V << LP_ANA_BOD_MODE0_INTR_ENA_S)
-#define LP_ANA_BOD_MODE0_INTR_ENA_V  0x00000001U
-#define LP_ANA_BOD_MODE0_INTR_ENA_S  29
-/** LP_ANA_BOD_MODE0_RESET_SEL : R/W; bitpos: [30]; default: 0;
+#define LP_ANALOG_PERI_BOD_MODE0_INTR_ENA    (BIT(29))
+#define LP_ANALOG_PERI_BOD_MODE0_INTR_ENA_M  (LP_ANALOG_PERI_BOD_MODE0_INTR_ENA_V << LP_ANALOG_PERI_BOD_MODE0_INTR_ENA_S)
+#define LP_ANALOG_PERI_BOD_MODE0_INTR_ENA_V  0x00000001U
+#define LP_ANALOG_PERI_BOD_MODE0_INTR_ENA_S  29
+/** LP_ANALOG_PERI_BOD_MODE0_RESET_SEL : R/W; bitpos: [30]; default: 0;
  *  need_des
  */
-#define LP_ANA_BOD_MODE0_RESET_SEL    (BIT(30))
-#define LP_ANA_BOD_MODE0_RESET_SEL_M  (LP_ANA_BOD_MODE0_RESET_SEL_V << LP_ANA_BOD_MODE0_RESET_SEL_S)
-#define LP_ANA_BOD_MODE0_RESET_SEL_V  0x00000001U
-#define LP_ANA_BOD_MODE0_RESET_SEL_S  30
-/** LP_ANA_BOD_MODE0_RESET_ENA : R/W; bitpos: [31]; default: 0;
+#define LP_ANALOG_PERI_BOD_MODE0_RESET_SEL    (BIT(30))
+#define LP_ANALOG_PERI_BOD_MODE0_RESET_SEL_M  (LP_ANALOG_PERI_BOD_MODE0_RESET_SEL_V << LP_ANALOG_PERI_BOD_MODE0_RESET_SEL_S)
+#define LP_ANALOG_PERI_BOD_MODE0_RESET_SEL_V  0x00000001U
+#define LP_ANALOG_PERI_BOD_MODE0_RESET_SEL_S  30
+/** LP_ANALOG_PERI_BOD_MODE0_RESET_ENA : R/W; bitpos: [31]; default: 0;
  *  need_des
  */
-#define LP_ANA_BOD_MODE0_RESET_ENA    (BIT(31))
-#define LP_ANA_BOD_MODE0_RESET_ENA_M  (LP_ANA_BOD_MODE0_RESET_ENA_V << LP_ANA_BOD_MODE0_RESET_ENA_S)
-#define LP_ANA_BOD_MODE0_RESET_ENA_V  0x00000001U
-#define LP_ANA_BOD_MODE0_RESET_ENA_S  31
+#define LP_ANALOG_PERI_BOD_MODE0_RESET_ENA    (BIT(31))
+#define LP_ANALOG_PERI_BOD_MODE0_RESET_ENA_M  (LP_ANALOG_PERI_BOD_MODE0_RESET_ENA_V << LP_ANALOG_PERI_BOD_MODE0_RESET_ENA_S)
+#define LP_ANALOG_PERI_BOD_MODE0_RESET_ENA_V  0x00000001U
+#define LP_ANALOG_PERI_BOD_MODE0_RESET_ENA_S  31
 
-/** LP_ANA_BOD_MODE1_CNTL_REG register
+/** LP_ANALOG_PERI_BOD_MODE1_CNTL_REG register
  *  need_des
  */
-#define LP_ANA_BOD_MODE1_CNTL_REG (DR_REG_LP_ANA_BASE + 0x4)
-/** LP_ANA_BOD_MODE1_RESET_ENA : R/W; bitpos: [31]; default: 0;
+#define LP_ANALOG_PERI_BOD_MODE1_CNTL_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x4)
+/** LP_ANALOG_PERI_BOD_MODE1_RESET_ENA : R/W; bitpos: [31]; default: 0;
  *  need_des
  */
-#define LP_ANA_BOD_MODE1_RESET_ENA    (BIT(31))
-#define LP_ANA_BOD_MODE1_RESET_ENA_M  (LP_ANA_BOD_MODE1_RESET_ENA_V << LP_ANA_BOD_MODE1_RESET_ENA_S)
-#define LP_ANA_BOD_MODE1_RESET_ENA_V  0x00000001U
-#define LP_ANA_BOD_MODE1_RESET_ENA_S  31
+#define LP_ANALOG_PERI_BOD_MODE1_RESET_ENA    (BIT(31))
+#define LP_ANALOG_PERI_BOD_MODE1_RESET_ENA_M  (LP_ANALOG_PERI_BOD_MODE1_RESET_ENA_V << LP_ANALOG_PERI_BOD_MODE1_RESET_ENA_S)
+#define LP_ANALOG_PERI_BOD_MODE1_RESET_ENA_V  0x00000001U
+#define LP_ANALOG_PERI_BOD_MODE1_RESET_ENA_S  31
 
-/** LP_ANA_VDD_SOURCE_CNTL_REG register
+/** LP_ANALOG_PERI_VDD_SOURCE_CNTL_REG register
  *  need_des
  */
-#define LP_ANA_VDD_SOURCE_CNTL_REG (DR_REG_LP_ANA_BASE + 0x8)
-/** LP_ANA_DETMODE_SEL : R/W; bitpos: [7:0]; default: 255;
+#define LP_ANALOG_PERI_VDD_SOURCE_CNTL_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x8)
+/** LP_ANALOG_PERI_DETMODE_SEL : R/W; bitpos: [7:0]; default: 255;
  *  need_des
  */
-#define LP_ANA_DETMODE_SEL    0x000000FFU
-#define LP_ANA_DETMODE_SEL_M  (LP_ANA_DETMODE_SEL_V << LP_ANA_DETMODE_SEL_S)
-#define LP_ANA_DETMODE_SEL_V  0x000000FFU
-#define LP_ANA_DETMODE_SEL_S  0
-/** LP_ANA_VGOOD_EVENT_RECORD : RO; bitpos: [15:8]; default: 0;
+#define LP_ANALOG_PERI_DETMODE_SEL    0x000000FFU
+#define LP_ANALOG_PERI_DETMODE_SEL_M  (LP_ANALOG_PERI_DETMODE_SEL_V << LP_ANALOG_PERI_DETMODE_SEL_S)
+#define LP_ANALOG_PERI_DETMODE_SEL_V  0x000000FFU
+#define LP_ANALOG_PERI_DETMODE_SEL_S  0
+/** LP_ANALOG_PERI_VGOOD_EVENT_RECORD : RO; bitpos: [15:8]; default: 0;
  *  need_des
  */
-#define LP_ANA_VGOOD_EVENT_RECORD    0x000000FFU
-#define LP_ANA_VGOOD_EVENT_RECORD_M  (LP_ANA_VGOOD_EVENT_RECORD_V << LP_ANA_VGOOD_EVENT_RECORD_S)
-#define LP_ANA_VGOOD_EVENT_RECORD_V  0x000000FFU
-#define LP_ANA_VGOOD_EVENT_RECORD_S  8
-/** LP_ANA_VBAT_EVENT_RECORD_CLR : WT; bitpos: [23:16]; default: 0;
+#define LP_ANALOG_PERI_VGOOD_EVENT_RECORD    0x000000FFU
+#define LP_ANALOG_PERI_VGOOD_EVENT_RECORD_M  (LP_ANALOG_PERI_VGOOD_EVENT_RECORD_V << LP_ANALOG_PERI_VGOOD_EVENT_RECORD_S)
+#define LP_ANALOG_PERI_VGOOD_EVENT_RECORD_V  0x000000FFU
+#define LP_ANALOG_PERI_VGOOD_EVENT_RECORD_S  8
+/** LP_ANALOG_PERI_VBAT_EVENT_RECORD_CLR : WT; bitpos: [23:16]; default: 0;
  *  need_des
  */
-#define LP_ANA_VBAT_EVENT_RECORD_CLR    0x000000FFU
-#define LP_ANA_VBAT_EVENT_RECORD_CLR_M  (LP_ANA_VBAT_EVENT_RECORD_CLR_V << LP_ANA_VBAT_EVENT_RECORD_CLR_S)
-#define LP_ANA_VBAT_EVENT_RECORD_CLR_V  0x000000FFU
-#define LP_ANA_VBAT_EVENT_RECORD_CLR_S  16
-/** LP_ANA_BOD_SOURCE_ENA : R/W; bitpos: [31:24]; default: 4;
+#define LP_ANALOG_PERI_VBAT_EVENT_RECORD_CLR    0x000000FFU
+#define LP_ANALOG_PERI_VBAT_EVENT_RECORD_CLR_M  (LP_ANALOG_PERI_VBAT_EVENT_RECORD_CLR_V << LP_ANALOG_PERI_VBAT_EVENT_RECORD_CLR_S)
+#define LP_ANALOG_PERI_VBAT_EVENT_RECORD_CLR_V  0x000000FFU
+#define LP_ANALOG_PERI_VBAT_EVENT_RECORD_CLR_S  16
+/** LP_ANALOG_PERI_BOD_SOURCE_ENA : R/W; bitpos: [31:24]; default: 4;
  *  need_des
  */
-#define LP_ANA_BOD_SOURCE_ENA    0x000000FFU
-#define LP_ANA_BOD_SOURCE_ENA_M  (LP_ANA_BOD_SOURCE_ENA_V << LP_ANA_BOD_SOURCE_ENA_S)
-#define LP_ANA_BOD_SOURCE_ENA_V  0x000000FFU
-#define LP_ANA_BOD_SOURCE_ENA_S  24
+#define LP_ANALOG_PERI_BOD_SOURCE_ENA    0x000000FFU
+#define LP_ANALOG_PERI_BOD_SOURCE_ENA_M  (LP_ANALOG_PERI_BOD_SOURCE_ENA_V << LP_ANALOG_PERI_BOD_SOURCE_ENA_S)
+#define LP_ANALOG_PERI_BOD_SOURCE_ENA_V  0x000000FFU
+#define LP_ANALOG_PERI_BOD_SOURCE_ENA_S  24
 
-/** LP_ANA_VDDBAT_BOD_CNTL_REG register
+/** LP_ANALOG_PERI_VDDBAT_BOD_CNTL_REG register
  *  need_des
  */
-#define LP_ANA_VDDBAT_BOD_CNTL_REG (DR_REG_LP_ANA_BASE + 0xc)
-/** LP_ANA_VDDBAT_UNDERVOLTAGE_FLAG : RO; bitpos: [0]; default: 0;
+#define LP_ANALOG_PERI_VDDBAT_BOD_CNTL_REG (DR_REG_LP_ANALOG_PERI_BASE + 0xc)
+/** LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_FLAG : RO; bitpos: [0]; default: 0;
  *  need_des
  */
-#define LP_ANA_VDDBAT_UNDERVOLTAGE_FLAG    (BIT(0))
-#define LP_ANA_VDDBAT_UNDERVOLTAGE_FLAG_M  (LP_ANA_VDDBAT_UNDERVOLTAGE_FLAG_V << LP_ANA_VDDBAT_UNDERVOLTAGE_FLAG_S)
-#define LP_ANA_VDDBAT_UNDERVOLTAGE_FLAG_V  0x00000001U
-#define LP_ANA_VDDBAT_UNDERVOLTAGE_FLAG_S  0
-/** LP_ANA_VDDBAT_CHARGER : R/W; bitpos: [10]; default: 0;
+#define LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_FLAG    (BIT(0))
+#define LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_FLAG_M  (LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_FLAG_V << LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_FLAG_S)
+#define LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_FLAG_V  0x00000001U
+#define LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_FLAG_S  0
+/** LP_ANALOG_PERI_VDDBAT_CHARGER : R/W; bitpos: [10]; default: 0;
  *  need_des
  */
-#define LP_ANA_VDDBAT_CHARGER    (BIT(10))
-#define LP_ANA_VDDBAT_CHARGER_M  (LP_ANA_VDDBAT_CHARGER_V << LP_ANA_VDDBAT_CHARGER_S)
-#define LP_ANA_VDDBAT_CHARGER_V  0x00000001U
-#define LP_ANA_VDDBAT_CHARGER_S  10
-/** LP_ANA_VDDBAT_CNT_CLR : R/W; bitpos: [11]; default: 0;
+#define LP_ANALOG_PERI_VDDBAT_CHARGER    (BIT(10))
+#define LP_ANALOG_PERI_VDDBAT_CHARGER_M  (LP_ANALOG_PERI_VDDBAT_CHARGER_V << LP_ANALOG_PERI_VDDBAT_CHARGER_S)
+#define LP_ANALOG_PERI_VDDBAT_CHARGER_V  0x00000001U
+#define LP_ANALOG_PERI_VDDBAT_CHARGER_S  10
+/** LP_ANALOG_PERI_VDDBAT_CNT_CLR : R/W; bitpos: [11]; default: 0;
  *  need_des
  */
-#define LP_ANA_VDDBAT_CNT_CLR    (BIT(11))
-#define LP_ANA_VDDBAT_CNT_CLR_M  (LP_ANA_VDDBAT_CNT_CLR_V << LP_ANA_VDDBAT_CNT_CLR_S)
-#define LP_ANA_VDDBAT_CNT_CLR_V  0x00000001U
-#define LP_ANA_VDDBAT_CNT_CLR_S  11
-/** LP_ANA_VDDBAT_UPVOLTAGE_TARGET : R/W; bitpos: [21:12]; default: 0;
+#define LP_ANALOG_PERI_VDDBAT_CNT_CLR    (BIT(11))
+#define LP_ANALOG_PERI_VDDBAT_CNT_CLR_M  (LP_ANALOG_PERI_VDDBAT_CNT_CLR_V << LP_ANALOG_PERI_VDDBAT_CNT_CLR_S)
+#define LP_ANALOG_PERI_VDDBAT_CNT_CLR_V  0x00000001U
+#define LP_ANALOG_PERI_VDDBAT_CNT_CLR_S  11
+/** LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_TARGET : R/W; bitpos: [21:12]; default: 0;
  *  need_des
  */
-#define LP_ANA_VDDBAT_UPVOLTAGE_TARGET    0x000003FFU
-#define LP_ANA_VDDBAT_UPVOLTAGE_TARGET_M  (LP_ANA_VDDBAT_UPVOLTAGE_TARGET_V << LP_ANA_VDDBAT_UPVOLTAGE_TARGET_S)
-#define LP_ANA_VDDBAT_UPVOLTAGE_TARGET_V  0x000003FFU
-#define LP_ANA_VDDBAT_UPVOLTAGE_TARGET_S  12
-/** LP_ANA_VDDBAT_UNDERVOLTAGE_TARGET : R/W; bitpos: [31:22]; default: 1023;
+#define LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_TARGET    0x000003FFU
+#define LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_TARGET_M  (LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_TARGET_V << LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_TARGET_S)
+#define LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_TARGET_V  0x000003FFU
+#define LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_TARGET_S  12
+/** LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_TARGET : R/W; bitpos: [31:22]; default: 1023;
  *  need_des
  */
-#define LP_ANA_VDDBAT_UNDERVOLTAGE_TARGET    0x000003FFU
-#define LP_ANA_VDDBAT_UNDERVOLTAGE_TARGET_M  (LP_ANA_VDDBAT_UNDERVOLTAGE_TARGET_V << LP_ANA_VDDBAT_UNDERVOLTAGE_TARGET_S)
-#define LP_ANA_VDDBAT_UNDERVOLTAGE_TARGET_V  0x000003FFU
-#define LP_ANA_VDDBAT_UNDERVOLTAGE_TARGET_S  22
+#define LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_TARGET    0x000003FFU
+#define LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_TARGET_M  (LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_TARGET_V << LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_TARGET_S)
+#define LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_TARGET_V  0x000003FFU
+#define LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_TARGET_S  22
 
-/** LP_ANA_VDDBAT_CHARGE_CNTL_REG register
+/** LP_ANALOG_PERI_VDDBAT_CHARGE_CNTL_REG register
  *  need_des
  */
-#define LP_ANA_VDDBAT_CHARGE_CNTL_REG (DR_REG_LP_ANA_BASE + 0x10)
-/** LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_FLAG : RO; bitpos: [0]; default: 0;
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_CNTL_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x10)
+/** LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_FLAG : RO; bitpos: [0]; default: 0;
  *  need_des
  */
-#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_FLAG    (BIT(0))
-#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_FLAG_M  (LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_FLAG_V << LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_FLAG_S)
-#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_FLAG_V  0x00000001U
-#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_FLAG_S  0
-/** LP_ANA_VDDBAT_CHARGE_CHARGER : R/W; bitpos: [10]; default: 0;
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_FLAG    (BIT(0))
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_FLAG_M  (LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_FLAG_V << LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_FLAG_S)
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_FLAG_V  0x00000001U
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_FLAG_S  0
+/** LP_ANALOG_PERI_VDDBAT_CHARGE_CHARGER : R/W; bitpos: [10]; default: 0;
  *  need_des
  */
-#define LP_ANA_VDDBAT_CHARGE_CHARGER    (BIT(10))
-#define LP_ANA_VDDBAT_CHARGE_CHARGER_M  (LP_ANA_VDDBAT_CHARGE_CHARGER_V << LP_ANA_VDDBAT_CHARGE_CHARGER_S)
-#define LP_ANA_VDDBAT_CHARGE_CHARGER_V  0x00000001U
-#define LP_ANA_VDDBAT_CHARGE_CHARGER_S  10
-/** LP_ANA_VDDBAT_CHARGE_CNT_CLR : R/W; bitpos: [11]; default: 0;
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_CHARGER    (BIT(10))
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_CHARGER_M  (LP_ANALOG_PERI_VDDBAT_CHARGE_CHARGER_V << LP_ANALOG_PERI_VDDBAT_CHARGE_CHARGER_S)
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_CHARGER_V  0x00000001U
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_CHARGER_S  10
+/** LP_ANALOG_PERI_VDDBAT_CHARGE_CNT_CLR : R/W; bitpos: [11]; default: 0;
  *  need_des
  */
-#define LP_ANA_VDDBAT_CHARGE_CNT_CLR    (BIT(11))
-#define LP_ANA_VDDBAT_CHARGE_CNT_CLR_M  (LP_ANA_VDDBAT_CHARGE_CNT_CLR_V << LP_ANA_VDDBAT_CHARGE_CNT_CLR_S)
-#define LP_ANA_VDDBAT_CHARGE_CNT_CLR_V  0x00000001U
-#define LP_ANA_VDDBAT_CHARGE_CNT_CLR_S  11
-/** LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_TARGET : R/W; bitpos: [21:12]; default: 0;
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_CNT_CLR    (BIT(11))
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_CNT_CLR_M  (LP_ANALOG_PERI_VDDBAT_CHARGE_CNT_CLR_V << LP_ANALOG_PERI_VDDBAT_CHARGE_CNT_CLR_S)
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_CNT_CLR_V  0x00000001U
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_CNT_CLR_S  11
+/** LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_TARGET : R/W; bitpos: [21:12]; default: 0;
  *  need_des
  */
-#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_TARGET    0x000003FFU
-#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_TARGET_M  (LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_TARGET_V << LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_TARGET_S)
-#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_TARGET_V  0x000003FFU
-#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_TARGET_S  12
-/** LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET : R/W; bitpos: [31:22]; default: 1023;
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_TARGET    0x000003FFU
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_TARGET_M  (LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_TARGET_V << LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_TARGET_S)
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_TARGET_V  0x000003FFU
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_TARGET_S  12
+/** LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET : R/W; bitpos: [31:22]; default: 1023;
  *  need_des
  */
-#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET    0x000003FFU
-#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET_M  (LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET_V << LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET_S)
-#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET_V  0x000003FFU
-#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET_S  22
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET    0x000003FFU
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET_M  (LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET_V << LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET_S)
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET_V  0x000003FFU
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET_S  22
 
-/** LP_ANA_CK_GLITCH_CNTL_REG register
+/** LP_ANALOG_PERI_CK_GLITCH_CNTL_REG register
  *  need_des
  */
-#define LP_ANA_CK_GLITCH_CNTL_REG (DR_REG_LP_ANA_BASE + 0x14)
-/** LP_ANA_CK_GLITCH_RESET_ENA : R/W; bitpos: [31]; default: 0;
+#define LP_ANALOG_PERI_CK_GLITCH_CNTL_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x14)
+/** LP_ANALOG_PERI_CK_GLITCH_RESET_ENA : R/W; bitpos: [31]; default: 0;
  *  need_des
  */
-#define LP_ANA_CK_GLITCH_RESET_ENA    (BIT(31))
-#define LP_ANA_CK_GLITCH_RESET_ENA_M  (LP_ANA_CK_GLITCH_RESET_ENA_V << LP_ANA_CK_GLITCH_RESET_ENA_S)
-#define LP_ANA_CK_GLITCH_RESET_ENA_V  0x00000001U
-#define LP_ANA_CK_GLITCH_RESET_ENA_S  31
+#define LP_ANALOG_PERI_CK_GLITCH_RESET_ENA    (BIT(31))
+#define LP_ANALOG_PERI_CK_GLITCH_RESET_ENA_M  (LP_ANALOG_PERI_CK_GLITCH_RESET_ENA_V << LP_ANALOG_PERI_CK_GLITCH_RESET_ENA_S)
+#define LP_ANALOG_PERI_CK_GLITCH_RESET_ENA_V  0x00000001U
+#define LP_ANALOG_PERI_CK_GLITCH_RESET_ENA_S  31
 
-/** LP_ANA_PG_GLITCH_CNTL_REG register
+/** LP_ANALOG_PERI_PG_GLITCH_CNTL_REG register
  *  need_des
  */
-#define LP_ANA_PG_GLITCH_CNTL_REG (DR_REG_LP_ANA_BASE + 0x18)
-/** LP_ANA_POWER_GLITCH_RESET_ENA : R/W; bitpos: [31]; default: 0;
+#define LP_ANALOG_PERI_PG_GLITCH_CNTL_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x18)
+/** LP_ANALOG_PERI_POWER_GLITCH_RESET_ENA : R/W; bitpos: [31]; default: 0;
  *  need_des
  */
-#define LP_ANA_POWER_GLITCH_RESET_ENA    (BIT(31))
-#define LP_ANA_POWER_GLITCH_RESET_ENA_M  (LP_ANA_POWER_GLITCH_RESET_ENA_V << LP_ANA_POWER_GLITCH_RESET_ENA_S)
-#define LP_ANA_POWER_GLITCH_RESET_ENA_V  0x00000001U
-#define LP_ANA_POWER_GLITCH_RESET_ENA_S  31
+#define LP_ANALOG_PERI_POWER_GLITCH_RESET_ENA    (BIT(31))
+#define LP_ANALOG_PERI_POWER_GLITCH_RESET_ENA_M  (LP_ANALOG_PERI_POWER_GLITCH_RESET_ENA_V << LP_ANALOG_PERI_POWER_GLITCH_RESET_ENA_S)
+#define LP_ANALOG_PERI_POWER_GLITCH_RESET_ENA_V  0x00000001U
+#define LP_ANALOG_PERI_POWER_GLITCH_RESET_ENA_S  31
 
-/** LP_ANA_FIB_ENABLE_REG register
+/** LP_ANALOG_PERI_FIB_ENABLE_REG register
  *  need_des
  */
-#define LP_ANA_FIB_ENABLE_REG (DR_REG_LP_ANA_BASE + 0x1c)
-/** LP_ANA_ANA_FIB_ENA : R/W; bitpos: [31:0]; default: 4294967295;
+#define LP_ANALOG_PERI_FIB_ENABLE_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x1c)
+/** LP_ANALOG_PERI_ANA_FIB_ENA : R/W; bitpos: [31:0]; default: 4294967295;
  *  need_des
  */
-#define LP_ANA_ANA_FIB_ENA    0xFFFFFFFFU
-#define LP_ANA_ANA_FIB_ENA_M  (LP_ANA_ANA_FIB_ENA_V << LP_ANA_ANA_FIB_ENA_S)
-#define LP_ANA_ANA_FIB_ENA_V  0xFFFFFFFFU
-#define LP_ANA_ANA_FIB_ENA_S  0
+#define LP_ANALOG_PERI_ANA_FIB_ENA    0xFFFFFFFFU
+#define LP_ANALOG_PERI_ANA_FIB_ENA_M  (LP_ANALOG_PERI_ANA_FIB_ENA_V << LP_ANALOG_PERI_ANA_FIB_ENA_S)
+#define LP_ANALOG_PERI_ANA_FIB_ENA_V  0xFFFFFFFFU
+#define LP_ANALOG_PERI_ANA_FIB_ENA_S  0
 
-/** LP_ANA_INT_RAW_REG register
+/** LP_ANALOG_PERI_INT_RAW_REG register
  *  need_des
  */
-#define LP_ANA_INT_RAW_REG (DR_REG_LP_ANA_BASE + 0x20)
-/** LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0;
+#define LP_ANALOG_PERI_INT_RAW_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x20)
+/** LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0;
  *  need_des
  */
-#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_RAW    (BIT(27))
-#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_RAW_M  (LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_RAW_V << LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_RAW_S)
-#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_RAW_V  0x00000001U
-#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_RAW_S  27
-/** LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0;
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_INT_RAW    (BIT(27))
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_INT_RAW_M  (LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_INT_RAW_V << LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_INT_RAW_S)
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_INT_RAW_V  0x00000001U
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_INT_RAW_S  27
+/** LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0;
  *  need_des
  */
-#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW    (BIT(28))
-#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW_M  (LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW_V << LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW_S)
-#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW_V  0x00000001U
-#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW_S  28
-/** LP_ANA_VDDBAT_UPVOLTAGE_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0;
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW    (BIT(28))
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW_M  (LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW_V << LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW_S)
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW_V  0x00000001U
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW_S  28
+/** LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0;
  *  need_des
  */
-#define LP_ANA_VDDBAT_UPVOLTAGE_INT_RAW    (BIT(29))
-#define LP_ANA_VDDBAT_UPVOLTAGE_INT_RAW_M  (LP_ANA_VDDBAT_UPVOLTAGE_INT_RAW_V << LP_ANA_VDDBAT_UPVOLTAGE_INT_RAW_S)
-#define LP_ANA_VDDBAT_UPVOLTAGE_INT_RAW_V  0x00000001U
-#define LP_ANA_VDDBAT_UPVOLTAGE_INT_RAW_S  29
-/** LP_ANA_VDDBAT_UNDERVOLTAGE_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0;
+#define LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_INT_RAW    (BIT(29))
+#define LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_INT_RAW_M  (LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_INT_RAW_V << LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_INT_RAW_S)
+#define LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_INT_RAW_V  0x00000001U
+#define LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_INT_RAW_S  29
+/** LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0;
  *  need_des
  */
-#define LP_ANA_VDDBAT_UNDERVOLTAGE_INT_RAW    (BIT(30))
-#define LP_ANA_VDDBAT_UNDERVOLTAGE_INT_RAW_M  (LP_ANA_VDDBAT_UNDERVOLTAGE_INT_RAW_V << LP_ANA_VDDBAT_UNDERVOLTAGE_INT_RAW_S)
-#define LP_ANA_VDDBAT_UNDERVOLTAGE_INT_RAW_V  0x00000001U
-#define LP_ANA_VDDBAT_UNDERVOLTAGE_INT_RAW_S  30
-/** LP_ANA_BOD_MODE0_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
+#define LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_INT_RAW    (BIT(30))
+#define LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_INT_RAW_M  (LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_INT_RAW_V << LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_INT_RAW_S)
+#define LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_INT_RAW_V  0x00000001U
+#define LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_INT_RAW_S  30
+/** LP_ANALOG_PERI_BOD_MODE0_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
  *  need_des
  */
-#define LP_ANA_BOD_MODE0_INT_RAW    (BIT(31))
-#define LP_ANA_BOD_MODE0_INT_RAW_M  (LP_ANA_BOD_MODE0_INT_RAW_V << LP_ANA_BOD_MODE0_INT_RAW_S)
-#define LP_ANA_BOD_MODE0_INT_RAW_V  0x00000001U
-#define LP_ANA_BOD_MODE0_INT_RAW_S  31
+#define LP_ANALOG_PERI_BOD_MODE0_INT_RAW    (BIT(31))
+#define LP_ANALOG_PERI_BOD_MODE0_INT_RAW_M  (LP_ANALOG_PERI_BOD_MODE0_INT_RAW_V << LP_ANALOG_PERI_BOD_MODE0_INT_RAW_S)
+#define LP_ANALOG_PERI_BOD_MODE0_INT_RAW_V  0x00000001U
+#define LP_ANALOG_PERI_BOD_MODE0_INT_RAW_S  31
 
-/** LP_ANA_INT_ST_REG register
+/** LP_ANALOG_PERI_INT_ST_REG register
  *  need_des
  */
-#define LP_ANA_INT_ST_REG (DR_REG_LP_ANA_BASE + 0x24)
-/** LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ST : RO; bitpos: [27]; default: 0;
+#define LP_ANALOG_PERI_INT_ST_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x24)
+/** LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_INT_ST : RO; bitpos: [27]; default: 0;
  *  need_des
  */
-#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ST    (BIT(27))
-#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ST_M  (LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ST_V << LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ST_S)
-#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ST_V  0x00000001U
-#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ST_S  27
-/** LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ST : RO; bitpos: [28]; default: 0;
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_INT_ST    (BIT(27))
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_INT_ST_M  (LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_INT_ST_V << LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_INT_ST_S)
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_INT_ST_V  0x00000001U
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_INT_ST_S  27
+/** LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ST : RO; bitpos: [28]; default: 0;
  *  need_des
  */
-#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ST    (BIT(28))
-#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ST_M  (LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ST_V << LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ST_S)
-#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ST_V  0x00000001U
-#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ST_S  28
-/** LP_ANA_VDDBAT_UPVOLTAGE_INT_ST : RO; bitpos: [29]; default: 0;
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ST    (BIT(28))
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ST_M  (LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ST_V << LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ST_S)
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ST_V  0x00000001U
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ST_S  28
+/** LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_INT_ST : RO; bitpos: [29]; default: 0;
  *  need_des
  */
-#define LP_ANA_VDDBAT_UPVOLTAGE_INT_ST    (BIT(29))
-#define LP_ANA_VDDBAT_UPVOLTAGE_INT_ST_M  (LP_ANA_VDDBAT_UPVOLTAGE_INT_ST_V << LP_ANA_VDDBAT_UPVOLTAGE_INT_ST_S)
-#define LP_ANA_VDDBAT_UPVOLTAGE_INT_ST_V  0x00000001U
-#define LP_ANA_VDDBAT_UPVOLTAGE_INT_ST_S  29
-/** LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ST : RO; bitpos: [30]; default: 0;
+#define LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_INT_ST    (BIT(29))
+#define LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_INT_ST_M  (LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_INT_ST_V << LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_INT_ST_S)
+#define LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_INT_ST_V  0x00000001U
+#define LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_INT_ST_S  29
+/** LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_INT_ST : RO; bitpos: [30]; default: 0;
  *  need_des
  */
-#define LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ST    (BIT(30))
-#define LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ST_M  (LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ST_V << LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ST_S)
-#define LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ST_V  0x00000001U
-#define LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ST_S  30
-/** LP_ANA_BOD_MODE0_INT_ST : RO; bitpos: [31]; default: 0;
+#define LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_INT_ST    (BIT(30))
+#define LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_INT_ST_M  (LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_INT_ST_V << LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_INT_ST_S)
+#define LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_INT_ST_V  0x00000001U
+#define LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_INT_ST_S  30
+/** LP_ANALOG_PERI_BOD_MODE0_INT_ST : RO; bitpos: [31]; default: 0;
  *  need_des
  */
-#define LP_ANA_BOD_MODE0_INT_ST    (BIT(31))
-#define LP_ANA_BOD_MODE0_INT_ST_M  (LP_ANA_BOD_MODE0_INT_ST_V << LP_ANA_BOD_MODE0_INT_ST_S)
-#define LP_ANA_BOD_MODE0_INT_ST_V  0x00000001U
-#define LP_ANA_BOD_MODE0_INT_ST_S  31
+#define LP_ANALOG_PERI_BOD_MODE0_INT_ST    (BIT(31))
+#define LP_ANALOG_PERI_BOD_MODE0_INT_ST_M  (LP_ANALOG_PERI_BOD_MODE0_INT_ST_V << LP_ANALOG_PERI_BOD_MODE0_INT_ST_S)
+#define LP_ANALOG_PERI_BOD_MODE0_INT_ST_V  0x00000001U
+#define LP_ANALOG_PERI_BOD_MODE0_INT_ST_S  31
 
-/** LP_ANA_INT_ENA_REG register
+/** LP_ANALOG_PERI_INT_ENA_REG register
  *  need_des
  */
-#define LP_ANA_INT_ENA_REG (DR_REG_LP_ANA_BASE + 0x28)
-/** LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ENA : R/W; bitpos: [27]; default: 0;
+#define LP_ANALOG_PERI_INT_ENA_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x28)
+/** LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_INT_ENA : R/W; bitpos: [27]; default: 0;
  *  need_des
  */
-#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ENA    (BIT(27))
-#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ENA_M  (LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ENA_V << LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ENA_S)
-#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ENA_V  0x00000001U
-#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ENA_S  27
-/** LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA : R/W; bitpos: [28]; default: 0;
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_INT_ENA    (BIT(27))
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_INT_ENA_M  (LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_INT_ENA_V << LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_INT_ENA_S)
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_INT_ENA_V  0x00000001U
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_INT_ENA_S  27
+/** LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA : R/W; bitpos: [28]; default: 0;
  *  need_des
  */
-#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA    (BIT(28))
-#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA_M  (LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA_V << LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA_S)
-#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA_V  0x00000001U
-#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA_S  28
-/** LP_ANA_VDDBAT_UPVOLTAGE_INT_ENA : R/W; bitpos: [29]; default: 0;
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA    (BIT(28))
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA_M  (LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA_V << LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA_S)
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA_V  0x00000001U
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA_S  28
+/** LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_INT_ENA : R/W; bitpos: [29]; default: 0;
  *  need_des
  */
-#define LP_ANA_VDDBAT_UPVOLTAGE_INT_ENA    (BIT(29))
-#define LP_ANA_VDDBAT_UPVOLTAGE_INT_ENA_M  (LP_ANA_VDDBAT_UPVOLTAGE_INT_ENA_V << LP_ANA_VDDBAT_UPVOLTAGE_INT_ENA_S)
-#define LP_ANA_VDDBAT_UPVOLTAGE_INT_ENA_V  0x00000001U
-#define LP_ANA_VDDBAT_UPVOLTAGE_INT_ENA_S  29
-/** LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ENA : R/W; bitpos: [30]; default: 0;
+#define LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_INT_ENA    (BIT(29))
+#define LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_INT_ENA_M  (LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_INT_ENA_V << LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_INT_ENA_S)
+#define LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_INT_ENA_V  0x00000001U
+#define LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_INT_ENA_S  29
+/** LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_INT_ENA : R/W; bitpos: [30]; default: 0;
  *  need_des
  */
-#define LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ENA    (BIT(30))
-#define LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ENA_M  (LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ENA_V << LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ENA_S)
-#define LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ENA_V  0x00000001U
-#define LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ENA_S  30
-/** LP_ANA_BOD_MODE0_INT_ENA : R/W; bitpos: [31]; default: 0;
+#define LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_INT_ENA    (BIT(30))
+#define LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_INT_ENA_M  (LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_INT_ENA_V << LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_INT_ENA_S)
+#define LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_INT_ENA_V  0x00000001U
+#define LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_INT_ENA_S  30
+/** LP_ANALOG_PERI_BOD_MODE0_INT_ENA : R/W; bitpos: [31]; default: 0;
  *  need_des
  */
-#define LP_ANA_BOD_MODE0_INT_ENA    (BIT(31))
-#define LP_ANA_BOD_MODE0_INT_ENA_M  (LP_ANA_BOD_MODE0_INT_ENA_V << LP_ANA_BOD_MODE0_INT_ENA_S)
-#define LP_ANA_BOD_MODE0_INT_ENA_V  0x00000001U
-#define LP_ANA_BOD_MODE0_INT_ENA_S  31
+#define LP_ANALOG_PERI_BOD_MODE0_INT_ENA    (BIT(31))
+#define LP_ANALOG_PERI_BOD_MODE0_INT_ENA_M  (LP_ANALOG_PERI_BOD_MODE0_INT_ENA_V << LP_ANALOG_PERI_BOD_MODE0_INT_ENA_S)
+#define LP_ANALOG_PERI_BOD_MODE0_INT_ENA_V  0x00000001U
+#define LP_ANALOG_PERI_BOD_MODE0_INT_ENA_S  31
 
-/** LP_ANA_INT_CLR_REG register
+/** LP_ANALOG_PERI_INT_CLR_REG register
  *  need_des
  */
-#define LP_ANA_INT_CLR_REG (DR_REG_LP_ANA_BASE + 0x2c)
-/** LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_CLR : WT; bitpos: [27]; default: 0;
+#define LP_ANALOG_PERI_INT_CLR_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x2c)
+/** LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_INT_CLR : WT; bitpos: [27]; default: 0;
  *  need_des
  */
-#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_CLR    (BIT(27))
-#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_CLR_M  (LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_CLR_V << LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_CLR_S)
-#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_CLR_V  0x00000001U
-#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_CLR_S  27
-/** LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_CLR : WT; bitpos: [28]; default: 0;
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_INT_CLR    (BIT(27))
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_INT_CLR_M  (LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_INT_CLR_V << LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_INT_CLR_S)
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_INT_CLR_V  0x00000001U
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_UPVOLTAGE_INT_CLR_S  27
+/** LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_INT_CLR : WT; bitpos: [28]; default: 0;
  *  need_des
  */
-#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_CLR    (BIT(28))
-#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_CLR_M  (LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_CLR_V << LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_CLR_S)
-#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_CLR_V  0x00000001U
-#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_CLR_S  28
-/** LP_ANA_VDDBAT_UPVOLTAGE_INT_CLR : WT; bitpos: [29]; default: 0;
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_INT_CLR    (BIT(28))
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_INT_CLR_M  (LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_INT_CLR_V << LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_INT_CLR_S)
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_INT_CLR_V  0x00000001U
+#define LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_INT_CLR_S  28
+/** LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_INT_CLR : WT; bitpos: [29]; default: 0;
  *  need_des
  */
-#define LP_ANA_VDDBAT_UPVOLTAGE_INT_CLR    (BIT(29))
-#define LP_ANA_VDDBAT_UPVOLTAGE_INT_CLR_M  (LP_ANA_VDDBAT_UPVOLTAGE_INT_CLR_V << LP_ANA_VDDBAT_UPVOLTAGE_INT_CLR_S)
-#define LP_ANA_VDDBAT_UPVOLTAGE_INT_CLR_V  0x00000001U
-#define LP_ANA_VDDBAT_UPVOLTAGE_INT_CLR_S  29
-/** LP_ANA_VDDBAT_UNDERVOLTAGE_INT_CLR : WT; bitpos: [30]; default: 0;
+#define LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_INT_CLR    (BIT(29))
+#define LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_INT_CLR_M  (LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_INT_CLR_V << LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_INT_CLR_S)
+#define LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_INT_CLR_V  0x00000001U
+#define LP_ANALOG_PERI_VDDBAT_UPVOLTAGE_INT_CLR_S  29
+/** LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_INT_CLR : WT; bitpos: [30]; default: 0;
  *  need_des
  */
-#define LP_ANA_VDDBAT_UNDERVOLTAGE_INT_CLR    (BIT(30))
-#define LP_ANA_VDDBAT_UNDERVOLTAGE_INT_CLR_M  (LP_ANA_VDDBAT_UNDERVOLTAGE_INT_CLR_V << LP_ANA_VDDBAT_UNDERVOLTAGE_INT_CLR_S)
-#define LP_ANA_VDDBAT_UNDERVOLTAGE_INT_CLR_V  0x00000001U
-#define LP_ANA_VDDBAT_UNDERVOLTAGE_INT_CLR_S  30
-/** LP_ANA_BOD_MODE0_INT_CLR : WT; bitpos: [31]; default: 0;
+#define LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_INT_CLR    (BIT(30))
+#define LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_INT_CLR_M  (LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_INT_CLR_V << LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_INT_CLR_S)
+#define LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_INT_CLR_V  0x00000001U
+#define LP_ANALOG_PERI_VDDBAT_UNDERVOLTAGE_INT_CLR_S  30
+/** LP_ANALOG_PERI_BOD_MODE0_INT_CLR : WT; bitpos: [31]; default: 0;
  *  need_des
  */
-#define LP_ANA_BOD_MODE0_INT_CLR    (BIT(31))
-#define LP_ANA_BOD_MODE0_INT_CLR_M  (LP_ANA_BOD_MODE0_INT_CLR_V << LP_ANA_BOD_MODE0_INT_CLR_S)
-#define LP_ANA_BOD_MODE0_INT_CLR_V  0x00000001U
-#define LP_ANA_BOD_MODE0_INT_CLR_S  31
+#define LP_ANALOG_PERI_BOD_MODE0_INT_CLR    (BIT(31))
+#define LP_ANALOG_PERI_BOD_MODE0_INT_CLR_M  (LP_ANALOG_PERI_BOD_MODE0_INT_CLR_V << LP_ANALOG_PERI_BOD_MODE0_INT_CLR_S)
+#define LP_ANALOG_PERI_BOD_MODE0_INT_CLR_V  0x00000001U
+#define LP_ANALOG_PERI_BOD_MODE0_INT_CLR_S  31
 
-/** LP_ANA_LP_INT_RAW_REG register
+/** LP_ANALOG_PERI_LP_INT_RAW_REG register
  *  need_des
  */
-#define LP_ANA_LP_INT_RAW_REG (DR_REG_LP_ANA_BASE + 0x30)
-/** LP_ANA_BOD_MODE0_LP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
+#define LP_ANALOG_PERI_LP_INT_RAW_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x30)
+/** LP_ANALOG_PERI_BOD_MODE0_LP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
  *  need_des
  */
-#define LP_ANA_BOD_MODE0_LP_INT_RAW    (BIT(31))
-#define LP_ANA_BOD_MODE0_LP_INT_RAW_M  (LP_ANA_BOD_MODE0_LP_INT_RAW_V << LP_ANA_BOD_MODE0_LP_INT_RAW_S)
-#define LP_ANA_BOD_MODE0_LP_INT_RAW_V  0x00000001U
-#define LP_ANA_BOD_MODE0_LP_INT_RAW_S  31
+#define LP_ANALOG_PERI_BOD_MODE0_LP_INT_RAW    (BIT(31))
+#define LP_ANALOG_PERI_BOD_MODE0_LP_INT_RAW_M  (LP_ANALOG_PERI_BOD_MODE0_LP_INT_RAW_V << LP_ANALOG_PERI_BOD_MODE0_LP_INT_RAW_S)
+#define LP_ANALOG_PERI_BOD_MODE0_LP_INT_RAW_V  0x00000001U
+#define LP_ANALOG_PERI_BOD_MODE0_LP_INT_RAW_S  31
 
-/** LP_ANA_LP_INT_ST_REG register
+/** LP_ANALOG_PERI_LP_INT_ST_REG register
  *  need_des
  */
-#define LP_ANA_LP_INT_ST_REG (DR_REG_LP_ANA_BASE + 0x34)
-/** LP_ANA_BOD_MODE0_LP_INT_ST : RO; bitpos: [31]; default: 0;
+#define LP_ANALOG_PERI_LP_INT_ST_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x34)
+/** LP_ANALOG_PERI_BOD_MODE0_LP_INT_ST : RO; bitpos: [31]; default: 0;
  *  need_des
  */
-#define LP_ANA_BOD_MODE0_LP_INT_ST    (BIT(31))
-#define LP_ANA_BOD_MODE0_LP_INT_ST_M  (LP_ANA_BOD_MODE0_LP_INT_ST_V << LP_ANA_BOD_MODE0_LP_INT_ST_S)
-#define LP_ANA_BOD_MODE0_LP_INT_ST_V  0x00000001U
-#define LP_ANA_BOD_MODE0_LP_INT_ST_S  31
+#define LP_ANALOG_PERI_BOD_MODE0_LP_INT_ST    (BIT(31))
+#define LP_ANALOG_PERI_BOD_MODE0_LP_INT_ST_M  (LP_ANALOG_PERI_BOD_MODE0_LP_INT_ST_V << LP_ANALOG_PERI_BOD_MODE0_LP_INT_ST_S)
+#define LP_ANALOG_PERI_BOD_MODE0_LP_INT_ST_V  0x00000001U
+#define LP_ANALOG_PERI_BOD_MODE0_LP_INT_ST_S  31
 
-/** LP_ANA_LP_INT_ENA_REG register
+/** LP_ANALOG_PERI_LP_INT_ENA_REG register
  *  need_des
  */
-#define LP_ANA_LP_INT_ENA_REG (DR_REG_LP_ANA_BASE + 0x38)
-/** LP_ANA_BOD_MODE0_LP_INT_ENA : R/W; bitpos: [31]; default: 0;
+#define LP_ANALOG_PERI_LP_INT_ENA_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x38)
+/** LP_ANALOG_PERI_BOD_MODE0_LP_INT_ENA : R/W; bitpos: [31]; default: 0;
  *  need_des
  */
-#define LP_ANA_BOD_MODE0_LP_INT_ENA    (BIT(31))
-#define LP_ANA_BOD_MODE0_LP_INT_ENA_M  (LP_ANA_BOD_MODE0_LP_INT_ENA_V << LP_ANA_BOD_MODE0_LP_INT_ENA_S)
-#define LP_ANA_BOD_MODE0_LP_INT_ENA_V  0x00000001U
-#define LP_ANA_BOD_MODE0_LP_INT_ENA_S  31
+#define LP_ANALOG_PERI_BOD_MODE0_LP_INT_ENA    (BIT(31))
+#define LP_ANALOG_PERI_BOD_MODE0_LP_INT_ENA_M  (LP_ANALOG_PERI_BOD_MODE0_LP_INT_ENA_V << LP_ANALOG_PERI_BOD_MODE0_LP_INT_ENA_S)
+#define LP_ANALOG_PERI_BOD_MODE0_LP_INT_ENA_V  0x00000001U
+#define LP_ANALOG_PERI_BOD_MODE0_LP_INT_ENA_S  31
 
-/** LP_ANA_LP_INT_CLR_REG register
+/** LP_ANALOG_PERI_LP_INT_CLR_REG register
  *  need_des
  */
-#define LP_ANA_LP_INT_CLR_REG (DR_REG_LP_ANA_BASE + 0x3c)
-/** LP_ANA_BOD_MODE0_LP_INT_CLR : WT; bitpos: [31]; default: 0;
+#define LP_ANALOG_PERI_LP_INT_CLR_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x3c)
+/** LP_ANALOG_PERI_BOD_MODE0_LP_INT_CLR : WT; bitpos: [31]; default: 0;
  *  need_des
  */
-#define LP_ANA_BOD_MODE0_LP_INT_CLR    (BIT(31))
-#define LP_ANA_BOD_MODE0_LP_INT_CLR_M  (LP_ANA_BOD_MODE0_LP_INT_CLR_V << LP_ANA_BOD_MODE0_LP_INT_CLR_S)
-#define LP_ANA_BOD_MODE0_LP_INT_CLR_V  0x00000001U
-#define LP_ANA_BOD_MODE0_LP_INT_CLR_S  31
+#define LP_ANALOG_PERI_BOD_MODE0_LP_INT_CLR    (BIT(31))
+#define LP_ANALOG_PERI_BOD_MODE0_LP_INT_CLR_M  (LP_ANALOG_PERI_BOD_MODE0_LP_INT_CLR_V << LP_ANALOG_PERI_BOD_MODE0_LP_INT_CLR_S)
+#define LP_ANALOG_PERI_BOD_MODE0_LP_INT_CLR_V  0x00000001U
+#define LP_ANALOG_PERI_BOD_MODE0_LP_INT_CLR_S  31
 
-/** LP_ANA_TOUCH_APPROACH_WORK_MEAS_NUM_REG register
+/** LP_ANALOG_PERI_TOUCH_APPROACH_WORK_MEAS_NUM_REG register
  *  need_des
  */
-#define LP_ANA_TOUCH_APPROACH_WORK_MEAS_NUM_REG (DR_REG_LP_ANA_BASE + 0xfc)
-/** LP_ANA_TOUCH_APPROACH_MEAS_NUM2 : R/W; bitpos: [9:0]; default: 100;
+#define LP_ANALOG_PERI_TOUCH_APPROACH_WORK_MEAS_NUM_REG (DR_REG_LP_ANALOG_PERI_BASE + 0xfc)
+/** LP_ANALOG_PERI_TOUCH_APPROACH_MEAS_NUM2 : R/W; bitpos: [9:0]; default: 100;
  *  need_des
  */
-#define LP_ANA_TOUCH_APPROACH_MEAS_NUM2    0x000003FFU
-#define LP_ANA_TOUCH_APPROACH_MEAS_NUM2_M  (LP_ANA_TOUCH_APPROACH_MEAS_NUM2_V << LP_ANA_TOUCH_APPROACH_MEAS_NUM2_S)
-#define LP_ANA_TOUCH_APPROACH_MEAS_NUM2_V  0x000003FFU
-#define LP_ANA_TOUCH_APPROACH_MEAS_NUM2_S  0
-/** LP_ANA_TOUCH_APPROACH_MEAS_NUM1 : R/W; bitpos: [19:10]; default: 100;
+#define LP_ANALOG_PERI_TOUCH_APPROACH_MEAS_NUM2    0x000003FFU
+#define LP_ANALOG_PERI_TOUCH_APPROACH_MEAS_NUM2_M  (LP_ANALOG_PERI_TOUCH_APPROACH_MEAS_NUM2_V << LP_ANALOG_PERI_TOUCH_APPROACH_MEAS_NUM2_S)
+#define LP_ANALOG_PERI_TOUCH_APPROACH_MEAS_NUM2_V  0x000003FFU
+#define LP_ANALOG_PERI_TOUCH_APPROACH_MEAS_NUM2_S  0
+/** LP_ANALOG_PERI_TOUCH_APPROACH_MEAS_NUM1 : R/W; bitpos: [19:10]; default: 100;
  *  need_des
  */
-#define LP_ANA_TOUCH_APPROACH_MEAS_NUM1    0x000003FFU
-#define LP_ANA_TOUCH_APPROACH_MEAS_NUM1_M  (LP_ANA_TOUCH_APPROACH_MEAS_NUM1_V << LP_ANA_TOUCH_APPROACH_MEAS_NUM1_S)
-#define LP_ANA_TOUCH_APPROACH_MEAS_NUM1_V  0x000003FFU
-#define LP_ANA_TOUCH_APPROACH_MEAS_NUM1_S  10
-/** LP_ANA_TOUCH_APPROACH_MEAS_NUM0 : R/W; bitpos: [29:20]; default: 100;
+#define LP_ANALOG_PERI_TOUCH_APPROACH_MEAS_NUM1    0x000003FFU
+#define LP_ANALOG_PERI_TOUCH_APPROACH_MEAS_NUM1_M  (LP_ANALOG_PERI_TOUCH_APPROACH_MEAS_NUM1_V << LP_ANALOG_PERI_TOUCH_APPROACH_MEAS_NUM1_S)
+#define LP_ANALOG_PERI_TOUCH_APPROACH_MEAS_NUM1_V  0x000003FFU
+#define LP_ANALOG_PERI_TOUCH_APPROACH_MEAS_NUM1_S  10
+/** LP_ANALOG_PERI_TOUCH_APPROACH_MEAS_NUM0 : R/W; bitpos: [29:20]; default: 100;
  *  need_des
  */
-#define LP_ANA_TOUCH_APPROACH_MEAS_NUM0    0x000003FFU
-#define LP_ANA_TOUCH_APPROACH_MEAS_NUM0_M  (LP_ANA_TOUCH_APPROACH_MEAS_NUM0_V << LP_ANA_TOUCH_APPROACH_MEAS_NUM0_S)
-#define LP_ANA_TOUCH_APPROACH_MEAS_NUM0_V  0x000003FFU
-#define LP_ANA_TOUCH_APPROACH_MEAS_NUM0_S  20
+#define LP_ANALOG_PERI_TOUCH_APPROACH_MEAS_NUM0    0x000003FFU
+#define LP_ANALOG_PERI_TOUCH_APPROACH_MEAS_NUM0_M  (LP_ANALOG_PERI_TOUCH_APPROACH_MEAS_NUM0_V << LP_ANALOG_PERI_TOUCH_APPROACH_MEAS_NUM0_S)
+#define LP_ANALOG_PERI_TOUCH_APPROACH_MEAS_NUM0_V  0x000003FFU
+#define LP_ANALOG_PERI_TOUCH_APPROACH_MEAS_NUM0_S  20
 
-/** LP_ANA_TOUCH_SCAN_CTRL1_REG register
+/** LP_ANALOG_PERI_TOUCH_SCAN_CTRL1_REG register
  *  need_des
  */
-#define LP_ANA_TOUCH_SCAN_CTRL1_REG (DR_REG_LP_ANA_BASE + 0x100)
-/** LP_ANA_TOUCH_SHIELD_PAD_EN : R/W; bitpos: [0]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_SCAN_CTRL1_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x100)
+/** LP_ANALOG_PERI_TOUCH_SHIELD_PAD_EN : R/W; bitpos: [0]; default: 0;
  *  need_des
  */
-#define LP_ANA_TOUCH_SHIELD_PAD_EN    (BIT(0))
-#define LP_ANA_TOUCH_SHIELD_PAD_EN_M  (LP_ANA_TOUCH_SHIELD_PAD_EN_V << LP_ANA_TOUCH_SHIELD_PAD_EN_S)
-#define LP_ANA_TOUCH_SHIELD_PAD_EN_V  0x00000001U
-#define LP_ANA_TOUCH_SHIELD_PAD_EN_S  0
-/** LP_ANA_TOUCH_INACTIVE_CONNECTION : R/W; bitpos: [1]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_SHIELD_PAD_EN    (BIT(0))
+#define LP_ANALOG_PERI_TOUCH_SHIELD_PAD_EN_M  (LP_ANALOG_PERI_TOUCH_SHIELD_PAD_EN_V << LP_ANALOG_PERI_TOUCH_SHIELD_PAD_EN_S)
+#define LP_ANALOG_PERI_TOUCH_SHIELD_PAD_EN_V  0x00000001U
+#define LP_ANALOG_PERI_TOUCH_SHIELD_PAD_EN_S  0
+/** LP_ANALOG_PERI_TOUCH_INACTIVE_CONNECTION : R/W; bitpos: [1]; default: 0;
  *  need_des
  */
-#define LP_ANA_TOUCH_INACTIVE_CONNECTION    (BIT(1))
-#define LP_ANA_TOUCH_INACTIVE_CONNECTION_M  (LP_ANA_TOUCH_INACTIVE_CONNECTION_V << LP_ANA_TOUCH_INACTIVE_CONNECTION_S)
-#define LP_ANA_TOUCH_INACTIVE_CONNECTION_V  0x00000001U
-#define LP_ANA_TOUCH_INACTIVE_CONNECTION_S  1
-/** LP_ANA_TOUCH_SCAN_PAD_MAP : R/W; bitpos: [16:2]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_INACTIVE_CONNECTION    (BIT(1))
+#define LP_ANALOG_PERI_TOUCH_INACTIVE_CONNECTION_M  (LP_ANALOG_PERI_TOUCH_INACTIVE_CONNECTION_V << LP_ANALOG_PERI_TOUCH_INACTIVE_CONNECTION_S)
+#define LP_ANALOG_PERI_TOUCH_INACTIVE_CONNECTION_V  0x00000001U
+#define LP_ANALOG_PERI_TOUCH_INACTIVE_CONNECTION_S  1
+/** LP_ANALOG_PERI_TOUCH_SCAN_PAD_MAP : R/W; bitpos: [16:2]; default: 0;
  *  need_des
  */
-#define LP_ANA_TOUCH_SCAN_PAD_MAP    0x00007FFFU
-#define LP_ANA_TOUCH_SCAN_PAD_MAP_M  (LP_ANA_TOUCH_SCAN_PAD_MAP_V << LP_ANA_TOUCH_SCAN_PAD_MAP_S)
-#define LP_ANA_TOUCH_SCAN_PAD_MAP_V  0x00007FFFU
-#define LP_ANA_TOUCH_SCAN_PAD_MAP_S  2
-/** LP_ANA_TOUCH_XPD_WAIT : R/W; bitpos: [31:17]; default: 4;
+#define LP_ANALOG_PERI_TOUCH_SCAN_PAD_MAP    0x00007FFFU
+#define LP_ANALOG_PERI_TOUCH_SCAN_PAD_MAP_M  (LP_ANALOG_PERI_TOUCH_SCAN_PAD_MAP_V << LP_ANALOG_PERI_TOUCH_SCAN_PAD_MAP_S)
+#define LP_ANALOG_PERI_TOUCH_SCAN_PAD_MAP_V  0x00007FFFU
+#define LP_ANALOG_PERI_TOUCH_SCAN_PAD_MAP_S  2
+/** LP_ANALOG_PERI_TOUCH_XPD_WAIT : R/W; bitpos: [31:17]; default: 4;
  *  need_des
  */
-#define LP_ANA_TOUCH_XPD_WAIT    0x00007FFFU
-#define LP_ANA_TOUCH_XPD_WAIT_M  (LP_ANA_TOUCH_XPD_WAIT_V << LP_ANA_TOUCH_XPD_WAIT_S)
-#define LP_ANA_TOUCH_XPD_WAIT_V  0x00007FFFU
-#define LP_ANA_TOUCH_XPD_WAIT_S  17
+#define LP_ANALOG_PERI_TOUCH_XPD_WAIT    0x00007FFFU
+#define LP_ANALOG_PERI_TOUCH_XPD_WAIT_M  (LP_ANALOG_PERI_TOUCH_XPD_WAIT_V << LP_ANALOG_PERI_TOUCH_XPD_WAIT_S)
+#define LP_ANALOG_PERI_TOUCH_XPD_WAIT_V  0x00007FFFU
+#define LP_ANALOG_PERI_TOUCH_XPD_WAIT_S  17
 
-/** LP_ANA_TOUCH_SCAN_CTRL2_REG register
+/** LP_ANALOG_PERI_TOUCH_SCAN_CTRL2_REG register
  *  need_des
  */
-#define LP_ANA_TOUCH_SCAN_CTRL2_REG (DR_REG_LP_ANA_BASE + 0x104)
-/** LP_ANA_TOUCH_TIMEOUT_NUM : R/W; bitpos: [21:6]; default: 65535;
+#define LP_ANALOG_PERI_TOUCH_SCAN_CTRL2_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x104)
+/** LP_ANALOG_PERI_TOUCH_TIMEOUT_NUM : R/W; bitpos: [21:6]; default: 65535;
  *  need_des
  */
-#define LP_ANA_TOUCH_TIMEOUT_NUM    0x0000FFFFU
-#define LP_ANA_TOUCH_TIMEOUT_NUM_M  (LP_ANA_TOUCH_TIMEOUT_NUM_V << LP_ANA_TOUCH_TIMEOUT_NUM_S)
-#define LP_ANA_TOUCH_TIMEOUT_NUM_V  0x0000FFFFU
-#define LP_ANA_TOUCH_TIMEOUT_NUM_S  6
-/** LP_ANA_TOUCH_TIMEOUT_EN : R/W; bitpos: [22]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_TIMEOUT_NUM    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_TIMEOUT_NUM_M  (LP_ANALOG_PERI_TOUCH_TIMEOUT_NUM_V << LP_ANALOG_PERI_TOUCH_TIMEOUT_NUM_S)
+#define LP_ANALOG_PERI_TOUCH_TIMEOUT_NUM_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_TIMEOUT_NUM_S  6
+/** LP_ANALOG_PERI_TOUCH_TIMEOUT_EN : R/W; bitpos: [22]; default: 0;
  *  need_des
  */
-#define LP_ANA_TOUCH_TIMEOUT_EN    (BIT(22))
-#define LP_ANA_TOUCH_TIMEOUT_EN_M  (LP_ANA_TOUCH_TIMEOUT_EN_V << LP_ANA_TOUCH_TIMEOUT_EN_S)
-#define LP_ANA_TOUCH_TIMEOUT_EN_V  0x00000001U
-#define LP_ANA_TOUCH_TIMEOUT_EN_S  22
-/** LP_ANA_TOUCH_OUT_RING : R/W; bitpos: [26:23]; default: 15;
+#define LP_ANALOG_PERI_TOUCH_TIMEOUT_EN    (BIT(22))
+#define LP_ANALOG_PERI_TOUCH_TIMEOUT_EN_M  (LP_ANALOG_PERI_TOUCH_TIMEOUT_EN_V << LP_ANALOG_PERI_TOUCH_TIMEOUT_EN_S)
+#define LP_ANALOG_PERI_TOUCH_TIMEOUT_EN_V  0x00000001U
+#define LP_ANALOG_PERI_TOUCH_TIMEOUT_EN_S  22
+/** LP_ANALOG_PERI_TOUCH_OUT_RING : R/W; bitpos: [26:23]; default: 15;
  *  need_des
  */
-#define LP_ANA_TOUCH_OUT_RING    0x0000000FU
-#define LP_ANA_TOUCH_OUT_RING_M  (LP_ANA_TOUCH_OUT_RING_V << LP_ANA_TOUCH_OUT_RING_S)
-#define LP_ANA_TOUCH_OUT_RING_V  0x0000000FU
-#define LP_ANA_TOUCH_OUT_RING_S  23
-/** LP_ANA_FREQ_SCAN_EN : R/W; bitpos: [27]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_OUT_RING    0x0000000FU
+#define LP_ANALOG_PERI_TOUCH_OUT_RING_M  (LP_ANALOG_PERI_TOUCH_OUT_RING_V << LP_ANALOG_PERI_TOUCH_OUT_RING_S)
+#define LP_ANALOG_PERI_TOUCH_OUT_RING_V  0x0000000FU
+#define LP_ANALOG_PERI_TOUCH_OUT_RING_S  23
+/** LP_ANALOG_PERI_FREQ_SCAN_EN : R/W; bitpos: [27]; default: 0;
  *  need_des
  */
-#define LP_ANA_FREQ_SCAN_EN    (BIT(27))
-#define LP_ANA_FREQ_SCAN_EN_M  (LP_ANA_FREQ_SCAN_EN_V << LP_ANA_FREQ_SCAN_EN_S)
-#define LP_ANA_FREQ_SCAN_EN_V  0x00000001U
-#define LP_ANA_FREQ_SCAN_EN_S  27
-/** LP_ANA_FREQ_SCAN_CNT_LIMIT : R/W; bitpos: [29:28]; default: 3;
+#define LP_ANALOG_PERI_FREQ_SCAN_EN    (BIT(27))
+#define LP_ANALOG_PERI_FREQ_SCAN_EN_M  (LP_ANALOG_PERI_FREQ_SCAN_EN_V << LP_ANALOG_PERI_FREQ_SCAN_EN_S)
+#define LP_ANALOG_PERI_FREQ_SCAN_EN_V  0x00000001U
+#define LP_ANALOG_PERI_FREQ_SCAN_EN_S  27
+/** LP_ANALOG_PERI_FREQ_SCAN_CNT_LIMIT : R/W; bitpos: [29:28]; default: 3;
  *  need_des
  */
-#define LP_ANA_FREQ_SCAN_CNT_LIMIT    0x00000003U
-#define LP_ANA_FREQ_SCAN_CNT_LIMIT_M  (LP_ANA_FREQ_SCAN_CNT_LIMIT_V << LP_ANA_FREQ_SCAN_CNT_LIMIT_S)
-#define LP_ANA_FREQ_SCAN_CNT_LIMIT_V  0x00000003U
-#define LP_ANA_FREQ_SCAN_CNT_LIMIT_S  28
+#define LP_ANALOG_PERI_FREQ_SCAN_CNT_LIMIT    0x00000003U
+#define LP_ANALOG_PERI_FREQ_SCAN_CNT_LIMIT_M  (LP_ANALOG_PERI_FREQ_SCAN_CNT_LIMIT_V << LP_ANALOG_PERI_FREQ_SCAN_CNT_LIMIT_S)
+#define LP_ANALOG_PERI_FREQ_SCAN_CNT_LIMIT_V  0x00000003U
+#define LP_ANALOG_PERI_FREQ_SCAN_CNT_LIMIT_S  28
 
-/** LP_ANA_TOUCH_WORK_REG register
+/** LP_ANALOG_PERI_TOUCH_WORK_REG register
  *  need_des
  */
-#define LP_ANA_TOUCH_WORK_REG (DR_REG_LP_ANA_BASE + 0x108)
-/** LP_ANA_DIV_NUM2 : R/W; bitpos: [18:16]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_WORK_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x108)
+/** LP_ANALOG_PERI_DIV_NUM2 : R/W; bitpos: [18:16]; default: 0;
  *  need_des
  */
-#define LP_ANA_DIV_NUM2    0x00000007U
-#define LP_ANA_DIV_NUM2_M  (LP_ANA_DIV_NUM2_V << LP_ANA_DIV_NUM2_S)
-#define LP_ANA_DIV_NUM2_V  0x00000007U
-#define LP_ANA_DIV_NUM2_S  16
-/** LP_ANA_DIV_NUM1 : R/W; bitpos: [21:19]; default: 0;
+#define LP_ANALOG_PERI_DIV_NUM2    0x00000007U
+#define LP_ANALOG_PERI_DIV_NUM2_M  (LP_ANALOG_PERI_DIV_NUM2_V << LP_ANALOG_PERI_DIV_NUM2_S)
+#define LP_ANALOG_PERI_DIV_NUM2_V  0x00000007U
+#define LP_ANALOG_PERI_DIV_NUM2_S  16
+/** LP_ANALOG_PERI_DIV_NUM1 : R/W; bitpos: [21:19]; default: 0;
  *  need_des
  */
-#define LP_ANA_DIV_NUM1    0x00000007U
-#define LP_ANA_DIV_NUM1_M  (LP_ANA_DIV_NUM1_V << LP_ANA_DIV_NUM1_S)
-#define LP_ANA_DIV_NUM1_V  0x00000007U
-#define LP_ANA_DIV_NUM1_S  19
-/** LP_ANA_DIV_NUM0 : R/W; bitpos: [24:22]; default: 0;
+#define LP_ANALOG_PERI_DIV_NUM1    0x00000007U
+#define LP_ANALOG_PERI_DIV_NUM1_M  (LP_ANALOG_PERI_DIV_NUM1_V << LP_ANALOG_PERI_DIV_NUM1_S)
+#define LP_ANALOG_PERI_DIV_NUM1_V  0x00000007U
+#define LP_ANALOG_PERI_DIV_NUM1_S  19
+/** LP_ANALOG_PERI_DIV_NUM0 : R/W; bitpos: [24:22]; default: 0;
  *  need_des
  */
-#define LP_ANA_DIV_NUM0    0x00000007U
-#define LP_ANA_DIV_NUM0_M  (LP_ANA_DIV_NUM0_V << LP_ANA_DIV_NUM0_S)
-#define LP_ANA_DIV_NUM0_V  0x00000007U
-#define LP_ANA_DIV_NUM0_S  22
-/** LP_ANA_TOUCH_OUT_SEL : R/W; bitpos: [25]; default: 0;
+#define LP_ANALOG_PERI_DIV_NUM0    0x00000007U
+#define LP_ANALOG_PERI_DIV_NUM0_M  (LP_ANALOG_PERI_DIV_NUM0_V << LP_ANALOG_PERI_DIV_NUM0_S)
+#define LP_ANALOG_PERI_DIV_NUM0_V  0x00000007U
+#define LP_ANALOG_PERI_DIV_NUM0_S  22
+/** LP_ANALOG_PERI_TOUCH_OUT_SEL : R/W; bitpos: [25]; default: 0;
  *  need_des
  */
-#define LP_ANA_TOUCH_OUT_SEL    (BIT(25))
-#define LP_ANA_TOUCH_OUT_SEL_M  (LP_ANA_TOUCH_OUT_SEL_V << LP_ANA_TOUCH_OUT_SEL_S)
-#define LP_ANA_TOUCH_OUT_SEL_V  0x00000001U
-#define LP_ANA_TOUCH_OUT_SEL_S  25
-/** LP_ANA_TOUCH_OUT_RESET : WT; bitpos: [26]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_OUT_SEL    (BIT(25))
+#define LP_ANALOG_PERI_TOUCH_OUT_SEL_M  (LP_ANALOG_PERI_TOUCH_OUT_SEL_V << LP_ANALOG_PERI_TOUCH_OUT_SEL_S)
+#define LP_ANALOG_PERI_TOUCH_OUT_SEL_V  0x00000001U
+#define LP_ANALOG_PERI_TOUCH_OUT_SEL_S  25
+/** LP_ANALOG_PERI_TOUCH_OUT_RESET : WT; bitpos: [26]; default: 0;
  *  need_des
  */
-#define LP_ANA_TOUCH_OUT_RESET    (BIT(26))
-#define LP_ANA_TOUCH_OUT_RESET_M  (LP_ANA_TOUCH_OUT_RESET_V << LP_ANA_TOUCH_OUT_RESET_S)
-#define LP_ANA_TOUCH_OUT_RESET_V  0x00000001U
-#define LP_ANA_TOUCH_OUT_RESET_S  26
-/** LP_ANA_TOUCH_OUT_GATE : R/W; bitpos: [27]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_OUT_RESET    (BIT(26))
+#define LP_ANALOG_PERI_TOUCH_OUT_RESET_M  (LP_ANALOG_PERI_TOUCH_OUT_RESET_V << LP_ANALOG_PERI_TOUCH_OUT_RESET_S)
+#define LP_ANALOG_PERI_TOUCH_OUT_RESET_V  0x00000001U
+#define LP_ANALOG_PERI_TOUCH_OUT_RESET_S  26
+/** LP_ANALOG_PERI_TOUCH_OUT_GATE : R/W; bitpos: [27]; default: 0;
  *  need_des
  */
-#define LP_ANA_TOUCH_OUT_GATE    (BIT(27))
-#define LP_ANA_TOUCH_OUT_GATE_M  (LP_ANA_TOUCH_OUT_GATE_V << LP_ANA_TOUCH_OUT_GATE_S)
-#define LP_ANA_TOUCH_OUT_GATE_V  0x00000001U
-#define LP_ANA_TOUCH_OUT_GATE_S  27
+#define LP_ANALOG_PERI_TOUCH_OUT_GATE    (BIT(27))
+#define LP_ANALOG_PERI_TOUCH_OUT_GATE_M  (LP_ANALOG_PERI_TOUCH_OUT_GATE_V << LP_ANALOG_PERI_TOUCH_OUT_GATE_S)
+#define LP_ANALOG_PERI_TOUCH_OUT_GATE_V  0x00000001U
+#define LP_ANALOG_PERI_TOUCH_OUT_GATE_S  27
 
-/** LP_ANA_TOUCH_WORK_MEAS_NUM_REG register
+/** LP_ANALOG_PERI_TOUCH_WORK_MEAS_NUM_REG register
  *  need_des
  */
-#define LP_ANA_TOUCH_WORK_MEAS_NUM_REG (DR_REG_LP_ANA_BASE + 0x10c)
-/** LP_ANA_TOUCH_MEAS_NUM2 : R/W; bitpos: [9:0]; default: 100;
+#define LP_ANALOG_PERI_TOUCH_WORK_MEAS_NUM_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x10c)
+/** LP_ANALOG_PERI_TOUCH_MEAS_NUM2 : R/W; bitpos: [9:0]; default: 100;
  *  need_des
  */
-#define LP_ANA_TOUCH_MEAS_NUM2    0x000003FFU
-#define LP_ANA_TOUCH_MEAS_NUM2_M  (LP_ANA_TOUCH_MEAS_NUM2_V << LP_ANA_TOUCH_MEAS_NUM2_S)
-#define LP_ANA_TOUCH_MEAS_NUM2_V  0x000003FFU
-#define LP_ANA_TOUCH_MEAS_NUM2_S  0
-/** LP_ANA_TOUCH_MEAS_NUM1 : R/W; bitpos: [19:10]; default: 100;
+#define LP_ANALOG_PERI_TOUCH_MEAS_NUM2    0x000003FFU
+#define LP_ANALOG_PERI_TOUCH_MEAS_NUM2_M  (LP_ANALOG_PERI_TOUCH_MEAS_NUM2_V << LP_ANALOG_PERI_TOUCH_MEAS_NUM2_S)
+#define LP_ANALOG_PERI_TOUCH_MEAS_NUM2_V  0x000003FFU
+#define LP_ANALOG_PERI_TOUCH_MEAS_NUM2_S  0
+/** LP_ANALOG_PERI_TOUCH_MEAS_NUM1 : R/W; bitpos: [19:10]; default: 100;
  *  need_des
  */
-#define LP_ANA_TOUCH_MEAS_NUM1    0x000003FFU
-#define LP_ANA_TOUCH_MEAS_NUM1_M  (LP_ANA_TOUCH_MEAS_NUM1_V << LP_ANA_TOUCH_MEAS_NUM1_S)
-#define LP_ANA_TOUCH_MEAS_NUM1_V  0x000003FFU
-#define LP_ANA_TOUCH_MEAS_NUM1_S  10
-/** LP_ANA_TOUCH_MEAS_NUM0 : R/W; bitpos: [29:20]; default: 100;
+#define LP_ANALOG_PERI_TOUCH_MEAS_NUM1    0x000003FFU
+#define LP_ANALOG_PERI_TOUCH_MEAS_NUM1_M  (LP_ANALOG_PERI_TOUCH_MEAS_NUM1_V << LP_ANALOG_PERI_TOUCH_MEAS_NUM1_S)
+#define LP_ANALOG_PERI_TOUCH_MEAS_NUM1_V  0x000003FFU
+#define LP_ANALOG_PERI_TOUCH_MEAS_NUM1_S  10
+/** LP_ANALOG_PERI_TOUCH_MEAS_NUM0 : R/W; bitpos: [29:20]; default: 100;
  *  need_des
  */
-#define LP_ANA_TOUCH_MEAS_NUM0    0x000003FFU
-#define LP_ANA_TOUCH_MEAS_NUM0_M  (LP_ANA_TOUCH_MEAS_NUM0_V << LP_ANA_TOUCH_MEAS_NUM0_S)
-#define LP_ANA_TOUCH_MEAS_NUM0_V  0x000003FFU
-#define LP_ANA_TOUCH_MEAS_NUM0_S  20
+#define LP_ANALOG_PERI_TOUCH_MEAS_NUM0    0x000003FFU
+#define LP_ANALOG_PERI_TOUCH_MEAS_NUM0_M  (LP_ANALOG_PERI_TOUCH_MEAS_NUM0_V << LP_ANALOG_PERI_TOUCH_MEAS_NUM0_S)
+#define LP_ANALOG_PERI_TOUCH_MEAS_NUM0_V  0x000003FFU
+#define LP_ANALOG_PERI_TOUCH_MEAS_NUM0_S  20
 
-/** LP_ANA_TOUCH_FILTER1_REG register
+/** LP_ANALOG_PERI_TOUCH_FILTER1_REG register
  *  need_des
  */
-#define LP_ANA_TOUCH_FILTER1_REG (DR_REG_LP_ANA_BASE + 0x110)
-/** LP_ANA_TOUCH_NEG_NOISE_DISUPDATE_BASELINE_EN : R/W; bitpos: [0]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_FILTER1_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x110)
+/** LP_ANALOG_PERI_TOUCH_NEG_NOISE_DISUPDATE_BASELINE_EN : R/W; bitpos: [0]; default: 0;
  *  Reserved
  */
-#define LP_ANA_TOUCH_NEG_NOISE_DISUPDATE_BASELINE_EN    (BIT(0))
-#define LP_ANA_TOUCH_NEG_NOISE_DISUPDATE_BASELINE_EN_M  (LP_ANA_TOUCH_NEG_NOISE_DISUPDATE_BASELINE_EN_V << LP_ANA_TOUCH_NEG_NOISE_DISUPDATE_BASELINE_EN_S)
-#define LP_ANA_TOUCH_NEG_NOISE_DISUPDATE_BASELINE_EN_V  0x00000001U
-#define LP_ANA_TOUCH_NEG_NOISE_DISUPDATE_BASELINE_EN_S  0
-/** LP_ANA_TOUCH_HYSTERESIS : R/W; bitpos: [2:1]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_NEG_NOISE_DISUPDATE_BASELINE_EN    (BIT(0))
+#define LP_ANALOG_PERI_TOUCH_NEG_NOISE_DISUPDATE_BASELINE_EN_M  (LP_ANALOG_PERI_TOUCH_NEG_NOISE_DISUPDATE_BASELINE_EN_V << LP_ANALOG_PERI_TOUCH_NEG_NOISE_DISUPDATE_BASELINE_EN_S)
+#define LP_ANALOG_PERI_TOUCH_NEG_NOISE_DISUPDATE_BASELINE_EN_V  0x00000001U
+#define LP_ANALOG_PERI_TOUCH_NEG_NOISE_DISUPDATE_BASELINE_EN_S  0
+/** LP_ANALOG_PERI_TOUCH_HYSTERESIS : R/W; bitpos: [2:1]; default: 0;
  *  need_des
  */
-#define LP_ANA_TOUCH_HYSTERESIS    0x00000003U
-#define LP_ANA_TOUCH_HYSTERESIS_M  (LP_ANA_TOUCH_HYSTERESIS_V << LP_ANA_TOUCH_HYSTERESIS_S)
-#define LP_ANA_TOUCH_HYSTERESIS_V  0x00000003U
-#define LP_ANA_TOUCH_HYSTERESIS_S  1
-/** LP_ANA_TOUCH_NEG_NOISE_THRES : R/W; bitpos: [4:3]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_HYSTERESIS    0x00000003U
+#define LP_ANALOG_PERI_TOUCH_HYSTERESIS_M  (LP_ANALOG_PERI_TOUCH_HYSTERESIS_V << LP_ANALOG_PERI_TOUCH_HYSTERESIS_S)
+#define LP_ANALOG_PERI_TOUCH_HYSTERESIS_V  0x00000003U
+#define LP_ANALOG_PERI_TOUCH_HYSTERESIS_S  1
+/** LP_ANALOG_PERI_TOUCH_NEG_NOISE_THRES : R/W; bitpos: [4:3]; default: 0;
  *  need_des
  */
-#define LP_ANA_TOUCH_NEG_NOISE_THRES    0x00000003U
-#define LP_ANA_TOUCH_NEG_NOISE_THRES_M  (LP_ANA_TOUCH_NEG_NOISE_THRES_V << LP_ANA_TOUCH_NEG_NOISE_THRES_S)
-#define LP_ANA_TOUCH_NEG_NOISE_THRES_V  0x00000003U
-#define LP_ANA_TOUCH_NEG_NOISE_THRES_S  3
-/** LP_ANA_TOUCH_NOISE_THRES : R/W; bitpos: [6:5]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_NEG_NOISE_THRES    0x00000003U
+#define LP_ANALOG_PERI_TOUCH_NEG_NOISE_THRES_M  (LP_ANALOG_PERI_TOUCH_NEG_NOISE_THRES_V << LP_ANALOG_PERI_TOUCH_NEG_NOISE_THRES_S)
+#define LP_ANALOG_PERI_TOUCH_NEG_NOISE_THRES_V  0x00000003U
+#define LP_ANALOG_PERI_TOUCH_NEG_NOISE_THRES_S  3
+/** LP_ANALOG_PERI_TOUCH_NOISE_THRES : R/W; bitpos: [6:5]; default: 0;
  *  need_des
  */
-#define LP_ANA_TOUCH_NOISE_THRES    0x00000003U
-#define LP_ANA_TOUCH_NOISE_THRES_M  (LP_ANA_TOUCH_NOISE_THRES_V << LP_ANA_TOUCH_NOISE_THRES_S)
-#define LP_ANA_TOUCH_NOISE_THRES_V  0x00000003U
-#define LP_ANA_TOUCH_NOISE_THRES_S  5
-/** LP_ANA_TOUCH_SMOOTH_LVL : R/W; bitpos: [8:7]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_NOISE_THRES    0x00000003U
+#define LP_ANALOG_PERI_TOUCH_NOISE_THRES_M  (LP_ANALOG_PERI_TOUCH_NOISE_THRES_V << LP_ANALOG_PERI_TOUCH_NOISE_THRES_S)
+#define LP_ANALOG_PERI_TOUCH_NOISE_THRES_V  0x00000003U
+#define LP_ANALOG_PERI_TOUCH_NOISE_THRES_S  5
+/** LP_ANALOG_PERI_TOUCH_SMOOTH_LVL : R/W; bitpos: [8:7]; default: 0;
  *  need_des
  */
-#define LP_ANA_TOUCH_SMOOTH_LVL    0x00000003U
-#define LP_ANA_TOUCH_SMOOTH_LVL_M  (LP_ANA_TOUCH_SMOOTH_LVL_V << LP_ANA_TOUCH_SMOOTH_LVL_S)
-#define LP_ANA_TOUCH_SMOOTH_LVL_V  0x00000003U
-#define LP_ANA_TOUCH_SMOOTH_LVL_S  7
-/** LP_ANA_TOUCH_JITTER_STEP : R/W; bitpos: [12:9]; default: 1;
+#define LP_ANALOG_PERI_TOUCH_SMOOTH_LVL    0x00000003U
+#define LP_ANALOG_PERI_TOUCH_SMOOTH_LVL_M  (LP_ANALOG_PERI_TOUCH_SMOOTH_LVL_V << LP_ANALOG_PERI_TOUCH_SMOOTH_LVL_S)
+#define LP_ANALOG_PERI_TOUCH_SMOOTH_LVL_V  0x00000003U
+#define LP_ANALOG_PERI_TOUCH_SMOOTH_LVL_S  7
+/** LP_ANALOG_PERI_TOUCH_JITTER_STEP : R/W; bitpos: [12:9]; default: 1;
  *  need_des
  */
-#define LP_ANA_TOUCH_JITTER_STEP    0x0000000FU
-#define LP_ANA_TOUCH_JITTER_STEP_M  (LP_ANA_TOUCH_JITTER_STEP_V << LP_ANA_TOUCH_JITTER_STEP_S)
-#define LP_ANA_TOUCH_JITTER_STEP_V  0x0000000FU
-#define LP_ANA_TOUCH_JITTER_STEP_S  9
-/** LP_ANA_TOUCH_FILTER_MODE : R/W; bitpos: [15:13]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_JITTER_STEP    0x0000000FU
+#define LP_ANALOG_PERI_TOUCH_JITTER_STEP_M  (LP_ANALOG_PERI_TOUCH_JITTER_STEP_V << LP_ANALOG_PERI_TOUCH_JITTER_STEP_S)
+#define LP_ANALOG_PERI_TOUCH_JITTER_STEP_V  0x0000000FU
+#define LP_ANALOG_PERI_TOUCH_JITTER_STEP_S  9
+/** LP_ANALOG_PERI_TOUCH_FILTER_MODE : R/W; bitpos: [15:13]; default: 0;
  *  need_des
  */
-#define LP_ANA_TOUCH_FILTER_MODE    0x00000007U
-#define LP_ANA_TOUCH_FILTER_MODE_M  (LP_ANA_TOUCH_FILTER_MODE_V << LP_ANA_TOUCH_FILTER_MODE_S)
-#define LP_ANA_TOUCH_FILTER_MODE_V  0x00000007U
-#define LP_ANA_TOUCH_FILTER_MODE_S  13
-/** LP_ANA_TOUCH_FILTER_EN : R/W; bitpos: [16]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_FILTER_MODE    0x00000007U
+#define LP_ANALOG_PERI_TOUCH_FILTER_MODE_M  (LP_ANALOG_PERI_TOUCH_FILTER_MODE_V << LP_ANALOG_PERI_TOUCH_FILTER_MODE_S)
+#define LP_ANALOG_PERI_TOUCH_FILTER_MODE_V  0x00000007U
+#define LP_ANALOG_PERI_TOUCH_FILTER_MODE_S  13
+/** LP_ANALOG_PERI_TOUCH_FILTER_EN : R/W; bitpos: [16]; default: 0;
  *  need_des
  */
-#define LP_ANA_TOUCH_FILTER_EN    (BIT(16))
-#define LP_ANA_TOUCH_FILTER_EN_M  (LP_ANA_TOUCH_FILTER_EN_V << LP_ANA_TOUCH_FILTER_EN_S)
-#define LP_ANA_TOUCH_FILTER_EN_V  0x00000001U
-#define LP_ANA_TOUCH_FILTER_EN_S  16
-/** LP_ANA_TOUCH_NEG_NOISE_LIMIT : R/W; bitpos: [20:17]; default: 5;
+#define LP_ANALOG_PERI_TOUCH_FILTER_EN    (BIT(16))
+#define LP_ANALOG_PERI_TOUCH_FILTER_EN_M  (LP_ANALOG_PERI_TOUCH_FILTER_EN_V << LP_ANALOG_PERI_TOUCH_FILTER_EN_S)
+#define LP_ANALOG_PERI_TOUCH_FILTER_EN_V  0x00000001U
+#define LP_ANALOG_PERI_TOUCH_FILTER_EN_S  16
+/** LP_ANALOG_PERI_TOUCH_NEG_NOISE_LIMIT : R/W; bitpos: [20:17]; default: 5;
  *  need_des
  */
-#define LP_ANA_TOUCH_NEG_NOISE_LIMIT    0x0000000FU
-#define LP_ANA_TOUCH_NEG_NOISE_LIMIT_M  (LP_ANA_TOUCH_NEG_NOISE_LIMIT_V << LP_ANA_TOUCH_NEG_NOISE_LIMIT_S)
-#define LP_ANA_TOUCH_NEG_NOISE_LIMIT_V  0x0000000FU
-#define LP_ANA_TOUCH_NEG_NOISE_LIMIT_S  17
-/** LP_ANA_TOUCH_APPROACH_LIMIT : R/W; bitpos: [28:21]; default: 80;
+#define LP_ANALOG_PERI_TOUCH_NEG_NOISE_LIMIT    0x0000000FU
+#define LP_ANALOG_PERI_TOUCH_NEG_NOISE_LIMIT_M  (LP_ANALOG_PERI_TOUCH_NEG_NOISE_LIMIT_V << LP_ANALOG_PERI_TOUCH_NEG_NOISE_LIMIT_S)
+#define LP_ANALOG_PERI_TOUCH_NEG_NOISE_LIMIT_V  0x0000000FU
+#define LP_ANALOG_PERI_TOUCH_NEG_NOISE_LIMIT_S  17
+/** LP_ANALOG_PERI_TOUCH_APPROACH_LIMIT : R/W; bitpos: [28:21]; default: 80;
  *  need_des
  */
-#define LP_ANA_TOUCH_APPROACH_LIMIT    0x000000FFU
-#define LP_ANA_TOUCH_APPROACH_LIMIT_M  (LP_ANA_TOUCH_APPROACH_LIMIT_V << LP_ANA_TOUCH_APPROACH_LIMIT_S)
-#define LP_ANA_TOUCH_APPROACH_LIMIT_V  0x000000FFU
-#define LP_ANA_TOUCH_APPROACH_LIMIT_S  21
-/** LP_ANA_TOUCH_DEBOUNCE_LIMIT : R/W; bitpos: [31:29]; default: 3;
+#define LP_ANALOG_PERI_TOUCH_APPROACH_LIMIT    0x000000FFU
+#define LP_ANALOG_PERI_TOUCH_APPROACH_LIMIT_M  (LP_ANALOG_PERI_TOUCH_APPROACH_LIMIT_V << LP_ANALOG_PERI_TOUCH_APPROACH_LIMIT_S)
+#define LP_ANALOG_PERI_TOUCH_APPROACH_LIMIT_V  0x000000FFU
+#define LP_ANALOG_PERI_TOUCH_APPROACH_LIMIT_S  21
+/** LP_ANALOG_PERI_TOUCH_DEBOUNCE_LIMIT : R/W; bitpos: [31:29]; default: 3;
  *  need_des
  */
-#define LP_ANA_TOUCH_DEBOUNCE_LIMIT    0x00000007U
-#define LP_ANA_TOUCH_DEBOUNCE_LIMIT_M  (LP_ANA_TOUCH_DEBOUNCE_LIMIT_V << LP_ANA_TOUCH_DEBOUNCE_LIMIT_S)
-#define LP_ANA_TOUCH_DEBOUNCE_LIMIT_V  0x00000007U
-#define LP_ANA_TOUCH_DEBOUNCE_LIMIT_S  29
+#define LP_ANALOG_PERI_TOUCH_DEBOUNCE_LIMIT    0x00000007U
+#define LP_ANALOG_PERI_TOUCH_DEBOUNCE_LIMIT_M  (LP_ANALOG_PERI_TOUCH_DEBOUNCE_LIMIT_V << LP_ANALOG_PERI_TOUCH_DEBOUNCE_LIMIT_S)
+#define LP_ANALOG_PERI_TOUCH_DEBOUNCE_LIMIT_V  0x00000007U
+#define LP_ANALOG_PERI_TOUCH_DEBOUNCE_LIMIT_S  29
 
-/** LP_ANA_TOUCH_FILTER2_REG register
+/** LP_ANALOG_PERI_TOUCH_FILTER2_REG register
  *  need_des
  */
-#define LP_ANA_TOUCH_FILTER2_REG (DR_REG_LP_ANA_BASE + 0x114)
-/** LP_ANA_TOUCH_OUTEN : R/W; bitpos: [29:15]; default: 16383;
+#define LP_ANALOG_PERI_TOUCH_FILTER2_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x114)
+/** LP_ANALOG_PERI_TOUCH_OUTEN : R/W; bitpos: [29:15]; default: 16383;
  *  need_des
  */
-#define LP_ANA_TOUCH_OUTEN    0x00007FFFU
-#define LP_ANA_TOUCH_OUTEN_M  (LP_ANA_TOUCH_OUTEN_V << LP_ANA_TOUCH_OUTEN_S)
-#define LP_ANA_TOUCH_OUTEN_V  0x00007FFFU
-#define LP_ANA_TOUCH_OUTEN_S  15
-/** LP_ANA_TOUCH_BYPASS_NOISE_THRES : R/W; bitpos: [30]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_OUTEN    0x00007FFFU
+#define LP_ANALOG_PERI_TOUCH_OUTEN_M  (LP_ANALOG_PERI_TOUCH_OUTEN_V << LP_ANALOG_PERI_TOUCH_OUTEN_S)
+#define LP_ANALOG_PERI_TOUCH_OUTEN_V  0x00007FFFU
+#define LP_ANALOG_PERI_TOUCH_OUTEN_S  15
+/** LP_ANALOG_PERI_TOUCH_BYPASS_NOISE_THRES : R/W; bitpos: [30]; default: 0;
  *  need_des
  */
-#define LP_ANA_TOUCH_BYPASS_NOISE_THRES    (BIT(30))
-#define LP_ANA_TOUCH_BYPASS_NOISE_THRES_M  (LP_ANA_TOUCH_BYPASS_NOISE_THRES_V << LP_ANA_TOUCH_BYPASS_NOISE_THRES_S)
-#define LP_ANA_TOUCH_BYPASS_NOISE_THRES_V  0x00000001U
-#define LP_ANA_TOUCH_BYPASS_NOISE_THRES_S  30
-/** LP_ANA_TOUCH_BYPASS_NEG_NOISE_THRES : R/W; bitpos: [31]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_BYPASS_NOISE_THRES    (BIT(30))
+#define LP_ANALOG_PERI_TOUCH_BYPASS_NOISE_THRES_M  (LP_ANALOG_PERI_TOUCH_BYPASS_NOISE_THRES_V << LP_ANALOG_PERI_TOUCH_BYPASS_NOISE_THRES_S)
+#define LP_ANALOG_PERI_TOUCH_BYPASS_NOISE_THRES_V  0x00000001U
+#define LP_ANALOG_PERI_TOUCH_BYPASS_NOISE_THRES_S  30
+/** LP_ANALOG_PERI_TOUCH_BYPASS_NEG_NOISE_THRES : R/W; bitpos: [31]; default: 0;
  *  need_des
  */
-#define LP_ANA_TOUCH_BYPASS_NEG_NOISE_THRES    (BIT(31))
-#define LP_ANA_TOUCH_BYPASS_NEG_NOISE_THRES_M  (LP_ANA_TOUCH_BYPASS_NEG_NOISE_THRES_V << LP_ANA_TOUCH_BYPASS_NEG_NOISE_THRES_S)
-#define LP_ANA_TOUCH_BYPASS_NEG_NOISE_THRES_V  0x00000001U
-#define LP_ANA_TOUCH_BYPASS_NEG_NOISE_THRES_S  31
+#define LP_ANALOG_PERI_TOUCH_BYPASS_NEG_NOISE_THRES    (BIT(31))
+#define LP_ANALOG_PERI_TOUCH_BYPASS_NEG_NOISE_THRES_M  (LP_ANALOG_PERI_TOUCH_BYPASS_NEG_NOISE_THRES_V << LP_ANALOG_PERI_TOUCH_BYPASS_NEG_NOISE_THRES_S)
+#define LP_ANALOG_PERI_TOUCH_BYPASS_NEG_NOISE_THRES_V  0x00000001U
+#define LP_ANALOG_PERI_TOUCH_BYPASS_NEG_NOISE_THRES_S  31
 
-/** LP_ANA_TOUCH_FILTER3_REG register
+/** LP_ANALOG_PERI_TOUCH_FILTER3_REG register
  *  need_des
  */
-#define LP_ANA_TOUCH_FILTER3_REG (DR_REG_LP_ANA_BASE + 0x118)
-/** LP_ANA_TOUCH_BASELINE_SW : R/W; bitpos: [15:0]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_FILTER3_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x118)
+/** LP_ANALOG_PERI_TOUCH_BASELINE_SW : R/W; bitpos: [15:0]; default: 0;
  *  need_des
  */
-#define LP_ANA_TOUCH_BASELINE_SW    0x0000FFFFU
-#define LP_ANA_TOUCH_BASELINE_SW_M  (LP_ANA_TOUCH_BASELINE_SW_V << LP_ANA_TOUCH_BASELINE_SW_S)
-#define LP_ANA_TOUCH_BASELINE_SW_V  0x0000FFFFU
-#define LP_ANA_TOUCH_BASELINE_SW_S  0
-/** LP_ANA_TOUCH_UPDATE_BASELINE_SW : WT; bitpos: [16]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_BASELINE_SW    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_BASELINE_SW_M  (LP_ANALOG_PERI_TOUCH_BASELINE_SW_V << LP_ANALOG_PERI_TOUCH_BASELINE_SW_S)
+#define LP_ANALOG_PERI_TOUCH_BASELINE_SW_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_BASELINE_SW_S  0
+/** LP_ANALOG_PERI_TOUCH_UPDATE_BASELINE_SW : WT; bitpos: [16]; default: 0;
  *  need_des
  */
-#define LP_ANA_TOUCH_UPDATE_BASELINE_SW    (BIT(16))
-#define LP_ANA_TOUCH_UPDATE_BASELINE_SW_M  (LP_ANA_TOUCH_UPDATE_BASELINE_SW_V << LP_ANA_TOUCH_UPDATE_BASELINE_SW_S)
-#define LP_ANA_TOUCH_UPDATE_BASELINE_SW_V  0x00000001U
-#define LP_ANA_TOUCH_UPDATE_BASELINE_SW_S  16
+#define LP_ANALOG_PERI_TOUCH_UPDATE_BASELINE_SW    (BIT(16))
+#define LP_ANALOG_PERI_TOUCH_UPDATE_BASELINE_SW_M  (LP_ANALOG_PERI_TOUCH_UPDATE_BASELINE_SW_V << LP_ANALOG_PERI_TOUCH_UPDATE_BASELINE_SW_S)
+#define LP_ANALOG_PERI_TOUCH_UPDATE_BASELINE_SW_V  0x00000001U
+#define LP_ANALOG_PERI_TOUCH_UPDATE_BASELINE_SW_S  16
 
-/** LP_ANA_TOUCH_SLP0_REG register
+/** LP_ANALOG_PERI_TOUCH_SLP0_REG register
  *  need_des
  */
-#define LP_ANA_TOUCH_SLP0_REG (DR_REG_LP_ANA_BASE + 0x11c)
-/** LP_ANA_TOUCH_SLP_TH0 : R/W; bitpos: [15:0]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_SLP0_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x11c)
+/** LP_ANALOG_PERI_TOUCH_SLP_TH0 : R/W; bitpos: [15:0]; default: 0;
  *  need_des
  */
-#define LP_ANA_TOUCH_SLP_TH0    0x0000FFFFU
-#define LP_ANA_TOUCH_SLP_TH0_M  (LP_ANA_TOUCH_SLP_TH0_V << LP_ANA_TOUCH_SLP_TH0_S)
-#define LP_ANA_TOUCH_SLP_TH0_V  0x0000FFFFU
-#define LP_ANA_TOUCH_SLP_TH0_S  0
-/** LP_ANA_TOUCH_SLP_CHANNEL_CLR : WT; bitpos: [16]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_SLP_TH0    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_SLP_TH0_M  (LP_ANALOG_PERI_TOUCH_SLP_TH0_V << LP_ANALOG_PERI_TOUCH_SLP_TH0_S)
+#define LP_ANALOG_PERI_TOUCH_SLP_TH0_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_SLP_TH0_S  0
+/** LP_ANALOG_PERI_TOUCH_SLP_CHANNEL_CLR : WT; bitpos: [16]; default: 0;
  *  need_des
  */
-#define LP_ANA_TOUCH_SLP_CHANNEL_CLR    (BIT(16))
-#define LP_ANA_TOUCH_SLP_CHANNEL_CLR_M  (LP_ANA_TOUCH_SLP_CHANNEL_CLR_V << LP_ANA_TOUCH_SLP_CHANNEL_CLR_S)
-#define LP_ANA_TOUCH_SLP_CHANNEL_CLR_V  0x00000001U
-#define LP_ANA_TOUCH_SLP_CHANNEL_CLR_S  16
-/** LP_ANA_TOUCH_SLP_PAD : R/W; bitpos: [20:17]; default: 15;
+#define LP_ANALOG_PERI_TOUCH_SLP_CHANNEL_CLR    (BIT(16))
+#define LP_ANALOG_PERI_TOUCH_SLP_CHANNEL_CLR_M  (LP_ANALOG_PERI_TOUCH_SLP_CHANNEL_CLR_V << LP_ANALOG_PERI_TOUCH_SLP_CHANNEL_CLR_S)
+#define LP_ANALOG_PERI_TOUCH_SLP_CHANNEL_CLR_V  0x00000001U
+#define LP_ANALOG_PERI_TOUCH_SLP_CHANNEL_CLR_S  16
+/** LP_ANALOG_PERI_TOUCH_SLP_PAD : R/W; bitpos: [20:17]; default: 15;
  *  need_des
  */
-#define LP_ANA_TOUCH_SLP_PAD    0x0000000FU
-#define LP_ANA_TOUCH_SLP_PAD_M  (LP_ANA_TOUCH_SLP_PAD_V << LP_ANA_TOUCH_SLP_PAD_S)
-#define LP_ANA_TOUCH_SLP_PAD_V  0x0000000FU
-#define LP_ANA_TOUCH_SLP_PAD_S  17
+#define LP_ANALOG_PERI_TOUCH_SLP_PAD    0x0000000FU
+#define LP_ANALOG_PERI_TOUCH_SLP_PAD_M  (LP_ANALOG_PERI_TOUCH_SLP_PAD_V << LP_ANALOG_PERI_TOUCH_SLP_PAD_S)
+#define LP_ANALOG_PERI_TOUCH_SLP_PAD_V  0x0000000FU
+#define LP_ANALOG_PERI_TOUCH_SLP_PAD_S  17
 
-/** LP_ANA_TOUCH_SLP1_REG register
+/** LP_ANALOG_PERI_TOUCH_SLP1_REG register
  *  need_des
  */
-#define LP_ANA_TOUCH_SLP1_REG (DR_REG_LP_ANA_BASE + 0x120)
-/** LP_ANA_TOUCH_SLP_TH2 : R/W; bitpos: [15:0]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_SLP1_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x120)
+/** LP_ANALOG_PERI_TOUCH_SLP_TH2 : R/W; bitpos: [15:0]; default: 0;
  *  need_des
  */
-#define LP_ANA_TOUCH_SLP_TH2    0x0000FFFFU
-#define LP_ANA_TOUCH_SLP_TH2_M  (LP_ANA_TOUCH_SLP_TH2_V << LP_ANA_TOUCH_SLP_TH2_S)
-#define LP_ANA_TOUCH_SLP_TH2_V  0x0000FFFFU
-#define LP_ANA_TOUCH_SLP_TH2_S  0
-/** LP_ANA_TOUCH_SLP_TH1 : R/W; bitpos: [31:16]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_SLP_TH2    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_SLP_TH2_M  (LP_ANALOG_PERI_TOUCH_SLP_TH2_V << LP_ANALOG_PERI_TOUCH_SLP_TH2_S)
+#define LP_ANALOG_PERI_TOUCH_SLP_TH2_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_SLP_TH2_S  0
+/** LP_ANALOG_PERI_TOUCH_SLP_TH1 : R/W; bitpos: [31:16]; default: 0;
  *  need_des
  */
-#define LP_ANA_TOUCH_SLP_TH1    0x0000FFFFU
-#define LP_ANA_TOUCH_SLP_TH1_M  (LP_ANA_TOUCH_SLP_TH1_V << LP_ANA_TOUCH_SLP_TH1_S)
-#define LP_ANA_TOUCH_SLP_TH1_V  0x0000FFFFU
-#define LP_ANA_TOUCH_SLP_TH1_S  16
+#define LP_ANALOG_PERI_TOUCH_SLP_TH1    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_SLP_TH1_M  (LP_ANALOG_PERI_TOUCH_SLP_TH1_V << LP_ANALOG_PERI_TOUCH_SLP_TH1_S)
+#define LP_ANALOG_PERI_TOUCH_SLP_TH1_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_SLP_TH1_S  16
 
-/** LP_ANA_TOUCH_CLR_REG register
+/** LP_ANALOG_PERI_TOUCH_CLR_REG register
  *  need_des
  */
-#define LP_ANA_TOUCH_CLR_REG (DR_REG_LP_ANA_BASE + 0x124)
-/** LP_ANA_TOUCH_CHANNEL_CLR : WT; bitpos: [14:0]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_CLR_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x124)
+/** LP_ANALOG_PERI_TOUCH_CHANNEL_CLR : WT; bitpos: [14:0]; default: 0;
  *  need_des
  */
-#define LP_ANA_TOUCH_CHANNEL_CLR    0x00007FFFU
-#define LP_ANA_TOUCH_CHANNEL_CLR_M  (LP_ANA_TOUCH_CHANNEL_CLR_V << LP_ANA_TOUCH_CHANNEL_CLR_S)
-#define LP_ANA_TOUCH_CHANNEL_CLR_V  0x00007FFFU
-#define LP_ANA_TOUCH_CHANNEL_CLR_S  0
-/** LP_ANA_TOUCH_STATUS_CLR : WT; bitpos: [15]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_CHANNEL_CLR    0x00007FFFU
+#define LP_ANALOG_PERI_TOUCH_CHANNEL_CLR_M  (LP_ANALOG_PERI_TOUCH_CHANNEL_CLR_V << LP_ANALOG_PERI_TOUCH_CHANNEL_CLR_S)
+#define LP_ANALOG_PERI_TOUCH_CHANNEL_CLR_V  0x00007FFFU
+#define LP_ANALOG_PERI_TOUCH_CHANNEL_CLR_S  0
+/** LP_ANALOG_PERI_TOUCH_STATUS_CLR : WT; bitpos: [15]; default: 0;
  *  need_des
  */
-#define LP_ANA_TOUCH_STATUS_CLR    (BIT(15))
-#define LP_ANA_TOUCH_STATUS_CLR_M  (LP_ANA_TOUCH_STATUS_CLR_V << LP_ANA_TOUCH_STATUS_CLR_S)
-#define LP_ANA_TOUCH_STATUS_CLR_V  0x00000001U
-#define LP_ANA_TOUCH_STATUS_CLR_S  15
+#define LP_ANALOG_PERI_TOUCH_STATUS_CLR    (BIT(15))
+#define LP_ANALOG_PERI_TOUCH_STATUS_CLR_M  (LP_ANALOG_PERI_TOUCH_STATUS_CLR_V << LP_ANALOG_PERI_TOUCH_STATUS_CLR_S)
+#define LP_ANALOG_PERI_TOUCH_STATUS_CLR_V  0x00000001U
+#define LP_ANALOG_PERI_TOUCH_STATUS_CLR_S  15
 
-/** LP_ANA_TOUCH_APPROACH_REG register
+/** LP_ANALOG_PERI_TOUCH_APPROACH_REG register
  *  need_des
  */
-#define LP_ANA_TOUCH_APPROACH_REG (DR_REG_LP_ANA_BASE + 0x128)
-/** LP_ANA_TOUCH_APPROACH_PAD0 : R/W; bitpos: [3:0]; default: 15;
+#define LP_ANALOG_PERI_TOUCH_APPROACH_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x128)
+/** LP_ANALOG_PERI_TOUCH_APPROACH_PAD0 : R/W; bitpos: [3:0]; default: 15;
  *  need_des
  */
-#define LP_ANA_TOUCH_APPROACH_PAD0    0x0000000FU
-#define LP_ANA_TOUCH_APPROACH_PAD0_M  (LP_ANA_TOUCH_APPROACH_PAD0_V << LP_ANA_TOUCH_APPROACH_PAD0_S)
-#define LP_ANA_TOUCH_APPROACH_PAD0_V  0x0000000FU
-#define LP_ANA_TOUCH_APPROACH_PAD0_S  0
-/** LP_ANA_TOUCH_APPROACH_PAD1 : R/W; bitpos: [7:4]; default: 15;
+#define LP_ANALOG_PERI_TOUCH_APPROACH_PAD0    0x0000000FU
+#define LP_ANALOG_PERI_TOUCH_APPROACH_PAD0_M  (LP_ANALOG_PERI_TOUCH_APPROACH_PAD0_V << LP_ANALOG_PERI_TOUCH_APPROACH_PAD0_S)
+#define LP_ANALOG_PERI_TOUCH_APPROACH_PAD0_V  0x0000000FU
+#define LP_ANALOG_PERI_TOUCH_APPROACH_PAD0_S  0
+/** LP_ANALOG_PERI_TOUCH_APPROACH_PAD1 : R/W; bitpos: [7:4]; default: 15;
  *  need_des
  */
-#define LP_ANA_TOUCH_APPROACH_PAD1    0x0000000FU
-#define LP_ANA_TOUCH_APPROACH_PAD1_M  (LP_ANA_TOUCH_APPROACH_PAD1_V << LP_ANA_TOUCH_APPROACH_PAD1_S)
-#define LP_ANA_TOUCH_APPROACH_PAD1_V  0x0000000FU
-#define LP_ANA_TOUCH_APPROACH_PAD1_S  4
-/** LP_ANA_TOUCH_APPROACH_PAD2 : R/W; bitpos: [11:8]; default: 15;
+#define LP_ANALOG_PERI_TOUCH_APPROACH_PAD1    0x0000000FU
+#define LP_ANALOG_PERI_TOUCH_APPROACH_PAD1_M  (LP_ANALOG_PERI_TOUCH_APPROACH_PAD1_V << LP_ANALOG_PERI_TOUCH_APPROACH_PAD1_S)
+#define LP_ANALOG_PERI_TOUCH_APPROACH_PAD1_V  0x0000000FU
+#define LP_ANALOG_PERI_TOUCH_APPROACH_PAD1_S  4
+/** LP_ANALOG_PERI_TOUCH_APPROACH_PAD2 : R/W; bitpos: [11:8]; default: 15;
  *  need_des
  */
-#define LP_ANA_TOUCH_APPROACH_PAD2    0x0000000FU
-#define LP_ANA_TOUCH_APPROACH_PAD2_M  (LP_ANA_TOUCH_APPROACH_PAD2_V << LP_ANA_TOUCH_APPROACH_PAD2_S)
-#define LP_ANA_TOUCH_APPROACH_PAD2_V  0x0000000FU
-#define LP_ANA_TOUCH_APPROACH_PAD2_S  8
-/** LP_ANA_TOUCH_SLP_APPROACH_EN : R/W; bitpos: [12]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_APPROACH_PAD2    0x0000000FU
+#define LP_ANALOG_PERI_TOUCH_APPROACH_PAD2_M  (LP_ANALOG_PERI_TOUCH_APPROACH_PAD2_V << LP_ANALOG_PERI_TOUCH_APPROACH_PAD2_S)
+#define LP_ANALOG_PERI_TOUCH_APPROACH_PAD2_V  0x0000000FU
+#define LP_ANALOG_PERI_TOUCH_APPROACH_PAD2_S  8
+/** LP_ANALOG_PERI_TOUCH_SLP_APPROACH_EN : R/W; bitpos: [12]; default: 0;
  *  need_des
  */
-#define LP_ANA_TOUCH_SLP_APPROACH_EN    (BIT(12))
-#define LP_ANA_TOUCH_SLP_APPROACH_EN_M  (LP_ANA_TOUCH_SLP_APPROACH_EN_V << LP_ANA_TOUCH_SLP_APPROACH_EN_S)
-#define LP_ANA_TOUCH_SLP_APPROACH_EN_V  0x00000001U
-#define LP_ANA_TOUCH_SLP_APPROACH_EN_S  12
+#define LP_ANALOG_PERI_TOUCH_SLP_APPROACH_EN    (BIT(12))
+#define LP_ANALOG_PERI_TOUCH_SLP_APPROACH_EN_M  (LP_ANALOG_PERI_TOUCH_SLP_APPROACH_EN_V << LP_ANALOG_PERI_TOUCH_SLP_APPROACH_EN_S)
+#define LP_ANALOG_PERI_TOUCH_SLP_APPROACH_EN_V  0x00000001U
+#define LP_ANALOG_PERI_TOUCH_SLP_APPROACH_EN_S  12
 
-/** LP_ANA_TOUCH_FREQ0_SCAN_PARA_REG register
+/** LP_ANALOG_PERI_TOUCH_FREQ0_SCAN_PARA_REG register
  *  need_des
  */
-#define LP_ANA_TOUCH_FREQ0_SCAN_PARA_REG (DR_REG_LP_ANA_BASE + 0x12c)
-/** LP_ANA_TOUCH_FREQ0_DCAP_LPF : R/W; bitpos: [6:0]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_FREQ0_SCAN_PARA_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x12c)
+/** LP_ANALOG_PERI_TOUCH_FREQ0_DCAP_LPF : R/W; bitpos: [6:0]; default: 0;
  *  need_des
  */
-#define LP_ANA_TOUCH_FREQ0_DCAP_LPF    0x0000007FU
-#define LP_ANA_TOUCH_FREQ0_DCAP_LPF_M  (LP_ANA_TOUCH_FREQ0_DCAP_LPF_V << LP_ANA_TOUCH_FREQ0_DCAP_LPF_S)
-#define LP_ANA_TOUCH_FREQ0_DCAP_LPF_V  0x0000007FU
-#define LP_ANA_TOUCH_FREQ0_DCAP_LPF_S  0
-/** LP_ANA_TOUCH_FREQ0_DRES_LPF : R/W; bitpos: [8:7]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_FREQ0_DCAP_LPF    0x0000007FU
+#define LP_ANALOG_PERI_TOUCH_FREQ0_DCAP_LPF_M  (LP_ANALOG_PERI_TOUCH_FREQ0_DCAP_LPF_V << LP_ANALOG_PERI_TOUCH_FREQ0_DCAP_LPF_S)
+#define LP_ANALOG_PERI_TOUCH_FREQ0_DCAP_LPF_V  0x0000007FU
+#define LP_ANALOG_PERI_TOUCH_FREQ0_DCAP_LPF_S  0
+/** LP_ANALOG_PERI_TOUCH_FREQ0_DRES_LPF : R/W; bitpos: [8:7]; default: 0;
  *  need_des
  */
-#define LP_ANA_TOUCH_FREQ0_DRES_LPF    0x00000003U
-#define LP_ANA_TOUCH_FREQ0_DRES_LPF_M  (LP_ANA_TOUCH_FREQ0_DRES_LPF_V << LP_ANA_TOUCH_FREQ0_DRES_LPF_S)
-#define LP_ANA_TOUCH_FREQ0_DRES_LPF_V  0x00000003U
-#define LP_ANA_TOUCH_FREQ0_DRES_LPF_S  7
-/** LP_ANA_TOUCH_FREQ0_DRV_LS : R/W; bitpos: [12:9]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_FREQ0_DRES_LPF    0x00000003U
+#define LP_ANALOG_PERI_TOUCH_FREQ0_DRES_LPF_M  (LP_ANALOG_PERI_TOUCH_FREQ0_DRES_LPF_V << LP_ANALOG_PERI_TOUCH_FREQ0_DRES_LPF_S)
+#define LP_ANALOG_PERI_TOUCH_FREQ0_DRES_LPF_V  0x00000003U
+#define LP_ANALOG_PERI_TOUCH_FREQ0_DRES_LPF_S  7
+/** LP_ANALOG_PERI_TOUCH_FREQ0_DRV_LS : R/W; bitpos: [12:9]; default: 0;
  *  need_des
  */
-#define LP_ANA_TOUCH_FREQ0_DRV_LS    0x0000000FU
-#define LP_ANA_TOUCH_FREQ0_DRV_LS_M  (LP_ANA_TOUCH_FREQ0_DRV_LS_V << LP_ANA_TOUCH_FREQ0_DRV_LS_S)
-#define LP_ANA_TOUCH_FREQ0_DRV_LS_V  0x0000000FU
-#define LP_ANA_TOUCH_FREQ0_DRV_LS_S  9
-/** LP_ANA_TOUCH_FREQ0_DRV_HS : R/W; bitpos: [17:13]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_FREQ0_DRV_LS    0x0000000FU
+#define LP_ANALOG_PERI_TOUCH_FREQ0_DRV_LS_M  (LP_ANALOG_PERI_TOUCH_FREQ0_DRV_LS_V << LP_ANALOG_PERI_TOUCH_FREQ0_DRV_LS_S)
+#define LP_ANALOG_PERI_TOUCH_FREQ0_DRV_LS_V  0x0000000FU
+#define LP_ANALOG_PERI_TOUCH_FREQ0_DRV_LS_S  9
+/** LP_ANALOG_PERI_TOUCH_FREQ0_DRV_HS : R/W; bitpos: [17:13]; default: 0;
  *  need_des
  */
-#define LP_ANA_TOUCH_FREQ0_DRV_HS    0x0000001FU
-#define LP_ANA_TOUCH_FREQ0_DRV_HS_M  (LP_ANA_TOUCH_FREQ0_DRV_HS_V << LP_ANA_TOUCH_FREQ0_DRV_HS_S)
-#define LP_ANA_TOUCH_FREQ0_DRV_HS_V  0x0000001FU
-#define LP_ANA_TOUCH_FREQ0_DRV_HS_S  13
-/** LP_ANA_TOUCH_FREQ0_DBIAS : R/W; bitpos: [22:18]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_FREQ0_DRV_HS    0x0000001FU
+#define LP_ANALOG_PERI_TOUCH_FREQ0_DRV_HS_M  (LP_ANALOG_PERI_TOUCH_FREQ0_DRV_HS_V << LP_ANALOG_PERI_TOUCH_FREQ0_DRV_HS_S)
+#define LP_ANALOG_PERI_TOUCH_FREQ0_DRV_HS_V  0x0000001FU
+#define LP_ANALOG_PERI_TOUCH_FREQ0_DRV_HS_S  13
+/** LP_ANALOG_PERI_TOUCH_FREQ0_DBIAS : R/W; bitpos: [22:18]; default: 0;
  *  need_des
  */
-#define LP_ANA_TOUCH_FREQ0_DBIAS    0x0000001FU
-#define LP_ANA_TOUCH_FREQ0_DBIAS_M  (LP_ANA_TOUCH_FREQ0_DBIAS_V << LP_ANA_TOUCH_FREQ0_DBIAS_S)
-#define LP_ANA_TOUCH_FREQ0_DBIAS_V  0x0000001FU
-#define LP_ANA_TOUCH_FREQ0_DBIAS_S  18
+#define LP_ANALOG_PERI_TOUCH_FREQ0_DBIAS    0x0000001FU
+#define LP_ANALOG_PERI_TOUCH_FREQ0_DBIAS_M  (LP_ANALOG_PERI_TOUCH_FREQ0_DBIAS_V << LP_ANALOG_PERI_TOUCH_FREQ0_DBIAS_S)
+#define LP_ANALOG_PERI_TOUCH_FREQ0_DBIAS_V  0x0000001FU
+#define LP_ANALOG_PERI_TOUCH_FREQ0_DBIAS_S  18
 
-/** LP_ANA_TOUCH_FREQ1_SCAN_PARA_REG register
+/** LP_ANALOG_PERI_TOUCH_FREQ1_SCAN_PARA_REG register
  *  need_des
  */
-#define LP_ANA_TOUCH_FREQ1_SCAN_PARA_REG (DR_REG_LP_ANA_BASE + 0x130)
-/** LP_ANA_TOUCH_FREQ1_DCAP_LPF : R/W; bitpos: [6:0]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_FREQ1_SCAN_PARA_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x130)
+/** LP_ANALOG_PERI_TOUCH_FREQ1_DCAP_LPF : R/W; bitpos: [6:0]; default: 0;
  *  need_des
  */
-#define LP_ANA_TOUCH_FREQ1_DCAP_LPF    0x0000007FU
-#define LP_ANA_TOUCH_FREQ1_DCAP_LPF_M  (LP_ANA_TOUCH_FREQ1_DCAP_LPF_V << LP_ANA_TOUCH_FREQ1_DCAP_LPF_S)
-#define LP_ANA_TOUCH_FREQ1_DCAP_LPF_V  0x0000007FU
-#define LP_ANA_TOUCH_FREQ1_DCAP_LPF_S  0
-/** LP_ANA_TOUCH_FREQ1_DRES_LPF : R/W; bitpos: [8:7]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_FREQ1_DCAP_LPF    0x0000007FU
+#define LP_ANALOG_PERI_TOUCH_FREQ1_DCAP_LPF_M  (LP_ANALOG_PERI_TOUCH_FREQ1_DCAP_LPF_V << LP_ANALOG_PERI_TOUCH_FREQ1_DCAP_LPF_S)
+#define LP_ANALOG_PERI_TOUCH_FREQ1_DCAP_LPF_V  0x0000007FU
+#define LP_ANALOG_PERI_TOUCH_FREQ1_DCAP_LPF_S  0
+/** LP_ANALOG_PERI_TOUCH_FREQ1_DRES_LPF : R/W; bitpos: [8:7]; default: 0;
  *  need_des
  */
-#define LP_ANA_TOUCH_FREQ1_DRES_LPF    0x00000003U
-#define LP_ANA_TOUCH_FREQ1_DRES_LPF_M  (LP_ANA_TOUCH_FREQ1_DRES_LPF_V << LP_ANA_TOUCH_FREQ1_DRES_LPF_S)
-#define LP_ANA_TOUCH_FREQ1_DRES_LPF_V  0x00000003U
-#define LP_ANA_TOUCH_FREQ1_DRES_LPF_S  7
-/** LP_ANA_TOUCH_FREQ1_DRV_LS : R/W; bitpos: [12:9]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_FREQ1_DRES_LPF    0x00000003U
+#define LP_ANALOG_PERI_TOUCH_FREQ1_DRES_LPF_M  (LP_ANALOG_PERI_TOUCH_FREQ1_DRES_LPF_V << LP_ANALOG_PERI_TOUCH_FREQ1_DRES_LPF_S)
+#define LP_ANALOG_PERI_TOUCH_FREQ1_DRES_LPF_V  0x00000003U
+#define LP_ANALOG_PERI_TOUCH_FREQ1_DRES_LPF_S  7
+/** LP_ANALOG_PERI_TOUCH_FREQ1_DRV_LS : R/W; bitpos: [12:9]; default: 0;
  *  need_des
  */
-#define LP_ANA_TOUCH_FREQ1_DRV_LS    0x0000000FU
-#define LP_ANA_TOUCH_FREQ1_DRV_LS_M  (LP_ANA_TOUCH_FREQ1_DRV_LS_V << LP_ANA_TOUCH_FREQ1_DRV_LS_S)
-#define LP_ANA_TOUCH_FREQ1_DRV_LS_V  0x0000000FU
-#define LP_ANA_TOUCH_FREQ1_DRV_LS_S  9
-/** LP_ANA_TOUCH_FREQ1_DRV_HS : R/W; bitpos: [17:13]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_FREQ1_DRV_LS    0x0000000FU
+#define LP_ANALOG_PERI_TOUCH_FREQ1_DRV_LS_M  (LP_ANALOG_PERI_TOUCH_FREQ1_DRV_LS_V << LP_ANALOG_PERI_TOUCH_FREQ1_DRV_LS_S)
+#define LP_ANALOG_PERI_TOUCH_FREQ1_DRV_LS_V  0x0000000FU
+#define LP_ANALOG_PERI_TOUCH_FREQ1_DRV_LS_S  9
+/** LP_ANALOG_PERI_TOUCH_FREQ1_DRV_HS : R/W; bitpos: [17:13]; default: 0;
  *  need_des
  */
-#define LP_ANA_TOUCH_FREQ1_DRV_HS    0x0000001FU
-#define LP_ANA_TOUCH_FREQ1_DRV_HS_M  (LP_ANA_TOUCH_FREQ1_DRV_HS_V << LP_ANA_TOUCH_FREQ1_DRV_HS_S)
-#define LP_ANA_TOUCH_FREQ1_DRV_HS_V  0x0000001FU
-#define LP_ANA_TOUCH_FREQ1_DRV_HS_S  13
-/** LP_ANA_TOUCH_FREQ1_DBIAS : R/W; bitpos: [22:18]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_FREQ1_DRV_HS    0x0000001FU
+#define LP_ANALOG_PERI_TOUCH_FREQ1_DRV_HS_M  (LP_ANALOG_PERI_TOUCH_FREQ1_DRV_HS_V << LP_ANALOG_PERI_TOUCH_FREQ1_DRV_HS_S)
+#define LP_ANALOG_PERI_TOUCH_FREQ1_DRV_HS_V  0x0000001FU
+#define LP_ANALOG_PERI_TOUCH_FREQ1_DRV_HS_S  13
+/** LP_ANALOG_PERI_TOUCH_FREQ1_DBIAS : R/W; bitpos: [22:18]; default: 0;
  *  need_des
  */
-#define LP_ANA_TOUCH_FREQ1_DBIAS    0x0000001FU
-#define LP_ANA_TOUCH_FREQ1_DBIAS_M  (LP_ANA_TOUCH_FREQ1_DBIAS_V << LP_ANA_TOUCH_FREQ1_DBIAS_S)
-#define LP_ANA_TOUCH_FREQ1_DBIAS_V  0x0000001FU
-#define LP_ANA_TOUCH_FREQ1_DBIAS_S  18
+#define LP_ANALOG_PERI_TOUCH_FREQ1_DBIAS    0x0000001FU
+#define LP_ANALOG_PERI_TOUCH_FREQ1_DBIAS_M  (LP_ANALOG_PERI_TOUCH_FREQ1_DBIAS_V << LP_ANALOG_PERI_TOUCH_FREQ1_DBIAS_S)
+#define LP_ANALOG_PERI_TOUCH_FREQ1_DBIAS_V  0x0000001FU
+#define LP_ANALOG_PERI_TOUCH_FREQ1_DBIAS_S  18
 
-/** LP_ANA_TOUCH_FREQ2_SCAN_PARA_REG register
+/** LP_ANALOG_PERI_TOUCH_FREQ2_SCAN_PARA_REG register
  *  need_des
  */
-#define LP_ANA_TOUCH_FREQ2_SCAN_PARA_REG (DR_REG_LP_ANA_BASE + 0x134)
-/** LP_ANA_TOUCH_FREQ2_DCAP_LPF : R/W; bitpos: [6:0]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_FREQ2_SCAN_PARA_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x134)
+/** LP_ANALOG_PERI_TOUCH_FREQ2_DCAP_LPF : R/W; bitpos: [6:0]; default: 0;
  *  need_des
  */
-#define LP_ANA_TOUCH_FREQ2_DCAP_LPF    0x0000007FU
-#define LP_ANA_TOUCH_FREQ2_DCAP_LPF_M  (LP_ANA_TOUCH_FREQ2_DCAP_LPF_V << LP_ANA_TOUCH_FREQ2_DCAP_LPF_S)
-#define LP_ANA_TOUCH_FREQ2_DCAP_LPF_V  0x0000007FU
-#define LP_ANA_TOUCH_FREQ2_DCAP_LPF_S  0
-/** LP_ANA_TOUCH_FREQ2_DRES_LPF : R/W; bitpos: [8:7]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_FREQ2_DCAP_LPF    0x0000007FU
+#define LP_ANALOG_PERI_TOUCH_FREQ2_DCAP_LPF_M  (LP_ANALOG_PERI_TOUCH_FREQ2_DCAP_LPF_V << LP_ANALOG_PERI_TOUCH_FREQ2_DCAP_LPF_S)
+#define LP_ANALOG_PERI_TOUCH_FREQ2_DCAP_LPF_V  0x0000007FU
+#define LP_ANALOG_PERI_TOUCH_FREQ2_DCAP_LPF_S  0
+/** LP_ANALOG_PERI_TOUCH_FREQ2_DRES_LPF : R/W; bitpos: [8:7]; default: 0;
  *  need_des
  */
-#define LP_ANA_TOUCH_FREQ2_DRES_LPF    0x00000003U
-#define LP_ANA_TOUCH_FREQ2_DRES_LPF_M  (LP_ANA_TOUCH_FREQ2_DRES_LPF_V << LP_ANA_TOUCH_FREQ2_DRES_LPF_S)
-#define LP_ANA_TOUCH_FREQ2_DRES_LPF_V  0x00000003U
-#define LP_ANA_TOUCH_FREQ2_DRES_LPF_S  7
-/** LP_ANA_TOUCH_FREQ2_DRV_LS : R/W; bitpos: [12:9]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_FREQ2_DRES_LPF    0x00000003U
+#define LP_ANALOG_PERI_TOUCH_FREQ2_DRES_LPF_M  (LP_ANALOG_PERI_TOUCH_FREQ2_DRES_LPF_V << LP_ANALOG_PERI_TOUCH_FREQ2_DRES_LPF_S)
+#define LP_ANALOG_PERI_TOUCH_FREQ2_DRES_LPF_V  0x00000003U
+#define LP_ANALOG_PERI_TOUCH_FREQ2_DRES_LPF_S  7
+/** LP_ANALOG_PERI_TOUCH_FREQ2_DRV_LS : R/W; bitpos: [12:9]; default: 0;
  *  need_des
  */
-#define LP_ANA_TOUCH_FREQ2_DRV_LS    0x0000000FU
-#define LP_ANA_TOUCH_FREQ2_DRV_LS_M  (LP_ANA_TOUCH_FREQ2_DRV_LS_V << LP_ANA_TOUCH_FREQ2_DRV_LS_S)
-#define LP_ANA_TOUCH_FREQ2_DRV_LS_V  0x0000000FU
-#define LP_ANA_TOUCH_FREQ2_DRV_LS_S  9
-/** LP_ANA_TOUCH_FREQ2_DRV_HS : R/W; bitpos: [17:13]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_FREQ2_DRV_LS    0x0000000FU
+#define LP_ANALOG_PERI_TOUCH_FREQ2_DRV_LS_M  (LP_ANALOG_PERI_TOUCH_FREQ2_DRV_LS_V << LP_ANALOG_PERI_TOUCH_FREQ2_DRV_LS_S)
+#define LP_ANALOG_PERI_TOUCH_FREQ2_DRV_LS_V  0x0000000FU
+#define LP_ANALOG_PERI_TOUCH_FREQ2_DRV_LS_S  9
+/** LP_ANALOG_PERI_TOUCH_FREQ2_DRV_HS : R/W; bitpos: [17:13]; default: 0;
  *  need_des
  */
-#define LP_ANA_TOUCH_FREQ2_DRV_HS    0x0000001FU
-#define LP_ANA_TOUCH_FREQ2_DRV_HS_M  (LP_ANA_TOUCH_FREQ2_DRV_HS_V << LP_ANA_TOUCH_FREQ2_DRV_HS_S)
-#define LP_ANA_TOUCH_FREQ2_DRV_HS_V  0x0000001FU
-#define LP_ANA_TOUCH_FREQ2_DRV_HS_S  13
-/** LP_ANA_TOUCH_FREQ2_DBIAS : R/W; bitpos: [22:18]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_FREQ2_DRV_HS    0x0000001FU
+#define LP_ANALOG_PERI_TOUCH_FREQ2_DRV_HS_M  (LP_ANALOG_PERI_TOUCH_FREQ2_DRV_HS_V << LP_ANALOG_PERI_TOUCH_FREQ2_DRV_HS_S)
+#define LP_ANALOG_PERI_TOUCH_FREQ2_DRV_HS_V  0x0000001FU
+#define LP_ANALOG_PERI_TOUCH_FREQ2_DRV_HS_S  13
+/** LP_ANALOG_PERI_TOUCH_FREQ2_DBIAS : R/W; bitpos: [22:18]; default: 0;
  *  need_des
  */
-#define LP_ANA_TOUCH_FREQ2_DBIAS    0x0000001FU
-#define LP_ANA_TOUCH_FREQ2_DBIAS_M  (LP_ANA_TOUCH_FREQ2_DBIAS_V << LP_ANA_TOUCH_FREQ2_DBIAS_S)
-#define LP_ANA_TOUCH_FREQ2_DBIAS_V  0x0000001FU
-#define LP_ANA_TOUCH_FREQ2_DBIAS_S  18
+#define LP_ANALOG_PERI_TOUCH_FREQ2_DBIAS    0x0000001FU
+#define LP_ANALOG_PERI_TOUCH_FREQ2_DBIAS_M  (LP_ANALOG_PERI_TOUCH_FREQ2_DBIAS_V << LP_ANALOG_PERI_TOUCH_FREQ2_DBIAS_S)
+#define LP_ANALOG_PERI_TOUCH_FREQ2_DBIAS_V  0x0000001FU
+#define LP_ANALOG_PERI_TOUCH_FREQ2_DBIAS_S  18
 
-/** LP_ANA_TOUCH_ANA_PARA_REG register
+/** LP_ANALOG_PERI_TOUCH_ANA_PARA_REG register
  *  need_des
  */
-#define LP_ANA_TOUCH_ANA_PARA_REG (DR_REG_LP_ANA_BASE + 0x138)
-/** LP_ANA_TOUCH_TOUCH_BUF_DRV : R/W; bitpos: [2:0]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_ANA_PARA_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x138)
+/** LP_ANALOG_PERI_TOUCH_TOUCH_BUF_DRV : R/W; bitpos: [2:0]; default: 0;
  *  need_des
  */
-#define LP_ANA_TOUCH_TOUCH_BUF_DRV    0x00000007U
-#define LP_ANA_TOUCH_TOUCH_BUF_DRV_M  (LP_ANA_TOUCH_TOUCH_BUF_DRV_V << LP_ANA_TOUCH_TOUCH_BUF_DRV_S)
-#define LP_ANA_TOUCH_TOUCH_BUF_DRV_V  0x00000007U
-#define LP_ANA_TOUCH_TOUCH_BUF_DRV_S  0
-/** LP_ANA_TOUCH_TOUCH_EN_CAL : R/W; bitpos: [3]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_TOUCH_BUF_DRV    0x00000007U
+#define LP_ANALOG_PERI_TOUCH_TOUCH_BUF_DRV_M  (LP_ANALOG_PERI_TOUCH_TOUCH_BUF_DRV_V << LP_ANALOG_PERI_TOUCH_TOUCH_BUF_DRV_S)
+#define LP_ANALOG_PERI_TOUCH_TOUCH_BUF_DRV_V  0x00000007U
+#define LP_ANALOG_PERI_TOUCH_TOUCH_BUF_DRV_S  0
+/** LP_ANALOG_PERI_TOUCH_TOUCH_EN_CAL : R/W; bitpos: [3]; default: 0;
  *  need_des
  */
-#define LP_ANA_TOUCH_TOUCH_EN_CAL    (BIT(3))
-#define LP_ANA_TOUCH_TOUCH_EN_CAL_M  (LP_ANA_TOUCH_TOUCH_EN_CAL_V << LP_ANA_TOUCH_TOUCH_EN_CAL_S)
-#define LP_ANA_TOUCH_TOUCH_EN_CAL_V  0x00000001U
-#define LP_ANA_TOUCH_TOUCH_EN_CAL_S  3
-/** LP_ANA_TOUCH_TOUCH_DCAP_CAL : R/W; bitpos: [10:4]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_TOUCH_EN_CAL    (BIT(3))
+#define LP_ANALOG_PERI_TOUCH_TOUCH_EN_CAL_M  (LP_ANALOG_PERI_TOUCH_TOUCH_EN_CAL_V << LP_ANALOG_PERI_TOUCH_TOUCH_EN_CAL_S)
+#define LP_ANALOG_PERI_TOUCH_TOUCH_EN_CAL_V  0x00000001U
+#define LP_ANALOG_PERI_TOUCH_TOUCH_EN_CAL_S  3
+/** LP_ANALOG_PERI_TOUCH_TOUCH_DCAP_CAL : R/W; bitpos: [10:4]; default: 0;
  *  need_des
  */
-#define LP_ANA_TOUCH_TOUCH_DCAP_CAL    0x0000007FU
-#define LP_ANA_TOUCH_TOUCH_DCAP_CAL_M  (LP_ANA_TOUCH_TOUCH_DCAP_CAL_V << LP_ANA_TOUCH_TOUCH_DCAP_CAL_S)
-#define LP_ANA_TOUCH_TOUCH_DCAP_CAL_V  0x0000007FU
-#define LP_ANA_TOUCH_TOUCH_DCAP_CAL_S  4
+#define LP_ANALOG_PERI_TOUCH_TOUCH_DCAP_CAL    0x0000007FU
+#define LP_ANALOG_PERI_TOUCH_TOUCH_DCAP_CAL_M  (LP_ANALOG_PERI_TOUCH_TOUCH_DCAP_CAL_V << LP_ANALOG_PERI_TOUCH_TOUCH_DCAP_CAL_S)
+#define LP_ANALOG_PERI_TOUCH_TOUCH_DCAP_CAL_V  0x0000007FU
+#define LP_ANALOG_PERI_TOUCH_TOUCH_DCAP_CAL_S  4
 
-/** LP_ANA_TOUCH_MUX0_REG register
+/** LP_ANALOG_PERI_TOUCH_MUX0_REG register
  *  need_des
  */
-#define LP_ANA_TOUCH_MUX0_REG (DR_REG_LP_ANA_BASE + 0x13c)
-/** LP_ANA_TOUCH_DATA_SEL : R/W; bitpos: [9:8]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_MUX0_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x13c)
+/** LP_ANALOG_PERI_TOUCH_DATA_SEL : R/W; bitpos: [9:8]; default: 0;
  *  need_des
  */
-#define LP_ANA_TOUCH_DATA_SEL    0x00000003U
-#define LP_ANA_TOUCH_DATA_SEL_M  (LP_ANA_TOUCH_DATA_SEL_V << LP_ANA_TOUCH_DATA_SEL_S)
-#define LP_ANA_TOUCH_DATA_SEL_V  0x00000003U
-#define LP_ANA_TOUCH_DATA_SEL_S  8
-/** LP_ANA_TOUCH_FREQ_SEL : R/W; bitpos: [11:10]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_DATA_SEL    0x00000003U
+#define LP_ANALOG_PERI_TOUCH_DATA_SEL_M  (LP_ANALOG_PERI_TOUCH_DATA_SEL_V << LP_ANALOG_PERI_TOUCH_DATA_SEL_S)
+#define LP_ANALOG_PERI_TOUCH_DATA_SEL_V  0x00000003U
+#define LP_ANALOG_PERI_TOUCH_DATA_SEL_S  8
+/** LP_ANALOG_PERI_TOUCH_FREQ_SEL : R/W; bitpos: [11:10]; default: 0;
  *  need_des
  */
-#define LP_ANA_TOUCH_FREQ_SEL    0x00000003U
-#define LP_ANA_TOUCH_FREQ_SEL_M  (LP_ANA_TOUCH_FREQ_SEL_V << LP_ANA_TOUCH_FREQ_SEL_S)
-#define LP_ANA_TOUCH_FREQ_SEL_V  0x00000003U
-#define LP_ANA_TOUCH_FREQ_SEL_S  10
-/** LP_ANA_TOUCH_BUFSEL : R/W; bitpos: [26:12]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_FREQ_SEL    0x00000003U
+#define LP_ANALOG_PERI_TOUCH_FREQ_SEL_M  (LP_ANALOG_PERI_TOUCH_FREQ_SEL_V << LP_ANALOG_PERI_TOUCH_FREQ_SEL_S)
+#define LP_ANALOG_PERI_TOUCH_FREQ_SEL_V  0x00000003U
+#define LP_ANALOG_PERI_TOUCH_FREQ_SEL_S  10
+/** LP_ANALOG_PERI_TOUCH_BUFSEL : R/W; bitpos: [26:12]; default: 0;
  *  need_des
  */
-#define LP_ANA_TOUCH_BUFSEL    0x00007FFFU
-#define LP_ANA_TOUCH_BUFSEL_M  (LP_ANA_TOUCH_BUFSEL_V << LP_ANA_TOUCH_BUFSEL_S)
-#define LP_ANA_TOUCH_BUFSEL_V  0x00007FFFU
-#define LP_ANA_TOUCH_BUFSEL_S  12
-/** LP_ANA_TOUCH_DONE_EN : R/W; bitpos: [27]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_BUFSEL    0x00007FFFU
+#define LP_ANALOG_PERI_TOUCH_BUFSEL_M  (LP_ANALOG_PERI_TOUCH_BUFSEL_V << LP_ANALOG_PERI_TOUCH_BUFSEL_S)
+#define LP_ANALOG_PERI_TOUCH_BUFSEL_V  0x00007FFFU
+#define LP_ANALOG_PERI_TOUCH_BUFSEL_S  12
+/** LP_ANALOG_PERI_TOUCH_DONE_EN : R/W; bitpos: [27]; default: 0;
  *  need_des
  */
-#define LP_ANA_TOUCH_DONE_EN    (BIT(27))
-#define LP_ANA_TOUCH_DONE_EN_M  (LP_ANA_TOUCH_DONE_EN_V << LP_ANA_TOUCH_DONE_EN_S)
-#define LP_ANA_TOUCH_DONE_EN_V  0x00000001U
-#define LP_ANA_TOUCH_DONE_EN_S  27
-/** LP_ANA_TOUCH_DONE_FORCE : R/W; bitpos: [28]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_DONE_EN    (BIT(27))
+#define LP_ANALOG_PERI_TOUCH_DONE_EN_M  (LP_ANALOG_PERI_TOUCH_DONE_EN_V << LP_ANALOG_PERI_TOUCH_DONE_EN_S)
+#define LP_ANALOG_PERI_TOUCH_DONE_EN_V  0x00000001U
+#define LP_ANALOG_PERI_TOUCH_DONE_EN_S  27
+/** LP_ANALOG_PERI_TOUCH_DONE_FORCE : R/W; bitpos: [28]; default: 0;
  *  need_des
  */
-#define LP_ANA_TOUCH_DONE_FORCE    (BIT(28))
-#define LP_ANA_TOUCH_DONE_FORCE_M  (LP_ANA_TOUCH_DONE_FORCE_V << LP_ANA_TOUCH_DONE_FORCE_S)
-#define LP_ANA_TOUCH_DONE_FORCE_V  0x00000001U
-#define LP_ANA_TOUCH_DONE_FORCE_S  28
-/** LP_ANA_TOUCH_FSM_EN : R/W; bitpos: [29]; default: 1;
+#define LP_ANALOG_PERI_TOUCH_DONE_FORCE    (BIT(28))
+#define LP_ANALOG_PERI_TOUCH_DONE_FORCE_M  (LP_ANALOG_PERI_TOUCH_DONE_FORCE_V << LP_ANALOG_PERI_TOUCH_DONE_FORCE_S)
+#define LP_ANALOG_PERI_TOUCH_DONE_FORCE_V  0x00000001U
+#define LP_ANALOG_PERI_TOUCH_DONE_FORCE_S  28
+/** LP_ANALOG_PERI_TOUCH_FSM_EN : R/W; bitpos: [29]; default: 1;
  *  need_des
  */
-#define LP_ANA_TOUCH_FSM_EN    (BIT(29))
-#define LP_ANA_TOUCH_FSM_EN_M  (LP_ANA_TOUCH_FSM_EN_V << LP_ANA_TOUCH_FSM_EN_S)
-#define LP_ANA_TOUCH_FSM_EN_V  0x00000001U
-#define LP_ANA_TOUCH_FSM_EN_S  29
-/** LP_ANA_TOUCH_START_EN : R/W; bitpos: [30]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_FSM_EN    (BIT(29))
+#define LP_ANALOG_PERI_TOUCH_FSM_EN_M  (LP_ANALOG_PERI_TOUCH_FSM_EN_V << LP_ANALOG_PERI_TOUCH_FSM_EN_S)
+#define LP_ANALOG_PERI_TOUCH_FSM_EN_V  0x00000001U
+#define LP_ANALOG_PERI_TOUCH_FSM_EN_S  29
+/** LP_ANALOG_PERI_TOUCH_START_EN : R/W; bitpos: [30]; default: 0;
  *  need_des
  */
-#define LP_ANA_TOUCH_START_EN    (BIT(30))
-#define LP_ANA_TOUCH_START_EN_M  (LP_ANA_TOUCH_START_EN_V << LP_ANA_TOUCH_START_EN_S)
-#define LP_ANA_TOUCH_START_EN_V  0x00000001U
-#define LP_ANA_TOUCH_START_EN_S  30
-/** LP_ANA_TOUCH_START_FORCE : R/W; bitpos: [31]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_START_EN    (BIT(30))
+#define LP_ANALOG_PERI_TOUCH_START_EN_M  (LP_ANALOG_PERI_TOUCH_START_EN_V << LP_ANALOG_PERI_TOUCH_START_EN_S)
+#define LP_ANALOG_PERI_TOUCH_START_EN_V  0x00000001U
+#define LP_ANALOG_PERI_TOUCH_START_EN_S  30
+/** LP_ANALOG_PERI_TOUCH_START_FORCE : R/W; bitpos: [31]; default: 0;
  *  need_des
  */
-#define LP_ANA_TOUCH_START_FORCE    (BIT(31))
-#define LP_ANA_TOUCH_START_FORCE_M  (LP_ANA_TOUCH_START_FORCE_V << LP_ANA_TOUCH_START_FORCE_S)
-#define LP_ANA_TOUCH_START_FORCE_V  0x00000001U
-#define LP_ANA_TOUCH_START_FORCE_S  31
+#define LP_ANALOG_PERI_TOUCH_START_FORCE    (BIT(31))
+#define LP_ANALOG_PERI_TOUCH_START_FORCE_M  (LP_ANALOG_PERI_TOUCH_START_FORCE_V << LP_ANALOG_PERI_TOUCH_START_FORCE_S)
+#define LP_ANALOG_PERI_TOUCH_START_FORCE_V  0x00000001U
+#define LP_ANALOG_PERI_TOUCH_START_FORCE_S  31
 
-/** LP_ANA_TOUCH_MUX1_REG register
+/** LP_ANALOG_PERI_TOUCH_MUX1_REG register
  *  need_des
  */
-#define LP_ANA_TOUCH_MUX1_REG (DR_REG_LP_ANA_BASE + 0x140)
-/** LP_ANA_TOUCH_START : R/W; bitpos: [14:0]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_MUX1_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x140)
+/** LP_ANALOG_PERI_TOUCH_START : R/W; bitpos: [14:0]; default: 0;
  *  need_des
  */
-#define LP_ANA_TOUCH_START    0x00007FFFU
-#define LP_ANA_TOUCH_START_M  (LP_ANA_TOUCH_START_V << LP_ANA_TOUCH_START_S)
-#define LP_ANA_TOUCH_START_V  0x00007FFFU
-#define LP_ANA_TOUCH_START_S  0
-/** LP_ANA_TOUCH_XPD : R/W; bitpos: [29:15]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_START    0x00007FFFU
+#define LP_ANALOG_PERI_TOUCH_START_M  (LP_ANALOG_PERI_TOUCH_START_V << LP_ANALOG_PERI_TOUCH_START_S)
+#define LP_ANALOG_PERI_TOUCH_START_V  0x00007FFFU
+#define LP_ANALOG_PERI_TOUCH_START_S  0
+/** LP_ANALOG_PERI_TOUCH_XPD : R/W; bitpos: [29:15]; default: 0;
  *  need_des
  */
-#define LP_ANA_TOUCH_XPD    0x00007FFFU
-#define LP_ANA_TOUCH_XPD_M  (LP_ANA_TOUCH_XPD_V << LP_ANA_TOUCH_XPD_S)
-#define LP_ANA_TOUCH_XPD_V  0x00007FFFU
-#define LP_ANA_TOUCH_XPD_S  15
+#define LP_ANALOG_PERI_TOUCH_XPD    0x00007FFFU
+#define LP_ANALOG_PERI_TOUCH_XPD_M  (LP_ANALOG_PERI_TOUCH_XPD_V << LP_ANALOG_PERI_TOUCH_XPD_S)
+#define LP_ANALOG_PERI_TOUCH_XPD_V  0x00007FFFU
+#define LP_ANALOG_PERI_TOUCH_XPD_S  15
 
-/** LP_ANA_TOUCH_PAD0_TH0_REG register
+/** LP_ANALOG_PERI_TOUCH_PAD0_TH0_REG register
  *  need_des
  */
-#define LP_ANA_TOUCH_PAD0_TH0_REG (DR_REG_LP_ANA_BASE + 0x144)
-/** LP_ANA_TOUCH_PAD0_TH0 : R/W; bitpos: [31:16]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_PAD0_TH0_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x144)
+/** LP_ANALOG_PERI_TOUCH_PAD0_TH0 : R/W; bitpos: [31:16]; default: 0;
  *  Reserved
  */
-#define LP_ANA_TOUCH_PAD0_TH0    0x0000FFFFU
-#define LP_ANA_TOUCH_PAD0_TH0_M  (LP_ANA_TOUCH_PAD0_TH0_V << LP_ANA_TOUCH_PAD0_TH0_S)
-#define LP_ANA_TOUCH_PAD0_TH0_V  0x0000FFFFU
-#define LP_ANA_TOUCH_PAD0_TH0_S  16
+#define LP_ANALOG_PERI_TOUCH_PAD0_TH0    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD0_TH0_M  (LP_ANALOG_PERI_TOUCH_PAD0_TH0_V << LP_ANALOG_PERI_TOUCH_PAD0_TH0_S)
+#define LP_ANALOG_PERI_TOUCH_PAD0_TH0_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD0_TH0_S  16
 
-/** LP_ANA_TOUCH_PAD0_TH1_REG register
+/** LP_ANALOG_PERI_TOUCH_PAD0_TH1_REG register
  *  need_des
  */
-#define LP_ANA_TOUCH_PAD0_TH1_REG (DR_REG_LP_ANA_BASE + 0x148)
-/** LP_ANA_TOUCH_PAD0_TH1 : R/W; bitpos: [31:16]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_PAD0_TH1_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x148)
+/** LP_ANALOG_PERI_TOUCH_PAD0_TH1 : R/W; bitpos: [31:16]; default: 0;
  *  Reserved
  */
-#define LP_ANA_TOUCH_PAD0_TH1    0x0000FFFFU
-#define LP_ANA_TOUCH_PAD0_TH1_M  (LP_ANA_TOUCH_PAD0_TH1_V << LP_ANA_TOUCH_PAD0_TH1_S)
-#define LP_ANA_TOUCH_PAD0_TH1_V  0x0000FFFFU
-#define LP_ANA_TOUCH_PAD0_TH1_S  16
+#define LP_ANALOG_PERI_TOUCH_PAD0_TH1    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD0_TH1_M  (LP_ANALOG_PERI_TOUCH_PAD0_TH1_V << LP_ANALOG_PERI_TOUCH_PAD0_TH1_S)
+#define LP_ANALOG_PERI_TOUCH_PAD0_TH1_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD0_TH1_S  16
 
-/** LP_ANA_TOUCH_PAD0_TH2_REG register
+/** LP_ANALOG_PERI_TOUCH_PAD0_TH2_REG register
  *  need_des
  */
-#define LP_ANA_TOUCH_PAD0_TH2_REG (DR_REG_LP_ANA_BASE + 0x14c)
-/** LP_ANA_TOUCH_PAD0_TH2 : R/W; bitpos: [31:16]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_PAD0_TH2_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x14c)
+/** LP_ANALOG_PERI_TOUCH_PAD0_TH2 : R/W; bitpos: [31:16]; default: 0;
  *  Reserved
  */
-#define LP_ANA_TOUCH_PAD0_TH2    0x0000FFFFU
-#define LP_ANA_TOUCH_PAD0_TH2_M  (LP_ANA_TOUCH_PAD0_TH2_V << LP_ANA_TOUCH_PAD0_TH2_S)
-#define LP_ANA_TOUCH_PAD0_TH2_V  0x0000FFFFU
-#define LP_ANA_TOUCH_PAD0_TH2_S  16
+#define LP_ANALOG_PERI_TOUCH_PAD0_TH2    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD0_TH2_M  (LP_ANALOG_PERI_TOUCH_PAD0_TH2_V << LP_ANALOG_PERI_TOUCH_PAD0_TH2_S)
+#define LP_ANALOG_PERI_TOUCH_PAD0_TH2_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD0_TH2_S  16
 
-/** LP_ANA_TOUCH_PAD1_TH0_REG register
+/** LP_ANALOG_PERI_TOUCH_PAD1_TH0_REG register
  *  need_des
  */
-#define LP_ANA_TOUCH_PAD1_TH0_REG (DR_REG_LP_ANA_BASE + 0x150)
-/** LP_ANA_TOUCH_PAD1_TH0 : R/W; bitpos: [31:16]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_PAD1_TH0_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x150)
+/** LP_ANALOG_PERI_TOUCH_PAD1_TH0 : R/W; bitpos: [31:16]; default: 0;
  *  Reserved
  */
-#define LP_ANA_TOUCH_PAD1_TH0    0x0000FFFFU
-#define LP_ANA_TOUCH_PAD1_TH0_M  (LP_ANA_TOUCH_PAD1_TH0_V << LP_ANA_TOUCH_PAD1_TH0_S)
-#define LP_ANA_TOUCH_PAD1_TH0_V  0x0000FFFFU
-#define LP_ANA_TOUCH_PAD1_TH0_S  16
+#define LP_ANALOG_PERI_TOUCH_PAD1_TH0    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD1_TH0_M  (LP_ANALOG_PERI_TOUCH_PAD1_TH0_V << LP_ANALOG_PERI_TOUCH_PAD1_TH0_S)
+#define LP_ANALOG_PERI_TOUCH_PAD1_TH0_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD1_TH0_S  16
 
-/** LP_ANA_TOUCH_PAD1_TH1_REG register
+/** LP_ANALOG_PERI_TOUCH_PAD1_TH1_REG register
  *  need_des
  */
-#define LP_ANA_TOUCH_PAD1_TH1_REG (DR_REG_LP_ANA_BASE + 0x154)
-/** LP_ANA_TOUCH_PAD1_TH1 : R/W; bitpos: [31:16]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_PAD1_TH1_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x154)
+/** LP_ANALOG_PERI_TOUCH_PAD1_TH1 : R/W; bitpos: [31:16]; default: 0;
  *  Reserved
  */
-#define LP_ANA_TOUCH_PAD1_TH1    0x0000FFFFU
-#define LP_ANA_TOUCH_PAD1_TH1_M  (LP_ANA_TOUCH_PAD1_TH1_V << LP_ANA_TOUCH_PAD1_TH1_S)
-#define LP_ANA_TOUCH_PAD1_TH1_V  0x0000FFFFU
-#define LP_ANA_TOUCH_PAD1_TH1_S  16
+#define LP_ANALOG_PERI_TOUCH_PAD1_TH1    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD1_TH1_M  (LP_ANALOG_PERI_TOUCH_PAD1_TH1_V << LP_ANALOG_PERI_TOUCH_PAD1_TH1_S)
+#define LP_ANALOG_PERI_TOUCH_PAD1_TH1_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD1_TH1_S  16
 
-/** LP_ANA_TOUCH_PAD1_TH2_REG register
+/** LP_ANALOG_PERI_TOUCH_PAD1_TH2_REG register
  *  need_des
  */
-#define LP_ANA_TOUCH_PAD1_TH2_REG (DR_REG_LP_ANA_BASE + 0x158)
-/** LP_ANA_TOUCH_PAD1_TH2 : R/W; bitpos: [31:16]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_PAD1_TH2_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x158)
+/** LP_ANALOG_PERI_TOUCH_PAD1_TH2 : R/W; bitpos: [31:16]; default: 0;
  *  Reserved
  */
-#define LP_ANA_TOUCH_PAD1_TH2    0x0000FFFFU
-#define LP_ANA_TOUCH_PAD1_TH2_M  (LP_ANA_TOUCH_PAD1_TH2_V << LP_ANA_TOUCH_PAD1_TH2_S)
-#define LP_ANA_TOUCH_PAD1_TH2_V  0x0000FFFFU
-#define LP_ANA_TOUCH_PAD1_TH2_S  16
+#define LP_ANALOG_PERI_TOUCH_PAD1_TH2    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD1_TH2_M  (LP_ANALOG_PERI_TOUCH_PAD1_TH2_V << LP_ANALOG_PERI_TOUCH_PAD1_TH2_S)
+#define LP_ANALOG_PERI_TOUCH_PAD1_TH2_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD1_TH2_S  16
 
-/** LP_ANA_TOUCH_PAD2_TH0_REG register
+/** LP_ANALOG_PERI_TOUCH_PAD2_TH0_REG register
  *  need_des
  */
-#define LP_ANA_TOUCH_PAD2_TH0_REG (DR_REG_LP_ANA_BASE + 0x15c)
-/** LP_ANA_TOUCH_PAD2_TH0 : R/W; bitpos: [31:16]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_PAD2_TH0_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x15c)
+/** LP_ANALOG_PERI_TOUCH_PAD2_TH0 : R/W; bitpos: [31:16]; default: 0;
  *  Reserved
  */
-#define LP_ANA_TOUCH_PAD2_TH0    0x0000FFFFU
-#define LP_ANA_TOUCH_PAD2_TH0_M  (LP_ANA_TOUCH_PAD2_TH0_V << LP_ANA_TOUCH_PAD2_TH0_S)
-#define LP_ANA_TOUCH_PAD2_TH0_V  0x0000FFFFU
-#define LP_ANA_TOUCH_PAD2_TH0_S  16
+#define LP_ANALOG_PERI_TOUCH_PAD2_TH0    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD2_TH0_M  (LP_ANALOG_PERI_TOUCH_PAD2_TH0_V << LP_ANALOG_PERI_TOUCH_PAD2_TH0_S)
+#define LP_ANALOG_PERI_TOUCH_PAD2_TH0_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD2_TH0_S  16
 
-/** LP_ANA_TOUCH_PAD2_TH1_REG register
+/** LP_ANALOG_PERI_TOUCH_PAD2_TH1_REG register
  *  need_des
  */
-#define LP_ANA_TOUCH_PAD2_TH1_REG (DR_REG_LP_ANA_BASE + 0x160)
-/** LP_ANA_TOUCH_PAD2_TH1 : R/W; bitpos: [31:16]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_PAD2_TH1_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x160)
+/** LP_ANALOG_PERI_TOUCH_PAD2_TH1 : R/W; bitpos: [31:16]; default: 0;
  *  Reserved
  */
-#define LP_ANA_TOUCH_PAD2_TH1    0x0000FFFFU
-#define LP_ANA_TOUCH_PAD2_TH1_M  (LP_ANA_TOUCH_PAD2_TH1_V << LP_ANA_TOUCH_PAD2_TH1_S)
-#define LP_ANA_TOUCH_PAD2_TH1_V  0x0000FFFFU
-#define LP_ANA_TOUCH_PAD2_TH1_S  16
+#define LP_ANALOG_PERI_TOUCH_PAD2_TH1    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD2_TH1_M  (LP_ANALOG_PERI_TOUCH_PAD2_TH1_V << LP_ANALOG_PERI_TOUCH_PAD2_TH1_S)
+#define LP_ANALOG_PERI_TOUCH_PAD2_TH1_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD2_TH1_S  16
 
-/** LP_ANA_TOUCH_PAD2_TH2_REG register
+/** LP_ANALOG_PERI_TOUCH_PAD2_TH2_REG register
  *  need_des
  */
-#define LP_ANA_TOUCH_PAD2_TH2_REG (DR_REG_LP_ANA_BASE + 0x164)
-/** LP_ANA_TOUCH_PAD2_TH2 : R/W; bitpos: [31:16]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_PAD2_TH2_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x164)
+/** LP_ANALOG_PERI_TOUCH_PAD2_TH2 : R/W; bitpos: [31:16]; default: 0;
  *  Reserved
  */
-#define LP_ANA_TOUCH_PAD2_TH2    0x0000FFFFU
-#define LP_ANA_TOUCH_PAD2_TH2_M  (LP_ANA_TOUCH_PAD2_TH2_V << LP_ANA_TOUCH_PAD2_TH2_S)
-#define LP_ANA_TOUCH_PAD2_TH2_V  0x0000FFFFU
-#define LP_ANA_TOUCH_PAD2_TH2_S  16
+#define LP_ANALOG_PERI_TOUCH_PAD2_TH2    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD2_TH2_M  (LP_ANALOG_PERI_TOUCH_PAD2_TH2_V << LP_ANALOG_PERI_TOUCH_PAD2_TH2_S)
+#define LP_ANALOG_PERI_TOUCH_PAD2_TH2_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD2_TH2_S  16
 
-/** LP_ANA_TOUCH_PAD3_TH0_REG register
+/** LP_ANALOG_PERI_TOUCH_PAD3_TH0_REG register
  *  need_des
  */
-#define LP_ANA_TOUCH_PAD3_TH0_REG (DR_REG_LP_ANA_BASE + 0x168)
-/** LP_ANA_TOUCH_PAD3_TH0 : R/W; bitpos: [31:16]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_PAD3_TH0_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x168)
+/** LP_ANALOG_PERI_TOUCH_PAD3_TH0 : R/W; bitpos: [31:16]; default: 0;
  *  Reserved
  */
-#define LP_ANA_TOUCH_PAD3_TH0    0x0000FFFFU
-#define LP_ANA_TOUCH_PAD3_TH0_M  (LP_ANA_TOUCH_PAD3_TH0_V << LP_ANA_TOUCH_PAD3_TH0_S)
-#define LP_ANA_TOUCH_PAD3_TH0_V  0x0000FFFFU
-#define LP_ANA_TOUCH_PAD3_TH0_S  16
+#define LP_ANALOG_PERI_TOUCH_PAD3_TH0    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD3_TH0_M  (LP_ANALOG_PERI_TOUCH_PAD3_TH0_V << LP_ANALOG_PERI_TOUCH_PAD3_TH0_S)
+#define LP_ANALOG_PERI_TOUCH_PAD3_TH0_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD3_TH0_S  16
 
-/** LP_ANA_TOUCH_PAD3_TH1_REG register
+/** LP_ANALOG_PERI_TOUCH_PAD3_TH1_REG register
  *  need_des
  */
-#define LP_ANA_TOUCH_PAD3_TH1_REG (DR_REG_LP_ANA_BASE + 0x16c)
-/** LP_ANA_TOUCH_PAD3_TH1 : R/W; bitpos: [31:16]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_PAD3_TH1_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x16c)
+/** LP_ANALOG_PERI_TOUCH_PAD3_TH1 : R/W; bitpos: [31:16]; default: 0;
  *  Reserved
  */
-#define LP_ANA_TOUCH_PAD3_TH1    0x0000FFFFU
-#define LP_ANA_TOUCH_PAD3_TH1_M  (LP_ANA_TOUCH_PAD3_TH1_V << LP_ANA_TOUCH_PAD3_TH1_S)
-#define LP_ANA_TOUCH_PAD3_TH1_V  0x0000FFFFU
-#define LP_ANA_TOUCH_PAD3_TH1_S  16
+#define LP_ANALOG_PERI_TOUCH_PAD3_TH1    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD3_TH1_M  (LP_ANALOG_PERI_TOUCH_PAD3_TH1_V << LP_ANALOG_PERI_TOUCH_PAD3_TH1_S)
+#define LP_ANALOG_PERI_TOUCH_PAD3_TH1_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD3_TH1_S  16
 
-/** LP_ANA_TOUCH_PAD3_TH2_REG register
+/** LP_ANALOG_PERI_TOUCH_PAD3_TH2_REG register
  *  need_des
  */
-#define LP_ANA_TOUCH_PAD3_TH2_REG (DR_REG_LP_ANA_BASE + 0x170)
-/** LP_ANA_TOUCH_PAD3_TH2 : R/W; bitpos: [31:16]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_PAD3_TH2_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x170)
+/** LP_ANALOG_PERI_TOUCH_PAD3_TH2 : R/W; bitpos: [31:16]; default: 0;
  *  Reserved
  */
-#define LP_ANA_TOUCH_PAD3_TH2    0x0000FFFFU
-#define LP_ANA_TOUCH_PAD3_TH2_M  (LP_ANA_TOUCH_PAD3_TH2_V << LP_ANA_TOUCH_PAD3_TH2_S)
-#define LP_ANA_TOUCH_PAD3_TH2_V  0x0000FFFFU
-#define LP_ANA_TOUCH_PAD3_TH2_S  16
+#define LP_ANALOG_PERI_TOUCH_PAD3_TH2    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD3_TH2_M  (LP_ANALOG_PERI_TOUCH_PAD3_TH2_V << LP_ANALOG_PERI_TOUCH_PAD3_TH2_S)
+#define LP_ANALOG_PERI_TOUCH_PAD3_TH2_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD3_TH2_S  16
 
-/** LP_ANA_TOUCH_PAD4_TH0_REG register
+/** LP_ANALOG_PERI_TOUCH_PAD4_TH0_REG register
  *  need_des
  */
-#define LP_ANA_TOUCH_PAD4_TH0_REG (DR_REG_LP_ANA_BASE + 0x174)
-/** LP_ANA_TOUCH_PAD4_TH0 : R/W; bitpos: [31:16]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_PAD4_TH0_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x174)
+/** LP_ANALOG_PERI_TOUCH_PAD4_TH0 : R/W; bitpos: [31:16]; default: 0;
  *  Reserved
  */
-#define LP_ANA_TOUCH_PAD4_TH0    0x0000FFFFU
-#define LP_ANA_TOUCH_PAD4_TH0_M  (LP_ANA_TOUCH_PAD4_TH0_V << LP_ANA_TOUCH_PAD4_TH0_S)
-#define LP_ANA_TOUCH_PAD4_TH0_V  0x0000FFFFU
-#define LP_ANA_TOUCH_PAD4_TH0_S  16
+#define LP_ANALOG_PERI_TOUCH_PAD4_TH0    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD4_TH0_M  (LP_ANALOG_PERI_TOUCH_PAD4_TH0_V << LP_ANALOG_PERI_TOUCH_PAD4_TH0_S)
+#define LP_ANALOG_PERI_TOUCH_PAD4_TH0_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD4_TH0_S  16
 
-/** LP_ANA_TOUCH_PAD4_TH1_REG register
+/** LP_ANALOG_PERI_TOUCH_PAD4_TH1_REG register
  *  need_des
  */
-#define LP_ANA_TOUCH_PAD4_TH1_REG (DR_REG_LP_ANA_BASE + 0x178)
-/** LP_ANA_TOUCH_PAD4_TH1 : R/W; bitpos: [31:16]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_PAD4_TH1_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x178)
+/** LP_ANALOG_PERI_TOUCH_PAD4_TH1 : R/W; bitpos: [31:16]; default: 0;
  *  Reserved
  */
-#define LP_ANA_TOUCH_PAD4_TH1    0x0000FFFFU
-#define LP_ANA_TOUCH_PAD4_TH1_M  (LP_ANA_TOUCH_PAD4_TH1_V << LP_ANA_TOUCH_PAD4_TH1_S)
-#define LP_ANA_TOUCH_PAD4_TH1_V  0x0000FFFFU
-#define LP_ANA_TOUCH_PAD4_TH1_S  16
+#define LP_ANALOG_PERI_TOUCH_PAD4_TH1    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD4_TH1_M  (LP_ANALOG_PERI_TOUCH_PAD4_TH1_V << LP_ANALOG_PERI_TOUCH_PAD4_TH1_S)
+#define LP_ANALOG_PERI_TOUCH_PAD4_TH1_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD4_TH1_S  16
 
-/** LP_ANA_TOUCH_PAD4_TH2_REG register
+/** LP_ANALOG_PERI_TOUCH_PAD4_TH2_REG register
  *  need_des
  */
-#define LP_ANA_TOUCH_PAD4_TH2_REG (DR_REG_LP_ANA_BASE + 0x17c)
-/** LP_ANA_TOUCH_PAD4_TH2 : R/W; bitpos: [31:16]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_PAD4_TH2_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x17c)
+/** LP_ANALOG_PERI_TOUCH_PAD4_TH2 : R/W; bitpos: [31:16]; default: 0;
  *  Reserved
  */
-#define LP_ANA_TOUCH_PAD4_TH2    0x0000FFFFU
-#define LP_ANA_TOUCH_PAD4_TH2_M  (LP_ANA_TOUCH_PAD4_TH2_V << LP_ANA_TOUCH_PAD4_TH2_S)
-#define LP_ANA_TOUCH_PAD4_TH2_V  0x0000FFFFU
-#define LP_ANA_TOUCH_PAD4_TH2_S  16
+#define LP_ANALOG_PERI_TOUCH_PAD4_TH2    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD4_TH2_M  (LP_ANALOG_PERI_TOUCH_PAD4_TH2_V << LP_ANALOG_PERI_TOUCH_PAD4_TH2_S)
+#define LP_ANALOG_PERI_TOUCH_PAD4_TH2_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD4_TH2_S  16
 
-/** LP_ANA_TOUCH_PAD5_TH0_REG register
+/** LP_ANALOG_PERI_TOUCH_PAD5_TH0_REG register
  *  need_des
  */
-#define LP_ANA_TOUCH_PAD5_TH0_REG (DR_REG_LP_ANA_BASE + 0x180)
-/** LP_ANA_TOUCH_PAD5_TH0 : R/W; bitpos: [31:16]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_PAD5_TH0_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x180)
+/** LP_ANALOG_PERI_TOUCH_PAD5_TH0 : R/W; bitpos: [31:16]; default: 0;
  *  Reserved
  */
-#define LP_ANA_TOUCH_PAD5_TH0    0x0000FFFFU
-#define LP_ANA_TOUCH_PAD5_TH0_M  (LP_ANA_TOUCH_PAD5_TH0_V << LP_ANA_TOUCH_PAD5_TH0_S)
-#define LP_ANA_TOUCH_PAD5_TH0_V  0x0000FFFFU
-#define LP_ANA_TOUCH_PAD5_TH0_S  16
+#define LP_ANALOG_PERI_TOUCH_PAD5_TH0    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD5_TH0_M  (LP_ANALOG_PERI_TOUCH_PAD5_TH0_V << LP_ANALOG_PERI_TOUCH_PAD5_TH0_S)
+#define LP_ANALOG_PERI_TOUCH_PAD5_TH0_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD5_TH0_S  16
 
-/** LP_ANA_TOUCH_PAD5_TH1_REG register
+/** LP_ANALOG_PERI_TOUCH_PAD5_TH1_REG register
  *  need_des
  */
-#define LP_ANA_TOUCH_PAD5_TH1_REG (DR_REG_LP_ANA_BASE + 0x184)
-/** LP_ANA_TOUCH_PAD5_TH1 : R/W; bitpos: [31:16]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_PAD5_TH1_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x184)
+/** LP_ANALOG_PERI_TOUCH_PAD5_TH1 : R/W; bitpos: [31:16]; default: 0;
  *  Reserved
  */
-#define LP_ANA_TOUCH_PAD5_TH1    0x0000FFFFU
-#define LP_ANA_TOUCH_PAD5_TH1_M  (LP_ANA_TOUCH_PAD5_TH1_V << LP_ANA_TOUCH_PAD5_TH1_S)
-#define LP_ANA_TOUCH_PAD5_TH1_V  0x0000FFFFU
-#define LP_ANA_TOUCH_PAD5_TH1_S  16
+#define LP_ANALOG_PERI_TOUCH_PAD5_TH1    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD5_TH1_M  (LP_ANALOG_PERI_TOUCH_PAD5_TH1_V << LP_ANALOG_PERI_TOUCH_PAD5_TH1_S)
+#define LP_ANALOG_PERI_TOUCH_PAD5_TH1_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD5_TH1_S  16
 
-/** LP_ANA_TOUCH_PAD5_TH2_REG register
+/** LP_ANALOG_PERI_TOUCH_PAD5_TH2_REG register
  *  need_des
  */
-#define LP_ANA_TOUCH_PAD5_TH2_REG (DR_REG_LP_ANA_BASE + 0x188)
-/** LP_ANA_TOUCH_PAD5_TH2 : R/W; bitpos: [31:16]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_PAD5_TH2_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x188)
+/** LP_ANALOG_PERI_TOUCH_PAD5_TH2 : R/W; bitpos: [31:16]; default: 0;
  *  Reserved
  */
-#define LP_ANA_TOUCH_PAD5_TH2    0x0000FFFFU
-#define LP_ANA_TOUCH_PAD5_TH2_M  (LP_ANA_TOUCH_PAD5_TH2_V << LP_ANA_TOUCH_PAD5_TH2_S)
-#define LP_ANA_TOUCH_PAD5_TH2_V  0x0000FFFFU
-#define LP_ANA_TOUCH_PAD5_TH2_S  16
+#define LP_ANALOG_PERI_TOUCH_PAD5_TH2    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD5_TH2_M  (LP_ANALOG_PERI_TOUCH_PAD5_TH2_V << LP_ANALOG_PERI_TOUCH_PAD5_TH2_S)
+#define LP_ANALOG_PERI_TOUCH_PAD5_TH2_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD5_TH2_S  16
 
-/** LP_ANA_TOUCH_PAD6_TH0_REG register
+/** LP_ANALOG_PERI_TOUCH_PAD6_TH0_REG register
  *  need_des
  */
-#define LP_ANA_TOUCH_PAD6_TH0_REG (DR_REG_LP_ANA_BASE + 0x18c)
-/** LP_ANA_TOUCH_PAD6_TH0 : R/W; bitpos: [31:16]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_PAD6_TH0_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x18c)
+/** LP_ANALOG_PERI_TOUCH_PAD6_TH0 : R/W; bitpos: [31:16]; default: 0;
  *  Reserved
  */
-#define LP_ANA_TOUCH_PAD6_TH0    0x0000FFFFU
-#define LP_ANA_TOUCH_PAD6_TH0_M  (LP_ANA_TOUCH_PAD6_TH0_V << LP_ANA_TOUCH_PAD6_TH0_S)
-#define LP_ANA_TOUCH_PAD6_TH0_V  0x0000FFFFU
-#define LP_ANA_TOUCH_PAD6_TH0_S  16
+#define LP_ANALOG_PERI_TOUCH_PAD6_TH0    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD6_TH0_M  (LP_ANALOG_PERI_TOUCH_PAD6_TH0_V << LP_ANALOG_PERI_TOUCH_PAD6_TH0_S)
+#define LP_ANALOG_PERI_TOUCH_PAD6_TH0_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD6_TH0_S  16
 
-/** LP_ANA_TOUCH_PAD6_TH1_REG register
+/** LP_ANALOG_PERI_TOUCH_PAD6_TH1_REG register
  *  need_des
  */
-#define LP_ANA_TOUCH_PAD6_TH1_REG (DR_REG_LP_ANA_BASE + 0x190)
-/** LP_ANA_TOUCH_PAD6_TH1 : R/W; bitpos: [31:16]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_PAD6_TH1_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x190)
+/** LP_ANALOG_PERI_TOUCH_PAD6_TH1 : R/W; bitpos: [31:16]; default: 0;
  *  Reserved
  */
-#define LP_ANA_TOUCH_PAD6_TH1    0x0000FFFFU
-#define LP_ANA_TOUCH_PAD6_TH1_M  (LP_ANA_TOUCH_PAD6_TH1_V << LP_ANA_TOUCH_PAD6_TH1_S)
-#define LP_ANA_TOUCH_PAD6_TH1_V  0x0000FFFFU
-#define LP_ANA_TOUCH_PAD6_TH1_S  16
+#define LP_ANALOG_PERI_TOUCH_PAD6_TH1    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD6_TH1_M  (LP_ANALOG_PERI_TOUCH_PAD6_TH1_V << LP_ANALOG_PERI_TOUCH_PAD6_TH1_S)
+#define LP_ANALOG_PERI_TOUCH_PAD6_TH1_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD6_TH1_S  16
 
-/** LP_ANA_TOUCH_PAD6_TH2_REG register
+/** LP_ANALOG_PERI_TOUCH_PAD6_TH2_REG register
  *  need_des
  */
-#define LP_ANA_TOUCH_PAD6_TH2_REG (DR_REG_LP_ANA_BASE + 0x194)
-/** LP_ANA_TOUCH_PAD6_TH2 : R/W; bitpos: [31:16]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_PAD6_TH2_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x194)
+/** LP_ANALOG_PERI_TOUCH_PAD6_TH2 : R/W; bitpos: [31:16]; default: 0;
  *  Reserved
  */
-#define LP_ANA_TOUCH_PAD6_TH2    0x0000FFFFU
-#define LP_ANA_TOUCH_PAD6_TH2_M  (LP_ANA_TOUCH_PAD6_TH2_V << LP_ANA_TOUCH_PAD6_TH2_S)
-#define LP_ANA_TOUCH_PAD6_TH2_V  0x0000FFFFU
-#define LP_ANA_TOUCH_PAD6_TH2_S  16
+#define LP_ANALOG_PERI_TOUCH_PAD6_TH2    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD6_TH2_M  (LP_ANALOG_PERI_TOUCH_PAD6_TH2_V << LP_ANALOG_PERI_TOUCH_PAD6_TH2_S)
+#define LP_ANALOG_PERI_TOUCH_PAD6_TH2_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD6_TH2_S  16
 
-/** LP_ANA_TOUCH_PAD7_TH0_REG register
+/** LP_ANALOG_PERI_TOUCH_PAD7_TH0_REG register
  *  need_des
  */
-#define LP_ANA_TOUCH_PAD7_TH0_REG (DR_REG_LP_ANA_BASE + 0x198)
-/** LP_ANA_TOUCH_PAD7_TH0 : R/W; bitpos: [31:16]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_PAD7_TH0_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x198)
+/** LP_ANALOG_PERI_TOUCH_PAD7_TH0 : R/W; bitpos: [31:16]; default: 0;
  *  Reserved
  */
-#define LP_ANA_TOUCH_PAD7_TH0    0x0000FFFFU
-#define LP_ANA_TOUCH_PAD7_TH0_M  (LP_ANA_TOUCH_PAD7_TH0_V << LP_ANA_TOUCH_PAD7_TH0_S)
-#define LP_ANA_TOUCH_PAD7_TH0_V  0x0000FFFFU
-#define LP_ANA_TOUCH_PAD7_TH0_S  16
+#define LP_ANALOG_PERI_TOUCH_PAD7_TH0    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD7_TH0_M  (LP_ANALOG_PERI_TOUCH_PAD7_TH0_V << LP_ANALOG_PERI_TOUCH_PAD7_TH0_S)
+#define LP_ANALOG_PERI_TOUCH_PAD7_TH0_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD7_TH0_S  16
 
-/** LP_ANA_TOUCH_PAD7_TH1_REG register
+/** LP_ANALOG_PERI_TOUCH_PAD7_TH1_REG register
  *  need_des
  */
-#define LP_ANA_TOUCH_PAD7_TH1_REG (DR_REG_LP_ANA_BASE + 0x19c)
-/** LP_ANA_TOUCH_PAD7_TH1 : R/W; bitpos: [31:16]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_PAD7_TH1_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x19c)
+/** LP_ANALOG_PERI_TOUCH_PAD7_TH1 : R/W; bitpos: [31:16]; default: 0;
  *  Reserved
  */
-#define LP_ANA_TOUCH_PAD7_TH1    0x0000FFFFU
-#define LP_ANA_TOUCH_PAD7_TH1_M  (LP_ANA_TOUCH_PAD7_TH1_V << LP_ANA_TOUCH_PAD7_TH1_S)
-#define LP_ANA_TOUCH_PAD7_TH1_V  0x0000FFFFU
-#define LP_ANA_TOUCH_PAD7_TH1_S  16
+#define LP_ANALOG_PERI_TOUCH_PAD7_TH1    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD7_TH1_M  (LP_ANALOG_PERI_TOUCH_PAD7_TH1_V << LP_ANALOG_PERI_TOUCH_PAD7_TH1_S)
+#define LP_ANALOG_PERI_TOUCH_PAD7_TH1_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD7_TH1_S  16
 
-/** LP_ANA_TOUCH_PAD7_TH2_REG register
+/** LP_ANALOG_PERI_TOUCH_PAD7_TH2_REG register
  *  need_des
  */
-#define LP_ANA_TOUCH_PAD7_TH2_REG (DR_REG_LP_ANA_BASE + 0x1a0)
-/** LP_ANA_TOUCH_PAD7_TH2 : R/W; bitpos: [31:16]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_PAD7_TH2_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x1a0)
+/** LP_ANALOG_PERI_TOUCH_PAD7_TH2 : R/W; bitpos: [31:16]; default: 0;
  *  Reserved
  */
-#define LP_ANA_TOUCH_PAD7_TH2    0x0000FFFFU
-#define LP_ANA_TOUCH_PAD7_TH2_M  (LP_ANA_TOUCH_PAD7_TH2_V << LP_ANA_TOUCH_PAD7_TH2_S)
-#define LP_ANA_TOUCH_PAD7_TH2_V  0x0000FFFFU
-#define LP_ANA_TOUCH_PAD7_TH2_S  16
+#define LP_ANALOG_PERI_TOUCH_PAD7_TH2    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD7_TH2_M  (LP_ANALOG_PERI_TOUCH_PAD7_TH2_V << LP_ANALOG_PERI_TOUCH_PAD7_TH2_S)
+#define LP_ANALOG_PERI_TOUCH_PAD7_TH2_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD7_TH2_S  16
 
-/** LP_ANA_TOUCH_PAD8_TH0_REG register
+/** LP_ANALOG_PERI_TOUCH_PAD8_TH0_REG register
  *  need_des
  */
-#define LP_ANA_TOUCH_PAD8_TH0_REG (DR_REG_LP_ANA_BASE + 0x1a4)
-/** LP_ANA_TOUCH_PAD8_TH0 : R/W; bitpos: [31:16]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_PAD8_TH0_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x1a4)
+/** LP_ANALOG_PERI_TOUCH_PAD8_TH0 : R/W; bitpos: [31:16]; default: 0;
  *  Reserved
  */
-#define LP_ANA_TOUCH_PAD8_TH0    0x0000FFFFU
-#define LP_ANA_TOUCH_PAD8_TH0_M  (LP_ANA_TOUCH_PAD8_TH0_V << LP_ANA_TOUCH_PAD8_TH0_S)
-#define LP_ANA_TOUCH_PAD8_TH0_V  0x0000FFFFU
-#define LP_ANA_TOUCH_PAD8_TH0_S  16
+#define LP_ANALOG_PERI_TOUCH_PAD8_TH0    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD8_TH0_M  (LP_ANALOG_PERI_TOUCH_PAD8_TH0_V << LP_ANALOG_PERI_TOUCH_PAD8_TH0_S)
+#define LP_ANALOG_PERI_TOUCH_PAD8_TH0_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD8_TH0_S  16
 
-/** LP_ANA_TOUCH_PAD8_TH1_REG register
+/** LP_ANALOG_PERI_TOUCH_PAD8_TH1_REG register
  *  need_des
  */
-#define LP_ANA_TOUCH_PAD8_TH1_REG (DR_REG_LP_ANA_BASE + 0x1a8)
-/** LP_ANA_TOUCH_PAD8_TH1 : R/W; bitpos: [31:16]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_PAD8_TH1_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x1a8)
+/** LP_ANALOG_PERI_TOUCH_PAD8_TH1 : R/W; bitpos: [31:16]; default: 0;
  *  Reserved
  */
-#define LP_ANA_TOUCH_PAD8_TH1    0x0000FFFFU
-#define LP_ANA_TOUCH_PAD8_TH1_M  (LP_ANA_TOUCH_PAD8_TH1_V << LP_ANA_TOUCH_PAD8_TH1_S)
-#define LP_ANA_TOUCH_PAD8_TH1_V  0x0000FFFFU
-#define LP_ANA_TOUCH_PAD8_TH1_S  16
+#define LP_ANALOG_PERI_TOUCH_PAD8_TH1    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD8_TH1_M  (LP_ANALOG_PERI_TOUCH_PAD8_TH1_V << LP_ANALOG_PERI_TOUCH_PAD8_TH1_S)
+#define LP_ANALOG_PERI_TOUCH_PAD8_TH1_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD8_TH1_S  16
 
-/** LP_ANA_TOUCH_PAD8_TH2_REG register
+/** LP_ANALOG_PERI_TOUCH_PAD8_TH2_REG register
  *  need_des
  */
-#define LP_ANA_TOUCH_PAD8_TH2_REG (DR_REG_LP_ANA_BASE + 0x1ac)
-/** LP_ANA_TOUCH_PAD8_TH2 : R/W; bitpos: [31:16]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_PAD8_TH2_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x1ac)
+/** LP_ANALOG_PERI_TOUCH_PAD8_TH2 : R/W; bitpos: [31:16]; default: 0;
  *  Reserved
  */
-#define LP_ANA_TOUCH_PAD8_TH2    0x0000FFFFU
-#define LP_ANA_TOUCH_PAD8_TH2_M  (LP_ANA_TOUCH_PAD8_TH2_V << LP_ANA_TOUCH_PAD8_TH2_S)
-#define LP_ANA_TOUCH_PAD8_TH2_V  0x0000FFFFU
-#define LP_ANA_TOUCH_PAD8_TH2_S  16
+#define LP_ANALOG_PERI_TOUCH_PAD8_TH2    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD8_TH2_M  (LP_ANALOG_PERI_TOUCH_PAD8_TH2_V << LP_ANALOG_PERI_TOUCH_PAD8_TH2_S)
+#define LP_ANALOG_PERI_TOUCH_PAD8_TH2_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD8_TH2_S  16
 
-/** LP_ANA_TOUCH_PAD9_TH0_REG register
+/** LP_ANALOG_PERI_TOUCH_PAD9_TH0_REG register
  *  need_des
  */
-#define LP_ANA_TOUCH_PAD9_TH0_REG (DR_REG_LP_ANA_BASE + 0x1b0)
-/** LP_ANA_TOUCH_PAD9_TH0 : R/W; bitpos: [31:16]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_PAD9_TH0_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x1b0)
+/** LP_ANALOG_PERI_TOUCH_PAD9_TH0 : R/W; bitpos: [31:16]; default: 0;
  *  Reserved
  */
-#define LP_ANA_TOUCH_PAD9_TH0    0x0000FFFFU
-#define LP_ANA_TOUCH_PAD9_TH0_M  (LP_ANA_TOUCH_PAD9_TH0_V << LP_ANA_TOUCH_PAD9_TH0_S)
-#define LP_ANA_TOUCH_PAD9_TH0_V  0x0000FFFFU
-#define LP_ANA_TOUCH_PAD9_TH0_S  16
+#define LP_ANALOG_PERI_TOUCH_PAD9_TH0    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD9_TH0_M  (LP_ANALOG_PERI_TOUCH_PAD9_TH0_V << LP_ANALOG_PERI_TOUCH_PAD9_TH0_S)
+#define LP_ANALOG_PERI_TOUCH_PAD9_TH0_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD9_TH0_S  16
 
-/** LP_ANA_TOUCH_PAD9_TH1_REG register
+/** LP_ANALOG_PERI_TOUCH_PAD9_TH1_REG register
  *  need_des
  */
-#define LP_ANA_TOUCH_PAD9_TH1_REG (DR_REG_LP_ANA_BASE + 0x1b4)
-/** LP_ANA_TOUCH_PAD9_TH1 : R/W; bitpos: [31:16]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_PAD9_TH1_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x1b4)
+/** LP_ANALOG_PERI_TOUCH_PAD9_TH1 : R/W; bitpos: [31:16]; default: 0;
  *  Reserved
  */
-#define LP_ANA_TOUCH_PAD9_TH1    0x0000FFFFU
-#define LP_ANA_TOUCH_PAD9_TH1_M  (LP_ANA_TOUCH_PAD9_TH1_V << LP_ANA_TOUCH_PAD9_TH1_S)
-#define LP_ANA_TOUCH_PAD9_TH1_V  0x0000FFFFU
-#define LP_ANA_TOUCH_PAD9_TH1_S  16
+#define LP_ANALOG_PERI_TOUCH_PAD9_TH1    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD9_TH1_M  (LP_ANALOG_PERI_TOUCH_PAD9_TH1_V << LP_ANALOG_PERI_TOUCH_PAD9_TH1_S)
+#define LP_ANALOG_PERI_TOUCH_PAD9_TH1_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD9_TH1_S  16
 
-/** LP_ANA_TOUCH_PAD9_TH2_REG register
+/** LP_ANALOG_PERI_TOUCH_PAD9_TH2_REG register
  *  need_des
  */
-#define LP_ANA_TOUCH_PAD9_TH2_REG (DR_REG_LP_ANA_BASE + 0x1b8)
-/** LP_ANA_TOUCH_PAD9_TH2 : R/W; bitpos: [31:16]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_PAD9_TH2_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x1b8)
+/** LP_ANALOG_PERI_TOUCH_PAD9_TH2 : R/W; bitpos: [31:16]; default: 0;
  *  Reserved
  */
-#define LP_ANA_TOUCH_PAD9_TH2    0x0000FFFFU
-#define LP_ANA_TOUCH_PAD9_TH2_M  (LP_ANA_TOUCH_PAD9_TH2_V << LP_ANA_TOUCH_PAD9_TH2_S)
-#define LP_ANA_TOUCH_PAD9_TH2_V  0x0000FFFFU
-#define LP_ANA_TOUCH_PAD9_TH2_S  16
+#define LP_ANALOG_PERI_TOUCH_PAD9_TH2    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD9_TH2_M  (LP_ANALOG_PERI_TOUCH_PAD9_TH2_V << LP_ANALOG_PERI_TOUCH_PAD9_TH2_S)
+#define LP_ANALOG_PERI_TOUCH_PAD9_TH2_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD9_TH2_S  16
 
-/** LP_ANA_TOUCH_PAD10_TH0_REG register
+/** LP_ANALOG_PERI_TOUCH_PAD10_TH0_REG register
  *  need_des
  */
-#define LP_ANA_TOUCH_PAD10_TH0_REG (DR_REG_LP_ANA_BASE + 0x1bc)
-/** LP_ANA_TOUCH_PAD10_TH0 : R/W; bitpos: [31:16]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_PAD10_TH0_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x1bc)
+/** LP_ANALOG_PERI_TOUCH_PAD10_TH0 : R/W; bitpos: [31:16]; default: 0;
  *  Reserved
  */
-#define LP_ANA_TOUCH_PAD10_TH0    0x0000FFFFU
-#define LP_ANA_TOUCH_PAD10_TH0_M  (LP_ANA_TOUCH_PAD10_TH0_V << LP_ANA_TOUCH_PAD10_TH0_S)
-#define LP_ANA_TOUCH_PAD10_TH0_V  0x0000FFFFU
-#define LP_ANA_TOUCH_PAD10_TH0_S  16
+#define LP_ANALOG_PERI_TOUCH_PAD10_TH0    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD10_TH0_M  (LP_ANALOG_PERI_TOUCH_PAD10_TH0_V << LP_ANALOG_PERI_TOUCH_PAD10_TH0_S)
+#define LP_ANALOG_PERI_TOUCH_PAD10_TH0_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD10_TH0_S  16
 
-/** LP_ANA_TOUCH_PAD10_TH1_REG register
+/** LP_ANALOG_PERI_TOUCH_PAD10_TH1_REG register
  *  need_des
  */
-#define LP_ANA_TOUCH_PAD10_TH1_REG (DR_REG_LP_ANA_BASE + 0x1c0)
-/** LP_ANA_TOUCH_PAD10_TH1 : R/W; bitpos: [31:16]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_PAD10_TH1_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x1c0)
+/** LP_ANALOG_PERI_TOUCH_PAD10_TH1 : R/W; bitpos: [31:16]; default: 0;
  *  Reserved
  */
-#define LP_ANA_TOUCH_PAD10_TH1    0x0000FFFFU
-#define LP_ANA_TOUCH_PAD10_TH1_M  (LP_ANA_TOUCH_PAD10_TH1_V << LP_ANA_TOUCH_PAD10_TH1_S)
-#define LP_ANA_TOUCH_PAD10_TH1_V  0x0000FFFFU
-#define LP_ANA_TOUCH_PAD10_TH1_S  16
+#define LP_ANALOG_PERI_TOUCH_PAD10_TH1    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD10_TH1_M  (LP_ANALOG_PERI_TOUCH_PAD10_TH1_V << LP_ANALOG_PERI_TOUCH_PAD10_TH1_S)
+#define LP_ANALOG_PERI_TOUCH_PAD10_TH1_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD10_TH1_S  16
 
-/** LP_ANA_TOUCH_PAD10_TH2_REG register
+/** LP_ANALOG_PERI_TOUCH_PAD10_TH2_REG register
  *  need_des
  */
-#define LP_ANA_TOUCH_PAD10_TH2_REG (DR_REG_LP_ANA_BASE + 0x1c4)
-/** LP_ANA_TOUCH_PAD10_TH2 : R/W; bitpos: [31:16]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_PAD10_TH2_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x1c4)
+/** LP_ANALOG_PERI_TOUCH_PAD10_TH2 : R/W; bitpos: [31:16]; default: 0;
  *  Reserved
  */
-#define LP_ANA_TOUCH_PAD10_TH2    0x0000FFFFU
-#define LP_ANA_TOUCH_PAD10_TH2_M  (LP_ANA_TOUCH_PAD10_TH2_V << LP_ANA_TOUCH_PAD10_TH2_S)
-#define LP_ANA_TOUCH_PAD10_TH2_V  0x0000FFFFU
-#define LP_ANA_TOUCH_PAD10_TH2_S  16
+#define LP_ANALOG_PERI_TOUCH_PAD10_TH2    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD10_TH2_M  (LP_ANALOG_PERI_TOUCH_PAD10_TH2_V << LP_ANALOG_PERI_TOUCH_PAD10_TH2_S)
+#define LP_ANALOG_PERI_TOUCH_PAD10_TH2_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD10_TH2_S  16
 
-/** LP_ANA_TOUCH_PAD11_TH0_REG register
+/** LP_ANALOG_PERI_TOUCH_PAD11_TH0_REG register
  *  need_des
  */
-#define LP_ANA_TOUCH_PAD11_TH0_REG (DR_REG_LP_ANA_BASE + 0x1c8)
-/** LP_ANA_TOUCH_PAD11_TH0 : R/W; bitpos: [31:16]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_PAD11_TH0_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x1c8)
+/** LP_ANALOG_PERI_TOUCH_PAD11_TH0 : R/W; bitpos: [31:16]; default: 0;
  *  Reserved
  */
-#define LP_ANA_TOUCH_PAD11_TH0    0x0000FFFFU
-#define LP_ANA_TOUCH_PAD11_TH0_M  (LP_ANA_TOUCH_PAD11_TH0_V << LP_ANA_TOUCH_PAD11_TH0_S)
-#define LP_ANA_TOUCH_PAD11_TH0_V  0x0000FFFFU
-#define LP_ANA_TOUCH_PAD11_TH0_S  16
+#define LP_ANALOG_PERI_TOUCH_PAD11_TH0    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD11_TH0_M  (LP_ANALOG_PERI_TOUCH_PAD11_TH0_V << LP_ANALOG_PERI_TOUCH_PAD11_TH0_S)
+#define LP_ANALOG_PERI_TOUCH_PAD11_TH0_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD11_TH0_S  16
 
-/** LP_ANA_TOUCH_PAD11_TH1_REG register
+/** LP_ANALOG_PERI_TOUCH_PAD11_TH1_REG register
  *  need_des
  */
-#define LP_ANA_TOUCH_PAD11_TH1_REG (DR_REG_LP_ANA_BASE + 0x1cc)
-/** LP_ANA_TOUCH_PAD11_TH1 : R/W; bitpos: [31:16]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_PAD11_TH1_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x1cc)
+/** LP_ANALOG_PERI_TOUCH_PAD11_TH1 : R/W; bitpos: [31:16]; default: 0;
  *  Reserved
  */
-#define LP_ANA_TOUCH_PAD11_TH1    0x0000FFFFU
-#define LP_ANA_TOUCH_PAD11_TH1_M  (LP_ANA_TOUCH_PAD11_TH1_V << LP_ANA_TOUCH_PAD11_TH1_S)
-#define LP_ANA_TOUCH_PAD11_TH1_V  0x0000FFFFU
-#define LP_ANA_TOUCH_PAD11_TH1_S  16
+#define LP_ANALOG_PERI_TOUCH_PAD11_TH1    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD11_TH1_M  (LP_ANALOG_PERI_TOUCH_PAD11_TH1_V << LP_ANALOG_PERI_TOUCH_PAD11_TH1_S)
+#define LP_ANALOG_PERI_TOUCH_PAD11_TH1_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD11_TH1_S  16
 
-/** LP_ANA_TOUCH_PAD11_TH2_REG register
+/** LP_ANALOG_PERI_TOUCH_PAD11_TH2_REG register
  *  need_des
  */
-#define LP_ANA_TOUCH_PAD11_TH2_REG (DR_REG_LP_ANA_BASE + 0x1d0)
-/** LP_ANA_TOUCH_PAD11_TH2 : R/W; bitpos: [31:16]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_PAD11_TH2_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x1d0)
+/** LP_ANALOG_PERI_TOUCH_PAD11_TH2 : R/W; bitpos: [31:16]; default: 0;
  *  Reserved
  */
-#define LP_ANA_TOUCH_PAD11_TH2    0x0000FFFFU
-#define LP_ANA_TOUCH_PAD11_TH2_M  (LP_ANA_TOUCH_PAD11_TH2_V << LP_ANA_TOUCH_PAD11_TH2_S)
-#define LP_ANA_TOUCH_PAD11_TH2_V  0x0000FFFFU
-#define LP_ANA_TOUCH_PAD11_TH2_S  16
+#define LP_ANALOG_PERI_TOUCH_PAD11_TH2    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD11_TH2_M  (LP_ANALOG_PERI_TOUCH_PAD11_TH2_V << LP_ANALOG_PERI_TOUCH_PAD11_TH2_S)
+#define LP_ANALOG_PERI_TOUCH_PAD11_TH2_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD11_TH2_S  16
 
-/** LP_ANA_TOUCH_PAD12_TH0_REG register
+/** LP_ANALOG_PERI_TOUCH_PAD12_TH0_REG register
  *  need_des
  */
-#define LP_ANA_TOUCH_PAD12_TH0_REG (DR_REG_LP_ANA_BASE + 0x1d4)
-/** LP_ANA_TOUCH_PAD12_TH0 : R/W; bitpos: [31:16]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_PAD12_TH0_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x1d4)
+/** LP_ANALOG_PERI_TOUCH_PAD12_TH0 : R/W; bitpos: [31:16]; default: 0;
  *  Reserved
  */
-#define LP_ANA_TOUCH_PAD12_TH0    0x0000FFFFU
-#define LP_ANA_TOUCH_PAD12_TH0_M  (LP_ANA_TOUCH_PAD12_TH0_V << LP_ANA_TOUCH_PAD12_TH0_S)
-#define LP_ANA_TOUCH_PAD12_TH0_V  0x0000FFFFU
-#define LP_ANA_TOUCH_PAD12_TH0_S  16
+#define LP_ANALOG_PERI_TOUCH_PAD12_TH0    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD12_TH0_M  (LP_ANALOG_PERI_TOUCH_PAD12_TH0_V << LP_ANALOG_PERI_TOUCH_PAD12_TH0_S)
+#define LP_ANALOG_PERI_TOUCH_PAD12_TH0_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD12_TH0_S  16
 
-/** LP_ANA_TOUCH_PAD12_TH1_REG register
+/** LP_ANALOG_PERI_TOUCH_PAD12_TH1_REG register
  *  need_des
  */
-#define LP_ANA_TOUCH_PAD12_TH1_REG (DR_REG_LP_ANA_BASE + 0x1d8)
-/** LP_ANA_TOUCH_PAD12_TH1 : R/W; bitpos: [31:16]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_PAD12_TH1_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x1d8)
+/** LP_ANALOG_PERI_TOUCH_PAD12_TH1 : R/W; bitpos: [31:16]; default: 0;
  *  Reserved
  */
-#define LP_ANA_TOUCH_PAD12_TH1    0x0000FFFFU
-#define LP_ANA_TOUCH_PAD12_TH1_M  (LP_ANA_TOUCH_PAD12_TH1_V << LP_ANA_TOUCH_PAD12_TH1_S)
-#define LP_ANA_TOUCH_PAD12_TH1_V  0x0000FFFFU
-#define LP_ANA_TOUCH_PAD12_TH1_S  16
+#define LP_ANALOG_PERI_TOUCH_PAD12_TH1    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD12_TH1_M  (LP_ANALOG_PERI_TOUCH_PAD12_TH1_V << LP_ANALOG_PERI_TOUCH_PAD12_TH1_S)
+#define LP_ANALOG_PERI_TOUCH_PAD12_TH1_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD12_TH1_S  16
 
-/** LP_ANA_TOUCH_PAD12_TH2_REG register
+/** LP_ANALOG_PERI_TOUCH_PAD12_TH2_REG register
  *  need_des
  */
-#define LP_ANA_TOUCH_PAD12_TH2_REG (DR_REG_LP_ANA_BASE + 0x1dc)
-/** LP_ANA_TOUCH_PAD12_TH2 : R/W; bitpos: [31:16]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_PAD12_TH2_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x1dc)
+/** LP_ANALOG_PERI_TOUCH_PAD12_TH2 : R/W; bitpos: [31:16]; default: 0;
  *  Reserved
  */
-#define LP_ANA_TOUCH_PAD12_TH2    0x0000FFFFU
-#define LP_ANA_TOUCH_PAD12_TH2_M  (LP_ANA_TOUCH_PAD12_TH2_V << LP_ANA_TOUCH_PAD12_TH2_S)
-#define LP_ANA_TOUCH_PAD12_TH2_V  0x0000FFFFU
-#define LP_ANA_TOUCH_PAD12_TH2_S  16
+#define LP_ANALOG_PERI_TOUCH_PAD12_TH2    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD12_TH2_M  (LP_ANALOG_PERI_TOUCH_PAD12_TH2_V << LP_ANALOG_PERI_TOUCH_PAD12_TH2_S)
+#define LP_ANALOG_PERI_TOUCH_PAD12_TH2_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD12_TH2_S  16
 
-/** LP_ANA_TOUCH_PAD13_TH0_REG register
+/** LP_ANALOG_PERI_TOUCH_PAD13_TH0_REG register
  *  need_des
  */
-#define LP_ANA_TOUCH_PAD13_TH0_REG (DR_REG_LP_ANA_BASE + 0x1e0)
-/** LP_ANA_TOUCH_PAD13_TH0 : R/W; bitpos: [31:16]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_PAD13_TH0_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x1e0)
+/** LP_ANALOG_PERI_TOUCH_PAD13_TH0 : R/W; bitpos: [31:16]; default: 0;
  *  Reserved
  */
-#define LP_ANA_TOUCH_PAD13_TH0    0x0000FFFFU
-#define LP_ANA_TOUCH_PAD13_TH0_M  (LP_ANA_TOUCH_PAD13_TH0_V << LP_ANA_TOUCH_PAD13_TH0_S)
-#define LP_ANA_TOUCH_PAD13_TH0_V  0x0000FFFFU
-#define LP_ANA_TOUCH_PAD13_TH0_S  16
+#define LP_ANALOG_PERI_TOUCH_PAD13_TH0    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD13_TH0_M  (LP_ANALOG_PERI_TOUCH_PAD13_TH0_V << LP_ANALOG_PERI_TOUCH_PAD13_TH0_S)
+#define LP_ANALOG_PERI_TOUCH_PAD13_TH0_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD13_TH0_S  16
 
-/** LP_ANA_TOUCH_PAD13_TH1_REG register
+/** LP_ANALOG_PERI_TOUCH_PAD13_TH1_REG register
  *  need_des
  */
-#define LP_ANA_TOUCH_PAD13_TH1_REG (DR_REG_LP_ANA_BASE + 0x1e4)
-/** LP_ANA_TOUCH_PAD13_TH1 : R/W; bitpos: [31:16]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_PAD13_TH1_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x1e4)
+/** LP_ANALOG_PERI_TOUCH_PAD13_TH1 : R/W; bitpos: [31:16]; default: 0;
  *  Reserved
  */
-#define LP_ANA_TOUCH_PAD13_TH1    0x0000FFFFU
-#define LP_ANA_TOUCH_PAD13_TH1_M  (LP_ANA_TOUCH_PAD13_TH1_V << LP_ANA_TOUCH_PAD13_TH1_S)
-#define LP_ANA_TOUCH_PAD13_TH1_V  0x0000FFFFU
-#define LP_ANA_TOUCH_PAD13_TH1_S  16
+#define LP_ANALOG_PERI_TOUCH_PAD13_TH1    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD13_TH1_M  (LP_ANALOG_PERI_TOUCH_PAD13_TH1_V << LP_ANALOG_PERI_TOUCH_PAD13_TH1_S)
+#define LP_ANALOG_PERI_TOUCH_PAD13_TH1_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD13_TH1_S  16
 
-/** LP_ANA_TOUCH_PAD13_TH2_REG register
+/** LP_ANALOG_PERI_TOUCH_PAD13_TH2_REG register
  *  need_des
  */
-#define LP_ANA_TOUCH_PAD13_TH2_REG (DR_REG_LP_ANA_BASE + 0x1e8)
-/** LP_ANA_TOUCH_PAD13_TH2 : R/W; bitpos: [31:16]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_PAD13_TH2_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x1e8)
+/** LP_ANALOG_PERI_TOUCH_PAD13_TH2 : R/W; bitpos: [31:16]; default: 0;
  *  Reserved
  */
-#define LP_ANA_TOUCH_PAD13_TH2    0x0000FFFFU
-#define LP_ANA_TOUCH_PAD13_TH2_M  (LP_ANA_TOUCH_PAD13_TH2_V << LP_ANA_TOUCH_PAD13_TH2_S)
-#define LP_ANA_TOUCH_PAD13_TH2_V  0x0000FFFFU
-#define LP_ANA_TOUCH_PAD13_TH2_S  16
+#define LP_ANALOG_PERI_TOUCH_PAD13_TH2    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD13_TH2_M  (LP_ANALOG_PERI_TOUCH_PAD13_TH2_V << LP_ANALOG_PERI_TOUCH_PAD13_TH2_S)
+#define LP_ANALOG_PERI_TOUCH_PAD13_TH2_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD13_TH2_S  16
 
-/** LP_ANA_TOUCH_PAD14_TH0_REG register
+/** LP_ANALOG_PERI_TOUCH_PAD14_TH0_REG register
  *  need_des
  */
-#define LP_ANA_TOUCH_PAD14_TH0_REG (DR_REG_LP_ANA_BASE + 0x1ec)
-/** LP_ANA_TOUCH_PAD14_TH0 : R/W; bitpos: [31:16]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_PAD14_TH0_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x1ec)
+/** LP_ANALOG_PERI_TOUCH_PAD14_TH0 : R/W; bitpos: [31:16]; default: 0;
  *  Reserved
  */
-#define LP_ANA_TOUCH_PAD14_TH0    0x0000FFFFU
-#define LP_ANA_TOUCH_PAD14_TH0_M  (LP_ANA_TOUCH_PAD14_TH0_V << LP_ANA_TOUCH_PAD14_TH0_S)
-#define LP_ANA_TOUCH_PAD14_TH0_V  0x0000FFFFU
-#define LP_ANA_TOUCH_PAD14_TH0_S  16
+#define LP_ANALOG_PERI_TOUCH_PAD14_TH0    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD14_TH0_M  (LP_ANALOG_PERI_TOUCH_PAD14_TH0_V << LP_ANALOG_PERI_TOUCH_PAD14_TH0_S)
+#define LP_ANALOG_PERI_TOUCH_PAD14_TH0_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD14_TH0_S  16
 
-/** LP_ANA_TOUCH_PAD14_TH1_REG register
+/** LP_ANALOG_PERI_TOUCH_PAD14_TH1_REG register
  *  need_des
  */
-#define LP_ANA_TOUCH_PAD14_TH1_REG (DR_REG_LP_ANA_BASE + 0x1f0)
-/** LP_ANA_TOUCH_PAD14_TH1 : R/W; bitpos: [31:16]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_PAD14_TH1_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x1f0)
+/** LP_ANALOG_PERI_TOUCH_PAD14_TH1 : R/W; bitpos: [31:16]; default: 0;
  *  Reserved
  */
-#define LP_ANA_TOUCH_PAD14_TH1    0x0000FFFFU
-#define LP_ANA_TOUCH_PAD14_TH1_M  (LP_ANA_TOUCH_PAD14_TH1_V << LP_ANA_TOUCH_PAD14_TH1_S)
-#define LP_ANA_TOUCH_PAD14_TH1_V  0x0000FFFFU
-#define LP_ANA_TOUCH_PAD14_TH1_S  16
+#define LP_ANALOG_PERI_TOUCH_PAD14_TH1    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD14_TH1_M  (LP_ANALOG_PERI_TOUCH_PAD14_TH1_V << LP_ANALOG_PERI_TOUCH_PAD14_TH1_S)
+#define LP_ANALOG_PERI_TOUCH_PAD14_TH1_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD14_TH1_S  16
 
-/** LP_ANA_TOUCH_PAD14_TH2_REG register
+/** LP_ANALOG_PERI_TOUCH_PAD14_TH2_REG register
  *  need_des
  */
-#define LP_ANA_TOUCH_PAD14_TH2_REG (DR_REG_LP_ANA_BASE + 0x1f4)
-/** LP_ANA_TOUCH_PAD14_TH2 : R/W; bitpos: [31:16]; default: 0;
+#define LP_ANALOG_PERI_TOUCH_PAD14_TH2_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x1f4)
+/** LP_ANALOG_PERI_TOUCH_PAD14_TH2 : R/W; bitpos: [31:16]; default: 0;
  *  Reserved
  */
-#define LP_ANA_TOUCH_PAD14_TH2    0x0000FFFFU
-#define LP_ANA_TOUCH_PAD14_TH2_M  (LP_ANA_TOUCH_PAD14_TH2_V << LP_ANA_TOUCH_PAD14_TH2_S)
-#define LP_ANA_TOUCH_PAD14_TH2_V  0x0000FFFFU
-#define LP_ANA_TOUCH_PAD14_TH2_S  16
+#define LP_ANALOG_PERI_TOUCH_PAD14_TH2    0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD14_TH2_M  (LP_ANALOG_PERI_TOUCH_PAD14_TH2_V << LP_ANALOG_PERI_TOUCH_PAD14_TH2_S)
+#define LP_ANALOG_PERI_TOUCH_PAD14_TH2_V  0x0000FFFFU
+#define LP_ANALOG_PERI_TOUCH_PAD14_TH2_S  16
 
-/** LP_ANA_DATE_REG register
+/** LP_ANALOG_PERI_DATE_REG register
  *  need_des
  */
-#define LP_ANA_DATE_REG (DR_REG_LP_ANA_BASE + 0x3fc)
-/** LP_ANA_LP_ANA_DATE : R/W; bitpos: [30:0]; default: 2294816;
+#define LP_ANALOG_PERI_DATE_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x3fc)
+/** LP_ANALOG_PERI_LP_ANALOG_PERI_DATE : R/W; bitpos: [30:0]; default: 2294816;
  *  need_des
  */
-#define LP_ANA_LP_ANA_DATE    0x7FFFFFFFU
-#define LP_ANA_LP_ANA_DATE_M  (LP_ANA_LP_ANA_DATE_V << LP_ANA_LP_ANA_DATE_S)
-#define LP_ANA_LP_ANA_DATE_V  0x7FFFFFFFU
-#define LP_ANA_LP_ANA_DATE_S  0
-/** LP_ANA_CLK_EN : R/W; bitpos: [31]; default: 0;
+#define LP_ANALOG_PERI_LP_ANALOG_PERI_DATE    0x7FFFFFFFU
+#define LP_ANALOG_PERI_LP_ANALOG_PERI_DATE_M  (LP_ANALOG_PERI_LP_ANALOG_PERI_DATE_V << LP_ANALOG_PERI_LP_ANALOG_PERI_DATE_S)
+#define LP_ANALOG_PERI_LP_ANALOG_PERI_DATE_V  0x7FFFFFFFU
+#define LP_ANALOG_PERI_LP_ANALOG_PERI_DATE_S  0
+/** LP_ANALOG_PERI_CLK_EN : R/W; bitpos: [31]; default: 0;
  *  need_des
  */
-#define LP_ANA_CLK_EN    (BIT(31))
-#define LP_ANA_CLK_EN_M  (LP_ANA_CLK_EN_V << LP_ANA_CLK_EN_S)
-#define LP_ANA_CLK_EN_V  0x00000001U
-#define LP_ANA_CLK_EN_S  31
+#define LP_ANALOG_PERI_CLK_EN    (BIT(31))
+#define LP_ANALOG_PERI_CLK_EN_M  (LP_ANALOG_PERI_CLK_EN_V << LP_ANALOG_PERI_CLK_EN_S)
+#define LP_ANALOG_PERI_CLK_EN_V  0x00000001U
+#define LP_ANALOG_PERI_CLK_EN_S  31
 
 #ifdef __cplusplus
 }

components/soc/esp32p4/include/soc/lp_analog_peri_struct.h

@@ -51,7 +51,7 @@ typedef union {
         uint32_t bod_mode0_reset_ena:1;
     };
     uint32_t val;
-} lp_ana_bod_mode0_cntl_reg_t;
+} lp_analog_peri_bod_mode0_cntl_reg_t;
 
 /** Type of bod_mode1_cntl register
  *  need_des
@@ -65,7 +65,7 @@ typedef union {
         uint32_t bod_mode1_reset_ena:1;
     };
     uint32_t val;
-} lp_ana_bod_mode1_cntl_reg_t;
+} lp_analog_peri_bod_mode1_cntl_reg_t;
 
 /** Type of vdd_source_cntl register
  *  need_des
@@ -90,7 +90,7 @@ typedef union {
         uint32_t bod_source_ena:8;
     };
     uint32_t val;
-} lp_ana_vdd_source_cntl_reg_t;
+} lp_analog_peri_vdd_source_cntl_reg_t;
 
 /** Type of vddbat_bod_cntl register
  *  need_des
@@ -120,7 +120,7 @@ typedef union {
         uint32_t vddbat_undervoltage_target:10;
     };
     uint32_t val;
-} lp_ana_vddbat_bod_cntl_reg_t;
+} lp_analog_peri_vddbat_bod_cntl_reg_t;
 
 /** Type of vddbat_charge_cntl register
  *  need_des
@@ -150,7 +150,7 @@ typedef union {
         uint32_t vddbat_charge_undervoltage_target:10;
     };
     uint32_t val;
-} lp_ana_vddbat_charge_cntl_reg_t;
+} lp_analog_peri_vddbat_charge_cntl_reg_t;
 
 /** Type of ck_glitch_cntl register
  *  need_des
@@ -164,7 +164,7 @@ typedef union {
         uint32_t ck_glitch_reset_ena:1;
     };
     uint32_t val;
-} lp_ana_ck_glitch_cntl_reg_t;
+} lp_analog_peri_ck_glitch_cntl_reg_t;
 
 /** Type of pg_glitch_cntl register
  *  need_des
@@ -178,7 +178,7 @@ typedef union {
         uint32_t power_glitch_reset_ena:1;
     };
     uint32_t val;
-} lp_ana_pg_glitch_cntl_reg_t;
+} lp_analog_peri_pg_glitch_cntl_reg_t;
 
 /** Type of fib_enable register
  *  need_des
@@ -191,7 +191,7 @@ typedef union {
         uint32_t ana_fib_ena:32;
     };
     uint32_t val;
-} lp_ana_fib_enable_reg_t;
+} lp_analog_peri_fib_enable_reg_t;
 
 /** Type of int_raw register
  *  need_des
@@ -221,7 +221,7 @@ typedef union {
         uint32_t bod_mode0_int_raw:1;
     };
     uint32_t val;
-} lp_ana_int_raw_reg_t;
+} lp_analog_peri_int_raw_reg_t;
 
 /** Type of int_st register
  *  need_des
@@ -251,7 +251,7 @@ typedef union {
         uint32_t bod_mode0_int_st:1;
     };
     uint32_t val;
-} lp_ana_int_st_reg_t;
+} lp_analog_peri_int_st_reg_t;
 
 /** Type of int_ena register
  *  need_des
@@ -281,7 +281,7 @@ typedef union {
         uint32_t bod_mode0_int_ena:1;
     };
     uint32_t val;
-} lp_ana_int_ena_reg_t;
+} lp_analog_peri_int_ena_reg_t;
 
 /** Type of int_clr register
  *  need_des
@@ -311,7 +311,7 @@ typedef union {
         uint32_t bod_mode0_int_clr:1;
     };
     uint32_t val;
-} lp_ana_int_clr_reg_t;
+} lp_analog_peri_int_clr_reg_t;
 
 /** Type of lp_int_raw register
  *  need_des
@@ -325,7 +325,7 @@ typedef union {
         uint32_t bod_mode0_lp_int_raw:1;
     };
     uint32_t val;
-} lp_ana_lp_int_raw_reg_t;
+} lp_analog_peri_lp_int_raw_reg_t;
 
 /** Type of lp_int_st register
  *  need_des
@@ -339,7 +339,7 @@ typedef union {
         uint32_t bod_mode0_lp_int_st:1;
     };
     uint32_t val;
-} lp_ana_lp_int_st_reg_t;
+} lp_analog_peri_lp_int_st_reg_t;
 
 /** Type of lp_int_ena register
  *  need_des
@@ -353,7 +353,7 @@ typedef union {
         uint32_t bod_mode0_lp_int_ena:1;
     };
     uint32_t val;
-} lp_ana_lp_int_ena_reg_t;
+} lp_analog_peri_lp_int_ena_reg_t;
 
 /** Type of lp_int_clr register
  *  need_des
@@ -367,7 +367,7 @@ typedef union {
         uint32_t bod_mode0_lp_int_clr:1;
     };
     uint32_t val;
-} lp_ana_lp_int_clr_reg_t;
+} lp_analog_peri_lp_int_clr_reg_t;
 
 /** Type of touch_approach_work_meas_num register
  *  need_des
@@ -389,7 +389,7 @@ typedef union {
         uint32_t reserved_30:2;
     };
     uint32_t val;
-} lp_ana_touch_approach_work_meas_num_reg_t;
+} lp_analog_peri_touch_approach_work_meas_num_reg_t;
 
 /** Type of touch_scan_ctrl1 register
  *  need_des
@@ -414,7 +414,7 @@ typedef union {
         uint32_t touch_xpd_wait:15;
     };
     uint32_t val;
-} lp_ana_touch_scan_ctrl1_reg_t;
+} lp_analog_peri_touch_scan_ctrl1_reg_t;
 
 /** Type of touch_scan_ctrl2 register
  *  need_des
@@ -445,7 +445,7 @@ typedef union {
         uint32_t reserved_30:2;
     };
     uint32_t val;
-} lp_ana_touch_scan_ctrl2_reg_t;
+} lp_analog_peri_touch_scan_ctrl2_reg_t;
 
 /** Type of touch_work register
  *  need_des
@@ -480,7 +480,7 @@ typedef union {
         uint32_t reserved_28:4;
     };
     uint32_t val;
-} lp_ana_touch_work_reg_t;
+} lp_analog_peri_touch_work_reg_t;
 
 /** Type of touch_work_meas_num register
  *  need_des
@@ -502,7 +502,7 @@ typedef union {
         uint32_t reserved_30:2;
     };
     uint32_t val;
-} lp_ana_touch_work_meas_num_reg_t;
+} lp_analog_peri_touch_work_meas_num_reg_t;
 
 /** Type of touch_filter1 register
  *  need_des
@@ -555,7 +555,7 @@ typedef union {
         uint32_t touch_debounce_limit:3;
     };
     uint32_t val;
-} lp_ana_touch_filter1_reg_t;
+} lp_analog_peri_touch_filter1_reg_t;
 
 /** Type of touch_filter2 register
  *  need_des
@@ -577,7 +577,7 @@ typedef union {
         uint32_t touch_bypass_neg_noise_thres:1;
     };
     uint32_t val;
-} lp_ana_touch_filter2_reg_t;
+} lp_analog_peri_touch_filter2_reg_t;
 
 /** Type of touch_filter3 register
  *  need_des
@@ -595,7 +595,7 @@ typedef union {
         uint32_t reserved_17:15;
     };
     uint32_t val;
-} lp_ana_touch_filter3_reg_t;
+} lp_analog_peri_touch_filter3_reg_t;
 
 /** Type of touch_slp0 register
  *  need_des
@@ -617,7 +617,7 @@ typedef union {
         uint32_t reserved_21:11;
     };
     uint32_t val;
-} lp_ana_touch_slp0_reg_t;
+} lp_analog_peri_touch_slp0_reg_t;
 
 /** Type of touch_slp1 register
  *  need_des
@@ -634,7 +634,7 @@ typedef union {
         uint32_t touch_slp_th1:16;
     };
     uint32_t val;
-} lp_ana_touch_slp1_reg_t;
+} lp_analog_peri_touch_slp1_reg_t;
 
 /** Type of touch_clr register
  *  need_des
@@ -652,7 +652,7 @@ typedef union {
         uint32_t reserved_16:16;
     };
     uint32_t val;
-} lp_ana_touch_clr_reg_t;
+} lp_analog_peri_touch_clr_reg_t;
 
 /** Type of touch_approach register
  *  need_des
@@ -678,7 +678,7 @@ typedef union {
         uint32_t reserved_13:19;
     };
     uint32_t val;
-} lp_ana_touch_approach_reg_t;
+} lp_analog_peri_touch_approach_reg_t;
 
 /** Type of touch_freq0_scan_para register
  *  need_des
@@ -708,7 +708,7 @@ typedef union {
         uint32_t reserved_23:9;
     };
     uint32_t val;
-} lp_ana_touch_freq0_scan_para_reg_t;
+} lp_analog_peri_touch_freq0_scan_para_reg_t;
 
 /** Type of touch_freq1_scan_para register
  *  need_des
@@ -738,7 +738,7 @@ typedef union {
         uint32_t reserved_23:9;
     };
     uint32_t val;
-} lp_ana_touch_freq1_scan_para_reg_t;
+} lp_analog_peri_touch_freq1_scan_para_reg_t;
 
 /** Type of touch_freq2_scan_para register
  *  need_des
@@ -768,7 +768,7 @@ typedef union {
         uint32_t reserved_23:9;
     };
     uint32_t val;
-} lp_ana_touch_freq2_scan_para_reg_t;
+} lp_analog_peri_touch_freq2_scan_para_reg_t;
 
 /** Type of touch_ana_para register
  *  need_des
@@ -790,7 +790,7 @@ typedef union {
         uint32_t reserved_11:21;
     };
     uint32_t val;
-} lp_ana_touch_ana_para_reg_t;
+} lp_analog_peri_touch_ana_para_reg_t;
 
 /** Type of touch_mux0 register
  *  need_des
@@ -832,7 +832,7 @@ typedef union {
         uint32_t touch_start_force:1;
     };
     uint32_t val;
-} lp_ana_touch_mux0_reg_t;
+} lp_analog_peri_touch_mux0_reg_t;
 
 /** Type of touch_mux1 register
  *  need_des
@@ -850,7 +850,7 @@ typedef union {
         uint32_t reserved_30:2;
     };
     uint32_t val;
-} lp_ana_touch_mux1_reg_t;
+} lp_analog_peri_touch_mux1_reg_t;
 
 /** Type of touch_pad0_th0 register
  *  need_des
@@ -864,7 +864,7 @@ typedef union {
         uint32_t touch_pad0_th0:16;
     };
     uint32_t val;
-} lp_ana_touch_pad0_th0_reg_t;
+} lp_analog_peri_touch_pad0_th0_reg_t;
 
 /** Type of touch_pad0_th1 register
  *  need_des
@@ -878,7 +878,7 @@ typedef union {
         uint32_t touch_pad0_th1:16;
     };
     uint32_t val;
-} lp_ana_touch_pad0_th1_reg_t;
+} lp_analog_peri_touch_pad0_th1_reg_t;
 
 /** Type of touch_pad0_th2 register
  *  need_des
@@ -892,7 +892,7 @@ typedef union {
         uint32_t touch_pad0_th2:16;
     };
     uint32_t val;
-} lp_ana_touch_pad0_th2_reg_t;
+} lp_analog_peri_touch_pad0_th2_reg_t;
 
 /** Type of touch_pad1_th0 register
  *  need_des
@@ -906,7 +906,7 @@ typedef union {
         uint32_t touch_pad1_th0:16;
     };
     uint32_t val;
-} lp_ana_touch_pad1_th0_reg_t;
+} lp_analog_peri_touch_pad1_th0_reg_t;
 
 /** Type of touch_pad1_th1 register
  *  need_des
@@ -920,7 +920,7 @@ typedef union {
         uint32_t touch_pad1_th1:16;
     };
     uint32_t val;
-} lp_ana_touch_pad1_th1_reg_t;
+} lp_analog_peri_touch_pad1_th1_reg_t;
 
 /** Type of touch_pad1_th2 register
  *  need_des
@@ -934,7 +934,7 @@ typedef union {
         uint32_t touch_pad1_th2:16;
     };
     uint32_t val;
-} lp_ana_touch_pad1_th2_reg_t;
+} lp_analog_peri_touch_pad1_th2_reg_t;
 
 /** Type of touch_pad2_th0 register
  *  need_des
@@ -948,7 +948,7 @@ typedef union {
         uint32_t touch_pad2_th0:16;
     };
     uint32_t val;
-} lp_ana_touch_pad2_th0_reg_t;
+} lp_analog_peri_touch_pad2_th0_reg_t;
 
 /** Type of touch_pad2_th1 register
  *  need_des
@@ -962,7 +962,7 @@ typedef union {
         uint32_t touch_pad2_th1:16;
     };
     uint32_t val;
-} lp_ana_touch_pad2_th1_reg_t;
+} lp_analog_peri_touch_pad2_th1_reg_t;
 
 /** Type of touch_pad2_th2 register
  *  need_des
@@ -976,7 +976,7 @@ typedef union {
         uint32_t touch_pad2_th2:16;
     };
     uint32_t val;
-} lp_ana_touch_pad2_th2_reg_t;
+} lp_analog_peri_touch_pad2_th2_reg_t;
 
 /** Type of touch_pad3_th0 register
  *  need_des
@@ -990,7 +990,7 @@ typedef union {
         uint32_t touch_pad3_th0:16;
     };
     uint32_t val;
-} lp_ana_touch_pad3_th0_reg_t;
+} lp_analog_peri_touch_pad3_th0_reg_t;
 
 /** Type of touch_pad3_th1 register
  *  need_des
@@ -1004,7 +1004,7 @@ typedef union {
         uint32_t touch_pad3_th1:16;
     };
     uint32_t val;
-} lp_ana_touch_pad3_th1_reg_t;
+} lp_analog_peri_touch_pad3_th1_reg_t;
 
 /** Type of touch_pad3_th2 register
  *  need_des
@@ -1018,7 +1018,7 @@ typedef union {
         uint32_t touch_pad3_th2:16;
     };
     uint32_t val;
-} lp_ana_touch_pad3_th2_reg_t;
+} lp_analog_peri_touch_pad3_th2_reg_t;
 
 /** Type of touch_pad4_th0 register
  *  need_des
@@ -1032,7 +1032,7 @@ typedef union {
         uint32_t touch_pad4_th0:16;
     };
     uint32_t val;
-} lp_ana_touch_pad4_th0_reg_t;
+} lp_analog_peri_touch_pad4_th0_reg_t;
 
 /** Type of touch_pad4_th1 register
  *  need_des
@@ -1046,7 +1046,7 @@ typedef union {
         uint32_t touch_pad4_th1:16;
     };
     uint32_t val;
-} lp_ana_touch_pad4_th1_reg_t;
+} lp_analog_peri_touch_pad4_th1_reg_t;
 
 /** Type of touch_pad4_th2 register
  *  need_des
@@ -1060,7 +1060,7 @@ typedef union {
         uint32_t touch_pad4_th2:16;
     };
     uint32_t val;
-} lp_ana_touch_pad4_th2_reg_t;
+} lp_analog_peri_touch_pad4_th2_reg_t;
 
 /** Type of touch_pad5_th0 register
  *  need_des
@@ -1074,7 +1074,7 @@ typedef union {
         uint32_t touch_pad5_th0:16;
     };
     uint32_t val;
-} lp_ana_touch_pad5_th0_reg_t;
+} lp_analog_peri_touch_pad5_th0_reg_t;
 
 /** Type of touch_pad5_th1 register
  *  need_des
@@ -1088,7 +1088,7 @@ typedef union {
         uint32_t touch_pad5_th1:16;
     };
     uint32_t val;
-} lp_ana_touch_pad5_th1_reg_t;
+} lp_analog_peri_touch_pad5_th1_reg_t;
 
 /** Type of touch_pad5_th2 register
  *  need_des
@@ -1102,7 +1102,7 @@ typedef union {
         uint32_t touch_pad5_th2:16;
     };
     uint32_t val;
-} lp_ana_touch_pad5_th2_reg_t;
+} lp_analog_peri_touch_pad5_th2_reg_t;
 
 /** Type of touch_pad6_th0 register
  *  need_des
@@ -1116,7 +1116,7 @@ typedef union {
         uint32_t touch_pad6_th0:16;
     };
     uint32_t val;
-} lp_ana_touch_pad6_th0_reg_t;
+} lp_analog_peri_touch_pad6_th0_reg_t;
 
 /** Type of touch_pad6_th1 register
  *  need_des
@@ -1130,7 +1130,7 @@ typedef union {
         uint32_t touch_pad6_th1:16;
     };
     uint32_t val;
-} lp_ana_touch_pad6_th1_reg_t;
+} lp_analog_peri_touch_pad6_th1_reg_t;
 
 /** Type of touch_pad6_th2 register
  *  need_des
@@ -1144,7 +1144,7 @@ typedef union {
         uint32_t touch_pad6_th2:16;
     };
     uint32_t val;
-} lp_ana_touch_pad6_th2_reg_t;
+} lp_analog_peri_touch_pad6_th2_reg_t;
 
 /** Type of touch_pad7_th0 register
  *  need_des
@@ -1158,7 +1158,7 @@ typedef union {
         uint32_t touch_pad7_th0:16;
     };
     uint32_t val;
-} lp_ana_touch_pad7_th0_reg_t;
+} lp_analog_peri_touch_pad7_th0_reg_t;
 
 /** Type of touch_pad7_th1 register
  *  need_des
@@ -1172,7 +1172,7 @@ typedef union {
         uint32_t touch_pad7_th1:16;
     };
     uint32_t val;
-} lp_ana_touch_pad7_th1_reg_t;
+} lp_analog_peri_touch_pad7_th1_reg_t;
 
 /** Type of touch_pad7_th2 register
  *  need_des
@@ -1186,7 +1186,7 @@ typedef union {
         uint32_t touch_pad7_th2:16;
     };
     uint32_t val;
-} lp_ana_touch_pad7_th2_reg_t;
+} lp_analog_peri_touch_pad7_th2_reg_t;
 
 /** Type of touch_pad8_th0 register
  *  need_des
@@ -1200,7 +1200,7 @@ typedef union {
         uint32_t touch_pad8_th0:16;
     };
     uint32_t val;
-} lp_ana_touch_pad8_th0_reg_t;
+} lp_analog_peri_touch_pad8_th0_reg_t;
 
 /** Type of touch_pad8_th1 register
  *  need_des
@@ -1214,7 +1214,7 @@ typedef union {
         uint32_t touch_pad8_th1:16;
     };
     uint32_t val;
-} lp_ana_touch_pad8_th1_reg_t;
+} lp_analog_peri_touch_pad8_th1_reg_t;
 
 /** Type of touch_pad8_th2 register
  *  need_des
@@ -1228,7 +1228,7 @@ typedef union {
         uint32_t touch_pad8_th2:16;
     };
     uint32_t val;
-} lp_ana_touch_pad8_th2_reg_t;
+} lp_analog_peri_touch_pad8_th2_reg_t;
 
 /** Type of touch_pad9_th0 register
  *  need_des
@@ -1242,7 +1242,7 @@ typedef union {
         uint32_t touch_pad9_th0:16;
     };
     uint32_t val;
-} lp_ana_touch_pad9_th0_reg_t;
+} lp_analog_peri_touch_pad9_th0_reg_t;
 
 /** Type of touch_pad9_th1 register
  *  need_des
@@ -1256,7 +1256,7 @@ typedef union {
         uint32_t touch_pad9_th1:16;
     };
     uint32_t val;
-} lp_ana_touch_pad9_th1_reg_t;
+} lp_analog_peri_touch_pad9_th1_reg_t;
 
 /** Type of touch_pad9_th2 register
  *  need_des
@@ -1270,7 +1270,7 @@ typedef union {
         uint32_t touch_pad9_th2:16;
     };
     uint32_t val;
-} lp_ana_touch_pad9_th2_reg_t;
+} lp_analog_peri_touch_pad9_th2_reg_t;
 
 /** Type of touch_pad10_th0 register
  *  need_des
@@ -1284,7 +1284,7 @@ typedef union {
         uint32_t touch_pad10_th0:16;
     };
     uint32_t val;
-} lp_ana_touch_pad10_th0_reg_t;
+} lp_analog_peri_touch_pad10_th0_reg_t;
 
 /** Type of touch_pad10_th1 register
  *  need_des
@@ -1298,7 +1298,7 @@ typedef union {
         uint32_t touch_pad10_th1:16;
     };
     uint32_t val;
-} lp_ana_touch_pad10_th1_reg_t;
+} lp_analog_peri_touch_pad10_th1_reg_t;
 
 /** Type of touch_pad10_th2 register
  *  need_des
@@ -1312,7 +1312,7 @@ typedef union {
         uint32_t touch_pad10_th2:16;
     };
     uint32_t val;
-} lp_ana_touch_pad10_th2_reg_t;
+} lp_analog_peri_touch_pad10_th2_reg_t;
 
 /** Type of touch_pad11_th0 register
  *  need_des
@@ -1326,7 +1326,7 @@ typedef union {
         uint32_t touch_pad11_th0:16;
     };
     uint32_t val;
-} lp_ana_touch_pad11_th0_reg_t;
+} lp_analog_peri_touch_pad11_th0_reg_t;
 
 /** Type of touch_pad11_th1 register
  *  need_des
@@ -1340,7 +1340,7 @@ typedef union {
         uint32_t touch_pad11_th1:16;
     };
     uint32_t val;
-} lp_ana_touch_pad11_th1_reg_t;
+} lp_analog_peri_touch_pad11_th1_reg_t;
 
 /** Type of touch_pad11_th2 register
  *  need_des
@@ -1354,7 +1354,7 @@ typedef union {
         uint32_t touch_pad11_th2:16;
     };
     uint32_t val;
-} lp_ana_touch_pad11_th2_reg_t;
+} lp_analog_peri_touch_pad11_th2_reg_t;
 
 /** Type of touch_pad12_th0 register
  *  need_des
@@ -1368,7 +1368,7 @@ typedef union {
         uint32_t touch_pad12_th0:16;
     };
     uint32_t val;
-} lp_ana_touch_pad12_th0_reg_t;
+} lp_analog_peri_touch_pad12_th0_reg_t;
 
 /** Type of touch_pad12_th1 register
  *  need_des
@@ -1382,7 +1382,7 @@ typedef union {
         uint32_t touch_pad12_th1:16;
     };
     uint32_t val;
-} lp_ana_touch_pad12_th1_reg_t;
+} lp_analog_peri_touch_pad12_th1_reg_t;
 
 /** Type of touch_pad12_th2 register
  *  need_des
@@ -1396,7 +1396,7 @@ typedef union {
         uint32_t touch_pad12_th2:16;
     };
     uint32_t val;
-} lp_ana_touch_pad12_th2_reg_t;
+} lp_analog_peri_touch_pad12_th2_reg_t;
 
 /** Type of touch_pad13_th0 register
  *  need_des
@@ -1410,7 +1410,7 @@ typedef union {
         uint32_t touch_pad13_th0:16;
     };
     uint32_t val;
-} lp_ana_touch_pad13_th0_reg_t;
+} lp_analog_peri_touch_pad13_th0_reg_t;
 
 /** Type of touch_pad13_th1 register
  *  need_des
@@ -1424,7 +1424,7 @@ typedef union {
         uint32_t touch_pad13_th1:16;
     };
     uint32_t val;
-} lp_ana_touch_pad13_th1_reg_t;
+} lp_analog_peri_touch_pad13_th1_reg_t;
 
 /** Type of touch_pad13_th2 register
  *  need_des
@@ -1438,7 +1438,7 @@ typedef union {
         uint32_t touch_pad13_th2:16;
     };
     uint32_t val;
-} lp_ana_touch_pad13_th2_reg_t;
+} lp_analog_peri_touch_pad13_th2_reg_t;
 
 /** Type of touch_pad14_th0 register
  *  need_des
@@ -1452,7 +1452,7 @@ typedef union {
         uint32_t touch_pad14_th0:16;
     };
     uint32_t val;
-} lp_ana_touch_pad14_th0_reg_t;
+} lp_analog_peri_touch_pad14_th0_reg_t;
 
 /** Type of touch_pad14_th1 register
  *  need_des
@@ -1466,7 +1466,7 @@ typedef union {
         uint32_t touch_pad14_th1:16;
     };
     uint32_t val;
-} lp_ana_touch_pad14_th1_reg_t;
+} lp_analog_peri_touch_pad14_th1_reg_t;
 
 /** Type of touch_pad14_th2 register
  *  need_des
@@ -1480,114 +1480,114 @@ typedef union {
         uint32_t touch_pad14_th2:16;
     };
     uint32_t val;
-} lp_ana_touch_pad14_th2_reg_t;
+} lp_analog_peri_touch_pad14_th2_reg_t;
 
 /** Type of date register
  *  need_des
  */
 typedef union {
     struct {
-        /** lp_ana_date : R/W; bitpos: [30:0]; default: 2294816;
+        /** lp_analog_peri_date : R/W; bitpos: [30:0]; default: 2294816;
          *  need_des
          */
-        uint32_t lp_ana_date:31;
+        uint32_t lp_analog_peri_date:31;
         /** clk_en : R/W; bitpos: [31]; default: 0;
          *  need_des
          */
         uint32_t clk_en:1;
     };
     uint32_t val;
-} lp_ana_date_reg_t;
+} lp_analog_peri_date_reg_t;
 
 
 typedef struct {
-    volatile lp_ana_bod_mode0_cntl_reg_t bod_mode0_cntl;
-    volatile lp_ana_bod_mode1_cntl_reg_t bod_mode1_cntl;
-    volatile lp_ana_vdd_source_cntl_reg_t vdd_source_cntl;
-    volatile lp_ana_vddbat_bod_cntl_reg_t vddbat_bod_cntl;
-    volatile lp_ana_vddbat_charge_cntl_reg_t vddbat_charge_cntl;
-    volatile lp_ana_ck_glitch_cntl_reg_t ck_glitch_cntl;
-    volatile lp_ana_pg_glitch_cntl_reg_t pg_glitch_cntl;
-    volatile lp_ana_fib_enable_reg_t fib_enable;
-    volatile lp_ana_int_raw_reg_t int_raw;
-    volatile lp_ana_int_st_reg_t int_st;
-    volatile lp_ana_int_ena_reg_t int_ena;
-    volatile lp_ana_int_clr_reg_t int_clr;
-    volatile lp_ana_lp_int_raw_reg_t lp_int_raw;
-    volatile lp_ana_lp_int_st_reg_t lp_int_st;
-    volatile lp_ana_lp_int_ena_reg_t lp_int_ena;
-    volatile lp_ana_lp_int_clr_reg_t lp_int_clr;
+    volatile lp_analog_peri_bod_mode0_cntl_reg_t bod_mode0_cntl;
+    volatile lp_analog_peri_bod_mode1_cntl_reg_t bod_mode1_cntl;
+    volatile lp_analog_peri_vdd_source_cntl_reg_t vdd_source_cntl;
+    volatile lp_analog_peri_vddbat_bod_cntl_reg_t vddbat_bod_cntl;
+    volatile lp_analog_peri_vddbat_charge_cntl_reg_t vddbat_charge_cntl;
+    volatile lp_analog_peri_ck_glitch_cntl_reg_t ck_glitch_cntl;
+    volatile lp_analog_peri_pg_glitch_cntl_reg_t pg_glitch_cntl;
+    volatile lp_analog_peri_fib_enable_reg_t fib_enable;
+    volatile lp_analog_peri_int_raw_reg_t int_raw;
+    volatile lp_analog_peri_int_st_reg_t int_st;
+    volatile lp_analog_peri_int_ena_reg_t int_ena;
+    volatile lp_analog_peri_int_clr_reg_t int_clr;
+    volatile lp_analog_peri_lp_int_raw_reg_t lp_int_raw;
+    volatile lp_analog_peri_lp_int_st_reg_t lp_int_st;
+    volatile lp_analog_peri_lp_int_ena_reg_t lp_int_ena;
+    volatile lp_analog_peri_lp_int_clr_reg_t lp_int_clr;
     uint32_t reserved_040[47];
-    volatile lp_ana_touch_approach_work_meas_num_reg_t touch_approach_work_meas_num;
-    volatile lp_ana_touch_scan_ctrl1_reg_t touch_scan_ctrl1;
-    volatile lp_ana_touch_scan_ctrl2_reg_t touch_scan_ctrl2;
-    volatile lp_ana_touch_work_reg_t touch_work;
-    volatile lp_ana_touch_work_meas_num_reg_t touch_work_meas_num;
-    volatile lp_ana_touch_filter1_reg_t touch_filter1;
-    volatile lp_ana_touch_filter2_reg_t touch_filter2;
-    volatile lp_ana_touch_filter3_reg_t touch_filter3;
-    volatile lp_ana_touch_slp0_reg_t touch_slp0;
-    volatile lp_ana_touch_slp1_reg_t touch_slp1;
-    volatile lp_ana_touch_clr_reg_t touch_clr;
-    volatile lp_ana_touch_approach_reg_t touch_approach;
-    volatile lp_ana_touch_freq0_scan_para_reg_t touch_freq0_scan_para;
-    volatile lp_ana_touch_freq1_scan_para_reg_t touch_freq1_scan_para;
-    volatile lp_ana_touch_freq2_scan_para_reg_t touch_freq2_scan_para;
-    volatile lp_ana_touch_ana_para_reg_t touch_ana_para;
-    volatile lp_ana_touch_mux0_reg_t touch_mux0;
-    volatile lp_ana_touch_mux1_reg_t touch_mux1;
-    volatile lp_ana_touch_pad0_th0_reg_t touch_pad0_th0;
-    volatile lp_ana_touch_pad0_th1_reg_t touch_pad0_th1;
-    volatile lp_ana_touch_pad0_th2_reg_t touch_pad0_th2;
-    volatile lp_ana_touch_pad1_th0_reg_t touch_pad1_th0;
-    volatile lp_ana_touch_pad1_th1_reg_t touch_pad1_th1;
-    volatile lp_ana_touch_pad1_th2_reg_t touch_pad1_th2;
-    volatile lp_ana_touch_pad2_th0_reg_t touch_pad2_th0;
-    volatile lp_ana_touch_pad2_th1_reg_t touch_pad2_th1;
-    volatile lp_ana_touch_pad2_th2_reg_t touch_pad2_th2;
-    volatile lp_ana_touch_pad3_th0_reg_t touch_pad3_th0;
-    volatile lp_ana_touch_pad3_th1_reg_t touch_pad3_th1;
-    volatile lp_ana_touch_pad3_th2_reg_t touch_pad3_th2;
-    volatile lp_ana_touch_pad4_th0_reg_t touch_pad4_th0;
-    volatile lp_ana_touch_pad4_th1_reg_t touch_pad4_th1;
-    volatile lp_ana_touch_pad4_th2_reg_t touch_pad4_th2;
-    volatile lp_ana_touch_pad5_th0_reg_t touch_pad5_th0;
-    volatile lp_ana_touch_pad5_th1_reg_t touch_pad5_th1;
-    volatile lp_ana_touch_pad5_th2_reg_t touch_pad5_th2;
-    volatile lp_ana_touch_pad6_th0_reg_t touch_pad6_th0;
-    volatile lp_ana_touch_pad6_th1_reg_t touch_pad6_th1;
-    volatile lp_ana_touch_pad6_th2_reg_t touch_pad6_th2;
-    volatile lp_ana_touch_pad7_th0_reg_t touch_pad7_th0;
-    volatile lp_ana_touch_pad7_th1_reg_t touch_pad7_th1;
-    volatile lp_ana_touch_pad7_th2_reg_t touch_pad7_th2;
-    volatile lp_ana_touch_pad8_th0_reg_t touch_pad8_th0;
-    volatile lp_ana_touch_pad8_th1_reg_t touch_pad8_th1;
-    volatile lp_ana_touch_pad8_th2_reg_t touch_pad8_th2;
-    volatile lp_ana_touch_pad9_th0_reg_t touch_pad9_th0;
-    volatile lp_ana_touch_pad9_th1_reg_t touch_pad9_th1;
-    volatile lp_ana_touch_pad9_th2_reg_t touch_pad9_th2;
-    volatile lp_ana_touch_pad10_th0_reg_t touch_pad10_th0;
-    volatile lp_ana_touch_pad10_th1_reg_t touch_pad10_th1;
-    volatile lp_ana_touch_pad10_th2_reg_t touch_pad10_th2;
-    volatile lp_ana_touch_pad11_th0_reg_t touch_pad11_th0;
-    volatile lp_ana_touch_pad11_th1_reg_t touch_pad11_th1;
-    volatile lp_ana_touch_pad11_th2_reg_t touch_pad11_th2;
-    volatile lp_ana_touch_pad12_th0_reg_t touch_pad12_th0;
-    volatile lp_ana_touch_pad12_th1_reg_t touch_pad12_th1;
-    volatile lp_ana_touch_pad12_th2_reg_t touch_pad12_th2;
-    volatile lp_ana_touch_pad13_th0_reg_t touch_pad13_th0;
-    volatile lp_ana_touch_pad13_th1_reg_t touch_pad13_th1;
-    volatile lp_ana_touch_pad13_th2_reg_t touch_pad13_th2;
-    volatile lp_ana_touch_pad14_th0_reg_t touch_pad14_th0;
-    volatile lp_ana_touch_pad14_th1_reg_t touch_pad14_th1;
-    volatile lp_ana_touch_pad14_th2_reg_t touch_pad14_th2;
+    volatile lp_analog_peri_touch_approach_work_meas_num_reg_t touch_approach_work_meas_num;
+    volatile lp_analog_peri_touch_scan_ctrl1_reg_t touch_scan_ctrl1;
+    volatile lp_analog_peri_touch_scan_ctrl2_reg_t touch_scan_ctrl2;
+    volatile lp_analog_peri_touch_work_reg_t touch_work;
+    volatile lp_analog_peri_touch_work_meas_num_reg_t touch_work_meas_num;
+    volatile lp_analog_peri_touch_filter1_reg_t touch_filter1;
+    volatile lp_analog_peri_touch_filter2_reg_t touch_filter2;
+    volatile lp_analog_peri_touch_filter3_reg_t touch_filter3;
+    volatile lp_analog_peri_touch_slp0_reg_t touch_slp0;
+    volatile lp_analog_peri_touch_slp1_reg_t touch_slp1;
+    volatile lp_analog_peri_touch_clr_reg_t touch_clr;
+    volatile lp_analog_peri_touch_approach_reg_t touch_approach;
+    volatile lp_analog_peri_touch_freq0_scan_para_reg_t touch_freq0_scan_para;
+    volatile lp_analog_peri_touch_freq1_scan_para_reg_t touch_freq1_scan_para;
+    volatile lp_analog_peri_touch_freq2_scan_para_reg_t touch_freq2_scan_para;
+    volatile lp_analog_peri_touch_ana_para_reg_t touch_ana_para;
+    volatile lp_analog_peri_touch_mux0_reg_t touch_mux0;
+    volatile lp_analog_peri_touch_mux1_reg_t touch_mux1;
+    volatile lp_analog_peri_touch_pad0_th0_reg_t touch_pad0_th0;
+    volatile lp_analog_peri_touch_pad0_th1_reg_t touch_pad0_th1;
+    volatile lp_analog_peri_touch_pad0_th2_reg_t touch_pad0_th2;
+    volatile lp_analog_peri_touch_pad1_th0_reg_t touch_pad1_th0;
+    volatile lp_analog_peri_touch_pad1_th1_reg_t touch_pad1_th1;
+    volatile lp_analog_peri_touch_pad1_th2_reg_t touch_pad1_th2;
+    volatile lp_analog_peri_touch_pad2_th0_reg_t touch_pad2_th0;
+    volatile lp_analog_peri_touch_pad2_th1_reg_t touch_pad2_th1;
+    volatile lp_analog_peri_touch_pad2_th2_reg_t touch_pad2_th2;
+    volatile lp_analog_peri_touch_pad3_th0_reg_t touch_pad3_th0;
+    volatile lp_analog_peri_touch_pad3_th1_reg_t touch_pad3_th1;
+    volatile lp_analog_peri_touch_pad3_th2_reg_t touch_pad3_th2;
+    volatile lp_analog_peri_touch_pad4_th0_reg_t touch_pad4_th0;
+    volatile lp_analog_peri_touch_pad4_th1_reg_t touch_pad4_th1;
+    volatile lp_analog_peri_touch_pad4_th2_reg_t touch_pad4_th2;
+    volatile lp_analog_peri_touch_pad5_th0_reg_t touch_pad5_th0;
+    volatile lp_analog_peri_touch_pad5_th1_reg_t touch_pad5_th1;
+    volatile lp_analog_peri_touch_pad5_th2_reg_t touch_pad5_th2;
+    volatile lp_analog_peri_touch_pad6_th0_reg_t touch_pad6_th0;
+    volatile lp_analog_peri_touch_pad6_th1_reg_t touch_pad6_th1;
+    volatile lp_analog_peri_touch_pad6_th2_reg_t touch_pad6_th2;
+    volatile lp_analog_peri_touch_pad7_th0_reg_t touch_pad7_th0;
+    volatile lp_analog_peri_touch_pad7_th1_reg_t touch_pad7_th1;
+    volatile lp_analog_peri_touch_pad7_th2_reg_t touch_pad7_th2;
+    volatile lp_analog_peri_touch_pad8_th0_reg_t touch_pad8_th0;
+    volatile lp_analog_peri_touch_pad8_th1_reg_t touch_pad8_th1;
+    volatile lp_analog_peri_touch_pad8_th2_reg_t touch_pad8_th2;
+    volatile lp_analog_peri_touch_pad9_th0_reg_t touch_pad9_th0;
+    volatile lp_analog_peri_touch_pad9_th1_reg_t touch_pad9_th1;
+    volatile lp_analog_peri_touch_pad9_th2_reg_t touch_pad9_th2;
+    volatile lp_analog_peri_touch_pad10_th0_reg_t touch_pad10_th0;
+    volatile lp_analog_peri_touch_pad10_th1_reg_t touch_pad10_th1;
+    volatile lp_analog_peri_touch_pad10_th2_reg_t touch_pad10_th2;
+    volatile lp_analog_peri_touch_pad11_th0_reg_t touch_pad11_th0;
+    volatile lp_analog_peri_touch_pad11_th1_reg_t touch_pad11_th1;
+    volatile lp_analog_peri_touch_pad11_th2_reg_t touch_pad11_th2;
+    volatile lp_analog_peri_touch_pad12_th0_reg_t touch_pad12_th0;
+    volatile lp_analog_peri_touch_pad12_th1_reg_t touch_pad12_th1;
+    volatile lp_analog_peri_touch_pad12_th2_reg_t touch_pad12_th2;
+    volatile lp_analog_peri_touch_pad13_th0_reg_t touch_pad13_th0;
+    volatile lp_analog_peri_touch_pad13_th1_reg_t touch_pad13_th1;
+    volatile lp_analog_peri_touch_pad13_th2_reg_t touch_pad13_th2;
+    volatile lp_analog_peri_touch_pad14_th0_reg_t touch_pad14_th0;
+    volatile lp_analog_peri_touch_pad14_th1_reg_t touch_pad14_th1;
+    volatile lp_analog_peri_touch_pad14_th2_reg_t touch_pad14_th2;
     uint32_t reserved_1f8[129];
-    volatile lp_ana_date_reg_t date;
-} lp_ana_dev_t;
+    volatile lp_analog_peri_date_reg_t date;
+} lp_analog_peri_dev_t;
 
 
 #ifndef __cplusplus
-_Static_assert(sizeof(lp_ana_dev_t) == 0x400, "Invalid size of lp_ana_dev_t structure");
+_Static_assert(sizeof(lp_analog_peri_dev_t) == 0x400, "Invalid size of lp_analog_peri_dev_t structure");
 #endif
 
 #ifdef __cplusplus

components/soc/esp32p4/include/soc/lp_intr_reg.h

@@ -11,224 +11,224 @@
 extern "C" {
 #endif
 
-/** LPINTR_SW_INT_RAW_REG register
+/** LP_INTR_SW_INT_RAW_REG register
  *  need_des
  */
-#define LPINTR_SW_INT_RAW_REG (DR_REG_LPINTR_BASE + 0x0)
-/** LPINTR_LP_SW_INT_RAW : R/W/WTC; bitpos: [31]; default: 0;
+#define LP_INTR_SW_INT_RAW_REG (DR_REG_LP_INTR_BASE + 0x0)
+/** LP_INTR_LP_SW_INT_RAW : R/W/WTC; bitpos: [31]; default: 0;
  *  need_des
  */
-#define LPINTR_LP_SW_INT_RAW    (BIT(31))
-#define LPINTR_LP_SW_INT_RAW_M  (LPINTR_LP_SW_INT_RAW_V << LPINTR_LP_SW_INT_RAW_S)
-#define LPINTR_LP_SW_INT_RAW_V  0x00000001U
-#define LPINTR_LP_SW_INT_RAW_S  31
+#define LP_INTR_LP_SW_INT_RAW    (BIT(31))
+#define LP_INTR_LP_SW_INT_RAW_M  (LP_INTR_LP_SW_INT_RAW_V << LP_INTR_LP_SW_INT_RAW_S)
+#define LP_INTR_LP_SW_INT_RAW_V  0x00000001U
+#define LP_INTR_LP_SW_INT_RAW_S  31
 
-/** LPINTR_SW_INT_ST_REG register
+/** LP_INTR_SW_INT_ST_REG register
  *  need_des
  */
-#define LPINTR_SW_INT_ST_REG (DR_REG_LPINTR_BASE + 0x4)
-/** LPINTR_LP_SW_INT_ST : RO; bitpos: [31]; default: 0;
+#define LP_INTR_SW_INT_ST_REG (DR_REG_LP_INTR_BASE + 0x4)
+/** LP_INTR_LP_SW_INT_ST : RO; bitpos: [31]; default: 0;
  *  need_des
  */
-#define LPINTR_LP_SW_INT_ST    (BIT(31))
-#define LPINTR_LP_SW_INT_ST_M  (LPINTR_LP_SW_INT_ST_V << LPINTR_LP_SW_INT_ST_S)
-#define LPINTR_LP_SW_INT_ST_V  0x00000001U
-#define LPINTR_LP_SW_INT_ST_S  31
+#define LP_INTR_LP_SW_INT_ST    (BIT(31))
+#define LP_INTR_LP_SW_INT_ST_M  (LP_INTR_LP_SW_INT_ST_V << LP_INTR_LP_SW_INT_ST_S)
+#define LP_INTR_LP_SW_INT_ST_V  0x00000001U
+#define LP_INTR_LP_SW_INT_ST_S  31
 
-/** LPINTR_SW_INT_ENA_REG register
+/** LP_INTR_SW_INT_ENA_REG register
  *  need_des
  */
-#define LPINTR_SW_INT_ENA_REG (DR_REG_LPINTR_BASE + 0x8)
-/** LPINTR_LP_SW_INT_ENA : R/W; bitpos: [31]; default: 0;
+#define LP_INTR_SW_INT_ENA_REG (DR_REG_LP_INTR_BASE + 0x8)
+/** LP_INTR_LP_SW_INT_ENA : R/W; bitpos: [31]; default: 0;
  *  need_des
  */
-#define LPINTR_LP_SW_INT_ENA    (BIT(31))
-#define LPINTR_LP_SW_INT_ENA_M  (LPINTR_LP_SW_INT_ENA_V << LPINTR_LP_SW_INT_ENA_S)
-#define LPINTR_LP_SW_INT_ENA_V  0x00000001U
-#define LPINTR_LP_SW_INT_ENA_S  31
+#define LP_INTR_LP_SW_INT_ENA    (BIT(31))
+#define LP_INTR_LP_SW_INT_ENA_M  (LP_INTR_LP_SW_INT_ENA_V << LP_INTR_LP_SW_INT_ENA_S)
+#define LP_INTR_LP_SW_INT_ENA_V  0x00000001U
+#define LP_INTR_LP_SW_INT_ENA_S  31
 
-/** LPINTR_SW_INT_CLR_REG register
+/** LP_INTR_SW_INT_CLR_REG register
  *  need_des
  */
-#define LPINTR_SW_INT_CLR_REG (DR_REG_LPINTR_BASE + 0xc)
-/** LPINTR_LP_SW_INT_CLR : WT; bitpos: [31]; default: 0;
+#define LP_INTR_SW_INT_CLR_REG (DR_REG_LP_INTR_BASE + 0xc)
+/** LP_INTR_LP_SW_INT_CLR : WT; bitpos: [31]; default: 0;
  *  need_des
  */
-#define LPINTR_LP_SW_INT_CLR    (BIT(31))
-#define LPINTR_LP_SW_INT_CLR_M  (LPINTR_LP_SW_INT_CLR_V << LPINTR_LP_SW_INT_CLR_S)
-#define LPINTR_LP_SW_INT_CLR_V  0x00000001U
-#define LPINTR_LP_SW_INT_CLR_S  31
+#define LP_INTR_LP_SW_INT_CLR    (BIT(31))
+#define LP_INTR_LP_SW_INT_CLR_M  (LP_INTR_LP_SW_INT_CLR_V << LP_INTR_LP_SW_INT_CLR_S)
+#define LP_INTR_LP_SW_INT_CLR_V  0x00000001U
+#define LP_INTR_LP_SW_INT_CLR_S  31
 
-/** LPINTR_STATUS_REG register
+/** LP_INTR_STATUS_REG register
  *  need_des
  */
-#define LPINTR_STATUS_REG (DR_REG_LPINTR_BASE + 0x10)
-/** LPINTR_LP_HUK_INTR_ST : RO; bitpos: [10]; default: 0;
+#define LP_INTR_STATUS_REG (DR_REG_LP_INTR_BASE + 0x10)
+/** LP_INTR_LP_HUK_INTR_ST : RO; bitpos: [10]; default: 0;
  *  need_des
  */
-#define LPINTR_LP_HUK_INTR_ST    (BIT(10))
-#define LPINTR_LP_HUK_INTR_ST_M  (LPINTR_LP_HUK_INTR_ST_V << LPINTR_LP_HUK_INTR_ST_S)
-#define LPINTR_LP_HUK_INTR_ST_V  0x00000001U
-#define LPINTR_LP_HUK_INTR_ST_S  10
-/** LPINTR_SYSREG_INTR_ST : RO; bitpos: [11]; default: 0;
+#define LP_INTR_LP_HUK_INTR_ST    (BIT(10))
+#define LP_INTR_LP_HUK_INTR_ST_M  (LP_INTR_LP_HUK_INTR_ST_V << LP_INTR_LP_HUK_INTR_ST_S)
+#define LP_INTR_LP_HUK_INTR_ST_V  0x00000001U
+#define LP_INTR_LP_HUK_INTR_ST_S  10
+/** LP_INTR_SYSREG_INTR_ST : RO; bitpos: [11]; default: 0;
  *  need_des
  */
-#define LPINTR_SYSREG_INTR_ST    (BIT(11))
-#define LPINTR_SYSREG_INTR_ST_M  (LPINTR_SYSREG_INTR_ST_V << LPINTR_SYSREG_INTR_ST_S)
-#define LPINTR_SYSREG_INTR_ST_V  0x00000001U
-#define LPINTR_SYSREG_INTR_ST_S  11
-/** LPINTR_LP_SW_INTR_ST : RO; bitpos: [12]; default: 0;
+#define LP_INTR_SYSREG_INTR_ST    (BIT(11))
+#define LP_INTR_SYSREG_INTR_ST_M  (LP_INTR_SYSREG_INTR_ST_V << LP_INTR_SYSREG_INTR_ST_S)
+#define LP_INTR_SYSREG_INTR_ST_V  0x00000001U
+#define LP_INTR_SYSREG_INTR_ST_S  11
+/** LP_INTR_LP_SW_INTR_ST : RO; bitpos: [12]; default: 0;
  *  need_des
  */
-#define LPINTR_LP_SW_INTR_ST    (BIT(12))
-#define LPINTR_LP_SW_INTR_ST_M  (LPINTR_LP_SW_INTR_ST_V << LPINTR_LP_SW_INTR_ST_S)
-#define LPINTR_LP_SW_INTR_ST_V  0x00000001U
-#define LPINTR_LP_SW_INTR_ST_S  12
-/** LPINTR_LP_EFUSE_INTR_ST : RO; bitpos: [13]; default: 0;
+#define LP_INTR_LP_SW_INTR_ST    (BIT(12))
+#define LP_INTR_LP_SW_INTR_ST_M  (LP_INTR_LP_SW_INTR_ST_V << LP_INTR_LP_SW_INTR_ST_S)
+#define LP_INTR_LP_SW_INTR_ST_V  0x00000001U
+#define LP_INTR_LP_SW_INTR_ST_S  12
+/** LP_INTR_LP_EFUSE_INTR_ST : RO; bitpos: [13]; default: 0;
  *  need_des
  */
-#define LPINTR_LP_EFUSE_INTR_ST    (BIT(13))
-#define LPINTR_LP_EFUSE_INTR_ST_M  (LPINTR_LP_EFUSE_INTR_ST_V << LPINTR_LP_EFUSE_INTR_ST_S)
-#define LPINTR_LP_EFUSE_INTR_ST_V  0x00000001U
-#define LPINTR_LP_EFUSE_INTR_ST_S  13
-/** LPINTR_LP_UART_INTR_ST : RO; bitpos: [14]; default: 0;
+#define LP_INTR_LP_EFUSE_INTR_ST    (BIT(13))
+#define LP_INTR_LP_EFUSE_INTR_ST_M  (LP_INTR_LP_EFUSE_INTR_ST_V << LP_INTR_LP_EFUSE_INTR_ST_S)
+#define LP_INTR_LP_EFUSE_INTR_ST_V  0x00000001U
+#define LP_INTR_LP_EFUSE_INTR_ST_S  13
+/** LP_INTR_LP_UART_INTR_ST : RO; bitpos: [14]; default: 0;
  *  need_des
  */
-#define LPINTR_LP_UART_INTR_ST    (BIT(14))
-#define LPINTR_LP_UART_INTR_ST_M  (LPINTR_LP_UART_INTR_ST_V << LPINTR_LP_UART_INTR_ST_S)
-#define LPINTR_LP_UART_INTR_ST_V  0x00000001U
-#define LPINTR_LP_UART_INTR_ST_S  14
-/** LPINTR_LP_TSENS_INTR_ST : RO; bitpos: [15]; default: 0;
+#define LP_INTR_LP_UART_INTR_ST    (BIT(14))
+#define LP_INTR_LP_UART_INTR_ST_M  (LP_INTR_LP_UART_INTR_ST_V << LP_INTR_LP_UART_INTR_ST_S)
+#define LP_INTR_LP_UART_INTR_ST_V  0x00000001U
+#define LP_INTR_LP_UART_INTR_ST_S  14
+/** LP_INTR_LP_TSENS_INTR_ST : RO; bitpos: [15]; default: 0;
  *  need_des
  */
-#define LPINTR_LP_TSENS_INTR_ST    (BIT(15))
-#define LPINTR_LP_TSENS_INTR_ST_M  (LPINTR_LP_TSENS_INTR_ST_V << LPINTR_LP_TSENS_INTR_ST_S)
-#define LPINTR_LP_TSENS_INTR_ST_V  0x00000001U
-#define LPINTR_LP_TSENS_INTR_ST_S  15
-/** LPINTR_LP_TOUCH_INTR_ST : RO; bitpos: [16]; default: 0;
+#define LP_INTR_LP_TSENS_INTR_ST    (BIT(15))
+#define LP_INTR_LP_TSENS_INTR_ST_M  (LP_INTR_LP_TSENS_INTR_ST_V << LP_INTR_LP_TSENS_INTR_ST_S)
+#define LP_INTR_LP_TSENS_INTR_ST_V  0x00000001U
+#define LP_INTR_LP_TSENS_INTR_ST_S  15
+/** LP_INTR_LP_TOUCH_INTR_ST : RO; bitpos: [16]; default: 0;
  *  need_des
  */
-#define LPINTR_LP_TOUCH_INTR_ST    (BIT(16))
-#define LPINTR_LP_TOUCH_INTR_ST_M  (LPINTR_LP_TOUCH_INTR_ST_V << LPINTR_LP_TOUCH_INTR_ST_S)
-#define LPINTR_LP_TOUCH_INTR_ST_V  0x00000001U
-#define LPINTR_LP_TOUCH_INTR_ST_S  16
-/** LPINTR_LP_SPI_INTR_ST : RO; bitpos: [17]; default: 0;
+#define LP_INTR_LP_TOUCH_INTR_ST    (BIT(16))
+#define LP_INTR_LP_TOUCH_INTR_ST_M  (LP_INTR_LP_TOUCH_INTR_ST_V << LP_INTR_LP_TOUCH_INTR_ST_S)
+#define LP_INTR_LP_TOUCH_INTR_ST_V  0x00000001U
+#define LP_INTR_LP_TOUCH_INTR_ST_S  16
+/** LP_INTR_LP_SPI_INTR_ST : RO; bitpos: [17]; default: 0;
  *  need_des
  */
-#define LPINTR_LP_SPI_INTR_ST    (BIT(17))
-#define LPINTR_LP_SPI_INTR_ST_M  (LPINTR_LP_SPI_INTR_ST_V << LPINTR_LP_SPI_INTR_ST_S)
-#define LPINTR_LP_SPI_INTR_ST_V  0x00000001U
-#define LPINTR_LP_SPI_INTR_ST_S  17
-/** LPINTR_LP_I2S_INTR_ST : RO; bitpos: [18]; default: 0;
+#define LP_INTR_LP_SPI_INTR_ST    (BIT(17))
+#define LP_INTR_LP_SPI_INTR_ST_M  (LP_INTR_LP_SPI_INTR_ST_V << LP_INTR_LP_SPI_INTR_ST_S)
+#define LP_INTR_LP_SPI_INTR_ST_V  0x00000001U
+#define LP_INTR_LP_SPI_INTR_ST_S  17
+/** LP_INTR_LP_I2S_INTR_ST : RO; bitpos: [18]; default: 0;
  *  need_des
  */
-#define LPINTR_LP_I2S_INTR_ST    (BIT(18))
-#define LPINTR_LP_I2S_INTR_ST_M  (LPINTR_LP_I2S_INTR_ST_V << LPINTR_LP_I2S_INTR_ST_S)
-#define LPINTR_LP_I2S_INTR_ST_V  0x00000001U
-#define LPINTR_LP_I2S_INTR_ST_S  18
-/** LPINTR_LP_I2C_INTR_ST : RO; bitpos: [19]; default: 0;
+#define LP_INTR_LP_I2S_INTR_ST    (BIT(18))
+#define LP_INTR_LP_I2S_INTR_ST_M  (LP_INTR_LP_I2S_INTR_ST_V << LP_INTR_LP_I2S_INTR_ST_S)
+#define LP_INTR_LP_I2S_INTR_ST_V  0x00000001U
+#define LP_INTR_LP_I2S_INTR_ST_S  18
+/** LP_INTR_LP_I2C_INTR_ST : RO; bitpos: [19]; default: 0;
  *  need_des
  */
-#define LPINTR_LP_I2C_INTR_ST    (BIT(19))
-#define LPINTR_LP_I2C_INTR_ST_M  (LPINTR_LP_I2C_INTR_ST_V << LPINTR_LP_I2C_INTR_ST_S)
-#define LPINTR_LP_I2C_INTR_ST_V  0x00000001U
-#define LPINTR_LP_I2C_INTR_ST_S  19
-/** LPINTR_LP_GPIO_INTR_ST : RO; bitpos: [20]; default: 0;
+#define LP_INTR_LP_I2C_INTR_ST    (BIT(19))
+#define LP_INTR_LP_I2C_INTR_ST_M  (LP_INTR_LP_I2C_INTR_ST_V << LP_INTR_LP_I2C_INTR_ST_S)
+#define LP_INTR_LP_I2C_INTR_ST_V  0x00000001U
+#define LP_INTR_LP_I2C_INTR_ST_S  19
+/** LP_INTR_LP_GPIO_INTR_ST : RO; bitpos: [20]; default: 0;
  *  need_des
  */
-#define LPINTR_LP_GPIO_INTR_ST    (BIT(20))
-#define LPINTR_LP_GPIO_INTR_ST_M  (LPINTR_LP_GPIO_INTR_ST_V << LPINTR_LP_GPIO_INTR_ST_S)
-#define LPINTR_LP_GPIO_INTR_ST_V  0x00000001U
-#define LPINTR_LP_GPIO_INTR_ST_S  20
-/** LPINTR_LP_ADC_INTR_ST : RO; bitpos: [21]; default: 0;
+#define LP_INTR_LP_GPIO_INTR_ST    (BIT(20))
+#define LP_INTR_LP_GPIO_INTR_ST_M  (LP_INTR_LP_GPIO_INTR_ST_V << LP_INTR_LP_GPIO_INTR_ST_S)
+#define LP_INTR_LP_GPIO_INTR_ST_V  0x00000001U
+#define LP_INTR_LP_GPIO_INTR_ST_S  20
+/** LP_INTR_LP_ADC_INTR_ST : RO; bitpos: [21]; default: 0;
  *  need_des
  */
-#define LPINTR_LP_ADC_INTR_ST    (BIT(21))
-#define LPINTR_LP_ADC_INTR_ST_M  (LPINTR_LP_ADC_INTR_ST_V << LPINTR_LP_ADC_INTR_ST_S)
-#define LPINTR_LP_ADC_INTR_ST_V  0x00000001U
-#define LPINTR_LP_ADC_INTR_ST_S  21
-/** LPINTR_ANAPERI_INTR_ST : RO; bitpos: [22]; default: 0;
+#define LP_INTR_LP_ADC_INTR_ST    (BIT(21))
+#define LP_INTR_LP_ADC_INTR_ST_M  (LP_INTR_LP_ADC_INTR_ST_V << LP_INTR_LP_ADC_INTR_ST_S)
+#define LP_INTR_LP_ADC_INTR_ST_V  0x00000001U
+#define LP_INTR_LP_ADC_INTR_ST_S  21
+/** LP_INTR_ANAPERI_INTR_ST : RO; bitpos: [22]; default: 0;
  *  need_des
  */
-#define LPINTR_ANAPERI_INTR_ST    (BIT(22))
-#define LPINTR_ANAPERI_INTR_ST_M  (LPINTR_ANAPERI_INTR_ST_V << LPINTR_ANAPERI_INTR_ST_S)
-#define LPINTR_ANAPERI_INTR_ST_V  0x00000001U
-#define LPINTR_ANAPERI_INTR_ST_S  22
-/** LPINTR_PMU_REG_1_INTR_ST : RO; bitpos: [23]; default: 0;
+#define LP_INTR_ANAPERI_INTR_ST    (BIT(22))
+#define LP_INTR_ANAPERI_INTR_ST_M  (LP_INTR_ANAPERI_INTR_ST_V << LP_INTR_ANAPERI_INTR_ST_S)
+#define LP_INTR_ANAPERI_INTR_ST_V  0x00000001U
+#define LP_INTR_ANAPERI_INTR_ST_S  22
+/** LP_INTR_PMU_REG_1_INTR_ST : RO; bitpos: [23]; default: 0;
  *  need_des
  */
-#define LPINTR_PMU_REG_1_INTR_ST    (BIT(23))
-#define LPINTR_PMU_REG_1_INTR_ST_M  (LPINTR_PMU_REG_1_INTR_ST_V << LPINTR_PMU_REG_1_INTR_ST_S)
-#define LPINTR_PMU_REG_1_INTR_ST_V  0x00000001U
-#define LPINTR_PMU_REG_1_INTR_ST_S  23
-/** LPINTR_PMU_REG_0_INTR_ST : RO; bitpos: [24]; default: 0;
+#define LP_INTR_PMU_REG_1_INTR_ST    (BIT(23))
+#define LP_INTR_PMU_REG_1_INTR_ST_M  (LP_INTR_PMU_REG_1_INTR_ST_V << LP_INTR_PMU_REG_1_INTR_ST_S)
+#define LP_INTR_PMU_REG_1_INTR_ST_V  0x00000001U
+#define LP_INTR_PMU_REG_1_INTR_ST_S  23
+/** LP_INTR_PMU_REG_0_INTR_ST : RO; bitpos: [24]; default: 0;
  *  need_des
  */
-#define LPINTR_PMU_REG_0_INTR_ST    (BIT(24))
-#define LPINTR_PMU_REG_0_INTR_ST_M  (LPINTR_PMU_REG_0_INTR_ST_V << LPINTR_PMU_REG_0_INTR_ST_S)
-#define LPINTR_PMU_REG_0_INTR_ST_V  0x00000001U
-#define LPINTR_PMU_REG_0_INTR_ST_S  24
-/** LPINTR_MB_LP_INTR_ST : RO; bitpos: [25]; default: 0;
+#define LP_INTR_PMU_REG_0_INTR_ST    (BIT(24))
+#define LP_INTR_PMU_REG_0_INTR_ST_M  (LP_INTR_PMU_REG_0_INTR_ST_V << LP_INTR_PMU_REG_0_INTR_ST_S)
+#define LP_INTR_PMU_REG_0_INTR_ST_V  0x00000001U
+#define LP_INTR_PMU_REG_0_INTR_ST_S  24
+/** LP_INTR_MB_LP_INTR_ST : RO; bitpos: [25]; default: 0;
  *  need_des
  */
-#define LPINTR_MB_LP_INTR_ST    (BIT(25))
-#define LPINTR_MB_LP_INTR_ST_M  (LPINTR_MB_LP_INTR_ST_V << LPINTR_MB_LP_INTR_ST_S)
-#define LPINTR_MB_LP_INTR_ST_V  0x00000001U
-#define LPINTR_MB_LP_INTR_ST_S  25
-/** LPINTR_MB_HP_INTR_ST : RO; bitpos: [26]; default: 0;
+#define LP_INTR_MB_LP_INTR_ST    (BIT(25))
+#define LP_INTR_MB_LP_INTR_ST_M  (LP_INTR_MB_LP_INTR_ST_V << LP_INTR_MB_LP_INTR_ST_S)
+#define LP_INTR_MB_LP_INTR_ST_V  0x00000001U
+#define LP_INTR_MB_LP_INTR_ST_S  25
+/** LP_INTR_MB_HP_INTR_ST : RO; bitpos: [26]; default: 0;
  *  need_des
  */
-#define LPINTR_MB_HP_INTR_ST    (BIT(26))
-#define LPINTR_MB_HP_INTR_ST_M  (LPINTR_MB_HP_INTR_ST_V << LPINTR_MB_HP_INTR_ST_S)
-#define LPINTR_MB_HP_INTR_ST_V  0x00000001U
-#define LPINTR_MB_HP_INTR_ST_S  26
-/** LPINTR_LP_TIMER_REG_1_INTR_ST : RO; bitpos: [27]; default: 0;
+#define LP_INTR_MB_HP_INTR_ST    (BIT(26))
+#define LP_INTR_MB_HP_INTR_ST_M  (LP_INTR_MB_HP_INTR_ST_V << LP_INTR_MB_HP_INTR_ST_S)
+#define LP_INTR_MB_HP_INTR_ST_V  0x00000001U
+#define LP_INTR_MB_HP_INTR_ST_S  26
+/** LP_INTR_LP_TIMER_REG_1_INTR_ST : RO; bitpos: [27]; default: 0;
  *  need_des
  */
-#define LPINTR_LP_TIMER_REG_1_INTR_ST    (BIT(27))
-#define LPINTR_LP_TIMER_REG_1_INTR_ST_M  (LPINTR_LP_TIMER_REG_1_INTR_ST_V << LPINTR_LP_TIMER_REG_1_INTR_ST_S)
-#define LPINTR_LP_TIMER_REG_1_INTR_ST_V  0x00000001U
-#define LPINTR_LP_TIMER_REG_1_INTR_ST_S  27
-/** LPINTR_LP_TIMER_REG_0_INTR_ST : RO; bitpos: [28]; default: 0;
+#define LP_INTR_LP_TIMER_REG_1_INTR_ST    (BIT(27))
+#define LP_INTR_LP_TIMER_REG_1_INTR_ST_M  (LP_INTR_LP_TIMER_REG_1_INTR_ST_V << LP_INTR_LP_TIMER_REG_1_INTR_ST_S)
+#define LP_INTR_LP_TIMER_REG_1_INTR_ST_V  0x00000001U
+#define LP_INTR_LP_TIMER_REG_1_INTR_ST_S  27
+/** LP_INTR_LP_TIMER_REG_0_INTR_ST : RO; bitpos: [28]; default: 0;
  *  need_des
  */
-#define LPINTR_LP_TIMER_REG_0_INTR_ST    (BIT(28))
-#define LPINTR_LP_TIMER_REG_0_INTR_ST_M  (LPINTR_LP_TIMER_REG_0_INTR_ST_V << LPINTR_LP_TIMER_REG_0_INTR_ST_S)
-#define LPINTR_LP_TIMER_REG_0_INTR_ST_V  0x00000001U
-#define LPINTR_LP_TIMER_REG_0_INTR_ST_S  28
-/** LPINTR_LP_WDT_INTR_ST : RO; bitpos: [29]; default: 0;
+#define LP_INTR_LP_TIMER_REG_0_INTR_ST    (BIT(28))
+#define LP_INTR_LP_TIMER_REG_0_INTR_ST_M  (LP_INTR_LP_TIMER_REG_0_INTR_ST_V << LP_INTR_LP_TIMER_REG_0_INTR_ST_S)
+#define LP_INTR_LP_TIMER_REG_0_INTR_ST_V  0x00000001U
+#define LP_INTR_LP_TIMER_REG_0_INTR_ST_S  28
+/** LP_INTR_LP_WDT_INTR_ST : RO; bitpos: [29]; default: 0;
  *  need_des
  */
-#define LPINTR_LP_WDT_INTR_ST    (BIT(29))
-#define LPINTR_LP_WDT_INTR_ST_M  (LPINTR_LP_WDT_INTR_ST_V << LPINTR_LP_WDT_INTR_ST_S)
-#define LPINTR_LP_WDT_INTR_ST_V  0x00000001U
-#define LPINTR_LP_WDT_INTR_ST_S  29
-/** LPINTR_LP_RTC_INTR_ST : RO; bitpos: [30]; default: 0;
+#define LP_INTR_LP_WDT_INTR_ST    (BIT(29))
+#define LP_INTR_LP_WDT_INTR_ST_M  (LP_INTR_LP_WDT_INTR_ST_V << LP_INTR_LP_WDT_INTR_ST_S)
+#define LP_INTR_LP_WDT_INTR_ST_V  0x00000001U
+#define LP_INTR_LP_WDT_INTR_ST_S  29
+/** LP_INTR_LP_RTC_INTR_ST : RO; bitpos: [30]; default: 0;
  *  need_des
  */
-#define LPINTR_LP_RTC_INTR_ST    (BIT(30))
-#define LPINTR_LP_RTC_INTR_ST_M  (LPINTR_LP_RTC_INTR_ST_V << LPINTR_LP_RTC_INTR_ST_S)
-#define LPINTR_LP_RTC_INTR_ST_V  0x00000001U
-#define LPINTR_LP_RTC_INTR_ST_S  30
-/** LPINTR_HP_INTR_ST : RO; bitpos: [31]; default: 0;
+#define LP_INTR_LP_RTC_INTR_ST    (BIT(30))
+#define LP_INTR_LP_RTC_INTR_ST_M  (LP_INTR_LP_RTC_INTR_ST_V << LP_INTR_LP_RTC_INTR_ST_S)
+#define LP_INTR_LP_RTC_INTR_ST_V  0x00000001U
+#define LP_INTR_LP_RTC_INTR_ST_S  30
+/** LP_INTR_HP_INTR_ST : RO; bitpos: [31]; default: 0;
  *  need_des
  */
-#define LPINTR_HP_INTR_ST    (BIT(31))
-#define LPINTR_HP_INTR_ST_M  (LPINTR_HP_INTR_ST_V << LPINTR_HP_INTR_ST_S)
-#define LPINTR_HP_INTR_ST_V  0x00000001U
-#define LPINTR_HP_INTR_ST_S  31
+#define LP_INTR_HP_INTR_ST    (BIT(31))
+#define LP_INTR_HP_INTR_ST_M  (LP_INTR_HP_INTR_ST_V << LP_INTR_HP_INTR_ST_S)
+#define LP_INTR_HP_INTR_ST_V  0x00000001U
+#define LP_INTR_HP_INTR_ST_S  31
 
-/** LPINTR_DATE_REG register
+/** LP_INTR_DATE_REG register
  *  need_des
  */
-#define LPINTR_DATE_REG (DR_REG_LPINTR_BASE + 0x3fc)
-/** LPINTR_CLK_EN : R/W; bitpos: [31]; default: 0;
+#define LP_INTR_DATE_REG (DR_REG_LP_INTR_BASE + 0x3fc)
+/** LP_INTR_CLK_EN : R/W; bitpos: [31]; default: 0;
  *  need_des
  */
-#define LPINTR_CLK_EN    (BIT(31))
-#define LPINTR_CLK_EN_M  (LPINTR_CLK_EN_V << LPINTR_CLK_EN_S)
-#define LPINTR_CLK_EN_V  0x00000001U
-#define LPINTR_CLK_EN_S  31
+#define LP_INTR_CLK_EN    (BIT(31))
+#define LP_INTR_CLK_EN_M  (LP_INTR_CLK_EN_V << LP_INTR_CLK_EN_S)
+#define LP_INTR_CLK_EN_V  0x00000001U
+#define LP_INTR_CLK_EN_S  31
 
 #ifdef __cplusplus
 }

components/soc/esp32p4/include/soc/lp_intr_struct.h

@@ -23,7 +23,7 @@ typedef union {
         uint32_t lp_sw_int_raw:1;
     };
     uint32_t val;
-} lpintr_sw_int_raw_reg_t;
+} lp_intr_sw_int_raw_reg_t;
 
 /** Type of sw_int_st register
  *  need_des
@@ -37,7 +37,7 @@ typedef union {
         uint32_t lp_sw_int_st:1;
     };
     uint32_t val;
-} lpintr_sw_int_st_reg_t;
+} lp_intr_sw_int_st_reg_t;
 
 /** Type of sw_int_ena register
  *  need_des
@@ -51,7 +51,7 @@ typedef union {
         uint32_t lp_sw_int_ena:1;
     };
     uint32_t val;
-} lpintr_sw_int_ena_reg_t;
+} lp_intr_sw_int_ena_reg_t;
 
 /** Type of sw_int_clr register
  *  need_des
@@ -65,7 +65,7 @@ typedef union {
         uint32_t lp_sw_int_clr:1;
     };
     uint32_t val;
-} lpintr_sw_int_clr_reg_t;
+} lp_intr_sw_int_clr_reg_t;
 
 
 /** Group: Status Registers */
@@ -165,7 +165,7 @@ typedef union {
         uint32_t hp_intr_st:1;
     };
     uint32_t val;
-} lpintr_status_reg_t;
+} lp_intr_status_reg_t;
 
 
 /** Group: configure_register */
@@ -181,22 +181,22 @@ typedef union {
         uint32_t clk_en:1;
     };
     uint32_t val;
-} lpintr_date_reg_t;
+} lp_intr_date_reg_t;
 
 
 typedef struct {
-    volatile lpintr_sw_int_raw_reg_t sw_int_raw;
-    volatile lpintr_sw_int_st_reg_t sw_int_st;
-    volatile lpintr_sw_int_ena_reg_t sw_int_ena;
-    volatile lpintr_sw_int_clr_reg_t sw_int_clr;
-    volatile lpintr_status_reg_t status;
+    volatile lp_intr_sw_int_raw_reg_t sw_int_raw;
+    volatile lp_intr_sw_int_st_reg_t sw_int_st;
+    volatile lp_intr_sw_int_ena_reg_t sw_int_ena;
+    volatile lp_intr_sw_int_clr_reg_t sw_int_clr;
+    volatile lp_intr_status_reg_t status;
     uint32_t reserved_014[250];
-    volatile lpintr_date_reg_t date;
-} lpintr_dev_t;
+    volatile lp_intr_date_reg_t date;
+} lp_intr_dev_t;
 
 
 #ifndef __cplusplus
-_Static_assert(sizeof(lpintr_dev_t) == 0x400, "Invalid size of lpintr_dev_t structure");
+_Static_assert(sizeof(lp_intr_dev_t) == 0x400, "Invalid size of lp_intr_dev_t structure");
 #endif
 
 #ifdef __cplusplus

components/soc/esp32p4/include/soc/lp_spi_reg.h

@@ -14,7 +14,7 @@ extern "C" {
 /** LP_SPI_CMD_REG register
  *  Command control register
  */
-#define LP_SPI_CMD_REG (DR_REG_LP_BASE + 0x0)
+#define LP_SPI_CMD_REG (DR_REG_LP_SPI_BASE + 0x0)
 /** LP_REG_UPDATE : WT; bitpos: [23]; default: 0;
  *  Set this bit to synchronize SPI registers from APB clock domain into SPI module
  *  clock domain, which is only used in SPI master mode.
@@ -36,7 +36,7 @@ extern "C" {
 /** LP_SPI_ADDR_REG register
  *  Address value register
  */
-#define LP_SPI_ADDR_REG (DR_REG_LP_BASE + 0x4)
+#define LP_SPI_ADDR_REG (DR_REG_LP_SPI_BASE + 0x4)
 /** LP_REG_USR_ADDR_VALUE : R/W; bitpos: [31:0]; default: 0;
  *  Address to slave. Can be configured in CONF state.
  */
@@ -48,7 +48,7 @@ extern "C" {
 /** LP_SPI_CTRL_REG register
  *  SPI control register
  */
-#define LP_SPI_CTRL_REG (DR_REG_LP_BASE + 0x8)
+#define LP_SPI_CTRL_REG (DR_REG_LP_SPI_BASE + 0x8)
 /** LP_REG_DUMMY_OUT : R/W; bitpos: [3]; default: 0;
  *  In the dummy phase the signal level of spi is output by the spi controller. Can be
  *  configured in CONF state.
@@ -93,7 +93,7 @@ extern "C" {
 /** LP_SPI_CLOCK_REG register
  *  SPI clock control register
  */
-#define LP_SPI_CLOCK_REG (DR_REG_LP_BASE + 0xc)
+#define LP_SPI_CLOCK_REG (DR_REG_LP_SPI_BASE + 0xc)
 /** LP_REG_CLKCNT_L : R/W; bitpos: [5:0]; default: 3;
  *  In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be
  *  0. Can be configured in CONF state.
@@ -137,7 +137,7 @@ extern "C" {
 /** LP_SPI_USER_REG register
  *  SPI USER control register
  */
-#define LP_SPI_USER_REG (DR_REG_LP_BASE + 0x10)
+#define LP_SPI_USER_REG (DR_REG_LP_SPI_BASE + 0x10)
 /** LP_REG_DOUTDIN : R/W; bitpos: [0]; default: 0;
  *  Set the bit to enable full duplex communication. 1: enable 0: disable. Can be
  *  configured in CONF state.
@@ -259,7 +259,7 @@ extern "C" {
 /** LP_SPI_USER1_REG register
  *  SPI USER control register 1
  */
-#define LP_SPI_USER1_REG (DR_REG_LP_BASE + 0x14)
+#define LP_SPI_USER1_REG (DR_REG_LP_SPI_BASE + 0x14)
 /** LP_REG_USR_DUMMY_CYCLELEN : R/W; bitpos: [7:0]; default: 7;
  *  The length in spi_clk cycles of dummy phase. The register value shall be
  *  (cycle_num-1). Can be configured in CONF state.
@@ -305,7 +305,7 @@ extern "C" {
 /** LP_SPI_USER2_REG register
  *  SPI USER control register 2
  */
-#define LP_SPI_USER2_REG (DR_REG_LP_BASE + 0x18)
+#define LP_SPI_USER2_REG (DR_REG_LP_SPI_BASE + 0x18)
 /** LP_REG_USR_COMMAND_VALUE : R/W; bitpos: [15:0]; default: 0;
  *  The value of  command. Can be configured in CONF state.
  */
@@ -334,7 +334,7 @@ extern "C" {
 /** LP_SPI_MS_DLEN_REG register
  *  SPI data bit length control register
  */
-#define LP_SPI_MS_DLEN_REG (DR_REG_LP_BASE + 0x1c)
+#define LP_SPI_MS_DLEN_REG (DR_REG_LP_SPI_BASE + 0x1c)
 /** LP_REG_MS_DATA_BITLEN : R/W; bitpos: [17:0]; default: 0;
  *  The value of these bits is the configured SPI transmission data bit length in
  *  master mode DMA controlled transfer or CPU controlled transfer. The value is also
@@ -349,7 +349,7 @@ extern "C" {
 /** LP_SPI_MISC_REG register
  *  SPI misc register
  */
-#define LP_SPI_MISC_REG (DR_REG_LP_BASE + 0x20)
+#define LP_SPI_MISC_REG (DR_REG_LP_SPI_BASE + 0x20)
 /** LP_REG_CS0_DIS : R/W; bitpos: [0]; default: 0;
  *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
  *  be configured in CONF state.
@@ -400,7 +400,7 @@ extern "C" {
 /** LP_SPI_DIN_MODE_REG register
  *  SPI input delay mode configuration
  */
-#define LP_SPI_DIN_MODE_REG (DR_REG_LP_BASE + 0x24)
+#define LP_SPI_DIN_MODE_REG (DR_REG_LP_SPI_BASE + 0x24)
 /** LP_REG_DIN0_MODE : R/W; bitpos: [1:0]; default: 0;
  *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
  *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
@@ -449,7 +449,7 @@ extern "C" {
 /** LP_SPI_DIN_NUM_REG register
  *  SPI input delay number configuration
  */
-#define LP_SPI_DIN_NUM_REG (DR_REG_LP_BASE + 0x28)
+#define LP_SPI_DIN_NUM_REG (DR_REG_LP_SPI_BASE + 0x28)
 /** LP_REG_DIN0_NUM : R/W; bitpos: [1:0]; default: 0;
  *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
  *  delayed by 2 cycles,...  Can be configured in CONF state.
@@ -486,7 +486,7 @@ extern "C" {
 /** LP_SPI_DOUT_MODE_REG register
  *  SPI output delay mode configuration
  */
-#define LP_SPI_DOUT_MODE_REG (DR_REG_LP_BASE + 0x2c)
+#define LP_SPI_DOUT_MODE_REG (DR_REG_LP_SPI_BASE + 0x2c)
 /** LP_REG_DOUT0_MODE : R/W; bitpos: [0]; default: 0;
  *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
  *  1: output delay for a SPI module clock cycle at its negative edge. Can be
@@ -527,7 +527,7 @@ extern "C" {
 /** LP_SPI_DMA_CONF_REG register
  *  SPI DMA control register
  */
-#define LP_SPI_DMA_CONF_REG (DR_REG_LP_BASE + 0x30)
+#define LP_SPI_DMA_CONF_REG (DR_REG_LP_SPI_BASE + 0x30)
 /** LP_REG_RX_AFIFO_RST : WT; bitpos: [29]; default: 0;
  *  Set this bit to reset RX AFIFO, which is used to receive data in SPI master and
  *  slave mode transfer.
@@ -548,7 +548,7 @@ extern "C" {
 /** LP_SPI_DMA_INT_ENA_REG register
  *  SPI DMA interrupt enable register
  */
-#define LP_SPI_DMA_INT_ENA_REG (DR_REG_LP_BASE + 0x34)
+#define LP_SPI_DMA_INT_ENA_REG (DR_REG_LP_SPI_BASE + 0x34)
 /** LP_REG_SLV_RD_BUF_DONE_INT_ENA : R/W; bitpos: [10]; default: 0;
  *  The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
  */
@@ -623,7 +623,7 @@ extern "C" {
 /** LP_SPI_DMA_INT_CLR_REG register
  *  SPI DMA interrupt clear register
  */
-#define LP_SPI_DMA_INT_CLR_REG (DR_REG_LP_BASE + 0x38)
+#define LP_SPI_DMA_INT_CLR_REG (DR_REG_LP_SPI_BASE + 0x38)
 /** LP_REG_SLV_RD_BUF_DONE_INT_CLR : WT; bitpos: [10]; default: 0;
  *  The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
  */
@@ -698,7 +698,7 @@ extern "C" {
 /** LP_SPI_DMA_INT_RAW_REG register
  *  SPI DMA interrupt raw register
  */
-#define LP_SPI_DMA_INT_RAW_REG (DR_REG_LP_BASE + 0x3c)
+#define LP_SPI_DMA_INT_RAW_REG (DR_REG_LP_SPI_BASE + 0x3c)
 /** LP_REG_SLV_RD_BUF_DONE_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
  *  The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF
  *  transmission is ended. 0: Others.
@@ -782,7 +782,7 @@ extern "C" {
 /** LP_SPI_DMA_INT_ST_REG register
  *  SPI DMA interrupt status register
  */
-#define LP_SPI_DMA_INT_ST_REG (DR_REG_LP_BASE + 0x40)
+#define LP_SPI_DMA_INT_ST_REG (DR_REG_LP_SPI_BASE + 0x40)
 /** LP_REG_SLV_RD_BUF_DONE_INT_ST : RO; bitpos: [10]; default: 0;
  *  The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
  */
@@ -857,7 +857,7 @@ extern "C" {
 /** LP_SPI_SLEEP_CONF0_REG register
  *  NA
  */
-#define LP_SPI_SLEEP_CONF0_REG (DR_REG_LP_BASE + 0x44)
+#define LP_SPI_SLEEP_CONF0_REG (DR_REG_LP_SPI_BASE + 0x44)
 /** LP_REG_SLV_WK_CHAR0 : R/W; bitpos: [7:0]; default: 10;
  *  NA
  */
@@ -911,7 +911,7 @@ extern "C" {
 /** LP_SPI_SLEEP_CONF1_REG register
  *  NA
  */
-#define LP_SPI_SLEEP_CONF1_REG (DR_REG_LP_BASE + 0x48)
+#define LP_SPI_SLEEP_CONF1_REG (DR_REG_LP_SPI_BASE + 0x48)
 /** LP_REG_SLV_WK_CHAR1 : R/W; bitpos: [7:0]; default: 11;
  *  NA
  */
@@ -944,7 +944,7 @@ extern "C" {
 /** LP_SPI_DMA_INT_SET_REG register
  *  SPI interrupt software set register
  */
-#define LP_SPI_DMA_INT_SET_REG (DR_REG_LP_BASE + 0x4c)
+#define LP_SPI_DMA_INT_SET_REG (DR_REG_LP_SPI_BASE + 0x4c)
 /** LP_SPI_SLV_RD_BUF_DONE_INT_SET : WT; bitpos: [10]; default: 0;
  *  The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
  */
@@ -1012,7 +1012,7 @@ extern "C" {
 /** LP_SPI_W0_REG register
  *  SPI CPU-controlled buffer0
  */
-#define LP_SPI_W0_REG (DR_REG_LP_BASE + 0x98)
+#define LP_SPI_W0_REG (DR_REG_LP_SPI_BASE + 0x98)
 /** LP_REG_BUF0 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
@@ -1024,7 +1024,7 @@ extern "C" {
 /** LP_SPI_W1_REG register
  *  SPI CPU-controlled buffer1
  */
-#define LP_SPI_W1_REG (DR_REG_LP_BASE + 0x9c)
+#define LP_SPI_W1_REG (DR_REG_LP_SPI_BASE + 0x9c)
 /** LP_REG_BUF1 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
@@ -1036,7 +1036,7 @@ extern "C" {
 /** LP_SPI_W2_REG register
  *  SPI CPU-controlled buffer2
  */
-#define LP_SPI_W2_REG (DR_REG_LP_BASE + 0xa0)
+#define LP_SPI_W2_REG (DR_REG_LP_SPI_BASE + 0xa0)
 /** LP_REG_BUF2 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
@@ -1048,7 +1048,7 @@ extern "C" {
 /** LP_SPI_W3_REG register
  *  SPI CPU-controlled buffer3
  */
-#define LP_SPI_W3_REG (DR_REG_LP_BASE + 0xa4)
+#define LP_SPI_W3_REG (DR_REG_LP_SPI_BASE + 0xa4)
 /** LP_REG_BUF3 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
@@ -1060,7 +1060,7 @@ extern "C" {
 /** LP_SPI_W4_REG register
  *  SPI CPU-controlled buffer4
  */
-#define LP_SPI_W4_REG (DR_REG_LP_BASE + 0xa8)
+#define LP_SPI_W4_REG (DR_REG_LP_SPI_BASE + 0xa8)
 /** LP_REG_BUF4 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
@@ -1072,7 +1072,7 @@ extern "C" {
 /** LP_SPI_W5_REG register
  *  SPI CPU-controlled buffer5
  */
-#define LP_SPI_W5_REG (DR_REG_LP_BASE + 0xac)
+#define LP_SPI_W5_REG (DR_REG_LP_SPI_BASE + 0xac)
 /** LP_REG_BUF5 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
@@ -1084,7 +1084,7 @@ extern "C" {
 /** LP_SPI_W6_REG register
  *  SPI CPU-controlled buffer6
  */
-#define LP_SPI_W6_REG (DR_REG_LP_BASE + 0xb0)
+#define LP_SPI_W6_REG (DR_REG_LP_SPI_BASE + 0xb0)
 /** LP_REG_BUF6 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
@@ -1096,7 +1096,7 @@ extern "C" {
 /** LP_SPI_W7_REG register
  *  SPI CPU-controlled buffer7
  */
-#define LP_SPI_W7_REG (DR_REG_LP_BASE + 0xb4)
+#define LP_SPI_W7_REG (DR_REG_LP_SPI_BASE + 0xb4)
 /** LP_REG_BUF7 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
@@ -1108,7 +1108,7 @@ extern "C" {
 /** LP_SPI_W8_REG register
  *  SPI CPU-controlled buffer8
  */
-#define LP_SPI_W8_REG (DR_REG_LP_BASE + 0xb8)
+#define LP_SPI_W8_REG (DR_REG_LP_SPI_BASE + 0xb8)
 /** LP_REG_BUF8 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
@@ -1120,7 +1120,7 @@ extern "C" {
 /** LP_SPI_W9_REG register
  *  SPI CPU-controlled buffer9
  */
-#define LP_SPI_W9_REG (DR_REG_LP_BASE + 0xbc)
+#define LP_SPI_W9_REG (DR_REG_LP_SPI_BASE + 0xbc)
 /** LP_REG_BUF9 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
@@ -1132,7 +1132,7 @@ extern "C" {
 /** LP_SPI_W10_REG register
  *  SPI CPU-controlled buffer10
  */
-#define LP_SPI_W10_REG (DR_REG_LP_BASE + 0xc0)
+#define LP_SPI_W10_REG (DR_REG_LP_SPI_BASE + 0xc0)
 /** LP_REG_BUF10 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
@@ -1144,7 +1144,7 @@ extern "C" {
 /** LP_SPI_W11_REG register
  *  SPI CPU-controlled buffer11
  */
-#define LP_SPI_W11_REG (DR_REG_LP_BASE + 0xc4)
+#define LP_SPI_W11_REG (DR_REG_LP_SPI_BASE + 0xc4)
 /** LP_REG_BUF11 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
@@ -1156,7 +1156,7 @@ extern "C" {
 /** LP_SPI_W12_REG register
  *  SPI CPU-controlled buffer12
  */
-#define LP_SPI_W12_REG (DR_REG_LP_BASE + 0xc8)
+#define LP_SPI_W12_REG (DR_REG_LP_SPI_BASE + 0xc8)
 /** LP_REG_BUF12 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
@@ -1168,7 +1168,7 @@ extern "C" {
 /** LP_SPI_W13_REG register
  *  SPI CPU-controlled buffer13
  */
-#define LP_SPI_W13_REG (DR_REG_LP_BASE + 0xcc)
+#define LP_SPI_W13_REG (DR_REG_LP_SPI_BASE + 0xcc)
 /** LP_REG_BUF13 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
@@ -1180,7 +1180,7 @@ extern "C" {
 /** LP_SPI_W14_REG register
  *  SPI CPU-controlled buffer14
  */
-#define LP_SPI_W14_REG (DR_REG_LP_BASE + 0xd0)
+#define LP_SPI_W14_REG (DR_REG_LP_SPI_BASE + 0xd0)
 /** LP_REG_BUF14 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
@@ -1192,7 +1192,7 @@ extern "C" {
 /** LP_SPI_W15_REG register
  *  SPI CPU-controlled buffer15
  */
-#define LP_SPI_W15_REG (DR_REG_LP_BASE + 0xd4)
+#define LP_SPI_W15_REG (DR_REG_LP_SPI_BASE + 0xd4)
 /** LP_REG_BUF15 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
@@ -1204,7 +1204,7 @@ extern "C" {
 /** LP_SPI_SLAVE_REG register
  *  SPI slave control register
  */
-#define LP_SPI_SLAVE_REG (DR_REG_LP_BASE + 0xe0)
+#define LP_SPI_SLAVE_REG (DR_REG_LP_SPI_BASE + 0xe0)
 /** LP_REG_CLK_MODE : R/W; bitpos: [1:0]; default: 0;
  *  SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed
  *  one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3:
@@ -1265,7 +1265,7 @@ extern "C" {
 /** LP_SPI_SLAVE1_REG register
  *  SPI slave control register 1
  */
-#define LP_SPI_SLAVE1_REG (DR_REG_LP_BASE + 0xe4)
+#define LP_SPI_SLAVE1_REG (DR_REG_LP_SPI_BASE + 0xe4)
 /** LP_REG_SLV_DATA_BITLEN : R/W/SS; bitpos: [17:0]; default: 0;
  *  The transferred data bit length in SPI slave FD and HD mode.
  */
@@ -1291,7 +1291,7 @@ extern "C" {
 /** LP_SPI_CLK_GATE_REG register
  *  SPI module clock and register clock control
  */
-#define LP_SPI_CLK_GATE_REG (DR_REG_LP_BASE + 0xe8)
+#define LP_SPI_CLK_GATE_REG (DR_REG_LP_SPI_BASE + 0xe8)
 /** LP_REG_CLK_EN : R/W; bitpos: [0]; default: 0;
  *  Set this bit to enable clk gate
  */
@@ -1318,7 +1318,7 @@ extern "C" {
 /** LP_SPI_DATE_REG register
  *  Version control
  */
-#define LP_SPI_DATE_REG (DR_REG_LP_BASE + 0xf0)
+#define LP_SPI_DATE_REG (DR_REG_LP_SPI_BASE + 0xf0)
 /** LP_REG_DATE : R/W; bitpos: [27:0]; default: 33591360;
  *  SPI register version.
  */
@@ -1330,7 +1330,7 @@ extern "C" {
 /** LP_RND_ECO_CS_REG register
  *  NA
  */
-#define LP_RND_ECO_CS_REG (DR_REG_LP_BASE + 0xf4)
+#define LP_RND_ECO_CS_REG (DR_REG_LP_SPI_BASE + 0xf4)
 /** LP_REG_RND_ECO_EN : R/W; bitpos: [0]; default: 0;
  *  NA
  */
@@ -1349,7 +1349,7 @@ extern "C" {
 /** LP_RND_ECO_LOW_REG register
  *  NA
  */
-#define LP_RND_ECO_LOW_REG (DR_REG_LP_BASE + 0xf8)
+#define LP_RND_ECO_LOW_REG (DR_REG_LP_SPI_BASE + 0xf8)
 /** LP_REG_RND_ECO_LOW : R/W; bitpos: [31:0]; default: 0;
  *  NA
  */
@@ -1361,7 +1361,7 @@ extern "C" {
 /** LP_RND_ECO_HIGH_REG register
  *  NA
  */
-#define LP_RND_ECO_HIGH_REG (DR_REG_LP_BASE + 0xfc)
+#define LP_RND_ECO_HIGH_REG (DR_REG_LP_SPI_BASE + 0xfc)
 /** LP_REG_RND_ECO_HIGH : R/W; bitpos: [31:0]; default: 65535;
  *  NA
  */

components/soc/esp32p4/include/soc/lp_sys_reg.h

@@ -1,1349 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** LPSYSREG_LP_SYS_VER_DATE_REG register
- *  need_des
- */
-#define LPSYSREG_LP_SYS_VER_DATE_REG (DR_REG_LP_SYS_BASE + 0x0)
-/** LPSYSREG_VER_DATE : R/W; bitpos: [31:0]; default: 539165961;
- *  need_des
- */
-#define LPSYSREG_VER_DATE    0xFFFFFFFFU
-#define LPSYSREG_VER_DATE_M  (LPSYSREG_VER_DATE_V << LPSYSREG_VER_DATE_S)
-#define LPSYSREG_VER_DATE_V  0xFFFFFFFFU
-#define LPSYSREG_VER_DATE_S  0
-
-/** LPSYSREG_CLK_SEL_CTRL_REG register
- *  need_des
- */
-#define LPSYSREG_CLK_SEL_CTRL_REG (DR_REG_LP_SYS_BASE + 0x4)
-/** LPSYSREG_ENA_SW_SEL_SYS_CLK : R/W; bitpos: [16]; default: 0;
- *  reserved
- */
-#define LPSYSREG_ENA_SW_SEL_SYS_CLK    (BIT(16))
-#define LPSYSREG_ENA_SW_SEL_SYS_CLK_M  (LPSYSREG_ENA_SW_SEL_SYS_CLK_V << LPSYSREG_ENA_SW_SEL_SYS_CLK_S)
-#define LPSYSREG_ENA_SW_SEL_SYS_CLK_V  0x00000001U
-#define LPSYSREG_ENA_SW_SEL_SYS_CLK_S  16
-/** LPSYSREG_SW_SYS_CLK_SRC_SEL : R/W; bitpos: [17]; default: 0;
- *  reserved
- */
-#define LPSYSREG_SW_SYS_CLK_SRC_SEL    (BIT(17))
-#define LPSYSREG_SW_SYS_CLK_SRC_SEL_M  (LPSYSREG_SW_SYS_CLK_SRC_SEL_V << LPSYSREG_SW_SYS_CLK_SRC_SEL_S)
-#define LPSYSREG_SW_SYS_CLK_SRC_SEL_V  0x00000001U
-#define LPSYSREG_SW_SYS_CLK_SRC_SEL_S  17
-
-/** LPSYSREG_SYS_CTRL_REG register
- *  need_des
- */
-#define LPSYSREG_SYS_CTRL_REG (DR_REG_LP_SYS_BASE + 0x8)
-/** LPSYSREG_LP_CORE_DISABLE : R/W; bitpos: [0]; default: 0;
- *  lp cpu disable
- */
-#define LPSYSREG_LP_CORE_DISABLE    (BIT(0))
-#define LPSYSREG_LP_CORE_DISABLE_M  (LPSYSREG_LP_CORE_DISABLE_V << LPSYSREG_LP_CORE_DISABLE_S)
-#define LPSYSREG_LP_CORE_DISABLE_V  0x00000001U
-#define LPSYSREG_LP_CORE_DISABLE_S  0
-/** LPSYSREG_SYS_SW_RST : WT; bitpos: [1]; default: 0;
- *  digital system software reset bit
- */
-#define LPSYSREG_SYS_SW_RST    (BIT(1))
-#define LPSYSREG_SYS_SW_RST_M  (LPSYSREG_SYS_SW_RST_V << LPSYSREG_SYS_SW_RST_S)
-#define LPSYSREG_SYS_SW_RST_V  0x00000001U
-#define LPSYSREG_SYS_SW_RST_S  1
-/** LPSYSREG_FORCE_DOWNLOAD_BOOT : R/W; bitpos: [2]; default: 0;
- *  need_des
- */
-#define LPSYSREG_FORCE_DOWNLOAD_BOOT    (BIT(2))
-#define LPSYSREG_FORCE_DOWNLOAD_BOOT_M  (LPSYSREG_FORCE_DOWNLOAD_BOOT_V << LPSYSREG_FORCE_DOWNLOAD_BOOT_S)
-#define LPSYSREG_FORCE_DOWNLOAD_BOOT_V  0x00000001U
-#define LPSYSREG_FORCE_DOWNLOAD_BOOT_S  2
-/** LPSYSREG_DIG_FIB : R/W; bitpos: [10:3]; default: 255;
- *  need_des
- */
-#define LPSYSREG_DIG_FIB    0x000000FFU
-#define LPSYSREG_DIG_FIB_M  (LPSYSREG_DIG_FIB_V << LPSYSREG_DIG_FIB_S)
-#define LPSYSREG_DIG_FIB_V  0x000000FFU
-#define LPSYSREG_DIG_FIB_S  3
-/** LPSYSREG_IO_MUX_RESET_DISABLE : R/W; bitpos: [11]; default: 0;
- *  reset disable bit for LP IOMUX
- */
-#define LPSYSREG_IO_MUX_RESET_DISABLE    (BIT(11))
-#define LPSYSREG_IO_MUX_RESET_DISABLE_M  (LPSYSREG_IO_MUX_RESET_DISABLE_V << LPSYSREG_IO_MUX_RESET_DISABLE_S)
-#define LPSYSREG_IO_MUX_RESET_DISABLE_V  0x00000001U
-#define LPSYSREG_IO_MUX_RESET_DISABLE_S  11
-/** LPSYSREG_ANA_FIB : RO; bitpos: [20:14]; default: 127;
- *  need_des
- */
-#define LPSYSREG_ANA_FIB    0x0000007FU
-#define LPSYSREG_ANA_FIB_M  (LPSYSREG_ANA_FIB_V << LPSYSREG_ANA_FIB_S)
-#define LPSYSREG_ANA_FIB_V  0x0000007FU
-#define LPSYSREG_ANA_FIB_S  14
-/** LPSYSREG_LP_FIB_SEL : R/W; bitpos: [28:21]; default: 255;
- *  need_des
- */
-#define LPSYSREG_LP_FIB_SEL    0x000000FFU
-#define LPSYSREG_LP_FIB_SEL_M  (LPSYSREG_LP_FIB_SEL_V << LPSYSREG_LP_FIB_SEL_S)
-#define LPSYSREG_LP_FIB_SEL_V  0x000000FFU
-#define LPSYSREG_LP_FIB_SEL_S  21
-/** LPSYSREG_LP_CORE_ETM_WAKEUP_FLAG_CLR : WT; bitpos: [29]; default: 0;
- *  need_des
- */
-#define LPSYSREG_LP_CORE_ETM_WAKEUP_FLAG_CLR    (BIT(29))
-#define LPSYSREG_LP_CORE_ETM_WAKEUP_FLAG_CLR_M  (LPSYSREG_LP_CORE_ETM_WAKEUP_FLAG_CLR_V << LPSYSREG_LP_CORE_ETM_WAKEUP_FLAG_CLR_S)
-#define LPSYSREG_LP_CORE_ETM_WAKEUP_FLAG_CLR_V  0x00000001U
-#define LPSYSREG_LP_CORE_ETM_WAKEUP_FLAG_CLR_S  29
-/** LPSYSREG_LP_CORE_ETM_WAKEUP_FLAG : R/WTC/SS; bitpos: [30]; default: 0;
- *  need_des
- */
-#define LPSYSREG_LP_CORE_ETM_WAKEUP_FLAG    (BIT(30))
-#define LPSYSREG_LP_CORE_ETM_WAKEUP_FLAG_M  (LPSYSREG_LP_CORE_ETM_WAKEUP_FLAG_V << LPSYSREG_LP_CORE_ETM_WAKEUP_FLAG_S)
-#define LPSYSREG_LP_CORE_ETM_WAKEUP_FLAG_V  0x00000001U
-#define LPSYSREG_LP_CORE_ETM_WAKEUP_FLAG_S  30
-/** LPSYSREG_SYSTIMER_STALL_SEL : R/W; bitpos: [31]; default: 0;
- *  0: use systimer_stall signal from hp_core0, 1: use systimer_stall signal from
- *  hp_core1
- */
-#define LPSYSREG_SYSTIMER_STALL_SEL    (BIT(31))
-#define LPSYSREG_SYSTIMER_STALL_SEL_M  (LPSYSREG_SYSTIMER_STALL_SEL_V << LPSYSREG_SYSTIMER_STALL_SEL_S)
-#define LPSYSREG_SYSTIMER_STALL_SEL_V  0x00000001U
-#define LPSYSREG_SYSTIMER_STALL_SEL_S  31
-
-/** LPSYSREG_LP_CLK_CTRL_REG register
- *  need_des
- */
-#define LPSYSREG_LP_CLK_CTRL_REG (DR_REG_LP_SYS_BASE + 0xc)
-/** LPSYSREG_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  need_des
- */
-#define LPSYSREG_CLK_EN    (BIT(0))
-#define LPSYSREG_CLK_EN_M  (LPSYSREG_CLK_EN_V << LPSYSREG_CLK_EN_S)
-#define LPSYSREG_CLK_EN_V  0x00000001U
-#define LPSYSREG_CLK_EN_S  0
-/** LPSYSREG_LP_FOSC_HP_CKEN : R/W; bitpos: [14]; default: 1;
- *  reserved
- */
-#define LPSYSREG_LP_FOSC_HP_CKEN    (BIT(14))
-#define LPSYSREG_LP_FOSC_HP_CKEN_M  (LPSYSREG_LP_FOSC_HP_CKEN_V << LPSYSREG_LP_FOSC_HP_CKEN_S)
-#define LPSYSREG_LP_FOSC_HP_CKEN_V  0x00000001U
-#define LPSYSREG_LP_FOSC_HP_CKEN_S  14
-
-/** LPSYSREG_LP_RST_CTRL_REG register
- *  need_des
- */
-#define LPSYSREG_LP_RST_CTRL_REG (DR_REG_LP_SYS_BASE + 0x10)
-/** LPSYSREG_ANA_RST_BYPASS : R/W; bitpos: [0]; default: 1;
- *  analog source reset bypass : wdt,brown out,super wdt,glitch
- */
-#define LPSYSREG_ANA_RST_BYPASS    (BIT(0))
-#define LPSYSREG_ANA_RST_BYPASS_M  (LPSYSREG_ANA_RST_BYPASS_V << LPSYSREG_ANA_RST_BYPASS_S)
-#define LPSYSREG_ANA_RST_BYPASS_V  0x00000001U
-#define LPSYSREG_ANA_RST_BYPASS_S  0
-/** LPSYSREG_SYS_RST_BYPASS : R/W; bitpos: [1]; default: 1;
- *  system source reset bypass : software reset,hp wdt,lp wdt,efuse
- */
-#define LPSYSREG_SYS_RST_BYPASS    (BIT(1))
-#define LPSYSREG_SYS_RST_BYPASS_M  (LPSYSREG_SYS_RST_BYPASS_V << LPSYSREG_SYS_RST_BYPASS_S)
-#define LPSYSREG_SYS_RST_BYPASS_V  0x00000001U
-#define LPSYSREG_SYS_RST_BYPASS_S  1
-/** LPSYSREG_EFUSE_FORCE_NORST : R/W; bitpos: [2]; default: 0;
- *  efuse force no reset control
- */
-#define LPSYSREG_EFUSE_FORCE_NORST    (BIT(2))
-#define LPSYSREG_EFUSE_FORCE_NORST_M  (LPSYSREG_EFUSE_FORCE_NORST_V << LPSYSREG_EFUSE_FORCE_NORST_S)
-#define LPSYSREG_EFUSE_FORCE_NORST_V  0x00000001U
-#define LPSYSREG_EFUSE_FORCE_NORST_S  2
-
-/** LPSYSREG_LP_CORE_BOOT_ADDR_REG register
- *  need_des
- */
-#define LPSYSREG_LP_CORE_BOOT_ADDR_REG (DR_REG_LP_SYS_BASE + 0x18)
-/** LPSYSREG_LP_CPU_BOOT_ADDR : R/W; bitpos: [31:0]; default: 1343225856;
- *  need_des
- */
-#define LPSYSREG_LP_CPU_BOOT_ADDR    0xFFFFFFFFU
-#define LPSYSREG_LP_CPU_BOOT_ADDR_M  (LPSYSREG_LP_CPU_BOOT_ADDR_V << LPSYSREG_LP_CPU_BOOT_ADDR_S)
-#define LPSYSREG_LP_CPU_BOOT_ADDR_V  0xFFFFFFFFU
-#define LPSYSREG_LP_CPU_BOOT_ADDR_S  0
-
-/** LPSYSREG_EXT_WAKEUP1_REG register
- *  need_des
- */
-#define LPSYSREG_EXT_WAKEUP1_REG (DR_REG_LP_SYS_BASE + 0x1c)
-/** LPSYSREG_EXT_WAKEUP1_SEL : R/W; bitpos: [15:0]; default: 0;
- *  Bitmap to select RTC pads for ext wakeup1
- */
-#define LPSYSREG_EXT_WAKEUP1_SEL    0x0000FFFFU
-#define LPSYSREG_EXT_WAKEUP1_SEL_M  (LPSYSREG_EXT_WAKEUP1_SEL_V << LPSYSREG_EXT_WAKEUP1_SEL_S)
-#define LPSYSREG_EXT_WAKEUP1_SEL_V  0x0000FFFFU
-#define LPSYSREG_EXT_WAKEUP1_SEL_S  0
-/** LPSYSREG_EXT_WAKEUP1_STATUS_CLR : WT; bitpos: [16]; default: 0;
- *  clear ext wakeup1 status
- */
-#define LPSYSREG_EXT_WAKEUP1_STATUS_CLR    (BIT(16))
-#define LPSYSREG_EXT_WAKEUP1_STATUS_CLR_M  (LPSYSREG_EXT_WAKEUP1_STATUS_CLR_V << LPSYSREG_EXT_WAKEUP1_STATUS_CLR_S)
-#define LPSYSREG_EXT_WAKEUP1_STATUS_CLR_V  0x00000001U
-#define LPSYSREG_EXT_WAKEUP1_STATUS_CLR_S  16
-
-/** LPSYSREG_EXT_WAKEUP1_STATUS_REG register
- *  need_des
- */
-#define LPSYSREG_EXT_WAKEUP1_STATUS_REG (DR_REG_LP_SYS_BASE + 0x20)
-/** LPSYSREG_EXT_WAKEUP1_STATUS : RO; bitpos: [15:0]; default: 0;
- *  ext wakeup1 status
- */
-#define LPSYSREG_EXT_WAKEUP1_STATUS    0x0000FFFFU
-#define LPSYSREG_EXT_WAKEUP1_STATUS_M  (LPSYSREG_EXT_WAKEUP1_STATUS_V << LPSYSREG_EXT_WAKEUP1_STATUS_S)
-#define LPSYSREG_EXT_WAKEUP1_STATUS_V  0x0000FFFFU
-#define LPSYSREG_EXT_WAKEUP1_STATUS_S  0
-
-/** LPSYSREG_LP_TCM_PWR_CTRL_REG register
- *  need_des
- */
-#define LPSYSREG_LP_TCM_PWR_CTRL_REG (DR_REG_LP_SYS_BASE + 0x24)
-/** LPSYSREG_LP_TCM_ROM_CLK_FORCE_ON : R/W; bitpos: [5]; default: 0;
- *  need_des
- */
-#define LPSYSREG_LP_TCM_ROM_CLK_FORCE_ON    (BIT(5))
-#define LPSYSREG_LP_TCM_ROM_CLK_FORCE_ON_M  (LPSYSREG_LP_TCM_ROM_CLK_FORCE_ON_V << LPSYSREG_LP_TCM_ROM_CLK_FORCE_ON_S)
-#define LPSYSREG_LP_TCM_ROM_CLK_FORCE_ON_V  0x00000001U
-#define LPSYSREG_LP_TCM_ROM_CLK_FORCE_ON_S  5
-/** LPSYSREG_LP_TCM_RAM_CLK_FORCE_ON : R/W; bitpos: [7]; default: 0;
- *  need_des
- */
-#define LPSYSREG_LP_TCM_RAM_CLK_FORCE_ON    (BIT(7))
-#define LPSYSREG_LP_TCM_RAM_CLK_FORCE_ON_M  (LPSYSREG_LP_TCM_RAM_CLK_FORCE_ON_V << LPSYSREG_LP_TCM_RAM_CLK_FORCE_ON_S)
-#define LPSYSREG_LP_TCM_RAM_CLK_FORCE_ON_V  0x00000001U
-#define LPSYSREG_LP_TCM_RAM_CLK_FORCE_ON_S  7
-
-/** LPSYSREG_BOOT_ADDR_HP_LP_REG_REG register
- *  need_des
- */
-#define LPSYSREG_BOOT_ADDR_HP_LP_REG_REG (DR_REG_LP_SYS_BASE + 0x28)
-/** LPSYSREG_BOOT_ADDR_HP_LP : R/W; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define LPSYSREG_BOOT_ADDR_HP_LP    0xFFFFFFFFU
-#define LPSYSREG_BOOT_ADDR_HP_LP_M  (LPSYSREG_BOOT_ADDR_HP_LP_V << LPSYSREG_BOOT_ADDR_HP_LP_S)
-#define LPSYSREG_BOOT_ADDR_HP_LP_V  0xFFFFFFFFU
-#define LPSYSREG_BOOT_ADDR_HP_LP_S  0
-
-/** LPSYSREG_LP_STORE0_REG register
- *  need_des
- */
-#define LPSYSREG_LP_STORE0_REG (DR_REG_LP_SYS_BASE + 0x2c)
-/** LPSYSREG_LP_SCRATCH0 : R/W; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define LPSYSREG_LP_SCRATCH0    0xFFFFFFFFU
-#define LPSYSREG_LP_SCRATCH0_M  (LPSYSREG_LP_SCRATCH0_V << LPSYSREG_LP_SCRATCH0_S)
-#define LPSYSREG_LP_SCRATCH0_V  0xFFFFFFFFU
-#define LPSYSREG_LP_SCRATCH0_S  0
-
-/** LPSYSREG_LP_STORE1_REG register
- *  need_des
- */
-#define LPSYSREG_LP_STORE1_REG (DR_REG_LP_SYS_BASE + 0x30)
-/** LPSYSREG_LP_SCRATCH1 : R/W; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define LPSYSREG_LP_SCRATCH1    0xFFFFFFFFU
-#define LPSYSREG_LP_SCRATCH1_M  (LPSYSREG_LP_SCRATCH1_V << LPSYSREG_LP_SCRATCH1_S)
-#define LPSYSREG_LP_SCRATCH1_V  0xFFFFFFFFU
-#define LPSYSREG_LP_SCRATCH1_S  0
-
-/** LPSYSREG_LP_STORE2_REG register
- *  need_des
- */
-#define LPSYSREG_LP_STORE2_REG (DR_REG_LP_SYS_BASE + 0x34)
-/** LPSYSREG_LP_SCRATCH2 : R/W; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define LPSYSREG_LP_SCRATCH2    0xFFFFFFFFU
-#define LPSYSREG_LP_SCRATCH2_M  (LPSYSREG_LP_SCRATCH2_V << LPSYSREG_LP_SCRATCH2_S)
-#define LPSYSREG_LP_SCRATCH2_V  0xFFFFFFFFU
-#define LPSYSREG_LP_SCRATCH2_S  0
-
-/** LPSYSREG_LP_STORE3_REG register
- *  need_des
- */
-#define LPSYSREG_LP_STORE3_REG (DR_REG_LP_SYS_BASE + 0x38)
-/** LPSYSREG_LP_SCRATCH3 : R/W; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define LPSYSREG_LP_SCRATCH3    0xFFFFFFFFU
-#define LPSYSREG_LP_SCRATCH3_M  (LPSYSREG_LP_SCRATCH3_V << LPSYSREG_LP_SCRATCH3_S)
-#define LPSYSREG_LP_SCRATCH3_V  0xFFFFFFFFU
-#define LPSYSREG_LP_SCRATCH3_S  0
-
-/** LPSYSREG_LP_STORE4_REG register
- *  need_des
- */
-#define LPSYSREG_LP_STORE4_REG (DR_REG_LP_SYS_BASE + 0x3c)
-/** LPSYSREG_LP_SCRATCH4 : R/W; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define LPSYSREG_LP_SCRATCH4    0xFFFFFFFFU
-#define LPSYSREG_LP_SCRATCH4_M  (LPSYSREG_LP_SCRATCH4_V << LPSYSREG_LP_SCRATCH4_S)
-#define LPSYSREG_LP_SCRATCH4_V  0xFFFFFFFFU
-#define LPSYSREG_LP_SCRATCH4_S  0
-
-/** LPSYSREG_LP_STORE5_REG register
- *  need_des
- */
-#define LPSYSREG_LP_STORE5_REG (DR_REG_LP_SYS_BASE + 0x40)
-/** LPSYSREG_LP_SCRATCH5 : R/W; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define LPSYSREG_LP_SCRATCH5    0xFFFFFFFFU
-#define LPSYSREG_LP_SCRATCH5_M  (LPSYSREG_LP_SCRATCH5_V << LPSYSREG_LP_SCRATCH5_S)
-#define LPSYSREG_LP_SCRATCH5_V  0xFFFFFFFFU
-#define LPSYSREG_LP_SCRATCH5_S  0
-
-/** LPSYSREG_LP_STORE6_REG register
- *  need_des
- */
-#define LPSYSREG_LP_STORE6_REG (DR_REG_LP_SYS_BASE + 0x44)
-/** LPSYSREG_LP_SCRATCH6 : R/W; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define LPSYSREG_LP_SCRATCH6    0xFFFFFFFFU
-#define LPSYSREG_LP_SCRATCH6_M  (LPSYSREG_LP_SCRATCH6_V << LPSYSREG_LP_SCRATCH6_S)
-#define LPSYSREG_LP_SCRATCH6_V  0xFFFFFFFFU
-#define LPSYSREG_LP_SCRATCH6_S  0
-
-/** LPSYSREG_LP_STORE7_REG register
- *  need_des
- */
-#define LPSYSREG_LP_STORE7_REG (DR_REG_LP_SYS_BASE + 0x48)
-/** LPSYSREG_LP_SCRATCH7 : R/W; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define LPSYSREG_LP_SCRATCH7    0xFFFFFFFFU
-#define LPSYSREG_LP_SCRATCH7_M  (LPSYSREG_LP_SCRATCH7_V << LPSYSREG_LP_SCRATCH7_S)
-#define LPSYSREG_LP_SCRATCH7_V  0xFFFFFFFFU
-#define LPSYSREG_LP_SCRATCH7_S  0
-
-/** LPSYSREG_LP_STORE8_REG register
- *  need_des
- */
-#define LPSYSREG_LP_STORE8_REG (DR_REG_LP_SYS_BASE + 0x4c)
-/** LPSYSREG_LP_SCRATCH8 : R/W; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define LPSYSREG_LP_SCRATCH8    0xFFFFFFFFU
-#define LPSYSREG_LP_SCRATCH8_M  (LPSYSREG_LP_SCRATCH8_V << LPSYSREG_LP_SCRATCH8_S)
-#define LPSYSREG_LP_SCRATCH8_V  0xFFFFFFFFU
-#define LPSYSREG_LP_SCRATCH8_S  0
-
-/** LPSYSREG_LP_STORE9_REG register
- *  need_des
- */
-#define LPSYSREG_LP_STORE9_REG (DR_REG_LP_SYS_BASE + 0x50)
-/** LPSYSREG_LP_SCRATCH9 : R/W; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define LPSYSREG_LP_SCRATCH9    0xFFFFFFFFU
-#define LPSYSREG_LP_SCRATCH9_M  (LPSYSREG_LP_SCRATCH9_V << LPSYSREG_LP_SCRATCH9_S)
-#define LPSYSREG_LP_SCRATCH9_V  0xFFFFFFFFU
-#define LPSYSREG_LP_SCRATCH9_S  0
-
-/** LPSYSREG_LP_STORE10_REG register
- *  need_des
- */
-#define LPSYSREG_LP_STORE10_REG (DR_REG_LP_SYS_BASE + 0x54)
-/** LPSYSREG_LP_SCRATCH10 : R/W; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define LPSYSREG_LP_SCRATCH10    0xFFFFFFFFU
-#define LPSYSREG_LP_SCRATCH10_M  (LPSYSREG_LP_SCRATCH10_V << LPSYSREG_LP_SCRATCH10_S)
-#define LPSYSREG_LP_SCRATCH10_V  0xFFFFFFFFU
-#define LPSYSREG_LP_SCRATCH10_S  0
-
-/** LPSYSREG_LP_STORE11_REG register
- *  need_des
- */
-#define LPSYSREG_LP_STORE11_REG (DR_REG_LP_SYS_BASE + 0x58)
-/** LPSYSREG_LP_SCRATCH11 : R/W; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define LPSYSREG_LP_SCRATCH11    0xFFFFFFFFU
-#define LPSYSREG_LP_SCRATCH11_M  (LPSYSREG_LP_SCRATCH11_V << LPSYSREG_LP_SCRATCH11_S)
-#define LPSYSREG_LP_SCRATCH11_V  0xFFFFFFFFU
-#define LPSYSREG_LP_SCRATCH11_S  0
-
-/** LPSYSREG_LP_STORE12_REG register
- *  need_des
- */
-#define LPSYSREG_LP_STORE12_REG (DR_REG_LP_SYS_BASE + 0x5c)
-/** LPSYSREG_LP_SCRATCH12 : R/W; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define LPSYSREG_LP_SCRATCH12    0xFFFFFFFFU
-#define LPSYSREG_LP_SCRATCH12_M  (LPSYSREG_LP_SCRATCH12_V << LPSYSREG_LP_SCRATCH12_S)
-#define LPSYSREG_LP_SCRATCH12_V  0xFFFFFFFFU
-#define LPSYSREG_LP_SCRATCH12_S  0
-
-/** LPSYSREG_LP_STORE13_REG register
- *  need_des
- */
-#define LPSYSREG_LP_STORE13_REG (DR_REG_LP_SYS_BASE + 0x60)
-/** LPSYSREG_LP_SCRATCH13 : R/W; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define LPSYSREG_LP_SCRATCH13    0xFFFFFFFFU
-#define LPSYSREG_LP_SCRATCH13_M  (LPSYSREG_LP_SCRATCH13_V << LPSYSREG_LP_SCRATCH13_S)
-#define LPSYSREG_LP_SCRATCH13_V  0xFFFFFFFFU
-#define LPSYSREG_LP_SCRATCH13_S  0
-
-/** LPSYSREG_LP_STORE14_REG register
- *  need_des
- */
-#define LPSYSREG_LP_STORE14_REG (DR_REG_LP_SYS_BASE + 0x64)
-/** LPSYSREG_LP_SCRATCH14 : R/W; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define LPSYSREG_LP_SCRATCH14    0xFFFFFFFFU
-#define LPSYSREG_LP_SCRATCH14_M  (LPSYSREG_LP_SCRATCH14_V << LPSYSREG_LP_SCRATCH14_S)
-#define LPSYSREG_LP_SCRATCH14_V  0xFFFFFFFFU
-#define LPSYSREG_LP_SCRATCH14_S  0
-
-/** LPSYSREG_LP_STORE15_REG register
- *  need_des
- */
-#define LPSYSREG_LP_STORE15_REG (DR_REG_LP_SYS_BASE + 0x68)
-/** LPSYSREG_LP_SCRATCH15 : R/W; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define LPSYSREG_LP_SCRATCH15    0xFFFFFFFFU
-#define LPSYSREG_LP_SCRATCH15_M  (LPSYSREG_LP_SCRATCH15_V << LPSYSREG_LP_SCRATCH15_S)
-#define LPSYSREG_LP_SCRATCH15_V  0xFFFFFFFFU
-#define LPSYSREG_LP_SCRATCH15_S  0
-
-/** LPSYSREG_LP_PROBEA_CTRL_REG register
- *  need_des
- */
-#define LPSYSREG_LP_PROBEA_CTRL_REG (DR_REG_LP_SYS_BASE + 0x6c)
-/** LPSYSREG_PROBE_A_MOD_SEL : R/W; bitpos: [15:0]; default: 0;
- *  need_des
- */
-#define LPSYSREG_PROBE_A_MOD_SEL    0x0000FFFFU
-#define LPSYSREG_PROBE_A_MOD_SEL_M  (LPSYSREG_PROBE_A_MOD_SEL_V << LPSYSREG_PROBE_A_MOD_SEL_S)
-#define LPSYSREG_PROBE_A_MOD_SEL_V  0x0000FFFFU
-#define LPSYSREG_PROBE_A_MOD_SEL_S  0
-/** LPSYSREG_PROBE_A_TOP_SEL : R/W; bitpos: [23:16]; default: 0;
- *  need_des
- */
-#define LPSYSREG_PROBE_A_TOP_SEL    0x000000FFU
-#define LPSYSREG_PROBE_A_TOP_SEL_M  (LPSYSREG_PROBE_A_TOP_SEL_V << LPSYSREG_PROBE_A_TOP_SEL_S)
-#define LPSYSREG_PROBE_A_TOP_SEL_V  0x000000FFU
-#define LPSYSREG_PROBE_A_TOP_SEL_S  16
-/** LPSYSREG_PROBE_L_SEL : R/W; bitpos: [25:24]; default: 0;
- *  need_des
- */
-#define LPSYSREG_PROBE_L_SEL    0x00000003U
-#define LPSYSREG_PROBE_L_SEL_M  (LPSYSREG_PROBE_L_SEL_V << LPSYSREG_PROBE_L_SEL_S)
-#define LPSYSREG_PROBE_L_SEL_V  0x00000003U
-#define LPSYSREG_PROBE_L_SEL_S  24
-/** LPSYSREG_PROBE_H_SEL : R/W; bitpos: [27:26]; default: 0;
- *  need_des
- */
-#define LPSYSREG_PROBE_H_SEL    0x00000003U
-#define LPSYSREG_PROBE_H_SEL_M  (LPSYSREG_PROBE_H_SEL_V << LPSYSREG_PROBE_H_SEL_S)
-#define LPSYSREG_PROBE_H_SEL_V  0x00000003U
-#define LPSYSREG_PROBE_H_SEL_S  26
-/** LPSYSREG_PROBE_GLOBAL_EN : R/W; bitpos: [28]; default: 0;
- *  need_des
- */
-#define LPSYSREG_PROBE_GLOBAL_EN    (BIT(28))
-#define LPSYSREG_PROBE_GLOBAL_EN_M  (LPSYSREG_PROBE_GLOBAL_EN_V << LPSYSREG_PROBE_GLOBAL_EN_S)
-#define LPSYSREG_PROBE_GLOBAL_EN_V  0x00000001U
-#define LPSYSREG_PROBE_GLOBAL_EN_S  28
-
-/** LPSYSREG_LP_PROBEB_CTRL_REG register
- *  need_des
- */
-#define LPSYSREG_LP_PROBEB_CTRL_REG (DR_REG_LP_SYS_BASE + 0x70)
-/** LPSYSREG_PROBE_B_MOD_SEL : R/W; bitpos: [15:0]; default: 0;
- *  need_des
- */
-#define LPSYSREG_PROBE_B_MOD_SEL    0x0000FFFFU
-#define LPSYSREG_PROBE_B_MOD_SEL_M  (LPSYSREG_PROBE_B_MOD_SEL_V << LPSYSREG_PROBE_B_MOD_SEL_S)
-#define LPSYSREG_PROBE_B_MOD_SEL_V  0x0000FFFFU
-#define LPSYSREG_PROBE_B_MOD_SEL_S  0
-/** LPSYSREG_PROBE_B_TOP_SEL : R/W; bitpos: [23:16]; default: 0;
- *  need_des
- */
-#define LPSYSREG_PROBE_B_TOP_SEL    0x000000FFU
-#define LPSYSREG_PROBE_B_TOP_SEL_M  (LPSYSREG_PROBE_B_TOP_SEL_V << LPSYSREG_PROBE_B_TOP_SEL_S)
-#define LPSYSREG_PROBE_B_TOP_SEL_V  0x000000FFU
-#define LPSYSREG_PROBE_B_TOP_SEL_S  16
-/** LPSYSREG_PROBE_B_EN : R/W; bitpos: [24]; default: 0;
- *  need_des
- */
-#define LPSYSREG_PROBE_B_EN    (BIT(24))
-#define LPSYSREG_PROBE_B_EN_M  (LPSYSREG_PROBE_B_EN_V << LPSYSREG_PROBE_B_EN_S)
-#define LPSYSREG_PROBE_B_EN_V  0x00000001U
-#define LPSYSREG_PROBE_B_EN_S  24
-
-/** LPSYSREG_LP_PROBE_OUT_REG register
- *  need_des
- */
-#define LPSYSREG_LP_PROBE_OUT_REG (DR_REG_LP_SYS_BASE + 0x74)
-/** LPSYSREG_PROBE_TOP_OUT : RO; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define LPSYSREG_PROBE_TOP_OUT    0xFFFFFFFFU
-#define LPSYSREG_PROBE_TOP_OUT_M  (LPSYSREG_PROBE_TOP_OUT_V << LPSYSREG_PROBE_TOP_OUT_S)
-#define LPSYSREG_PROBE_TOP_OUT_V  0xFFFFFFFFU
-#define LPSYSREG_PROBE_TOP_OUT_S  0
-
-/** LPSYSREG_F2S_APB_BRG_CNTL_REG register
- *  need_des
- */
-#define LPSYSREG_F2S_APB_BRG_CNTL_REG (DR_REG_LP_SYS_BASE + 0x9c)
-/** LPSYSREG_F2S_APB_POSTW_EN : R/W; bitpos: [0]; default: 0;
- *  reserved
- */
-#define LPSYSREG_F2S_APB_POSTW_EN    (BIT(0))
-#define LPSYSREG_F2S_APB_POSTW_EN_M  (LPSYSREG_F2S_APB_POSTW_EN_V << LPSYSREG_F2S_APB_POSTW_EN_S)
-#define LPSYSREG_F2S_APB_POSTW_EN_V  0x00000001U
-#define LPSYSREG_F2S_APB_POSTW_EN_S  0
-
-/** LPSYSREG_USB_CTRL_REG register
- *  need_des
- */
-#define LPSYSREG_USB_CTRL_REG (DR_REG_LP_SYS_BASE + 0x100)
-/** LPSYSREG_SW_HW_USB_PHY_SEL : R/W; bitpos: [0]; default: 0;
- *  need_des
- */
-#define LPSYSREG_SW_HW_USB_PHY_SEL    (BIT(0))
-#define LPSYSREG_SW_HW_USB_PHY_SEL_M  (LPSYSREG_SW_HW_USB_PHY_SEL_V << LPSYSREG_SW_HW_USB_PHY_SEL_S)
-#define LPSYSREG_SW_HW_USB_PHY_SEL_V  0x00000001U
-#define LPSYSREG_SW_HW_USB_PHY_SEL_S  0
-/** LPSYSREG_SW_USB_PHY_SEL : R/W; bitpos: [1]; default: 0;
- *  need_des
- */
-#define LPSYSREG_SW_USB_PHY_SEL    (BIT(1))
-#define LPSYSREG_SW_USB_PHY_SEL_M  (LPSYSREG_SW_USB_PHY_SEL_V << LPSYSREG_SW_USB_PHY_SEL_S)
-#define LPSYSREG_SW_USB_PHY_SEL_V  0x00000001U
-#define LPSYSREG_SW_USB_PHY_SEL_S  1
-/** LPSYSREG_USBOTG20_WAKEUP_CLR : WT; bitpos: [2]; default: 0;
- *  clear usb wakeup to PMU.
- */
-#define LPSYSREG_USBOTG20_WAKEUP_CLR    (BIT(2))
-#define LPSYSREG_USBOTG20_WAKEUP_CLR_M  (LPSYSREG_USBOTG20_WAKEUP_CLR_V << LPSYSREG_USBOTG20_WAKEUP_CLR_S)
-#define LPSYSREG_USBOTG20_WAKEUP_CLR_V  0x00000001U
-#define LPSYSREG_USBOTG20_WAKEUP_CLR_S  2
-/** LPSYSREG_USBOTG20_IN_SUSPEND : R/W; bitpos: [3]; default: 0;
- *  indicate usb otg2.0 is in suspend state.
- */
-#define LPSYSREG_USBOTG20_IN_SUSPEND    (BIT(3))
-#define LPSYSREG_USBOTG20_IN_SUSPEND_M  (LPSYSREG_USBOTG20_IN_SUSPEND_V << LPSYSREG_USBOTG20_IN_SUSPEND_S)
-#define LPSYSREG_USBOTG20_IN_SUSPEND_V  0x00000001U
-#define LPSYSREG_USBOTG20_IN_SUSPEND_S  3
-
-/** LPSYSREG_ANA_XPD_PAD_GROUP_REG register
- *  need_des
- */
-#define LPSYSREG_ANA_XPD_PAD_GROUP_REG (DR_REG_LP_SYS_BASE + 0x10c)
-/** LPSYSREG_ANA_REG_XPD_PAD_GROUP : R/W; bitpos: [7:0]; default: 255;
- *  Set 1 to power up pad group
- */
-#define LPSYSREG_ANA_REG_XPD_PAD_GROUP    0x000000FFU
-#define LPSYSREG_ANA_REG_XPD_PAD_GROUP_M  (LPSYSREG_ANA_REG_XPD_PAD_GROUP_V << LPSYSREG_ANA_REG_XPD_PAD_GROUP_S)
-#define LPSYSREG_ANA_REG_XPD_PAD_GROUP_V  0x000000FFU
-#define LPSYSREG_ANA_REG_XPD_PAD_GROUP_S  0
-
-/** LPSYSREG_LP_TCM_RAM_RDN_ECO_CS_REG register
- *  need_des
- */
-#define LPSYSREG_LP_TCM_RAM_RDN_ECO_CS_REG (DR_REG_LP_SYS_BASE + 0x110)
-/** LPSYSREG_LP_TCM_RAM_RDN_ECO_EN : R/W; bitpos: [0]; default: 0;
- *  need_des
- */
-#define LPSYSREG_LP_TCM_RAM_RDN_ECO_EN    (BIT(0))
-#define LPSYSREG_LP_TCM_RAM_RDN_ECO_EN_M  (LPSYSREG_LP_TCM_RAM_RDN_ECO_EN_V << LPSYSREG_LP_TCM_RAM_RDN_ECO_EN_S)
-#define LPSYSREG_LP_TCM_RAM_RDN_ECO_EN_V  0x00000001U
-#define LPSYSREG_LP_TCM_RAM_RDN_ECO_EN_S  0
-/** LPSYSREG_LP_TCM_RAM_RDN_ECO_RESULT : RO; bitpos: [1]; default: 0;
- *  need_des
- */
-#define LPSYSREG_LP_TCM_RAM_RDN_ECO_RESULT    (BIT(1))
-#define LPSYSREG_LP_TCM_RAM_RDN_ECO_RESULT_M  (LPSYSREG_LP_TCM_RAM_RDN_ECO_RESULT_V << LPSYSREG_LP_TCM_RAM_RDN_ECO_RESULT_S)
-#define LPSYSREG_LP_TCM_RAM_RDN_ECO_RESULT_V  0x00000001U
-#define LPSYSREG_LP_TCM_RAM_RDN_ECO_RESULT_S  1
-
-/** LPSYSREG_LP_TCM_RAM_RDN_ECO_LOW_REG register
- *  need_des
- */
-#define LPSYSREG_LP_TCM_RAM_RDN_ECO_LOW_REG (DR_REG_LP_SYS_BASE + 0x114)
-/** LPSYSREG_LP_TCM_RAM_RDN_ECO_LOW : R/W; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define LPSYSREG_LP_TCM_RAM_RDN_ECO_LOW    0xFFFFFFFFU
-#define LPSYSREG_LP_TCM_RAM_RDN_ECO_LOW_M  (LPSYSREG_LP_TCM_RAM_RDN_ECO_LOW_V << LPSYSREG_LP_TCM_RAM_RDN_ECO_LOW_S)
-#define LPSYSREG_LP_TCM_RAM_RDN_ECO_LOW_V  0xFFFFFFFFU
-#define LPSYSREG_LP_TCM_RAM_RDN_ECO_LOW_S  0
-
-/** LPSYSREG_LP_TCM_RAM_RDN_ECO_HIGH_REG register
- *  need_des
- */
-#define LPSYSREG_LP_TCM_RAM_RDN_ECO_HIGH_REG (DR_REG_LP_SYS_BASE + 0x118)
-/** LPSYSREG_LP_TCM_RAM_RDN_ECO_HIGH : R/W; bitpos: [31:0]; default: 4294967295;
- *  need_des
- */
-#define LPSYSREG_LP_TCM_RAM_RDN_ECO_HIGH    0xFFFFFFFFU
-#define LPSYSREG_LP_TCM_RAM_RDN_ECO_HIGH_M  (LPSYSREG_LP_TCM_RAM_RDN_ECO_HIGH_V << LPSYSREG_LP_TCM_RAM_RDN_ECO_HIGH_S)
-#define LPSYSREG_LP_TCM_RAM_RDN_ECO_HIGH_V  0xFFFFFFFFU
-#define LPSYSREG_LP_TCM_RAM_RDN_ECO_HIGH_S  0
-
-/** LPSYSREG_LP_TCM_ROM_RDN_ECO_CS_REG register
- *  need_des
- */
-#define LPSYSREG_LP_TCM_ROM_RDN_ECO_CS_REG (DR_REG_LP_SYS_BASE + 0x11c)
-/** LPSYSREG_LP_TCM_ROM_RDN_ECO_EN : R/W; bitpos: [0]; default: 0;
- *  need_des
- */
-#define LPSYSREG_LP_TCM_ROM_RDN_ECO_EN    (BIT(0))
-#define LPSYSREG_LP_TCM_ROM_RDN_ECO_EN_M  (LPSYSREG_LP_TCM_ROM_RDN_ECO_EN_V << LPSYSREG_LP_TCM_ROM_RDN_ECO_EN_S)
-#define LPSYSREG_LP_TCM_ROM_RDN_ECO_EN_V  0x00000001U
-#define LPSYSREG_LP_TCM_ROM_RDN_ECO_EN_S  0
-/** LPSYSREG_LP_TCM_ROM_RDN_ECO_RESULT : RO; bitpos: [1]; default: 0;
- *  need_des
- */
-#define LPSYSREG_LP_TCM_ROM_RDN_ECO_RESULT    (BIT(1))
-#define LPSYSREG_LP_TCM_ROM_RDN_ECO_RESULT_M  (LPSYSREG_LP_TCM_ROM_RDN_ECO_RESULT_V << LPSYSREG_LP_TCM_ROM_RDN_ECO_RESULT_S)
-#define LPSYSREG_LP_TCM_ROM_RDN_ECO_RESULT_V  0x00000001U
-#define LPSYSREG_LP_TCM_ROM_RDN_ECO_RESULT_S  1
-
-/** LPSYSREG_LP_TCM_ROM_RDN_ECO_LOW_REG register
- *  need_des
- */
-#define LPSYSREG_LP_TCM_ROM_RDN_ECO_LOW_REG (DR_REG_LP_SYS_BASE + 0x120)
-/** LPSYSREG_LP_TCM_ROM_RDN_ECO_LOW : R/W; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define LPSYSREG_LP_TCM_ROM_RDN_ECO_LOW    0xFFFFFFFFU
-#define LPSYSREG_LP_TCM_ROM_RDN_ECO_LOW_M  (LPSYSREG_LP_TCM_ROM_RDN_ECO_LOW_V << LPSYSREG_LP_TCM_ROM_RDN_ECO_LOW_S)
-#define LPSYSREG_LP_TCM_ROM_RDN_ECO_LOW_V  0xFFFFFFFFU
-#define LPSYSREG_LP_TCM_ROM_RDN_ECO_LOW_S  0
-
-/** LPSYSREG_LP_TCM_ROM_RDN_ECO_HIGH_REG register
- *  need_des
- */
-#define LPSYSREG_LP_TCM_ROM_RDN_ECO_HIGH_REG (DR_REG_LP_SYS_BASE + 0x124)
-/** LPSYSREG_LP_TCM_ROM_RDN_ECO_HIGH : R/W; bitpos: [31:0]; default: 4294967295;
- *  need_des
- */
-#define LPSYSREG_LP_TCM_ROM_RDN_ECO_HIGH    0xFFFFFFFFU
-#define LPSYSREG_LP_TCM_ROM_RDN_ECO_HIGH_M  (LPSYSREG_LP_TCM_ROM_RDN_ECO_HIGH_V << LPSYSREG_LP_TCM_ROM_RDN_ECO_HIGH_S)
-#define LPSYSREG_LP_TCM_ROM_RDN_ECO_HIGH_V  0xFFFFFFFFU
-#define LPSYSREG_LP_TCM_ROM_RDN_ECO_HIGH_S  0
-
-/** LPSYSREG_HP_ROOT_CLK_CTRL_REG register
- *  need_des
- */
-#define LPSYSREG_HP_ROOT_CLK_CTRL_REG (DR_REG_LP_SYS_BASE + 0x130)
-/** LPSYSREG_CPU_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  clock gate enable for hp cpu root 400M clk
- */
-#define LPSYSREG_CPU_CLK_EN    (BIT(0))
-#define LPSYSREG_CPU_CLK_EN_M  (LPSYSREG_CPU_CLK_EN_V << LPSYSREG_CPU_CLK_EN_S)
-#define LPSYSREG_CPU_CLK_EN_V  0x00000001U
-#define LPSYSREG_CPU_CLK_EN_S  0
-/** LPSYSREG_SYS_CLK_EN : R/W; bitpos: [1]; default: 1;
- *  clock gate enable for hp sys root 480M clk
- */
-#define LPSYSREG_SYS_CLK_EN    (BIT(1))
-#define LPSYSREG_SYS_CLK_EN_M  (LPSYSREG_SYS_CLK_EN_V << LPSYSREG_SYS_CLK_EN_S)
-#define LPSYSREG_SYS_CLK_EN_V  0x00000001U
-#define LPSYSREG_SYS_CLK_EN_S  1
-
-/** LPSYSREG_LP_PMU_RDN_ECO_LOW_REG register
- *  need_des
- */
-#define LPSYSREG_LP_PMU_RDN_ECO_LOW_REG (DR_REG_LP_SYS_BASE + 0x138)
-/** LPSYSREG_PMU_RDN_ECO_LOW : R/W; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define LPSYSREG_PMU_RDN_ECO_LOW    0xFFFFFFFFU
-#define LPSYSREG_PMU_RDN_ECO_LOW_M  (LPSYSREG_PMU_RDN_ECO_LOW_V << LPSYSREG_PMU_RDN_ECO_LOW_S)
-#define LPSYSREG_PMU_RDN_ECO_LOW_V  0xFFFFFFFFU
-#define LPSYSREG_PMU_RDN_ECO_LOW_S  0
-
-/** LPSYSREG_LP_PMU_RDN_ECO_HIGH_REG register
- *  need_des
- */
-#define LPSYSREG_LP_PMU_RDN_ECO_HIGH_REG (DR_REG_LP_SYS_BASE + 0x13c)
-/** LPSYSREG_PMU_RDN_ECO_HIGH : R/W; bitpos: [31:0]; default: 4294967295;
- *  need_des
- */
-#define LPSYSREG_PMU_RDN_ECO_HIGH    0xFFFFFFFFU
-#define LPSYSREG_PMU_RDN_ECO_HIGH_M  (LPSYSREG_PMU_RDN_ECO_HIGH_V << LPSYSREG_PMU_RDN_ECO_HIGH_S)
-#define LPSYSREG_PMU_RDN_ECO_HIGH_V  0xFFFFFFFFU
-#define LPSYSREG_PMU_RDN_ECO_HIGH_S  0
-
-/** LPSYSREG_PAD_COMP0_REG register
- *  need_des
- */
-#define LPSYSREG_PAD_COMP0_REG (DR_REG_LP_SYS_BASE + 0x148)
-/** LPSYSREG_DREF_COMP0 : R/W; bitpos: [2:0]; default: 0;
- *  pad comp dref
- */
-#define LPSYSREG_DREF_COMP0    0x00000007U
-#define LPSYSREG_DREF_COMP0_M  (LPSYSREG_DREF_COMP0_V << LPSYSREG_DREF_COMP0_S)
-#define LPSYSREG_DREF_COMP0_V  0x00000007U
-#define LPSYSREG_DREF_COMP0_S  0
-/** LPSYSREG_MODE_COMP0 : R/W; bitpos: [3]; default: 0;
- *  pad comp mode
- */
-#define LPSYSREG_MODE_COMP0    (BIT(3))
-#define LPSYSREG_MODE_COMP0_M  (LPSYSREG_MODE_COMP0_V << LPSYSREG_MODE_COMP0_S)
-#define LPSYSREG_MODE_COMP0_V  0x00000001U
-#define LPSYSREG_MODE_COMP0_S  3
-/** LPSYSREG_XPD_COMP0 : R/W; bitpos: [4]; default: 0;
- *  pad comp xpd
- */
-#define LPSYSREG_XPD_COMP0    (BIT(4))
-#define LPSYSREG_XPD_COMP0_M  (LPSYSREG_XPD_COMP0_V << LPSYSREG_XPD_COMP0_S)
-#define LPSYSREG_XPD_COMP0_V  0x00000001U
-#define LPSYSREG_XPD_COMP0_S  4
-
-/** LPSYSREG_PAD_COMP1_REG register
- *  need_des
- */
-#define LPSYSREG_PAD_COMP1_REG (DR_REG_LP_SYS_BASE + 0x14c)
-/** LPSYSREG_DREF_COMP1 : R/W; bitpos: [2:0]; default: 0;
- *  pad comp dref
- */
-#define LPSYSREG_DREF_COMP1    0x00000007U
-#define LPSYSREG_DREF_COMP1_M  (LPSYSREG_DREF_COMP1_V << LPSYSREG_DREF_COMP1_S)
-#define LPSYSREG_DREF_COMP1_V  0x00000007U
-#define LPSYSREG_DREF_COMP1_S  0
-/** LPSYSREG_MODE_COMP1 : R/W; bitpos: [3]; default: 0;
- *  pad comp mode
- */
-#define LPSYSREG_MODE_COMP1    (BIT(3))
-#define LPSYSREG_MODE_COMP1_M  (LPSYSREG_MODE_COMP1_V << LPSYSREG_MODE_COMP1_S)
-#define LPSYSREG_MODE_COMP1_V  0x00000001U
-#define LPSYSREG_MODE_COMP1_S  3
-/** LPSYSREG_XPD_COMP1 : R/W; bitpos: [4]; default: 0;
- *  pad comp xpd
- */
-#define LPSYSREG_XPD_COMP1    (BIT(4))
-#define LPSYSREG_XPD_COMP1_M  (LPSYSREG_XPD_COMP1_V << LPSYSREG_XPD_COMP1_S)
-#define LPSYSREG_XPD_COMP1_V  0x00000001U
-#define LPSYSREG_XPD_COMP1_S  4
-
-/** LPSYSREG_BACKUP_DMA_CFG0_REG register
- *  need_des
- */
-#define LPSYSREG_BACKUP_DMA_CFG0_REG (DR_REG_LP_SYS_BASE + 0x154)
-/** LPSYSREG_BURST_LIMIT_AON : R/W; bitpos: [4:0]; default: 10;
- *  need_des
- */
-#define LPSYSREG_BURST_LIMIT_AON    0x0000001FU
-#define LPSYSREG_BURST_LIMIT_AON_M  (LPSYSREG_BURST_LIMIT_AON_V << LPSYSREG_BURST_LIMIT_AON_S)
-#define LPSYSREG_BURST_LIMIT_AON_V  0x0000001FU
-#define LPSYSREG_BURST_LIMIT_AON_S  0
-/** LPSYSREG_READ_INTERVAL_AON : R/W; bitpos: [11:5]; default: 10;
- *  need_des
- */
-#define LPSYSREG_READ_INTERVAL_AON    0x0000007FU
-#define LPSYSREG_READ_INTERVAL_AON_M  (LPSYSREG_READ_INTERVAL_AON_V << LPSYSREG_READ_INTERVAL_AON_S)
-#define LPSYSREG_READ_INTERVAL_AON_V  0x0000007FU
-#define LPSYSREG_READ_INTERVAL_AON_S  5
-/** LPSYSREG_LINK_BACKUP_TOUT_THRES_AON : R/W; bitpos: [21:12]; default: 100;
- *  need_des
- */
-#define LPSYSREG_LINK_BACKUP_TOUT_THRES_AON    0x000003FFU
-#define LPSYSREG_LINK_BACKUP_TOUT_THRES_AON_M  (LPSYSREG_LINK_BACKUP_TOUT_THRES_AON_V << LPSYSREG_LINK_BACKUP_TOUT_THRES_AON_S)
-#define LPSYSREG_LINK_BACKUP_TOUT_THRES_AON_V  0x000003FFU
-#define LPSYSREG_LINK_BACKUP_TOUT_THRES_AON_S  12
-/** LPSYSREG_LINK_TOUT_THRES_AON : R/W; bitpos: [31:22]; default: 100;
- *  need_des
- */
-#define LPSYSREG_LINK_TOUT_THRES_AON    0x000003FFU
-#define LPSYSREG_LINK_TOUT_THRES_AON_M  (LPSYSREG_LINK_TOUT_THRES_AON_V << LPSYSREG_LINK_TOUT_THRES_AON_S)
-#define LPSYSREG_LINK_TOUT_THRES_AON_V  0x000003FFU
-#define LPSYSREG_LINK_TOUT_THRES_AON_S  22
-
-/** LPSYSREG_BACKUP_DMA_CFG1_REG register
- *  need_des
- */
-#define LPSYSREG_BACKUP_DMA_CFG1_REG (DR_REG_LP_SYS_BASE + 0x158)
-/** LPSYSREG_AON_BYPASS : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define LPSYSREG_AON_BYPASS    (BIT(31))
-#define LPSYSREG_AON_BYPASS_M  (LPSYSREG_AON_BYPASS_V << LPSYSREG_AON_BYPASS_S)
-#define LPSYSREG_AON_BYPASS_V  0x00000001U
-#define LPSYSREG_AON_BYPASS_S  31
-
-/** LPSYSREG_BACKUP_DMA_CFG2_REG register
- *  need_des
- */
-#define LPSYSREG_BACKUP_DMA_CFG2_REG (DR_REG_LP_SYS_BASE + 0x15c)
-/** LPSYSREG_LINK_ADDR_AON : R/W; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define LPSYSREG_LINK_ADDR_AON    0xFFFFFFFFU
-#define LPSYSREG_LINK_ADDR_AON_M  (LPSYSREG_LINK_ADDR_AON_V << LPSYSREG_LINK_ADDR_AON_S)
-#define LPSYSREG_LINK_ADDR_AON_V  0xFFFFFFFFU
-#define LPSYSREG_LINK_ADDR_AON_S  0
-
-/** LPSYSREG_BOOT_ADDR_HP_CORE1_REG register
- *  need_des
- */
-#define LPSYSREG_BOOT_ADDR_HP_CORE1_REG (DR_REG_LP_SYS_BASE + 0x164)
-/** LPSYSREG_BOOT_ADDR_HP_CORE1 : R/W; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define LPSYSREG_BOOT_ADDR_HP_CORE1    0xFFFFFFFFU
-#define LPSYSREG_BOOT_ADDR_HP_CORE1_M  (LPSYSREG_BOOT_ADDR_HP_CORE1_V << LPSYSREG_BOOT_ADDR_HP_CORE1_S)
-#define LPSYSREG_BOOT_ADDR_HP_CORE1_V  0xFFFFFFFFU
-#define LPSYSREG_BOOT_ADDR_HP_CORE1_S  0
-
-/** LPSYSREG_LP_ADDRHOLE_ADDR_REG register
- *  need_des
- */
-#define LPSYSREG_LP_ADDRHOLE_ADDR_REG (DR_REG_LP_SYS_BASE + 0x168)
-/** LPSYSREG_LP_ADDRHOLE_ADDR : RO; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define LPSYSREG_LP_ADDRHOLE_ADDR    0xFFFFFFFFU
-#define LPSYSREG_LP_ADDRHOLE_ADDR_M  (LPSYSREG_LP_ADDRHOLE_ADDR_V << LPSYSREG_LP_ADDRHOLE_ADDR_S)
-#define LPSYSREG_LP_ADDRHOLE_ADDR_V  0xFFFFFFFFU
-#define LPSYSREG_LP_ADDRHOLE_ADDR_S  0
-
-/** LPSYSREG_LP_ADDRHOLE_INFO_REG register
- *  need_des
- */
-#define LPSYSREG_LP_ADDRHOLE_INFO_REG (DR_REG_LP_SYS_BASE + 0x16c)
-/** LPSYSREG_LP_ADDRHOLE_ID : RO; bitpos: [4:0]; default: 0;
- *  master id: 5'h0: hp core0, 5'h1:hp core1, 5'h2:lp core, 5'h3:usb otg11, 5'h4:
- *  regdma, 5'h5: gmac, 5'h5 sdmmc, 5'h7: usbotg20, 5'h8: trace0, 5'h9: trace1, 5'ha
- *  tcm monitor, 5'hb: l2mem monitor. 5'h10~5'h1f: ahb pdma.
- */
-#define LPSYSREG_LP_ADDRHOLE_ID    0x0000001FU
-#define LPSYSREG_LP_ADDRHOLE_ID_M  (LPSYSREG_LP_ADDRHOLE_ID_V << LPSYSREG_LP_ADDRHOLE_ID_S)
-#define LPSYSREG_LP_ADDRHOLE_ID_V  0x0000001FU
-#define LPSYSREG_LP_ADDRHOLE_ID_S  0
-/** LPSYSREG_LP_ADDRHOLE_WR : RO; bitpos: [5]; default: 0;
- *  1:write trans, 0: read trans.
- */
-#define LPSYSREG_LP_ADDRHOLE_WR    (BIT(5))
-#define LPSYSREG_LP_ADDRHOLE_WR_M  (LPSYSREG_LP_ADDRHOLE_WR_V << LPSYSREG_LP_ADDRHOLE_WR_S)
-#define LPSYSREG_LP_ADDRHOLE_WR_V  0x00000001U
-#define LPSYSREG_LP_ADDRHOLE_WR_S  5
-/** LPSYSREG_LP_ADDRHOLE_SECURE : RO; bitpos: [6]; default: 0;
- *  1: illegal address access, 0: access without permission
- */
-#define LPSYSREG_LP_ADDRHOLE_SECURE    (BIT(6))
-#define LPSYSREG_LP_ADDRHOLE_SECURE_M  (LPSYSREG_LP_ADDRHOLE_SECURE_V << LPSYSREG_LP_ADDRHOLE_SECURE_S)
-#define LPSYSREG_LP_ADDRHOLE_SECURE_V  0x00000001U
-#define LPSYSREG_LP_ADDRHOLE_SECURE_S  6
-
-/** LPSYSREG_INT_RAW_REG register
- *  raw interrupt register
- */
-#define LPSYSREG_INT_RAW_REG (DR_REG_LP_SYS_BASE + 0x170)
-/** LPSYSREG_LP_ADDRHOLE_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0;
- *  the raw interrupt status of lp addrhole(for lp peri  and lp ram tee apm, and lp
- *  matrix default slave)
- */
-#define LPSYSREG_LP_ADDRHOLE_INT_RAW    (BIT(0))
-#define LPSYSREG_LP_ADDRHOLE_INT_RAW_M  (LPSYSREG_LP_ADDRHOLE_INT_RAW_V << LPSYSREG_LP_ADDRHOLE_INT_RAW_S)
-#define LPSYSREG_LP_ADDRHOLE_INT_RAW_V  0x00000001U
-#define LPSYSREG_LP_ADDRHOLE_INT_RAW_S  0
-/** LPSYSREG_IDBUS_ADDRHOLE_INT_RAW : R/SS/WTC; bitpos: [1]; default: 0;
- *  the raw interrupt status of idbus addrhole(only for lp cpu ibus and dbus)
- */
-#define LPSYSREG_IDBUS_ADDRHOLE_INT_RAW    (BIT(1))
-#define LPSYSREG_IDBUS_ADDRHOLE_INT_RAW_M  (LPSYSREG_IDBUS_ADDRHOLE_INT_RAW_V << LPSYSREG_IDBUS_ADDRHOLE_INT_RAW_S)
-#define LPSYSREG_IDBUS_ADDRHOLE_INT_RAW_V  0x00000001U
-#define LPSYSREG_IDBUS_ADDRHOLE_INT_RAW_S  1
-/** LPSYSREG_LP_CORE_AHB_TIMEOUT_INT_RAW : R/SS/WTC; bitpos: [2]; default: 0;
- *  the raw interrupt status of lp core ahb bus timeout
- */
-#define LPSYSREG_LP_CORE_AHB_TIMEOUT_INT_RAW    (BIT(2))
-#define LPSYSREG_LP_CORE_AHB_TIMEOUT_INT_RAW_M  (LPSYSREG_LP_CORE_AHB_TIMEOUT_INT_RAW_V << LPSYSREG_LP_CORE_AHB_TIMEOUT_INT_RAW_S)
-#define LPSYSREG_LP_CORE_AHB_TIMEOUT_INT_RAW_V  0x00000001U
-#define LPSYSREG_LP_CORE_AHB_TIMEOUT_INT_RAW_S  2
-/** LPSYSREG_LP_CORE_IBUS_TIMEOUT_INT_RAW : R/SS/WTC; bitpos: [3]; default: 0;
- *  the raw interrupt status of lp core  ibus timeout
- */
-#define LPSYSREG_LP_CORE_IBUS_TIMEOUT_INT_RAW    (BIT(3))
-#define LPSYSREG_LP_CORE_IBUS_TIMEOUT_INT_RAW_M  (LPSYSREG_LP_CORE_IBUS_TIMEOUT_INT_RAW_V << LPSYSREG_LP_CORE_IBUS_TIMEOUT_INT_RAW_S)
-#define LPSYSREG_LP_CORE_IBUS_TIMEOUT_INT_RAW_V  0x00000001U
-#define LPSYSREG_LP_CORE_IBUS_TIMEOUT_INT_RAW_S  3
-/** LPSYSREG_LP_CORE_DBUS_TIMEOUT_INT_RAW : R/SS/WTC; bitpos: [4]; default: 0;
- *  the raw interrupt status of lp core  dbus timeout
- */
-#define LPSYSREG_LP_CORE_DBUS_TIMEOUT_INT_RAW    (BIT(4))
-#define LPSYSREG_LP_CORE_DBUS_TIMEOUT_INT_RAW_M  (LPSYSREG_LP_CORE_DBUS_TIMEOUT_INT_RAW_V << LPSYSREG_LP_CORE_DBUS_TIMEOUT_INT_RAW_S)
-#define LPSYSREG_LP_CORE_DBUS_TIMEOUT_INT_RAW_V  0x00000001U
-#define LPSYSREG_LP_CORE_DBUS_TIMEOUT_INT_RAW_S  4
-/** LPSYSREG_ETM_TASK_ULP_INT_RAW : R/SS/WTC; bitpos: [5]; default: 0;
- *  the raw interrupt status of etm task ulp
- */
-#define LPSYSREG_ETM_TASK_ULP_INT_RAW    (BIT(5))
-#define LPSYSREG_ETM_TASK_ULP_INT_RAW_M  (LPSYSREG_ETM_TASK_ULP_INT_RAW_V << LPSYSREG_ETM_TASK_ULP_INT_RAW_S)
-#define LPSYSREG_ETM_TASK_ULP_INT_RAW_V  0x00000001U
-#define LPSYSREG_ETM_TASK_ULP_INT_RAW_S  5
-/** LPSYSREG_SLOW_CLK_TICK_INT_RAW : R/SS/WTC; bitpos: [6]; default: 0;
- *  the raw interrupt status of slow_clk_tick
- */
-#define LPSYSREG_SLOW_CLK_TICK_INT_RAW    (BIT(6))
-#define LPSYSREG_SLOW_CLK_TICK_INT_RAW_M  (LPSYSREG_SLOW_CLK_TICK_INT_RAW_V << LPSYSREG_SLOW_CLK_TICK_INT_RAW_S)
-#define LPSYSREG_SLOW_CLK_TICK_INT_RAW_V  0x00000001U
-#define LPSYSREG_SLOW_CLK_TICK_INT_RAW_S  6
-
-/** LPSYSREG_INT_ST_REG register
- *  masked interrupt register
- */
-#define LPSYSREG_INT_ST_REG (DR_REG_LP_SYS_BASE + 0x174)
-/** LPSYSREG_LP_ADDRHOLE_INT_ST : RO; bitpos: [0]; default: 0;
- *  the masked interrupt status of lp addrhole (for lp peri  and lp ram tee apm, and lp
- *  matrix default slave)
- */
-#define LPSYSREG_LP_ADDRHOLE_INT_ST    (BIT(0))
-#define LPSYSREG_LP_ADDRHOLE_INT_ST_M  (LPSYSREG_LP_ADDRHOLE_INT_ST_V << LPSYSREG_LP_ADDRHOLE_INT_ST_S)
-#define LPSYSREG_LP_ADDRHOLE_INT_ST_V  0x00000001U
-#define LPSYSREG_LP_ADDRHOLE_INT_ST_S  0
-/** LPSYSREG_IDBUS_ADDRHOLE_INT_ST : RO; bitpos: [1]; default: 0;
- *  the masked interrupt status of idbus addrhole(only for lp cpu ibus and dbus)
- */
-#define LPSYSREG_IDBUS_ADDRHOLE_INT_ST    (BIT(1))
-#define LPSYSREG_IDBUS_ADDRHOLE_INT_ST_M  (LPSYSREG_IDBUS_ADDRHOLE_INT_ST_V << LPSYSREG_IDBUS_ADDRHOLE_INT_ST_S)
-#define LPSYSREG_IDBUS_ADDRHOLE_INT_ST_V  0x00000001U
-#define LPSYSREG_IDBUS_ADDRHOLE_INT_ST_S  1
-/** LPSYSREG_LP_CORE_AHB_TIMEOUT_INT_ST : RO; bitpos: [2]; default: 0;
- *  the masked interrupt status of lp core ahb bus timeout
- */
-#define LPSYSREG_LP_CORE_AHB_TIMEOUT_INT_ST    (BIT(2))
-#define LPSYSREG_LP_CORE_AHB_TIMEOUT_INT_ST_M  (LPSYSREG_LP_CORE_AHB_TIMEOUT_INT_ST_V << LPSYSREG_LP_CORE_AHB_TIMEOUT_INT_ST_S)
-#define LPSYSREG_LP_CORE_AHB_TIMEOUT_INT_ST_V  0x00000001U
-#define LPSYSREG_LP_CORE_AHB_TIMEOUT_INT_ST_S  2
-/** LPSYSREG_LP_CORE_IBUS_TIMEOUT_INT_ST : RO; bitpos: [3]; default: 0;
- *  the masked interrupt status of lp core  ibus timeout
- */
-#define LPSYSREG_LP_CORE_IBUS_TIMEOUT_INT_ST    (BIT(3))
-#define LPSYSREG_LP_CORE_IBUS_TIMEOUT_INT_ST_M  (LPSYSREG_LP_CORE_IBUS_TIMEOUT_INT_ST_V << LPSYSREG_LP_CORE_IBUS_TIMEOUT_INT_ST_S)
-#define LPSYSREG_LP_CORE_IBUS_TIMEOUT_INT_ST_V  0x00000001U
-#define LPSYSREG_LP_CORE_IBUS_TIMEOUT_INT_ST_S  3
-/** LPSYSREG_LP_CORE_DBUS_TIMEOUT_INT_ST : RO; bitpos: [4]; default: 0;
- *  the masked interrupt status of lp core  dbus timeout
- */
-#define LPSYSREG_LP_CORE_DBUS_TIMEOUT_INT_ST    (BIT(4))
-#define LPSYSREG_LP_CORE_DBUS_TIMEOUT_INT_ST_M  (LPSYSREG_LP_CORE_DBUS_TIMEOUT_INT_ST_V << LPSYSREG_LP_CORE_DBUS_TIMEOUT_INT_ST_S)
-#define LPSYSREG_LP_CORE_DBUS_TIMEOUT_INT_ST_V  0x00000001U
-#define LPSYSREG_LP_CORE_DBUS_TIMEOUT_INT_ST_S  4
-/** LPSYSREG_ETM_TASK_ULP_INT_ST : RO; bitpos: [5]; default: 0;
- *  the masked interrupt status of etm task ulp
- */
-#define LPSYSREG_ETM_TASK_ULP_INT_ST    (BIT(5))
-#define LPSYSREG_ETM_TASK_ULP_INT_ST_M  (LPSYSREG_ETM_TASK_ULP_INT_ST_V << LPSYSREG_ETM_TASK_ULP_INT_ST_S)
-#define LPSYSREG_ETM_TASK_ULP_INT_ST_V  0x00000001U
-#define LPSYSREG_ETM_TASK_ULP_INT_ST_S  5
-/** LPSYSREG_SLOW_CLK_TICK_INT_ST : RO; bitpos: [6]; default: 0;
- *  the masked interrupt status of slow_clk_tick
- */
-#define LPSYSREG_SLOW_CLK_TICK_INT_ST    (BIT(6))
-#define LPSYSREG_SLOW_CLK_TICK_INT_ST_M  (LPSYSREG_SLOW_CLK_TICK_INT_ST_V << LPSYSREG_SLOW_CLK_TICK_INT_ST_S)
-#define LPSYSREG_SLOW_CLK_TICK_INT_ST_V  0x00000001U
-#define LPSYSREG_SLOW_CLK_TICK_INT_ST_S  6
-
-/** LPSYSREG_INT_ENA_REG register
- *  masked interrupt register
- */
-#define LPSYSREG_INT_ENA_REG (DR_REG_LP_SYS_BASE + 0x178)
-/** LPSYSREG_LP_ADDRHOLE_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  Write 1 to enable lp addrhole int
- */
-#define LPSYSREG_LP_ADDRHOLE_INT_ENA    (BIT(0))
-#define LPSYSREG_LP_ADDRHOLE_INT_ENA_M  (LPSYSREG_LP_ADDRHOLE_INT_ENA_V << LPSYSREG_LP_ADDRHOLE_INT_ENA_S)
-#define LPSYSREG_LP_ADDRHOLE_INT_ENA_V  0x00000001U
-#define LPSYSREG_LP_ADDRHOLE_INT_ENA_S  0
-/** LPSYSREG_IDBUS_ADDRHOLE_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  Write 1 to enable idbus addrhole int
- */
-#define LPSYSREG_IDBUS_ADDRHOLE_INT_ENA    (BIT(1))
-#define LPSYSREG_IDBUS_ADDRHOLE_INT_ENA_M  (LPSYSREG_IDBUS_ADDRHOLE_INT_ENA_V << LPSYSREG_IDBUS_ADDRHOLE_INT_ENA_S)
-#define LPSYSREG_IDBUS_ADDRHOLE_INT_ENA_V  0x00000001U
-#define LPSYSREG_IDBUS_ADDRHOLE_INT_ENA_S  1
-/** LPSYSREG_LP_CORE_AHB_TIMEOUT_INT_ENA : R/W; bitpos: [2]; default: 0;
- *  Write 1 to enable lp_core_ahb_timeout int
- */
-#define LPSYSREG_LP_CORE_AHB_TIMEOUT_INT_ENA    (BIT(2))
-#define LPSYSREG_LP_CORE_AHB_TIMEOUT_INT_ENA_M  (LPSYSREG_LP_CORE_AHB_TIMEOUT_INT_ENA_V << LPSYSREG_LP_CORE_AHB_TIMEOUT_INT_ENA_S)
-#define LPSYSREG_LP_CORE_AHB_TIMEOUT_INT_ENA_V  0x00000001U
-#define LPSYSREG_LP_CORE_AHB_TIMEOUT_INT_ENA_S  2
-/** LPSYSREG_LP_CORE_IBUS_TIMEOUT_INT_ENA : R/W; bitpos: [3]; default: 0;
- *  Write 1 to enable lp_core_ibus_timeout int
- */
-#define LPSYSREG_LP_CORE_IBUS_TIMEOUT_INT_ENA    (BIT(3))
-#define LPSYSREG_LP_CORE_IBUS_TIMEOUT_INT_ENA_M  (LPSYSREG_LP_CORE_IBUS_TIMEOUT_INT_ENA_V << LPSYSREG_LP_CORE_IBUS_TIMEOUT_INT_ENA_S)
-#define LPSYSREG_LP_CORE_IBUS_TIMEOUT_INT_ENA_V  0x00000001U
-#define LPSYSREG_LP_CORE_IBUS_TIMEOUT_INT_ENA_S  3
-/** LPSYSREG_LP_CORE_DBUS_TIMEOUT_INT_ENA : R/W; bitpos: [4]; default: 0;
- *  Write 1 to enable lp_core_dbus_timeout int
- */
-#define LPSYSREG_LP_CORE_DBUS_TIMEOUT_INT_ENA    (BIT(4))
-#define LPSYSREG_LP_CORE_DBUS_TIMEOUT_INT_ENA_M  (LPSYSREG_LP_CORE_DBUS_TIMEOUT_INT_ENA_V << LPSYSREG_LP_CORE_DBUS_TIMEOUT_INT_ENA_S)
-#define LPSYSREG_LP_CORE_DBUS_TIMEOUT_INT_ENA_V  0x00000001U
-#define LPSYSREG_LP_CORE_DBUS_TIMEOUT_INT_ENA_S  4
-/** LPSYSREG_ETM_TASK_ULP_INT_ENA : R/W; bitpos: [5]; default: 0;
- *  Write 1 to enable etm task ulp int
- */
-#define LPSYSREG_ETM_TASK_ULP_INT_ENA    (BIT(5))
-#define LPSYSREG_ETM_TASK_ULP_INT_ENA_M  (LPSYSREG_ETM_TASK_ULP_INT_ENA_V << LPSYSREG_ETM_TASK_ULP_INT_ENA_S)
-#define LPSYSREG_ETM_TASK_ULP_INT_ENA_V  0x00000001U
-#define LPSYSREG_ETM_TASK_ULP_INT_ENA_S  5
-/** LPSYSREG_SLOW_CLK_TICK_INT_ENA : R/W; bitpos: [6]; default: 0;
- *  Write 1 to enable slow_clk_tick int
- */
-#define LPSYSREG_SLOW_CLK_TICK_INT_ENA    (BIT(6))
-#define LPSYSREG_SLOW_CLK_TICK_INT_ENA_M  (LPSYSREG_SLOW_CLK_TICK_INT_ENA_V << LPSYSREG_SLOW_CLK_TICK_INT_ENA_S)
-#define LPSYSREG_SLOW_CLK_TICK_INT_ENA_V  0x00000001U
-#define LPSYSREG_SLOW_CLK_TICK_INT_ENA_S  6
-
-/** LPSYSREG_INT_CLR_REG register
- *  interrupt clear register
- */
-#define LPSYSREG_INT_CLR_REG (DR_REG_LP_SYS_BASE + 0x17c)
-/** LPSYSREG_LP_ADDRHOLE_INT_CLR : WT; bitpos: [0]; default: 0;
- *  write 1 to clear lp addrhole int
- */
-#define LPSYSREG_LP_ADDRHOLE_INT_CLR    (BIT(0))
-#define LPSYSREG_LP_ADDRHOLE_INT_CLR_M  (LPSYSREG_LP_ADDRHOLE_INT_CLR_V << LPSYSREG_LP_ADDRHOLE_INT_CLR_S)
-#define LPSYSREG_LP_ADDRHOLE_INT_CLR_V  0x00000001U
-#define LPSYSREG_LP_ADDRHOLE_INT_CLR_S  0
-/** LPSYSREG_IDBUS_ADDRHOLE_INT_CLR : WT; bitpos: [1]; default: 0;
- *  write 1 to clear idbus addrhole int
- */
-#define LPSYSREG_IDBUS_ADDRHOLE_INT_CLR    (BIT(1))
-#define LPSYSREG_IDBUS_ADDRHOLE_INT_CLR_M  (LPSYSREG_IDBUS_ADDRHOLE_INT_CLR_V << LPSYSREG_IDBUS_ADDRHOLE_INT_CLR_S)
-#define LPSYSREG_IDBUS_ADDRHOLE_INT_CLR_V  0x00000001U
-#define LPSYSREG_IDBUS_ADDRHOLE_INT_CLR_S  1
-/** LPSYSREG_LP_CORE_AHB_TIMEOUT_INT_CLR : WT; bitpos: [2]; default: 0;
- *  Write 1 to clear lp_core_ahb_timeout int
- */
-#define LPSYSREG_LP_CORE_AHB_TIMEOUT_INT_CLR    (BIT(2))
-#define LPSYSREG_LP_CORE_AHB_TIMEOUT_INT_CLR_M  (LPSYSREG_LP_CORE_AHB_TIMEOUT_INT_CLR_V << LPSYSREG_LP_CORE_AHB_TIMEOUT_INT_CLR_S)
-#define LPSYSREG_LP_CORE_AHB_TIMEOUT_INT_CLR_V  0x00000001U
-#define LPSYSREG_LP_CORE_AHB_TIMEOUT_INT_CLR_S  2
-/** LPSYSREG_LP_CORE_IBUS_TIMEOUT_INT_CLR : WT; bitpos: [3]; default: 0;
- *  Write 1 to clear lp_core_ibus_timeout int
- */
-#define LPSYSREG_LP_CORE_IBUS_TIMEOUT_INT_CLR    (BIT(3))
-#define LPSYSREG_LP_CORE_IBUS_TIMEOUT_INT_CLR_M  (LPSYSREG_LP_CORE_IBUS_TIMEOUT_INT_CLR_V << LPSYSREG_LP_CORE_IBUS_TIMEOUT_INT_CLR_S)
-#define LPSYSREG_LP_CORE_IBUS_TIMEOUT_INT_CLR_V  0x00000001U
-#define LPSYSREG_LP_CORE_IBUS_TIMEOUT_INT_CLR_S  3
-/** LPSYSREG_LP_CORE_DBUS_TIMEOUT_INT_CLR : WT; bitpos: [4]; default: 0;
- *  Write 1 to clear lp_core_dbus_timeout int
- */
-#define LPSYSREG_LP_CORE_DBUS_TIMEOUT_INT_CLR    (BIT(4))
-#define LPSYSREG_LP_CORE_DBUS_TIMEOUT_INT_CLR_M  (LPSYSREG_LP_CORE_DBUS_TIMEOUT_INT_CLR_V << LPSYSREG_LP_CORE_DBUS_TIMEOUT_INT_CLR_S)
-#define LPSYSREG_LP_CORE_DBUS_TIMEOUT_INT_CLR_V  0x00000001U
-#define LPSYSREG_LP_CORE_DBUS_TIMEOUT_INT_CLR_S  4
-/** LPSYSREG_ETM_TASK_ULP_INT_CLR : WT; bitpos: [5]; default: 0;
- *  Write 1 to clear etm tasl ulp int
- */
-#define LPSYSREG_ETM_TASK_ULP_INT_CLR    (BIT(5))
-#define LPSYSREG_ETM_TASK_ULP_INT_CLR_M  (LPSYSREG_ETM_TASK_ULP_INT_CLR_V << LPSYSREG_ETM_TASK_ULP_INT_CLR_S)
-#define LPSYSREG_ETM_TASK_ULP_INT_CLR_V  0x00000001U
-#define LPSYSREG_ETM_TASK_ULP_INT_CLR_S  5
-/** LPSYSREG_SLOW_CLK_TICK_INT_CLR : WT; bitpos: [6]; default: 0;
- *  Write 1 to clear slow_clk_tick int
- */
-#define LPSYSREG_SLOW_CLK_TICK_INT_CLR    (BIT(6))
-#define LPSYSREG_SLOW_CLK_TICK_INT_CLR_M  (LPSYSREG_SLOW_CLK_TICK_INT_CLR_V << LPSYSREG_SLOW_CLK_TICK_INT_CLR_S)
-#define LPSYSREG_SLOW_CLK_TICK_INT_CLR_V  0x00000001U
-#define LPSYSREG_SLOW_CLK_TICK_INT_CLR_S  6
-
-/** LPSYSREG_HP_MEM_AUX_CTRL_REG register
- *  need_des
- */
-#define LPSYSREG_HP_MEM_AUX_CTRL_REG (DR_REG_LP_SYS_BASE + 0x180)
-/** LPSYSREG_HP_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 8304;
- *  need_des
- */
-#define LPSYSREG_HP_MEM_AUX_CTRL    0xFFFFFFFFU
-#define LPSYSREG_HP_MEM_AUX_CTRL_M  (LPSYSREG_HP_MEM_AUX_CTRL_V << LPSYSREG_HP_MEM_AUX_CTRL_S)
-#define LPSYSREG_HP_MEM_AUX_CTRL_V  0xFFFFFFFFU
-#define LPSYSREG_HP_MEM_AUX_CTRL_S  0
-
-/** LPSYSREG_LP_MEM_AUX_CTRL_REG register
- *  need_des
- */
-#define LPSYSREG_LP_MEM_AUX_CTRL_REG (DR_REG_LP_SYS_BASE + 0x184)
-/** LPSYSREG_LP_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 8304;
- *  need_des
- */
-#define LPSYSREG_LP_MEM_AUX_CTRL    0xFFFFFFFFU
-#define LPSYSREG_LP_MEM_AUX_CTRL_M  (LPSYSREG_LP_MEM_AUX_CTRL_V << LPSYSREG_LP_MEM_AUX_CTRL_S)
-#define LPSYSREG_LP_MEM_AUX_CTRL_V  0xFFFFFFFFU
-#define LPSYSREG_LP_MEM_AUX_CTRL_S  0
-
-/** LPSYSREG_HP_ROM_AUX_CTRL_REG register
- *  need_des
- */
-#define LPSYSREG_HP_ROM_AUX_CTRL_REG (DR_REG_LP_SYS_BASE + 0x188)
-/** LPSYSREG_HP_ROM_AUX_CTRL : R/W; bitpos: [31:0]; default: 112;
- *  need_des
- */
-#define LPSYSREG_HP_ROM_AUX_CTRL    0xFFFFFFFFU
-#define LPSYSREG_HP_ROM_AUX_CTRL_M  (LPSYSREG_HP_ROM_AUX_CTRL_V << LPSYSREG_HP_ROM_AUX_CTRL_S)
-#define LPSYSREG_HP_ROM_AUX_CTRL_V  0xFFFFFFFFU
-#define LPSYSREG_HP_ROM_AUX_CTRL_S  0
-
-/** LPSYSREG_LP_ROM_AUX_CTRL_REG register
- *  need_des
- */
-#define LPSYSREG_LP_ROM_AUX_CTRL_REG (DR_REG_LP_SYS_BASE + 0x18c)
-/** LPSYSREG_LP_ROM_AUX_CTRL : R/W; bitpos: [31:0]; default: 112;
- *  need_des
- */
-#define LPSYSREG_LP_ROM_AUX_CTRL    0xFFFFFFFFU
-#define LPSYSREG_LP_ROM_AUX_CTRL_M  (LPSYSREG_LP_ROM_AUX_CTRL_V << LPSYSREG_LP_ROM_AUX_CTRL_S)
-#define LPSYSREG_LP_ROM_AUX_CTRL_V  0xFFFFFFFFU
-#define LPSYSREG_LP_ROM_AUX_CTRL_S  0
-
-/** LPSYSREG_LP_CPU_DBG_PC_REG register
- *  need_des
- */
-#define LPSYSREG_LP_CPU_DBG_PC_REG (DR_REG_LP_SYS_BASE + 0x190)
-/** LPSYSREG_LP_CPU_DBG_PC : RO; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define LPSYSREG_LP_CPU_DBG_PC    0xFFFFFFFFU
-#define LPSYSREG_LP_CPU_DBG_PC_M  (LPSYSREG_LP_CPU_DBG_PC_V << LPSYSREG_LP_CPU_DBG_PC_S)
-#define LPSYSREG_LP_CPU_DBG_PC_V  0xFFFFFFFFU
-#define LPSYSREG_LP_CPU_DBG_PC_S  0
-
-/** LPSYSREG_LP_CPU_EXC_PC_REG register
- *  need_des
- */
-#define LPSYSREG_LP_CPU_EXC_PC_REG (DR_REG_LP_SYS_BASE + 0x194)
-/** LPSYSREG_LP_CPU_EXC_PC : RO; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define LPSYSREG_LP_CPU_EXC_PC    0xFFFFFFFFU
-#define LPSYSREG_LP_CPU_EXC_PC_M  (LPSYSREG_LP_CPU_EXC_PC_V << LPSYSREG_LP_CPU_EXC_PC_S)
-#define LPSYSREG_LP_CPU_EXC_PC_V  0xFFFFFFFFU
-#define LPSYSREG_LP_CPU_EXC_PC_S  0
-
-/** LPSYSREG_IDBUS_ADDRHOLE_ADDR_REG register
- *  need_des
- */
-#define LPSYSREG_IDBUS_ADDRHOLE_ADDR_REG (DR_REG_LP_SYS_BASE + 0x198)
-/** LPSYSREG_IDBUS_ADDRHOLE_ADDR : RO; bitpos: [31:0]; default: 0;
- *  need_des
- */
-#define LPSYSREG_IDBUS_ADDRHOLE_ADDR    0xFFFFFFFFU
-#define LPSYSREG_IDBUS_ADDRHOLE_ADDR_M  (LPSYSREG_IDBUS_ADDRHOLE_ADDR_V << LPSYSREG_IDBUS_ADDRHOLE_ADDR_S)
-#define LPSYSREG_IDBUS_ADDRHOLE_ADDR_V  0xFFFFFFFFU
-#define LPSYSREG_IDBUS_ADDRHOLE_ADDR_S  0
-
-/** LPSYSREG_IDBUS_ADDRHOLE_INFO_REG register
- *  need_des
- */
-#define LPSYSREG_IDBUS_ADDRHOLE_INFO_REG (DR_REG_LP_SYS_BASE + 0x19c)
-/** LPSYSREG_IDBUS_ADDRHOLE_ID : RO; bitpos: [4:0]; default: 0;
- *  need_des
- */
-#define LPSYSREG_IDBUS_ADDRHOLE_ID    0x0000001FU
-#define LPSYSREG_IDBUS_ADDRHOLE_ID_M  (LPSYSREG_IDBUS_ADDRHOLE_ID_V << LPSYSREG_IDBUS_ADDRHOLE_ID_S)
-#define LPSYSREG_IDBUS_ADDRHOLE_ID_V  0x0000001FU
-#define LPSYSREG_IDBUS_ADDRHOLE_ID_S  0
-/** LPSYSREG_IDBUS_ADDRHOLE_WR : RO; bitpos: [5]; default: 0;
- *  need_des
- */
-#define LPSYSREG_IDBUS_ADDRHOLE_WR    (BIT(5))
-#define LPSYSREG_IDBUS_ADDRHOLE_WR_M  (LPSYSREG_IDBUS_ADDRHOLE_WR_V << LPSYSREG_IDBUS_ADDRHOLE_WR_S)
-#define LPSYSREG_IDBUS_ADDRHOLE_WR_V  0x00000001U
-#define LPSYSREG_IDBUS_ADDRHOLE_WR_S  5
-/** LPSYSREG_IDBUS_ADDRHOLE_SECURE : RO; bitpos: [6]; default: 0;
- *  need_des
- */
-#define LPSYSREG_IDBUS_ADDRHOLE_SECURE    (BIT(6))
-#define LPSYSREG_IDBUS_ADDRHOLE_SECURE_M  (LPSYSREG_IDBUS_ADDRHOLE_SECURE_V << LPSYSREG_IDBUS_ADDRHOLE_SECURE_S)
-#define LPSYSREG_IDBUS_ADDRHOLE_SECURE_V  0x00000001U
-#define LPSYSREG_IDBUS_ADDRHOLE_SECURE_S  6
-
-/** LPSYSREG_HP_POR_RST_BYPASS_CTRL_REG register
- *  need_des
- */
-#define LPSYSREG_HP_POR_RST_BYPASS_CTRL_REG (DR_REG_LP_SYS_BASE + 0x1a0)
-/** LPSYSREG_HP_PO_CNNT_RSTN_BYPASS_CTRL : R/W; bitpos: [15:8]; default: 255;
- *  [15] 1'b1: po_cnnt_rstn bypass sys_sw_rstn
- *  [14] 1'b1: po_cnnt_rstn bypass hp_wdt_sys_rstn
- *  [13] 1'b1: po_cnnt_rstn bypass hp_cpu_intrusion_rstn
- *  [12] 1'b1: po_cnnt_rstn bypass hp_sdio_sys_rstn
- *  [11] 1'b1: po_cnnt_rstn bypass usb_jtag_chip_rst
- *  [10] 1'b1: po_cnnt_rstn bypass usb_uart_chip_rst
- *  [9] 1'b1: po_cnnt_rstn bypass lp_wdt_hp_sys_rstn
- *  [8] 1'b1: po_cnnt_rstn bypass efuse_err_rstn
- */
-#define LPSYSREG_HP_PO_CNNT_RSTN_BYPASS_CTRL    0x000000FFU
-#define LPSYSREG_HP_PO_CNNT_RSTN_BYPASS_CTRL_M  (LPSYSREG_HP_PO_CNNT_RSTN_BYPASS_CTRL_V << LPSYSREG_HP_PO_CNNT_RSTN_BYPASS_CTRL_S)
-#define LPSYSREG_HP_PO_CNNT_RSTN_BYPASS_CTRL_V  0x000000FFU
-#define LPSYSREG_HP_PO_CNNT_RSTN_BYPASS_CTRL_S  8
-/** LPSYSREG_HP_PO_RSTN_BYPASS_CTRL : R/W; bitpos: [31:24]; default: 255;
- *  [31] 1'b1: po_rstn bypass sys_sw_rstn
- *  [30] 1'b1: po_rstn bypass hp_wdt_sys_rstn
- *  [29] 1'b1: po_rstn bypass hp_cpu_intrusion_rstn
- *  [28] 1'b1: po_rstn bypass hp_sdio_sys_rstn
- *  [27] 1'b1: po_rstn bypass usb_jtag_chip_rst
- *  [26] 1'b1: po_rstn bypass usb_uart_chip_rst
- *  [25] 1'b1: po_rstn bypass lp_wdt_hp_sys_rstn
- *  [24] 1'b1: po_rstn bypass efuse_err_rstn
- */
-#define LPSYSREG_HP_PO_RSTN_BYPASS_CTRL    0x000000FFU
-#define LPSYSREG_HP_PO_RSTN_BYPASS_CTRL_M  (LPSYSREG_HP_PO_RSTN_BYPASS_CTRL_V << LPSYSREG_HP_PO_RSTN_BYPASS_CTRL_S)
-#define LPSYSREG_HP_PO_RSTN_BYPASS_CTRL_V  0x000000FFU
-#define LPSYSREG_HP_PO_RSTN_BYPASS_CTRL_S  24
-
-/** LPSYSREG_RNG_DATA_REG register
- *  rng data register
- */
-#define LPSYSREG_RNG_DATA_REG (DR_REG_LP_SYS_BASE + 0x1a4)
-/** LPSYSREG_RND_DATA : RO; bitpos: [31:0]; default: 0;
- *  result of rng output
- */
-#define LPSYSREG_RND_DATA    0xFFFFFFFFU
-#define LPSYSREG_RND_DATA_M  (LPSYSREG_RND_DATA_V << LPSYSREG_RND_DATA_S)
-#define LPSYSREG_RND_DATA_V  0xFFFFFFFFU
-#define LPSYSREG_RND_DATA_S  0
-
-/** LPSYSREG_LP_CORE_AHB_TIMEOUT_REG register
- *  need_des
- */
-#define LPSYSREG_LP_CORE_AHB_TIMEOUT_REG (DR_REG_LP_SYS_BASE + 0x1b0)
-/** LPSYSREG_LP_CORE_AHB_TIMEOUT_EN : R/W; bitpos: [0]; default: 1;
- *  set this field to 1 to enable lp core ahb timeout handle
- */
-#define LPSYSREG_LP_CORE_AHB_TIMEOUT_EN    (BIT(0))
-#define LPSYSREG_LP_CORE_AHB_TIMEOUT_EN_M  (LPSYSREG_LP_CORE_AHB_TIMEOUT_EN_V << LPSYSREG_LP_CORE_AHB_TIMEOUT_EN_S)
-#define LPSYSREG_LP_CORE_AHB_TIMEOUT_EN_V  0x00000001U
-#define LPSYSREG_LP_CORE_AHB_TIMEOUT_EN_S  0
-/** LPSYSREG_LP_CORE_AHB_TIMEOUT_THRES : R/W; bitpos: [16:1]; default: 65535;
- *  This field used to set lp core ahb bus timeout  threshold
- */
-#define LPSYSREG_LP_CORE_AHB_TIMEOUT_THRES    0x0000FFFFU
-#define LPSYSREG_LP_CORE_AHB_TIMEOUT_THRES_M  (LPSYSREG_LP_CORE_AHB_TIMEOUT_THRES_V << LPSYSREG_LP_CORE_AHB_TIMEOUT_THRES_S)
-#define LPSYSREG_LP_CORE_AHB_TIMEOUT_THRES_V  0x0000FFFFU
-#define LPSYSREG_LP_CORE_AHB_TIMEOUT_THRES_S  1
-/** LPSYSREG_LP2HP_AHB_TIMEOUT_EN : R/W; bitpos: [17]; default: 1;
- *  set this field to 1 to enable lp2hp ahb timeout handle
- */
-#define LPSYSREG_LP2HP_AHB_TIMEOUT_EN    (BIT(17))
-#define LPSYSREG_LP2HP_AHB_TIMEOUT_EN_M  (LPSYSREG_LP2HP_AHB_TIMEOUT_EN_V << LPSYSREG_LP2HP_AHB_TIMEOUT_EN_S)
-#define LPSYSREG_LP2HP_AHB_TIMEOUT_EN_V  0x00000001U
-#define LPSYSREG_LP2HP_AHB_TIMEOUT_EN_S  17
-/** LPSYSREG_LP2HP_AHB_TIMEOUT_THRES : R/W; bitpos: [22:18]; default: 31;
- *  This field used to set lp2hp ahb bus timeout  threshold
- */
-#define LPSYSREG_LP2HP_AHB_TIMEOUT_THRES    0x0000001FU
-#define LPSYSREG_LP2HP_AHB_TIMEOUT_THRES_M  (LPSYSREG_LP2HP_AHB_TIMEOUT_THRES_V << LPSYSREG_LP2HP_AHB_TIMEOUT_THRES_S)
-#define LPSYSREG_LP2HP_AHB_TIMEOUT_THRES_V  0x0000001FU
-#define LPSYSREG_LP2HP_AHB_TIMEOUT_THRES_S  18
-
-/** LPSYSREG_LP_CORE_IBUS_TIMEOUT_REG register
- *  need_des
- */
-#define LPSYSREG_LP_CORE_IBUS_TIMEOUT_REG (DR_REG_LP_SYS_BASE + 0x1b4)
-/** LPSYSREG_LP_CORE_IBUS_TIMEOUT_EN : R/W; bitpos: [0]; default: 1;
- *  set this field to 1 to enable lp core ibus timeout handle
- */
-#define LPSYSREG_LP_CORE_IBUS_TIMEOUT_EN    (BIT(0))
-#define LPSYSREG_LP_CORE_IBUS_TIMEOUT_EN_M  (LPSYSREG_LP_CORE_IBUS_TIMEOUT_EN_V << LPSYSREG_LP_CORE_IBUS_TIMEOUT_EN_S)
-#define LPSYSREG_LP_CORE_IBUS_TIMEOUT_EN_V  0x00000001U
-#define LPSYSREG_LP_CORE_IBUS_TIMEOUT_EN_S  0
-/** LPSYSREG_LP_CORE_IBUS_TIMEOUT_THRES : R/W; bitpos: [16:1]; default: 65535;
- *  This field used to set lp core ibus timeout  threshold
- */
-#define LPSYSREG_LP_CORE_IBUS_TIMEOUT_THRES    0x0000FFFFU
-#define LPSYSREG_LP_CORE_IBUS_TIMEOUT_THRES_M  (LPSYSREG_LP_CORE_IBUS_TIMEOUT_THRES_V << LPSYSREG_LP_CORE_IBUS_TIMEOUT_THRES_S)
-#define LPSYSREG_LP_CORE_IBUS_TIMEOUT_THRES_V  0x0000FFFFU
-#define LPSYSREG_LP_CORE_IBUS_TIMEOUT_THRES_S  1
-
-/** LPSYSREG_LP_CORE_DBUS_TIMEOUT_REG register
- *  need_des
- */
-#define LPSYSREG_LP_CORE_DBUS_TIMEOUT_REG (DR_REG_LP_SYS_BASE + 0x1b8)
-/** LPSYSREG_LP_CORE_DBUS_TIMEOUT_EN : R/W; bitpos: [0]; default: 1;
- *  set this field to 1 to enable lp core dbus timeout handle
- */
-#define LPSYSREG_LP_CORE_DBUS_TIMEOUT_EN    (BIT(0))
-#define LPSYSREG_LP_CORE_DBUS_TIMEOUT_EN_M  (LPSYSREG_LP_CORE_DBUS_TIMEOUT_EN_V << LPSYSREG_LP_CORE_DBUS_TIMEOUT_EN_S)
-#define LPSYSREG_LP_CORE_DBUS_TIMEOUT_EN_V  0x00000001U
-#define LPSYSREG_LP_CORE_DBUS_TIMEOUT_EN_S  0
-/** LPSYSREG_LP_CORE_DBUS_TIMEOUT_THRES : R/W; bitpos: [16:1]; default: 65535;
- *  This field used to set lp core dbus timeout  threshold
- */
-#define LPSYSREG_LP_CORE_DBUS_TIMEOUT_THRES    0x0000FFFFU
-#define LPSYSREG_LP_CORE_DBUS_TIMEOUT_THRES_M  (LPSYSREG_LP_CORE_DBUS_TIMEOUT_THRES_V << LPSYSREG_LP_CORE_DBUS_TIMEOUT_THRES_S)
-#define LPSYSREG_LP_CORE_DBUS_TIMEOUT_THRES_V  0x0000FFFFU
-#define LPSYSREG_LP_CORE_DBUS_TIMEOUT_THRES_S  1
-
-/** LPSYSREG_LP_CORE_ERR_RESP_DIS_REG register
- *  need_des
- */
-#define LPSYSREG_LP_CORE_ERR_RESP_DIS_REG (DR_REG_LP_SYS_BASE + 0x1bc)
-/** LPSYSREG_LP_CORE_ERR_RESP_DIS : R/W; bitpos: [2:0]; default: 0;
- *  Set bit0 to disable ibus err resp;Set bit1 to disable dbus err resp; Set bit 2 to
- *  disable ahb err resp.
- */
-#define LPSYSREG_LP_CORE_ERR_RESP_DIS    0x00000007U
-#define LPSYSREG_LP_CORE_ERR_RESP_DIS_M  (LPSYSREG_LP_CORE_ERR_RESP_DIS_V << LPSYSREG_LP_CORE_ERR_RESP_DIS_S)
-#define LPSYSREG_LP_CORE_ERR_RESP_DIS_V  0x00000007U
-#define LPSYSREG_LP_CORE_ERR_RESP_DIS_S  0
-
-/** LPSYSREG_RNG_CFG_REG register
- *  rng cfg register
- */
-#define LPSYSREG_RNG_CFG_REG (DR_REG_LP_SYS_BASE + 0x1c0)
-/** LPSYSREG_RNG_TIMER_EN : R/W; bitpos: [0]; default: 1;
- *  enable rng timer
- */
-#define LPSYSREG_RNG_TIMER_EN    (BIT(0))
-#define LPSYSREG_RNG_TIMER_EN_M  (LPSYSREG_RNG_TIMER_EN_V << LPSYSREG_RNG_TIMER_EN_S)
-#define LPSYSREG_RNG_TIMER_EN_V  0x00000001U
-#define LPSYSREG_RNG_TIMER_EN_S  0
-/** LPSYSREG_RNG_TIMER_PSCALE : R/W; bitpos: [8:1]; default: 1;
- *  configure ng timer pscale
- */
-#define LPSYSREG_RNG_TIMER_PSCALE    0x000000FFU
-#define LPSYSREG_RNG_TIMER_PSCALE_M  (LPSYSREG_RNG_TIMER_PSCALE_V << LPSYSREG_RNG_TIMER_PSCALE_S)
-#define LPSYSREG_RNG_TIMER_PSCALE_V  0x000000FFU
-#define LPSYSREG_RNG_TIMER_PSCALE_S  1
-/** LPSYSREG_RNG_SAR_ENABLE : R/W; bitpos: [9]; default: 0;
- *  enable rng_saradc
- */
-#define LPSYSREG_RNG_SAR_ENABLE    (BIT(9))
-#define LPSYSREG_RNG_SAR_ENABLE_M  (LPSYSREG_RNG_SAR_ENABLE_V << LPSYSREG_RNG_SAR_ENABLE_S)
-#define LPSYSREG_RNG_SAR_ENABLE_V  0x00000001U
-#define LPSYSREG_RNG_SAR_ENABLE_S  9
-/** LPSYSREG_RNG_SAR_DATA : RO; bitpos: [28:16]; default: 0;
- *  debug rng sar sample cnt
- */
-#define LPSYSREG_RNG_SAR_DATA    0x00001FFFU
-#define LPSYSREG_RNG_SAR_DATA_M  (LPSYSREG_RNG_SAR_DATA_V << LPSYSREG_RNG_SAR_DATA_S)
-#define LPSYSREG_RNG_SAR_DATA_V  0x00001FFFU
-#define LPSYSREG_RNG_SAR_DATA_S  16
-
-#ifdef __cplusplus
-}
-#endif

components/soc/esp32p4/include/soc/lp_system_reg.h

@@ -0,0 +1,1349 @@
+/**
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** LP_SYSTEM_REG_LP_SYS_VER_DATE_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_SYS_VER_DATE_REG (DR_REG_LP_SYS_BASE + 0x0)
+/** LP_SYSTEM_REG_VER_DATE : R/W; bitpos: [31:0]; default: 539165961;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_VER_DATE    0xFFFFFFFFU
+#define LP_SYSTEM_REG_VER_DATE_M  (LP_SYSTEM_REG_VER_DATE_V << LP_SYSTEM_REG_VER_DATE_S)
+#define LP_SYSTEM_REG_VER_DATE_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_VER_DATE_S  0
+
+/** LP_SYSTEM_REG_CLK_SEL_CTRL_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_CLK_SEL_CTRL_REG (DR_REG_LP_SYS_BASE + 0x4)
+/** LP_SYSTEM_REG_ENA_SW_SEL_SYS_CLK : R/W; bitpos: [16]; default: 0;
+ *  reserved
+ */
+#define LP_SYSTEM_REG_ENA_SW_SEL_SYS_CLK    (BIT(16))
+#define LP_SYSTEM_REG_ENA_SW_SEL_SYS_CLK_M  (LP_SYSTEM_REG_ENA_SW_SEL_SYS_CLK_V << LP_SYSTEM_REG_ENA_SW_SEL_SYS_CLK_S)
+#define LP_SYSTEM_REG_ENA_SW_SEL_SYS_CLK_V  0x00000001U
+#define LP_SYSTEM_REG_ENA_SW_SEL_SYS_CLK_S  16
+/** LP_SYSTEM_REG_SW_SYS_CLK_SRC_SEL : R/W; bitpos: [17]; default: 0;
+ *  reserved
+ */
+#define LP_SYSTEM_REG_SW_SYS_CLK_SRC_SEL    (BIT(17))
+#define LP_SYSTEM_REG_SW_SYS_CLK_SRC_SEL_M  (LP_SYSTEM_REG_SW_SYS_CLK_SRC_SEL_V << LP_SYSTEM_REG_SW_SYS_CLK_SRC_SEL_S)
+#define LP_SYSTEM_REG_SW_SYS_CLK_SRC_SEL_V  0x00000001U
+#define LP_SYSTEM_REG_SW_SYS_CLK_SRC_SEL_S  17
+
+/** LP_SYSTEM_REG_SYS_CTRL_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_SYS_CTRL_REG (DR_REG_LP_SYS_BASE + 0x8)
+/** LP_SYSTEM_REG_LP_CORE_DISABLE : R/W; bitpos: [0]; default: 0;
+ *  lp cpu disable
+ */
+#define LP_SYSTEM_REG_LP_CORE_DISABLE    (BIT(0))
+#define LP_SYSTEM_REG_LP_CORE_DISABLE_M  (LP_SYSTEM_REG_LP_CORE_DISABLE_V << LP_SYSTEM_REG_LP_CORE_DISABLE_S)
+#define LP_SYSTEM_REG_LP_CORE_DISABLE_V  0x00000001U
+#define LP_SYSTEM_REG_LP_CORE_DISABLE_S  0
+/** LP_SYSTEM_REG_SYS_SW_RST : WT; bitpos: [1]; default: 0;
+ *  digital system software reset bit
+ */
+#define LP_SYSTEM_REG_SYS_SW_RST    (BIT(1))
+#define LP_SYSTEM_REG_SYS_SW_RST_M  (LP_SYSTEM_REG_SYS_SW_RST_V << LP_SYSTEM_REG_SYS_SW_RST_S)
+#define LP_SYSTEM_REG_SYS_SW_RST_V  0x00000001U
+#define LP_SYSTEM_REG_SYS_SW_RST_S  1
+/** LP_SYSTEM_REG_FORCE_DOWNLOAD_BOOT : R/W; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_FORCE_DOWNLOAD_BOOT    (BIT(2))
+#define LP_SYSTEM_REG_FORCE_DOWNLOAD_BOOT_M  (LP_SYSTEM_REG_FORCE_DOWNLOAD_BOOT_V << LP_SYSTEM_REG_FORCE_DOWNLOAD_BOOT_S)
+#define LP_SYSTEM_REG_FORCE_DOWNLOAD_BOOT_V  0x00000001U
+#define LP_SYSTEM_REG_FORCE_DOWNLOAD_BOOT_S  2
+/** LP_SYSTEM_REG_DIG_FIB : R/W; bitpos: [10:3]; default: 255;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_DIG_FIB    0x000000FFU
+#define LP_SYSTEM_REG_DIG_FIB_M  (LP_SYSTEM_REG_DIG_FIB_V << LP_SYSTEM_REG_DIG_FIB_S)
+#define LP_SYSTEM_REG_DIG_FIB_V  0x000000FFU
+#define LP_SYSTEM_REG_DIG_FIB_S  3
+/** LP_SYSTEM_REG_IO_MUX_RESET_DISABLE : R/W; bitpos: [11]; default: 0;
+ *  reset disable bit for LP IOMUX
+ */
+#define LP_SYSTEM_REG_IO_MUX_RESET_DISABLE    (BIT(11))
+#define LP_SYSTEM_REG_IO_MUX_RESET_DISABLE_M  (LP_SYSTEM_REG_IO_MUX_RESET_DISABLE_V << LP_SYSTEM_REG_IO_MUX_RESET_DISABLE_S)
+#define LP_SYSTEM_REG_IO_MUX_RESET_DISABLE_V  0x00000001U
+#define LP_SYSTEM_REG_IO_MUX_RESET_DISABLE_S  11
+/** LP_SYSTEM_REG_ANA_FIB : RO; bitpos: [20:14]; default: 127;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_ANA_FIB    0x0000007FU
+#define LP_SYSTEM_REG_ANA_FIB_M  (LP_SYSTEM_REG_ANA_FIB_V << LP_SYSTEM_REG_ANA_FIB_S)
+#define LP_SYSTEM_REG_ANA_FIB_V  0x0000007FU
+#define LP_SYSTEM_REG_ANA_FIB_S  14
+/** LP_SYSTEM_REG_LP_FIB_SEL : R/W; bitpos: [28:21]; default: 255;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_FIB_SEL    0x000000FFU
+#define LP_SYSTEM_REG_LP_FIB_SEL_M  (LP_SYSTEM_REG_LP_FIB_SEL_V << LP_SYSTEM_REG_LP_FIB_SEL_S)
+#define LP_SYSTEM_REG_LP_FIB_SEL_V  0x000000FFU
+#define LP_SYSTEM_REG_LP_FIB_SEL_S  21
+/** LP_SYSTEM_REG_LP_CORE_ETM_WAKEUP_FLAG_CLR : WT; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_CORE_ETM_WAKEUP_FLAG_CLR    (BIT(29))
+#define LP_SYSTEM_REG_LP_CORE_ETM_WAKEUP_FLAG_CLR_M  (LP_SYSTEM_REG_LP_CORE_ETM_WAKEUP_FLAG_CLR_V << LP_SYSTEM_REG_LP_CORE_ETM_WAKEUP_FLAG_CLR_S)
+#define LP_SYSTEM_REG_LP_CORE_ETM_WAKEUP_FLAG_CLR_V  0x00000001U
+#define LP_SYSTEM_REG_LP_CORE_ETM_WAKEUP_FLAG_CLR_S  29
+/** LP_SYSTEM_REG_LP_CORE_ETM_WAKEUP_FLAG : R/WTC/SS; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_CORE_ETM_WAKEUP_FLAG    (BIT(30))
+#define LP_SYSTEM_REG_LP_CORE_ETM_WAKEUP_FLAG_M  (LP_SYSTEM_REG_LP_CORE_ETM_WAKEUP_FLAG_V << LP_SYSTEM_REG_LP_CORE_ETM_WAKEUP_FLAG_S)
+#define LP_SYSTEM_REG_LP_CORE_ETM_WAKEUP_FLAG_V  0x00000001U
+#define LP_SYSTEM_REG_LP_CORE_ETM_WAKEUP_FLAG_S  30
+/** LP_SYSTEM_REG_SYSTIMER_STALL_SEL : R/W; bitpos: [31]; default: 0;
+ *  0: use systimer_stall signal from hp_core0, 1: use systimer_stall signal from
+ *  hp_core1
+ */
+#define LP_SYSTEM_REG_SYSTIMER_STALL_SEL    (BIT(31))
+#define LP_SYSTEM_REG_SYSTIMER_STALL_SEL_M  (LP_SYSTEM_REG_SYSTIMER_STALL_SEL_V << LP_SYSTEM_REG_SYSTIMER_STALL_SEL_S)
+#define LP_SYSTEM_REG_SYSTIMER_STALL_SEL_V  0x00000001U
+#define LP_SYSTEM_REG_SYSTIMER_STALL_SEL_S  31
+
+/** LP_SYSTEM_REG_LP_CLK_CTRL_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_CLK_CTRL_REG (DR_REG_LP_SYS_BASE + 0xc)
+/** LP_SYSTEM_REG_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_CLK_EN    (BIT(0))
+#define LP_SYSTEM_REG_CLK_EN_M  (LP_SYSTEM_REG_CLK_EN_V << LP_SYSTEM_REG_CLK_EN_S)
+#define LP_SYSTEM_REG_CLK_EN_V  0x00000001U
+#define LP_SYSTEM_REG_CLK_EN_S  0
+/** LP_SYSTEM_REG_LP_FOSC_HP_CKEN : R/W; bitpos: [14]; default: 1;
+ *  reserved
+ */
+#define LP_SYSTEM_REG_LP_FOSC_HP_CKEN    (BIT(14))
+#define LP_SYSTEM_REG_LP_FOSC_HP_CKEN_M  (LP_SYSTEM_REG_LP_FOSC_HP_CKEN_V << LP_SYSTEM_REG_LP_FOSC_HP_CKEN_S)
+#define LP_SYSTEM_REG_LP_FOSC_HP_CKEN_V  0x00000001U
+#define LP_SYSTEM_REG_LP_FOSC_HP_CKEN_S  14
+
+/** LP_SYSTEM_REG_LP_RST_CTRL_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_RST_CTRL_REG (DR_REG_LP_SYS_BASE + 0x10)
+/** LP_SYSTEM_REG_ANA_RST_BYPASS : R/W; bitpos: [0]; default: 1;
+ *  analog source reset bypass : wdt,brown out,super wdt,glitch
+ */
+#define LP_SYSTEM_REG_ANA_RST_BYPASS    (BIT(0))
+#define LP_SYSTEM_REG_ANA_RST_BYPASS_M  (LP_SYSTEM_REG_ANA_RST_BYPASS_V << LP_SYSTEM_REG_ANA_RST_BYPASS_S)
+#define LP_SYSTEM_REG_ANA_RST_BYPASS_V  0x00000001U
+#define LP_SYSTEM_REG_ANA_RST_BYPASS_S  0
+/** LP_SYSTEM_REG_SYS_RST_BYPASS : R/W; bitpos: [1]; default: 1;
+ *  system source reset bypass : software reset,hp wdt,lp wdt,efuse
+ */
+#define LP_SYSTEM_REG_SYS_RST_BYPASS    (BIT(1))
+#define LP_SYSTEM_REG_SYS_RST_BYPASS_M  (LP_SYSTEM_REG_SYS_RST_BYPASS_V << LP_SYSTEM_REG_SYS_RST_BYPASS_S)
+#define LP_SYSTEM_REG_SYS_RST_BYPASS_V  0x00000001U
+#define LP_SYSTEM_REG_SYS_RST_BYPASS_S  1
+/** LP_SYSTEM_REG_EFUSE_FORCE_NORST : R/W; bitpos: [2]; default: 0;
+ *  efuse force no reset control
+ */
+#define LP_SYSTEM_REG_EFUSE_FORCE_NORST    (BIT(2))
+#define LP_SYSTEM_REG_EFUSE_FORCE_NORST_M  (LP_SYSTEM_REG_EFUSE_FORCE_NORST_V << LP_SYSTEM_REG_EFUSE_FORCE_NORST_S)
+#define LP_SYSTEM_REG_EFUSE_FORCE_NORST_V  0x00000001U
+#define LP_SYSTEM_REG_EFUSE_FORCE_NORST_S  2
+
+/** LP_SYSTEM_REG_LP_CORE_BOOT_ADDR_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_CORE_BOOT_ADDR_REG (DR_REG_LP_SYS_BASE + 0x18)
+/** LP_SYSTEM_REG_LP_CPU_BOOT_ADDR : R/W; bitpos: [31:0]; default: 1343225856;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_CPU_BOOT_ADDR    0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_CPU_BOOT_ADDR_M  (LP_SYSTEM_REG_LP_CPU_BOOT_ADDR_V << LP_SYSTEM_REG_LP_CPU_BOOT_ADDR_S)
+#define LP_SYSTEM_REG_LP_CPU_BOOT_ADDR_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_CPU_BOOT_ADDR_S  0
+
+/** LP_SYSTEM_REG_EXT_WAKEUP1_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_EXT_WAKEUP1_REG (DR_REG_LP_SYS_BASE + 0x1c)
+/** LP_SYSTEM_REG_EXT_WAKEUP1_SEL : R/W; bitpos: [15:0]; default: 0;
+ *  Bitmap to select RTC pads for ext wakeup1
+ */
+#define LP_SYSTEM_REG_EXT_WAKEUP1_SEL    0x0000FFFFU
+#define LP_SYSTEM_REG_EXT_WAKEUP1_SEL_M  (LP_SYSTEM_REG_EXT_WAKEUP1_SEL_V << LP_SYSTEM_REG_EXT_WAKEUP1_SEL_S)
+#define LP_SYSTEM_REG_EXT_WAKEUP1_SEL_V  0x0000FFFFU
+#define LP_SYSTEM_REG_EXT_WAKEUP1_SEL_S  0
+/** LP_SYSTEM_REG_EXT_WAKEUP1_STATUS_CLR : WT; bitpos: [16]; default: 0;
+ *  clear ext wakeup1 status
+ */
+#define LP_SYSTEM_REG_EXT_WAKEUP1_STATUS_CLR    (BIT(16))
+#define LP_SYSTEM_REG_EXT_WAKEUP1_STATUS_CLR_M  (LP_SYSTEM_REG_EXT_WAKEUP1_STATUS_CLR_V << LP_SYSTEM_REG_EXT_WAKEUP1_STATUS_CLR_S)
+#define LP_SYSTEM_REG_EXT_WAKEUP1_STATUS_CLR_V  0x00000001U
+#define LP_SYSTEM_REG_EXT_WAKEUP1_STATUS_CLR_S  16
+
+/** LP_SYSTEM_REG_EXT_WAKEUP1_STATUS_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_EXT_WAKEUP1_STATUS_REG (DR_REG_LP_SYS_BASE + 0x20)
+/** LP_SYSTEM_REG_EXT_WAKEUP1_STATUS : RO; bitpos: [15:0]; default: 0;
+ *  ext wakeup1 status
+ */
+#define LP_SYSTEM_REG_EXT_WAKEUP1_STATUS    0x0000FFFFU
+#define LP_SYSTEM_REG_EXT_WAKEUP1_STATUS_M  (LP_SYSTEM_REG_EXT_WAKEUP1_STATUS_V << LP_SYSTEM_REG_EXT_WAKEUP1_STATUS_S)
+#define LP_SYSTEM_REG_EXT_WAKEUP1_STATUS_V  0x0000FFFFU
+#define LP_SYSTEM_REG_EXT_WAKEUP1_STATUS_S  0
+
+/** LP_SYSTEM_REG_LP_TCM_PWR_CTRL_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_TCM_PWR_CTRL_REG (DR_REG_LP_SYS_BASE + 0x24)
+/** LP_SYSTEM_REG_LP_TCM_ROM_CLK_FORCE_ON : R/W; bitpos: [5]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_TCM_ROM_CLK_FORCE_ON    (BIT(5))
+#define LP_SYSTEM_REG_LP_TCM_ROM_CLK_FORCE_ON_M  (LP_SYSTEM_REG_LP_TCM_ROM_CLK_FORCE_ON_V << LP_SYSTEM_REG_LP_TCM_ROM_CLK_FORCE_ON_S)
+#define LP_SYSTEM_REG_LP_TCM_ROM_CLK_FORCE_ON_V  0x00000001U
+#define LP_SYSTEM_REG_LP_TCM_ROM_CLK_FORCE_ON_S  5
+/** LP_SYSTEM_REG_LP_TCM_RAM_CLK_FORCE_ON : R/W; bitpos: [7]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_TCM_RAM_CLK_FORCE_ON    (BIT(7))
+#define LP_SYSTEM_REG_LP_TCM_RAM_CLK_FORCE_ON_M  (LP_SYSTEM_REG_LP_TCM_RAM_CLK_FORCE_ON_V << LP_SYSTEM_REG_LP_TCM_RAM_CLK_FORCE_ON_S)
+#define LP_SYSTEM_REG_LP_TCM_RAM_CLK_FORCE_ON_V  0x00000001U
+#define LP_SYSTEM_REG_LP_TCM_RAM_CLK_FORCE_ON_S  7
+
+/** LP_SYSTEM_REG_BOOT_ADDR_HP_LP_REG_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_BOOT_ADDR_HP_LP_REG_REG (DR_REG_LP_SYS_BASE + 0x28)
+/** LP_SYSTEM_REG_BOOT_ADDR_HP_LP : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_BOOT_ADDR_HP_LP    0xFFFFFFFFU
+#define LP_SYSTEM_REG_BOOT_ADDR_HP_LP_M  (LP_SYSTEM_REG_BOOT_ADDR_HP_LP_V << LP_SYSTEM_REG_BOOT_ADDR_HP_LP_S)
+#define LP_SYSTEM_REG_BOOT_ADDR_HP_LP_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_BOOT_ADDR_HP_LP_S  0
+
+/** LP_SYSTEM_REG_LP_STORE0_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_STORE0_REG (DR_REG_LP_SYS_BASE + 0x2c)
+/** LP_SYSTEM_REG_LP_SCRATCH0 : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_SCRATCH0    0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_SCRATCH0_M  (LP_SYSTEM_REG_LP_SCRATCH0_V << LP_SYSTEM_REG_LP_SCRATCH0_S)
+#define LP_SYSTEM_REG_LP_SCRATCH0_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_SCRATCH0_S  0
+
+/** LP_SYSTEM_REG_LP_STORE1_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_STORE1_REG (DR_REG_LP_SYS_BASE + 0x30)
+/** LP_SYSTEM_REG_LP_SCRATCH1 : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_SCRATCH1    0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_SCRATCH1_M  (LP_SYSTEM_REG_LP_SCRATCH1_V << LP_SYSTEM_REG_LP_SCRATCH1_S)
+#define LP_SYSTEM_REG_LP_SCRATCH1_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_SCRATCH1_S  0
+
+/** LP_SYSTEM_REG_LP_STORE2_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_STORE2_REG (DR_REG_LP_SYS_BASE + 0x34)
+/** LP_SYSTEM_REG_LP_SCRATCH2 : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_SCRATCH2    0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_SCRATCH2_M  (LP_SYSTEM_REG_LP_SCRATCH2_V << LP_SYSTEM_REG_LP_SCRATCH2_S)
+#define LP_SYSTEM_REG_LP_SCRATCH2_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_SCRATCH2_S  0
+
+/** LP_SYSTEM_REG_LP_STORE3_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_STORE3_REG (DR_REG_LP_SYS_BASE + 0x38)
+/** LP_SYSTEM_REG_LP_SCRATCH3 : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_SCRATCH3    0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_SCRATCH3_M  (LP_SYSTEM_REG_LP_SCRATCH3_V << LP_SYSTEM_REG_LP_SCRATCH3_S)
+#define LP_SYSTEM_REG_LP_SCRATCH3_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_SCRATCH3_S  0
+
+/** LP_SYSTEM_REG_LP_STORE4_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_STORE4_REG (DR_REG_LP_SYS_BASE + 0x3c)
+/** LP_SYSTEM_REG_LP_SCRATCH4 : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_SCRATCH4    0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_SCRATCH4_M  (LP_SYSTEM_REG_LP_SCRATCH4_V << LP_SYSTEM_REG_LP_SCRATCH4_S)
+#define LP_SYSTEM_REG_LP_SCRATCH4_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_SCRATCH4_S  0
+
+/** LP_SYSTEM_REG_LP_STORE5_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_STORE5_REG (DR_REG_LP_SYS_BASE + 0x40)
+/** LP_SYSTEM_REG_LP_SCRATCH5 : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_SCRATCH5    0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_SCRATCH5_M  (LP_SYSTEM_REG_LP_SCRATCH5_V << LP_SYSTEM_REG_LP_SCRATCH5_S)
+#define LP_SYSTEM_REG_LP_SCRATCH5_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_SCRATCH5_S  0
+
+/** LP_SYSTEM_REG_LP_STORE6_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_STORE6_REG (DR_REG_LP_SYS_BASE + 0x44)
+/** LP_SYSTEM_REG_LP_SCRATCH6 : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_SCRATCH6    0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_SCRATCH6_M  (LP_SYSTEM_REG_LP_SCRATCH6_V << LP_SYSTEM_REG_LP_SCRATCH6_S)
+#define LP_SYSTEM_REG_LP_SCRATCH6_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_SCRATCH6_S  0
+
+/** LP_SYSTEM_REG_LP_STORE7_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_STORE7_REG (DR_REG_LP_SYS_BASE + 0x48)
+/** LP_SYSTEM_REG_LP_SCRATCH7 : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_SCRATCH7    0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_SCRATCH7_M  (LP_SYSTEM_REG_LP_SCRATCH7_V << LP_SYSTEM_REG_LP_SCRATCH7_S)
+#define LP_SYSTEM_REG_LP_SCRATCH7_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_SCRATCH7_S  0
+
+/** LP_SYSTEM_REG_LP_STORE8_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_STORE8_REG (DR_REG_LP_SYS_BASE + 0x4c)
+/** LP_SYSTEM_REG_LP_SCRATCH8 : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_SCRATCH8    0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_SCRATCH8_M  (LP_SYSTEM_REG_LP_SCRATCH8_V << LP_SYSTEM_REG_LP_SCRATCH8_S)
+#define LP_SYSTEM_REG_LP_SCRATCH8_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_SCRATCH8_S  0
+
+/** LP_SYSTEM_REG_LP_STORE9_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_STORE9_REG (DR_REG_LP_SYS_BASE + 0x50)
+/** LP_SYSTEM_REG_LP_SCRATCH9 : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_SCRATCH9    0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_SCRATCH9_M  (LP_SYSTEM_REG_LP_SCRATCH9_V << LP_SYSTEM_REG_LP_SCRATCH9_S)
+#define LP_SYSTEM_REG_LP_SCRATCH9_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_SCRATCH9_S  0
+
+/** LP_SYSTEM_REG_LP_STORE10_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_STORE10_REG (DR_REG_LP_SYS_BASE + 0x54)
+/** LP_SYSTEM_REG_LP_SCRATCH10 : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_SCRATCH10    0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_SCRATCH10_M  (LP_SYSTEM_REG_LP_SCRATCH10_V << LP_SYSTEM_REG_LP_SCRATCH10_S)
+#define LP_SYSTEM_REG_LP_SCRATCH10_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_SCRATCH10_S  0
+
+/** LP_SYSTEM_REG_LP_STORE11_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_STORE11_REG (DR_REG_LP_SYS_BASE + 0x58)
+/** LP_SYSTEM_REG_LP_SCRATCH11 : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_SCRATCH11    0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_SCRATCH11_M  (LP_SYSTEM_REG_LP_SCRATCH11_V << LP_SYSTEM_REG_LP_SCRATCH11_S)
+#define LP_SYSTEM_REG_LP_SCRATCH11_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_SCRATCH11_S  0
+
+/** LP_SYSTEM_REG_LP_STORE12_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_STORE12_REG (DR_REG_LP_SYS_BASE + 0x5c)
+/** LP_SYSTEM_REG_LP_SCRATCH12 : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_SCRATCH12    0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_SCRATCH12_M  (LP_SYSTEM_REG_LP_SCRATCH12_V << LP_SYSTEM_REG_LP_SCRATCH12_S)
+#define LP_SYSTEM_REG_LP_SCRATCH12_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_SCRATCH12_S  0
+
+/** LP_SYSTEM_REG_LP_STORE13_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_STORE13_REG (DR_REG_LP_SYS_BASE + 0x60)
+/** LP_SYSTEM_REG_LP_SCRATCH13 : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_SCRATCH13    0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_SCRATCH13_M  (LP_SYSTEM_REG_LP_SCRATCH13_V << LP_SYSTEM_REG_LP_SCRATCH13_S)
+#define LP_SYSTEM_REG_LP_SCRATCH13_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_SCRATCH13_S  0
+
+/** LP_SYSTEM_REG_LP_STORE14_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_STORE14_REG (DR_REG_LP_SYS_BASE + 0x64)
+/** LP_SYSTEM_REG_LP_SCRATCH14 : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_SCRATCH14    0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_SCRATCH14_M  (LP_SYSTEM_REG_LP_SCRATCH14_V << LP_SYSTEM_REG_LP_SCRATCH14_S)
+#define LP_SYSTEM_REG_LP_SCRATCH14_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_SCRATCH14_S  0
+
+/** LP_SYSTEM_REG_LP_STORE15_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_STORE15_REG (DR_REG_LP_SYS_BASE + 0x68)
+/** LP_SYSTEM_REG_LP_SCRATCH15 : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_SCRATCH15    0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_SCRATCH15_M  (LP_SYSTEM_REG_LP_SCRATCH15_V << LP_SYSTEM_REG_LP_SCRATCH15_S)
+#define LP_SYSTEM_REG_LP_SCRATCH15_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_SCRATCH15_S  0
+
+/** LP_SYSTEM_REG_LP_PROBEA_CTRL_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_PROBEA_CTRL_REG (DR_REG_LP_SYS_BASE + 0x6c)
+/** LP_SYSTEM_REG_PROBE_A_MOD_SEL : R/W; bitpos: [15:0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_PROBE_A_MOD_SEL    0x0000FFFFU
+#define LP_SYSTEM_REG_PROBE_A_MOD_SEL_M  (LP_SYSTEM_REG_PROBE_A_MOD_SEL_V << LP_SYSTEM_REG_PROBE_A_MOD_SEL_S)
+#define LP_SYSTEM_REG_PROBE_A_MOD_SEL_V  0x0000FFFFU
+#define LP_SYSTEM_REG_PROBE_A_MOD_SEL_S  0
+/** LP_SYSTEM_REG_PROBE_A_TOP_SEL : R/W; bitpos: [23:16]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_PROBE_A_TOP_SEL    0x000000FFU
+#define LP_SYSTEM_REG_PROBE_A_TOP_SEL_M  (LP_SYSTEM_REG_PROBE_A_TOP_SEL_V << LP_SYSTEM_REG_PROBE_A_TOP_SEL_S)
+#define LP_SYSTEM_REG_PROBE_A_TOP_SEL_V  0x000000FFU
+#define LP_SYSTEM_REG_PROBE_A_TOP_SEL_S  16
+/** LP_SYSTEM_REG_PROBE_L_SEL : R/W; bitpos: [25:24]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_PROBE_L_SEL    0x00000003U
+#define LP_SYSTEM_REG_PROBE_L_SEL_M  (LP_SYSTEM_REG_PROBE_L_SEL_V << LP_SYSTEM_REG_PROBE_L_SEL_S)
+#define LP_SYSTEM_REG_PROBE_L_SEL_V  0x00000003U
+#define LP_SYSTEM_REG_PROBE_L_SEL_S  24
+/** LP_SYSTEM_REG_PROBE_H_SEL : R/W; bitpos: [27:26]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_PROBE_H_SEL    0x00000003U
+#define LP_SYSTEM_REG_PROBE_H_SEL_M  (LP_SYSTEM_REG_PROBE_H_SEL_V << LP_SYSTEM_REG_PROBE_H_SEL_S)
+#define LP_SYSTEM_REG_PROBE_H_SEL_V  0x00000003U
+#define LP_SYSTEM_REG_PROBE_H_SEL_S  26
+/** LP_SYSTEM_REG_PROBE_GLOBAL_EN : R/W; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_PROBE_GLOBAL_EN    (BIT(28))
+#define LP_SYSTEM_REG_PROBE_GLOBAL_EN_M  (LP_SYSTEM_REG_PROBE_GLOBAL_EN_V << LP_SYSTEM_REG_PROBE_GLOBAL_EN_S)
+#define LP_SYSTEM_REG_PROBE_GLOBAL_EN_V  0x00000001U
+#define LP_SYSTEM_REG_PROBE_GLOBAL_EN_S  28
+
+/** LP_SYSTEM_REG_LP_PROBEB_CTRL_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_PROBEB_CTRL_REG (DR_REG_LP_SYS_BASE + 0x70)
+/** LP_SYSTEM_REG_PROBE_B_MOD_SEL : R/W; bitpos: [15:0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_PROBE_B_MOD_SEL    0x0000FFFFU
+#define LP_SYSTEM_REG_PROBE_B_MOD_SEL_M  (LP_SYSTEM_REG_PROBE_B_MOD_SEL_V << LP_SYSTEM_REG_PROBE_B_MOD_SEL_S)
+#define LP_SYSTEM_REG_PROBE_B_MOD_SEL_V  0x0000FFFFU
+#define LP_SYSTEM_REG_PROBE_B_MOD_SEL_S  0
+/** LP_SYSTEM_REG_PROBE_B_TOP_SEL : R/W; bitpos: [23:16]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_PROBE_B_TOP_SEL    0x000000FFU
+#define LP_SYSTEM_REG_PROBE_B_TOP_SEL_M  (LP_SYSTEM_REG_PROBE_B_TOP_SEL_V << LP_SYSTEM_REG_PROBE_B_TOP_SEL_S)
+#define LP_SYSTEM_REG_PROBE_B_TOP_SEL_V  0x000000FFU
+#define LP_SYSTEM_REG_PROBE_B_TOP_SEL_S  16
+/** LP_SYSTEM_REG_PROBE_B_EN : R/W; bitpos: [24]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_PROBE_B_EN    (BIT(24))
+#define LP_SYSTEM_REG_PROBE_B_EN_M  (LP_SYSTEM_REG_PROBE_B_EN_V << LP_SYSTEM_REG_PROBE_B_EN_S)
+#define LP_SYSTEM_REG_PROBE_B_EN_V  0x00000001U
+#define LP_SYSTEM_REG_PROBE_B_EN_S  24
+
+/** LP_SYSTEM_REG_LP_PROBE_OUT_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_PROBE_OUT_REG (DR_REG_LP_SYS_BASE + 0x74)
+/** LP_SYSTEM_REG_PROBE_TOP_OUT : RO; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_PROBE_TOP_OUT    0xFFFFFFFFU
+#define LP_SYSTEM_REG_PROBE_TOP_OUT_M  (LP_SYSTEM_REG_PROBE_TOP_OUT_V << LP_SYSTEM_REG_PROBE_TOP_OUT_S)
+#define LP_SYSTEM_REG_PROBE_TOP_OUT_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_PROBE_TOP_OUT_S  0
+
+/** LP_SYSTEM_REG_F2S_APB_BRG_CNTL_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_F2S_APB_BRG_CNTL_REG (DR_REG_LP_SYS_BASE + 0x9c)
+/** LP_SYSTEM_REG_F2S_APB_POSTW_EN : R/W; bitpos: [0]; default: 0;
+ *  reserved
+ */
+#define LP_SYSTEM_REG_F2S_APB_POSTW_EN    (BIT(0))
+#define LP_SYSTEM_REG_F2S_APB_POSTW_EN_M  (LP_SYSTEM_REG_F2S_APB_POSTW_EN_V << LP_SYSTEM_REG_F2S_APB_POSTW_EN_S)
+#define LP_SYSTEM_REG_F2S_APB_POSTW_EN_V  0x00000001U
+#define LP_SYSTEM_REG_F2S_APB_POSTW_EN_S  0
+
+/** LP_SYSTEM_REG_USB_CTRL_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_USB_CTRL_REG (DR_REG_LP_SYS_BASE + 0x100)
+/** LP_SYSTEM_REG_SW_HW_USB_PHY_SEL : R/W; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_SW_HW_USB_PHY_SEL    (BIT(0))
+#define LP_SYSTEM_REG_SW_HW_USB_PHY_SEL_M  (LP_SYSTEM_REG_SW_HW_USB_PHY_SEL_V << LP_SYSTEM_REG_SW_HW_USB_PHY_SEL_S)
+#define LP_SYSTEM_REG_SW_HW_USB_PHY_SEL_V  0x00000001U
+#define LP_SYSTEM_REG_SW_HW_USB_PHY_SEL_S  0
+/** LP_SYSTEM_REG_SW_USB_PHY_SEL : R/W; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_SW_USB_PHY_SEL    (BIT(1))
+#define LP_SYSTEM_REG_SW_USB_PHY_SEL_M  (LP_SYSTEM_REG_SW_USB_PHY_SEL_V << LP_SYSTEM_REG_SW_USB_PHY_SEL_S)
+#define LP_SYSTEM_REG_SW_USB_PHY_SEL_V  0x00000001U
+#define LP_SYSTEM_REG_SW_USB_PHY_SEL_S  1
+/** LP_SYSTEM_REG_USBOTG20_WAKEUP_CLR : WT; bitpos: [2]; default: 0;
+ *  clear usb wakeup to PMU.
+ */
+#define LP_SYSTEM_REG_USBOTG20_WAKEUP_CLR    (BIT(2))
+#define LP_SYSTEM_REG_USBOTG20_WAKEUP_CLR_M  (LP_SYSTEM_REG_USBOTG20_WAKEUP_CLR_V << LP_SYSTEM_REG_USBOTG20_WAKEUP_CLR_S)
+#define LP_SYSTEM_REG_USBOTG20_WAKEUP_CLR_V  0x00000001U
+#define LP_SYSTEM_REG_USBOTG20_WAKEUP_CLR_S  2
+/** LP_SYSTEM_REG_USBOTG20_IN_SUSPEND : R/W; bitpos: [3]; default: 0;
+ *  indicate usb otg2.0 is in suspend state.
+ */
+#define LP_SYSTEM_REG_USBOTG20_IN_SUSPEND    (BIT(3))
+#define LP_SYSTEM_REG_USBOTG20_IN_SUSPEND_M  (LP_SYSTEM_REG_USBOTG20_IN_SUSPEND_V << LP_SYSTEM_REG_USBOTG20_IN_SUSPEND_S)
+#define LP_SYSTEM_REG_USBOTG20_IN_SUSPEND_V  0x00000001U
+#define LP_SYSTEM_REG_USBOTG20_IN_SUSPEND_S  3
+
+/** LP_SYSTEM_REG_ANA_XPD_PAD_GROUP_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_ANA_XPD_PAD_GROUP_REG (DR_REG_LP_SYS_BASE + 0x10c)
+/** LP_SYSTEM_REG_ANA_REG_XPD_PAD_GROUP : R/W; bitpos: [7:0]; default: 255;
+ *  Set 1 to power up pad group
+ */
+#define LP_SYSTEM_REG_ANA_REG_XPD_PAD_GROUP    0x000000FFU
+#define LP_SYSTEM_REG_ANA_REG_XPD_PAD_GROUP_M  (LP_SYSTEM_REG_ANA_REG_XPD_PAD_GROUP_V << LP_SYSTEM_REG_ANA_REG_XPD_PAD_GROUP_S)
+#define LP_SYSTEM_REG_ANA_REG_XPD_PAD_GROUP_V  0x000000FFU
+#define LP_SYSTEM_REG_ANA_REG_XPD_PAD_GROUP_S  0
+
+/** LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_CS_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_CS_REG (DR_REG_LP_SYS_BASE + 0x110)
+/** LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_EN : R/W; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_EN    (BIT(0))
+#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_EN_M  (LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_EN_V << LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_EN_S)
+#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_EN_V  0x00000001U
+#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_EN_S  0
+/** LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_RESULT : RO; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_RESULT    (BIT(1))
+#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_RESULT_M  (LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_RESULT_V << LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_RESULT_S)
+#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_RESULT_V  0x00000001U
+#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_RESULT_S  1
+
+/** LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_LOW_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_LOW_REG (DR_REG_LP_SYS_BASE + 0x114)
+/** LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_LOW : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_LOW    0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_LOW_M  (LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_LOW_V << LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_LOW_S)
+#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_LOW_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_LOW_S  0
+
+/** LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_HIGH_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_HIGH_REG (DR_REG_LP_SYS_BASE + 0x118)
+/** LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_HIGH : R/W; bitpos: [31:0]; default: 4294967295;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_HIGH    0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_HIGH_M  (LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_HIGH_V << LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_HIGH_S)
+#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_HIGH_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_TCM_RAM_RDN_ECO_HIGH_S  0
+
+/** LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_CS_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_CS_REG (DR_REG_LP_SYS_BASE + 0x11c)
+/** LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_EN : R/W; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_EN    (BIT(0))
+#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_EN_M  (LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_EN_V << LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_EN_S)
+#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_EN_V  0x00000001U
+#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_EN_S  0
+/** LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_RESULT : RO; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_RESULT    (BIT(1))
+#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_RESULT_M  (LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_RESULT_V << LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_RESULT_S)
+#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_RESULT_V  0x00000001U
+#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_RESULT_S  1
+
+/** LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_LOW_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_LOW_REG (DR_REG_LP_SYS_BASE + 0x120)
+/** LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_LOW : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_LOW    0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_LOW_M  (LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_LOW_V << LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_LOW_S)
+#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_LOW_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_LOW_S  0
+
+/** LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_HIGH_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_HIGH_REG (DR_REG_LP_SYS_BASE + 0x124)
+/** LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_HIGH : R/W; bitpos: [31:0]; default: 4294967295;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_HIGH    0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_HIGH_M  (LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_HIGH_V << LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_HIGH_S)
+#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_HIGH_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_TCM_ROM_RDN_ECO_HIGH_S  0
+
+/** LP_SYSTEM_REG_HP_ROOT_CLK_CTRL_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_HP_ROOT_CLK_CTRL_REG (DR_REG_LP_SYS_BASE + 0x130)
+/** LP_SYSTEM_REG_CPU_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  clock gate enable for hp cpu root 400M clk
+ */
+#define LP_SYSTEM_REG_CPU_CLK_EN    (BIT(0))
+#define LP_SYSTEM_REG_CPU_CLK_EN_M  (LP_SYSTEM_REG_CPU_CLK_EN_V << LP_SYSTEM_REG_CPU_CLK_EN_S)
+#define LP_SYSTEM_REG_CPU_CLK_EN_V  0x00000001U
+#define LP_SYSTEM_REG_CPU_CLK_EN_S  0
+/** LP_SYSTEM_REG_SYS_CLK_EN : R/W; bitpos: [1]; default: 1;
+ *  clock gate enable for hp sys root 480M clk
+ */
+#define LP_SYSTEM_REG_SYS_CLK_EN    (BIT(1))
+#define LP_SYSTEM_REG_SYS_CLK_EN_M  (LP_SYSTEM_REG_SYS_CLK_EN_V << LP_SYSTEM_REG_SYS_CLK_EN_S)
+#define LP_SYSTEM_REG_SYS_CLK_EN_V  0x00000001U
+#define LP_SYSTEM_REG_SYS_CLK_EN_S  1
+
+/** LP_SYSTEM_REG_LP_PMU_RDN_ECO_LOW_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_PMU_RDN_ECO_LOW_REG (DR_REG_LP_SYS_BASE + 0x138)
+/** LP_SYSTEM_REG_PMU_RDN_ECO_LOW : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_PMU_RDN_ECO_LOW    0xFFFFFFFFU
+#define LP_SYSTEM_REG_PMU_RDN_ECO_LOW_M  (LP_SYSTEM_REG_PMU_RDN_ECO_LOW_V << LP_SYSTEM_REG_PMU_RDN_ECO_LOW_S)
+#define LP_SYSTEM_REG_PMU_RDN_ECO_LOW_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_PMU_RDN_ECO_LOW_S  0
+
+/** LP_SYSTEM_REG_LP_PMU_RDN_ECO_HIGH_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_PMU_RDN_ECO_HIGH_REG (DR_REG_LP_SYS_BASE + 0x13c)
+/** LP_SYSTEM_REG_PMU_RDN_ECO_HIGH : R/W; bitpos: [31:0]; default: 4294967295;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_PMU_RDN_ECO_HIGH    0xFFFFFFFFU
+#define LP_SYSTEM_REG_PMU_RDN_ECO_HIGH_M  (LP_SYSTEM_REG_PMU_RDN_ECO_HIGH_V << LP_SYSTEM_REG_PMU_RDN_ECO_HIGH_S)
+#define LP_SYSTEM_REG_PMU_RDN_ECO_HIGH_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_PMU_RDN_ECO_HIGH_S  0
+
+/** LP_SYSTEM_REG_PAD_COMP0_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_PAD_COMP0_REG (DR_REG_LP_SYS_BASE + 0x148)
+/** LP_SYSTEM_REG_DREF_COMP0 : R/W; bitpos: [2:0]; default: 0;
+ *  pad comp dref
+ */
+#define LP_SYSTEM_REG_DREF_COMP0    0x00000007U
+#define LP_SYSTEM_REG_DREF_COMP0_M  (LP_SYSTEM_REG_DREF_COMP0_V << LP_SYSTEM_REG_DREF_COMP0_S)
+#define LP_SYSTEM_REG_DREF_COMP0_V  0x00000007U
+#define LP_SYSTEM_REG_DREF_COMP0_S  0
+/** LP_SYSTEM_REG_MODE_COMP0 : R/W; bitpos: [3]; default: 0;
+ *  pad comp mode
+ */
+#define LP_SYSTEM_REG_MODE_COMP0    (BIT(3))
+#define LP_SYSTEM_REG_MODE_COMP0_M  (LP_SYSTEM_REG_MODE_COMP0_V << LP_SYSTEM_REG_MODE_COMP0_S)
+#define LP_SYSTEM_REG_MODE_COMP0_V  0x00000001U
+#define LP_SYSTEM_REG_MODE_COMP0_S  3
+/** LP_SYSTEM_REG_XPD_COMP0 : R/W; bitpos: [4]; default: 0;
+ *  pad comp xpd
+ */
+#define LP_SYSTEM_REG_XPD_COMP0    (BIT(4))
+#define LP_SYSTEM_REG_XPD_COMP0_M  (LP_SYSTEM_REG_XPD_COMP0_V << LP_SYSTEM_REG_XPD_COMP0_S)
+#define LP_SYSTEM_REG_XPD_COMP0_V  0x00000001U
+#define LP_SYSTEM_REG_XPD_COMP0_S  4
+
+/** LP_SYSTEM_REG_PAD_COMP1_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_PAD_COMP1_REG (DR_REG_LP_SYS_BASE + 0x14c)
+/** LP_SYSTEM_REG_DREF_COMP1 : R/W; bitpos: [2:0]; default: 0;
+ *  pad comp dref
+ */
+#define LP_SYSTEM_REG_DREF_COMP1    0x00000007U
+#define LP_SYSTEM_REG_DREF_COMP1_M  (LP_SYSTEM_REG_DREF_COMP1_V << LP_SYSTEM_REG_DREF_COMP1_S)
+#define LP_SYSTEM_REG_DREF_COMP1_V  0x00000007U
+#define LP_SYSTEM_REG_DREF_COMP1_S  0
+/** LP_SYSTEM_REG_MODE_COMP1 : R/W; bitpos: [3]; default: 0;
+ *  pad comp mode
+ */
+#define LP_SYSTEM_REG_MODE_COMP1    (BIT(3))
+#define LP_SYSTEM_REG_MODE_COMP1_M  (LP_SYSTEM_REG_MODE_COMP1_V << LP_SYSTEM_REG_MODE_COMP1_S)
+#define LP_SYSTEM_REG_MODE_COMP1_V  0x00000001U
+#define LP_SYSTEM_REG_MODE_COMP1_S  3
+/** LP_SYSTEM_REG_XPD_COMP1 : R/W; bitpos: [4]; default: 0;
+ *  pad comp xpd
+ */
+#define LP_SYSTEM_REG_XPD_COMP1    (BIT(4))
+#define LP_SYSTEM_REG_XPD_COMP1_M  (LP_SYSTEM_REG_XPD_COMP1_V << LP_SYSTEM_REG_XPD_COMP1_S)
+#define LP_SYSTEM_REG_XPD_COMP1_V  0x00000001U
+#define LP_SYSTEM_REG_XPD_COMP1_S  4
+
+/** LP_SYSTEM_REG_BACKUP_DMA_CFG0_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_BACKUP_DMA_CFG0_REG (DR_REG_LP_SYS_BASE + 0x154)
+/** LP_SYSTEM_REG_BURST_LIMIT_AON : R/W; bitpos: [4:0]; default: 10;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_BURST_LIMIT_AON    0x0000001FU
+#define LP_SYSTEM_REG_BURST_LIMIT_AON_M  (LP_SYSTEM_REG_BURST_LIMIT_AON_V << LP_SYSTEM_REG_BURST_LIMIT_AON_S)
+#define LP_SYSTEM_REG_BURST_LIMIT_AON_V  0x0000001FU
+#define LP_SYSTEM_REG_BURST_LIMIT_AON_S  0
+/** LP_SYSTEM_REG_READ_INTERVAL_AON : R/W; bitpos: [11:5]; default: 10;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_READ_INTERVAL_AON    0x0000007FU
+#define LP_SYSTEM_REG_READ_INTERVAL_AON_M  (LP_SYSTEM_REG_READ_INTERVAL_AON_V << LP_SYSTEM_REG_READ_INTERVAL_AON_S)
+#define LP_SYSTEM_REG_READ_INTERVAL_AON_V  0x0000007FU
+#define LP_SYSTEM_REG_READ_INTERVAL_AON_S  5
+/** LP_SYSTEM_REG_LINK_BACKUP_TOUT_THRES_AON : R/W; bitpos: [21:12]; default: 100;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LINK_BACKUP_TOUT_THRES_AON    0x000003FFU
+#define LP_SYSTEM_REG_LINK_BACKUP_TOUT_THRES_AON_M  (LP_SYSTEM_REG_LINK_BACKUP_TOUT_THRES_AON_V << LP_SYSTEM_REG_LINK_BACKUP_TOUT_THRES_AON_S)
+#define LP_SYSTEM_REG_LINK_BACKUP_TOUT_THRES_AON_V  0x000003FFU
+#define LP_SYSTEM_REG_LINK_BACKUP_TOUT_THRES_AON_S  12
+/** LP_SYSTEM_REG_LINK_TOUT_THRES_AON : R/W; bitpos: [31:22]; default: 100;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LINK_TOUT_THRES_AON    0x000003FFU
+#define LP_SYSTEM_REG_LINK_TOUT_THRES_AON_M  (LP_SYSTEM_REG_LINK_TOUT_THRES_AON_V << LP_SYSTEM_REG_LINK_TOUT_THRES_AON_S)
+#define LP_SYSTEM_REG_LINK_TOUT_THRES_AON_V  0x000003FFU
+#define LP_SYSTEM_REG_LINK_TOUT_THRES_AON_S  22
+
+/** LP_SYSTEM_REG_BACKUP_DMA_CFG1_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_BACKUP_DMA_CFG1_REG (DR_REG_LP_SYS_BASE + 0x158)
+/** LP_SYSTEM_REG_AON_BYPASS : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_AON_BYPASS    (BIT(31))
+#define LP_SYSTEM_REG_AON_BYPASS_M  (LP_SYSTEM_REG_AON_BYPASS_V << LP_SYSTEM_REG_AON_BYPASS_S)
+#define LP_SYSTEM_REG_AON_BYPASS_V  0x00000001U
+#define LP_SYSTEM_REG_AON_BYPASS_S  31
+
+/** LP_SYSTEM_REG_BACKUP_DMA_CFG2_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_BACKUP_DMA_CFG2_REG (DR_REG_LP_SYS_BASE + 0x15c)
+/** LP_SYSTEM_REG_LINK_ADDR_AON : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LINK_ADDR_AON    0xFFFFFFFFU
+#define LP_SYSTEM_REG_LINK_ADDR_AON_M  (LP_SYSTEM_REG_LINK_ADDR_AON_V << LP_SYSTEM_REG_LINK_ADDR_AON_S)
+#define LP_SYSTEM_REG_LINK_ADDR_AON_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_LINK_ADDR_AON_S  0
+
+/** LP_SYSTEM_REG_BOOT_ADDR_HP_CORE1_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_BOOT_ADDR_HP_CORE1_REG (DR_REG_LP_SYS_BASE + 0x164)
+/** LP_SYSTEM_REG_BOOT_ADDR_HP_CORE1 : R/W; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_BOOT_ADDR_HP_CORE1    0xFFFFFFFFU
+#define LP_SYSTEM_REG_BOOT_ADDR_HP_CORE1_M  (LP_SYSTEM_REG_BOOT_ADDR_HP_CORE1_V << LP_SYSTEM_REG_BOOT_ADDR_HP_CORE1_S)
+#define LP_SYSTEM_REG_BOOT_ADDR_HP_CORE1_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_BOOT_ADDR_HP_CORE1_S  0
+
+/** LP_SYSTEM_REG_LP_ADDRHOLE_ADDR_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_ADDRHOLE_ADDR_REG (DR_REG_LP_SYS_BASE + 0x168)
+/** LP_SYSTEM_REG_LP_ADDRHOLE_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_ADDRHOLE_ADDR    0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_ADDRHOLE_ADDR_M  (LP_SYSTEM_REG_LP_ADDRHOLE_ADDR_V << LP_SYSTEM_REG_LP_ADDRHOLE_ADDR_S)
+#define LP_SYSTEM_REG_LP_ADDRHOLE_ADDR_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_ADDRHOLE_ADDR_S  0
+
+/** LP_SYSTEM_REG_LP_ADDRHOLE_INFO_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_ADDRHOLE_INFO_REG (DR_REG_LP_SYS_BASE + 0x16c)
+/** LP_SYSTEM_REG_LP_ADDRHOLE_ID : RO; bitpos: [4:0]; default: 0;
+ *  master id: 5'h0: hp core0, 5'h1:hp core1, 5'h2:lp core, 5'h3:usb otg11, 5'h4:
+ *  regdma, 5'h5: gmac, 5'h5 sdmmc, 5'h7: usbotg20, 5'h8: trace0, 5'h9: trace1, 5'ha
+ *  tcm monitor, 5'hb: l2mem monitor. 5'h10~5'h1f: ahb pdma.
+ */
+#define LP_SYSTEM_REG_LP_ADDRHOLE_ID    0x0000001FU
+#define LP_SYSTEM_REG_LP_ADDRHOLE_ID_M  (LP_SYSTEM_REG_LP_ADDRHOLE_ID_V << LP_SYSTEM_REG_LP_ADDRHOLE_ID_S)
+#define LP_SYSTEM_REG_LP_ADDRHOLE_ID_V  0x0000001FU
+#define LP_SYSTEM_REG_LP_ADDRHOLE_ID_S  0
+/** LP_SYSTEM_REG_LP_ADDRHOLE_WR : RO; bitpos: [5]; default: 0;
+ *  1:write trans, 0: read trans.
+ */
+#define LP_SYSTEM_REG_LP_ADDRHOLE_WR    (BIT(5))
+#define LP_SYSTEM_REG_LP_ADDRHOLE_WR_M  (LP_SYSTEM_REG_LP_ADDRHOLE_WR_V << LP_SYSTEM_REG_LP_ADDRHOLE_WR_S)
+#define LP_SYSTEM_REG_LP_ADDRHOLE_WR_V  0x00000001U
+#define LP_SYSTEM_REG_LP_ADDRHOLE_WR_S  5
+/** LP_SYSTEM_REG_LP_ADDRHOLE_SECURE : RO; bitpos: [6]; default: 0;
+ *  1: illegal address access, 0: access without permission
+ */
+#define LP_SYSTEM_REG_LP_ADDRHOLE_SECURE    (BIT(6))
+#define LP_SYSTEM_REG_LP_ADDRHOLE_SECURE_M  (LP_SYSTEM_REG_LP_ADDRHOLE_SECURE_V << LP_SYSTEM_REG_LP_ADDRHOLE_SECURE_S)
+#define LP_SYSTEM_REG_LP_ADDRHOLE_SECURE_V  0x00000001U
+#define LP_SYSTEM_REG_LP_ADDRHOLE_SECURE_S  6
+
+/** LP_SYSTEM_REG_INT_RAW_REG register
+ *  raw interrupt register
+ */
+#define LP_SYSTEM_REG_INT_RAW_REG (DR_REG_LP_SYS_BASE + 0x170)
+/** LP_SYSTEM_REG_LP_ADDRHOLE_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0;
+ *  the raw interrupt status of lp addrhole(for lp peri  and lp ram tee apm, and lp
+ *  matrix default slave)
+ */
+#define LP_SYSTEM_REG_LP_ADDRHOLE_INT_RAW    (BIT(0))
+#define LP_SYSTEM_REG_LP_ADDRHOLE_INT_RAW_M  (LP_SYSTEM_REG_LP_ADDRHOLE_INT_RAW_V << LP_SYSTEM_REG_LP_ADDRHOLE_INT_RAW_S)
+#define LP_SYSTEM_REG_LP_ADDRHOLE_INT_RAW_V  0x00000001U
+#define LP_SYSTEM_REG_LP_ADDRHOLE_INT_RAW_S  0
+/** LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_RAW : R/SS/WTC; bitpos: [1]; default: 0;
+ *  the raw interrupt status of idbus addrhole(only for lp cpu ibus and dbus)
+ */
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_RAW    (BIT(1))
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_RAW_M  (LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_RAW_V << LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_RAW_S)
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_RAW_V  0x00000001U
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_RAW_S  1
+/** LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_RAW : R/SS/WTC; bitpos: [2]; default: 0;
+ *  the raw interrupt status of lp core ahb bus timeout
+ */
+#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_RAW    (BIT(2))
+#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_RAW_M  (LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_RAW_V << LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_RAW_S)
+#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_RAW_V  0x00000001U
+#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_RAW_S  2
+/** LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_RAW : R/SS/WTC; bitpos: [3]; default: 0;
+ *  the raw interrupt status of lp core  ibus timeout
+ */
+#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_RAW    (BIT(3))
+#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_RAW_M  (LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_RAW_V << LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_RAW_S)
+#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_RAW_V  0x00000001U
+#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_RAW_S  3
+/** LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_RAW : R/SS/WTC; bitpos: [4]; default: 0;
+ *  the raw interrupt status of lp core  dbus timeout
+ */
+#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_RAW    (BIT(4))
+#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_RAW_M  (LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_RAW_V << LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_RAW_S)
+#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_RAW_V  0x00000001U
+#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_RAW_S  4
+/** LP_SYSTEM_REG_ETM_TASK_ULP_INT_RAW : R/SS/WTC; bitpos: [5]; default: 0;
+ *  the raw interrupt status of etm task ulp
+ */
+#define LP_SYSTEM_REG_ETM_TASK_ULP_INT_RAW    (BIT(5))
+#define LP_SYSTEM_REG_ETM_TASK_ULP_INT_RAW_M  (LP_SYSTEM_REG_ETM_TASK_ULP_INT_RAW_V << LP_SYSTEM_REG_ETM_TASK_ULP_INT_RAW_S)
+#define LP_SYSTEM_REG_ETM_TASK_ULP_INT_RAW_V  0x00000001U
+#define LP_SYSTEM_REG_ETM_TASK_ULP_INT_RAW_S  5
+/** LP_SYSTEM_REG_SLOW_CLK_TICK_INT_RAW : R/SS/WTC; bitpos: [6]; default: 0;
+ *  the raw interrupt status of slow_clk_tick
+ */
+#define LP_SYSTEM_REG_SLOW_CLK_TICK_INT_RAW    (BIT(6))
+#define LP_SYSTEM_REG_SLOW_CLK_TICK_INT_RAW_M  (LP_SYSTEM_REG_SLOW_CLK_TICK_INT_RAW_V << LP_SYSTEM_REG_SLOW_CLK_TICK_INT_RAW_S)
+#define LP_SYSTEM_REG_SLOW_CLK_TICK_INT_RAW_V  0x00000001U
+#define LP_SYSTEM_REG_SLOW_CLK_TICK_INT_RAW_S  6
+
+/** LP_SYSTEM_REG_INT_ST_REG register
+ *  masked interrupt register
+ */
+#define LP_SYSTEM_REG_INT_ST_REG (DR_REG_LP_SYS_BASE + 0x174)
+/** LP_SYSTEM_REG_LP_ADDRHOLE_INT_ST : RO; bitpos: [0]; default: 0;
+ *  the masked interrupt status of lp addrhole (for lp peri  and lp ram tee apm, and lp
+ *  matrix default slave)
+ */
+#define LP_SYSTEM_REG_LP_ADDRHOLE_INT_ST    (BIT(0))
+#define LP_SYSTEM_REG_LP_ADDRHOLE_INT_ST_M  (LP_SYSTEM_REG_LP_ADDRHOLE_INT_ST_V << LP_SYSTEM_REG_LP_ADDRHOLE_INT_ST_S)
+#define LP_SYSTEM_REG_LP_ADDRHOLE_INT_ST_V  0x00000001U
+#define LP_SYSTEM_REG_LP_ADDRHOLE_INT_ST_S  0
+/** LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_ST : RO; bitpos: [1]; default: 0;
+ *  the masked interrupt status of idbus addrhole(only for lp cpu ibus and dbus)
+ */
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_ST    (BIT(1))
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_ST_M  (LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_ST_V << LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_ST_S)
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_ST_V  0x00000001U
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_ST_S  1
+/** LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_ST : RO; bitpos: [2]; default: 0;
+ *  the masked interrupt status of lp core ahb bus timeout
+ */
+#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_ST    (BIT(2))
+#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_ST_M  (LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_ST_V << LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_ST_S)
+#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_ST_V  0x00000001U
+#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_ST_S  2
+/** LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_ST : RO; bitpos: [3]; default: 0;
+ *  the masked interrupt status of lp core  ibus timeout
+ */
+#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_ST    (BIT(3))
+#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_ST_M  (LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_ST_V << LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_ST_S)
+#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_ST_V  0x00000001U
+#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_ST_S  3
+/** LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_ST : RO; bitpos: [4]; default: 0;
+ *  the masked interrupt status of lp core  dbus timeout
+ */
+#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_ST    (BIT(4))
+#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_ST_M  (LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_ST_V << LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_ST_S)
+#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_ST_V  0x00000001U
+#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_ST_S  4
+/** LP_SYSTEM_REG_ETM_TASK_ULP_INT_ST : RO; bitpos: [5]; default: 0;
+ *  the masked interrupt status of etm task ulp
+ */
+#define LP_SYSTEM_REG_ETM_TASK_ULP_INT_ST    (BIT(5))
+#define LP_SYSTEM_REG_ETM_TASK_ULP_INT_ST_M  (LP_SYSTEM_REG_ETM_TASK_ULP_INT_ST_V << LP_SYSTEM_REG_ETM_TASK_ULP_INT_ST_S)
+#define LP_SYSTEM_REG_ETM_TASK_ULP_INT_ST_V  0x00000001U
+#define LP_SYSTEM_REG_ETM_TASK_ULP_INT_ST_S  5
+/** LP_SYSTEM_REG_SLOW_CLK_TICK_INT_ST : RO; bitpos: [6]; default: 0;
+ *  the masked interrupt status of slow_clk_tick
+ */
+#define LP_SYSTEM_REG_SLOW_CLK_TICK_INT_ST    (BIT(6))
+#define LP_SYSTEM_REG_SLOW_CLK_TICK_INT_ST_M  (LP_SYSTEM_REG_SLOW_CLK_TICK_INT_ST_V << LP_SYSTEM_REG_SLOW_CLK_TICK_INT_ST_S)
+#define LP_SYSTEM_REG_SLOW_CLK_TICK_INT_ST_V  0x00000001U
+#define LP_SYSTEM_REG_SLOW_CLK_TICK_INT_ST_S  6
+
+/** LP_SYSTEM_REG_INT_ENA_REG register
+ *  masked interrupt register
+ */
+#define LP_SYSTEM_REG_INT_ENA_REG (DR_REG_LP_SYS_BASE + 0x178)
+/** LP_SYSTEM_REG_LP_ADDRHOLE_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  Write 1 to enable lp addrhole int
+ */
+#define LP_SYSTEM_REG_LP_ADDRHOLE_INT_ENA    (BIT(0))
+#define LP_SYSTEM_REG_LP_ADDRHOLE_INT_ENA_M  (LP_SYSTEM_REG_LP_ADDRHOLE_INT_ENA_V << LP_SYSTEM_REG_LP_ADDRHOLE_INT_ENA_S)
+#define LP_SYSTEM_REG_LP_ADDRHOLE_INT_ENA_V  0x00000001U
+#define LP_SYSTEM_REG_LP_ADDRHOLE_INT_ENA_S  0
+/** LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  Write 1 to enable idbus addrhole int
+ */
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_ENA    (BIT(1))
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_ENA_M  (LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_ENA_V << LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_ENA_S)
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_ENA_V  0x00000001U
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_ENA_S  1
+/** LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  Write 1 to enable lp_core_ahb_timeout int
+ */
+#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_ENA    (BIT(2))
+#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_ENA_M  (LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_ENA_V << LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_ENA_S)
+#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_ENA_V  0x00000001U
+#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_ENA_S  2
+/** LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  Write 1 to enable lp_core_ibus_timeout int
+ */
+#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_ENA    (BIT(3))
+#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_ENA_M  (LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_ENA_V << LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_ENA_S)
+#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_ENA_V  0x00000001U
+#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_ENA_S  3
+/** LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  Write 1 to enable lp_core_dbus_timeout int
+ */
+#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_ENA    (BIT(4))
+#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_ENA_M  (LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_ENA_V << LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_ENA_S)
+#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_ENA_V  0x00000001U
+#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_ENA_S  4
+/** LP_SYSTEM_REG_ETM_TASK_ULP_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  Write 1 to enable etm task ulp int
+ */
+#define LP_SYSTEM_REG_ETM_TASK_ULP_INT_ENA    (BIT(5))
+#define LP_SYSTEM_REG_ETM_TASK_ULP_INT_ENA_M  (LP_SYSTEM_REG_ETM_TASK_ULP_INT_ENA_V << LP_SYSTEM_REG_ETM_TASK_ULP_INT_ENA_S)
+#define LP_SYSTEM_REG_ETM_TASK_ULP_INT_ENA_V  0x00000001U
+#define LP_SYSTEM_REG_ETM_TASK_ULP_INT_ENA_S  5
+/** LP_SYSTEM_REG_SLOW_CLK_TICK_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  Write 1 to enable slow_clk_tick int
+ */
+#define LP_SYSTEM_REG_SLOW_CLK_TICK_INT_ENA    (BIT(6))
+#define LP_SYSTEM_REG_SLOW_CLK_TICK_INT_ENA_M  (LP_SYSTEM_REG_SLOW_CLK_TICK_INT_ENA_V << LP_SYSTEM_REG_SLOW_CLK_TICK_INT_ENA_S)
+#define LP_SYSTEM_REG_SLOW_CLK_TICK_INT_ENA_V  0x00000001U
+#define LP_SYSTEM_REG_SLOW_CLK_TICK_INT_ENA_S  6
+
+/** LP_SYSTEM_REG_INT_CLR_REG register
+ *  interrupt clear register
+ */
+#define LP_SYSTEM_REG_INT_CLR_REG (DR_REG_LP_SYS_BASE + 0x17c)
+/** LP_SYSTEM_REG_LP_ADDRHOLE_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  write 1 to clear lp addrhole int
+ */
+#define LP_SYSTEM_REG_LP_ADDRHOLE_INT_CLR    (BIT(0))
+#define LP_SYSTEM_REG_LP_ADDRHOLE_INT_CLR_M  (LP_SYSTEM_REG_LP_ADDRHOLE_INT_CLR_V << LP_SYSTEM_REG_LP_ADDRHOLE_INT_CLR_S)
+#define LP_SYSTEM_REG_LP_ADDRHOLE_INT_CLR_V  0x00000001U
+#define LP_SYSTEM_REG_LP_ADDRHOLE_INT_CLR_S  0
+/** LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  write 1 to clear idbus addrhole int
+ */
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_CLR    (BIT(1))
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_CLR_M  (LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_CLR_V << LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_CLR_S)
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_CLR_V  0x00000001U
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INT_CLR_S  1
+/** LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Write 1 to clear lp_core_ahb_timeout int
+ */
+#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_CLR    (BIT(2))
+#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_CLR_M  (LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_CLR_V << LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_CLR_S)
+#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_CLR_V  0x00000001U
+#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_INT_CLR_S  2
+/** LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Write 1 to clear lp_core_ibus_timeout int
+ */
+#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_CLR    (BIT(3))
+#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_CLR_M  (LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_CLR_V << LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_CLR_S)
+#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_CLR_V  0x00000001U
+#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_INT_CLR_S  3
+/** LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Write 1 to clear lp_core_dbus_timeout int
+ */
+#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_CLR    (BIT(4))
+#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_CLR_M  (LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_CLR_V << LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_CLR_S)
+#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_CLR_V  0x00000001U
+#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_INT_CLR_S  4
+/** LP_SYSTEM_REG_ETM_TASK_ULP_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Write 1 to clear etm tasl ulp int
+ */
+#define LP_SYSTEM_REG_ETM_TASK_ULP_INT_CLR    (BIT(5))
+#define LP_SYSTEM_REG_ETM_TASK_ULP_INT_CLR_M  (LP_SYSTEM_REG_ETM_TASK_ULP_INT_CLR_V << LP_SYSTEM_REG_ETM_TASK_ULP_INT_CLR_S)
+#define LP_SYSTEM_REG_ETM_TASK_ULP_INT_CLR_V  0x00000001U
+#define LP_SYSTEM_REG_ETM_TASK_ULP_INT_CLR_S  5
+/** LP_SYSTEM_REG_SLOW_CLK_TICK_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Write 1 to clear slow_clk_tick int
+ */
+#define LP_SYSTEM_REG_SLOW_CLK_TICK_INT_CLR    (BIT(6))
+#define LP_SYSTEM_REG_SLOW_CLK_TICK_INT_CLR_M  (LP_SYSTEM_REG_SLOW_CLK_TICK_INT_CLR_V << LP_SYSTEM_REG_SLOW_CLK_TICK_INT_CLR_S)
+#define LP_SYSTEM_REG_SLOW_CLK_TICK_INT_CLR_V  0x00000001U
+#define LP_SYSTEM_REG_SLOW_CLK_TICK_INT_CLR_S  6
+
+/** LP_SYSTEM_REG_HP_MEM_AUX_CTRL_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_HP_MEM_AUX_CTRL_REG (DR_REG_LP_SYS_BASE + 0x180)
+/** LP_SYSTEM_REG_HP_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 8304;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_HP_MEM_AUX_CTRL    0xFFFFFFFFU
+#define LP_SYSTEM_REG_HP_MEM_AUX_CTRL_M  (LP_SYSTEM_REG_HP_MEM_AUX_CTRL_V << LP_SYSTEM_REG_HP_MEM_AUX_CTRL_S)
+#define LP_SYSTEM_REG_HP_MEM_AUX_CTRL_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_HP_MEM_AUX_CTRL_S  0
+
+/** LP_SYSTEM_REG_LP_MEM_AUX_CTRL_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_MEM_AUX_CTRL_REG (DR_REG_LP_SYS_BASE + 0x184)
+/** LP_SYSTEM_REG_LP_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 8304;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_MEM_AUX_CTRL    0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_MEM_AUX_CTRL_M  (LP_SYSTEM_REG_LP_MEM_AUX_CTRL_V << LP_SYSTEM_REG_LP_MEM_AUX_CTRL_S)
+#define LP_SYSTEM_REG_LP_MEM_AUX_CTRL_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_MEM_AUX_CTRL_S  0
+
+/** LP_SYSTEM_REG_HP_ROM_AUX_CTRL_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_HP_ROM_AUX_CTRL_REG (DR_REG_LP_SYS_BASE + 0x188)
+/** LP_SYSTEM_REG_HP_ROM_AUX_CTRL : R/W; bitpos: [31:0]; default: 112;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_HP_ROM_AUX_CTRL    0xFFFFFFFFU
+#define LP_SYSTEM_REG_HP_ROM_AUX_CTRL_M  (LP_SYSTEM_REG_HP_ROM_AUX_CTRL_V << LP_SYSTEM_REG_HP_ROM_AUX_CTRL_S)
+#define LP_SYSTEM_REG_HP_ROM_AUX_CTRL_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_HP_ROM_AUX_CTRL_S  0
+
+/** LP_SYSTEM_REG_LP_ROM_AUX_CTRL_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_ROM_AUX_CTRL_REG (DR_REG_LP_SYS_BASE + 0x18c)
+/** LP_SYSTEM_REG_LP_ROM_AUX_CTRL : R/W; bitpos: [31:0]; default: 112;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_ROM_AUX_CTRL    0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_ROM_AUX_CTRL_M  (LP_SYSTEM_REG_LP_ROM_AUX_CTRL_V << LP_SYSTEM_REG_LP_ROM_AUX_CTRL_S)
+#define LP_SYSTEM_REG_LP_ROM_AUX_CTRL_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_ROM_AUX_CTRL_S  0
+
+/** LP_SYSTEM_REG_LP_CPU_DBG_PC_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_CPU_DBG_PC_REG (DR_REG_LP_SYS_BASE + 0x190)
+/** LP_SYSTEM_REG_LP_CPU_DBG_PC : RO; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_CPU_DBG_PC    0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_CPU_DBG_PC_M  (LP_SYSTEM_REG_LP_CPU_DBG_PC_V << LP_SYSTEM_REG_LP_CPU_DBG_PC_S)
+#define LP_SYSTEM_REG_LP_CPU_DBG_PC_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_CPU_DBG_PC_S  0
+
+/** LP_SYSTEM_REG_LP_CPU_EXC_PC_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_CPU_EXC_PC_REG (DR_REG_LP_SYS_BASE + 0x194)
+/** LP_SYSTEM_REG_LP_CPU_EXC_PC : RO; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_CPU_EXC_PC    0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_CPU_EXC_PC_M  (LP_SYSTEM_REG_LP_CPU_EXC_PC_V << LP_SYSTEM_REG_LP_CPU_EXC_PC_S)
+#define LP_SYSTEM_REG_LP_CPU_EXC_PC_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_LP_CPU_EXC_PC_S  0
+
+/** LP_SYSTEM_REG_IDBUS_ADDRHOLE_ADDR_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_ADDR_REG (DR_REG_LP_SYS_BASE + 0x198)
+/** LP_SYSTEM_REG_IDBUS_ADDRHOLE_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_ADDR    0xFFFFFFFFU
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_ADDR_M  (LP_SYSTEM_REG_IDBUS_ADDRHOLE_ADDR_V << LP_SYSTEM_REG_IDBUS_ADDRHOLE_ADDR_S)
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_ADDR_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_ADDR_S  0
+
+/** LP_SYSTEM_REG_IDBUS_ADDRHOLE_INFO_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_INFO_REG (DR_REG_LP_SYS_BASE + 0x19c)
+/** LP_SYSTEM_REG_IDBUS_ADDRHOLE_ID : RO; bitpos: [4:0]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_ID    0x0000001FU
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_ID_M  (LP_SYSTEM_REG_IDBUS_ADDRHOLE_ID_V << LP_SYSTEM_REG_IDBUS_ADDRHOLE_ID_S)
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_ID_V  0x0000001FU
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_ID_S  0
+/** LP_SYSTEM_REG_IDBUS_ADDRHOLE_WR : RO; bitpos: [5]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_WR    (BIT(5))
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_WR_M  (LP_SYSTEM_REG_IDBUS_ADDRHOLE_WR_V << LP_SYSTEM_REG_IDBUS_ADDRHOLE_WR_S)
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_WR_V  0x00000001U
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_WR_S  5
+/** LP_SYSTEM_REG_IDBUS_ADDRHOLE_SECURE : RO; bitpos: [6]; default: 0;
+ *  need_des
+ */
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_SECURE    (BIT(6))
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_SECURE_M  (LP_SYSTEM_REG_IDBUS_ADDRHOLE_SECURE_V << LP_SYSTEM_REG_IDBUS_ADDRHOLE_SECURE_S)
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_SECURE_V  0x00000001U
+#define LP_SYSTEM_REG_IDBUS_ADDRHOLE_SECURE_S  6
+
+/** LP_SYSTEM_REG_HP_POR_RST_BYPASS_CTRL_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_HP_POR_RST_BYPASS_CTRL_REG (DR_REG_LP_SYS_BASE + 0x1a0)
+/** LP_SYSTEM_REG_HP_PO_CNNT_RSTN_BYPASS_CTRL : R/W; bitpos: [15:8]; default: 255;
+ *  [15] 1'b1: po_cnnt_rstn bypass sys_sw_rstn
+ *  [14] 1'b1: po_cnnt_rstn bypass hp_wdt_sys_rstn
+ *  [13] 1'b1: po_cnnt_rstn bypass hp_cpu_intrusion_rstn
+ *  [12] 1'b1: po_cnnt_rstn bypass hp_sdio_sys_rstn
+ *  [11] 1'b1: po_cnnt_rstn bypass usb_jtag_chip_rst
+ *  [10] 1'b1: po_cnnt_rstn bypass usb_uart_chip_rst
+ *  [9] 1'b1: po_cnnt_rstn bypass lp_wdt_hp_sys_rstn
+ *  [8] 1'b1: po_cnnt_rstn bypass efuse_err_rstn
+ */
+#define LP_SYSTEM_REG_HP_PO_CNNT_RSTN_BYPASS_CTRL    0x000000FFU
+#define LP_SYSTEM_REG_HP_PO_CNNT_RSTN_BYPASS_CTRL_M  (LP_SYSTEM_REG_HP_PO_CNNT_RSTN_BYPASS_CTRL_V << LP_SYSTEM_REG_HP_PO_CNNT_RSTN_BYPASS_CTRL_S)
+#define LP_SYSTEM_REG_HP_PO_CNNT_RSTN_BYPASS_CTRL_V  0x000000FFU
+#define LP_SYSTEM_REG_HP_PO_CNNT_RSTN_BYPASS_CTRL_S  8
+/** LP_SYSTEM_REG_HP_PO_RSTN_BYPASS_CTRL : R/W; bitpos: [31:24]; default: 255;
+ *  [31] 1'b1: po_rstn bypass sys_sw_rstn
+ *  [30] 1'b1: po_rstn bypass hp_wdt_sys_rstn
+ *  [29] 1'b1: po_rstn bypass hp_cpu_intrusion_rstn
+ *  [28] 1'b1: po_rstn bypass hp_sdio_sys_rstn
+ *  [27] 1'b1: po_rstn bypass usb_jtag_chip_rst
+ *  [26] 1'b1: po_rstn bypass usb_uart_chip_rst
+ *  [25] 1'b1: po_rstn bypass lp_wdt_hp_sys_rstn
+ *  [24] 1'b1: po_rstn bypass efuse_err_rstn
+ */
+#define LP_SYSTEM_REG_HP_PO_RSTN_BYPASS_CTRL    0x000000FFU
+#define LP_SYSTEM_REG_HP_PO_RSTN_BYPASS_CTRL_M  (LP_SYSTEM_REG_HP_PO_RSTN_BYPASS_CTRL_V << LP_SYSTEM_REG_HP_PO_RSTN_BYPASS_CTRL_S)
+#define LP_SYSTEM_REG_HP_PO_RSTN_BYPASS_CTRL_V  0x000000FFU
+#define LP_SYSTEM_REG_HP_PO_RSTN_BYPASS_CTRL_S  24
+
+/** LP_SYSTEM_REG_RNG_DATA_REG register
+ *  rng data register
+ */
+#define LP_SYSTEM_REG_RNG_DATA_REG (DR_REG_LP_SYS_BASE + 0x1a4)
+/** LP_SYSTEM_REG_RND_DATA : RO; bitpos: [31:0]; default: 0;
+ *  result of rng output
+ */
+#define LP_SYSTEM_REG_RND_DATA    0xFFFFFFFFU
+#define LP_SYSTEM_REG_RND_DATA_M  (LP_SYSTEM_REG_RND_DATA_V << LP_SYSTEM_REG_RND_DATA_S)
+#define LP_SYSTEM_REG_RND_DATA_V  0xFFFFFFFFU
+#define LP_SYSTEM_REG_RND_DATA_S  0
+
+/** LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_REG (DR_REG_LP_SYS_BASE + 0x1b0)
+/** LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_EN : R/W; bitpos: [0]; default: 1;
+ *  set this field to 1 to enable lp core ahb timeout handle
+ */
+#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_EN    (BIT(0))
+#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_EN_M  (LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_EN_V << LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_EN_S)
+#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_EN_V  0x00000001U
+#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_EN_S  0
+/** LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_THRES : R/W; bitpos: [16:1]; default: 65535;
+ *  This field used to set lp core ahb bus timeout  threshold
+ */
+#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_THRES    0x0000FFFFU
+#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_THRES_M  (LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_THRES_V << LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_THRES_S)
+#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_THRES_V  0x0000FFFFU
+#define LP_SYSTEM_REG_LP_CORE_AHB_TIMEOUT_THRES_S  1
+/** LP_SYSTEM_REG_LP2HP_AHB_TIMEOUT_EN : R/W; bitpos: [17]; default: 1;
+ *  set this field to 1 to enable lp2hp ahb timeout handle
+ */
+#define LP_SYSTEM_REG_LP2HP_AHB_TIMEOUT_EN    (BIT(17))
+#define LP_SYSTEM_REG_LP2HP_AHB_TIMEOUT_EN_M  (LP_SYSTEM_REG_LP2HP_AHB_TIMEOUT_EN_V << LP_SYSTEM_REG_LP2HP_AHB_TIMEOUT_EN_S)
+#define LP_SYSTEM_REG_LP2HP_AHB_TIMEOUT_EN_V  0x00000001U
+#define LP_SYSTEM_REG_LP2HP_AHB_TIMEOUT_EN_S  17
+/** LP_SYSTEM_REG_LP2HP_AHB_TIMEOUT_THRES : R/W; bitpos: [22:18]; default: 31;
+ *  This field used to set lp2hp ahb bus timeout  threshold
+ */
+#define LP_SYSTEM_REG_LP2HP_AHB_TIMEOUT_THRES    0x0000001FU
+#define LP_SYSTEM_REG_LP2HP_AHB_TIMEOUT_THRES_M  (LP_SYSTEM_REG_LP2HP_AHB_TIMEOUT_THRES_V << LP_SYSTEM_REG_LP2HP_AHB_TIMEOUT_THRES_S)
+#define LP_SYSTEM_REG_LP2HP_AHB_TIMEOUT_THRES_V  0x0000001FU
+#define LP_SYSTEM_REG_LP2HP_AHB_TIMEOUT_THRES_S  18
+
+/** LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_REG (DR_REG_LP_SYS_BASE + 0x1b4)
+/** LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_EN : R/W; bitpos: [0]; default: 1;
+ *  set this field to 1 to enable lp core ibus timeout handle
+ */
+#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_EN    (BIT(0))
+#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_EN_M  (LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_EN_V << LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_EN_S)
+#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_EN_V  0x00000001U
+#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_EN_S  0
+/** LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_THRES : R/W; bitpos: [16:1]; default: 65535;
+ *  This field used to set lp core ibus timeout  threshold
+ */
+#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_THRES    0x0000FFFFU
+#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_THRES_M  (LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_THRES_V << LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_THRES_S)
+#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_THRES_V  0x0000FFFFU
+#define LP_SYSTEM_REG_LP_CORE_IBUS_TIMEOUT_THRES_S  1
+
+/** LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_REG (DR_REG_LP_SYS_BASE + 0x1b8)
+/** LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_EN : R/W; bitpos: [0]; default: 1;
+ *  set this field to 1 to enable lp core dbus timeout handle
+ */
+#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_EN    (BIT(0))
+#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_EN_M  (LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_EN_V << LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_EN_S)
+#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_EN_V  0x00000001U
+#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_EN_S  0
+/** LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_THRES : R/W; bitpos: [16:1]; default: 65535;
+ *  This field used to set lp core dbus timeout  threshold
+ */
+#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_THRES    0x0000FFFFU
+#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_THRES_M  (LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_THRES_V << LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_THRES_S)
+#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_THRES_V  0x0000FFFFU
+#define LP_SYSTEM_REG_LP_CORE_DBUS_TIMEOUT_THRES_S  1
+
+/** LP_SYSTEM_REG_LP_CORE_ERR_RESP_DIS_REG register
+ *  need_des
+ */
+#define LP_SYSTEM_REG_LP_CORE_ERR_RESP_DIS_REG (DR_REG_LP_SYS_BASE + 0x1bc)
+/** LP_SYSTEM_REG_LP_CORE_ERR_RESP_DIS : R/W; bitpos: [2:0]; default: 0;
+ *  Set bit0 to disable ibus err resp;Set bit1 to disable dbus err resp; Set bit 2 to
+ *  disable ahb err resp.
+ */
+#define LP_SYSTEM_REG_LP_CORE_ERR_RESP_DIS    0x00000007U
+#define LP_SYSTEM_REG_LP_CORE_ERR_RESP_DIS_M  (LP_SYSTEM_REG_LP_CORE_ERR_RESP_DIS_V << LP_SYSTEM_REG_LP_CORE_ERR_RESP_DIS_S)
+#define LP_SYSTEM_REG_LP_CORE_ERR_RESP_DIS_V  0x00000007U
+#define LP_SYSTEM_REG_LP_CORE_ERR_RESP_DIS_S  0
+
+/** LP_SYSTEM_REG_RNG_CFG_REG register
+ *  rng cfg register
+ */
+#define LP_SYSTEM_REG_RNG_CFG_REG (DR_REG_LP_SYS_BASE + 0x1c0)
+/** LP_SYSTEM_REG_RNG_TIMER_EN : R/W; bitpos: [0]; default: 1;
+ *  enable rng timer
+ */
+#define LP_SYSTEM_REG_RNG_TIMER_EN    (BIT(0))
+#define LP_SYSTEM_REG_RNG_TIMER_EN_M  (LP_SYSTEM_REG_RNG_TIMER_EN_V << LP_SYSTEM_REG_RNG_TIMER_EN_S)
+#define LP_SYSTEM_REG_RNG_TIMER_EN_V  0x00000001U
+#define LP_SYSTEM_REG_RNG_TIMER_EN_S  0
+/** LP_SYSTEM_REG_RNG_TIMER_PSCALE : R/W; bitpos: [8:1]; default: 1;
+ *  configure ng timer pscale
+ */
+#define LP_SYSTEM_REG_RNG_TIMER_PSCALE    0x000000FFU
+#define LP_SYSTEM_REG_RNG_TIMER_PSCALE_M  (LP_SYSTEM_REG_RNG_TIMER_PSCALE_V << LP_SYSTEM_REG_RNG_TIMER_PSCALE_S)
+#define LP_SYSTEM_REG_RNG_TIMER_PSCALE_V  0x000000FFU
+#define LP_SYSTEM_REG_RNG_TIMER_PSCALE_S  1
+/** LP_SYSTEM_REG_RNG_SAR_ENABLE : R/W; bitpos: [9]; default: 0;
+ *  enable rng_saradc
+ */
+#define LP_SYSTEM_REG_RNG_SAR_ENABLE    (BIT(9))
+#define LP_SYSTEM_REG_RNG_SAR_ENABLE_M  (LP_SYSTEM_REG_RNG_SAR_ENABLE_V << LP_SYSTEM_REG_RNG_SAR_ENABLE_S)
+#define LP_SYSTEM_REG_RNG_SAR_ENABLE_V  0x00000001U
+#define LP_SYSTEM_REG_RNG_SAR_ENABLE_S  9
+/** LP_SYSTEM_REG_RNG_SAR_DATA : RO; bitpos: [28:16]; default: 0;
+ *  debug rng sar sample cnt
+ */
+#define LP_SYSTEM_REG_RNG_SAR_DATA    0x00001FFFU
+#define LP_SYSTEM_REG_RNG_SAR_DATA_M  (LP_SYSTEM_REG_RNG_SAR_DATA_V << LP_SYSTEM_REG_RNG_SAR_DATA_S)
+#define LP_SYSTEM_REG_RNG_SAR_DATA_V  0x00001FFFU
+#define LP_SYSTEM_REG_RNG_SAR_DATA_S  16
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32p4/include/soc/lp_sys_struct.h → components/soc/esp32p4/include/soc/lp_system_struct.h

@@ -22,7 +22,7 @@ typedef union {
         uint32_t ver_date:32;
     };
     uint32_t val;
-} lpsysreg_lp_sys_ver_date_reg_t;
+} lp_system_reg_lp_sys_ver_date_reg_t;
 
 /** Type of clk_sel_ctrl register
  *  need_des
@@ -41,7 +41,7 @@ typedef union {
         uint32_t reserved_18:14;
     };
     uint32_t val;
-} lpsysreg_clk_sel_ctrl_reg_t;
+} lp_system_reg_clk_sel_ctrl_reg_t;
 
 /** Type of sys_ctrl register
  *  need_des
@@ -92,7 +92,7 @@ typedef union {
         uint32_t systimer_stall_sel:1;
     };
     uint32_t val;
-} lpsysreg_sys_ctrl_reg_t;
+} lp_system_reg_sys_ctrl_reg_t;
 
 /** Type of lp_clk_ctrl register
  *  need_des
@@ -111,7 +111,7 @@ typedef union {
         uint32_t reserved_15:17;
     };
     uint32_t val;
-} lpsysreg_lp_clk_ctrl_reg_t;
+} lp_system_reg_lp_clk_ctrl_reg_t;
 
 /** Type of lp_rst_ctrl register
  *  need_des
@@ -133,7 +133,7 @@ typedef union {
         uint32_t reserved_3:29;
     };
     uint32_t val;
-} lpsysreg_lp_rst_ctrl_reg_t;
+} lp_system_reg_lp_rst_ctrl_reg_t;
 
 /** Type of lp_core_boot_addr register
  *  need_des
@@ -146,7 +146,7 @@ typedef union {
         uint32_t lp_cpu_boot_addr:32;
     };
     uint32_t val;
-} lpsysreg_lp_core_boot_addr_reg_t;
+} lp_system_reg_lp_core_boot_addr_reg_t;
 
 /** Type of ext_wakeup1 register
  *  need_des
@@ -164,7 +164,7 @@ typedef union {
         uint32_t reserved_17:15;
     };
     uint32_t val;
-} lpsysreg_ext_wakeup1_reg_t;
+} lp_system_reg_ext_wakeup1_reg_t;
 
 /** Type of ext_wakeup1_status register
  *  need_des
@@ -178,7 +178,7 @@ typedef union {
         uint32_t reserved_16:16;
     };
     uint32_t val;
-} lpsysreg_ext_wakeup1_status_reg_t;
+} lp_system_reg_ext_wakeup1_status_reg_t;
 
 /** Type of lp_tcm_pwr_ctrl register
  *  need_des
@@ -198,7 +198,7 @@ typedef union {
         uint32_t reserved_8:24;
     };
     uint32_t val;
-} lpsysreg_lp_tcm_pwr_ctrl_reg_t;
+} lp_system_reg_lp_tcm_pwr_ctrl_reg_t;
 
 /** Type of boot_addr_hp_lp_reg register
  *  need_des
@@ -211,7 +211,7 @@ typedef union {
         uint32_t boot_addr_hp_lp:32;
     };
     uint32_t val;
-} lpsysreg_boot_addr_hp_lp_reg_reg_t;
+} lp_system_reg_boot_addr_hp_lp_reg_reg_t;
 
 /** Type of lp_store0 register
  *  need_des
@@ -224,7 +224,7 @@ typedef union {
         uint32_t lp_scratch0:32;
     };
     uint32_t val;
-} lpsysreg_lp_store0_reg_t;
+} lp_system_reg_lp_store0_reg_t;
 
 /** Type of lp_store1 register
  *  need_des
@@ -237,7 +237,7 @@ typedef union {
         uint32_t lp_scratch1:32;
     };
     uint32_t val;
-} lpsysreg_lp_store1_reg_t;
+} lp_system_reg_lp_store1_reg_t;
 
 /** Type of lp_store2 register
  *  need_des
@@ -250,7 +250,7 @@ typedef union {
         uint32_t lp_scratch2:32;
     };
     uint32_t val;
-} lpsysreg_lp_store2_reg_t;
+} lp_system_reg_lp_store2_reg_t;
 
 /** Type of lp_store3 register
  *  need_des
@@ -263,7 +263,7 @@ typedef union {
         uint32_t lp_scratch3:32;
     };
     uint32_t val;
-} lpsysreg_lp_store3_reg_t;
+} lp_system_reg_lp_store3_reg_t;
 
 /** Type of lp_store4 register
  *  need_des
@@ -276,7 +276,7 @@ typedef union {
         uint32_t lp_scratch4:32;
     };
     uint32_t val;
-} lpsysreg_lp_store4_reg_t;
+} lp_system_reg_lp_store4_reg_t;
 
 /** Type of lp_store5 register
  *  need_des
@@ -289,7 +289,7 @@ typedef union {
         uint32_t lp_scratch5:32;
     };
     uint32_t val;
-} lpsysreg_lp_store5_reg_t;
+} lp_system_reg_lp_store5_reg_t;
 
 /** Type of lp_store6 register
  *  need_des
@@ -302,7 +302,7 @@ typedef union {
         uint32_t lp_scratch6:32;
     };
     uint32_t val;
-} lpsysreg_lp_store6_reg_t;
+} lp_system_reg_lp_store6_reg_t;
 
 /** Type of lp_store7 register
  *  need_des
@@ -315,7 +315,7 @@ typedef union {
         uint32_t lp_scratch7:32;
     };
     uint32_t val;
-} lpsysreg_lp_store7_reg_t;
+} lp_system_reg_lp_store7_reg_t;
 
 /** Type of lp_store8 register
  *  need_des
@@ -328,7 +328,7 @@ typedef union {
         uint32_t lp_scratch8:32;
     };
     uint32_t val;
-} lpsysreg_lp_store8_reg_t;
+} lp_system_reg_lp_store8_reg_t;
 
 /** Type of lp_store9 register
  *  need_des
@@ -341,7 +341,7 @@ typedef union {
         uint32_t lp_scratch9:32;
     };
     uint32_t val;
-} lpsysreg_lp_store9_reg_t;
+} lp_system_reg_lp_store9_reg_t;
 
 /** Type of lp_store10 register
  *  need_des
@@ -354,7 +354,7 @@ typedef union {
         uint32_t lp_scratch10:32;
     };
     uint32_t val;
-} lpsysreg_lp_store10_reg_t;
+} lp_system_reg_lp_store10_reg_t;
 
 /** Type of lp_store11 register
  *  need_des
@@ -367,7 +367,7 @@ typedef union {
         uint32_t lp_scratch11:32;
     };
     uint32_t val;
-} lpsysreg_lp_store11_reg_t;
+} lp_system_reg_lp_store11_reg_t;
 
 /** Type of lp_store12 register
  *  need_des
@@ -380,7 +380,7 @@ typedef union {
         uint32_t lp_scratch12:32;
     };
     uint32_t val;
-} lpsysreg_lp_store12_reg_t;
+} lp_system_reg_lp_store12_reg_t;
 
 /** Type of lp_store13 register
  *  need_des
@@ -393,7 +393,7 @@ typedef union {
         uint32_t lp_scratch13:32;
     };
     uint32_t val;
-} lpsysreg_lp_store13_reg_t;
+} lp_system_reg_lp_store13_reg_t;
 
 /** Type of lp_store14 register
  *  need_des
@@ -406,7 +406,7 @@ typedef union {
         uint32_t lp_scratch14:32;
     };
     uint32_t val;
-} lpsysreg_lp_store14_reg_t;
+} lp_system_reg_lp_store14_reg_t;
 
 /** Type of lp_store15 register
  *  need_des
@@ -419,7 +419,7 @@ typedef union {
         uint32_t lp_scratch15:32;
     };
     uint32_t val;
-} lpsysreg_lp_store15_reg_t;
+} lp_system_reg_lp_store15_reg_t;
 
 /** Type of lp_probea_ctrl register
  *  need_des
@@ -449,7 +449,7 @@ typedef union {
         uint32_t reserved_29:3;
     };
     uint32_t val;
-} lpsysreg_lp_probea_ctrl_reg_t;
+} lp_system_reg_lp_probea_ctrl_reg_t;
 
 /** Type of lp_probeb_ctrl register
  *  need_des
@@ -471,7 +471,7 @@ typedef union {
         uint32_t reserved_25:7;
     };
     uint32_t val;
-} lpsysreg_lp_probeb_ctrl_reg_t;
+} lp_system_reg_lp_probeb_ctrl_reg_t;
 
 /** Type of lp_probe_out register
  *  need_des
@@ -484,7 +484,7 @@ typedef union {
         uint32_t probe_top_out:32;
     };
     uint32_t val;
-} lpsysreg_lp_probe_out_reg_t;
+} lp_system_reg_lp_probe_out_reg_t;
 
 /** Type of f2s_apb_brg_cntl register
  *  need_des
@@ -498,7 +498,7 @@ typedef union {
         uint32_t reserved_1:31;
     };
     uint32_t val;
-} lpsysreg_f2s_apb_brg_cntl_reg_t;
+} lp_system_reg_f2s_apb_brg_cntl_reg_t;
 
 /** Type of usb_ctrl register
  *  need_des
@@ -524,7 +524,7 @@ typedef union {
         uint32_t reserved_4:28;
     };
     uint32_t val;
-} lpsysreg_usb_ctrl_reg_t;
+} lp_system_reg_usb_ctrl_reg_t;
 
 /** Type of ana_xpd_pad_group register
  *  need_des
@@ -538,7 +538,7 @@ typedef union {
         uint32_t reserved_8:24;
     };
     uint32_t val;
-} lpsysreg_ana_xpd_pad_group_reg_t;
+} lp_system_reg_ana_xpd_pad_group_reg_t;
 
 /** Type of lp_tcm_ram_rdn_eco_cs register
  *  need_des
@@ -556,7 +556,7 @@ typedef union {
         uint32_t reserved_2:30;
     };
     uint32_t val;
-} lpsysreg_lp_tcm_ram_rdn_eco_cs_reg_t;
+} lp_system_reg_lp_tcm_ram_rdn_eco_cs_reg_t;
 
 /** Type of lp_tcm_ram_rdn_eco_low register
  *  need_des
@@ -569,7 +569,7 @@ typedef union {
         uint32_t lp_tcm_ram_rdn_eco_low:32;
     };
     uint32_t val;
-} lpsysreg_lp_tcm_ram_rdn_eco_low_reg_t;
+} lp_system_reg_lp_tcm_ram_rdn_eco_low_reg_t;
 
 /** Type of lp_tcm_ram_rdn_eco_high register
  *  need_des
@@ -582,7 +582,7 @@ typedef union {
         uint32_t lp_tcm_ram_rdn_eco_high:32;
     };
     uint32_t val;
-} lpsysreg_lp_tcm_ram_rdn_eco_high_reg_t;
+} lp_system_reg_lp_tcm_ram_rdn_eco_high_reg_t;
 
 /** Type of lp_tcm_rom_rdn_eco_cs register
  *  need_des
@@ -600,7 +600,7 @@ typedef union {
         uint32_t reserved_2:30;
     };
     uint32_t val;
-} lpsysreg_lp_tcm_rom_rdn_eco_cs_reg_t;
+} lp_system_reg_lp_tcm_rom_rdn_eco_cs_reg_t;
 
 /** Type of lp_tcm_rom_rdn_eco_low register
  *  need_des
@@ -613,7 +613,7 @@ typedef union {
         uint32_t lp_tcm_rom_rdn_eco_low:32;
     };
     uint32_t val;
-} lpsysreg_lp_tcm_rom_rdn_eco_low_reg_t;
+} lp_system_reg_lp_tcm_rom_rdn_eco_low_reg_t;
 
 /** Type of lp_tcm_rom_rdn_eco_high register
  *  need_des
@@ -626,7 +626,7 @@ typedef union {
         uint32_t lp_tcm_rom_rdn_eco_high:32;
     };
     uint32_t val;
-} lpsysreg_lp_tcm_rom_rdn_eco_high_reg_t;
+} lp_system_reg_lp_tcm_rom_rdn_eco_high_reg_t;
 
 /** Type of hp_root_clk_ctrl register
  *  need_des
@@ -644,7 +644,7 @@ typedef union {
         uint32_t reserved_2:30;
     };
     uint32_t val;
-} lpsysreg_hp_root_clk_ctrl_reg_t;
+} lp_system_reg_hp_root_clk_ctrl_reg_t;
 
 /** Type of lp_pmu_rdn_eco_low register
  *  need_des
@@ -657,7 +657,7 @@ typedef union {
         uint32_t pmu_rdn_eco_low:32;
     };
     uint32_t val;
-} lpsysreg_lp_pmu_rdn_eco_low_reg_t;
+} lp_system_reg_lp_pmu_rdn_eco_low_reg_t;
 
 /** Type of lp_pmu_rdn_eco_high register
  *  need_des
@@ -670,7 +670,7 @@ typedef union {
         uint32_t pmu_rdn_eco_high:32;
     };
     uint32_t val;
-} lpsysreg_lp_pmu_rdn_eco_high_reg_t;
+} lp_system_reg_lp_pmu_rdn_eco_high_reg_t;
 
 /** Type of pad_comp0 register
  *  need_des
@@ -692,7 +692,7 @@ typedef union {
         uint32_t reserved_5:27;
     };
     uint32_t val;
-} lpsysreg_pad_comp0_reg_t;
+} lp_system_reg_pad_comp0_reg_t;
 
 /** Type of pad_comp1 register
  *  need_des
@@ -714,7 +714,7 @@ typedef union {
         uint32_t reserved_5:27;
     };
     uint32_t val;
-} lpsysreg_pad_comp1_reg_t;
+} lp_system_reg_pad_comp1_reg_t;
 
 /** Type of backup_dma_cfg0 register
  *  need_des
@@ -739,7 +739,7 @@ typedef union {
         uint32_t link_tout_thres_aon:10;
     };
     uint32_t val;
-} lpsysreg_backup_dma_cfg0_reg_t;
+} lp_system_reg_backup_dma_cfg0_reg_t;
 
 /** Type of backup_dma_cfg1 register
  *  need_des
@@ -753,7 +753,7 @@ typedef union {
         uint32_t aon_bypass:1;
     };
     uint32_t val;
-} lpsysreg_backup_dma_cfg1_reg_t;
+} lp_system_reg_backup_dma_cfg1_reg_t;
 
 /** Type of backup_dma_cfg2 register
  *  need_des
@@ -766,7 +766,7 @@ typedef union {
         uint32_t link_addr_aon:32;
     };
     uint32_t val;
-} lpsysreg_backup_dma_cfg2_reg_t;
+} lp_system_reg_backup_dma_cfg2_reg_t;
 
 /** Type of boot_addr_hp_core1 register
  *  need_des
@@ -779,7 +779,7 @@ typedef union {
         uint32_t boot_addr_hp_core1:32;
     };
     uint32_t val;
-} lpsysreg_boot_addr_hp_core1_reg_t;
+} lp_system_reg_boot_addr_hp_core1_reg_t;
 
 /** Type of hp_mem_aux_ctrl register
  *  need_des
@@ -792,7 +792,7 @@ typedef union {
         uint32_t hp_mem_aux_ctrl:32;
     };
     uint32_t val;
-} lpsysreg_hp_mem_aux_ctrl_reg_t;
+} lp_system_reg_hp_mem_aux_ctrl_reg_t;
 
 /** Type of lp_mem_aux_ctrl register
  *  need_des
@@ -805,7 +805,7 @@ typedef union {
         uint32_t lp_mem_aux_ctrl:32;
     };
     uint32_t val;
-} lpsysreg_lp_mem_aux_ctrl_reg_t;
+} lp_system_reg_lp_mem_aux_ctrl_reg_t;
 
 /** Type of hp_rom_aux_ctrl register
  *  need_des
@@ -818,7 +818,7 @@ typedef union {
         uint32_t hp_rom_aux_ctrl:32;
     };
     uint32_t val;
-} lpsysreg_hp_rom_aux_ctrl_reg_t;
+} lp_system_reg_hp_rom_aux_ctrl_reg_t;
 
 /** Type of lp_rom_aux_ctrl register
  *  need_des
@@ -831,7 +831,7 @@ typedef union {
         uint32_t lp_rom_aux_ctrl:32;
     };
     uint32_t val;
-} lpsysreg_lp_rom_aux_ctrl_reg_t;
+} lp_system_reg_lp_rom_aux_ctrl_reg_t;
 
 /** Type of hp_por_rst_bypass_ctrl register
  *  need_des
@@ -864,7 +864,7 @@ typedef union {
         uint32_t hp_po_rstn_bypass_ctrl:8;
     };
     uint32_t val;
-} lpsysreg_hp_por_rst_bypass_ctrl_reg_t;
+} lp_system_reg_hp_por_rst_bypass_ctrl_reg_t;
 
 /** Type of lp_core_ahb_timeout register
  *  need_des
@@ -890,7 +890,7 @@ typedef union {
         uint32_t reserved_23:9;
     };
     uint32_t val;
-} lpsysreg_lp_core_ahb_timeout_reg_t;
+} lp_system_reg_lp_core_ahb_timeout_reg_t;
 
 /** Type of lp_core_ibus_timeout register
  *  need_des
@@ -908,7 +908,7 @@ typedef union {
         uint32_t reserved_17:15;
     };
     uint32_t val;
-} lpsysreg_lp_core_ibus_timeout_reg_t;
+} lp_system_reg_lp_core_ibus_timeout_reg_t;
 
 /** Type of lp_core_dbus_timeout register
  *  need_des
@@ -926,7 +926,7 @@ typedef union {
         uint32_t reserved_17:15;
     };
     uint32_t val;
-} lpsysreg_lp_core_dbus_timeout_reg_t;
+} lp_system_reg_lp_core_dbus_timeout_reg_t;
 
 
 /** Group: status_register */
@@ -941,7 +941,7 @@ typedef union {
         uint32_t lp_addrhole_addr:32;
     };
     uint32_t val;
-} lpsysreg_lp_addrhole_addr_reg_t;
+} lp_system_reg_lp_addrhole_addr_reg_t;
 
 /** Type of lp_addrhole_info register
  *  need_des
@@ -965,7 +965,7 @@ typedef union {
         uint32_t reserved_7:25;
     };
     uint32_t val;
-} lpsysreg_lp_addrhole_info_reg_t;
+} lp_system_reg_lp_addrhole_info_reg_t;
 
 /** Type of lp_cpu_dbg_pc register
  *  need_des
@@ -978,7 +978,7 @@ typedef union {
         uint32_t lp_cpu_dbg_pc:32;
     };
     uint32_t val;
-} lpsysreg_lp_cpu_dbg_pc_reg_t;
+} lp_system_reg_lp_cpu_dbg_pc_reg_t;
 
 /** Type of lp_cpu_exc_pc register
  *  need_des
@@ -991,7 +991,7 @@ typedef union {
         uint32_t lp_cpu_exc_pc:32;
     };
     uint32_t val;
-} lpsysreg_lp_cpu_exc_pc_reg_t;
+} lp_system_reg_lp_cpu_exc_pc_reg_t;
 
 /** Type of idbus_addrhole_addr register
  *  need_des
@@ -1004,7 +1004,7 @@ typedef union {
         uint32_t idbus_addrhole_addr:32;
     };
     uint32_t val;
-} lpsysreg_idbus_addrhole_addr_reg_t;
+} lp_system_reg_idbus_addrhole_addr_reg_t;
 
 /** Type of idbus_addrhole_info register
  *  need_des
@@ -1026,7 +1026,7 @@ typedef union {
         uint32_t reserved_7:25;
     };
     uint32_t val;
-} lpsysreg_idbus_addrhole_info_reg_t;
+} lp_system_reg_idbus_addrhole_info_reg_t;
 
 /** Type of rng_data register
  *  rng data register
@@ -1039,7 +1039,7 @@ typedef union {
         uint32_t rnd_data:32;
     };
     uint32_t val;
-} lpsysreg_rng_data_reg_t;
+} lp_system_reg_rng_data_reg_t;
 
 
 /** Group: Interrupt Registers */
@@ -1080,7 +1080,7 @@ typedef union {
         uint32_t reserved_7:25;
     };
     uint32_t val;
-} lpsysreg_int_raw_reg_t;
+} lp_system_reg_int_raw_reg_t;
 
 /** Type of int_st register
  *  masked interrupt register
@@ -1119,7 +1119,7 @@ typedef union {
         uint32_t reserved_7:25;
     };
     uint32_t val;
-} lpsysreg_int_st_reg_t;
+} lp_system_reg_int_st_reg_t;
 
 /** Type of int_ena register
  *  masked interrupt register
@@ -1157,7 +1157,7 @@ typedef union {
         uint32_t reserved_7:25;
     };
     uint32_t val;
-} lpsysreg_int_ena_reg_t;
+} lp_system_reg_int_ena_reg_t;
 
 /** Type of int_clr register
  *  interrupt clear register
@@ -1195,7 +1195,7 @@ typedef union {
         uint32_t reserved_7:25;
     };
     uint32_t val;
-} lpsysreg_int_clr_reg_t;
+} lp_system_reg_int_clr_reg_t;
 
 
 /** Group: control registers */
@@ -1212,7 +1212,7 @@ typedef union {
         uint32_t reserved_3:29;
     };
     uint32_t val;
-} lpsysreg_lp_core_err_resp_dis_reg_t;
+} lp_system_reg_lp_core_err_resp_dis_reg_t;
 
 /** Type of rng_cfg register
  *  rng cfg register
@@ -1239,93 +1239,93 @@ typedef union {
         uint32_t reserved_29:3;
     };
     uint32_t val;
-} lpsysreg_rng_cfg_reg_t;
+} lp_system_reg_rng_cfg_reg_t;
 
 
 typedef struct {
-    volatile lpsysreg_lp_sys_ver_date_reg_t lp_sys_ver_date;
-    volatile lpsysreg_clk_sel_ctrl_reg_t clk_sel_ctrl;
-    volatile lpsysreg_sys_ctrl_reg_t sys_ctrl;
-    volatile lpsysreg_lp_clk_ctrl_reg_t lp_clk_ctrl;
-    volatile lpsysreg_lp_rst_ctrl_reg_t lp_rst_ctrl;
+    volatile lp_system_reg_lp_sys_ver_date_reg_t lp_sys_ver_date;
+    volatile lp_system_reg_clk_sel_ctrl_reg_t clk_sel_ctrl;
+    volatile lp_system_reg_sys_ctrl_reg_t sys_ctrl;
+    volatile lp_system_reg_lp_clk_ctrl_reg_t lp_clk_ctrl;
+    volatile lp_system_reg_lp_rst_ctrl_reg_t lp_rst_ctrl;
     uint32_t reserved_014;
-    volatile lpsysreg_lp_core_boot_addr_reg_t lp_core_boot_addr;
-    volatile lpsysreg_ext_wakeup1_reg_t ext_wakeup1;
-    volatile lpsysreg_ext_wakeup1_status_reg_t ext_wakeup1_status;
-    volatile lpsysreg_lp_tcm_pwr_ctrl_reg_t lp_tcm_pwr_ctrl;
-    volatile lpsysreg_boot_addr_hp_lp_reg_reg_t boot_addr_hp_lp_reg;
-    volatile lpsysreg_lp_store0_reg_t lp_store0;
-    volatile lpsysreg_lp_store1_reg_t lp_store1;
-    volatile lpsysreg_lp_store2_reg_t lp_store2;
-    volatile lpsysreg_lp_store3_reg_t lp_store3;
-    volatile lpsysreg_lp_store4_reg_t lp_store4;
-    volatile lpsysreg_lp_store5_reg_t lp_store5;
-    volatile lpsysreg_lp_store6_reg_t lp_store6;
-    volatile lpsysreg_lp_store7_reg_t lp_store7;
-    volatile lpsysreg_lp_store8_reg_t lp_store8;
-    volatile lpsysreg_lp_store9_reg_t lp_store9;
-    volatile lpsysreg_lp_store10_reg_t lp_store10;
-    volatile lpsysreg_lp_store11_reg_t lp_store11;
-    volatile lpsysreg_lp_store12_reg_t lp_store12;
-    volatile lpsysreg_lp_store13_reg_t lp_store13;
-    volatile lpsysreg_lp_store14_reg_t lp_store14;
-    volatile lpsysreg_lp_store15_reg_t lp_store15;
-    volatile lpsysreg_lp_probea_ctrl_reg_t lp_probea_ctrl;
-    volatile lpsysreg_lp_probeb_ctrl_reg_t lp_probeb_ctrl;
-    volatile lpsysreg_lp_probe_out_reg_t lp_probe_out;
+    volatile lp_system_reg_lp_core_boot_addr_reg_t lp_core_boot_addr;
+    volatile lp_system_reg_ext_wakeup1_reg_t ext_wakeup1;
+    volatile lp_system_reg_ext_wakeup1_status_reg_t ext_wakeup1_status;
+    volatile lp_system_reg_lp_tcm_pwr_ctrl_reg_t lp_tcm_pwr_ctrl;
+    volatile lp_system_reg_boot_addr_hp_lp_reg_reg_t boot_addr_hp_lp_reg;
+    volatile lp_system_reg_lp_store0_reg_t lp_store0;
+    volatile lp_system_reg_lp_store1_reg_t lp_store1;
+    volatile lp_system_reg_lp_store2_reg_t lp_store2;
+    volatile lp_system_reg_lp_store3_reg_t lp_store3;
+    volatile lp_system_reg_lp_store4_reg_t lp_store4;
+    volatile lp_system_reg_lp_store5_reg_t lp_store5;
+    volatile lp_system_reg_lp_store6_reg_t lp_store6;
+    volatile lp_system_reg_lp_store7_reg_t lp_store7;
+    volatile lp_system_reg_lp_store8_reg_t lp_store8;
+    volatile lp_system_reg_lp_store9_reg_t lp_store9;
+    volatile lp_system_reg_lp_store10_reg_t lp_store10;
+    volatile lp_system_reg_lp_store11_reg_t lp_store11;
+    volatile lp_system_reg_lp_store12_reg_t lp_store12;
+    volatile lp_system_reg_lp_store13_reg_t lp_store13;
+    volatile lp_system_reg_lp_store14_reg_t lp_store14;
+    volatile lp_system_reg_lp_store15_reg_t lp_store15;
+    volatile lp_system_reg_lp_probea_ctrl_reg_t lp_probea_ctrl;
+    volatile lp_system_reg_lp_probeb_ctrl_reg_t lp_probeb_ctrl;
+    volatile lp_system_reg_lp_probe_out_reg_t lp_probe_out;
     uint32_t reserved_078[9];
-    volatile lpsysreg_f2s_apb_brg_cntl_reg_t f2s_apb_brg_cntl;
+    volatile lp_system_reg_f2s_apb_brg_cntl_reg_t f2s_apb_brg_cntl;
     uint32_t reserved_0a0[24];
-    volatile lpsysreg_usb_ctrl_reg_t usb_ctrl;
+    volatile lp_system_reg_usb_ctrl_reg_t usb_ctrl;
     uint32_t reserved_104[2];
-    volatile lpsysreg_ana_xpd_pad_group_reg_t ana_xpd_pad_group;
-    volatile lpsysreg_lp_tcm_ram_rdn_eco_cs_reg_t lp_tcm_ram_rdn_eco_cs;
-    volatile lpsysreg_lp_tcm_ram_rdn_eco_low_reg_t lp_tcm_ram_rdn_eco_low;
-    volatile lpsysreg_lp_tcm_ram_rdn_eco_high_reg_t lp_tcm_ram_rdn_eco_high;
-    volatile lpsysreg_lp_tcm_rom_rdn_eco_cs_reg_t lp_tcm_rom_rdn_eco_cs;
-    volatile lpsysreg_lp_tcm_rom_rdn_eco_low_reg_t lp_tcm_rom_rdn_eco_low;
-    volatile lpsysreg_lp_tcm_rom_rdn_eco_high_reg_t lp_tcm_rom_rdn_eco_high;
+    volatile lp_system_reg_ana_xpd_pad_group_reg_t ana_xpd_pad_group;
+    volatile lp_system_reg_lp_tcm_ram_rdn_eco_cs_reg_t lp_tcm_ram_rdn_eco_cs;
+    volatile lp_system_reg_lp_tcm_ram_rdn_eco_low_reg_t lp_tcm_ram_rdn_eco_low;
+    volatile lp_system_reg_lp_tcm_ram_rdn_eco_high_reg_t lp_tcm_ram_rdn_eco_high;
+    volatile lp_system_reg_lp_tcm_rom_rdn_eco_cs_reg_t lp_tcm_rom_rdn_eco_cs;
+    volatile lp_system_reg_lp_tcm_rom_rdn_eco_low_reg_t lp_tcm_rom_rdn_eco_low;
+    volatile lp_system_reg_lp_tcm_rom_rdn_eco_high_reg_t lp_tcm_rom_rdn_eco_high;
     uint32_t reserved_128[2];
-    volatile lpsysreg_hp_root_clk_ctrl_reg_t hp_root_clk_ctrl;
+    volatile lp_system_reg_hp_root_clk_ctrl_reg_t hp_root_clk_ctrl;
     uint32_t reserved_134;
-    volatile lpsysreg_lp_pmu_rdn_eco_low_reg_t lp_pmu_rdn_eco_low;
-    volatile lpsysreg_lp_pmu_rdn_eco_high_reg_t lp_pmu_rdn_eco_high;
+    volatile lp_system_reg_lp_pmu_rdn_eco_low_reg_t lp_pmu_rdn_eco_low;
+    volatile lp_system_reg_lp_pmu_rdn_eco_high_reg_t lp_pmu_rdn_eco_high;
     uint32_t reserved_140[2];
-    volatile lpsysreg_pad_comp0_reg_t pad_comp0;
-    volatile lpsysreg_pad_comp1_reg_t pad_comp1;
+    volatile lp_system_reg_pad_comp0_reg_t pad_comp0;
+    volatile lp_system_reg_pad_comp1_reg_t pad_comp1;
     uint32_t reserved_150;
-    volatile lpsysreg_backup_dma_cfg0_reg_t backup_dma_cfg0;
-    volatile lpsysreg_backup_dma_cfg1_reg_t backup_dma_cfg1;
-    volatile lpsysreg_backup_dma_cfg2_reg_t backup_dma_cfg2;
+    volatile lp_system_reg_backup_dma_cfg0_reg_t backup_dma_cfg0;
+    volatile lp_system_reg_backup_dma_cfg1_reg_t backup_dma_cfg1;
+    volatile lp_system_reg_backup_dma_cfg2_reg_t backup_dma_cfg2;
     uint32_t reserved_160;
-    volatile lpsysreg_boot_addr_hp_core1_reg_t boot_addr_hp_core1;
-    volatile lpsysreg_lp_addrhole_addr_reg_t lp_addrhole_addr;
-    volatile lpsysreg_lp_addrhole_info_reg_t lp_addrhole_info;
-    volatile lpsysreg_int_raw_reg_t int_raw;
-    volatile lpsysreg_int_st_reg_t int_st;
-    volatile lpsysreg_int_ena_reg_t int_ena;
-    volatile lpsysreg_int_clr_reg_t int_clr;
-    volatile lpsysreg_hp_mem_aux_ctrl_reg_t hp_mem_aux_ctrl;
-    volatile lpsysreg_lp_mem_aux_ctrl_reg_t lp_mem_aux_ctrl;
-    volatile lpsysreg_hp_rom_aux_ctrl_reg_t hp_rom_aux_ctrl;
-    volatile lpsysreg_lp_rom_aux_ctrl_reg_t lp_rom_aux_ctrl;
-    volatile lpsysreg_lp_cpu_dbg_pc_reg_t lp_cpu_dbg_pc;
-    volatile lpsysreg_lp_cpu_exc_pc_reg_t lp_cpu_exc_pc;
-    volatile lpsysreg_idbus_addrhole_addr_reg_t idbus_addrhole_addr;
-    volatile lpsysreg_idbus_addrhole_info_reg_t idbus_addrhole_info;
-    volatile lpsysreg_hp_por_rst_bypass_ctrl_reg_t hp_por_rst_bypass_ctrl;
-    volatile lpsysreg_rng_data_reg_t rng_data;
+    volatile lp_system_reg_boot_addr_hp_core1_reg_t boot_addr_hp_core1;
+    volatile lp_system_reg_lp_addrhole_addr_reg_t lp_addrhole_addr;
+    volatile lp_system_reg_lp_addrhole_info_reg_t lp_addrhole_info;
+    volatile lp_system_reg_int_raw_reg_t int_raw;
+    volatile lp_system_reg_int_st_reg_t int_st;
+    volatile lp_system_reg_int_ena_reg_t int_ena;
+    volatile lp_system_reg_int_clr_reg_t int_clr;
+    volatile lp_system_reg_hp_mem_aux_ctrl_reg_t hp_mem_aux_ctrl;
+    volatile lp_system_reg_lp_mem_aux_ctrl_reg_t lp_mem_aux_ctrl;
+    volatile lp_system_reg_hp_rom_aux_ctrl_reg_t hp_rom_aux_ctrl;
+    volatile lp_system_reg_lp_rom_aux_ctrl_reg_t lp_rom_aux_ctrl;
+    volatile lp_system_reg_lp_cpu_dbg_pc_reg_t lp_cpu_dbg_pc;
+    volatile lp_system_reg_lp_cpu_exc_pc_reg_t lp_cpu_exc_pc;
+    volatile lp_system_reg_idbus_addrhole_addr_reg_t idbus_addrhole_addr;
+    volatile lp_system_reg_idbus_addrhole_info_reg_t idbus_addrhole_info;
+    volatile lp_system_reg_hp_por_rst_bypass_ctrl_reg_t hp_por_rst_bypass_ctrl;
+    volatile lp_system_reg_rng_data_reg_t rng_data;
     uint32_t reserved_1a8[2];
-    volatile lpsysreg_lp_core_ahb_timeout_reg_t lp_core_ahb_timeout;
-    volatile lpsysreg_lp_core_ibus_timeout_reg_t lp_core_ibus_timeout;
-    volatile lpsysreg_lp_core_dbus_timeout_reg_t lp_core_dbus_timeout;
-    volatile lpsysreg_lp_core_err_resp_dis_reg_t lp_core_err_resp_dis;
-    volatile lpsysreg_rng_cfg_reg_t rng_cfg;
-} lpsysreg_dev_t;
+    volatile lp_system_reg_lp_core_ahb_timeout_reg_t lp_core_ahb_timeout;
+    volatile lp_system_reg_lp_core_ibus_timeout_reg_t lp_core_ibus_timeout;
+    volatile lp_system_reg_lp_core_dbus_timeout_reg_t lp_core_dbus_timeout;
+    volatile lp_system_reg_lp_core_err_resp_dis_reg_t lp_core_err_resp_dis;
+    volatile lp_system_reg_rng_cfg_reg_t rng_cfg;
+} lp_system_reg_dev_t;
 
 
 #ifndef __cplusplus
-_Static_assert(sizeof(lpsysreg_dev_t) == 0x1c4, "Invalid size of lpsysreg_dev_t structure");
+_Static_assert(sizeof(lp_system_reg_dev_t) == 0x1c4, "Invalid size of lp_system_reg_dev_t structure");
 #endif
 
 #ifdef __cplusplus

components/soc/esp32p4/include/soc/spi_reg.h

@@ -14,7 +14,7 @@ extern "C" {
 /** SPI_CMD_REG register
  *  Command control register
  */
-#define SPI_CMD_REG (DR_REG_SPI_BASE + 0x0)
+#define SPI_CMD_REG(i) (REG_SPI_BASE(i) + 0x0)
 /** SPI_CONF_BITLEN : R/W; bitpos: [17:0]; default: 0;
  *  Define the APB cycles of  SPI_CONF state. Can be configured in CONF state.
  */
@@ -44,7 +44,7 @@ extern "C" {
 /** SPI_ADDR_REG register
  *  Address value register
  */
-#define SPI_ADDR_REG (DR_REG_SPI_BASE + 0x4)
+#define SPI_ADDR_REG(i) (REG_SPI_BASE(i) + 0x4)
 /** SPI_USR_ADDR_VALUE : R/W; bitpos: [31:0]; default: 0;
  *  Address to slave. Can be configured in CONF state.
  */
@@ -56,7 +56,7 @@ extern "C" {
 /** SPI_CTRL_REG register
  *  SPI control register
  */
-#define SPI_CTRL_REG (DR_REG_SPI_BASE + 0x8)
+#define SPI_CTRL_REG(i) (REG_SPI_BASE(i) + 0x8)
 /** SPI_DUMMY_OUT : R/W; bitpos: [3]; default: 0;
  *  0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase,
  *  the FSPI bus signals are output. Can be configured in CONF state.
@@ -192,7 +192,7 @@ extern "C" {
 /** SPI_CLOCK_REG register
  *  SPI clock control register
  */
-#define SPI_CLOCK_REG (DR_REG_SPI_BASE + 0xc)
+#define SPI_CLOCK_REG(i) (REG_SPI_BASE(i) + 0xc)
 /** SPI_CLKCNT_L : R/W; bitpos: [5:0]; default: 3;
  *  In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be
  *  0. Can be configured in CONF state.
@@ -236,7 +236,7 @@ extern "C" {
 /** SPI_USER_REG register
  *  SPI USER control register
  */
-#define SPI_USER_REG (DR_REG_SPI_BASE + 0x10)
+#define SPI_USER_REG(i) (REG_SPI_BASE(i) + 0x10)
 /** SPI_DOUTDIN : R/W; bitpos: [0]; default: 0;
  *  Set the bit to enable full duplex communication. 1: enable 0: disable. Can be
  *  configured in CONF state.
@@ -410,7 +410,7 @@ extern "C" {
 /** SPI_USER1_REG register
  *  SPI USER control register 1
  */
-#define SPI_USER1_REG (DR_REG_SPI_BASE + 0x14)
+#define SPI_USER1_REG(i) (REG_SPI_BASE(i) + 0x14)
 /** SPI_USR_DUMMY_CYCLELEN : R/W; bitpos: [7:0]; default: 7;
  *  The length in spi_clk cycles of dummy phase. The register value shall be
  *  (cycle_num-1). Can be configured in CONF state.
@@ -456,7 +456,7 @@ extern "C" {
 /** SPI_USER2_REG register
  *  SPI USER control register 2
  */
-#define SPI_USER2_REG (DR_REG_SPI_BASE + 0x18)
+#define SPI_USER2_REG(i) (REG_SPI_BASE(i) + 0x18)
 /** SPI_USR_COMMAND_VALUE : R/W; bitpos: [15:0]; default: 0;
  *  The value of  command. Can be configured in CONF state.
  */
@@ -485,7 +485,7 @@ extern "C" {
 /** SPI_MS_DLEN_REG register
  *  SPI data bit length control register
  */
-#define SPI_MS_DLEN_REG (DR_REG_SPI_BASE + 0x1c)
+#define SPI_MS_DLEN_REG(i) (REG_SPI_BASE(i) + 0x1c)
 /** SPI_MS_DATA_BITLEN : R/W; bitpos: [17:0]; default: 0;
  *  The value of these bits is the configured SPI transmission data bit length in
  *  master mode DMA controlled transfer or CPU controlled transfer. The value is also
@@ -500,7 +500,7 @@ extern "C" {
 /** SPI_MISC_REG register
  *  SPI misc register
  */
-#define SPI_MISC_REG (DR_REG_SPI_BASE + 0x20)
+#define SPI_MISC_REG(i) (REG_SPI_BASE(i) + 0x20)
 /** SPI_CS0_DIS : R/W; bitpos: [0]; default: 0;
  *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
  *  be configured in CONF state.
@@ -650,7 +650,7 @@ extern "C" {
 /** SPI_DIN_MODE_REG register
  *  SPI input delay mode configuration
  */
-#define SPI_DIN_MODE_REG (DR_REG_SPI_BASE + 0x24)
+#define SPI_DIN_MODE_REG(i) (REG_SPI_BASE(i) + 0x24)
 /** SPI_DIN0_MODE : R/W; bitpos: [1:0]; default: 0;
  *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
  *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
@@ -739,7 +739,7 @@ extern "C" {
 /** SPI_DIN_NUM_REG register
  *  SPI input delay number configuration
  */
-#define SPI_DIN_NUM_REG (DR_REG_SPI_BASE + 0x28)
+#define SPI_DIN_NUM_REG(i) (REG_SPI_BASE(i) + 0x28)
 /** SPI_DIN0_NUM : R/W; bitpos: [1:0]; default: 0;
  *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
  *  delayed by 2 cycles,...  Can be configured in CONF state.
@@ -812,7 +812,7 @@ extern "C" {
 /** SPI_DOUT_MODE_REG register
  *  SPI output delay mode configuration
  */
-#define SPI_DOUT_MODE_REG (DR_REG_SPI_BASE + 0x2c)
+#define SPI_DOUT_MODE_REG(i) (REG_SPI_BASE(i) + 0x2c)
 /** SPI_DOUT0_MODE : R/W; bitpos: [0]; default: 0;
  *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
  *  1: output delay for a SPI module clock cycle at its negative edge. Can be
@@ -903,7 +903,7 @@ extern "C" {
 /** SPI_DMA_CONF_REG register
  *  SPI DMA control register
  */
-#define SPI_DMA_CONF_REG (DR_REG_SPI_BASE + 0x30)
+#define SPI_DMA_CONF_REG(i) (REG_SPI_BASE(i) + 0x30)
 /** SPI_DMA_OUTFIFO_EMPTY : RO; bitpos: [0]; default: 1;
  *  Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data. 0:
  *  DMA TX FIFO is ready for sending data.
@@ -995,7 +995,7 @@ extern "C" {
 /** SPI_DMA_INT_ENA_REG register
  *  SPI interrupt enable register
  */
-#define SPI_DMA_INT_ENA_REG (DR_REG_SPI_BASE + 0x34)
+#define SPI_DMA_INT_ENA_REG(i) (REG_SPI_BASE(i) + 0x34)
 /** SPI_DMA_INFIFO_FULL_ERR_INT_ENA : R/W; bitpos: [0]; default: 0;
  *  The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
  */
@@ -1148,7 +1148,7 @@ extern "C" {
 /** SPI_DMA_INT_CLR_REG register
  *  SPI interrupt clear register
  */
-#define SPI_DMA_INT_CLR_REG (DR_REG_SPI_BASE + 0x38)
+#define SPI_DMA_INT_CLR_REG(i) (REG_SPI_BASE(i) + 0x38)
 /** SPI_DMA_INFIFO_FULL_ERR_INT_CLR : WT; bitpos: [0]; default: 0;
  *  The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
  */
@@ -1301,7 +1301,7 @@ extern "C" {
 /** SPI_DMA_INT_RAW_REG register
  *  SPI interrupt raw register
  */
-#define SPI_DMA_INT_RAW_REG (DR_REG_SPI_BASE + 0x3c)
+#define SPI_DMA_INT_RAW_REG(i) (REG_SPI_BASE(i) + 0x3c)
 /** SPI_DMA_INFIFO_FULL_ERR_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
  *  1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the
  *  receive data.  0: Others.
@@ -1476,7 +1476,7 @@ extern "C" {
 /** SPI_DMA_INT_ST_REG register
  *  SPI interrupt status register
  */
-#define SPI_DMA_INT_ST_REG (DR_REG_SPI_BASE + 0x40)
+#define SPI_DMA_INT_ST_REG(i) (REG_SPI_BASE(i) + 0x40)
 /** SPI_DMA_INFIFO_FULL_ERR_INT_ST : RO; bitpos: [0]; default: 0;
  *  The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
  */
@@ -1629,7 +1629,7 @@ extern "C" {
 /** SPI_DMA_INT_SET_REG register
  *  SPI interrupt software set register
  */
-#define SPI_DMA_INT_SET_REG (DR_REG_SPI_BASE + 0x44)
+#define SPI_DMA_INT_SET_REG(i) (REG_SPI_BASE(i) + 0x44)
 /** SPI_DMA_INFIFO_FULL_ERR_INT_SET : WT; bitpos: [0]; default: 0;
  *  The software set bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
  */
@@ -1782,7 +1782,7 @@ extern "C" {
 /** SPI_W0_REG register
  *  SPI CPU-controlled buffer0
  */
-#define SPI_W0_REG (DR_REG_SPI_BASE + 0x98)
+#define SPI_W0_REG(i) (REG_SPI_BASE(i) + 0x98)
 /** SPI_BUF0 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
@@ -1794,7 +1794,7 @@ extern "C" {
 /** SPI_W1_REG register
  *  SPI CPU-controlled buffer1
  */
-#define SPI_W1_REG (DR_REG_SPI_BASE + 0x9c)
+#define SPI_W1_REG(i) (REG_SPI_BASE(i) + 0x9c)
 /** SPI_BUF1 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
@@ -1806,7 +1806,7 @@ extern "C" {
 /** SPI_W2_REG register
  *  SPI CPU-controlled buffer2
  */
-#define SPI_W2_REG (DR_REG_SPI_BASE + 0xa0)
+#define SPI_W2_REG(i) (REG_SPI_BASE(i) + 0xa0)
 /** SPI_BUF2 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
@@ -1818,7 +1818,7 @@ extern "C" {
 /** SPI_W3_REG register
  *  SPI CPU-controlled buffer3
  */
-#define SPI_W3_REG (DR_REG_SPI_BASE + 0xa4)
+#define SPI_W3_REG(i) (REG_SPI_BASE(i) + 0xa4)
 /** SPI_BUF3 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
@@ -1830,7 +1830,7 @@ extern "C" {
 /** SPI_W4_REG register
  *  SPI CPU-controlled buffer4
  */
-#define SPI_W4_REG (DR_REG_SPI_BASE + 0xa8)
+#define SPI_W4_REG(i) (REG_SPI_BASE(i) + 0xa8)
 /** SPI_BUF4 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
@@ -1842,7 +1842,7 @@ extern "C" {
 /** SPI_W5_REG register
  *  SPI CPU-controlled buffer5
  */
-#define SPI_W5_REG (DR_REG_SPI_BASE + 0xac)
+#define SPI_W5_REG(i) (REG_SPI_BASE(i) + 0xac)
 /** SPI_BUF5 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
@@ -1854,7 +1854,7 @@ extern "C" {
 /** SPI_W6_REG register
  *  SPI CPU-controlled buffer6
  */
-#define SPI_W6_REG (DR_REG_SPI_BASE + 0xb0)
+#define SPI_W6_REG(i) (REG_SPI_BASE(i) + 0xb0)
 /** SPI_BUF6 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
@@ -1866,7 +1866,7 @@ extern "C" {
 /** SPI_W7_REG register
  *  SPI CPU-controlled buffer7
  */
-#define SPI_W7_REG (DR_REG_SPI_BASE + 0xb4)
+#define SPI_W7_REG(i) (REG_SPI_BASE(i) + 0xb4)
 /** SPI_BUF7 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
@@ -1878,7 +1878,7 @@ extern "C" {
 /** SPI_W8_REG register
  *  SPI CPU-controlled buffer8
  */
-#define SPI_W8_REG (DR_REG_SPI_BASE + 0xb8)
+#define SPI_W8_REG(i) (REG_SPI_BASE(i) + 0xb8)
 /** SPI_BUF8 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
@@ -1890,7 +1890,7 @@ extern "C" {
 /** SPI_W9_REG register
  *  SPI CPU-controlled buffer9
  */
-#define SPI_W9_REG (DR_REG_SPI_BASE + 0xbc)
+#define SPI_W9_REG(i) (REG_SPI_BASE(i) + 0xbc)
 /** SPI_BUF9 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
@@ -1902,7 +1902,7 @@ extern "C" {
 /** SPI_W10_REG register
  *  SPI CPU-controlled buffer10
  */
-#define SPI_W10_REG (DR_REG_SPI_BASE + 0xc0)
+#define SPI_W10_REG(i) (REG_SPI_BASE(i) + 0xc0)
 /** SPI_BUF10 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
@@ -1914,7 +1914,7 @@ extern "C" {
 /** SPI_W11_REG register
  *  SPI CPU-controlled buffer11
  */
-#define SPI_W11_REG (DR_REG_SPI_BASE + 0xc4)
+#define SPI_W11_REG(i) (REG_SPI_BASE(i) + 0xc4)
 /** SPI_BUF11 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
@@ -1926,7 +1926,7 @@ extern "C" {
 /** SPI_W12_REG register
  *  SPI CPU-controlled buffer12
  */
-#define SPI_W12_REG (DR_REG_SPI_BASE + 0xc8)
+#define SPI_W12_REG(i) (REG_SPI_BASE(i) + 0xc8)
 /** SPI_BUF12 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
@@ -1938,7 +1938,7 @@ extern "C" {
 /** SPI_W13_REG register
  *  SPI CPU-controlled buffer13
  */
-#define SPI_W13_REG (DR_REG_SPI_BASE + 0xcc)
+#define SPI_W13_REG(i) (REG_SPI_BASE(i) + 0xcc)
 /** SPI_BUF13 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
@@ -1950,7 +1950,7 @@ extern "C" {
 /** SPI_W14_REG register
  *  SPI CPU-controlled buffer14
  */
-#define SPI_W14_REG (DR_REG_SPI_BASE + 0xd0)
+#define SPI_W14_REG(i) (REG_SPI_BASE(i) + 0xd0)
 /** SPI_BUF14 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
@@ -1962,7 +1962,7 @@ extern "C" {
 /** SPI_W15_REG register
  *  SPI CPU-controlled buffer15
  */
-#define SPI_W15_REG (DR_REG_SPI_BASE + 0xd4)
+#define SPI_W15_REG(i) (REG_SPI_BASE(i) + 0xd4)
 /** SPI_BUF15 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
@@ -1974,7 +1974,7 @@ extern "C" {
 /** SPI_SLAVE_REG register
  *  SPI slave control register
  */
-#define SPI_SLAVE_REG (DR_REG_SPI_BASE + 0xe0)
+#define SPI_SLAVE_REG(i) (REG_SPI_BASE(i) + 0xe0)
 /** SPI_CLK_MODE : R/W; bitpos: [1:0]; default: 0;
  *  SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed
  *  one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3:
@@ -2085,7 +2085,7 @@ extern "C" {
 /** SPI_SLAVE1_REG register
  *  SPI slave control register 1
  */
-#define SPI_SLAVE1_REG (DR_REG_SPI_BASE + 0xe4)
+#define SPI_SLAVE1_REG(i) (REG_SPI_BASE(i) + 0xe4)
 /** SPI_SLV_DATA_BITLEN : R/W/SS; bitpos: [17:0]; default: 0;
  *  The transferred data bit length in SPI slave FD and HD mode.
  */
@@ -2111,7 +2111,7 @@ extern "C" {
 /** SPI_CLK_GATE_REG register
  *  SPI module clock and register clock control
  */
-#define SPI_CLK_GATE_REG (DR_REG_SPI_BASE + 0xe8)
+#define SPI_CLK_GATE_REG(i) (REG_SPI_BASE(i) + 0xe8)
 /** SPI_CLK_EN : R/W; bitpos: [0]; default: 0;
  *  Set this bit to enable clk gate
  */
@@ -2138,7 +2138,7 @@ extern "C" {
 /** SPI_DATE_REG register
  *  Version control
  */
-#define SPI_DATE_REG (DR_REG_SPI_BASE + 0xf0)
+#define SPI_DATE_REG(i) (REG_SPI_BASE(i) + 0xf0)
 /** SPI_DATE : R/W; bitpos: [27:0]; default: 35680770;
  *  SPI register version.
  */

components/soc/esp32p4/include/soc/spi_struct.h

@@ -1393,6 +1393,8 @@ typedef struct {
     volatile spi_date_reg_t date;
 } spi_dev_t;
 
+extern spi_dev_t GPSPI2;
+extern spi_dev_t GPSPI3;
 
 #ifndef __cplusplus
 _Static_assert(sizeof(spi_dev_t) == 0xf4, "Invalid size of spi_dev_t structure");

components/soc/esp32p4/include/soc/sys_timer_reg.h

@@ -1,630 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** SYSTIMER_CONF_REG register
- *  Configure system timer clock
- */
-#define SYSTIMER_CONF_REG (DR_REG_SYSTIMER_BASE + 0x0)
-/** SYSTIMER_ETM_EN : R/W; bitpos: [1]; default: 0;
- *  enable systimer's etm task and event
- */
-#define SYSTIMER_ETM_EN    (BIT(1))
-#define SYSTIMER_ETM_EN_M  (SYSTIMER_ETM_EN_V << SYSTIMER_ETM_EN_S)
-#define SYSTIMER_ETM_EN_V  0x00000001U
-#define SYSTIMER_ETM_EN_S  1
-/** SYSTIMER_TARGET2_WORK_EN : R/W; bitpos: [22]; default: 0;
- *  target2 work enable
- */
-#define SYSTIMER_TARGET2_WORK_EN    (BIT(22))
-#define SYSTIMER_TARGET2_WORK_EN_M  (SYSTIMER_TARGET2_WORK_EN_V << SYSTIMER_TARGET2_WORK_EN_S)
-#define SYSTIMER_TARGET2_WORK_EN_V  0x00000001U
-#define SYSTIMER_TARGET2_WORK_EN_S  22
-/** SYSTIMER_TARGET1_WORK_EN : R/W; bitpos: [23]; default: 0;
- *  target1 work enable
- */
-#define SYSTIMER_TARGET1_WORK_EN    (BIT(23))
-#define SYSTIMER_TARGET1_WORK_EN_M  (SYSTIMER_TARGET1_WORK_EN_V << SYSTIMER_TARGET1_WORK_EN_S)
-#define SYSTIMER_TARGET1_WORK_EN_V  0x00000001U
-#define SYSTIMER_TARGET1_WORK_EN_S  23
-/** SYSTIMER_TARGET0_WORK_EN : R/W; bitpos: [24]; default: 0;
- *  target0 work enable
- */
-#define SYSTIMER_TARGET0_WORK_EN    (BIT(24))
-#define SYSTIMER_TARGET0_WORK_EN_M  (SYSTIMER_TARGET0_WORK_EN_V << SYSTIMER_TARGET0_WORK_EN_S)
-#define SYSTIMER_TARGET0_WORK_EN_V  0x00000001U
-#define SYSTIMER_TARGET0_WORK_EN_S  24
-/** SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN : R/W; bitpos: [25]; default: 1;
- *  If timer unit1 is stalled when core1 stalled
- */
-#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN    (BIT(25))
-#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_M  (SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_V << SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_S)
-#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_V  0x00000001U
-#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_S  25
-/** SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN : R/W; bitpos: [26]; default: 1;
- *  If timer unit1 is stalled when core0 stalled
- */
-#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN    (BIT(26))
-#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_M  (SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_V << SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_S)
-#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_V  0x00000001U
-#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_S  26
-/** SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN : R/W; bitpos: [27]; default: 0;
- *  If timer unit0 is stalled when core1 stalled
- */
-#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN    (BIT(27))
-#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_M  (SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_V << SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_S)
-#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_V  0x00000001U
-#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_S  27
-/** SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN : R/W; bitpos: [28]; default: 0;
- *  If timer unit0 is stalled when core0 stalled
- */
-#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN    (BIT(28))
-#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_M  (SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_V << SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_S)
-#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_V  0x00000001U
-#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_S  28
-/** SYSTIMER_TIMER_UNIT1_WORK_EN : R/W; bitpos: [29]; default: 0;
- *  timer unit1 work enable
- */
-#define SYSTIMER_TIMER_UNIT1_WORK_EN    (BIT(29))
-#define SYSTIMER_TIMER_UNIT1_WORK_EN_M  (SYSTIMER_TIMER_UNIT1_WORK_EN_V << SYSTIMER_TIMER_UNIT1_WORK_EN_S)
-#define SYSTIMER_TIMER_UNIT1_WORK_EN_V  0x00000001U
-#define SYSTIMER_TIMER_UNIT1_WORK_EN_S  29
-/** SYSTIMER_TIMER_UNIT0_WORK_EN : R/W; bitpos: [30]; default: 1;
- *  timer unit0 work enable
- */
-#define SYSTIMER_TIMER_UNIT0_WORK_EN    (BIT(30))
-#define SYSTIMER_TIMER_UNIT0_WORK_EN_M  (SYSTIMER_TIMER_UNIT0_WORK_EN_V << SYSTIMER_TIMER_UNIT0_WORK_EN_S)
-#define SYSTIMER_TIMER_UNIT0_WORK_EN_V  0x00000001U
-#define SYSTIMER_TIMER_UNIT0_WORK_EN_S  30
-/** SYSTIMER_CLK_EN : R/W; bitpos: [31]; default: 0;
- *  register file clk gating
- */
-#define SYSTIMER_CLK_EN    (BIT(31))
-#define SYSTIMER_CLK_EN_M  (SYSTIMER_CLK_EN_V << SYSTIMER_CLK_EN_S)
-#define SYSTIMER_CLK_EN_V  0x00000001U
-#define SYSTIMER_CLK_EN_S  31
-
-/** SYSTIMER_UNIT0_OP_REG register
- *  system timer unit0 value update register
- */
-#define SYSTIMER_UNIT0_OP_REG (DR_REG_SYSTIMER_BASE + 0x4)
-/** SYSTIMER_TIMER_UNIT0_VALUE_VALID : R/SS/WTC; bitpos: [29]; default: 0;
- *  timer value is sync and valid
- */
-#define SYSTIMER_TIMER_UNIT0_VALUE_VALID    (BIT(29))
-#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_M  (SYSTIMER_TIMER_UNIT0_VALUE_VALID_V << SYSTIMER_TIMER_UNIT0_VALUE_VALID_S)
-#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_V  0x00000001U
-#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_S  29
-/** SYSTIMER_TIMER_UNIT0_UPDATE : WT; bitpos: [30]; default: 0;
- *  update timer_unit0
- */
-#define SYSTIMER_TIMER_UNIT0_UPDATE    (BIT(30))
-#define SYSTIMER_TIMER_UNIT0_UPDATE_M  (SYSTIMER_TIMER_UNIT0_UPDATE_V << SYSTIMER_TIMER_UNIT0_UPDATE_S)
-#define SYSTIMER_TIMER_UNIT0_UPDATE_V  0x00000001U
-#define SYSTIMER_TIMER_UNIT0_UPDATE_S  30
-
-/** SYSTIMER_UNIT1_OP_REG register
- *  system timer unit1 value update register
- */
-#define SYSTIMER_UNIT1_OP_REG (DR_REG_SYSTIMER_BASE + 0x8)
-/** SYSTIMER_TIMER_UNIT1_VALUE_VALID : R/SS/WTC; bitpos: [29]; default: 0;
- *  timer value is sync and valid
- */
-#define SYSTIMER_TIMER_UNIT1_VALUE_VALID    (BIT(29))
-#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_M  (SYSTIMER_TIMER_UNIT1_VALUE_VALID_V << SYSTIMER_TIMER_UNIT1_VALUE_VALID_S)
-#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_V  0x00000001U
-#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_S  29
-/** SYSTIMER_TIMER_UNIT1_UPDATE : WT; bitpos: [30]; default: 0;
- *  update timer unit1
- */
-#define SYSTIMER_TIMER_UNIT1_UPDATE    (BIT(30))
-#define SYSTIMER_TIMER_UNIT1_UPDATE_M  (SYSTIMER_TIMER_UNIT1_UPDATE_V << SYSTIMER_TIMER_UNIT1_UPDATE_S)
-#define SYSTIMER_TIMER_UNIT1_UPDATE_V  0x00000001U
-#define SYSTIMER_TIMER_UNIT1_UPDATE_S  30
-
-/** SYSTIMER_UNIT0_LOAD_HI_REG register
- *  system timer unit0 value high load register
- */
-#define SYSTIMER_UNIT0_LOAD_HI_REG (DR_REG_SYSTIMER_BASE + 0xc)
-/** SYSTIMER_TIMER_UNIT0_LOAD_HI : R/W; bitpos: [19:0]; default: 0;
- *  timer unit0 load high 20 bits
- */
-#define SYSTIMER_TIMER_UNIT0_LOAD_HI    0x000FFFFFU
-#define SYSTIMER_TIMER_UNIT0_LOAD_HI_M  (SYSTIMER_TIMER_UNIT0_LOAD_HI_V << SYSTIMER_TIMER_UNIT0_LOAD_HI_S)
-#define SYSTIMER_TIMER_UNIT0_LOAD_HI_V  0x000FFFFFU
-#define SYSTIMER_TIMER_UNIT0_LOAD_HI_S  0
-
-/** SYSTIMER_UNIT0_LOAD_LO_REG register
- *  system timer unit0 value low load register
- */
-#define SYSTIMER_UNIT0_LOAD_LO_REG (DR_REG_SYSTIMER_BASE + 0x10)
-/** SYSTIMER_TIMER_UNIT0_LOAD_LO : R/W; bitpos: [31:0]; default: 0;
- *  timer unit0 load low 32 bits
- */
-#define SYSTIMER_TIMER_UNIT0_LOAD_LO    0xFFFFFFFFU
-#define SYSTIMER_TIMER_UNIT0_LOAD_LO_M  (SYSTIMER_TIMER_UNIT0_LOAD_LO_V << SYSTIMER_TIMER_UNIT0_LOAD_LO_S)
-#define SYSTIMER_TIMER_UNIT0_LOAD_LO_V  0xFFFFFFFFU
-#define SYSTIMER_TIMER_UNIT0_LOAD_LO_S  0
-
-/** SYSTIMER_UNIT1_LOAD_HI_REG register
- *  system timer unit1 value high load register
- */
-#define SYSTIMER_UNIT1_LOAD_HI_REG (DR_REG_SYSTIMER_BASE + 0x14)
-/** SYSTIMER_TIMER_UNIT1_LOAD_HI : R/W; bitpos: [19:0]; default: 0;
- *  timer unit1 load high 20 bits
- */
-#define SYSTIMER_TIMER_UNIT1_LOAD_HI    0x000FFFFFU
-#define SYSTIMER_TIMER_UNIT1_LOAD_HI_M  (SYSTIMER_TIMER_UNIT1_LOAD_HI_V << SYSTIMER_TIMER_UNIT1_LOAD_HI_S)
-#define SYSTIMER_TIMER_UNIT1_LOAD_HI_V  0x000FFFFFU
-#define SYSTIMER_TIMER_UNIT1_LOAD_HI_S  0
-
-/** SYSTIMER_UNIT1_LOAD_LO_REG register
- *  system timer unit1 value low load register
- */
-#define SYSTIMER_UNIT1_LOAD_LO_REG (DR_REG_SYSTIMER_BASE + 0x18)
-/** SYSTIMER_TIMER_UNIT1_LOAD_LO : R/W; bitpos: [31:0]; default: 0;
- *  timer unit1 load low 32 bits
- */
-#define SYSTIMER_TIMER_UNIT1_LOAD_LO    0xFFFFFFFFU
-#define SYSTIMER_TIMER_UNIT1_LOAD_LO_M  (SYSTIMER_TIMER_UNIT1_LOAD_LO_V << SYSTIMER_TIMER_UNIT1_LOAD_LO_S)
-#define SYSTIMER_TIMER_UNIT1_LOAD_LO_V  0xFFFFFFFFU
-#define SYSTIMER_TIMER_UNIT1_LOAD_LO_S  0
-
-/** SYSTIMER_TARGET0_HI_REG register
- *  system timer comp0 value high register
- */
-#define SYSTIMER_TARGET0_HI_REG (DR_REG_SYSTIMER_BASE + 0x1c)
-/** SYSTIMER_TIMER_TARGET0_HI : R/W; bitpos: [19:0]; default: 0;
- *  timer taget0 high 20 bits
- */
-#define SYSTIMER_TIMER_TARGET0_HI    0x000FFFFFU
-#define SYSTIMER_TIMER_TARGET0_HI_M  (SYSTIMER_TIMER_TARGET0_HI_V << SYSTIMER_TIMER_TARGET0_HI_S)
-#define SYSTIMER_TIMER_TARGET0_HI_V  0x000FFFFFU
-#define SYSTIMER_TIMER_TARGET0_HI_S  0
-
-/** SYSTIMER_TARGET0_LO_REG register
- *  system timer comp0 value low register
- */
-#define SYSTIMER_TARGET0_LO_REG (DR_REG_SYSTIMER_BASE + 0x20)
-/** SYSTIMER_TIMER_TARGET0_LO : R/W; bitpos: [31:0]; default: 0;
- *  timer taget0 low 32 bits
- */
-#define SYSTIMER_TIMER_TARGET0_LO    0xFFFFFFFFU
-#define SYSTIMER_TIMER_TARGET0_LO_M  (SYSTIMER_TIMER_TARGET0_LO_V << SYSTIMER_TIMER_TARGET0_LO_S)
-#define SYSTIMER_TIMER_TARGET0_LO_V  0xFFFFFFFFU
-#define SYSTIMER_TIMER_TARGET0_LO_S  0
-
-/** SYSTIMER_TARGET1_HI_REG register
- *  system timer comp1 value high register
- */
-#define SYSTIMER_TARGET1_HI_REG (DR_REG_SYSTIMER_BASE + 0x24)
-/** SYSTIMER_TIMER_TARGET1_HI : R/W; bitpos: [19:0]; default: 0;
- *  timer taget1 high 20 bits
- */
-#define SYSTIMER_TIMER_TARGET1_HI    0x000FFFFFU
-#define SYSTIMER_TIMER_TARGET1_HI_M  (SYSTIMER_TIMER_TARGET1_HI_V << SYSTIMER_TIMER_TARGET1_HI_S)
-#define SYSTIMER_TIMER_TARGET1_HI_V  0x000FFFFFU
-#define SYSTIMER_TIMER_TARGET1_HI_S  0
-
-/** SYSTIMER_TARGET1_LO_REG register
- *  system timer comp1 value low register
- */
-#define SYSTIMER_TARGET1_LO_REG (DR_REG_SYSTIMER_BASE + 0x28)
-/** SYSTIMER_TIMER_TARGET1_LO : R/W; bitpos: [31:0]; default: 0;
- *  timer taget1 low 32 bits
- */
-#define SYSTIMER_TIMER_TARGET1_LO    0xFFFFFFFFU
-#define SYSTIMER_TIMER_TARGET1_LO_M  (SYSTIMER_TIMER_TARGET1_LO_V << SYSTIMER_TIMER_TARGET1_LO_S)
-#define SYSTIMER_TIMER_TARGET1_LO_V  0xFFFFFFFFU
-#define SYSTIMER_TIMER_TARGET1_LO_S  0
-
-/** SYSTIMER_TARGET2_HI_REG register
- *  system timer comp2 value high register
- */
-#define SYSTIMER_TARGET2_HI_REG (DR_REG_SYSTIMER_BASE + 0x2c)
-/** SYSTIMER_TIMER_TARGET2_HI : R/W; bitpos: [19:0]; default: 0;
- *  timer taget2 high 20 bits
- */
-#define SYSTIMER_TIMER_TARGET2_HI    0x000FFFFFU
-#define SYSTIMER_TIMER_TARGET2_HI_M  (SYSTIMER_TIMER_TARGET2_HI_V << SYSTIMER_TIMER_TARGET2_HI_S)
-#define SYSTIMER_TIMER_TARGET2_HI_V  0x000FFFFFU
-#define SYSTIMER_TIMER_TARGET2_HI_S  0
-
-/** SYSTIMER_TARGET2_LO_REG register
- *  system timer comp2 value low register
- */
-#define SYSTIMER_TARGET2_LO_REG (DR_REG_SYSTIMER_BASE + 0x30)
-/** SYSTIMER_TIMER_TARGET2_LO : R/W; bitpos: [31:0]; default: 0;
- *  timer taget2 low 32 bits
- */
-#define SYSTIMER_TIMER_TARGET2_LO    0xFFFFFFFFU
-#define SYSTIMER_TIMER_TARGET2_LO_M  (SYSTIMER_TIMER_TARGET2_LO_V << SYSTIMER_TIMER_TARGET2_LO_S)
-#define SYSTIMER_TIMER_TARGET2_LO_V  0xFFFFFFFFU
-#define SYSTIMER_TIMER_TARGET2_LO_S  0
-
-/** SYSTIMER_TARGET0_CONF_REG register
- *  system timer comp0 target mode register
- */
-#define SYSTIMER_TARGET0_CONF_REG (DR_REG_SYSTIMER_BASE + 0x34)
-/** SYSTIMER_TARGET0_PERIOD : R/W; bitpos: [25:0]; default: 0;
- *  target0 period
- */
-#define SYSTIMER_TARGET0_PERIOD    0x03FFFFFFU
-#define SYSTIMER_TARGET0_PERIOD_M  (SYSTIMER_TARGET0_PERIOD_V << SYSTIMER_TARGET0_PERIOD_S)
-#define SYSTIMER_TARGET0_PERIOD_V  0x03FFFFFFU
-#define SYSTIMER_TARGET0_PERIOD_S  0
-/** SYSTIMER_TARGET0_PERIOD_MODE : R/W; bitpos: [30]; default: 0;
- *  Set target0 to period mode
- */
-#define SYSTIMER_TARGET0_PERIOD_MODE    (BIT(30))
-#define SYSTIMER_TARGET0_PERIOD_MODE_M  (SYSTIMER_TARGET0_PERIOD_MODE_V << SYSTIMER_TARGET0_PERIOD_MODE_S)
-#define SYSTIMER_TARGET0_PERIOD_MODE_V  0x00000001U
-#define SYSTIMER_TARGET0_PERIOD_MODE_S  30
-/** SYSTIMER_TARGET0_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0;
- *  select which unit to compare
- */
-#define SYSTIMER_TARGET0_TIMER_UNIT_SEL    (BIT(31))
-#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_M  (SYSTIMER_TARGET0_TIMER_UNIT_SEL_V << SYSTIMER_TARGET0_TIMER_UNIT_SEL_S)
-#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_V  0x00000001U
-#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_S  31
-
-/** SYSTIMER_TARGET1_CONF_REG register
- *  system timer comp1 target mode register
- */
-#define SYSTIMER_TARGET1_CONF_REG (DR_REG_SYSTIMER_BASE + 0x38)
-/** SYSTIMER_TARGET1_PERIOD : R/W; bitpos: [25:0]; default: 0;
- *  target1 period
- */
-#define SYSTIMER_TARGET1_PERIOD    0x03FFFFFFU
-#define SYSTIMER_TARGET1_PERIOD_M  (SYSTIMER_TARGET1_PERIOD_V << SYSTIMER_TARGET1_PERIOD_S)
-#define SYSTIMER_TARGET1_PERIOD_V  0x03FFFFFFU
-#define SYSTIMER_TARGET1_PERIOD_S  0
-/** SYSTIMER_TARGET1_PERIOD_MODE : R/W; bitpos: [30]; default: 0;
- *  Set target1 to period mode
- */
-#define SYSTIMER_TARGET1_PERIOD_MODE    (BIT(30))
-#define SYSTIMER_TARGET1_PERIOD_MODE_M  (SYSTIMER_TARGET1_PERIOD_MODE_V << SYSTIMER_TARGET1_PERIOD_MODE_S)
-#define SYSTIMER_TARGET1_PERIOD_MODE_V  0x00000001U
-#define SYSTIMER_TARGET1_PERIOD_MODE_S  30
-/** SYSTIMER_TARGET1_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0;
- *  select which unit to compare
- */
-#define SYSTIMER_TARGET1_TIMER_UNIT_SEL    (BIT(31))
-#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_M  (SYSTIMER_TARGET1_TIMER_UNIT_SEL_V << SYSTIMER_TARGET1_TIMER_UNIT_SEL_S)
-#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_V  0x00000001U
-#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_S  31
-
-/** SYSTIMER_TARGET2_CONF_REG register
- *  system timer comp2 target mode register
- */
-#define SYSTIMER_TARGET2_CONF_REG (DR_REG_SYSTIMER_BASE + 0x3c)
-/** SYSTIMER_TARGET2_PERIOD : R/W; bitpos: [25:0]; default: 0;
- *  target2 period
- */
-#define SYSTIMER_TARGET2_PERIOD    0x03FFFFFFU
-#define SYSTIMER_TARGET2_PERIOD_M  (SYSTIMER_TARGET2_PERIOD_V << SYSTIMER_TARGET2_PERIOD_S)
-#define SYSTIMER_TARGET2_PERIOD_V  0x03FFFFFFU
-#define SYSTIMER_TARGET2_PERIOD_S  0
-/** SYSTIMER_TARGET2_PERIOD_MODE : R/W; bitpos: [30]; default: 0;
- *  Set target2 to period mode
- */
-#define SYSTIMER_TARGET2_PERIOD_MODE    (BIT(30))
-#define SYSTIMER_TARGET2_PERIOD_MODE_M  (SYSTIMER_TARGET2_PERIOD_MODE_V << SYSTIMER_TARGET2_PERIOD_MODE_S)
-#define SYSTIMER_TARGET2_PERIOD_MODE_V  0x00000001U
-#define SYSTIMER_TARGET2_PERIOD_MODE_S  30
-/** SYSTIMER_TARGET2_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0;
- *  select which unit to compare
- */
-#define SYSTIMER_TARGET2_TIMER_UNIT_SEL    (BIT(31))
-#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_M  (SYSTIMER_TARGET2_TIMER_UNIT_SEL_V << SYSTIMER_TARGET2_TIMER_UNIT_SEL_S)
-#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_V  0x00000001U
-#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_S  31
-
-/** SYSTIMER_UNIT0_VALUE_HI_REG register
- *  system timer unit0 value high register
- */
-#define SYSTIMER_UNIT0_VALUE_HI_REG (DR_REG_SYSTIMER_BASE + 0x40)
-/** SYSTIMER_TIMER_UNIT0_VALUE_HI : RO; bitpos: [19:0]; default: 0;
- *  timer read value high 20bits
- */
-#define SYSTIMER_TIMER_UNIT0_VALUE_HI    0x000FFFFFU
-#define SYSTIMER_TIMER_UNIT0_VALUE_HI_M  (SYSTIMER_TIMER_UNIT0_VALUE_HI_V << SYSTIMER_TIMER_UNIT0_VALUE_HI_S)
-#define SYSTIMER_TIMER_UNIT0_VALUE_HI_V  0x000FFFFFU
-#define SYSTIMER_TIMER_UNIT0_VALUE_HI_S  0
-
-/** SYSTIMER_UNIT0_VALUE_LO_REG register
- *  system timer unit0 value low register
- */
-#define SYSTIMER_UNIT0_VALUE_LO_REG (DR_REG_SYSTIMER_BASE + 0x44)
-/** SYSTIMER_TIMER_UNIT0_VALUE_LO : RO; bitpos: [31:0]; default: 0;
- *  timer read value low 32bits
- */
-#define SYSTIMER_TIMER_UNIT0_VALUE_LO    0xFFFFFFFFU
-#define SYSTIMER_TIMER_UNIT0_VALUE_LO_M  (SYSTIMER_TIMER_UNIT0_VALUE_LO_V << SYSTIMER_TIMER_UNIT0_VALUE_LO_S)
-#define SYSTIMER_TIMER_UNIT0_VALUE_LO_V  0xFFFFFFFFU
-#define SYSTIMER_TIMER_UNIT0_VALUE_LO_S  0
-
-/** SYSTIMER_UNIT1_VALUE_HI_REG register
- *  system timer unit1 value high register
- */
-#define SYSTIMER_UNIT1_VALUE_HI_REG (DR_REG_SYSTIMER_BASE + 0x48)
-/** SYSTIMER_TIMER_UNIT1_VALUE_HI : RO; bitpos: [19:0]; default: 0;
- *  timer read value high 20bits
- */
-#define SYSTIMER_TIMER_UNIT1_VALUE_HI    0x000FFFFFU
-#define SYSTIMER_TIMER_UNIT1_VALUE_HI_M  (SYSTIMER_TIMER_UNIT1_VALUE_HI_V << SYSTIMER_TIMER_UNIT1_VALUE_HI_S)
-#define SYSTIMER_TIMER_UNIT1_VALUE_HI_V  0x000FFFFFU
-#define SYSTIMER_TIMER_UNIT1_VALUE_HI_S  0
-
-/** SYSTIMER_UNIT1_VALUE_LO_REG register
- *  system timer unit1 value low register
- */
-#define SYSTIMER_UNIT1_VALUE_LO_REG (DR_REG_SYSTIMER_BASE + 0x4c)
-/** SYSTIMER_TIMER_UNIT1_VALUE_LO : RO; bitpos: [31:0]; default: 0;
- *  timer read value low 32bits
- */
-#define SYSTIMER_TIMER_UNIT1_VALUE_LO    0xFFFFFFFFU
-#define SYSTIMER_TIMER_UNIT1_VALUE_LO_M  (SYSTIMER_TIMER_UNIT1_VALUE_LO_V << SYSTIMER_TIMER_UNIT1_VALUE_LO_S)
-#define SYSTIMER_TIMER_UNIT1_VALUE_LO_V  0xFFFFFFFFU
-#define SYSTIMER_TIMER_UNIT1_VALUE_LO_S  0
-
-/** SYSTIMER_COMP0_LOAD_REG register
- *  system timer comp0 conf sync register
- */
-#define SYSTIMER_COMP0_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x50)
-/** SYSTIMER_TIMER_COMP0_LOAD : WT; bitpos: [0]; default: 0;
- *  timer comp0 sync enable signal
- */
-#define SYSTIMER_TIMER_COMP0_LOAD    (BIT(0))
-#define SYSTIMER_TIMER_COMP0_LOAD_M  (SYSTIMER_TIMER_COMP0_LOAD_V << SYSTIMER_TIMER_COMP0_LOAD_S)
-#define SYSTIMER_TIMER_COMP0_LOAD_V  0x00000001U
-#define SYSTIMER_TIMER_COMP0_LOAD_S  0
-
-/** SYSTIMER_COMP1_LOAD_REG register
- *  system timer comp1 conf sync register
- */
-#define SYSTIMER_COMP1_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x54)
-/** SYSTIMER_TIMER_COMP1_LOAD : WT; bitpos: [0]; default: 0;
- *  timer comp1 sync enable signal
- */
-#define SYSTIMER_TIMER_COMP1_LOAD    (BIT(0))
-#define SYSTIMER_TIMER_COMP1_LOAD_M  (SYSTIMER_TIMER_COMP1_LOAD_V << SYSTIMER_TIMER_COMP1_LOAD_S)
-#define SYSTIMER_TIMER_COMP1_LOAD_V  0x00000001U
-#define SYSTIMER_TIMER_COMP1_LOAD_S  0
-
-/** SYSTIMER_COMP2_LOAD_REG register
- *  system timer comp2 conf sync register
- */
-#define SYSTIMER_COMP2_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x58)
-/** SYSTIMER_TIMER_COMP2_LOAD : WT; bitpos: [0]; default: 0;
- *  timer comp2 sync enable signal
- */
-#define SYSTIMER_TIMER_COMP2_LOAD    (BIT(0))
-#define SYSTIMER_TIMER_COMP2_LOAD_M  (SYSTIMER_TIMER_COMP2_LOAD_V << SYSTIMER_TIMER_COMP2_LOAD_S)
-#define SYSTIMER_TIMER_COMP2_LOAD_V  0x00000001U
-#define SYSTIMER_TIMER_COMP2_LOAD_S  0
-
-/** SYSTIMER_UNIT0_LOAD_REG register
- *  system timer unit0 conf sync register
- */
-#define SYSTIMER_UNIT0_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x5c)
-/** SYSTIMER_TIMER_UNIT0_LOAD : WT; bitpos: [0]; default: 0;
- *  timer unit0 sync enable signal
- */
-#define SYSTIMER_TIMER_UNIT0_LOAD    (BIT(0))
-#define SYSTIMER_TIMER_UNIT0_LOAD_M  (SYSTIMER_TIMER_UNIT0_LOAD_V << SYSTIMER_TIMER_UNIT0_LOAD_S)
-#define SYSTIMER_TIMER_UNIT0_LOAD_V  0x00000001U
-#define SYSTIMER_TIMER_UNIT0_LOAD_S  0
-
-/** SYSTIMER_UNIT1_LOAD_REG register
- *  system timer unit1 conf sync register
- */
-#define SYSTIMER_UNIT1_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x60)
-/** SYSTIMER_TIMER_UNIT1_LOAD : WT; bitpos: [0]; default: 0;
- *  timer unit1 sync enable signal
- */
-#define SYSTIMER_TIMER_UNIT1_LOAD    (BIT(0))
-#define SYSTIMER_TIMER_UNIT1_LOAD_M  (SYSTIMER_TIMER_UNIT1_LOAD_V << SYSTIMER_TIMER_UNIT1_LOAD_S)
-#define SYSTIMER_TIMER_UNIT1_LOAD_V  0x00000001U
-#define SYSTIMER_TIMER_UNIT1_LOAD_S  0
-
-/** SYSTIMER_INT_ENA_REG register
- *  systimer interrupt enable register
- */
-#define SYSTIMER_INT_ENA_REG (DR_REG_SYSTIMER_BASE + 0x64)
-/** SYSTIMER_TARGET0_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  interupt0 enable
- */
-#define SYSTIMER_TARGET0_INT_ENA    (BIT(0))
-#define SYSTIMER_TARGET0_INT_ENA_M  (SYSTIMER_TARGET0_INT_ENA_V << SYSTIMER_TARGET0_INT_ENA_S)
-#define SYSTIMER_TARGET0_INT_ENA_V  0x00000001U
-#define SYSTIMER_TARGET0_INT_ENA_S  0
-/** SYSTIMER_TARGET1_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  interupt1 enable
- */
-#define SYSTIMER_TARGET1_INT_ENA    (BIT(1))
-#define SYSTIMER_TARGET1_INT_ENA_M  (SYSTIMER_TARGET1_INT_ENA_V << SYSTIMER_TARGET1_INT_ENA_S)
-#define SYSTIMER_TARGET1_INT_ENA_V  0x00000001U
-#define SYSTIMER_TARGET1_INT_ENA_S  1
-/** SYSTIMER_TARGET2_INT_ENA : R/W; bitpos: [2]; default: 0;
- *  interupt2 enable
- */
-#define SYSTIMER_TARGET2_INT_ENA    (BIT(2))
-#define SYSTIMER_TARGET2_INT_ENA_M  (SYSTIMER_TARGET2_INT_ENA_V << SYSTIMER_TARGET2_INT_ENA_S)
-#define SYSTIMER_TARGET2_INT_ENA_V  0x00000001U
-#define SYSTIMER_TARGET2_INT_ENA_S  2
-
-/** SYSTIMER_INT_RAW_REG register
- *  systimer interrupt raw register
- */
-#define SYSTIMER_INT_RAW_REG (DR_REG_SYSTIMER_BASE + 0x68)
-/** SYSTIMER_TARGET0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
- *  interupt0 raw
- */
-#define SYSTIMER_TARGET0_INT_RAW    (BIT(0))
-#define SYSTIMER_TARGET0_INT_RAW_M  (SYSTIMER_TARGET0_INT_RAW_V << SYSTIMER_TARGET0_INT_RAW_S)
-#define SYSTIMER_TARGET0_INT_RAW_V  0x00000001U
-#define SYSTIMER_TARGET0_INT_RAW_S  0
-/** SYSTIMER_TARGET1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
- *  interupt1 raw
- */
-#define SYSTIMER_TARGET1_INT_RAW    (BIT(1))
-#define SYSTIMER_TARGET1_INT_RAW_M  (SYSTIMER_TARGET1_INT_RAW_V << SYSTIMER_TARGET1_INT_RAW_S)
-#define SYSTIMER_TARGET1_INT_RAW_V  0x00000001U
-#define SYSTIMER_TARGET1_INT_RAW_S  1
-/** SYSTIMER_TARGET2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
- *  interupt2 raw
- */
-#define SYSTIMER_TARGET2_INT_RAW    (BIT(2))
-#define SYSTIMER_TARGET2_INT_RAW_M  (SYSTIMER_TARGET2_INT_RAW_V << SYSTIMER_TARGET2_INT_RAW_S)
-#define SYSTIMER_TARGET2_INT_RAW_V  0x00000001U
-#define SYSTIMER_TARGET2_INT_RAW_S  2
-
-/** SYSTIMER_INT_CLR_REG register
- *  systimer interrupt clear register
- */
-#define SYSTIMER_INT_CLR_REG (DR_REG_SYSTIMER_BASE + 0x6c)
-/** SYSTIMER_TARGET0_INT_CLR : WT; bitpos: [0]; default: 0;
- *  interupt0 clear
- */
-#define SYSTIMER_TARGET0_INT_CLR    (BIT(0))
-#define SYSTIMER_TARGET0_INT_CLR_M  (SYSTIMER_TARGET0_INT_CLR_V << SYSTIMER_TARGET0_INT_CLR_S)
-#define SYSTIMER_TARGET0_INT_CLR_V  0x00000001U
-#define SYSTIMER_TARGET0_INT_CLR_S  0
-/** SYSTIMER_TARGET1_INT_CLR : WT; bitpos: [1]; default: 0;
- *  interupt1 clear
- */
-#define SYSTIMER_TARGET1_INT_CLR    (BIT(1))
-#define SYSTIMER_TARGET1_INT_CLR_M  (SYSTIMER_TARGET1_INT_CLR_V << SYSTIMER_TARGET1_INT_CLR_S)
-#define SYSTIMER_TARGET1_INT_CLR_V  0x00000001U
-#define SYSTIMER_TARGET1_INT_CLR_S  1
-/** SYSTIMER_TARGET2_INT_CLR : WT; bitpos: [2]; default: 0;
- *  interupt2 clear
- */
-#define SYSTIMER_TARGET2_INT_CLR    (BIT(2))
-#define SYSTIMER_TARGET2_INT_CLR_M  (SYSTIMER_TARGET2_INT_CLR_V << SYSTIMER_TARGET2_INT_CLR_S)
-#define SYSTIMER_TARGET2_INT_CLR_V  0x00000001U
-#define SYSTIMER_TARGET2_INT_CLR_S  2
-
-/** SYSTIMER_INT_ST_REG register
- *  systimer interrupt status register
- */
-#define SYSTIMER_INT_ST_REG (DR_REG_SYSTIMER_BASE + 0x70)
-/** SYSTIMER_TARGET0_INT_ST : RO; bitpos: [0]; default: 0;
- *  interupt0 status
- */
-#define SYSTIMER_TARGET0_INT_ST    (BIT(0))
-#define SYSTIMER_TARGET0_INT_ST_M  (SYSTIMER_TARGET0_INT_ST_V << SYSTIMER_TARGET0_INT_ST_S)
-#define SYSTIMER_TARGET0_INT_ST_V  0x00000001U
-#define SYSTIMER_TARGET0_INT_ST_S  0
-/** SYSTIMER_TARGET1_INT_ST : RO; bitpos: [1]; default: 0;
- *  interupt1 status
- */
-#define SYSTIMER_TARGET1_INT_ST    (BIT(1))
-#define SYSTIMER_TARGET1_INT_ST_M  (SYSTIMER_TARGET1_INT_ST_V << SYSTIMER_TARGET1_INT_ST_S)
-#define SYSTIMER_TARGET1_INT_ST_V  0x00000001U
-#define SYSTIMER_TARGET1_INT_ST_S  1
-/** SYSTIMER_TARGET2_INT_ST : RO; bitpos: [2]; default: 0;
- *  interupt2 status
- */
-#define SYSTIMER_TARGET2_INT_ST    (BIT(2))
-#define SYSTIMER_TARGET2_INT_ST_M  (SYSTIMER_TARGET2_INT_ST_V << SYSTIMER_TARGET2_INT_ST_S)
-#define SYSTIMER_TARGET2_INT_ST_V  0x00000001U
-#define SYSTIMER_TARGET2_INT_ST_S  2
-
-/** SYSTIMER_REAL_TARGET0_LO_REG register
- *  system timer comp0 actual target value low register
- */
-#define SYSTIMER_REAL_TARGET0_LO_REG (DR_REG_SYSTIMER_BASE + 0x74)
-/** SYSTIMER_TARGET0_LO_RO : RO; bitpos: [31:0]; default: 0;
- *  actual target value value low 32bits
- */
-#define SYSTIMER_TARGET0_LO_RO    0xFFFFFFFFU
-#define SYSTIMER_TARGET0_LO_RO_M  (SYSTIMER_TARGET0_LO_RO_V << SYSTIMER_TARGET0_LO_RO_S)
-#define SYSTIMER_TARGET0_LO_RO_V  0xFFFFFFFFU
-#define SYSTIMER_TARGET0_LO_RO_S  0
-
-/** SYSTIMER_REAL_TARGET0_HI_REG register
- *  system timer comp0 actual target value high register
- */
-#define SYSTIMER_REAL_TARGET0_HI_REG (DR_REG_SYSTIMER_BASE + 0x78)
-/** SYSTIMER_TARGET0_HI_RO : RO; bitpos: [19:0]; default: 0;
- *  actual target value value high 20bits
- */
-#define SYSTIMER_TARGET0_HI_RO    0x000FFFFFU
-#define SYSTIMER_TARGET0_HI_RO_M  (SYSTIMER_TARGET0_HI_RO_V << SYSTIMER_TARGET0_HI_RO_S)
-#define SYSTIMER_TARGET0_HI_RO_V  0x000FFFFFU
-#define SYSTIMER_TARGET0_HI_RO_S  0
-
-/** SYSTIMER_REAL_TARGET1_LO_REG register
- *  system timer comp1 actual target value low register
- */
-#define SYSTIMER_REAL_TARGET1_LO_REG (DR_REG_SYSTIMER_BASE + 0x7c)
-/** SYSTIMER_TARGET1_LO_RO : RO; bitpos: [31:0]; default: 0;
- *  actual target value value low 32bits
- */
-#define SYSTIMER_TARGET1_LO_RO    0xFFFFFFFFU
-#define SYSTIMER_TARGET1_LO_RO_M  (SYSTIMER_TARGET1_LO_RO_V << SYSTIMER_TARGET1_LO_RO_S)
-#define SYSTIMER_TARGET1_LO_RO_V  0xFFFFFFFFU
-#define SYSTIMER_TARGET1_LO_RO_S  0
-
-/** SYSTIMER_REAL_TARGET1_HI_REG register
- *  system timer comp1 actual target value high register
- */
-#define SYSTIMER_REAL_TARGET1_HI_REG (DR_REG_SYSTIMER_BASE + 0x80)
-/** SYSTIMER_TARGET1_HI_RO : RO; bitpos: [19:0]; default: 0;
- *  actual target value value high 20bits
- */
-#define SYSTIMER_TARGET1_HI_RO    0x000FFFFFU
-#define SYSTIMER_TARGET1_HI_RO_M  (SYSTIMER_TARGET1_HI_RO_V << SYSTIMER_TARGET1_HI_RO_S)
-#define SYSTIMER_TARGET1_HI_RO_V  0x000FFFFFU
-#define SYSTIMER_TARGET1_HI_RO_S  0
-
-/** SYSTIMER_REAL_TARGET2_LO_REG register
- *  system timer comp2 actual target value low register
- */
-#define SYSTIMER_REAL_TARGET2_LO_REG (DR_REG_SYSTIMER_BASE + 0x84)
-/** SYSTIMER_TARGET2_LO_RO : RO; bitpos: [31:0]; default: 0;
- *  actual target value value low 32bits
- */
-#define SYSTIMER_TARGET2_LO_RO    0xFFFFFFFFU
-#define SYSTIMER_TARGET2_LO_RO_M  (SYSTIMER_TARGET2_LO_RO_V << SYSTIMER_TARGET2_LO_RO_S)
-#define SYSTIMER_TARGET2_LO_RO_V  0xFFFFFFFFU
-#define SYSTIMER_TARGET2_LO_RO_S  0
-
-/** SYSTIMER_REAL_TARGET2_HI_REG register
- *  system timer comp2 actual target value high register
- */
-#define SYSTIMER_REAL_TARGET2_HI_REG (DR_REG_SYSTIMER_BASE + 0x88)
-/** SYSTIMER_TARGET2_HI_RO : RO; bitpos: [19:0]; default: 0;
- *  actual target value value high 20bits
- */
-#define SYSTIMER_TARGET2_HI_RO    0x000FFFFFU
-#define SYSTIMER_TARGET2_HI_RO_M  (SYSTIMER_TARGET2_HI_RO_V << SYSTIMER_TARGET2_HI_RO_S)
-#define SYSTIMER_TARGET2_HI_RO_V  0x000FFFFFU
-#define SYSTIMER_TARGET2_HI_RO_S  0
-
-/** SYSTIMER_DATE_REG register
- *  system timer version control register
- */
-#define SYSTIMER_DATE_REG (DR_REG_SYSTIMER_BASE + 0xfc)
-/** SYSTIMER_DATE : R/W; bitpos: [31:0]; default: 35655795;
- *  systimer register version
- */
-#define SYSTIMER_DATE    0xFFFFFFFFU
-#define SYSTIMER_DATE_M  (SYSTIMER_DATE_V << SYSTIMER_DATE_S)
-#define SYSTIMER_DATE_V  0xFFFFFFFFU
-#define SYSTIMER_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif

components/soc/esp32p4/include/soc/sys_timer_struct.h

@@ -1,682 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: SYSTEM TIMER CLK CONTROL REGISTER */
-/** Type of conf register
- *  Configure system timer clock
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:1;
-        /** etm_en : R/W; bitpos: [1]; default: 0;
-         *  enable systimer's etm task and event
-         */
-        uint32_t etm_en:1;
-        uint32_t reserved_2:20;
-        /** target2_work_en : R/W; bitpos: [22]; default: 0;
-         *  target2 work enable
-         */
-        uint32_t target2_work_en:1;
-        /** target1_work_en : R/W; bitpos: [23]; default: 0;
-         *  target1 work enable
-         */
-        uint32_t target1_work_en:1;
-        /** target0_work_en : R/W; bitpos: [24]; default: 0;
-         *  target0 work enable
-         */
-        uint32_t target0_work_en:1;
-        /** timer_unit1_core1_stall_en : R/W; bitpos: [25]; default: 1;
-         *  If timer unit1 is stalled when core1 stalled
-         */
-        uint32_t timer_unit1_core1_stall_en:1;
-        /** timer_unit1_core0_stall_en : R/W; bitpos: [26]; default: 1;
-         *  If timer unit1 is stalled when core0 stalled
-         */
-        uint32_t timer_unit1_core0_stall_en:1;
-        /** timer_unit0_core1_stall_en : R/W; bitpos: [27]; default: 0;
-         *  If timer unit0 is stalled when core1 stalled
-         */
-        uint32_t timer_unit0_core1_stall_en:1;
-        /** timer_unit0_core0_stall_en : R/W; bitpos: [28]; default: 0;
-         *  If timer unit0 is stalled when core0 stalled
-         */
-        uint32_t timer_unit0_core0_stall_en:1;
-        /** timer_unit1_work_en : R/W; bitpos: [29]; default: 0;
-         *  timer unit1 work enable
-         */
-        uint32_t timer_unit1_work_en:1;
-        /** timer_unit0_work_en : R/W; bitpos: [30]; default: 1;
-         *  timer unit0 work enable
-         */
-        uint32_t timer_unit0_work_en:1;
-        /** clk_en : R/W; bitpos: [31]; default: 0;
-         *  register file clk gating
-         */
-        uint32_t clk_en:1;
-    };
-    uint32_t val;
-} systimer_conf_reg_t;
-
-
-/** Group: SYSTEM TIMER UNIT0 CONTROL AND CONFIGURATION REGISTER */
-/** Type of unit0_op register
- *  system timer unit0 value update register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:29;
-        /** timer_unit0_value_valid : R/SS/WTC; bitpos: [29]; default: 0;
-         *  timer value is sync and valid
-         */
-        uint32_t timer_unit0_value_valid:1;
-        /** timer_unit0_update : WT; bitpos: [30]; default: 0;
-         *  update timer_unit0
-         */
-        uint32_t timer_unit0_update:1;
-        uint32_t reserved_31:1;
-    };
-    uint32_t val;
-} systimer_unit0_op_reg_t;
-
-/** Type of unit0_load_hi register
- *  system timer unit0 value high load register
- */
-typedef union {
-    struct {
-        /** timer_unit0_load_hi : R/W; bitpos: [19:0]; default: 0;
-         *  timer unit0 load high 20 bits
-         */
-        uint32_t timer_unit0_load_hi:20;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} systimer_unit0_load_hi_reg_t;
-
-/** Type of unit0_load_lo register
- *  system timer unit0 value low load register
- */
-typedef union {
-    struct {
-        /** timer_unit0_load_lo : R/W; bitpos: [31:0]; default: 0;
-         *  timer unit0 load low 32 bits
-         */
-        uint32_t timer_unit0_load_lo:32;
-    };
-    uint32_t val;
-} systimer_unit0_load_lo_reg_t;
-
-/** Type of unit0_value_hi register
- *  system timer unit0 value high register
- */
-typedef union {
-    struct {
-        /** timer_unit0_value_hi : RO; bitpos: [19:0]; default: 0;
-         *  timer read value high 20bits
-         */
-        uint32_t timer_unit0_value_hi:20;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} systimer_unit0_value_hi_reg_t;
-
-/** Type of unit0_value_lo register
- *  system timer unit0 value low register
- */
-typedef union {
-    struct {
-        /** timer_unit0_value_lo : RO; bitpos: [31:0]; default: 0;
-         *  timer read value low 32bits
-         */
-        uint32_t timer_unit0_value_lo:32;
-    };
-    uint32_t val;
-} systimer_unit0_value_lo_reg_t;
-
-/** Type of unit0_load register
- *  system timer unit0 conf sync register
- */
-typedef union {
-    struct {
-        /** timer_unit0_load : WT; bitpos: [0]; default: 0;
-         *  timer unit0 sync enable signal
-         */
-        uint32_t timer_unit0_load:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} systimer_unit0_load_reg_t;
-
-
-/** Group: SYSTEM TIMER UNIT1 CONTROL AND CONFIGURATION REGISTER */
-/** Type of unit1_op register
- *  system timer unit1 value update register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:29;
-        /** timer_unit1_value_valid : R/SS/WTC; bitpos: [29]; default: 0;
-         *  timer value is sync and valid
-         */
-        uint32_t timer_unit1_value_valid:1;
-        /** timer_unit1_update : WT; bitpos: [30]; default: 0;
-         *  update timer unit1
-         */
-        uint32_t timer_unit1_update:1;
-        uint32_t reserved_31:1;
-    };
-    uint32_t val;
-} systimer_unit1_op_reg_t;
-
-/** Type of unit1_load_hi register
- *  system timer unit1 value high load register
- */
-typedef union {
-    struct {
-        /** timer_unit1_load_hi : R/W; bitpos: [19:0]; default: 0;
-         *  timer unit1 load high 20 bits
-         */
-        uint32_t timer_unit1_load_hi:20;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} systimer_unit1_load_hi_reg_t;
-
-/** Type of unit1_load_lo register
- *  system timer unit1 value low load register
- */
-typedef union {
-    struct {
-        /** timer_unit1_load_lo : R/W; bitpos: [31:0]; default: 0;
-         *  timer unit1 load low 32 bits
-         */
-        uint32_t timer_unit1_load_lo:32;
-    };
-    uint32_t val;
-} systimer_unit1_load_lo_reg_t;
-
-/** Type of unit1_value_hi register
- *  system timer unit1 value high register
- */
-typedef union {
-    struct {
-        /** timer_unit1_value_hi : RO; bitpos: [19:0]; default: 0;
-         *  timer read value high 20bits
-         */
-        uint32_t timer_unit1_value_hi:20;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} systimer_unit1_value_hi_reg_t;
-
-/** Type of unit1_value_lo register
- *  system timer unit1 value low register
- */
-typedef union {
-    struct {
-        /** timer_unit1_value_lo : RO; bitpos: [31:0]; default: 0;
-         *  timer read value low 32bits
-         */
-        uint32_t timer_unit1_value_lo:32;
-    };
-    uint32_t val;
-} systimer_unit1_value_lo_reg_t;
-
-/** Type of unit1_load register
- *  system timer unit1 conf sync register
- */
-typedef union {
-    struct {
-        /** timer_unit1_load : WT; bitpos: [0]; default: 0;
-         *  timer unit1 sync enable signal
-         */
-        uint32_t timer_unit1_load:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} systimer_unit1_load_reg_t;
-
-
-/** Group: SYSTEM TIMER COMP0 CONTROL AND CONFIGURATION REGISTER */
-/** Type of target0_hi register
- *  system timer comp0 value high register
- */
-typedef union {
-    struct {
-        /** timer_target0_hi : R/W; bitpos: [19:0]; default: 0;
-         *  timer taget0 high 20 bits
-         */
-        uint32_t timer_target0_hi:20;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} systimer_target0_hi_reg_t;
-
-/** Type of target0_lo register
- *  system timer comp0 value low register
- */
-typedef union {
-    struct {
-        /** timer_target0_lo : R/W; bitpos: [31:0]; default: 0;
-         *  timer taget0 low 32 bits
-         */
-        uint32_t timer_target0_lo:32;
-    };
-    uint32_t val;
-} systimer_target0_lo_reg_t;
-
-/** Type of target0_conf register
- *  system timer comp0 target mode register
- */
-typedef union {
-    struct {
-        /** target0_period : R/W; bitpos: [25:0]; default: 0;
-         *  target0 period
-         */
-        uint32_t target0_period:26;
-        uint32_t reserved_26:4;
-        /** target0_period_mode : R/W; bitpos: [30]; default: 0;
-         *  Set target0 to period mode
-         */
-        uint32_t target0_period_mode:1;
-        /** target0_timer_unit_sel : R/W; bitpos: [31]; default: 0;
-         *  select which unit to compare
-         */
-        uint32_t target0_timer_unit_sel:1;
-    };
-    uint32_t val;
-} systimer_target0_conf_reg_t;
-
-/** Type of comp0_load register
- *  system timer comp0 conf sync register
- */
-typedef union {
-    struct {
-        /** timer_comp0_load : WT; bitpos: [0]; default: 0;
-         *  timer comp0 sync enable signal
-         */
-        uint32_t timer_comp0_load:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} systimer_comp0_load_reg_t;
-
-
-/** Group: SYSTEM TIMER COMP1 CONTROL AND CONFIGURATION REGISTER */
-/** Type of target1_hi register
- *  system timer comp1 value high register
- */
-typedef union {
-    struct {
-        /** timer_target1_hi : R/W; bitpos: [19:0]; default: 0;
-         *  timer taget1 high 20 bits
-         */
-        uint32_t timer_target1_hi:20;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} systimer_target1_hi_reg_t;
-
-/** Type of target1_lo register
- *  system timer comp1 value low register
- */
-typedef union {
-    struct {
-        /** timer_target1_lo : R/W; bitpos: [31:0]; default: 0;
-         *  timer taget1 low 32 bits
-         */
-        uint32_t timer_target1_lo:32;
-    };
-    uint32_t val;
-} systimer_target1_lo_reg_t;
-
-/** Type of target1_conf register
- *  system timer comp1 target mode register
- */
-typedef union {
-    struct {
-        /** target1_period : R/W; bitpos: [25:0]; default: 0;
-         *  target1 period
-         */
-        uint32_t target1_period:26;
-        uint32_t reserved_26:4;
-        /** target1_period_mode : R/W; bitpos: [30]; default: 0;
-         *  Set target1 to period mode
-         */
-        uint32_t target1_period_mode:1;
-        /** target1_timer_unit_sel : R/W; bitpos: [31]; default: 0;
-         *  select which unit to compare
-         */
-        uint32_t target1_timer_unit_sel:1;
-    };
-    uint32_t val;
-} systimer_target1_conf_reg_t;
-
-/** Type of comp1_load register
- *  system timer comp1 conf sync register
- */
-typedef union {
-    struct {
-        /** timer_comp1_load : WT; bitpos: [0]; default: 0;
-         *  timer comp1 sync enable signal
-         */
-        uint32_t timer_comp1_load:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} systimer_comp1_load_reg_t;
-
-
-/** Group: SYSTEM TIMER COMP2 CONTROL AND CONFIGURATION REGISTER */
-/** Type of target2_hi register
- *  system timer comp2 value high register
- */
-typedef union {
-    struct {
-        /** timer_target2_hi : R/W; bitpos: [19:0]; default: 0;
-         *  timer taget2 high 20 bits
-         */
-        uint32_t timer_target2_hi:20;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} systimer_target2_hi_reg_t;
-
-/** Type of target2_lo register
- *  system timer comp2 value low register
- */
-typedef union {
-    struct {
-        /** timer_target2_lo : R/W; bitpos: [31:0]; default: 0;
-         *  timer taget2 low 32 bits
-         */
-        uint32_t timer_target2_lo:32;
-    };
-    uint32_t val;
-} systimer_target2_lo_reg_t;
-
-/** Type of target2_conf register
- *  system timer comp2 target mode register
- */
-typedef union {
-    struct {
-        /** target2_period : R/W; bitpos: [25:0]; default: 0;
-         *  target2 period
-         */
-        uint32_t target2_period:26;
-        uint32_t reserved_26:4;
-        /** target2_period_mode : R/W; bitpos: [30]; default: 0;
-         *  Set target2 to period mode
-         */
-        uint32_t target2_period_mode:1;
-        /** target2_timer_unit_sel : R/W; bitpos: [31]; default: 0;
-         *  select which unit to compare
-         */
-        uint32_t target2_timer_unit_sel:1;
-    };
-    uint32_t val;
-} systimer_target2_conf_reg_t;
-
-/** Type of comp2_load register
- *  system timer comp2 conf sync register
- */
-typedef union {
-    struct {
-        /** timer_comp2_load : WT; bitpos: [0]; default: 0;
-         *  timer comp2 sync enable signal
-         */
-        uint32_t timer_comp2_load:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} systimer_comp2_load_reg_t;
-
-
-/** Group: SYSTEM TIMER INTERRUPT REGISTER */
-/** Type of int_ena register
- *  systimer interrupt enable register
- */
-typedef union {
-    struct {
-        /** target0_int_ena : R/W; bitpos: [0]; default: 0;
-         *  interupt0 enable
-         */
-        uint32_t target0_int_ena:1;
-        /** target1_int_ena : R/W; bitpos: [1]; default: 0;
-         *  interupt1 enable
-         */
-        uint32_t target1_int_ena:1;
-        /** target2_int_ena : R/W; bitpos: [2]; default: 0;
-         *  interupt2 enable
-         */
-        uint32_t target2_int_ena:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} systimer_int_ena_reg_t;
-
-/** Type of int_raw register
- *  systimer interrupt raw register
- */
-typedef union {
-    struct {
-        /** target0_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
-         *  interupt0 raw
-         */
-        uint32_t target0_int_raw:1;
-        /** target1_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
-         *  interupt1 raw
-         */
-        uint32_t target1_int_raw:1;
-        /** target2_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
-         *  interupt2 raw
-         */
-        uint32_t target2_int_raw:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} systimer_int_raw_reg_t;
-
-/** Type of int_clr register
- *  systimer interrupt clear register
- */
-typedef union {
-    struct {
-        /** target0_int_clr : WT; bitpos: [0]; default: 0;
-         *  interupt0 clear
-         */
-        uint32_t target0_int_clr:1;
-        /** target1_int_clr : WT; bitpos: [1]; default: 0;
-         *  interupt1 clear
-         */
-        uint32_t target1_int_clr:1;
-        /** target2_int_clr : WT; bitpos: [2]; default: 0;
-         *  interupt2 clear
-         */
-        uint32_t target2_int_clr:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} systimer_int_clr_reg_t;
-
-/** Type of int_st register
- *  systimer interrupt status register
- */
-typedef union {
-    struct {
-        /** target0_int_st : RO; bitpos: [0]; default: 0;
-         *  interupt0 status
-         */
-        uint32_t target0_int_st:1;
-        /** target1_int_st : RO; bitpos: [1]; default: 0;
-         *  interupt1 status
-         */
-        uint32_t target1_int_st:1;
-        /** target2_int_st : RO; bitpos: [2]; default: 0;
-         *  interupt2 status
-         */
-        uint32_t target2_int_st:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} systimer_int_st_reg_t;
-
-
-/** Group: SYSTEM TIMER COMP0 STATUS REGISTER */
-/** Type of real_target0_lo register
- *  system timer comp0 actual target value low register
- */
-typedef union {
-    struct {
-        /** target0_lo_ro : RO; bitpos: [31:0]; default: 0;
-         *  actual target value value low 32bits
-         */
-        uint32_t target0_lo_ro:32;
-    };
-    uint32_t val;
-} systimer_real_target0_lo_reg_t;
-
-/** Type of real_target0_hi register
- *  system timer comp0 actual target value high register
- */
-typedef union {
-    struct {
-        /** target0_hi_ro : RO; bitpos: [19:0]; default: 0;
-         *  actual target value value high 20bits
-         */
-        uint32_t target0_hi_ro:20;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} systimer_real_target0_hi_reg_t;
-
-
-/** Group: SYSTEM TIMER COMP1 STATUS REGISTER */
-/** Type of real_target1_lo register
- *  system timer comp1 actual target value low register
- */
-typedef union {
-    struct {
-        /** target1_lo_ro : RO; bitpos: [31:0]; default: 0;
-         *  actual target value value low 32bits
-         */
-        uint32_t target1_lo_ro:32;
-    };
-    uint32_t val;
-} systimer_real_target1_lo_reg_t;
-
-/** Type of real_target1_hi register
- *  system timer comp1 actual target value high register
- */
-typedef union {
-    struct {
-        /** target1_hi_ro : RO; bitpos: [19:0]; default: 0;
-         *  actual target value value high 20bits
-         */
-        uint32_t target1_hi_ro:20;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} systimer_real_target1_hi_reg_t;
-
-
-/** Group: SYSTEM TIMER COMP2 STATUS REGISTER */
-/** Type of real_target2_lo register
- *  system timer comp2 actual target value low register
- */
-typedef union {
-    struct {
-        /** target2_lo_ro : RO; bitpos: [31:0]; default: 0;
-         *  actual target value value low 32bits
-         */
-        uint32_t target2_lo_ro:32;
-    };
-    uint32_t val;
-} systimer_real_target2_lo_reg_t;
-
-/** Type of real_target2_hi register
- *  system timer comp2 actual target value high register
- */
-typedef union {
-    struct {
-        /** target2_hi_ro : RO; bitpos: [19:0]; default: 0;
-         *  actual target value value high 20bits
-         */
-        uint32_t target2_hi_ro:20;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} systimer_real_target2_hi_reg_t;
-
-
-/** Group: VERSION REGISTER */
-/** Type of date register
- *  system timer version control register
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [31:0]; default: 35655795;
-         *  systimer register version
-         */
-        uint32_t date:32;
-    };
-    uint32_t val;
-} systimer_date_reg_t;
-
-
-typedef struct {
-    volatile systimer_conf_reg_t conf;
-    volatile systimer_unit0_op_reg_t unit0_op;
-    volatile systimer_unit1_op_reg_t unit1_op;
-    volatile systimer_unit0_load_hi_reg_t unit0_load_hi;
-    volatile systimer_unit0_load_lo_reg_t unit0_load_lo;
-    volatile systimer_unit1_load_hi_reg_t unit1_load_hi;
-    volatile systimer_unit1_load_lo_reg_t unit1_load_lo;
-    volatile systimer_target0_hi_reg_t target0_hi;
-    volatile systimer_target0_lo_reg_t target0_lo;
-    volatile systimer_target1_hi_reg_t target1_hi;
-    volatile systimer_target1_lo_reg_t target1_lo;
-    volatile systimer_target2_hi_reg_t target2_hi;
-    volatile systimer_target2_lo_reg_t target2_lo;
-    volatile systimer_target0_conf_reg_t target0_conf;
-    volatile systimer_target1_conf_reg_t target1_conf;
-    volatile systimer_target2_conf_reg_t target2_conf;
-    volatile systimer_unit0_value_hi_reg_t unit0_value_hi;
-    volatile systimer_unit0_value_lo_reg_t unit0_value_lo;
-    volatile systimer_unit1_value_hi_reg_t unit1_value_hi;
-    volatile systimer_unit1_value_lo_reg_t unit1_value_lo;
-    volatile systimer_comp0_load_reg_t comp0_load;
-    volatile systimer_comp1_load_reg_t comp1_load;
-    volatile systimer_comp2_load_reg_t comp2_load;
-    volatile systimer_unit0_load_reg_t unit0_load;
-    volatile systimer_unit1_load_reg_t unit1_load;
-    volatile systimer_int_ena_reg_t int_ena;
-    volatile systimer_int_raw_reg_t int_raw;
-    volatile systimer_int_clr_reg_t int_clr;
-    volatile systimer_int_st_reg_t int_st;
-    volatile systimer_real_target0_lo_reg_t real_target0_lo;
-    volatile systimer_real_target0_hi_reg_t real_target0_hi;
-    volatile systimer_real_target1_lo_reg_t real_target1_lo;
-    volatile systimer_real_target1_hi_reg_t real_target1_hi;
-    volatile systimer_real_target2_lo_reg_t real_target2_lo;
-    volatile systimer_real_target2_hi_reg_t real_target2_hi;
-    uint32_t reserved_08c[28];
-    volatile systimer_date_reg_t date;
-} systimer_dev_t;
-
-
-#ifndef __cplusplus
-_Static_assert(sizeof(systimer_dev_t) == 0x100, "Invalid size of systimer_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif

components/soc/esp32p4/include/soc/timers_reg.h → components/soc/esp32p4/include/soc/timer_group_reg.h

@@ -14,7 +14,7 @@ extern "C" {
 /** TIMG_T0CONFIG_REG register
  *  Timer 0 configuration register
  */
-#define TIMG_T0CONFIG_REG (DR_REG_TIMG_BASE + 0x0)
+#define TIMG_T0CONFIG_REG(i) (REG_TIMG_BASE(i) + 0x0)
 /** TIMG_T0_ALARM_EN : R/W/SC; bitpos: [10]; default: 0;
  *  When set, the alarm is enabled. This bit is automatically cleared once an
  *  alarm occurs.
@@ -63,7 +63,7 @@ extern "C" {
 /** TIMG_T0LO_REG register
  *  Timer 0 current value, low 32 bits
  */
-#define TIMG_T0LO_REG (DR_REG_TIMG_BASE + 0x4)
+#define TIMG_T0LO_REG(i) (REG_TIMG_BASE(i) + 0x4)
 /** TIMG_T0_LO : RO; bitpos: [31:0]; default: 0;
  *  After writing to TIMG_T0UPDATE_REG, the low 32 bits of the time-base counter
  *  of timer 0 can be read here.
@@ -76,7 +76,7 @@ extern "C" {
 /** TIMG_T0HI_REG register
  *  Timer 0 current value, high 22 bits
  */
-#define TIMG_T0HI_REG (DR_REG_TIMG_BASE + 0x8)
+#define TIMG_T0HI_REG(i) (REG_TIMG_BASE(i) + 0x8)
 /** TIMG_T0_HI : RO; bitpos: [21:0]; default: 0;
  *  After writing to TIMG_T0UPDATE_REG, the high 22 bits of the time-base counter
  *  of timer 0 can be read here.
@@ -89,7 +89,7 @@ extern "C" {
 /** TIMG_T0UPDATE_REG register
  *  Write to copy current timer value to TIMGn_T0_(LO/HI)_REG
  */
-#define TIMG_T0UPDATE_REG (DR_REG_TIMG_BASE + 0xc)
+#define TIMG_T0UPDATE_REG(i) (REG_TIMG_BASE(i) + 0xc)
 /** TIMG_T0_UPDATE : R/W/SC; bitpos: [31]; default: 0;
  *  After writing 0 or 1 to TIMG_T0UPDATE_REG, the counter value is latched.
  */
@@ -101,7 +101,7 @@ extern "C" {
 /** TIMG_T0ALARMLO_REG register
  *  Timer 0 alarm value, low 32 bits
  */
-#define TIMG_T0ALARMLO_REG (DR_REG_TIMG_BASE + 0x10)
+#define TIMG_T0ALARMLO_REG(i) (REG_TIMG_BASE(i) + 0x10)
 /** TIMG_T0_ALARM_LO : R/W; bitpos: [31:0]; default: 0;
  *  Timer 0 alarm trigger time-base counter value, low 32 bits.
  */
@@ -113,7 +113,7 @@ extern "C" {
 /** TIMG_T0ALARMHI_REG register
  *  Timer 0 alarm value, high bits
  */
-#define TIMG_T0ALARMHI_REG (DR_REG_TIMG_BASE + 0x14)
+#define TIMG_T0ALARMHI_REG(i) (REG_TIMG_BASE(i) + 0x14)
 /** TIMG_T0_ALARM_HI : R/W; bitpos: [21:0]; default: 0;
  *  Timer 0 alarm trigger time-base counter value, high 22 bits.
  */
@@ -125,7 +125,7 @@ extern "C" {
 /** TIMG_T0LOADLO_REG register
  *  Timer 0 reload value, low 32 bits
  */
-#define TIMG_T0LOADLO_REG (DR_REG_TIMG_BASE + 0x18)
+#define TIMG_T0LOADLO_REG(i) (REG_TIMG_BASE(i) + 0x18)
 /** TIMG_T0_LOAD_LO : R/W; bitpos: [31:0]; default: 0;
  *  Low 32 bits of the value that a reload will load onto timer 0 time-base
  *  Counter.
@@ -138,7 +138,7 @@ extern "C" {
 /** TIMG_T0LOADHI_REG register
  *  Timer 0 reload value, high 22 bits
  */
-#define TIMG_T0LOADHI_REG (DR_REG_TIMG_BASE + 0x1c)
+#define TIMG_T0LOADHI_REG(i) (REG_TIMG_BASE(i) + 0x1c)
 /** TIMG_T0_LOAD_HI : R/W; bitpos: [21:0]; default: 0;
  *  High 22 bits of the value that a reload will load onto timer 0 time-base
  *  counter.
@@ -151,7 +151,7 @@ extern "C" {
 /** TIMG_T0LOAD_REG register
  *  Write to reload timer from TIMG_T0_(LOADLOLOADHI)_REG
  */
-#define TIMG_T0LOAD_REG (DR_REG_TIMG_BASE + 0x20)
+#define TIMG_T0LOAD_REG(i) (REG_TIMG_BASE(i) + 0x20)
 /** TIMG_T0_LOAD : WT; bitpos: [31:0]; default: 0;
  *
  *  Write any value to trigger a timer 0 time-base counter reload.
@@ -164,7 +164,7 @@ extern "C" {
 /** TIMG_T1CONFIG_REG register
  *  Timer 1 configuration register
  */
-#define TIMG_T1CONFIG_REG (DR_REG_TIMG_BASE + 0x24)
+#define TIMG_T1CONFIG_REG(i) (REG_TIMG_BASE(i) + 0x24)
 /** TIMG_T1_ALARM_EN : R/W/SC; bitpos: [10]; default: 0;
  *  When set, the alarm is enabled. This bit is automatically cleared once an
  *  alarm occurs.
@@ -213,7 +213,7 @@ extern "C" {
 /** TIMG_T1LO_REG register
  *  Timer 1 current value, low 32 bits
  */
-#define TIMG_T1LO_REG (DR_REG_TIMG_BASE + 0x28)
+#define TIMG_T1LO_REG(i) (REG_TIMG_BASE(i) + 0x28)
 /** TIMG_T1_LO : RO; bitpos: [31:0]; default: 0;
  *  After writing to TIMG_T1UPDATE_REG, the low 32 bits of the time-base counter
  *  of timer 1 can be read here.
@@ -226,7 +226,7 @@ extern "C" {
 /** TIMG_T1HI_REG register
  *  Timer 1 current value, high 22 bits
  */
-#define TIMG_T1HI_REG (DR_REG_TIMG_BASE + 0x2c)
+#define TIMG_T1HI_REG(i) (REG_TIMG_BASE(i) + 0x2c)
 /** TIMG_T1_HI : RO; bitpos: [21:0]; default: 0;
  *  After writing to TIMG_T1UPDATE_REG, the high 22 bits of the time-base counter
  *  of timer 1 can be read here.
@@ -239,7 +239,7 @@ extern "C" {
 /** TIMG_T1UPDATE_REG register
  *  Write to copy current timer value to TIMGn_T1_(LO/HI)_REG
  */
-#define TIMG_T1UPDATE_REG (DR_REG_TIMG_BASE + 0x30)
+#define TIMG_T1UPDATE_REG(i) (REG_TIMG_BASE(i) + 0x30)
 /** TIMG_T1_UPDATE : R/W/SC; bitpos: [31]; default: 0;
  *  After writing 0 or 1 to TIMG_T1UPDATE_REG, the counter value is latched.
  */
@@ -251,7 +251,7 @@ extern "C" {
 /** TIMG_T1ALARMLO_REG register
  *  Timer 1 alarm value, low 32 bits
  */
-#define TIMG_T1ALARMLO_REG (DR_REG_TIMG_BASE + 0x34)
+#define TIMG_T1ALARMLO_REG(i) (REG_TIMG_BASE(i) + 0x34)
 /** TIMG_T1_ALARM_LO : R/W; bitpos: [31:0]; default: 0;
  *  Timer 1 alarm trigger time-base counter value, low 32 bits.
  */
@@ -263,7 +263,7 @@ extern "C" {
 /** TIMG_T1ALARMHI_REG register
  *  Timer 1 alarm value, high bits
  */
-#define TIMG_T1ALARMHI_REG (DR_REG_TIMG_BASE + 0x38)
+#define TIMG_T1ALARMHI_REG(i) (REG_TIMG_BASE(i) + 0x38)
 /** TIMG_T1_ALARM_HI : R/W; bitpos: [21:0]; default: 0;
  *  Timer 1 alarm trigger time-base counter value, high 22 bits.
  */
@@ -275,7 +275,7 @@ extern "C" {
 /** TIMG_T1LOADLO_REG register
  *  Timer 1 reload value, low 32 bits
  */
-#define TIMG_T1LOADLO_REG (DR_REG_TIMG_BASE + 0x3c)
+#define TIMG_T1LOADLO_REG(i) (REG_TIMG_BASE(i) + 0x3c)
 /** TIMG_T1_LOAD_LO : R/W; bitpos: [31:0]; default: 0;
  *  Low 32 bits of the value that a reload will load onto timer 1 time-base
  *  Counter.
@@ -288,7 +288,7 @@ extern "C" {
 /** TIMG_T1LOADHI_REG register
  *  Timer 1 reload value, high 22 bits
  */
-#define TIMG_T1LOADHI_REG (DR_REG_TIMG_BASE + 0x40)
+#define TIMG_T1LOADHI_REG(i) (REG_TIMG_BASE(i) + 0x40)
 /** TIMG_T1_LOAD_HI : R/W; bitpos: [21:0]; default: 0;
  *  High 22 bits of the value that a reload will load onto timer 1 time-base
  *  counter.
@@ -301,7 +301,7 @@ extern "C" {
 /** TIMG_T1LOAD_REG register
  *  Write to reload timer from TIMG_T1_(LOADLOLOADHI)_REG
  */
-#define TIMG_T1LOAD_REG (DR_REG_TIMG_BASE + 0x44)
+#define TIMG_T1LOAD_REG(i) (REG_TIMG_BASE(i) + 0x44)
 /** TIMG_T1_LOAD : WT; bitpos: [31:0]; default: 0;
  *
  *  Write any value to trigger a timer 1 time-base counter reload.
@@ -314,7 +314,7 @@ extern "C" {
 /** TIMG_WDTCONFIG0_REG register
  *  Watchdog timer configuration register
  */
-#define TIMG_WDTCONFIG0_REG (DR_REG_TIMG_BASE + 0x48)
+#define TIMG_WDTCONFIG0_REG(i) (REG_TIMG_BASE(i) + 0x48)
 /** TIMG_WDT_APPCPU_RESET_EN : R/W; bitpos: [12]; default: 0;
  *  WDT reset CPU enable.
  */
@@ -398,7 +398,7 @@ extern "C" {
 /** TIMG_WDTCONFIG1_REG register
  *  Watchdog timer prescaler register
  */
-#define TIMG_WDTCONFIG1_REG (DR_REG_TIMG_BASE + 0x4c)
+#define TIMG_WDTCONFIG1_REG(i) (REG_TIMG_BASE(i) + 0x4c)
 /** TIMG_WDT_DIVCNT_RST : WT; bitpos: [0]; default: 0;
  *  When set, WDT 's clock divider counter will be reset.
  */
@@ -418,7 +418,7 @@ extern "C" {
 /** TIMG_WDTCONFIG2_REG register
  *  Watchdog timer stage 0 timeout value
  */
-#define TIMG_WDTCONFIG2_REG (DR_REG_TIMG_BASE + 0x50)
+#define TIMG_WDTCONFIG2_REG(i) (REG_TIMG_BASE(i) + 0x50)
 /** TIMG_WDT_STG0_HOLD : R/W; bitpos: [31:0]; default: 26000000;
  *  Stage 0 timeout value, in MWDT clock cycles.
  */
@@ -430,7 +430,7 @@ extern "C" {
 /** TIMG_WDTCONFIG3_REG register
  *  Watchdog timer stage 1 timeout value
  */
-#define TIMG_WDTCONFIG3_REG (DR_REG_TIMG_BASE + 0x54)
+#define TIMG_WDTCONFIG3_REG(i) (REG_TIMG_BASE(i) + 0x54)
 /** TIMG_WDT_STG1_HOLD : R/W; bitpos: [31:0]; default: 134217727;
  *  Stage 1 timeout value, in MWDT clock cycles.
  */
@@ -442,7 +442,7 @@ extern "C" {
 /** TIMG_WDTCONFIG4_REG register
  *  Watchdog timer stage 2 timeout value
  */
-#define TIMG_WDTCONFIG4_REG (DR_REG_TIMG_BASE + 0x58)
+#define TIMG_WDTCONFIG4_REG(i) (REG_TIMG_BASE(i) + 0x58)
 /** TIMG_WDT_STG2_HOLD : R/W; bitpos: [31:0]; default: 1048575;
  *  Stage 2 timeout value, in MWDT clock cycles.
  */
@@ -454,7 +454,7 @@ extern "C" {
 /** TIMG_WDTCONFIG5_REG register
  *  Watchdog timer stage 3 timeout value
  */
-#define TIMG_WDTCONFIG5_REG (DR_REG_TIMG_BASE + 0x5c)
+#define TIMG_WDTCONFIG5_REG(i) (REG_TIMG_BASE(i) + 0x5c)
 /** TIMG_WDT_STG3_HOLD : R/W; bitpos: [31:0]; default: 1048575;
  *  Stage 3 timeout value, in MWDT clock cycles.
  */
@@ -466,7 +466,7 @@ extern "C" {
 /** TIMG_WDTFEED_REG register
  *  Write to feed the watchdog timer
  */
-#define TIMG_WDTFEED_REG (DR_REG_TIMG_BASE + 0x60)
+#define TIMG_WDTFEED_REG(i) (REG_TIMG_BASE(i) + 0x60)
 /** TIMG_WDT_FEED : WT; bitpos: [31:0]; default: 0;
  *  Write any value to feed the MWDT. (WO)
  */
@@ -478,7 +478,7 @@ extern "C" {
 /** TIMG_WDTWPROTECT_REG register
  *  Watchdog write protect register
  */
-#define TIMG_WDTWPROTECT_REG (DR_REG_TIMG_BASE + 0x64)
+#define TIMG_WDTWPROTECT_REG(i) (REG_TIMG_BASE(i) + 0x64)
 /** TIMG_WDT_WKEY : R/W; bitpos: [31:0]; default: 1356348065;
  *  If the register contains a different value than its reset value, write
  *  protection is enabled.
@@ -491,7 +491,7 @@ extern "C" {
 /** TIMG_RTCCALICFG_REG register
  *  RTC calibration configure register
  */
-#define TIMG_RTCCALICFG_REG (DR_REG_TIMG_BASE + 0x68)
+#define TIMG_RTCCALICFG_REG(i) (REG_TIMG_BASE(i) + 0x68)
 /** TIMG_RTC_CALI_START_CYCLING : R/W; bitpos: [12]; default: 1;
  *  0: one-shot frequency calculation,1: periodic frequency calculation,
  */
@@ -531,7 +531,7 @@ extern "C" {
 /** TIMG_RTCCALICFG1_REG register
  *  RTC calibration configure1 register
  */
-#define TIMG_RTCCALICFG1_REG (DR_REG_TIMG_BASE + 0x6c)
+#define TIMG_RTCCALICFG1_REG(i) (REG_TIMG_BASE(i) + 0x6c)
 /** TIMG_RTC_CALI_CYCLING_DATA_VLD : RO; bitpos: [0]; default: 0;
  *  indicate periodic frequency calculation is done.
  */
@@ -551,7 +551,7 @@ extern "C" {
 /** TIMG_INT_ENA_TIMERS_REG register
  *  Interrupt enable bits
  */
-#define TIMG_INT_ENA_TIMERS_REG (DR_REG_TIMG_BASE + 0x70)
+#define TIMG_INT_ENA_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x70)
 /** TIMG_T0_INT_ENA : R/W; bitpos: [0]; default: 0;
  *  The interrupt enable bit for the TIMG_T$x_INT interrupt.
  */
@@ -577,7 +577,7 @@ extern "C" {
 /** TIMG_INT_RAW_TIMERS_REG register
  *  Raw interrupt status
  */
-#define TIMG_INT_RAW_TIMERS_REG (DR_REG_TIMG_BASE + 0x74)
+#define TIMG_INT_RAW_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x74)
 /** TIMG_T0_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0;
  *  The raw interrupt status bit for the TIMG_T$x_INT interrupt.
  */
@@ -603,7 +603,7 @@ extern "C" {
 /** TIMG_INT_ST_TIMERS_REG register
  *  Masked interrupt status
  */
-#define TIMG_INT_ST_TIMERS_REG (DR_REG_TIMG_BASE + 0x78)
+#define TIMG_INT_ST_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x78)
 /** TIMG_T0_INT_ST : RO; bitpos: [0]; default: 0;
  *  The masked interrupt status bit for the TIMG_T$x_INT interrupt.
  */
@@ -629,7 +629,7 @@ extern "C" {
 /** TIMG_INT_CLR_TIMERS_REG register
  *  Interrupt clear bits
  */
-#define TIMG_INT_CLR_TIMERS_REG (DR_REG_TIMG_BASE + 0x7c)
+#define TIMG_INT_CLR_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x7c)
 /** TIMG_T0_INT_CLR : WT; bitpos: [0]; default: 0;
  *  Set this bit to clear the TIMG_T$x_INT interrupt.
  */
@@ -655,7 +655,7 @@ extern "C" {
 /** TIMG_RTCCALICFG2_REG register
  *  Timer group calibration register
  */
-#define TIMG_RTCCALICFG2_REG (DR_REG_TIMG_BASE + 0x80)
+#define TIMG_RTCCALICFG2_REG(i) (REG_TIMG_BASE(i) + 0x80)
 /** TIMG_RTC_CALI_TIMEOUT : RO; bitpos: [0]; default: 0;
  *  RTC calibration timeout indicator
  */
@@ -682,7 +682,7 @@ extern "C" {
 /** TIMG_NTIMERS_DATE_REG register
  *  Timer version control register
  */
-#define TIMG_NTIMERS_DATE_REG (DR_REG_TIMG_BASE + 0xf8)
+#define TIMG_NTIMERS_DATE_REG(i) (REG_TIMG_BASE(i) + 0xf8)
 /** TIMG_NTIMGS_DATE : R/W; bitpos: [27:0]; default: 35688770;
  *  Timer version control register
  */
@@ -694,7 +694,7 @@ extern "C" {
 /** TIMG_REGCLK_REG register
  *  Timer group clock gate register
  */
-#define TIMG_REGCLK_REG (DR_REG_TIMG_BASE + 0xfc)
+#define TIMG_REGCLK_REG(i) (REG_TIMG_BASE(i) + 0xfc)
 /** TIMG_ETM_EN : R/W; bitpos: [28]; default: 1;
  *  enable timer's etm task and event
  */

components/soc/esp32p4/include/soc/timers_struct.h → components/soc/esp32p4/include/soc/timer_group_struct.h

@@ -562,6 +562,8 @@ typedef struct {
     volatile timg_regclk_reg_t regclk;
 } timg_dev_t;
 
+extern timg_dev_t TIMERG0;
+extern timg_dev_t TIMERG1;
 
 #ifndef __cplusplus
 _Static_assert(sizeof(timg_dev_t) == 0x100, "Invalid size of timg_dev_t structure");

components/soc/esp32p4/include/soc/twai_reg.h

@@ -0,0 +1,791 @@
+/**
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** TWAI_MODE_REG register
+ *  TWAI mode register.
+ */
+#define TWAI_MODE_REG(i) (REG_TWAI_BASE(i) + 0x0)
+/** TWAI_RESET_MODE : R/W; bitpos: [0]; default: 1;
+ *  1: reset, detection of a set reset mode bit results in aborting the current
+ *  transmission/reception of a message and entering the reset mode. 0: normal, on the
+ *  '1-to-0' transition of the reset mode bit, the TWAI controller returns to the
+ *  operating mode.
+ */
+#define TWAI_RESET_MODE    (BIT(0))
+#define TWAI_RESET_MODE_M  (TWAI_RESET_MODE_V << TWAI_RESET_MODE_S)
+#define TWAI_RESET_MODE_V  0x00000001U
+#define TWAI_RESET_MODE_S  0
+/** TWAI_LISTEN_ONLY_MODE : R/W; bitpos: [1]; default: 0;
+ *  1: listen only, in this mode the TWAI controller would give no acknowledge to the
+ *  TWAI-bus, even if a message is received successfully. The error counters are
+ *  stopped at the current value. 0: normal.
+ */
+#define TWAI_LISTEN_ONLY_MODE    (BIT(1))
+#define TWAI_LISTEN_ONLY_MODE_M  (TWAI_LISTEN_ONLY_MODE_V << TWAI_LISTEN_ONLY_MODE_S)
+#define TWAI_LISTEN_ONLY_MODE_V  0x00000001U
+#define TWAI_LISTEN_ONLY_MODE_S  1
+/** TWAI_SELF_TEST_MODE : R/W; bitpos: [2]; default: 0;
+ *  1: self test, in this mode a full node test is possible without any other active
+ *  node on the bus using the self reception request command. The TWAI controller will
+ *  perform a successful transmission, even if there is no acknowledge received. 0:
+ *  normal, an acknowledge is required for successful transmission.
+ */
+#define TWAI_SELF_TEST_MODE    (BIT(2))
+#define TWAI_SELF_TEST_MODE_M  (TWAI_SELF_TEST_MODE_V << TWAI_SELF_TEST_MODE_S)
+#define TWAI_SELF_TEST_MODE_V  0x00000001U
+#define TWAI_SELF_TEST_MODE_S  2
+/** TWAI_ACCEPTANCE_FILTER_MODE : R/W; bitpos: [3]; default: 0;
+ *  1:single, the single acceptance filter option is enabled (one filter with the
+ *  length of 32 bit is active). 0:dual, the dual acceptance filter option is enabled
+ *  (two filters, each with the length of 16 bit are active).
+ */
+#define TWAI_ACCEPTANCE_FILTER_MODE    (BIT(3))
+#define TWAI_ACCEPTANCE_FILTER_MODE_M  (TWAI_ACCEPTANCE_FILTER_MODE_V << TWAI_ACCEPTANCE_FILTER_MODE_S)
+#define TWAI_ACCEPTANCE_FILTER_MODE_V  0x00000001U
+#define TWAI_ACCEPTANCE_FILTER_MODE_S  3
+
+/** TWAI_CMD_REG register
+ *  TWAI command register.
+ */
+#define TWAI_CMD_REG(i) (REG_TWAI_BASE(i) + 0x4)
+/** TWAI_TX_REQUEST : WO; bitpos: [0]; default: 0;
+ *  1: present, a message shall be transmitted. 0: absent
+ */
+#define TWAI_TX_REQUEST    (BIT(0))
+#define TWAI_TX_REQUEST_M  (TWAI_TX_REQUEST_V << TWAI_TX_REQUEST_S)
+#define TWAI_TX_REQUEST_V  0x00000001U
+#define TWAI_TX_REQUEST_S  0
+/** TWAI_ABORT_TX : WO; bitpos: [1]; default: 0;
+ *  1: present, if not already in progress, a pending transmission request is
+ *  cancelled. 0: absent
+ */
+#define TWAI_ABORT_TX    (BIT(1))
+#define TWAI_ABORT_TX_M  (TWAI_ABORT_TX_V << TWAI_ABORT_TX_S)
+#define TWAI_ABORT_TX_V  0x00000001U
+#define TWAI_ABORT_TX_S  1
+/** TWAI_RELEASE_BUFFER : WO; bitpos: [2]; default: 0;
+ *  1: released, the receive buffer, representing the message memory space in the
+ *  RXFIFO is released. 0: no action
+ */
+#define TWAI_RELEASE_BUFFER    (BIT(2))
+#define TWAI_RELEASE_BUFFER_M  (TWAI_RELEASE_BUFFER_V << TWAI_RELEASE_BUFFER_S)
+#define TWAI_RELEASE_BUFFER_V  0x00000001U
+#define TWAI_RELEASE_BUFFER_S  2
+/** TWAI_CLEAR_DATA_OVERRUN : WO; bitpos: [3]; default: 0;
+ *  1: clear, the data overrun status bit is cleared. 0: no action.
+ */
+#define TWAI_CLEAR_DATA_OVERRUN    (BIT(3))
+#define TWAI_CLEAR_DATA_OVERRUN_M  (TWAI_CLEAR_DATA_OVERRUN_V << TWAI_CLEAR_DATA_OVERRUN_S)
+#define TWAI_CLEAR_DATA_OVERRUN_V  0x00000001U
+#define TWAI_CLEAR_DATA_OVERRUN_S  3
+/** TWAI_SELF_RX_REQUEST : WO; bitpos: [4]; default: 0;
+ *  1: present, a message shall be transmitted and received simultaneously. 0: absent.
+ */
+#define TWAI_SELF_RX_REQUEST    (BIT(4))
+#define TWAI_SELF_RX_REQUEST_M  (TWAI_SELF_RX_REQUEST_V << TWAI_SELF_RX_REQUEST_S)
+#define TWAI_SELF_RX_REQUEST_V  0x00000001U
+#define TWAI_SELF_RX_REQUEST_S  4
+
+/** TWAI_STATUS_REG register
+ *  TWAI status register.
+ */
+#define TWAI_STATUS_REG(i) (REG_TWAI_BASE(i) + 0x8)
+/** TWAI_STATUS_RECEIVE_BUFFER : RO; bitpos: [0]; default: 0;
+ *  1: full, one or more complete messages are available in the RXFIFO. 0: empty, no
+ *  message is available
+ */
+#define TWAI_STATUS_RECEIVE_BUFFER    (BIT(0))
+#define TWAI_STATUS_RECEIVE_BUFFER_M  (TWAI_STATUS_RECEIVE_BUFFER_V << TWAI_STATUS_RECEIVE_BUFFER_S)
+#define TWAI_STATUS_RECEIVE_BUFFER_V  0x00000001U
+#define TWAI_STATUS_RECEIVE_BUFFER_S  0
+/** TWAI_STATUS_OVERRUN : RO; bitpos: [1]; default: 0;
+ *  1: overrun, a message was lost because there was not enough space for that message
+ *  in the RXFIFO. 0: absent, no data overrun has occurred since the last clear data
+ *  overrun command was given
+ */
+#define TWAI_STATUS_OVERRUN    (BIT(1))
+#define TWAI_STATUS_OVERRUN_M  (TWAI_STATUS_OVERRUN_V << TWAI_STATUS_OVERRUN_S)
+#define TWAI_STATUS_OVERRUN_V  0x00000001U
+#define TWAI_STATUS_OVERRUN_S  1
+/** TWAI_STATUS_TRANSMIT_BUFFER : RO; bitpos: [2]; default: 0;
+ *  1: released, the CPU may write a message into the transmit buffer. 0: locked, the
+ *  CPU cannot access the transmit buffer, a message is either waiting for transmission
+ *  or is in the process of being transmitted
+ */
+#define TWAI_STATUS_TRANSMIT_BUFFER    (BIT(2))
+#define TWAI_STATUS_TRANSMIT_BUFFER_M  (TWAI_STATUS_TRANSMIT_BUFFER_V << TWAI_STATUS_TRANSMIT_BUFFER_S)
+#define TWAI_STATUS_TRANSMIT_BUFFER_V  0x00000001U
+#define TWAI_STATUS_TRANSMIT_BUFFER_S  2
+/** TWAI_STATUS_TRANSMISSION_COMPLETE : RO; bitpos: [3]; default: 0;
+ *  1: complete, last requested transmission has been successfully completed. 0:
+ *  incomplete, previously requested transmission is not yet completed
+ */
+#define TWAI_STATUS_TRANSMISSION_COMPLETE    (BIT(3))
+#define TWAI_STATUS_TRANSMISSION_COMPLETE_M  (TWAI_STATUS_TRANSMISSION_COMPLETE_V << TWAI_STATUS_TRANSMISSION_COMPLETE_S)
+#define TWAI_STATUS_TRANSMISSION_COMPLETE_V  0x00000001U
+#define TWAI_STATUS_TRANSMISSION_COMPLETE_S  3
+/** TWAI_STATUS_RECEIVE : RO; bitpos: [4]; default: 0;
+ *  1: receive, the TWAI controller is receiving a message. 0: idle
+ */
+#define TWAI_STATUS_RECEIVE    (BIT(4))
+#define TWAI_STATUS_RECEIVE_M  (TWAI_STATUS_RECEIVE_V << TWAI_STATUS_RECEIVE_S)
+#define TWAI_STATUS_RECEIVE_V  0x00000001U
+#define TWAI_STATUS_RECEIVE_S  4
+/** TWAI_STATUS_TRANSMIT : RO; bitpos: [5]; default: 0;
+ *  1: transmit, the TWAI controller is transmitting a message. 0: idle
+ */
+#define TWAI_STATUS_TRANSMIT    (BIT(5))
+#define TWAI_STATUS_TRANSMIT_M  (TWAI_STATUS_TRANSMIT_V << TWAI_STATUS_TRANSMIT_S)
+#define TWAI_STATUS_TRANSMIT_V  0x00000001U
+#define TWAI_STATUS_TRANSMIT_S  5
+/** TWAI_STATUS_ERR : RO; bitpos: [6]; default: 0;
+ *  1: error, at least one of the error counters has reached or exceeded the CPU
+ *  warning limit defined by the Error Warning Limit Register (EWLR). 0: ok, both error
+ *  counters are below the warning limit
+ */
+#define TWAI_STATUS_ERR    (BIT(6))
+#define TWAI_STATUS_ERR_M  (TWAI_STATUS_ERR_V << TWAI_STATUS_ERR_S)
+#define TWAI_STATUS_ERR_V  0x00000001U
+#define TWAI_STATUS_ERR_S  6
+/** TWAI_STATUS_NODE_BUS_OFF : RO; bitpos: [7]; default: 0;
+ *  1: bus-off, the TWAI controller is not involved in bus activities. 0: bus-on, the
+ *  TWAI controller is involved in bus activities
+ */
+#define TWAI_STATUS_NODE_BUS_OFF    (BIT(7))
+#define TWAI_STATUS_NODE_BUS_OFF_M  (TWAI_STATUS_NODE_BUS_OFF_V << TWAI_STATUS_NODE_BUS_OFF_S)
+#define TWAI_STATUS_NODE_BUS_OFF_V  0x00000001U
+#define TWAI_STATUS_NODE_BUS_OFF_S  7
+/** TWAI_STATUS_MISS : RO; bitpos: [8]; default: 0;
+ *  1: current message is destroyed because of FIFO overflow.
+ */
+#define TWAI_STATUS_MISS    (BIT(8))
+#define TWAI_STATUS_MISS_M  (TWAI_STATUS_MISS_V << TWAI_STATUS_MISS_S)
+#define TWAI_STATUS_MISS_V  0x00000001U
+#define TWAI_STATUS_MISS_S  8
+
+/** TWAI_INTERRUPT_REG register
+ *  Interrupt signals' register.
+ */
+#define TWAI_INTERRUPT_REG(i) (REG_TWAI_BASE(i) + 0xc)
+/** TWAI_RECEIVE_INT_ST : RO; bitpos: [0]; default: 0;
+ *  1: this bit is set while the receive FIFO is not empty and the RIE bit is set
+ *  within the interrupt enable register. 0: reset
+ */
+#define TWAI_RECEIVE_INT_ST    (BIT(0))
+#define TWAI_RECEIVE_INT_ST_M  (TWAI_RECEIVE_INT_ST_V << TWAI_RECEIVE_INT_ST_S)
+#define TWAI_RECEIVE_INT_ST_V  0x00000001U
+#define TWAI_RECEIVE_INT_ST_S  0
+/** TWAI_TRANSMIT_INT_ST : RO; bitpos: [1]; default: 0;
+ *  1: this bit is set whenever the transmit buffer status changes from '0-to-1'
+ *  (released) and the TIE bit is set within the interrupt enable register. 0: reset
+ */
+#define TWAI_TRANSMIT_INT_ST    (BIT(1))
+#define TWAI_TRANSMIT_INT_ST_M  (TWAI_TRANSMIT_INT_ST_V << TWAI_TRANSMIT_INT_ST_S)
+#define TWAI_TRANSMIT_INT_ST_V  0x00000001U
+#define TWAI_TRANSMIT_INT_ST_S  1
+/** TWAI_ERR_WARNING_INT_ST : RO; bitpos: [2]; default: 0;
+ *  1: this bit is set on every change (set and clear) of either the error status or
+ *  bus status bits and the EIE bit is set within the interrupt enable register. 0:
+ *  reset
+ */
+#define TWAI_ERR_WARNING_INT_ST    (BIT(2))
+#define TWAI_ERR_WARNING_INT_ST_M  (TWAI_ERR_WARNING_INT_ST_V << TWAI_ERR_WARNING_INT_ST_S)
+#define TWAI_ERR_WARNING_INT_ST_V  0x00000001U
+#define TWAI_ERR_WARNING_INT_ST_S  2
+/** TWAI_DATA_OVERRUN_INT_ST : RO; bitpos: [3]; default: 0;
+ *  1: this bit is set on a '0-to-1' transition of the data overrun status bit and the
+ *  DOIE bit is set within the interrupt enable register. 0: reset
+ */
+#define TWAI_DATA_OVERRUN_INT_ST    (BIT(3))
+#define TWAI_DATA_OVERRUN_INT_ST_M  (TWAI_DATA_OVERRUN_INT_ST_V << TWAI_DATA_OVERRUN_INT_ST_S)
+#define TWAI_DATA_OVERRUN_INT_ST_V  0x00000001U
+#define TWAI_DATA_OVERRUN_INT_ST_S  3
+/** TWAI_TS_COUNTER_OVFL_INT_ST : RO; bitpos: [4]; default: 0;
+ *  1: this bit is set then the timestamp counter reaches the maximum value and
+ *  overflow.
+ */
+#define TWAI_TS_COUNTER_OVFL_INT_ST    (BIT(4))
+#define TWAI_TS_COUNTER_OVFL_INT_ST_M  (TWAI_TS_COUNTER_OVFL_INT_ST_V << TWAI_TS_COUNTER_OVFL_INT_ST_S)
+#define TWAI_TS_COUNTER_OVFL_INT_ST_V  0x00000001U
+#define TWAI_TS_COUNTER_OVFL_INT_ST_S  4
+/** TWAI_ERR_PASSIVE_INT_ST : RO; bitpos: [5]; default: 0;
+ *  1: this bit is set whenever the TWAI controller has reached the error passive
+ *  status (at least one error counter exceeds the protocol-defined level of 127) or if
+ *  the TWAI controller is in the error passive status and enters the error active
+ *  status again and the EPIE bit is set within the interrupt enable register. 0: reset
+ */
+#define TWAI_ERR_PASSIVE_INT_ST    (BIT(5))
+#define TWAI_ERR_PASSIVE_INT_ST_M  (TWAI_ERR_PASSIVE_INT_ST_V << TWAI_ERR_PASSIVE_INT_ST_S)
+#define TWAI_ERR_PASSIVE_INT_ST_V  0x00000001U
+#define TWAI_ERR_PASSIVE_INT_ST_S  5
+/** TWAI_ARBITRATION_LOST_INT_ST : RO; bitpos: [6]; default: 0;
+ *  1: this bit is set when the TWAI controller lost the arbitration and becomes a
+ *  receiver and the ALIE bit is set within the interrupt enable register. 0: reset
+ */
+#define TWAI_ARBITRATION_LOST_INT_ST    (BIT(6))
+#define TWAI_ARBITRATION_LOST_INT_ST_M  (TWAI_ARBITRATION_LOST_INT_ST_V << TWAI_ARBITRATION_LOST_INT_ST_S)
+#define TWAI_ARBITRATION_LOST_INT_ST_V  0x00000001U
+#define TWAI_ARBITRATION_LOST_INT_ST_S  6
+/** TWAI_BUS_ERR_INT_ST : RO; bitpos: [7]; default: 0;
+ *  1: this bit is set when the TWAI controller detects an error on the TWAI-bus and
+ *  the BEIE bit is set within the interrupt enable register. 0: reset
+ */
+#define TWAI_BUS_ERR_INT_ST    (BIT(7))
+#define TWAI_BUS_ERR_INT_ST_M  (TWAI_BUS_ERR_INT_ST_V << TWAI_BUS_ERR_INT_ST_S)
+#define TWAI_BUS_ERR_INT_ST_V  0x00000001U
+#define TWAI_BUS_ERR_INT_ST_S  7
+/** TWAI_IDLE_INT_ST : RO; bitpos: [8]; default: 0;
+ *  1: this bit is set when the TWAI controller detects state of TWAI become IDLE and
+ *  this interrupt enable bit is set within the interrupt enable register. 0: reset
+ */
+#define TWAI_IDLE_INT_ST    (BIT(8))
+#define TWAI_IDLE_INT_ST_M  (TWAI_IDLE_INT_ST_V << TWAI_IDLE_INT_ST_S)
+#define TWAI_IDLE_INT_ST_V  0x00000001U
+#define TWAI_IDLE_INT_ST_S  8
+
+/** TWAI_INTERRUPT_ENABLE_REG register
+ *  Interrupt enable register.
+ */
+#define TWAI_INTERRUPT_ENABLE_REG(i) (REG_TWAI_BASE(i) + 0x10)
+/** TWAI_EXT_RECEIVE_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  1: enabled, when the receive buffer status is 'full' the TWAI controller requests
+ *  the respective interrupt. 0: disable
+ */
+#define TWAI_EXT_RECEIVE_INT_ENA    (BIT(0))
+#define TWAI_EXT_RECEIVE_INT_ENA_M  (TWAI_EXT_RECEIVE_INT_ENA_V << TWAI_EXT_RECEIVE_INT_ENA_S)
+#define TWAI_EXT_RECEIVE_INT_ENA_V  0x00000001U
+#define TWAI_EXT_RECEIVE_INT_ENA_S  0
+/** TWAI_EXT_TRANSMIT_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  1: enabled, when a message has been successfully transmitted or the transmit buffer
+ *  is accessible again (e.g. after an abort transmission command), the TWAI controller
+ *  requests the respective interrupt. 0: disable
+ */
+#define TWAI_EXT_TRANSMIT_INT_ENA    (BIT(1))
+#define TWAI_EXT_TRANSMIT_INT_ENA_M  (TWAI_EXT_TRANSMIT_INT_ENA_V << TWAI_EXT_TRANSMIT_INT_ENA_S)
+#define TWAI_EXT_TRANSMIT_INT_ENA_V  0x00000001U
+#define TWAI_EXT_TRANSMIT_INT_ENA_S  1
+/** TWAI_EXT_ERR_WARNING_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  1: enabled, if the error or bus status change (see status register. Table 14), the
+ *  TWAI controllerrequests the respective interrupt. 0: disable
+ */
+#define TWAI_EXT_ERR_WARNING_INT_ENA    (BIT(2))
+#define TWAI_EXT_ERR_WARNING_INT_ENA_M  (TWAI_EXT_ERR_WARNING_INT_ENA_V << TWAI_EXT_ERR_WARNING_INT_ENA_S)
+#define TWAI_EXT_ERR_WARNING_INT_ENA_V  0x00000001U
+#define TWAI_EXT_ERR_WARNING_INT_ENA_S  2
+/** TWAI_EXT_DATA_OVERRUN_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  1: enabled, if the data overrun status bit is set (see status register. Table 14),
+ *  the TWAI controllerrequests the respective interrupt. 0: disable
+ */
+#define TWAI_EXT_DATA_OVERRUN_INT_ENA    (BIT(3))
+#define TWAI_EXT_DATA_OVERRUN_INT_ENA_M  (TWAI_EXT_DATA_OVERRUN_INT_ENA_V << TWAI_EXT_DATA_OVERRUN_INT_ENA_S)
+#define TWAI_EXT_DATA_OVERRUN_INT_ENA_V  0x00000001U
+#define TWAI_EXT_DATA_OVERRUN_INT_ENA_S  3
+/** TWAI_TS_COUNTER_OVFL_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  enable the timestamp counter overflow interrupt request.
+ */
+#define TWAI_TS_COUNTER_OVFL_INT_ENA    (BIT(4))
+#define TWAI_TS_COUNTER_OVFL_INT_ENA_M  (TWAI_TS_COUNTER_OVFL_INT_ENA_V << TWAI_TS_COUNTER_OVFL_INT_ENA_S)
+#define TWAI_TS_COUNTER_OVFL_INT_ENA_V  0x00000001U
+#define TWAI_TS_COUNTER_OVFL_INT_ENA_S  4
+/** TWAI_ERR_PASSIVE_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  1: enabled, if the error status of the TWAI controller changes from error active to
+ *  error passive or vice versa, the respective interrupt is requested. 0: disable
+ */
+#define TWAI_ERR_PASSIVE_INT_ENA    (BIT(5))
+#define TWAI_ERR_PASSIVE_INT_ENA_M  (TWAI_ERR_PASSIVE_INT_ENA_V << TWAI_ERR_PASSIVE_INT_ENA_S)
+#define TWAI_ERR_PASSIVE_INT_ENA_V  0x00000001U
+#define TWAI_ERR_PASSIVE_INT_ENA_S  5
+/** TWAI_ARBITRATION_LOST_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  1: enabled, if the TWAI controller has lost arbitration, the respective interrupt
+ *  is requested. 0: disable
+ */
+#define TWAI_ARBITRATION_LOST_INT_ENA    (BIT(6))
+#define TWAI_ARBITRATION_LOST_INT_ENA_M  (TWAI_ARBITRATION_LOST_INT_ENA_V << TWAI_ARBITRATION_LOST_INT_ENA_S)
+#define TWAI_ARBITRATION_LOST_INT_ENA_V  0x00000001U
+#define TWAI_ARBITRATION_LOST_INT_ENA_S  6
+/** TWAI_BUS_ERR_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  1: enabled, if an bus error has been detected, the TWAI controller requests the
+ *  respective interrupt. 0: disable
+ */
+#define TWAI_BUS_ERR_INT_ENA    (BIT(7))
+#define TWAI_BUS_ERR_INT_ENA_M  (TWAI_BUS_ERR_INT_ENA_V << TWAI_BUS_ERR_INT_ENA_S)
+#define TWAI_BUS_ERR_INT_ENA_V  0x00000001U
+#define TWAI_BUS_ERR_INT_ENA_S  7
+/** TWAI_IDLE_INT_ENA : RO; bitpos: [8]; default: 0;
+ *  1: enabled, if state of TWAI become IDLE, the TWAI controller requests the
+ *  respective interrupt. 0: disable
+ */
+#define TWAI_IDLE_INT_ENA    (BIT(8))
+#define TWAI_IDLE_INT_ENA_M  (TWAI_IDLE_INT_ENA_V << TWAI_IDLE_INT_ENA_S)
+#define TWAI_IDLE_INT_ENA_V  0x00000001U
+#define TWAI_IDLE_INT_ENA_S  8
+
+/** TWAI_BUS_TIMING_0_REG register
+ *  Bit timing configuration register 0.
+ */
+#define TWAI_BUS_TIMING_0_REG(i) (REG_TWAI_BASE(i) + 0x18)
+/** TWAI_BAUD_PRESC : R/W; bitpos: [13:0]; default: 0;
+ *  The period of the TWAI system clock is programmable and determines the individual
+ *  bit timing. Software has R/W permission in reset mode and RO permission in
+ *  operation mode.
+ */
+#define TWAI_BAUD_PRESC    0x00003FFFU
+#define TWAI_BAUD_PRESC_M  (TWAI_BAUD_PRESC_V << TWAI_BAUD_PRESC_S)
+#define TWAI_BAUD_PRESC_V  0x00003FFFU
+#define TWAI_BAUD_PRESC_S  0
+/** TWAI_SYNC_JUMP_WIDTH : R/W; bitpos: [15:14]; default: 0;
+ *  The synchronization jump width defines the maximum number of clock cycles a bit
+ *  period may be shortened or lengthened. Software has R/W permission in reset mode
+ *  and RO in operation mode.
+ */
+#define TWAI_SYNC_JUMP_WIDTH    0x00000003U
+#define TWAI_SYNC_JUMP_WIDTH_M  (TWAI_SYNC_JUMP_WIDTH_V << TWAI_SYNC_JUMP_WIDTH_S)
+#define TWAI_SYNC_JUMP_WIDTH_V  0x00000003U
+#define TWAI_SYNC_JUMP_WIDTH_S  14
+
+/** TWAI_BUS_TIMING_1_REG register
+ *  Bit timing configuration register 1.
+ */
+#define TWAI_BUS_TIMING_1_REG(i) (REG_TWAI_BASE(i) + 0x1c)
+/** TWAI_TIME_SEGMENT1 : R/W; bitpos: [3:0]; default: 0;
+ *  The number of clock cycles in TSEG1 per bit timing. Software has R/W permission in
+ *  reset mode and RO in operation mode.
+ */
+#define TWAI_TIME_SEGMENT1    0x0000000FU
+#define TWAI_TIME_SEGMENT1_M  (TWAI_TIME_SEGMENT1_V << TWAI_TIME_SEGMENT1_S)
+#define TWAI_TIME_SEGMENT1_V  0x0000000FU
+#define TWAI_TIME_SEGMENT1_S  0
+/** TWAI_TIME_SEGMENT2 : R/W; bitpos: [6:4]; default: 0;
+ *  The number of clock cycles in TSEG2 per bit timing. Software has R/W permission in
+ *  reset mode and RO in operation mode.
+ */
+#define TWAI_TIME_SEGMENT2    0x00000007U
+#define TWAI_TIME_SEGMENT2_M  (TWAI_TIME_SEGMENT2_V << TWAI_TIME_SEGMENT2_S)
+#define TWAI_TIME_SEGMENT2_V  0x00000007U
+#define TWAI_TIME_SEGMENT2_S  4
+/** TWAI_TIME_SAMPLING : R/W; bitpos: [7]; default: 0;
+ *  1: triple, the bus is sampled three times. 0: single, the bus is sampled once.
+ *  Software has R/W permission in reset mode and RO in operation mode.
+ */
+#define TWAI_TIME_SAMPLING    (BIT(7))
+#define TWAI_TIME_SAMPLING_M  (TWAI_TIME_SAMPLING_V << TWAI_TIME_SAMPLING_S)
+#define TWAI_TIME_SAMPLING_V  0x00000001U
+#define TWAI_TIME_SAMPLING_S  7
+
+/** TWAI_ARB_LOST_CAP_REG register
+ *  TWAI arbiter lost capture register.
+ */
+#define TWAI_ARB_LOST_CAP_REG(i) (REG_TWAI_BASE(i) + 0x2c)
+/** TWAI_ARBITRATION_LOST_CAPTURE : RO; bitpos: [4:0]; default: 0;
+ *  This register contains information about the bit position of losing arbitration.
+ */
+#define TWAI_ARBITRATION_LOST_CAPTURE    0x0000001FU
+#define TWAI_ARBITRATION_LOST_CAPTURE_M  (TWAI_ARBITRATION_LOST_CAPTURE_V << TWAI_ARBITRATION_LOST_CAPTURE_S)
+#define TWAI_ARBITRATION_LOST_CAPTURE_V  0x0000001FU
+#define TWAI_ARBITRATION_LOST_CAPTURE_S  0
+
+/** TWAI_ERR_CODE_CAP_REG register
+ *  TWAI error info capture register.
+ */
+#define TWAI_ERR_CODE_CAP_REG(i) (REG_TWAI_BASE(i) + 0x30)
+/** TWAI_ERR_CAPTURE_CODE_SEGMENT : RO; bitpos: [4:0]; default: 0;
+ *  This register contains information about the location of errors on the bus.
+ */
+#define TWAI_ERR_CAPTURE_CODE_SEGMENT    0x0000001FU
+#define TWAI_ERR_CAPTURE_CODE_SEGMENT_M  (TWAI_ERR_CAPTURE_CODE_SEGMENT_V << TWAI_ERR_CAPTURE_CODE_SEGMENT_S)
+#define TWAI_ERR_CAPTURE_CODE_SEGMENT_V  0x0000001FU
+#define TWAI_ERR_CAPTURE_CODE_SEGMENT_S  0
+/** TWAI_ERR_CAPTURE_CODE_DIRECTION : RO; bitpos: [5]; default: 0;
+ *  1: RX, error occurred during reception. 0: TX, error occurred during transmission.
+ */
+#define TWAI_ERR_CAPTURE_CODE_DIRECTION    (BIT(5))
+#define TWAI_ERR_CAPTURE_CODE_DIRECTION_M  (TWAI_ERR_CAPTURE_CODE_DIRECTION_V << TWAI_ERR_CAPTURE_CODE_DIRECTION_S)
+#define TWAI_ERR_CAPTURE_CODE_DIRECTION_V  0x00000001U
+#define TWAI_ERR_CAPTURE_CODE_DIRECTION_S  5
+/** TWAI_ERR_CAPTURE_CODE_TYPE : RO; bitpos: [7:6]; default: 0;
+ *  00: bit error. 01: form error. 10:stuff error. 11:other type of error.
+ */
+#define TWAI_ERR_CAPTURE_CODE_TYPE    0x00000003U
+#define TWAI_ERR_CAPTURE_CODE_TYPE_M  (TWAI_ERR_CAPTURE_CODE_TYPE_V << TWAI_ERR_CAPTURE_CODE_TYPE_S)
+#define TWAI_ERR_CAPTURE_CODE_TYPE_V  0x00000003U
+#define TWAI_ERR_CAPTURE_CODE_TYPE_S  6
+
+/** TWAI_ERR_WARNING_LIMIT_REG register
+ *  TWAI error threshold configuration register.
+ */
+#define TWAI_ERR_WARNING_LIMIT_REG(i) (REG_TWAI_BASE(i) + 0x34)
+/** TWAI_ERR_WARNING_LIMIT : R/W; bitpos: [7:0]; default: 96;
+ *  The threshold that trigger error warning interrupt when this interrupt is enabled.
+ *  Software has R/W permission in reset mode and RO in operation mode.
+ */
+#define TWAI_ERR_WARNING_LIMIT    0x000000FFU
+#define TWAI_ERR_WARNING_LIMIT_M  (TWAI_ERR_WARNING_LIMIT_V << TWAI_ERR_WARNING_LIMIT_S)
+#define TWAI_ERR_WARNING_LIMIT_V  0x000000FFU
+#define TWAI_ERR_WARNING_LIMIT_S  0
+
+/** TWAI_RX_ERR_CNT_REG register
+ *  Rx error counter register.
+ */
+#define TWAI_RX_ERR_CNT_REG(i) (REG_TWAI_BASE(i) + 0x38)
+/** TWAI_RX_ERR_CNT : R/W; bitpos: [7:0]; default: 0;
+ *  The RX error counter register reflects the current value of the transmit error
+ *  counter. Software has R/W permission in reset mode and RO in operation mode.
+ */
+#define TWAI_RX_ERR_CNT    0x000000FFU
+#define TWAI_RX_ERR_CNT_M  (TWAI_RX_ERR_CNT_V << TWAI_RX_ERR_CNT_S)
+#define TWAI_RX_ERR_CNT_V  0x000000FFU
+#define TWAI_RX_ERR_CNT_S  0
+
+/** TWAI_TX_ERR_CNT_REG register
+ *  Tx error counter register.
+ */
+#define TWAI_TX_ERR_CNT_REG(i) (REG_TWAI_BASE(i) + 0x3c)
+/** TWAI_TX_ERR_CNT : R/W; bitpos: [7:0]; default: 0;
+ *  The TX error counter register reflects the current value of the transmit error
+ *  counter. Software has R/W permission in reset mode and RO in operation mode.
+ */
+#define TWAI_TX_ERR_CNT    0x000000FFU
+#define TWAI_TX_ERR_CNT_M  (TWAI_TX_ERR_CNT_V << TWAI_TX_ERR_CNT_S)
+#define TWAI_TX_ERR_CNT_V  0x000000FFU
+#define TWAI_TX_ERR_CNT_S  0
+
+/** TWAI_DATA_0_REG register
+ *  Data register 0.
+ */
+#define TWAI_DATA_0_REG(i) (REG_TWAI_BASE(i) + 0x40)
+/** TWAI_DATA_0 : R/W; bitpos: [7:0]; default: 0;
+ *  In reset mode, it is acceptance code register 0 with R/W Permission. In operation
+ *  mode, when software initiate write operation, it is tx data register 0 and when
+ *  software initiate read operation, it is rx data register 0.
+ */
+#define TWAI_DATA_0    0x000000FFU
+#define TWAI_DATA_0_M  (TWAI_DATA_0_V << TWAI_DATA_0_S)
+#define TWAI_DATA_0_V  0x000000FFU
+#define TWAI_DATA_0_S  0
+
+/** TWAI_DATA_1_REG register
+ *  Data register 1.
+ */
+#define TWAI_DATA_1_REG(i) (REG_TWAI_BASE(i) + 0x44)
+/** TWAI_DATA_1 : R/W; bitpos: [7:0]; default: 0;
+ *  In reset mode, it is acceptance code register 1 with R/W Permission. In operation
+ *  mode, when software initiate write operation, it is tx data register 1 and when
+ *  software initiate read operation, it is rx data register 1.
+ */
+#define TWAI_DATA_1    0x000000FFU
+#define TWAI_DATA_1_M  (TWAI_DATA_1_V << TWAI_DATA_1_S)
+#define TWAI_DATA_1_V  0x000000FFU
+#define TWAI_DATA_1_S  0
+
+/** TWAI_DATA_2_REG register
+ *  Data register 2.
+ */
+#define TWAI_DATA_2_REG(i) (REG_TWAI_BASE(i) + 0x48)
+/** TWAI_DATA_2 : R/W; bitpos: [7:0]; default: 0;
+ *  In reset mode, it is acceptance code register 2 with R/W Permission. In operation
+ *  mode, when software initiate write operation, it is tx data register 2 and when
+ *  software initiate read operation, it is rx data register 2.
+ */
+#define TWAI_DATA_2    0x000000FFU
+#define TWAI_DATA_2_M  (TWAI_DATA_2_V << TWAI_DATA_2_S)
+#define TWAI_DATA_2_V  0x000000FFU
+#define TWAI_DATA_2_S  0
+
+/** TWAI_DATA_3_REG register
+ *  Data register 3.
+ */
+#define TWAI_DATA_3_REG(i) (REG_TWAI_BASE(i) + 0x4c)
+/** TWAI_DATA_3 : R/W; bitpos: [7:0]; default: 0;
+ *  In reset mode, it is acceptance code register 3 with R/W Permission. In operation
+ *  mode, when software initiate write operation, it is tx data register 3 and when
+ *  software initiate read operation, it is rx data register 3.
+ */
+#define TWAI_DATA_3    0x000000FFU
+#define TWAI_DATA_3_M  (TWAI_DATA_3_V << TWAI_DATA_3_S)
+#define TWAI_DATA_3_V  0x000000FFU
+#define TWAI_DATA_3_S  0
+
+/** TWAI_DATA_4_REG register
+ *  Data register 4.
+ */
+#define TWAI_DATA_4_REG(i) (REG_TWAI_BASE(i) + 0x50)
+/** TWAI_DATA_4 : R/W; bitpos: [7:0]; default: 0;
+ *  In reset mode, it is acceptance mask register 0 with R/W Permission. In operation
+ *  mode, when software initiate write operation, it is tx data register 4 and when
+ *  software initiate read operation, it is rx data register 4.
+ */
+#define TWAI_DATA_4    0x000000FFU
+#define TWAI_DATA_4_M  (TWAI_DATA_4_V << TWAI_DATA_4_S)
+#define TWAI_DATA_4_V  0x000000FFU
+#define TWAI_DATA_4_S  0
+
+/** TWAI_DATA_5_REG register
+ *  Data register 5.
+ */
+#define TWAI_DATA_5_REG(i) (REG_TWAI_BASE(i) + 0x54)
+/** TWAI_DATA_5 : R/W; bitpos: [7:0]; default: 0;
+ *  In reset mode, it is acceptance mask register 1 with R/W Permission. In operation
+ *  mode, when software initiate write operation, it is tx data register 5 and when
+ *  software initiate read operation, it is rx data register 5.
+ */
+#define TWAI_DATA_5    0x000000FFU
+#define TWAI_DATA_5_M  (TWAI_DATA_5_V << TWAI_DATA_5_S)
+#define TWAI_DATA_5_V  0x000000FFU
+#define TWAI_DATA_5_S  0
+
+/** TWAI_DATA_6_REG register
+ *  Data register 6.
+ */
+#define TWAI_DATA_6_REG(i) (REG_TWAI_BASE(i) + 0x58)
+/** TWAI_DATA_6 : R/W; bitpos: [7:0]; default: 0;
+ *  In reset mode, it is acceptance mask register 2 with R/W Permission. In operation
+ *  mode, when software initiate write operation, it is tx data register 6 and when
+ *  software initiate read operation, it is rx data register 6.
+ */
+#define TWAI_DATA_6    0x000000FFU
+#define TWAI_DATA_6_M  (TWAI_DATA_6_V << TWAI_DATA_6_S)
+#define TWAI_DATA_6_V  0x000000FFU
+#define TWAI_DATA_6_S  0
+
+/** TWAI_DATA_7_REG register
+ *  Data register 7.
+ */
+#define TWAI_DATA_7_REG(i) (REG_TWAI_BASE(i) + 0x5c)
+/** TWAI_DATA_7 : R/W; bitpos: [7:0]; default: 0;
+ *  In reset mode, it is acceptance mask register 3 with R/W Permission. In operation
+ *  mode, when software initiate write operation, it is tx data register 7 and when
+ *  software initiate read operation, it is rx data register 7.
+ */
+#define TWAI_DATA_7    0x000000FFU
+#define TWAI_DATA_7_M  (TWAI_DATA_7_V << TWAI_DATA_7_S)
+#define TWAI_DATA_7_V  0x000000FFU
+#define TWAI_DATA_7_S  0
+
+/** TWAI_DATA_8_REG register
+ *  Data register 8.
+ */
+#define TWAI_DATA_8_REG(i) (REG_TWAI_BASE(i) + 0x60)
+/** TWAI_DATA_8 : R/W; bitpos: [7:0]; default: 0;
+ *  In reset mode, reserved with RO. In operation mode, when software initiate write
+ *  operation, it is tx data register 8 and when software initiate read operation, it
+ *  is rx data register 8.
+ */
+#define TWAI_DATA_8    0x000000FFU
+#define TWAI_DATA_8_M  (TWAI_DATA_8_V << TWAI_DATA_8_S)
+#define TWAI_DATA_8_V  0x000000FFU
+#define TWAI_DATA_8_S  0
+
+/** TWAI_DATA_9_REG register
+ *  Data register 9.
+ */
+#define TWAI_DATA_9_REG(i) (REG_TWAI_BASE(i) + 0x64)
+/** TWAI_DATA_9 : R/W; bitpos: [7:0]; default: 0;
+ *  In reset mode, reserved with RO. In operation mode, when software initiate write
+ *  operation, it is tx data register 9 and when software initiate read operation, it
+ *  is rx data register 9.
+ */
+#define TWAI_DATA_9    0x000000FFU
+#define TWAI_DATA_9_M  (TWAI_DATA_9_V << TWAI_DATA_9_S)
+#define TWAI_DATA_9_V  0x000000FFU
+#define TWAI_DATA_9_S  0
+
+/** TWAI_DATA_10_REG register
+ *  Data register 10.
+ */
+#define TWAI_DATA_10_REG(i) (REG_TWAI_BASE(i) + 0x68)
+/** TWAI_DATA_10 : R/W; bitpos: [7:0]; default: 0;
+ *  In reset mode, reserved with RO. In operation mode, when software initiate write
+ *  operation, it is tx data register 10 and when software initiate read operation, it
+ *  is rx data register 10.
+ */
+#define TWAI_DATA_10    0x000000FFU
+#define TWAI_DATA_10_M  (TWAI_DATA_10_V << TWAI_DATA_10_S)
+#define TWAI_DATA_10_V  0x000000FFU
+#define TWAI_DATA_10_S  0
+
+/** TWAI_DATA_11_REG register
+ *  Data register 11.
+ */
+#define TWAI_DATA_11_REG(i) (REG_TWAI_BASE(i) + 0x6c)
+/** TWAI_DATA_11 : R/W; bitpos: [7:0]; default: 0;
+ *  In reset mode, reserved with RO. In operation mode, when software initiate write
+ *  operation, it is tx data register 11 and when software initiate read operation, it
+ *  is rx data register 11.
+ */
+#define TWAI_DATA_11    0x000000FFU
+#define TWAI_DATA_11_M  (TWAI_DATA_11_V << TWAI_DATA_11_S)
+#define TWAI_DATA_11_V  0x000000FFU
+#define TWAI_DATA_11_S  0
+
+/** TWAI_DATA_12_REG register
+ *  Data register 12.
+ */
+#define TWAI_DATA_12_REG(i) (REG_TWAI_BASE(i) + 0x70)
+/** TWAI_DATA_12 : R/W; bitpos: [7:0]; default: 0;
+ *  In reset mode, reserved with RO. In operation mode, when software initiate write
+ *  operation, it is tx data register 12 and when software initiate read operation, it
+ *  is rx data register 12.
+ */
+#define TWAI_DATA_12    0x000000FFU
+#define TWAI_DATA_12_M  (TWAI_DATA_12_V << TWAI_DATA_12_S)
+#define TWAI_DATA_12_V  0x000000FFU
+#define TWAI_DATA_12_S  0
+
+/** TWAI_RX_MESSAGE_COUNTER_REG register
+ *  Received message counter register.
+ */
+#define TWAI_RX_MESSAGE_COUNTER_REG(i) (REG_TWAI_BASE(i) + 0x74)
+/** TWAI_RX_MESSAGE_COUNTER : RO; bitpos: [6:0]; default: 0;
+ *  Reflects the number of messages available within the RXFIFO. The value is
+ *  incremented with each receive event and decremented by the release receive buffer
+ *  command.
+ */
+#define TWAI_RX_MESSAGE_COUNTER    0x0000007FU
+#define TWAI_RX_MESSAGE_COUNTER_M  (TWAI_RX_MESSAGE_COUNTER_V << TWAI_RX_MESSAGE_COUNTER_S)
+#define TWAI_RX_MESSAGE_COUNTER_V  0x0000007FU
+#define TWAI_RX_MESSAGE_COUNTER_S  0
+
+/** TWAI_CLOCK_DIVIDER_REG register
+ *  Clock divider register.
+ */
+#define TWAI_CLOCK_DIVIDER_REG(i) (REG_TWAI_BASE(i) + 0x7c)
+/** TWAI_CD : R/W; bitpos: [7:0]; default: 0;
+ *  These bits are used to define the frequency at the external CLKOUT pin.
+ */
+#define TWAI_CD    0x000000FFU
+#define TWAI_CD_M  (TWAI_CD_V << TWAI_CD_S)
+#define TWAI_CD_V  0x000000FFU
+#define TWAI_CD_S  0
+/** TWAI_CLOCK_OFF : R/W; bitpos: [8]; default: 0;
+ *  1: Disable the external CLKOUT pin. 0: Enable the external CLKOUT pin. Software has
+ *  R/W permission in reset mode and RO in operation mode.
+ */
+#define TWAI_CLOCK_OFF    (BIT(8))
+#define TWAI_CLOCK_OFF_M  (TWAI_CLOCK_OFF_V << TWAI_CLOCK_OFF_S)
+#define TWAI_CLOCK_OFF_V  0x00000001U
+#define TWAI_CLOCK_OFF_S  8
+
+/** TWAI_SW_STANDBY_CFG_REG register
+ *  Software configure standby pin directly.
+ */
+#define TWAI_SW_STANDBY_CFG_REG(i) (REG_TWAI_BASE(i) + 0x80)
+/** TWAI_SW_STANDBY_EN : R/W; bitpos: [0]; default: 0;
+ *  Enable standby pin.
+ */
+#define TWAI_SW_STANDBY_EN    (BIT(0))
+#define TWAI_SW_STANDBY_EN_M  (TWAI_SW_STANDBY_EN_V << TWAI_SW_STANDBY_EN_S)
+#define TWAI_SW_STANDBY_EN_V  0x00000001U
+#define TWAI_SW_STANDBY_EN_S  0
+/** TWAI_SW_STANDBY_CLR : R/W; bitpos: [1]; default: 1;
+ *  Clear standby pin.
+ */
+#define TWAI_SW_STANDBY_CLR    (BIT(1))
+#define TWAI_SW_STANDBY_CLR_M  (TWAI_SW_STANDBY_CLR_V << TWAI_SW_STANDBY_CLR_S)
+#define TWAI_SW_STANDBY_CLR_V  0x00000001U
+#define TWAI_SW_STANDBY_CLR_S  1
+
+/** TWAI_HW_CFG_REG register
+ *  Hardware configure standby pin.
+ */
+#define TWAI_HW_CFG_REG(i) (REG_TWAI_BASE(i) + 0x84)
+/** TWAI_HW_STANDBY_EN : R/W; bitpos: [0]; default: 0;
+ *  Enable function that hardware control standby pin.
+ */
+#define TWAI_HW_STANDBY_EN    (BIT(0))
+#define TWAI_HW_STANDBY_EN_M  (TWAI_HW_STANDBY_EN_V << TWAI_HW_STANDBY_EN_S)
+#define TWAI_HW_STANDBY_EN_V  0x00000001U
+#define TWAI_HW_STANDBY_EN_S  0
+
+/** TWAI_HW_STANDBY_CNT_REG register
+ *  Configure standby counter.
+ */
+#define TWAI_HW_STANDBY_CNT_REG(i) (REG_TWAI_BASE(i) + 0x88)
+/** TWAI_STANDBY_WAIT_CNT : R/W; bitpos: [31:0]; default: 1;
+ *  Configure the number of cycles before standby becomes high when TWAI_HW_STANDBY_EN
+ *  is enabled.
+ */
+#define TWAI_STANDBY_WAIT_CNT    0xFFFFFFFFU
+#define TWAI_STANDBY_WAIT_CNT_M  (TWAI_STANDBY_WAIT_CNT_V << TWAI_STANDBY_WAIT_CNT_S)
+#define TWAI_STANDBY_WAIT_CNT_V  0xFFFFFFFFU
+#define TWAI_STANDBY_WAIT_CNT_S  0
+
+/** TWAI_IDLE_INTR_CNT_REG register
+ *  Configure idle interrupt counter.
+ */
+#define TWAI_IDLE_INTR_CNT_REG(i) (REG_TWAI_BASE(i) + 0x8c)
+/** TWAI_IDLE_INTR_CNT : R/W; bitpos: [31:0]; default: 1;
+ *  Configure the number of cycles before triggering idle interrupt.
+ */
+#define TWAI_IDLE_INTR_CNT    0xFFFFFFFFU
+#define TWAI_IDLE_INTR_CNT_M  (TWAI_IDLE_INTR_CNT_V << TWAI_IDLE_INTR_CNT_S)
+#define TWAI_IDLE_INTR_CNT_V  0xFFFFFFFFU
+#define TWAI_IDLE_INTR_CNT_S  0
+
+/** TWAI_ECO_CFG_REG register
+ *  ECO configuration register.
+ */
+#define TWAI_ECO_CFG_REG(i) (REG_TWAI_BASE(i) + 0x90)
+/** TWAI_RDN_ENA : R/W; bitpos: [0]; default: 0;
+ *  Enable eco module.
+ */
+#define TWAI_RDN_ENA    (BIT(0))
+#define TWAI_RDN_ENA_M  (TWAI_RDN_ENA_V << TWAI_RDN_ENA_S)
+#define TWAI_RDN_ENA_V  0x00000001U
+#define TWAI_RDN_ENA_S  0
+/** TWAI_RDN_RESULT : RO; bitpos: [1]; default: 1;
+ *  Output of eco module.
+ */
+#define TWAI_RDN_RESULT    (BIT(1))
+#define TWAI_RDN_RESULT_M  (TWAI_RDN_RESULT_V << TWAI_RDN_RESULT_S)
+#define TWAI_RDN_RESULT_V  0x00000001U
+#define TWAI_RDN_RESULT_S  1
+
+/** TWAI_TIMESTAMP_DATA_REG register
+ *  Timestamp data register
+ */
+#define TWAI_TIMESTAMP_DATA_REG(i) (REG_TWAI_BASE(i) + 0x94)
+/** TWAI_TIMESTAMP_DATA : RO; bitpos: [31:0]; default: 0;
+ *  Data of timestamp of a CAN frame.
+ */
+#define TWAI_TIMESTAMP_DATA    0xFFFFFFFFU
+#define TWAI_TIMESTAMP_DATA_M  (TWAI_TIMESTAMP_DATA_V << TWAI_TIMESTAMP_DATA_S)
+#define TWAI_TIMESTAMP_DATA_V  0xFFFFFFFFU
+#define TWAI_TIMESTAMP_DATA_S  0
+
+/** TWAI_TIMESTAMP_PRESCALER_REG register
+ *  Timestamp configuration register
+ */
+#define TWAI_TIMESTAMP_PRESCALER_REG(i) (REG_TWAI_BASE(i) + 0x98)
+/** TWAI_TS_DIV_NUM : R/W; bitpos: [15:0]; default: 31;
+ *  Configures the clock division number of timestamp counter.
+ */
+#define TWAI_TS_DIV_NUM    0x0000FFFFU
+#define TWAI_TS_DIV_NUM_M  (TWAI_TS_DIV_NUM_V << TWAI_TS_DIV_NUM_S)
+#define TWAI_TS_DIV_NUM_V  0x0000FFFFU
+#define TWAI_TS_DIV_NUM_S  0
+
+/** TWAI_TIMESTAMP_CFG_REG register
+ *  Timestamp configuration register
+ */
+#define TWAI_TIMESTAMP_CFG_REG(i) (REG_TWAI_BASE(i) + 0x9c)
+/** TWAI_TS_ENABLE : R/W; bitpos: [0]; default: 0;
+ *  enable the timestamp collection function.
+ */
+#define TWAI_TS_ENABLE    (BIT(0))
+#define TWAI_TS_ENABLE_M  (TWAI_TS_ENABLE_V << TWAI_TS_ENABLE_S)
+#define TWAI_TS_ENABLE_V  0x00000001U
+#define TWAI_TS_ENABLE_S  0
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32p4/include/soc/uart_reg.h

@@ -0,0 +1,1579 @@
+/**
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** UART_FIFO_REG register
+ *  FIFO data register
+ */
+#define UART_FIFO_REG(i) (REG_UART_BASE(i) + 0x0)
+/** UART_RXFIFO_RD_BYTE : RO; bitpos: [7:0]; default: 0;
+ *  UART $n accesses FIFO via this register.
+ */
+#define UART_RXFIFO_RD_BYTE    0x000000FFU
+#define UART_RXFIFO_RD_BYTE_M  (UART_RXFIFO_RD_BYTE_V << UART_RXFIFO_RD_BYTE_S)
+#define UART_RXFIFO_RD_BYTE_V  0x000000FFU
+#define UART_RXFIFO_RD_BYTE_S  0
+
+/** UART_INT_RAW_REG register
+ *  Raw interrupt status
+ */
+#define UART_INT_RAW_REG(i) (REG_UART_BASE(i) + 0x4)
+/** UART_RXFIFO_FULL_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver receives more data than
+ *  what rxfifo_full_thrhd specifies.
+ */
+#define UART_RXFIFO_FULL_INT_RAW    (BIT(0))
+#define UART_RXFIFO_FULL_INT_RAW_M  (UART_RXFIFO_FULL_INT_RAW_V << UART_RXFIFO_FULL_INT_RAW_S)
+#define UART_RXFIFO_FULL_INT_RAW_V  0x00000001U
+#define UART_RXFIFO_FULL_INT_RAW_S  0
+/** UART_TXFIFO_EMPTY_INT_RAW : R/WTC/SS; bitpos: [1]; default: 1;
+ *  This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is
+ *  less than what txfifo_empty_thrhd specifies .
+ */
+#define UART_TXFIFO_EMPTY_INT_RAW    (BIT(1))
+#define UART_TXFIFO_EMPTY_INT_RAW_M  (UART_TXFIFO_EMPTY_INT_RAW_V << UART_TXFIFO_EMPTY_INT_RAW_S)
+#define UART_TXFIFO_EMPTY_INT_RAW_V  0x00000001U
+#define UART_TXFIFO_EMPTY_INT_RAW_S  1
+/** UART_PARITY_ERR_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver detects a parity error in
+ *  the data.
+ */
+#define UART_PARITY_ERR_INT_RAW    (BIT(2))
+#define UART_PARITY_ERR_INT_RAW_M  (UART_PARITY_ERR_INT_RAW_V << UART_PARITY_ERR_INT_RAW_S)
+#define UART_PARITY_ERR_INT_RAW_V  0x00000001U
+#define UART_PARITY_ERR_INT_RAW_S  2
+/** UART_FRM_ERR_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver detects a data frame error
+ *  .
+ */
+#define UART_FRM_ERR_INT_RAW    (BIT(3))
+#define UART_FRM_ERR_INT_RAW_M  (UART_FRM_ERR_INT_RAW_V << UART_FRM_ERR_INT_RAW_S)
+#define UART_FRM_ERR_INT_RAW_V  0x00000001U
+#define UART_FRM_ERR_INT_RAW_S  3
+/** UART_RXFIFO_OVF_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver receives more data than
+ *  the FIFO can store.
+ */
+#define UART_RXFIFO_OVF_INT_RAW    (BIT(4))
+#define UART_RXFIFO_OVF_INT_RAW_M  (UART_RXFIFO_OVF_INT_RAW_V << UART_RXFIFO_OVF_INT_RAW_S)
+#define UART_RXFIFO_OVF_INT_RAW_V  0x00000001U
+#define UART_RXFIFO_OVF_INT_RAW_S  4
+/** UART_DSR_CHG_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver detects the edge change of
+ *  DSRn signal.
+ */
+#define UART_DSR_CHG_INT_RAW    (BIT(5))
+#define UART_DSR_CHG_INT_RAW_M  (UART_DSR_CHG_INT_RAW_V << UART_DSR_CHG_INT_RAW_S)
+#define UART_DSR_CHG_INT_RAW_V  0x00000001U
+#define UART_DSR_CHG_INT_RAW_S  5
+/** UART_CTS_CHG_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver detects the edge change of
+ *  CTSn signal.
+ */
+#define UART_CTS_CHG_INT_RAW    (BIT(6))
+#define UART_CTS_CHG_INT_RAW_M  (UART_CTS_CHG_INT_RAW_V << UART_CTS_CHG_INT_RAW_S)
+#define UART_CTS_CHG_INT_RAW_V  0x00000001U
+#define UART_CTS_CHG_INT_RAW_S  6
+/** UART_BRK_DET_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver detects a 0 after the stop
+ *  bit.
+ */
+#define UART_BRK_DET_INT_RAW    (BIT(7))
+#define UART_BRK_DET_INT_RAW_M  (UART_BRK_DET_INT_RAW_V << UART_BRK_DET_INT_RAW_S)
+#define UART_BRK_DET_INT_RAW_V  0x00000001U
+#define UART_BRK_DET_INT_RAW_S  7
+/** UART_RXFIFO_TOUT_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver takes more time than
+ *  rx_tout_thrhd to receive a byte.
+ */
+#define UART_RXFIFO_TOUT_INT_RAW    (BIT(8))
+#define UART_RXFIFO_TOUT_INT_RAW_M  (UART_RXFIFO_TOUT_INT_RAW_V << UART_RXFIFO_TOUT_INT_RAW_S)
+#define UART_RXFIFO_TOUT_INT_RAW_V  0x00000001U
+#define UART_RXFIFO_TOUT_INT_RAW_S  8
+/** UART_SW_XON_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver recevies Xon char when
+ *  uart_sw_flow_con_en is set to 1.
+ */
+#define UART_SW_XON_INT_RAW    (BIT(9))
+#define UART_SW_XON_INT_RAW_M  (UART_SW_XON_INT_RAW_V << UART_SW_XON_INT_RAW_S)
+#define UART_SW_XON_INT_RAW_V  0x00000001U
+#define UART_SW_XON_INT_RAW_S  9
+/** UART_SW_XOFF_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver receives Xoff char when
+ *  uart_sw_flow_con_en is set to 1.
+ */
+#define UART_SW_XOFF_INT_RAW    (BIT(10))
+#define UART_SW_XOFF_INT_RAW_M  (UART_SW_XOFF_INT_RAW_V << UART_SW_XOFF_INT_RAW_S)
+#define UART_SW_XOFF_INT_RAW_V  0x00000001U
+#define UART_SW_XOFF_INT_RAW_S  10
+/** UART_GLITCH_DET_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver detects a glitch in the
+ *  middle of a start bit.
+ */
+#define UART_GLITCH_DET_INT_RAW    (BIT(11))
+#define UART_GLITCH_DET_INT_RAW_M  (UART_GLITCH_DET_INT_RAW_V << UART_GLITCH_DET_INT_RAW_S)
+#define UART_GLITCH_DET_INT_RAW_V  0x00000001U
+#define UART_GLITCH_DET_INT_RAW_S  11
+/** UART_TX_BRK_DONE_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
+ *  This interrupt raw bit turns to high level when transmitter completes  sending
+ *  NULL characters after all data in Tx-FIFO are sent.
+ */
+#define UART_TX_BRK_DONE_INT_RAW    (BIT(12))
+#define UART_TX_BRK_DONE_INT_RAW_M  (UART_TX_BRK_DONE_INT_RAW_V << UART_TX_BRK_DONE_INT_RAW_S)
+#define UART_TX_BRK_DONE_INT_RAW_V  0x00000001U
+#define UART_TX_BRK_DONE_INT_RAW_S  12
+/** UART_TX_BRK_IDLE_DONE_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
+ *  This interrupt raw bit turns to high level when transmitter has kept the shortest
+ *  duration after sending the  last data.
+ */
+#define UART_TX_BRK_IDLE_DONE_INT_RAW    (BIT(13))
+#define UART_TX_BRK_IDLE_DONE_INT_RAW_M  (UART_TX_BRK_IDLE_DONE_INT_RAW_V << UART_TX_BRK_IDLE_DONE_INT_RAW_S)
+#define UART_TX_BRK_IDLE_DONE_INT_RAW_V  0x00000001U
+#define UART_TX_BRK_IDLE_DONE_INT_RAW_S  13
+/** UART_TX_DONE_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0;
+ *  This interrupt raw bit turns to high level when transmitter has send out all data
+ *  in FIFO.
+ */
+#define UART_TX_DONE_INT_RAW    (BIT(14))
+#define UART_TX_DONE_INT_RAW_M  (UART_TX_DONE_INT_RAW_V << UART_TX_DONE_INT_RAW_S)
+#define UART_TX_DONE_INT_RAW_V  0x00000001U
+#define UART_TX_DONE_INT_RAW_S  14
+/** UART_RS485_PARITY_ERR_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver detects a parity error
+ *  from the echo of transmitter in rs485 mode.
+ */
+#define UART_RS485_PARITY_ERR_INT_RAW    (BIT(15))
+#define UART_RS485_PARITY_ERR_INT_RAW_M  (UART_RS485_PARITY_ERR_INT_RAW_V << UART_RS485_PARITY_ERR_INT_RAW_S)
+#define UART_RS485_PARITY_ERR_INT_RAW_V  0x00000001U
+#define UART_RS485_PARITY_ERR_INT_RAW_S  15
+/** UART_RS485_FRM_ERR_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver detects a data frame error
+ *  from the echo of transmitter in rs485 mode.
+ */
+#define UART_RS485_FRM_ERR_INT_RAW    (BIT(16))
+#define UART_RS485_FRM_ERR_INT_RAW_M  (UART_RS485_FRM_ERR_INT_RAW_V << UART_RS485_FRM_ERR_INT_RAW_S)
+#define UART_RS485_FRM_ERR_INT_RAW_V  0x00000001U
+#define UART_RS485_FRM_ERR_INT_RAW_S  16
+/** UART_RS485_CLASH_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0;
+ *  This interrupt raw bit turns to high level when detects a clash between transmitter
+ *  and receiver in rs485 mode.
+ */
+#define UART_RS485_CLASH_INT_RAW    (BIT(17))
+#define UART_RS485_CLASH_INT_RAW_M  (UART_RS485_CLASH_INT_RAW_V << UART_RS485_CLASH_INT_RAW_S)
+#define UART_RS485_CLASH_INT_RAW_V  0x00000001U
+#define UART_RS485_CLASH_INT_RAW_S  17
+/** UART_AT_CMD_CHAR_DET_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver detects the configured
+ *  at_cmd char.
+ */
+#define UART_AT_CMD_CHAR_DET_INT_RAW    (BIT(18))
+#define UART_AT_CMD_CHAR_DET_INT_RAW_M  (UART_AT_CMD_CHAR_DET_INT_RAW_V << UART_AT_CMD_CHAR_DET_INT_RAW_S)
+#define UART_AT_CMD_CHAR_DET_INT_RAW_V  0x00000001U
+#define UART_AT_CMD_CHAR_DET_INT_RAW_S  18
+/** UART_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0;
+ *  This interrupt raw bit turns to high level when input rxd edge changes more times
+ *  than what reg_active_threshold specifies in light sleeping mode.
+ */
+#define UART_WAKEUP_INT_RAW    (BIT(19))
+#define UART_WAKEUP_INT_RAW_M  (UART_WAKEUP_INT_RAW_V << UART_WAKEUP_INT_RAW_S)
+#define UART_WAKEUP_INT_RAW_V  0x00000001U
+#define UART_WAKEUP_INT_RAW_S  19
+
+/** UART_INT_ST_REG register
+ *  Masked interrupt status
+ */
+#define UART_INT_ST_REG(i) (REG_UART_BASE(i) + 0x8)
+/** UART_RXFIFO_FULL_INT_ST : RO; bitpos: [0]; default: 0;
+ *  This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1.
+ */
+#define UART_RXFIFO_FULL_INT_ST    (BIT(0))
+#define UART_RXFIFO_FULL_INT_ST_M  (UART_RXFIFO_FULL_INT_ST_V << UART_RXFIFO_FULL_INT_ST_S)
+#define UART_RXFIFO_FULL_INT_ST_V  0x00000001U
+#define UART_RXFIFO_FULL_INT_ST_S  0
+/** UART_TXFIFO_EMPTY_INT_ST : RO; bitpos: [1]; default: 0;
+ *  This is the status bit for  txfifo_empty_int_raw  when txfifo_empty_int_ena is set
+ *  to 1.
+ */
+#define UART_TXFIFO_EMPTY_INT_ST    (BIT(1))
+#define UART_TXFIFO_EMPTY_INT_ST_M  (UART_TXFIFO_EMPTY_INT_ST_V << UART_TXFIFO_EMPTY_INT_ST_S)
+#define UART_TXFIFO_EMPTY_INT_ST_V  0x00000001U
+#define UART_TXFIFO_EMPTY_INT_ST_S  1
+/** UART_PARITY_ERR_INT_ST : RO; bitpos: [2]; default: 0;
+ *  This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1.
+ */
+#define UART_PARITY_ERR_INT_ST    (BIT(2))
+#define UART_PARITY_ERR_INT_ST_M  (UART_PARITY_ERR_INT_ST_V << UART_PARITY_ERR_INT_ST_S)
+#define UART_PARITY_ERR_INT_ST_V  0x00000001U
+#define UART_PARITY_ERR_INT_ST_S  2
+/** UART_FRM_ERR_INT_ST : RO; bitpos: [3]; default: 0;
+ *  This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1.
+ */
+#define UART_FRM_ERR_INT_ST    (BIT(3))
+#define UART_FRM_ERR_INT_ST_M  (UART_FRM_ERR_INT_ST_V << UART_FRM_ERR_INT_ST_S)
+#define UART_FRM_ERR_INT_ST_V  0x00000001U
+#define UART_FRM_ERR_INT_ST_S  3
+/** UART_RXFIFO_OVF_INT_ST : RO; bitpos: [4]; default: 0;
+ *  This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1.
+ */
+#define UART_RXFIFO_OVF_INT_ST    (BIT(4))
+#define UART_RXFIFO_OVF_INT_ST_M  (UART_RXFIFO_OVF_INT_ST_V << UART_RXFIFO_OVF_INT_ST_S)
+#define UART_RXFIFO_OVF_INT_ST_V  0x00000001U
+#define UART_RXFIFO_OVF_INT_ST_S  4
+/** UART_DSR_CHG_INT_ST : RO; bitpos: [5]; default: 0;
+ *  This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.
+ */
+#define UART_DSR_CHG_INT_ST    (BIT(5))
+#define UART_DSR_CHG_INT_ST_M  (UART_DSR_CHG_INT_ST_V << UART_DSR_CHG_INT_ST_S)
+#define UART_DSR_CHG_INT_ST_V  0x00000001U
+#define UART_DSR_CHG_INT_ST_S  5
+/** UART_CTS_CHG_INT_ST : RO; bitpos: [6]; default: 0;
+ *  This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.
+ */
+#define UART_CTS_CHG_INT_ST    (BIT(6))
+#define UART_CTS_CHG_INT_ST_M  (UART_CTS_CHG_INT_ST_V << UART_CTS_CHG_INT_ST_S)
+#define UART_CTS_CHG_INT_ST_V  0x00000001U
+#define UART_CTS_CHG_INT_ST_S  6
+/** UART_BRK_DET_INT_ST : RO; bitpos: [7]; default: 0;
+ *  This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.
+ */
+#define UART_BRK_DET_INT_ST    (BIT(7))
+#define UART_BRK_DET_INT_ST_M  (UART_BRK_DET_INT_ST_V << UART_BRK_DET_INT_ST_S)
+#define UART_BRK_DET_INT_ST_V  0x00000001U
+#define UART_BRK_DET_INT_ST_S  7
+/** UART_RXFIFO_TOUT_INT_ST : RO; bitpos: [8]; default: 0;
+ *  This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1.
+ */
+#define UART_RXFIFO_TOUT_INT_ST    (BIT(8))
+#define UART_RXFIFO_TOUT_INT_ST_M  (UART_RXFIFO_TOUT_INT_ST_V << UART_RXFIFO_TOUT_INT_ST_S)
+#define UART_RXFIFO_TOUT_INT_ST_V  0x00000001U
+#define UART_RXFIFO_TOUT_INT_ST_S  8
+/** UART_SW_XON_INT_ST : RO; bitpos: [9]; default: 0;
+ *  This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.
+ */
+#define UART_SW_XON_INT_ST    (BIT(9))
+#define UART_SW_XON_INT_ST_M  (UART_SW_XON_INT_ST_V << UART_SW_XON_INT_ST_S)
+#define UART_SW_XON_INT_ST_V  0x00000001U
+#define UART_SW_XON_INT_ST_S  9
+/** UART_SW_XOFF_INT_ST : RO; bitpos: [10]; default: 0;
+ *  This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.
+ */
+#define UART_SW_XOFF_INT_ST    (BIT(10))
+#define UART_SW_XOFF_INT_ST_M  (UART_SW_XOFF_INT_ST_V << UART_SW_XOFF_INT_ST_S)
+#define UART_SW_XOFF_INT_ST_V  0x00000001U
+#define UART_SW_XOFF_INT_ST_S  10
+/** UART_GLITCH_DET_INT_ST : RO; bitpos: [11]; default: 0;
+ *  This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.
+ */
+#define UART_GLITCH_DET_INT_ST    (BIT(11))
+#define UART_GLITCH_DET_INT_ST_M  (UART_GLITCH_DET_INT_ST_V << UART_GLITCH_DET_INT_ST_S)
+#define UART_GLITCH_DET_INT_ST_V  0x00000001U
+#define UART_GLITCH_DET_INT_ST_S  11
+/** UART_TX_BRK_DONE_INT_ST : RO; bitpos: [12]; default: 0;
+ *  This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.
+ */
+#define UART_TX_BRK_DONE_INT_ST    (BIT(12))
+#define UART_TX_BRK_DONE_INT_ST_M  (UART_TX_BRK_DONE_INT_ST_V << UART_TX_BRK_DONE_INT_ST_S)
+#define UART_TX_BRK_DONE_INT_ST_V  0x00000001U
+#define UART_TX_BRK_DONE_INT_ST_S  12
+/** UART_TX_BRK_IDLE_DONE_INT_ST : RO; bitpos: [13]; default: 0;
+ *  This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena
+ *  is set to 1.
+ */
+#define UART_TX_BRK_IDLE_DONE_INT_ST    (BIT(13))
+#define UART_TX_BRK_IDLE_DONE_INT_ST_M  (UART_TX_BRK_IDLE_DONE_INT_ST_V << UART_TX_BRK_IDLE_DONE_INT_ST_S)
+#define UART_TX_BRK_IDLE_DONE_INT_ST_V  0x00000001U
+#define UART_TX_BRK_IDLE_DONE_INT_ST_S  13
+/** UART_TX_DONE_INT_ST : RO; bitpos: [14]; default: 0;
+ *  This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.
+ */
+#define UART_TX_DONE_INT_ST    (BIT(14))
+#define UART_TX_DONE_INT_ST_M  (UART_TX_DONE_INT_ST_V << UART_TX_DONE_INT_ST_S)
+#define UART_TX_DONE_INT_ST_V  0x00000001U
+#define UART_TX_DONE_INT_ST_S  14
+/** UART_RS485_PARITY_ERR_INT_ST : RO; bitpos: [15]; default: 0;
+ *  This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is
+ *  set to 1.
+ */
+#define UART_RS485_PARITY_ERR_INT_ST    (BIT(15))
+#define UART_RS485_PARITY_ERR_INT_ST_M  (UART_RS485_PARITY_ERR_INT_ST_V << UART_RS485_PARITY_ERR_INT_ST_S)
+#define UART_RS485_PARITY_ERR_INT_ST_V  0x00000001U
+#define UART_RS485_PARITY_ERR_INT_ST_S  15
+/** UART_RS485_FRM_ERR_INT_ST : RO; bitpos: [16]; default: 0;
+ *  This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set
+ *  to 1.
+ */
+#define UART_RS485_FRM_ERR_INT_ST    (BIT(16))
+#define UART_RS485_FRM_ERR_INT_ST_M  (UART_RS485_FRM_ERR_INT_ST_V << UART_RS485_FRM_ERR_INT_ST_S)
+#define UART_RS485_FRM_ERR_INT_ST_V  0x00000001U
+#define UART_RS485_FRM_ERR_INT_ST_S  16
+/** UART_RS485_CLASH_INT_ST : RO; bitpos: [17]; default: 0;
+ *  This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1.
+ */
+#define UART_RS485_CLASH_INT_ST    (BIT(17))
+#define UART_RS485_CLASH_INT_ST_M  (UART_RS485_CLASH_INT_ST_V << UART_RS485_CLASH_INT_ST_S)
+#define UART_RS485_CLASH_INT_ST_V  0x00000001U
+#define UART_RS485_CLASH_INT_ST_S  17
+/** UART_AT_CMD_CHAR_DET_INT_ST : RO; bitpos: [18]; default: 0;
+ *  This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set
+ *  to 1.
+ */
+#define UART_AT_CMD_CHAR_DET_INT_ST    (BIT(18))
+#define UART_AT_CMD_CHAR_DET_INT_ST_M  (UART_AT_CMD_CHAR_DET_INT_ST_V << UART_AT_CMD_CHAR_DET_INT_ST_S)
+#define UART_AT_CMD_CHAR_DET_INT_ST_V  0x00000001U
+#define UART_AT_CMD_CHAR_DET_INT_ST_S  18
+/** UART_WAKEUP_INT_ST : RO; bitpos: [19]; default: 0;
+ *  This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1.
+ */
+#define UART_WAKEUP_INT_ST    (BIT(19))
+#define UART_WAKEUP_INT_ST_M  (UART_WAKEUP_INT_ST_V << UART_WAKEUP_INT_ST_S)
+#define UART_WAKEUP_INT_ST_V  0x00000001U
+#define UART_WAKEUP_INT_ST_S  19
+
+/** UART_INT_ENA_REG register
+ *  Interrupt enable bits
+ */
+#define UART_INT_ENA_REG(i) (REG_UART_BASE(i) + 0xc)
+/** UART_RXFIFO_FULL_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  This is the enable bit for rxfifo_full_int_st register.
+ */
+#define UART_RXFIFO_FULL_INT_ENA    (BIT(0))
+#define UART_RXFIFO_FULL_INT_ENA_M  (UART_RXFIFO_FULL_INT_ENA_V << UART_RXFIFO_FULL_INT_ENA_S)
+#define UART_RXFIFO_FULL_INT_ENA_V  0x00000001U
+#define UART_RXFIFO_FULL_INT_ENA_S  0
+/** UART_TXFIFO_EMPTY_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  This is the enable bit for txfifo_empty_int_st register.
+ */
+#define UART_TXFIFO_EMPTY_INT_ENA    (BIT(1))
+#define UART_TXFIFO_EMPTY_INT_ENA_M  (UART_TXFIFO_EMPTY_INT_ENA_V << UART_TXFIFO_EMPTY_INT_ENA_S)
+#define UART_TXFIFO_EMPTY_INT_ENA_V  0x00000001U
+#define UART_TXFIFO_EMPTY_INT_ENA_S  1
+/** UART_PARITY_ERR_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  This is the enable bit for parity_err_int_st register.
+ */
+#define UART_PARITY_ERR_INT_ENA    (BIT(2))
+#define UART_PARITY_ERR_INT_ENA_M  (UART_PARITY_ERR_INT_ENA_V << UART_PARITY_ERR_INT_ENA_S)
+#define UART_PARITY_ERR_INT_ENA_V  0x00000001U
+#define UART_PARITY_ERR_INT_ENA_S  2
+/** UART_FRM_ERR_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  This is the enable bit for frm_err_int_st register.
+ */
+#define UART_FRM_ERR_INT_ENA    (BIT(3))
+#define UART_FRM_ERR_INT_ENA_M  (UART_FRM_ERR_INT_ENA_V << UART_FRM_ERR_INT_ENA_S)
+#define UART_FRM_ERR_INT_ENA_V  0x00000001U
+#define UART_FRM_ERR_INT_ENA_S  3
+/** UART_RXFIFO_OVF_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  This is the enable bit for rxfifo_ovf_int_st register.
+ */
+#define UART_RXFIFO_OVF_INT_ENA    (BIT(4))
+#define UART_RXFIFO_OVF_INT_ENA_M  (UART_RXFIFO_OVF_INT_ENA_V << UART_RXFIFO_OVF_INT_ENA_S)
+#define UART_RXFIFO_OVF_INT_ENA_V  0x00000001U
+#define UART_RXFIFO_OVF_INT_ENA_S  4
+/** UART_DSR_CHG_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  This is the enable bit for dsr_chg_int_st register.
+ */
+#define UART_DSR_CHG_INT_ENA    (BIT(5))
+#define UART_DSR_CHG_INT_ENA_M  (UART_DSR_CHG_INT_ENA_V << UART_DSR_CHG_INT_ENA_S)
+#define UART_DSR_CHG_INT_ENA_V  0x00000001U
+#define UART_DSR_CHG_INT_ENA_S  5
+/** UART_CTS_CHG_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  This is the enable bit for cts_chg_int_st register.
+ */
+#define UART_CTS_CHG_INT_ENA    (BIT(6))
+#define UART_CTS_CHG_INT_ENA_M  (UART_CTS_CHG_INT_ENA_V << UART_CTS_CHG_INT_ENA_S)
+#define UART_CTS_CHG_INT_ENA_V  0x00000001U
+#define UART_CTS_CHG_INT_ENA_S  6
+/** UART_BRK_DET_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  This is the enable bit for brk_det_int_st register.
+ */
+#define UART_BRK_DET_INT_ENA    (BIT(7))
+#define UART_BRK_DET_INT_ENA_M  (UART_BRK_DET_INT_ENA_V << UART_BRK_DET_INT_ENA_S)
+#define UART_BRK_DET_INT_ENA_V  0x00000001U
+#define UART_BRK_DET_INT_ENA_S  7
+/** UART_RXFIFO_TOUT_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  This is the enable bit for rxfifo_tout_int_st register.
+ */
+#define UART_RXFIFO_TOUT_INT_ENA    (BIT(8))
+#define UART_RXFIFO_TOUT_INT_ENA_M  (UART_RXFIFO_TOUT_INT_ENA_V << UART_RXFIFO_TOUT_INT_ENA_S)
+#define UART_RXFIFO_TOUT_INT_ENA_V  0x00000001U
+#define UART_RXFIFO_TOUT_INT_ENA_S  8
+/** UART_SW_XON_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  This is the enable bit for sw_xon_int_st register.
+ */
+#define UART_SW_XON_INT_ENA    (BIT(9))
+#define UART_SW_XON_INT_ENA_M  (UART_SW_XON_INT_ENA_V << UART_SW_XON_INT_ENA_S)
+#define UART_SW_XON_INT_ENA_V  0x00000001U
+#define UART_SW_XON_INT_ENA_S  9
+/** UART_SW_XOFF_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  This is the enable bit for sw_xoff_int_st register.
+ */
+#define UART_SW_XOFF_INT_ENA    (BIT(10))
+#define UART_SW_XOFF_INT_ENA_M  (UART_SW_XOFF_INT_ENA_V << UART_SW_XOFF_INT_ENA_S)
+#define UART_SW_XOFF_INT_ENA_V  0x00000001U
+#define UART_SW_XOFF_INT_ENA_S  10
+/** UART_GLITCH_DET_INT_ENA : R/W; bitpos: [11]; default: 0;
+ *  This is the enable bit for glitch_det_int_st register.
+ */
+#define UART_GLITCH_DET_INT_ENA    (BIT(11))
+#define UART_GLITCH_DET_INT_ENA_M  (UART_GLITCH_DET_INT_ENA_V << UART_GLITCH_DET_INT_ENA_S)
+#define UART_GLITCH_DET_INT_ENA_V  0x00000001U
+#define UART_GLITCH_DET_INT_ENA_S  11
+/** UART_TX_BRK_DONE_INT_ENA : R/W; bitpos: [12]; default: 0;
+ *  This is the enable bit for tx_brk_done_int_st register.
+ */
+#define UART_TX_BRK_DONE_INT_ENA    (BIT(12))
+#define UART_TX_BRK_DONE_INT_ENA_M  (UART_TX_BRK_DONE_INT_ENA_V << UART_TX_BRK_DONE_INT_ENA_S)
+#define UART_TX_BRK_DONE_INT_ENA_V  0x00000001U
+#define UART_TX_BRK_DONE_INT_ENA_S  12
+/** UART_TX_BRK_IDLE_DONE_INT_ENA : R/W; bitpos: [13]; default: 0;
+ *  This is the enable bit for tx_brk_idle_done_int_st register.
+ */
+#define UART_TX_BRK_IDLE_DONE_INT_ENA    (BIT(13))
+#define UART_TX_BRK_IDLE_DONE_INT_ENA_M  (UART_TX_BRK_IDLE_DONE_INT_ENA_V << UART_TX_BRK_IDLE_DONE_INT_ENA_S)
+#define UART_TX_BRK_IDLE_DONE_INT_ENA_V  0x00000001U
+#define UART_TX_BRK_IDLE_DONE_INT_ENA_S  13
+/** UART_TX_DONE_INT_ENA : R/W; bitpos: [14]; default: 0;
+ *  This is the enable bit for tx_done_int_st register.
+ */
+#define UART_TX_DONE_INT_ENA    (BIT(14))
+#define UART_TX_DONE_INT_ENA_M  (UART_TX_DONE_INT_ENA_V << UART_TX_DONE_INT_ENA_S)
+#define UART_TX_DONE_INT_ENA_V  0x00000001U
+#define UART_TX_DONE_INT_ENA_S  14
+/** UART_RS485_PARITY_ERR_INT_ENA : R/W; bitpos: [15]; default: 0;
+ *  This is the enable bit for rs485_parity_err_int_st register.
+ */
+#define UART_RS485_PARITY_ERR_INT_ENA    (BIT(15))
+#define UART_RS485_PARITY_ERR_INT_ENA_M  (UART_RS485_PARITY_ERR_INT_ENA_V << UART_RS485_PARITY_ERR_INT_ENA_S)
+#define UART_RS485_PARITY_ERR_INT_ENA_V  0x00000001U
+#define UART_RS485_PARITY_ERR_INT_ENA_S  15
+/** UART_RS485_FRM_ERR_INT_ENA : R/W; bitpos: [16]; default: 0;
+ *  This is the enable bit for rs485_parity_err_int_st register.
+ */
+#define UART_RS485_FRM_ERR_INT_ENA    (BIT(16))
+#define UART_RS485_FRM_ERR_INT_ENA_M  (UART_RS485_FRM_ERR_INT_ENA_V << UART_RS485_FRM_ERR_INT_ENA_S)
+#define UART_RS485_FRM_ERR_INT_ENA_V  0x00000001U
+#define UART_RS485_FRM_ERR_INT_ENA_S  16
+/** UART_RS485_CLASH_INT_ENA : R/W; bitpos: [17]; default: 0;
+ *  This is the enable bit for rs485_clash_int_st register.
+ */
+#define UART_RS485_CLASH_INT_ENA    (BIT(17))
+#define UART_RS485_CLASH_INT_ENA_M  (UART_RS485_CLASH_INT_ENA_V << UART_RS485_CLASH_INT_ENA_S)
+#define UART_RS485_CLASH_INT_ENA_V  0x00000001U
+#define UART_RS485_CLASH_INT_ENA_S  17
+/** UART_AT_CMD_CHAR_DET_INT_ENA : R/W; bitpos: [18]; default: 0;
+ *  This is the enable bit for at_cmd_char_det_int_st register.
+ */
+#define UART_AT_CMD_CHAR_DET_INT_ENA    (BIT(18))
+#define UART_AT_CMD_CHAR_DET_INT_ENA_M  (UART_AT_CMD_CHAR_DET_INT_ENA_V << UART_AT_CMD_CHAR_DET_INT_ENA_S)
+#define UART_AT_CMD_CHAR_DET_INT_ENA_V  0x00000001U
+#define UART_AT_CMD_CHAR_DET_INT_ENA_S  18
+/** UART_WAKEUP_INT_ENA : R/W; bitpos: [19]; default: 0;
+ *  This is the enable bit for uart_wakeup_int_st register.
+ */
+#define UART_WAKEUP_INT_ENA    (BIT(19))
+#define UART_WAKEUP_INT_ENA_M  (UART_WAKEUP_INT_ENA_V << UART_WAKEUP_INT_ENA_S)
+#define UART_WAKEUP_INT_ENA_V  0x00000001U
+#define UART_WAKEUP_INT_ENA_S  19
+
+/** UART_INT_CLR_REG register
+ *  Interrupt clear bits
+ */
+#define UART_INT_CLR_REG(i) (REG_UART_BASE(i) + 0x10)
+/** UART_RXFIFO_FULL_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the rxfifo_full_int_raw interrupt.
+ */
+#define UART_RXFIFO_FULL_INT_CLR    (BIT(0))
+#define UART_RXFIFO_FULL_INT_CLR_M  (UART_RXFIFO_FULL_INT_CLR_V << UART_RXFIFO_FULL_INT_CLR_S)
+#define UART_RXFIFO_FULL_INT_CLR_V  0x00000001U
+#define UART_RXFIFO_FULL_INT_CLR_S  0
+/** UART_TXFIFO_EMPTY_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear txfifo_empty_int_raw interrupt.
+ */
+#define UART_TXFIFO_EMPTY_INT_CLR    (BIT(1))
+#define UART_TXFIFO_EMPTY_INT_CLR_M  (UART_TXFIFO_EMPTY_INT_CLR_V << UART_TXFIFO_EMPTY_INT_CLR_S)
+#define UART_TXFIFO_EMPTY_INT_CLR_V  0x00000001U
+#define UART_TXFIFO_EMPTY_INT_CLR_S  1
+/** UART_PARITY_ERR_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear parity_err_int_raw interrupt.
+ */
+#define UART_PARITY_ERR_INT_CLR    (BIT(2))
+#define UART_PARITY_ERR_INT_CLR_M  (UART_PARITY_ERR_INT_CLR_V << UART_PARITY_ERR_INT_CLR_S)
+#define UART_PARITY_ERR_INT_CLR_V  0x00000001U
+#define UART_PARITY_ERR_INT_CLR_S  2
+/** UART_FRM_ERR_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear frm_err_int_raw interrupt.
+ */
+#define UART_FRM_ERR_INT_CLR    (BIT(3))
+#define UART_FRM_ERR_INT_CLR_M  (UART_FRM_ERR_INT_CLR_V << UART_FRM_ERR_INT_CLR_S)
+#define UART_FRM_ERR_INT_CLR_V  0x00000001U
+#define UART_FRM_ERR_INT_CLR_S  3
+/** UART_RXFIFO_OVF_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear rxfifo_ovf_int_raw interrupt.
+ */
+#define UART_RXFIFO_OVF_INT_CLR    (BIT(4))
+#define UART_RXFIFO_OVF_INT_CLR_M  (UART_RXFIFO_OVF_INT_CLR_V << UART_RXFIFO_OVF_INT_CLR_S)
+#define UART_RXFIFO_OVF_INT_CLR_V  0x00000001U
+#define UART_RXFIFO_OVF_INT_CLR_S  4
+/** UART_DSR_CHG_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the dsr_chg_int_raw interrupt.
+ */
+#define UART_DSR_CHG_INT_CLR    (BIT(5))
+#define UART_DSR_CHG_INT_CLR_M  (UART_DSR_CHG_INT_CLR_V << UART_DSR_CHG_INT_CLR_S)
+#define UART_DSR_CHG_INT_CLR_V  0x00000001U
+#define UART_DSR_CHG_INT_CLR_S  5
+/** UART_CTS_CHG_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear the cts_chg_int_raw interrupt.
+ */
+#define UART_CTS_CHG_INT_CLR    (BIT(6))
+#define UART_CTS_CHG_INT_CLR_M  (UART_CTS_CHG_INT_CLR_V << UART_CTS_CHG_INT_CLR_S)
+#define UART_CTS_CHG_INT_CLR_V  0x00000001U
+#define UART_CTS_CHG_INT_CLR_S  6
+/** UART_BRK_DET_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the brk_det_int_raw interrupt.
+ */
+#define UART_BRK_DET_INT_CLR    (BIT(7))
+#define UART_BRK_DET_INT_CLR_M  (UART_BRK_DET_INT_CLR_V << UART_BRK_DET_INT_CLR_S)
+#define UART_BRK_DET_INT_CLR_V  0x00000001U
+#define UART_BRK_DET_INT_CLR_S  7
+/** UART_RXFIFO_TOUT_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the rxfifo_tout_int_raw interrupt.
+ */
+#define UART_RXFIFO_TOUT_INT_CLR    (BIT(8))
+#define UART_RXFIFO_TOUT_INT_CLR_M  (UART_RXFIFO_TOUT_INT_CLR_V << UART_RXFIFO_TOUT_INT_CLR_S)
+#define UART_RXFIFO_TOUT_INT_CLR_V  0x00000001U
+#define UART_RXFIFO_TOUT_INT_CLR_S  8
+/** UART_SW_XON_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Set this bit to clear the sw_xon_int_raw interrupt.
+ */
+#define UART_SW_XON_INT_CLR    (BIT(9))
+#define UART_SW_XON_INT_CLR_M  (UART_SW_XON_INT_CLR_V << UART_SW_XON_INT_CLR_S)
+#define UART_SW_XON_INT_CLR_V  0x00000001U
+#define UART_SW_XON_INT_CLR_S  9
+/** UART_SW_XOFF_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  Set this bit to clear the sw_xoff_int_raw interrupt.
+ */
+#define UART_SW_XOFF_INT_CLR    (BIT(10))
+#define UART_SW_XOFF_INT_CLR_M  (UART_SW_XOFF_INT_CLR_V << UART_SW_XOFF_INT_CLR_S)
+#define UART_SW_XOFF_INT_CLR_V  0x00000001U
+#define UART_SW_XOFF_INT_CLR_S  10
+/** UART_GLITCH_DET_INT_CLR : WT; bitpos: [11]; default: 0;
+ *  Set this bit to clear the glitch_det_int_raw interrupt.
+ */
+#define UART_GLITCH_DET_INT_CLR    (BIT(11))
+#define UART_GLITCH_DET_INT_CLR_M  (UART_GLITCH_DET_INT_CLR_V << UART_GLITCH_DET_INT_CLR_S)
+#define UART_GLITCH_DET_INT_CLR_V  0x00000001U
+#define UART_GLITCH_DET_INT_CLR_S  11
+/** UART_TX_BRK_DONE_INT_CLR : WT; bitpos: [12]; default: 0;
+ *  Set this bit to clear the tx_brk_done_int_raw interrupt..
+ */
+#define UART_TX_BRK_DONE_INT_CLR    (BIT(12))
+#define UART_TX_BRK_DONE_INT_CLR_M  (UART_TX_BRK_DONE_INT_CLR_V << UART_TX_BRK_DONE_INT_CLR_S)
+#define UART_TX_BRK_DONE_INT_CLR_V  0x00000001U
+#define UART_TX_BRK_DONE_INT_CLR_S  12
+/** UART_TX_BRK_IDLE_DONE_INT_CLR : WT; bitpos: [13]; default: 0;
+ *  Set this bit to clear the tx_brk_idle_done_int_raw interrupt.
+ */
+#define UART_TX_BRK_IDLE_DONE_INT_CLR    (BIT(13))
+#define UART_TX_BRK_IDLE_DONE_INT_CLR_M  (UART_TX_BRK_IDLE_DONE_INT_CLR_V << UART_TX_BRK_IDLE_DONE_INT_CLR_S)
+#define UART_TX_BRK_IDLE_DONE_INT_CLR_V  0x00000001U
+#define UART_TX_BRK_IDLE_DONE_INT_CLR_S  13
+/** UART_TX_DONE_INT_CLR : WT; bitpos: [14]; default: 0;
+ *  Set this bit to clear the tx_done_int_raw interrupt.
+ */
+#define UART_TX_DONE_INT_CLR    (BIT(14))
+#define UART_TX_DONE_INT_CLR_M  (UART_TX_DONE_INT_CLR_V << UART_TX_DONE_INT_CLR_S)
+#define UART_TX_DONE_INT_CLR_V  0x00000001U
+#define UART_TX_DONE_INT_CLR_S  14
+/** UART_RS485_PARITY_ERR_INT_CLR : WT; bitpos: [15]; default: 0;
+ *  Set this bit to clear the rs485_parity_err_int_raw interrupt.
+ */
+#define UART_RS485_PARITY_ERR_INT_CLR    (BIT(15))
+#define UART_RS485_PARITY_ERR_INT_CLR_M  (UART_RS485_PARITY_ERR_INT_CLR_V << UART_RS485_PARITY_ERR_INT_CLR_S)
+#define UART_RS485_PARITY_ERR_INT_CLR_V  0x00000001U
+#define UART_RS485_PARITY_ERR_INT_CLR_S  15
+/** UART_RS485_FRM_ERR_INT_CLR : WT; bitpos: [16]; default: 0;
+ *  Set this bit to clear the rs485_frm_err_int_raw interrupt.
+ */
+#define UART_RS485_FRM_ERR_INT_CLR    (BIT(16))
+#define UART_RS485_FRM_ERR_INT_CLR_M  (UART_RS485_FRM_ERR_INT_CLR_V << UART_RS485_FRM_ERR_INT_CLR_S)
+#define UART_RS485_FRM_ERR_INT_CLR_V  0x00000001U
+#define UART_RS485_FRM_ERR_INT_CLR_S  16
+/** UART_RS485_CLASH_INT_CLR : WT; bitpos: [17]; default: 0;
+ *  Set this bit to clear the rs485_clash_int_raw interrupt.
+ */
+#define UART_RS485_CLASH_INT_CLR    (BIT(17))
+#define UART_RS485_CLASH_INT_CLR_M  (UART_RS485_CLASH_INT_CLR_V << UART_RS485_CLASH_INT_CLR_S)
+#define UART_RS485_CLASH_INT_CLR_V  0x00000001U
+#define UART_RS485_CLASH_INT_CLR_S  17
+/** UART_AT_CMD_CHAR_DET_INT_CLR : WT; bitpos: [18]; default: 0;
+ *  Set this bit to clear the at_cmd_char_det_int_raw interrupt.
+ */
+#define UART_AT_CMD_CHAR_DET_INT_CLR    (BIT(18))
+#define UART_AT_CMD_CHAR_DET_INT_CLR_M  (UART_AT_CMD_CHAR_DET_INT_CLR_V << UART_AT_CMD_CHAR_DET_INT_CLR_S)
+#define UART_AT_CMD_CHAR_DET_INT_CLR_V  0x00000001U
+#define UART_AT_CMD_CHAR_DET_INT_CLR_S  18
+/** UART_WAKEUP_INT_CLR : WT; bitpos: [19]; default: 0;
+ *  Set this bit to clear the uart_wakeup_int_raw interrupt.
+ */
+#define UART_WAKEUP_INT_CLR    (BIT(19))
+#define UART_WAKEUP_INT_CLR_M  (UART_WAKEUP_INT_CLR_V << UART_WAKEUP_INT_CLR_S)
+#define UART_WAKEUP_INT_CLR_V  0x00000001U
+#define UART_WAKEUP_INT_CLR_S  19
+
+/** UART_CLKDIV_SYNC_REG register
+ *  Clock divider configuration
+ */
+#define UART_CLKDIV_SYNC_REG(i) (REG_UART_BASE(i) + 0x14)
+/** UART_CLKDIV : R/W; bitpos: [11:0]; default: 694;
+ *  The integral part of the frequency divider factor.
+ */
+#define UART_CLKDIV    0x00000FFFU
+#define UART_CLKDIV_M  (UART_CLKDIV_V << UART_CLKDIV_S)
+#define UART_CLKDIV_V  0x00000FFFU
+#define UART_CLKDIV_S  0
+/** UART_CLKDIV_FRAG : R/W; bitpos: [23:20]; default: 0;
+ *  The decimal part of the frequency divider factor.
+ */
+#define UART_CLKDIV_FRAG    0x0000000FU
+#define UART_CLKDIV_FRAG_M  (UART_CLKDIV_FRAG_V << UART_CLKDIV_FRAG_S)
+#define UART_CLKDIV_FRAG_V  0x0000000FU
+#define UART_CLKDIV_FRAG_S  20
+
+/** UART_RX_FILT_REG register
+ *  Rx Filter configuration
+ */
+#define UART_RX_FILT_REG(i) (REG_UART_BASE(i) + 0x18)
+/** UART_GLITCH_FILT : R/W; bitpos: [7:0]; default: 8;
+ *  when input pulse width is lower than this value the pulse is ignored.
+ */
+#define UART_GLITCH_FILT    0x000000FFU
+#define UART_GLITCH_FILT_M  (UART_GLITCH_FILT_V << UART_GLITCH_FILT_S)
+#define UART_GLITCH_FILT_V  0x000000FFU
+#define UART_GLITCH_FILT_S  0
+/** UART_GLITCH_FILT_EN : R/W; bitpos: [8]; default: 0;
+ *  Set this bit to enable Rx signal filter.
+ */
+#define UART_GLITCH_FILT_EN    (BIT(8))
+#define UART_GLITCH_FILT_EN_M  (UART_GLITCH_FILT_EN_V << UART_GLITCH_FILT_EN_S)
+#define UART_GLITCH_FILT_EN_V  0x00000001U
+#define UART_GLITCH_FILT_EN_S  8
+
+/** UART_STATUS_REG register
+ *  UART status register
+ */
+#define UART_STATUS_REG(i) (REG_UART_BASE(i) + 0x1c)
+/** UART_RXFIFO_CNT : RO; bitpos: [7:0]; default: 0;
+ *  Stores the byte number of valid data in Rx-FIFO.
+ */
+#define UART_RXFIFO_CNT    0x000000FFU
+#define UART_RXFIFO_CNT_M  (UART_RXFIFO_CNT_V << UART_RXFIFO_CNT_S)
+#define UART_RXFIFO_CNT_V  0x000000FFU
+#define UART_RXFIFO_CNT_S  0
+/** UART_DSRN : RO; bitpos: [13]; default: 0;
+ *  The register represent the level value of the internal uart dsr signal.
+ */
+#define UART_DSRN    (BIT(13))
+#define UART_DSRN_M  (UART_DSRN_V << UART_DSRN_S)
+#define UART_DSRN_V  0x00000001U
+#define UART_DSRN_S  13
+/** UART_CTSN : RO; bitpos: [14]; default: 1;
+ *  This register represent the level value of the internal uart cts signal.
+ */
+#define UART_CTSN    (BIT(14))
+#define UART_CTSN_M  (UART_CTSN_V << UART_CTSN_S)
+#define UART_CTSN_V  0x00000001U
+#define UART_CTSN_S  14
+/** UART_RXD : RO; bitpos: [15]; default: 1;
+ *  This register represent the  level value of the internal uart rxd signal.
+ */
+#define UART_RXD    (BIT(15))
+#define UART_RXD_M  (UART_RXD_V << UART_RXD_S)
+#define UART_RXD_V  0x00000001U
+#define UART_RXD_S  15
+/** UART_TXFIFO_CNT : RO; bitpos: [23:16]; default: 0;
+ *  Stores the byte number of data in Tx-FIFO.
+ */
+#define UART_TXFIFO_CNT    0x000000FFU
+#define UART_TXFIFO_CNT_M  (UART_TXFIFO_CNT_V << UART_TXFIFO_CNT_S)
+#define UART_TXFIFO_CNT_V  0x000000FFU
+#define UART_TXFIFO_CNT_S  16
+/** UART_DTRN : RO; bitpos: [29]; default: 1;
+ *  This bit represents the level of the internal uart dtr signal.
+ */
+#define UART_DTRN    (BIT(29))
+#define UART_DTRN_M  (UART_DTRN_V << UART_DTRN_S)
+#define UART_DTRN_V  0x00000001U
+#define UART_DTRN_S  29
+/** UART_RTSN : RO; bitpos: [30]; default: 1;
+ *  This bit represents the level of the internal uart rts signal.
+ */
+#define UART_RTSN    (BIT(30))
+#define UART_RTSN_M  (UART_RTSN_V << UART_RTSN_S)
+#define UART_RTSN_V  0x00000001U
+#define UART_RTSN_S  30
+/** UART_TXD : RO; bitpos: [31]; default: 1;
+ *  This bit represents the  level of the internal uart txd signal.
+ */
+#define UART_TXD    (BIT(31))
+#define UART_TXD_M  (UART_TXD_V << UART_TXD_S)
+#define UART_TXD_V  0x00000001U
+#define UART_TXD_S  31
+
+/** UART_CONF0_SYNC_REG register
+ *  a
+ */
+#define UART_CONF0_SYNC_REG(i) (REG_UART_BASE(i) + 0x20)
+/** UART_PARITY : R/W; bitpos: [0]; default: 0;
+ *  This register is used to configure the parity check mode.
+ */
+#define UART_PARITY    (BIT(0))
+#define UART_PARITY_M  (UART_PARITY_V << UART_PARITY_S)
+#define UART_PARITY_V  0x00000001U
+#define UART_PARITY_S  0
+/** UART_PARITY_EN : R/W; bitpos: [1]; default: 0;
+ *  Set this bit to enable uart parity check.
+ */
+#define UART_PARITY_EN    (BIT(1))
+#define UART_PARITY_EN_M  (UART_PARITY_EN_V << UART_PARITY_EN_S)
+#define UART_PARITY_EN_V  0x00000001U
+#define UART_PARITY_EN_S  1
+/** UART_BIT_NUM : R/W; bitpos: [3:2]; default: 3;
+ *  This register is used to set the length of data.
+ */
+#define UART_BIT_NUM    0x00000003U
+#define UART_BIT_NUM_M  (UART_BIT_NUM_V << UART_BIT_NUM_S)
+#define UART_BIT_NUM_V  0x00000003U
+#define UART_BIT_NUM_S  2
+/** UART_STOP_BIT_NUM : R/W; bitpos: [5:4]; default: 1;
+ *  This register is used to set the length of  stop bit.
+ */
+#define UART_STOP_BIT_NUM    0x00000003U
+#define UART_STOP_BIT_NUM_M  (UART_STOP_BIT_NUM_V << UART_STOP_BIT_NUM_S)
+#define UART_STOP_BIT_NUM_V  0x00000003U
+#define UART_STOP_BIT_NUM_S  4
+/** UART_TXD_BRK : R/W; bitpos: [6]; default: 0;
+ *  Set this bit to enbale transmitter to  send NULL when the process of sending data
+ *  is done.
+ */
+#define UART_TXD_BRK    (BIT(6))
+#define UART_TXD_BRK_M  (UART_TXD_BRK_V << UART_TXD_BRK_S)
+#define UART_TXD_BRK_V  0x00000001U
+#define UART_TXD_BRK_S  6
+/** UART_IRDA_DPLX : R/W; bitpos: [7]; default: 0;
+ *  Set this bit to enable IrDA loopback mode.
+ */
+#define UART_IRDA_DPLX    (BIT(7))
+#define UART_IRDA_DPLX_M  (UART_IRDA_DPLX_V << UART_IRDA_DPLX_S)
+#define UART_IRDA_DPLX_V  0x00000001U
+#define UART_IRDA_DPLX_S  7
+/** UART_IRDA_TX_EN : R/W; bitpos: [8]; default: 0;
+ *  This is the start enable bit for IrDA transmitter.
+ */
+#define UART_IRDA_TX_EN    (BIT(8))
+#define UART_IRDA_TX_EN_M  (UART_IRDA_TX_EN_V << UART_IRDA_TX_EN_S)
+#define UART_IRDA_TX_EN_V  0x00000001U
+#define UART_IRDA_TX_EN_S  8
+/** UART_IRDA_WCTL : R/W; bitpos: [9]; default: 0;
+ *  1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA
+ *  transmitter's 11th bit to 0.
+ */
+#define UART_IRDA_WCTL    (BIT(9))
+#define UART_IRDA_WCTL_M  (UART_IRDA_WCTL_V << UART_IRDA_WCTL_S)
+#define UART_IRDA_WCTL_V  0x00000001U
+#define UART_IRDA_WCTL_S  9
+/** UART_IRDA_TX_INV : R/W; bitpos: [10]; default: 0;
+ *  Set this bit to invert the level of  IrDA transmitter.
+ */
+#define UART_IRDA_TX_INV    (BIT(10))
+#define UART_IRDA_TX_INV_M  (UART_IRDA_TX_INV_V << UART_IRDA_TX_INV_S)
+#define UART_IRDA_TX_INV_V  0x00000001U
+#define UART_IRDA_TX_INV_S  10
+/** UART_IRDA_RX_INV : R/W; bitpos: [11]; default: 0;
+ *  Set this bit to invert the level of IrDA receiver.
+ */
+#define UART_IRDA_RX_INV    (BIT(11))
+#define UART_IRDA_RX_INV_M  (UART_IRDA_RX_INV_V << UART_IRDA_RX_INV_S)
+#define UART_IRDA_RX_INV_V  0x00000001U
+#define UART_IRDA_RX_INV_S  11
+/** UART_LOOPBACK : R/W; bitpos: [12]; default: 0;
+ *  Set this bit to enable uart loopback test mode.
+ */
+#define UART_LOOPBACK    (BIT(12))
+#define UART_LOOPBACK_M  (UART_LOOPBACK_V << UART_LOOPBACK_S)
+#define UART_LOOPBACK_V  0x00000001U
+#define UART_LOOPBACK_S  12
+/** UART_TX_FLOW_EN : R/W; bitpos: [13]; default: 0;
+ *  Set this bit to enable flow control function for transmitter.
+ */
+#define UART_TX_FLOW_EN    (BIT(13))
+#define UART_TX_FLOW_EN_M  (UART_TX_FLOW_EN_V << UART_TX_FLOW_EN_S)
+#define UART_TX_FLOW_EN_V  0x00000001U
+#define UART_TX_FLOW_EN_S  13
+/** UART_IRDA_EN : R/W; bitpos: [14]; default: 0;
+ *  Set this bit to enable IrDA protocol.
+ */
+#define UART_IRDA_EN    (BIT(14))
+#define UART_IRDA_EN_M  (UART_IRDA_EN_V << UART_IRDA_EN_S)
+#define UART_IRDA_EN_V  0x00000001U
+#define UART_IRDA_EN_S  14
+/** UART_RXD_INV : R/W; bitpos: [15]; default: 0;
+ *  Set this bit to inverse the level value of uart rxd signal.
+ */
+#define UART_RXD_INV    (BIT(15))
+#define UART_RXD_INV_M  (UART_RXD_INV_V << UART_RXD_INV_S)
+#define UART_RXD_INV_V  0x00000001U
+#define UART_RXD_INV_S  15
+/** UART_TXD_INV : R/W; bitpos: [16]; default: 0;
+ *  Set this bit to inverse the level value of uart txd signal.
+ */
+#define UART_TXD_INV    (BIT(16))
+#define UART_TXD_INV_M  (UART_TXD_INV_V << UART_TXD_INV_S)
+#define UART_TXD_INV_V  0x00000001U
+#define UART_TXD_INV_S  16
+/** UART_DIS_RX_DAT_OVF : R/W; bitpos: [17]; default: 0;
+ *  Disable UART Rx data overflow detect.
+ */
+#define UART_DIS_RX_DAT_OVF    (BIT(17))
+#define UART_DIS_RX_DAT_OVF_M  (UART_DIS_RX_DAT_OVF_V << UART_DIS_RX_DAT_OVF_S)
+#define UART_DIS_RX_DAT_OVF_V  0x00000001U
+#define UART_DIS_RX_DAT_OVF_S  17
+/** UART_ERR_WR_MASK : R/W; bitpos: [18]; default: 0;
+ *  1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver
+ *  stores the data even if the  received data is wrong.
+ */
+#define UART_ERR_WR_MASK    (BIT(18))
+#define UART_ERR_WR_MASK_M  (UART_ERR_WR_MASK_V << UART_ERR_WR_MASK_S)
+#define UART_ERR_WR_MASK_V  0x00000001U
+#define UART_ERR_WR_MASK_S  18
+/** UART_AUTOBAUD_EN : R/W; bitpos: [19]; default: 0;
+ *  This is the enable bit for detecting baudrate.
+ */
+#define UART_AUTOBAUD_EN    (BIT(19))
+#define UART_AUTOBAUD_EN_M  (UART_AUTOBAUD_EN_V << UART_AUTOBAUD_EN_S)
+#define UART_AUTOBAUD_EN_V  0x00000001U
+#define UART_AUTOBAUD_EN_S  19
+/** UART_MEM_CLK_EN : R/W; bitpos: [20]; default: 0;
+ *  UART memory clock gate enable signal.
+ */
+#define UART_MEM_CLK_EN    (BIT(20))
+#define UART_MEM_CLK_EN_M  (UART_MEM_CLK_EN_V << UART_MEM_CLK_EN_S)
+#define UART_MEM_CLK_EN_V  0x00000001U
+#define UART_MEM_CLK_EN_S  20
+/** UART_SW_RTS : R/W; bitpos: [21]; default: 0;
+ *  This register is used to configure the software rts signal which is used in
+ *  software flow control.
+ */
+#define UART_SW_RTS    (BIT(21))
+#define UART_SW_RTS_M  (UART_SW_RTS_V << UART_SW_RTS_S)
+#define UART_SW_RTS_V  0x00000001U
+#define UART_SW_RTS_S  21
+/** UART_RXFIFO_RST : R/W; bitpos: [22]; default: 0;
+ *  Set this bit to reset the uart receive-FIFO.
+ */
+#define UART_RXFIFO_RST    (BIT(22))
+#define UART_RXFIFO_RST_M  (UART_RXFIFO_RST_V << UART_RXFIFO_RST_S)
+#define UART_RXFIFO_RST_V  0x00000001U
+#define UART_RXFIFO_RST_S  22
+/** UART_TXFIFO_RST : R/W; bitpos: [23]; default: 0;
+ *  Set this bit to reset the uart transmit-FIFO.
+ */
+#define UART_TXFIFO_RST    (BIT(23))
+#define UART_TXFIFO_RST_M  (UART_TXFIFO_RST_V << UART_TXFIFO_RST_S)
+#define UART_TXFIFO_RST_V  0x00000001U
+#define UART_TXFIFO_RST_S  23
+
+/** UART_CONF1_REG register
+ *  Configuration register 1
+ */
+#define UART_CONF1_REG(i) (REG_UART_BASE(i) + 0x24)
+/** UART_RXFIFO_FULL_THRHD : R/W; bitpos: [7:0]; default: 96;
+ *  It will produce rxfifo_full_int interrupt when receiver receives more data than
+ *  this register value.
+ */
+#define UART_RXFIFO_FULL_THRHD    0x000000FFU
+#define UART_RXFIFO_FULL_THRHD_M  (UART_RXFIFO_FULL_THRHD_V << UART_RXFIFO_FULL_THRHD_S)
+#define UART_RXFIFO_FULL_THRHD_V  0x000000FFU
+#define UART_RXFIFO_FULL_THRHD_S  0
+/** UART_TXFIFO_EMPTY_THRHD : R/W; bitpos: [15:8]; default: 96;
+ *  It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less
+ *  than this register value.
+ */
+#define UART_TXFIFO_EMPTY_THRHD    0x000000FFU
+#define UART_TXFIFO_EMPTY_THRHD_M  (UART_TXFIFO_EMPTY_THRHD_V << UART_TXFIFO_EMPTY_THRHD_S)
+#define UART_TXFIFO_EMPTY_THRHD_V  0x000000FFU
+#define UART_TXFIFO_EMPTY_THRHD_S  8
+/** UART_CTS_INV : R/W; bitpos: [16]; default: 0;
+ *  Set this bit to inverse the level value of uart cts signal.
+ */
+#define UART_CTS_INV    (BIT(16))
+#define UART_CTS_INV_M  (UART_CTS_INV_V << UART_CTS_INV_S)
+#define UART_CTS_INV_V  0x00000001U
+#define UART_CTS_INV_S  16
+/** UART_DSR_INV : R/W; bitpos: [17]; default: 0;
+ *  Set this bit to inverse the level value of uart dsr signal.
+ */
+#define UART_DSR_INV    (BIT(17))
+#define UART_DSR_INV_M  (UART_DSR_INV_V << UART_DSR_INV_S)
+#define UART_DSR_INV_V  0x00000001U
+#define UART_DSR_INV_S  17
+/** UART_RTS_INV : R/W; bitpos: [18]; default: 0;
+ *  Set this bit to inverse the level value of uart rts signal.
+ */
+#define UART_RTS_INV    (BIT(18))
+#define UART_RTS_INV_M  (UART_RTS_INV_V << UART_RTS_INV_S)
+#define UART_RTS_INV_V  0x00000001U
+#define UART_RTS_INV_S  18
+/** UART_DTR_INV : R/W; bitpos: [19]; default: 0;
+ *  Set this bit to inverse the level value of uart dtr signal.
+ */
+#define UART_DTR_INV    (BIT(19))
+#define UART_DTR_INV_M  (UART_DTR_INV_V << UART_DTR_INV_S)
+#define UART_DTR_INV_V  0x00000001U
+#define UART_DTR_INV_S  19
+/** UART_SW_DTR : R/W; bitpos: [20]; default: 0;
+ *  This register is used to configure the software dtr signal which is used in
+ *  software flow control.
+ */
+#define UART_SW_DTR    (BIT(20))
+#define UART_SW_DTR_M  (UART_SW_DTR_V << UART_SW_DTR_S)
+#define UART_SW_DTR_V  0x00000001U
+#define UART_SW_DTR_S  20
+/** UART_CLK_EN : R/W; bitpos: [21]; default: 0;
+ *  1'h1: Force clock on for register. 1'h0: Support clock only when application writes
+ *  registers.
+ */
+#define UART_CLK_EN    (BIT(21))
+#define UART_CLK_EN_M  (UART_CLK_EN_V << UART_CLK_EN_S)
+#define UART_CLK_EN_V  0x00000001U
+#define UART_CLK_EN_S  21
+
+/** UART_HWFC_CONF_SYNC_REG register
+ *  Hardware flow-control configuration
+ */
+#define UART_HWFC_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x2c)
+/** UART_RX_FLOW_THRHD : R/W; bitpos: [7:0]; default: 0;
+ *  This register is used to configure the maximum amount of data that can be received
+ *  when hardware flow control works.
+ */
+#define UART_RX_FLOW_THRHD    0x000000FFU
+#define UART_RX_FLOW_THRHD_M  (UART_RX_FLOW_THRHD_V << UART_RX_FLOW_THRHD_S)
+#define UART_RX_FLOW_THRHD_V  0x000000FFU
+#define UART_RX_FLOW_THRHD_S  0
+/** UART_RX_FLOW_EN : R/W; bitpos: [8]; default: 0;
+ *  This is the flow enable bit for UART receiver.
+ */
+#define UART_RX_FLOW_EN    (BIT(8))
+#define UART_RX_FLOW_EN_M  (UART_RX_FLOW_EN_V << UART_RX_FLOW_EN_S)
+#define UART_RX_FLOW_EN_V  0x00000001U
+#define UART_RX_FLOW_EN_S  8
+
+/** UART_SLEEP_CONF0_REG register
+ *  UART sleep configure register 0
+ */
+#define UART_SLEEP_CONF0_REG(i) (REG_UART_BASE(i) + 0x30)
+/** UART_WK_CHAR1 : R/W; bitpos: [7:0]; default: 0;
+ *  This register restores the specified wake up char1 to wake up
+ */
+#define UART_WK_CHAR1    0x000000FFU
+#define UART_WK_CHAR1_M  (UART_WK_CHAR1_V << UART_WK_CHAR1_S)
+#define UART_WK_CHAR1_V  0x000000FFU
+#define UART_WK_CHAR1_S  0
+/** UART_WK_CHAR2 : R/W; bitpos: [15:8]; default: 0;
+ *  This register restores the specified wake up char2 to wake up
+ */
+#define UART_WK_CHAR2    0x000000FFU
+#define UART_WK_CHAR2_M  (UART_WK_CHAR2_V << UART_WK_CHAR2_S)
+#define UART_WK_CHAR2_V  0x000000FFU
+#define UART_WK_CHAR2_S  8
+/** UART_WK_CHAR3 : R/W; bitpos: [23:16]; default: 0;
+ *  This register restores the specified wake up char3 to wake up
+ */
+#define UART_WK_CHAR3    0x000000FFU
+#define UART_WK_CHAR3_M  (UART_WK_CHAR3_V << UART_WK_CHAR3_S)
+#define UART_WK_CHAR3_V  0x000000FFU
+#define UART_WK_CHAR3_S  16
+/** UART_WK_CHAR4 : R/W; bitpos: [31:24]; default: 0;
+ *  This register restores the specified wake up char4 to wake up
+ */
+#define UART_WK_CHAR4    0x000000FFU
+#define UART_WK_CHAR4_M  (UART_WK_CHAR4_V << UART_WK_CHAR4_S)
+#define UART_WK_CHAR4_V  0x000000FFU
+#define UART_WK_CHAR4_S  24
+
+/** UART_SLEEP_CONF1_REG register
+ *  UART sleep configure register 1
+ */
+#define UART_SLEEP_CONF1_REG(i) (REG_UART_BASE(i) + 0x34)
+/** UART_WK_CHAR0 : R/W; bitpos: [7:0]; default: 0;
+ *  This register restores the specified char0 to wake up
+ */
+#define UART_WK_CHAR0    0x000000FFU
+#define UART_WK_CHAR0_M  (UART_WK_CHAR0_V << UART_WK_CHAR0_S)
+#define UART_WK_CHAR0_V  0x000000FFU
+#define UART_WK_CHAR0_S  0
+
+/** UART_SLEEP_CONF2_REG register
+ *  UART sleep configure register 2
+ */
+#define UART_SLEEP_CONF2_REG(i) (REG_UART_BASE(i) + 0x38)
+/** UART_ACTIVE_THRESHOLD : R/W; bitpos: [9:0]; default: 240;
+ *  The uart is activated from light sleeping mode when the input rxd edge changes more
+ *  times than this register value.
+ */
+#define UART_ACTIVE_THRESHOLD    0x000003FFU
+#define UART_ACTIVE_THRESHOLD_M  (UART_ACTIVE_THRESHOLD_V << UART_ACTIVE_THRESHOLD_S)
+#define UART_ACTIVE_THRESHOLD_V  0x000003FFU
+#define UART_ACTIVE_THRESHOLD_S  0
+/** UART_RX_WAKE_UP_THRHD : R/W; bitpos: [17:10]; default: 1;
+ *  In wake up mode 1 this field is used to set the received data number threshold to
+ *  wake up chip.
+ */
+#define UART_RX_WAKE_UP_THRHD    0x000000FFU
+#define UART_RX_WAKE_UP_THRHD_M  (UART_RX_WAKE_UP_THRHD_V << UART_RX_WAKE_UP_THRHD_S)
+#define UART_RX_WAKE_UP_THRHD_V  0x000000FFU
+#define UART_RX_WAKE_UP_THRHD_S  10
+/** UART_WK_CHAR_NUM : R/W; bitpos: [20:18]; default: 5;
+ *  This register is used to select number of wake up char.
+ */
+#define UART_WK_CHAR_NUM    0x00000007U
+#define UART_WK_CHAR_NUM_M  (UART_WK_CHAR_NUM_V << UART_WK_CHAR_NUM_S)
+#define UART_WK_CHAR_NUM_V  0x00000007U
+#define UART_WK_CHAR_NUM_S  18
+/** UART_WK_CHAR_MASK : R/W; bitpos: [25:21]; default: 0;
+ *  This register is used to mask  wake up char.
+ */
+#define UART_WK_CHAR_MASK    0x0000001FU
+#define UART_WK_CHAR_MASK_M  (UART_WK_CHAR_MASK_V << UART_WK_CHAR_MASK_S)
+#define UART_WK_CHAR_MASK_V  0x0000001FU
+#define UART_WK_CHAR_MASK_S  21
+/** UART_WK_MODE_SEL : R/W; bitpos: [27:26]; default: 0;
+ *  This register is used to select wake up mode. 0: RXD toggling to wake up. 1:
+ *  received data number larger than
+ */
+#define UART_WK_MODE_SEL    0x00000003U
+#define UART_WK_MODE_SEL_M  (UART_WK_MODE_SEL_V << UART_WK_MODE_SEL_S)
+#define UART_WK_MODE_SEL_V  0x00000003U
+#define UART_WK_MODE_SEL_S  26
+
+/** UART_SWFC_CONF0_SYNC_REG register
+ *  Software flow-control character configuration
+ */
+#define UART_SWFC_CONF0_SYNC_REG(i) (REG_UART_BASE(i) + 0x3c)
+/** UART_XON_CHAR : R/W; bitpos: [7:0]; default: 17;
+ *  This register stores the Xon flow control char.
+ */
+#define UART_XON_CHAR    0x000000FFU
+#define UART_XON_CHAR_M  (UART_XON_CHAR_V << UART_XON_CHAR_S)
+#define UART_XON_CHAR_V  0x000000FFU
+#define UART_XON_CHAR_S  0
+/** UART_XOFF_CHAR : R/W; bitpos: [15:8]; default: 19;
+ *  This register stores the Xoff flow control char.
+ */
+#define UART_XOFF_CHAR    0x000000FFU
+#define UART_XOFF_CHAR_M  (UART_XOFF_CHAR_V << UART_XOFF_CHAR_S)
+#define UART_XOFF_CHAR_V  0x000000FFU
+#define UART_XOFF_CHAR_S  8
+/** UART_XON_XOFF_STILL_SEND : R/W; bitpos: [16]; default: 0;
+ *  In software flow control mode, UART Tx is disabled once UART Rx receives XOFF. In
+ *  this status, UART Tx can not transmit XOFF even the received data number is larger
+ *  than UART_XOFF_THRESHOLD. Set this bit to enable UART Tx can transmit XON/XOFF when
+ *  UART Tx is disabled.
+ */
+#define UART_XON_XOFF_STILL_SEND    (BIT(16))
+#define UART_XON_XOFF_STILL_SEND_M  (UART_XON_XOFF_STILL_SEND_V << UART_XON_XOFF_STILL_SEND_S)
+#define UART_XON_XOFF_STILL_SEND_V  0x00000001U
+#define UART_XON_XOFF_STILL_SEND_S  16
+/** UART_SW_FLOW_CON_EN : R/W; bitpos: [17]; default: 0;
+ *  Set this bit to enable software flow control. It is used with register sw_xon or
+ *  sw_xoff.
+ */
+#define UART_SW_FLOW_CON_EN    (BIT(17))
+#define UART_SW_FLOW_CON_EN_M  (UART_SW_FLOW_CON_EN_V << UART_SW_FLOW_CON_EN_S)
+#define UART_SW_FLOW_CON_EN_V  0x00000001U
+#define UART_SW_FLOW_CON_EN_S  17
+/** UART_XONOFF_DEL : R/W; bitpos: [18]; default: 0;
+ *  Set this bit to remove flow control char from the received data.
+ */
+#define UART_XONOFF_DEL    (BIT(18))
+#define UART_XONOFF_DEL_M  (UART_XONOFF_DEL_V << UART_XONOFF_DEL_S)
+#define UART_XONOFF_DEL_V  0x00000001U
+#define UART_XONOFF_DEL_S  18
+/** UART_FORCE_XON : R/W; bitpos: [19]; default: 0;
+ *  Set this bit to enable the transmitter to go on sending data.
+ */
+#define UART_FORCE_XON    (BIT(19))
+#define UART_FORCE_XON_M  (UART_FORCE_XON_V << UART_FORCE_XON_S)
+#define UART_FORCE_XON_V  0x00000001U
+#define UART_FORCE_XON_S  19
+/** UART_FORCE_XOFF : R/W; bitpos: [20]; default: 0;
+ *  Set this bit to stop the  transmitter from sending data.
+ */
+#define UART_FORCE_XOFF    (BIT(20))
+#define UART_FORCE_XOFF_M  (UART_FORCE_XOFF_V << UART_FORCE_XOFF_S)
+#define UART_FORCE_XOFF_V  0x00000001U
+#define UART_FORCE_XOFF_S  20
+/** UART_SEND_XON : R/W/SS/SC; bitpos: [21]; default: 0;
+ *  Set this bit to send Xon char. It is cleared by hardware automatically.
+ */
+#define UART_SEND_XON    (BIT(21))
+#define UART_SEND_XON_M  (UART_SEND_XON_V << UART_SEND_XON_S)
+#define UART_SEND_XON_V  0x00000001U
+#define UART_SEND_XON_S  21
+/** UART_SEND_XOFF : R/W/SS/SC; bitpos: [22]; default: 0;
+ *  Set this bit to send Xoff char. It is cleared by hardware automatically.
+ */
+#define UART_SEND_XOFF    (BIT(22))
+#define UART_SEND_XOFF_M  (UART_SEND_XOFF_V << UART_SEND_XOFF_S)
+#define UART_SEND_XOFF_V  0x00000001U
+#define UART_SEND_XOFF_S  22
+
+/** UART_SWFC_CONF1_REG register
+ *  Software flow-control character configuration
+ */
+#define UART_SWFC_CONF1_REG(i) (REG_UART_BASE(i) + 0x40)
+/** UART_XON_THRESHOLD : R/W; bitpos: [7:0]; default: 0;
+ *  When the data amount in Rx-FIFO is less than this register value with
+ *  uart_sw_flow_con_en set to 1  it will send a Xon char.
+ */
+#define UART_XON_THRESHOLD    0x000000FFU
+#define UART_XON_THRESHOLD_M  (UART_XON_THRESHOLD_V << UART_XON_THRESHOLD_S)
+#define UART_XON_THRESHOLD_V  0x000000FFU
+#define UART_XON_THRESHOLD_S  0
+/** UART_XOFF_THRESHOLD : R/W; bitpos: [15:8]; default: 224;
+ *  When the data amount in Rx-FIFO is more than this register value with
+ *  uart_sw_flow_con_en set to 1  it will send a Xoff char.
+ */
+#define UART_XOFF_THRESHOLD    0x000000FFU
+#define UART_XOFF_THRESHOLD_M  (UART_XOFF_THRESHOLD_V << UART_XOFF_THRESHOLD_S)
+#define UART_XOFF_THRESHOLD_V  0x000000FFU
+#define UART_XOFF_THRESHOLD_S  8
+
+/** UART_TXBRK_CONF_SYNC_REG register
+ *  Tx Break character configuration
+ */
+#define UART_TXBRK_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x44)
+/** UART_TX_BRK_NUM : R/W; bitpos: [7:0]; default: 10;
+ *  This register is used to configure the number of 0 to be sent after the process of
+ *  sending data is done. It is active when txd_brk is set to 1.
+ */
+#define UART_TX_BRK_NUM    0x000000FFU
+#define UART_TX_BRK_NUM_M  (UART_TX_BRK_NUM_V << UART_TX_BRK_NUM_S)
+#define UART_TX_BRK_NUM_V  0x000000FFU
+#define UART_TX_BRK_NUM_S  0
+
+/** UART_IDLE_CONF_SYNC_REG register
+ *  Frame-end idle configuration
+ */
+#define UART_IDLE_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x48)
+/** UART_RX_IDLE_THRHD : R/W; bitpos: [9:0]; default: 256;
+ *  It will produce frame end signal when receiver takes more time to receive one byte
+ *  data than this register value.
+ */
+#define UART_RX_IDLE_THRHD    0x000003FFU
+#define UART_RX_IDLE_THRHD_M  (UART_RX_IDLE_THRHD_V << UART_RX_IDLE_THRHD_S)
+#define UART_RX_IDLE_THRHD_V  0x000003FFU
+#define UART_RX_IDLE_THRHD_S  0
+/** UART_TX_IDLE_NUM : R/W; bitpos: [19:10]; default: 256;
+ *  This register is used to configure the duration time between transfers.
+ */
+#define UART_TX_IDLE_NUM    0x000003FFU
+#define UART_TX_IDLE_NUM_M  (UART_TX_IDLE_NUM_V << UART_TX_IDLE_NUM_S)
+#define UART_TX_IDLE_NUM_V  0x000003FFU
+#define UART_TX_IDLE_NUM_S  10
+
+/** UART_RS485_CONF_SYNC_REG register
+ *  RS485 mode configuration
+ */
+#define UART_RS485_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x4c)
+/** UART_RS485_EN : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to choose the rs485 mode.
+ */
+#define UART_RS485_EN    (BIT(0))
+#define UART_RS485_EN_M  (UART_RS485_EN_V << UART_RS485_EN_S)
+#define UART_RS485_EN_V  0x00000001U
+#define UART_RS485_EN_S  0
+/** UART_DL0_EN : R/W; bitpos: [1]; default: 0;
+ *  Set this bit to delay the stop bit by 1 bit.
+ */
+#define UART_DL0_EN    (BIT(1))
+#define UART_DL0_EN_M  (UART_DL0_EN_V << UART_DL0_EN_S)
+#define UART_DL0_EN_V  0x00000001U
+#define UART_DL0_EN_S  1
+/** UART_DL1_EN : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to delay the stop bit by 1 bit.
+ */
+#define UART_DL1_EN    (BIT(2))
+#define UART_DL1_EN_M  (UART_DL1_EN_V << UART_DL1_EN_S)
+#define UART_DL1_EN_V  0x00000001U
+#define UART_DL1_EN_S  2
+/** UART_RS485TX_RX_EN : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to enable receiver could receive data when the transmitter is
+ *  transmitting data in rs485 mode.
+ */
+#define UART_RS485TX_RX_EN    (BIT(3))
+#define UART_RS485TX_RX_EN_M  (UART_RS485TX_RX_EN_V << UART_RS485TX_RX_EN_S)
+#define UART_RS485TX_RX_EN_V  0x00000001U
+#define UART_RS485TX_RX_EN_S  3
+/** UART_RS485RXBY_TX_EN : R/W; bitpos: [4]; default: 0;
+ *  1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy.
+ */
+#define UART_RS485RXBY_TX_EN    (BIT(4))
+#define UART_RS485RXBY_TX_EN_M  (UART_RS485RXBY_TX_EN_V << UART_RS485RXBY_TX_EN_S)
+#define UART_RS485RXBY_TX_EN_V  0x00000001U
+#define UART_RS485RXBY_TX_EN_S  4
+/** UART_RS485_RX_DLY_NUM : R/W; bitpos: [5]; default: 0;
+ *  This register is used to delay the receiver's internal data signal.
+ */
+#define UART_RS485_RX_DLY_NUM    (BIT(5))
+#define UART_RS485_RX_DLY_NUM_M  (UART_RS485_RX_DLY_NUM_V << UART_RS485_RX_DLY_NUM_S)
+#define UART_RS485_RX_DLY_NUM_V  0x00000001U
+#define UART_RS485_RX_DLY_NUM_S  5
+/** UART_RS485_TX_DLY_NUM : R/W; bitpos: [9:6]; default: 0;
+ *  This register is used to delay the transmitter's internal data signal.
+ */
+#define UART_RS485_TX_DLY_NUM    0x0000000FU
+#define UART_RS485_TX_DLY_NUM_M  (UART_RS485_TX_DLY_NUM_V << UART_RS485_TX_DLY_NUM_S)
+#define UART_RS485_TX_DLY_NUM_V  0x0000000FU
+#define UART_RS485_TX_DLY_NUM_S  6
+
+/** UART_AT_CMD_PRECNT_SYNC_REG register
+ *  Pre-sequence timing configuration
+ */
+#define UART_AT_CMD_PRECNT_SYNC_REG(i) (REG_UART_BASE(i) + 0x50)
+/** UART_PRE_IDLE_NUM : R/W; bitpos: [15:0]; default: 2305;
+ *  This register is used to configure the idle duration time before the first at_cmd
+ *  is received by receiver.
+ */
+#define UART_PRE_IDLE_NUM    0x0000FFFFU
+#define UART_PRE_IDLE_NUM_M  (UART_PRE_IDLE_NUM_V << UART_PRE_IDLE_NUM_S)
+#define UART_PRE_IDLE_NUM_V  0x0000FFFFU
+#define UART_PRE_IDLE_NUM_S  0
+
+/** UART_AT_CMD_POSTCNT_SYNC_REG register
+ *  Post-sequence timing configuration
+ */
+#define UART_AT_CMD_POSTCNT_SYNC_REG(i) (REG_UART_BASE(i) + 0x54)
+/** UART_POST_IDLE_NUM : R/W; bitpos: [15:0]; default: 2305;
+ *  This register is used to configure the duration time between the last at_cmd and
+ *  the next data.
+ */
+#define UART_POST_IDLE_NUM    0x0000FFFFU
+#define UART_POST_IDLE_NUM_M  (UART_POST_IDLE_NUM_V << UART_POST_IDLE_NUM_S)
+#define UART_POST_IDLE_NUM_V  0x0000FFFFU
+#define UART_POST_IDLE_NUM_S  0
+
+/** UART_AT_CMD_GAPTOUT_SYNC_REG register
+ *  Timeout configuration
+ */
+#define UART_AT_CMD_GAPTOUT_SYNC_REG(i) (REG_UART_BASE(i) + 0x58)
+/** UART_RX_GAP_TOUT : R/W; bitpos: [15:0]; default: 11;
+ *  This register is used to configure the duration time between the at_cmd chars.
+ */
+#define UART_RX_GAP_TOUT    0x0000FFFFU
+#define UART_RX_GAP_TOUT_M  (UART_RX_GAP_TOUT_V << UART_RX_GAP_TOUT_S)
+#define UART_RX_GAP_TOUT_V  0x0000FFFFU
+#define UART_RX_GAP_TOUT_S  0
+
+/** UART_AT_CMD_CHAR_SYNC_REG register
+ *  AT escape sequence detection configuration
+ */
+#define UART_AT_CMD_CHAR_SYNC_REG(i) (REG_UART_BASE(i) + 0x5c)
+/** UART_AT_CMD_CHAR : R/W; bitpos: [7:0]; default: 43;
+ *  This register is used to configure the content of at_cmd char.
+ */
+#define UART_AT_CMD_CHAR    0x000000FFU
+#define UART_AT_CMD_CHAR_M  (UART_AT_CMD_CHAR_V << UART_AT_CMD_CHAR_S)
+#define UART_AT_CMD_CHAR_V  0x000000FFU
+#define UART_AT_CMD_CHAR_S  0
+/** UART_CHAR_NUM : R/W; bitpos: [15:8]; default: 3;
+ *  This register is used to configure the num of continuous at_cmd chars received by
+ *  receiver.
+ */
+#define UART_CHAR_NUM    0x000000FFU
+#define UART_CHAR_NUM_M  (UART_CHAR_NUM_V << UART_CHAR_NUM_S)
+#define UART_CHAR_NUM_V  0x000000FFU
+#define UART_CHAR_NUM_S  8
+
+/** UART_MEM_CONF_REG register
+ *  UART memory power configuration
+ */
+#define UART_MEM_CONF_REG(i) (REG_UART_BASE(i) + 0x60)
+/** UART_MEM_FORCE_PD : R/W; bitpos: [25]; default: 0;
+ *  Set this bit to force power down UART memory.
+ */
+#define UART_MEM_FORCE_PD    (BIT(25))
+#define UART_MEM_FORCE_PD_M  (UART_MEM_FORCE_PD_V << UART_MEM_FORCE_PD_S)
+#define UART_MEM_FORCE_PD_V  0x00000001U
+#define UART_MEM_FORCE_PD_S  25
+/** UART_MEM_FORCE_PU : R/W; bitpos: [26]; default: 0;
+ *  Set this bit to force power up UART memory.
+ */
+#define UART_MEM_FORCE_PU    (BIT(26))
+#define UART_MEM_FORCE_PU_M  (UART_MEM_FORCE_PU_V << UART_MEM_FORCE_PU_S)
+#define UART_MEM_FORCE_PU_V  0x00000001U
+#define UART_MEM_FORCE_PU_S  26
+
+/** UART_TOUT_CONF_SYNC_REG register
+ *  UART threshold and allocation configuration
+ */
+#define UART_TOUT_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x64)
+/** UART_RX_TOUT_EN : R/W; bitpos: [0]; default: 0;
+ *  This is the enble bit for uart receiver's timeout function.
+ */
+#define UART_RX_TOUT_EN    (BIT(0))
+#define UART_RX_TOUT_EN_M  (UART_RX_TOUT_EN_V << UART_RX_TOUT_EN_S)
+#define UART_RX_TOUT_EN_V  0x00000001U
+#define UART_RX_TOUT_EN_S  0
+/** UART_RX_TOUT_FLOW_DIS : R/W; bitpos: [1]; default: 0;
+ *  Set this bit to stop accumulating idle_cnt when hardware flow control works.
+ */
+#define UART_RX_TOUT_FLOW_DIS    (BIT(1))
+#define UART_RX_TOUT_FLOW_DIS_M  (UART_RX_TOUT_FLOW_DIS_V << UART_RX_TOUT_FLOW_DIS_S)
+#define UART_RX_TOUT_FLOW_DIS_V  0x00000001U
+#define UART_RX_TOUT_FLOW_DIS_S  1
+/** UART_RX_TOUT_THRHD : R/W; bitpos: [11:2]; default: 10;
+ *  This register is used to configure the threshold time that receiver takes to
+ *  receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver
+ *  takes more time to receive one byte with rx_tout_en set to 1.
+ */
+#define UART_RX_TOUT_THRHD    0x000003FFU
+#define UART_RX_TOUT_THRHD_M  (UART_RX_TOUT_THRHD_V << UART_RX_TOUT_THRHD_S)
+#define UART_RX_TOUT_THRHD_V  0x000003FFU
+#define UART_RX_TOUT_THRHD_S  2
+
+/** UART_MEM_TX_STATUS_REG register
+ *  Tx-SRAM write and read offset address.
+ */
+#define UART_MEM_TX_STATUS_REG(i) (REG_UART_BASE(i) + 0x68)
+/** UART_TX_SRAM_WADDR : RO; bitpos: [7:0]; default: 0;
+ *  This register stores the offset write address in Tx-SRAM.
+ */
+#define UART_TX_SRAM_WADDR    0x000000FFU
+#define UART_TX_SRAM_WADDR_M  (UART_TX_SRAM_WADDR_V << UART_TX_SRAM_WADDR_S)
+#define UART_TX_SRAM_WADDR_V  0x000000FFU
+#define UART_TX_SRAM_WADDR_S  0
+/** UART_TX_SRAM_RADDR : RO; bitpos: [16:9]; default: 0;
+ *  This register stores the offset read address in Tx-SRAM.
+ */
+#define UART_TX_SRAM_RADDR    0x000000FFU
+#define UART_TX_SRAM_RADDR_M  (UART_TX_SRAM_RADDR_V << UART_TX_SRAM_RADDR_S)
+#define UART_TX_SRAM_RADDR_V  0x000000FFU
+#define UART_TX_SRAM_RADDR_S  9
+
+/** UART_MEM_RX_STATUS_REG register
+ *  Rx-SRAM write and read offset address.
+ */
+#define UART_MEM_RX_STATUS_REG(i) (REG_UART_BASE(i) + 0x6c)
+/** UART_RX_SRAM_RADDR : RO; bitpos: [7:0]; default: 128;
+ *  This register stores the offset read address in RX-SRAM.
+ */
+#define UART_RX_SRAM_RADDR    0x000000FFU
+#define UART_RX_SRAM_RADDR_M  (UART_RX_SRAM_RADDR_V << UART_RX_SRAM_RADDR_S)
+#define UART_RX_SRAM_RADDR_V  0x000000FFU
+#define UART_RX_SRAM_RADDR_S  0
+/** UART_RX_SRAM_WADDR : RO; bitpos: [16:9]; default: 128;
+ *  This register stores the offset write address in Rx-SRAM.
+ */
+#define UART_RX_SRAM_WADDR    0x000000FFU
+#define UART_RX_SRAM_WADDR_M  (UART_RX_SRAM_WADDR_V << UART_RX_SRAM_WADDR_S)
+#define UART_RX_SRAM_WADDR_V  0x000000FFU
+#define UART_RX_SRAM_WADDR_S  9
+
+/** UART_FSM_STATUS_REG register
+ *  UART transmit and receive status.
+ */
+#define UART_FSM_STATUS_REG(i) (REG_UART_BASE(i) + 0x70)
+/** UART_ST_URX_OUT : RO; bitpos: [3:0]; default: 0;
+ *  This is the status register of receiver.
+ */
+#define UART_ST_URX_OUT    0x0000000FU
+#define UART_ST_URX_OUT_M  (UART_ST_URX_OUT_V << UART_ST_URX_OUT_S)
+#define UART_ST_URX_OUT_V  0x0000000FU
+#define UART_ST_URX_OUT_S  0
+/** UART_ST_UTX_OUT : RO; bitpos: [7:4]; default: 0;
+ *  This is the status register of transmitter.
+ */
+#define UART_ST_UTX_OUT    0x0000000FU
+#define UART_ST_UTX_OUT_M  (UART_ST_UTX_OUT_V << UART_ST_UTX_OUT_S)
+#define UART_ST_UTX_OUT_V  0x0000000FU
+#define UART_ST_UTX_OUT_S  4
+
+/** UART_POSPULSE_REG register
+ *  Autobaud high pulse register
+ */
+#define UART_POSPULSE_REG(i) (REG_UART_BASE(i) + 0x74)
+/** UART_POSEDGE_MIN_CNT : RO; bitpos: [11:0]; default: 4095;
+ *  This register stores the minimal input clock count between two positive edges. It
+ *  is used in boudrate-detect process.
+ */
+#define UART_POSEDGE_MIN_CNT    0x00000FFFU
+#define UART_POSEDGE_MIN_CNT_M  (UART_POSEDGE_MIN_CNT_V << UART_POSEDGE_MIN_CNT_S)
+#define UART_POSEDGE_MIN_CNT_V  0x00000FFFU
+#define UART_POSEDGE_MIN_CNT_S  0
+
+/** UART_NEGPULSE_REG register
+ *  Autobaud low pulse register
+ */
+#define UART_NEGPULSE_REG(i) (REG_UART_BASE(i) + 0x78)
+/** UART_NEGEDGE_MIN_CNT : RO; bitpos: [11:0]; default: 4095;
+ *  This register stores the minimal input clock count between two negative edges. It
+ *  is used in boudrate-detect process.
+ */
+#define UART_NEGEDGE_MIN_CNT    0x00000FFFU
+#define UART_NEGEDGE_MIN_CNT_M  (UART_NEGEDGE_MIN_CNT_V << UART_NEGEDGE_MIN_CNT_S)
+#define UART_NEGEDGE_MIN_CNT_V  0x00000FFFU
+#define UART_NEGEDGE_MIN_CNT_S  0
+
+/** UART_LOWPULSE_REG register
+ *  Autobaud minimum low pulse duration register
+ */
+#define UART_LOWPULSE_REG(i) (REG_UART_BASE(i) + 0x7c)
+/** UART_LOWPULSE_MIN_CNT : RO; bitpos: [11:0]; default: 4095;
+ *  This register stores the value of the minimum duration time of the low level pulse.
+ *  It is used in baud rate-detect process.
+ */
+#define UART_LOWPULSE_MIN_CNT    0x00000FFFU
+#define UART_LOWPULSE_MIN_CNT_M  (UART_LOWPULSE_MIN_CNT_V << UART_LOWPULSE_MIN_CNT_S)
+#define UART_LOWPULSE_MIN_CNT_V  0x00000FFFU
+#define UART_LOWPULSE_MIN_CNT_S  0
+
+/** UART_HIGHPULSE_REG register
+ *  Autobaud minimum high pulse duration register
+ */
+#define UART_HIGHPULSE_REG(i) (REG_UART_BASE(i) + 0x80)
+/** UART_HIGHPULSE_MIN_CNT : RO; bitpos: [11:0]; default: 4095;
+ *  This register stores  the value of the maxinum duration time for the high level
+ *  pulse. It is used in baud rate-detect process.
+ */
+#define UART_HIGHPULSE_MIN_CNT    0x00000FFFU
+#define UART_HIGHPULSE_MIN_CNT_M  (UART_HIGHPULSE_MIN_CNT_V << UART_HIGHPULSE_MIN_CNT_S)
+#define UART_HIGHPULSE_MIN_CNT_V  0x00000FFFU
+#define UART_HIGHPULSE_MIN_CNT_S  0
+
+/** UART_RXD_CNT_REG register
+ *  Autobaud edge change count register
+ */
+#define UART_RXD_CNT_REG(i) (REG_UART_BASE(i) + 0x84)
+/** UART_RXD_EDGE_CNT : RO; bitpos: [9:0]; default: 0;
+ *  This register stores the count of rxd edge change. It is used in baud rate-detect
+ *  process.
+ */
+#define UART_RXD_EDGE_CNT    0x000003FFU
+#define UART_RXD_EDGE_CNT_M  (UART_RXD_EDGE_CNT_V << UART_RXD_EDGE_CNT_S)
+#define UART_RXD_EDGE_CNT_V  0x000003FFU
+#define UART_RXD_EDGE_CNT_S  0
+
+/** UART_CLK_CONF_REG register
+ *  UART core clock configuration
+ */
+#define UART_CLK_CONF_REG(i) (REG_UART_BASE(i) + 0x88)
+/** UART_TX_SCLK_EN : R/W; bitpos: [24]; default: 1;
+ *  Set this bit to enable UART Tx clock.
+ */
+#define UART_TX_SCLK_EN    (BIT(24))
+#define UART_TX_SCLK_EN_M  (UART_TX_SCLK_EN_V << UART_TX_SCLK_EN_S)
+#define UART_TX_SCLK_EN_V  0x00000001U
+#define UART_TX_SCLK_EN_S  24
+/** UART_RX_SCLK_EN : R/W; bitpos: [25]; default: 1;
+ *  Set this bit to enable UART Rx clock.
+ */
+#define UART_RX_SCLK_EN    (BIT(25))
+#define UART_RX_SCLK_EN_M  (UART_RX_SCLK_EN_V << UART_RX_SCLK_EN_S)
+#define UART_RX_SCLK_EN_V  0x00000001U
+#define UART_RX_SCLK_EN_S  25
+/** UART_TX_RST_CORE : R/W; bitpos: [26]; default: 0;
+ *  Write 1 then write 0 to this bit to reset UART Tx.
+ */
+#define UART_TX_RST_CORE    (BIT(26))
+#define UART_TX_RST_CORE_M  (UART_TX_RST_CORE_V << UART_TX_RST_CORE_S)
+#define UART_TX_RST_CORE_V  0x00000001U
+#define UART_TX_RST_CORE_S  26
+/** UART_RX_RST_CORE : R/W; bitpos: [27]; default: 0;
+ *  Write 1 then write 0 to this bit to reset UART Rx.
+ */
+#define UART_RX_RST_CORE    (BIT(27))
+#define UART_RX_RST_CORE_M  (UART_RX_RST_CORE_V << UART_RX_RST_CORE_S)
+#define UART_RX_RST_CORE_V  0x00000001U
+#define UART_RX_RST_CORE_S  27
+
+/** UART_DATE_REG register
+ *  UART Version register
+ */
+#define UART_DATE_REG(i) (REG_UART_BASE(i) + 0x8c)
+/** UART_DATE : R/W; bitpos: [31:0]; default: 36720720;
+ *  This is the version register.
+ */
+#define UART_DATE    0xFFFFFFFFU
+#define UART_DATE_M  (UART_DATE_V << UART_DATE_S)
+#define UART_DATE_V  0xFFFFFFFFU
+#define UART_DATE_S  0
+
+/** UART_AFIFO_STATUS_REG register
+ *  UART AFIFO Status
+ */
+#define UART_AFIFO_STATUS_REG(i) (REG_UART_BASE(i) + 0x90)
+/** UART_TX_AFIFO_FULL : RO; bitpos: [0]; default: 0;
+ *  Full signal of APB TX AFIFO.
+ */
+#define UART_TX_AFIFO_FULL    (BIT(0))
+#define UART_TX_AFIFO_FULL_M  (UART_TX_AFIFO_FULL_V << UART_TX_AFIFO_FULL_S)
+#define UART_TX_AFIFO_FULL_V  0x00000001U
+#define UART_TX_AFIFO_FULL_S  0
+/** UART_TX_AFIFO_EMPTY : RO; bitpos: [1]; default: 1;
+ *  Empty signal of APB TX AFIFO.
+ */
+#define UART_TX_AFIFO_EMPTY    (BIT(1))
+#define UART_TX_AFIFO_EMPTY_M  (UART_TX_AFIFO_EMPTY_V << UART_TX_AFIFO_EMPTY_S)
+#define UART_TX_AFIFO_EMPTY_V  0x00000001U
+#define UART_TX_AFIFO_EMPTY_S  1
+/** UART_RX_AFIFO_FULL : RO; bitpos: [2]; default: 0;
+ *  Full signal of APB RX AFIFO.
+ */
+#define UART_RX_AFIFO_FULL    (BIT(2))
+#define UART_RX_AFIFO_FULL_M  (UART_RX_AFIFO_FULL_V << UART_RX_AFIFO_FULL_S)
+#define UART_RX_AFIFO_FULL_V  0x00000001U
+#define UART_RX_AFIFO_FULL_S  2
+/** UART_RX_AFIFO_EMPTY : RO; bitpos: [3]; default: 1;
+ *  Empty signal of APB RX AFIFO.
+ */
+#define UART_RX_AFIFO_EMPTY    (BIT(3))
+#define UART_RX_AFIFO_EMPTY_M  (UART_RX_AFIFO_EMPTY_V << UART_RX_AFIFO_EMPTY_S)
+#define UART_RX_AFIFO_EMPTY_V  0x00000001U
+#define UART_RX_AFIFO_EMPTY_S  3
+
+/** UART_REG_UPDATE_REG register
+ *  UART Registers Configuration Update register
+ */
+#define UART_REG_UPDATE_REG(i) (REG_UART_BASE(i) + 0x98)
+/** UART_REG_UPDATE : R/W/SC; bitpos: [0]; default: 0;
+ *  Software write 1 would synchronize registers into UART Core clock domain and would
+ *  be cleared by hardware after synchronization is done.
+ */
+#define UART_REG_UPDATE    (BIT(0))
+#define UART_REG_UPDATE_M  (UART_REG_UPDATE_V << UART_REG_UPDATE_S)
+#define UART_REG_UPDATE_V  0x00000001U
+#define UART_REG_UPDATE_S  0
+
+/** UART_ID_REG register
+ *  UART ID register
+ */
+#define UART_ID_REG(i) (REG_UART_BASE(i) + 0x9c)
+/** UART_ID : R/W; bitpos: [31:0]; default: 1280;
+ *  This register is used to configure the uart_id.
+ */
+#define UART_ID    0xFFFFFFFFU
+#define UART_ID_M  (UART_ID_V << UART_ID_S)
+#define UART_ID_V  0xFFFFFFFFU
+#define UART_ID_S  0
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32p4/include/soc/wdev_reg.h

@@ -0,0 +1,14 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include "soc.h"
+#include "soc/lpperi_reg.h"
+
+//TODO: IDF-6522
+/* Hardware random number generator register */
+#define WDEV_RND_REG    0x600260b0