sleep: fix sleep current issue caused by sar adc

components/esp_hw_support/include/esp_private/sar_periph_ctrl.h

@@ -62,6 +62,16 @@ void sar_periph_ctrl_pwdet_power_acquire(void);
  */
 void sar_periph_ctrl_pwdet_power_release(void);
 
+/**
+ * @brief Enable SAR power when system wakes up
+ */
+void sar_periph_ctrl_power_enable(void);
+
+/**
+ * @brief Disable SAR power when system goes to sleep
+ */
+void sar_periph_ctrl_power_disable(void);
+
 #ifdef __cplusplus
 }
 #endif

components/esp_hw_support/port/esp32/sar_periph_ctrl.c

@@ -32,6 +32,13 @@ void sar_periph_ctrl_init(void)
     //Add other periph power control initialisation here
 }
 
+void sar_periph_ctrl_power_enable(void)
+{
+    portENTER_CRITICAL_SAFE(&rtc_spinlock);
+    sar_ctrl_ll_set_power_mode(SAR_CTRL_LL_POWER_ON);
+    portEXIT_CRITICAL_SAFE(&rtc_spinlock);
+}
+
 void sar_periph_ctrl_power_disable(void)
 {
     portENTER_CRITICAL_SAFE(&rtc_spinlock);

components/esp_hw_support/port/esp32c2/sar_periph_ctrl.c

@@ -34,6 +34,13 @@ void sar_periph_ctrl_init(void)
     //Add other periph power control initialisation here
 }
 
+void sar_periph_ctrl_power_enable(void)
+{
+    portENTER_CRITICAL_SAFE(&rtc_spinlock);
+    sar_ctrl_ll_set_power_mode(SAR_CTRL_LL_POWER_FSM);
+    portEXIT_CRITICAL_SAFE(&rtc_spinlock);
+}
+
 void sar_periph_ctrl_power_disable(void)
 {
     portENTER_CRITICAL_SAFE(&rtc_spinlock);

components/esp_hw_support/port/esp32c3/sar_periph_ctrl.c

@@ -34,6 +34,13 @@ void sar_periph_ctrl_init(void)
     //Add other periph power control initialisation here
 }
 
+void sar_periph_ctrl_power_enable(void)
+{
+    portENTER_CRITICAL_SAFE(&rtc_spinlock);
+    sar_ctrl_ll_set_power_mode(SAR_CTRL_LL_POWER_FSM);
+    portEXIT_CRITICAL_SAFE(&rtc_spinlock);
+}
+
 void sar_periph_ctrl_power_disable(void)
 {
     portENTER_CRITICAL_SAFE(&rtc_spinlock);

components/esp_hw_support/port/esp32c6/sar_periph_ctrl.c

@@ -31,6 +31,13 @@ void sar_periph_ctrl_init(void)
     //Add other periph power control initialisation here
 }
 
+void sar_periph_ctrl_power_enable(void)
+{
+    portENTER_CRITICAL_SAFE(&rtc_spinlock);
+    sar_ctrl_ll_force_power_ctrl_from_pwdet(true);
+    portEXIT_CRITICAL_SAFE(&rtc_spinlock);
+}
+
 void sar_periph_ctrl_power_disable(void)
 {
     portENTER_CRITICAL_SAFE(&rtc_spinlock);

components/esp_hw_support/port/esp32h2/sar_periph_ctrl.c

@@ -30,6 +30,13 @@ void sar_periph_ctrl_init(void)
     //Add other periph power control initialisation here
 }
 
+void sar_periph_ctrl_power_enable(void)
+{
+    portENTER_CRITICAL_SAFE(&rtc_spinlock);
+    sar_ctrl_ll_force_power_ctrl_from_pwdet(true);
+    portEXIT_CRITICAL_SAFE(&rtc_spinlock);
+}
+
 void sar_periph_ctrl_power_disable(void)
 {
     portENTER_CRITICAL_SAFE(&rtc_spinlock);

components/esp_hw_support/port/esp32h4/sar_periph_ctrl.c

@@ -29,6 +29,11 @@ void sar_periph_ctrl_init(void)
     //TODO: IDF-6123
 }
 
+void sar_periph_ctrl_power_enable(void)
+{
+    //TODO: IDF-6123
+}
+
 void sar_periph_ctrl_power_disable(void)
 {
     //TODO: IDF-6123

components/esp_hw_support/port/esp32s2/sar_periph_ctrl.c

@@ -34,6 +34,13 @@ void sar_periph_ctrl_init(void)
     //Add other periph power control initialisation here
 }
 
+void sar_periph_ctrl_power_enable(void)
+{
+    portENTER_CRITICAL_SAFE(&rtc_spinlock);
+    sar_ctrl_ll_set_power_mode(SAR_CTRL_LL_POWER_FSM);
+    portEXIT_CRITICAL_SAFE(&rtc_spinlock);
+}
+
 void sar_periph_ctrl_power_disable(void)
 {
     portENTER_CRITICAL_SAFE(&rtc_spinlock);

components/esp_hw_support/port/esp32s3/sar_periph_ctrl.c

@@ -34,6 +34,13 @@ void sar_periph_ctrl_init(void)
     //Add other periph power control initialisation here
 }
 
+void sar_periph_ctrl_power_enable(void)
+{
+    portENTER_CRITICAL_SAFE(&rtc_spinlock);
+    sar_ctrl_ll_set_power_mode(SAR_CTRL_LL_POWER_FSM);
+    portEXIT_CRITICAL_SAFE(&rtc_spinlock);
+}
+
 void sar_periph_ctrl_power_disable(void)
 {
     portENTER_CRITICAL_SAFE(&rtc_spinlock);

components/esp_hw_support/sleep_modes.c

@@ -60,6 +60,7 @@
 #include "esp_private/esp_clk.h"
 #include "esp_private/esp_task_wdt.h"
 #include "esp_private/spi_flash_os.h"
+#include "esp_private/sar_periph_ctrl.h"
 
 #ifdef CONFIG_IDF_TARGET_ESP32
 #include "esp32/rom/cache.h"
@@ -404,6 +405,7 @@ inline static void IRAM_ATTR misc_modules_sleep_prepare(void)
 #if REGI2C_ANA_CALI_PD_WORKAROUND
     regi2c_analog_cali_reg_read();
 #endif
+    sar_periph_ctrl_power_disable();
 }
 
 /**
@@ -411,6 +413,7 @@ inline static void IRAM_ATTR misc_modules_sleep_prepare(void)
  */
 inline static void IRAM_ATTR misc_modules_wake_prepare(void)
 {
+    sar_periph_ctrl_power_enable();
 #if SOC_PM_SUPPORT_CPU_PD && SOC_PM_CPU_RETENTION_BY_RTCCNTL
     sleep_disable_cpu_retention();
 #endif