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+/*
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+ * FreeRTOS Kernel V10.5.1 (ESP-IDF SMP modified)
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+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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+ *
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+ * SPDX-FileCopyrightText: 2021 Amazon.com, Inc. or its affiliates
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+ *
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+ * SPDX-License-Identifier: MIT
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+ *
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+ * SPDX-FileContributor: 2023 Espressif Systems (Shanghai) CO LTD
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+ *
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+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
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+ * this software and associated documentation files (the "Software"), to deal in
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+ * the Software without restriction, including without limitation the rights to
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+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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+ * the Software, and to permit persons to whom the Software is furnished to do so,
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+ * subject to the following conditions:
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+ *
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+ * The above copyright notice and this permission notice shall be included in all
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+ * copies or substantial portions of the Software.
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+ *
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+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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+ *
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+ * https://www.FreeRTOS.org
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+ * https://github.com/FreeRTOS
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+ *
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+ */
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+
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+/*
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+ * The FreeRTOS kernel's RISC-V port is split between the the code that is
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+ * common across all currently supported RISC-V chips (implementations of the
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+ * RISC-V ISA), and code which tailors the port to a specific RISC-V chip:
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+ *
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+ * + The code that is common to all RISC-V chips is implemented in
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+ * FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S. There is only one
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+ * portASM.S file because the same file is used no matter which RISC-V chip is
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+ * in use.
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+ *
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+ * + The code that tailors the kernel's RISC-V port to a specific RISC-V
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+ * chip is implemented in freertos_risc_v_chip_specific_extensions.h. There
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+ * is one freertos_risc_v_chip_specific_extensions.h that can be used with any
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+ * RISC-V chip that both includes a standard CLINT and does not add to the
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+ * base set of RISC-V registers. There are additional
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+ * freertos_risc_v_chip_specific_extensions.h files for RISC-V implementations
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+ * that do not include a standard CLINT or do add to the base set of RISC-V
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+ * registers.
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+ *
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+ * CARE MUST BE TAKEN TO INCLDUE THE CORRECT
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+ * freertos_risc_v_chip_specific_extensions.h HEADER FILE FOR THE CHIP
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+ * IN USE. To include the correct freertos_risc_v_chip_specific_extensions.h
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+ * header file ensure the path to the correct header file is in the assembler's
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+ * include path.
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+ *
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+ * This freertos_risc_v_chip_specific_extensions.h is for use on RISC-V chips
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+ * that include a standard CLINT and do not add to the base set of RISC-V
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+ * registers.
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+ *
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+ */
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+
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+#include "portContext.h"
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+
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+/* Check the freertos_risc_v_chip_specific_extensions.h and/or command line
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+definitions. */
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+#if defined( portasmHAS_CLINT ) && defined( portasmHAS_MTIME )
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+ #error The portasmHAS_CLINT constant has been deprecated. Please replace it with portasmHAS_MTIME. portasmHAS_CLINT and portasmHAS_MTIME cannot both be defined at once. See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
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+#endif
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+
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+#ifdef portasmHAS_CLINT
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+ #warning The portasmHAS_CLINT constant has been deprecated. Please replace it with portasmHAS_MTIME and portasmHAS_SIFIVE_CLINT. For now portasmHAS_MTIME and portasmHAS_SIFIVE_CLINT are derived from portasmHAS_CLINT. See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
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+ #define portasmHAS_MTIME portasmHAS_CLINT
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+ #define portasmHAS_SIFIVE_CLINT portasmHAS_CLINT
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+#endif
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+
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+#ifndef portasmHAS_MTIME
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+ #error freertos_risc_v_chip_specific_extensions.h must define portasmHAS_MTIME to either 1 (MTIME clock present) or 0 (MTIME clock not present). See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
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+#endif
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+
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+#ifndef portasmHAS_SIFIVE_CLINT
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+ #define portasmHAS_SIFIVE_CLINT 0
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+#endif
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+
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+.global xPortStartFirstTask
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+.global pxPortInitialiseStack
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+.global freertos_risc_v_trap_handler
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+.global freertos_risc_v_exception_handler
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+.global freertos_risc_v_interrupt_handler
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+.global freertos_risc_v_mtimer_interrupt_handler
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+
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+.extern vTaskSwitchContext
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+.extern xTaskIncrementTick
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+.extern pullMachineTimerCompareRegister
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+.extern pullNextTime
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+.extern uxTimerIncrementsForOneTick /* size_t type so 32-bit on 32-bit core and 64-bits on 64-bit core. */
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+.extern xTaskReturnAddress
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+
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+.weak freertos_risc_v_application_exception_handler
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+.weak freertos_risc_v_application_interrupt_handler
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+/*-----------------------------------------------------------*/
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+
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+.macro portUPDATE_MTIMER_COMPARE_REGISTER
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+ load_x a0, pullMachineTimerCompareRegister /* Load address of compare register into a0. */
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+ load_x a1, pullNextTime /* Load the address of ullNextTime into a1. */
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+
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+ #if( __riscv_xlen == 32 )
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+
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+ /* Update the 64-bit mtimer compare match value in two 32-bit writes. */
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+ li a4, -1
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+ lw a2, 0(a1) /* Load the low word of ullNextTime into a2. */
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+ lw a3, 4(a1) /* Load the high word of ullNextTime into a3. */
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+ sw a4, 0(a0) /* Low word no smaller than old value to start with - will be overwritten below. */
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+ sw a3, 4(a0) /* Store high word of ullNextTime into compare register. No smaller than new value. */
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+ sw a2, 0(a0) /* Store low word of ullNextTime into compare register. */
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+ lw t0, uxTimerIncrementsForOneTick /* Load the value of ullTimerIncrementForOneTick into t0 (could this be optimized by storing in an array next to pullNextTime?). */
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+ add a4, t0, a2 /* Add the low word of ullNextTime to the timer increments for one tick (assumes timer increment for one tick fits in 32-bits). */
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+ sltu t1, a4, a2 /* See if the sum of low words overflowed (what about the zero case?). */
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+ add t2, a3, t1 /* Add overflow to high word of ullNextTime. */
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+ sw a4, 0(a1) /* Store new low word of ullNextTime. */
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+ sw t2, 4(a1) /* Store new high word of ullNextTime. */
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+
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+ #endif /* __riscv_xlen == 32 */
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+
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+ #if( __riscv_xlen == 64 )
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+
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+ /* Update the 64-bit mtimer compare match value. */
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+ ld t2, 0(a1) /* Load ullNextTime into t2. */
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+ sd t2, 0(a0) /* Store ullNextTime into compare register. */
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+ ld t0, uxTimerIncrementsForOneTick /* Load the value of ullTimerIncrementForOneTick into t0 (could this be optimized by storing in an array next to pullNextTime?). */
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+ add t4, t0, t2 /* Add ullNextTime to the timer increments for one tick. */
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+ sd t4, 0(a1) /* Store ullNextTime. */
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+
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+ #endif /* __riscv_xlen == 64 */
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+ .endm
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+/*-----------------------------------------------------------*/
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+
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+/*
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+ * Unlike other ports pxPortInitialiseStack() is written in assembly code as it
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+ * needs access to the portasmADDITIONAL_CONTEXT_SIZE constant. The prototype
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+ * for the function is as per the other ports:
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+ * StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters );
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+ *
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+ * As per the standard RISC-V ABI pxTopcOfStack is passed in in a0, pxCode in
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+ * a1, and pvParameters in a2. The new top of stack is passed out in a0.
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+ *
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+ * RISC-V maps registers to ABI names as follows (X1 to X31 integer registers
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+ * for the 'I' profile, X1 to X15 for the 'E' profile, currently I assumed).
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+ *
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+ * Register ABI Name Description Saver
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+ * x0 zero Hard-wired zero -
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+ * x1 ra Return address Caller
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+ * x2 sp Stack pointer Callee
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+ * x3 gp Global pointer -
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+ * x4 tp Thread pointer -
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+ * x5-7 t0-2 Temporaries Caller
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+ * x8 s0/fp Saved register/Frame pointer Callee
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+ * x9 s1 Saved register Callee
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+ * x10-11 a0-1 Function Arguments/return values Caller
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+ * x12-17 a2-7 Function arguments Caller
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+ * x18-27 s2-11 Saved registers Callee
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+ * x28-31 t3-6 Temporaries Caller
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+ *
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+ * The RISC-V context is saved t FreeRTOS tasks in the following stack frame,
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+ * where the global and thread pointers are currently assumed to be constant so
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+ * are not saved:
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+ *
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+ * mstatus
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+ * xCriticalNesting
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+ * x31
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+ * x30
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+ * x29
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+ * x28
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+ * x27
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+ * x26
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+ * x25
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+ * x24
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+ * x23
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+ * x22
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+ * x21
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+ * x20
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+ * x19
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+ * x18
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+ * x17
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+ * x16
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+ * x15
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+ * x14
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+ * x13
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+ * x12
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+ * x11
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+ * pvParameters
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+ * x9
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+ * x8
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+ * x7
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+ * x6
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+ * x5
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+ * portTASK_RETURN_ADDRESS
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+ * [chip specific registers go here]
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+ * pxCode
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+ */
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+pxPortInitialiseStack:
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+ csrr t0, mstatus /* Obtain current mstatus value. */
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+ andi t0, t0, ~0x8 /* Ensure interrupts are disabled when the stack is restored within an ISR. Required when a task is created after the schedulre has been started, otherwise interrupts would be disabled anyway. */
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+ addi t1, x0, 0x188 /* Generate the value 0x1880, which are the MPIE and MPP bits to set in mstatus. */
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+ slli t1, t1, 4
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+ or t0, t0, t1 /* Set MPIE and MPP bits in mstatus value. */
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+
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+ addi a0, a0, -portWORD_SIZE
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+ store_x t0, 0(a0) /* mstatus onto the stack. */
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+ addi a0, a0, -portWORD_SIZE /* Space for critical nesting count. */
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+ store_x x0, 0(a0) /* Critical nesting count starts at 0 for every task. */
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+
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+#ifdef __riscv_32e
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+ addi a0, a0, -(6 * portWORD_SIZE) /* Space for registers x11-x15. */
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+#else
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+ addi a0, a0, -(22 * portWORD_SIZE) /* Space for registers x11-x31. */
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+#endif
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+ store_x a2, 0(a0) /* Task parameters (pvParameters parameter) goes into register X10/a0 on the stack. */
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+ addi a0, a0, -(6 * portWORD_SIZE) /* Space for registers x5-x9. */
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+ load_x t0, xTaskReturnAddress
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+ store_x t0, 0(a0) /* Return address onto the stack. */
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+ addi t0, x0, portasmADDITIONAL_CONTEXT_SIZE /* The number of chip specific additional registers. */
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+chip_specific_stack_frame: /* First add any chip specific registers to the stack frame being created. */
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+ beq t0, x0, 1f /* No more chip specific registers to save. */
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+ addi a0, a0, -portWORD_SIZE /* Make space for chip specific register. */
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+ store_x x0, 0(a0) /* Give the chip specific register an initial value of zero. */
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+ addi t0, t0, -1 /* Decrement the count of chip specific registers remaining. */
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+ j chip_specific_stack_frame /* Until no more chip specific registers. */
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+1:
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+ addi a0, a0, -portWORD_SIZE
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+ store_x a1, 0(a0) /* mret value (pxCode parameter) onto the stack. */
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+ ret
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+/*-----------------------------------------------------------*/
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+
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+xPortStartFirstTask:
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+ load_x sp, pxCurrentTCB /* Load pxCurrentTCB. */
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+ load_x sp, 0( sp ) /* Read sp from first TCB member. */
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+
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+ load_x x1, 0( sp ) /* Note for starting the scheduler the exception return address is used as the function return address. */
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+
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+ portasmRESTORE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to restore any registers unique to the RISC-V implementation. */
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+
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+ load_x x7, 4 * portWORD_SIZE( sp ) /* t2 */
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+ load_x x8, 5 * portWORD_SIZE( sp ) /* s0/fp */
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+ load_x x9, 6 * portWORD_SIZE( sp ) /* s1 */
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+ load_x x10, 7 * portWORD_SIZE( sp ) /* a0 */
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+ load_x x11, 8 * portWORD_SIZE( sp ) /* a1 */
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+ load_x x12, 9 * portWORD_SIZE( sp ) /* a2 */
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+ load_x x13, 10 * portWORD_SIZE( sp ) /* a3 */
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+ load_x x14, 11 * portWORD_SIZE( sp ) /* a4 */
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+ load_x x15, 12 * portWORD_SIZE( sp ) /* a5 */
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+#ifndef __riscv_32e
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+ load_x x16, 13 * portWORD_SIZE( sp ) /* a6 */
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+ load_x x17, 14 * portWORD_SIZE( sp ) /* a7 */
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+ load_x x18, 15 * portWORD_SIZE( sp ) /* s2 */
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+ load_x x19, 16 * portWORD_SIZE( sp ) /* s3 */
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+ load_x x20, 17 * portWORD_SIZE( sp ) /* s4 */
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+ load_x x21, 18 * portWORD_SIZE( sp ) /* s5 */
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+ load_x x22, 19 * portWORD_SIZE( sp ) /* s6 */
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+ load_x x23, 20 * portWORD_SIZE( sp ) /* s7 */
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+ load_x x24, 21 * portWORD_SIZE( sp ) /* s8 */
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+ load_x x25, 22 * portWORD_SIZE( sp ) /* s9 */
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+ load_x x26, 23 * portWORD_SIZE( sp ) /* s10 */
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+ load_x x27, 24 * portWORD_SIZE( sp ) /* s11 */
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+ load_x x28, 25 * portWORD_SIZE( sp ) /* t3 */
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+ load_x x29, 26 * portWORD_SIZE( sp ) /* t4 */
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+ load_x x30, 27 * portWORD_SIZE( sp ) /* t5 */
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+ load_x x31, 28 * portWORD_SIZE( sp ) /* t6 */
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+#endif
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+
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+ load_x x5, portCRITICAL_NESTING_OFFSET * portWORD_SIZE( sp ) /* Obtain xCriticalNesting value for this task from task's stack. */
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+ load_x x6, pxCriticalNesting /* Load the address of xCriticalNesting into x6. */
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+ store_x x5, 0( x6 ) /* Restore the critical nesting value for this task. */
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+
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+ load_x x5, portMSTATUS_OFFSET * portWORD_SIZE( sp ) /* Initial mstatus into x5 (t0). */
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+ addi x5, x5, 0x08 /* Set MIE bit so the first task starts with interrupts enabled - required as returns with ret not eret. */
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+ csrrw x0, mstatus, x5 /* Interrupts enabled from here! */
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+
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+ load_x x5, 2 * portWORD_SIZE( sp ) /* Initial x5 (t0) value. */
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+ load_x x6, 3 * portWORD_SIZE( sp ) /* Initial x6 (t1) value. */
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+
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+ addi sp, sp, portCONTEXT_SIZE
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+ ret
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+/*-----------------------------------------------------------*/
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+
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+freertos_risc_v_application_exception_handler:
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+ csrr t0, mcause /* For viewing in the debugger only. */
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+ csrr t1, mepc /* For viewing in the debugger only */
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+ csrr t2, mstatus /* For viewing in the debugger only */
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+ j .
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+/*-----------------------------------------------------------*/
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+
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+freertos_risc_v_application_interrupt_handler:
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+ csrr t0, mcause /* For viewing in the debugger only. */
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+ csrr t1, mepc /* For viewing in the debugger only */
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+ csrr t2, mstatus /* For viewing in the debugger only */
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+ j .
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+/*-----------------------------------------------------------*/
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+
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+.section .text.freertos_risc_v_exception_handler
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+freertos_risc_v_exception_handler:
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+ portcontextSAVE_EXCEPTION_CONTEXT
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+ /* a0 now contains mcause. */
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+ li t0, 11 /* 11 == environment call. */
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+ bne a0, t0, other_exception /* Not an M environment call, so some other exception. */
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+ call vTaskSwitchContext
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+ portcontextRESTORE_CONTEXT
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+
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+other_exception:
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+ call freertos_risc_v_application_exception_handler
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+ portcontextRESTORE_CONTEXT
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+/*-----------------------------------------------------------*/
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+
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+.section .text.freertos_risc_v_interrupt_handler
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+freertos_risc_v_interrupt_handler:
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+ portcontextSAVE_INTERRUPT_CONTEXT
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+ call freertos_risc_v_application_interrupt_handler
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+ portcontextRESTORE_CONTEXT
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+/*-----------------------------------------------------------*/
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+
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+.section .text.freertos_risc_v_mtimer_interrupt_handler
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+freertos_risc_v_mtimer_interrupt_handler:
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+ portcontextSAVE_INTERRUPT_CONTEXT
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+ portUPDATE_MTIMER_COMPARE_REGISTER
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+ call xTaskIncrementTick
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+ beqz a0, exit_without_context_switch /* Don't switch context if incrementing tick didn't unblock a task. */
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+ call vTaskSwitchContext
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+exit_without_context_switch:
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|
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+ portcontextRESTORE_CONTEXT
|
|
|
+/*-----------------------------------------------------------*/
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|
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+
|
|
|
+.section .text.freertos_risc_v_trap_handler
|
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+.align 8
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+freertos_risc_v_trap_handler:
|
|
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+ portcontextSAVE_CONTEXT_INTERNAL
|
|
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+
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+ csrr a0, mcause
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|
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+ csrr a1, mepc
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+
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|
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+ bge a0, x0, synchronous_exception
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+
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+asynchronous_interrupt:
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+ store_x a1, 0( sp ) /* Asynchronous interrupt so save unmodified exception return address. */
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|
|
+ load_x sp, xISRStackTop /* Switch to ISR stack. */
|
|
|
+ j handle_interrupt
|
|
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+
|
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+synchronous_exception:
|
|
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+ addi a1, a1, 4 /* Synchronous so update exception return address to the instruction after the instruction that generated the exeption. */
|
|
|
+ store_x a1, 0( sp ) /* Save updated exception return address. */
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|
|
+ load_x sp, xISRStackTop /* Switch to ISR stack. */
|
|
|
+ j handle_exception
|
|
|
+
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|
|
+handle_interrupt:
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|
|
+#if( portasmHAS_MTIME != 0 )
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|
|
+
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|
|
+ test_if_mtimer: /* If there is a CLINT then the mtimer is used to generate the tick interrupt. */
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|
|
+ addi t0, x0, 1
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+ slli t0, t0, __riscv_xlen - 1 /* LSB is already set, shift into MSB. Shift 31 on 32-bit or 63 on 64-bit cores. */
|
|
|
+ addi t1, t0, 7 /* 0x8000[]0007 == machine timer interrupt. */
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|
|
+ bne a0, t1, application_interrupt_handler
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|
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+
|
|
|
+ portUPDATE_MTIMER_COMPARE_REGISTER
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|
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+ call xTaskIncrementTick
|
|
|
+ beqz a0, processed_source /* Don't switch context if incrementing tick didn't unblock a task. */
|
|
|
+ call vTaskSwitchContext
|
|
|
+ j processed_source
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|
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+
|
|
|
+#endif /* portasmHAS_MTIME */
|
|
|
+
|
|
|
+application_interrupt_handler:
|
|
|
+ call freertos_risc_v_application_interrupt_handler
|
|
|
+ j processed_source
|
|
|
+
|
|
|
+handle_exception:
|
|
|
+ /* a0 contains mcause. */
|
|
|
+ li t0, 11 /* 11 == environment call. */
|
|
|
+ bne a0, t0, application_exception_handler /* Not an M environment call, so some other exception. */
|
|
|
+ call vTaskSwitchContext
|
|
|
+ j processed_source
|
|
|
+
|
|
|
+application_exception_handler:
|
|
|
+ call freertos_risc_v_application_exception_handler
|
|
|
+ j processed_source /* No other exceptions handled yet. */
|
|
|
+
|
|
|
+processed_source:
|
|
|
+ portcontextRESTORE_CONTEXT
|
|
|
+/*-----------------------------------------------------------*/
|
Zim Kalinowski