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@@ -400,10 +400,11 @@ void esp_deep_sleep_deregister_hook(esp_deep_sleep_cb_t old_dslp_cb)
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portEXIT_CRITICAL(&spinlock_rtc_deep_sleep);
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}
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-#if (CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP && CONFIG_ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND) \
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+#if (CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP && CONFIG_ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND && !CONFIG_IDF_TARGET_ESP32H2) \
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|| CONFIG_ESP_SLEEP_CACHE_SAFE_ASSERTION
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static int s_cache_suspend_cnt = 0;
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+// Must be called from critical sections.
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static void IRAM_ATTR suspend_cache(void) {
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s_cache_suspend_cnt++;
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if (s_cache_suspend_cnt == 1) {
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@@ -411,9 +412,10 @@ static void IRAM_ATTR suspend_cache(void) {
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}
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}
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+// Must be called from critical sections.
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static void IRAM_ATTR resume_cache(void) {
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s_cache_suspend_cnt--;
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- assert(s_cache_suspend_cnt >= 0 && "cache resume doesn't match suspend ops");
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+ assert(s_cache_suspend_cnt >= 0 && DRAM_STR("cache resume doesn't match suspend ops"));
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if (s_cache_suspend_cnt == 0) {
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cache_hal_resume(CACHE_TYPE_ALL);
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}
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@@ -427,7 +429,7 @@ static void IRAM_ATTR flush_uarts(void)
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#ifdef CONFIG_IDF_TARGET_ESP32
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esp_rom_uart_tx_wait_idle(i);
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#else
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- if (periph_ll_periph_enabled(PERIPH_UART0_MODULE + i)) {
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+ if (periph_ll_uart_enabled(i)) {
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esp_rom_uart_tx_wait_idle(i);
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}
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#endif
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@@ -437,14 +439,15 @@ static void IRAM_ATTR flush_uarts(void)
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static uint32_t s_suspended_uarts_bmap = 0;
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/**
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- * Suspend enabled uarts and return suspended uarts bit map
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+ * Suspend enabled uarts and return suspended uarts bit map.
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+ * Must be called from critical sections.
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*/
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-static IRAM_ATTR void suspend_uarts(void)
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+FORCE_INLINE_ATTR void suspend_uarts(void)
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{
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s_suspended_uarts_bmap = 0;
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for (int i = 0; i < SOC_UART_HP_NUM; ++i) {
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#ifndef CONFIG_IDF_TARGET_ESP32
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- if (!periph_ll_periph_enabled(PERIPH_UART0_MODULE + i)) {
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+ if (!periph_ll_uart_enabled(i)) {
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continue;
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}
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#endif
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@@ -461,7 +464,8 @@ static IRAM_ATTR void suspend_uarts(void)
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}
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}
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-static void IRAM_ATTR resume_uarts(void)
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+// Must be called from critical sections
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+FORCE_INLINE_ATTR void resume_uarts(void)
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{
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for (int i = 0; i < SOC_UART_HP_NUM; ++i) {
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if (s_suspended_uarts_bmap & 0x1) {
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@@ -487,7 +491,7 @@ static void IRAM_ATTR resume_uarts(void)
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completion time has exceeded the wakeup time, we should abandon the flush, skip the sleep and
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return ESP_ERR_SLEEP_REJECT.
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*/
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-static bool light_sleep_uart_prepare(uint32_t pd_flags, int64_t sleep_duration)
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+FORCE_INLINE_ATTR bool light_sleep_uart_prepare(uint32_t pd_flags, int64_t sleep_duration)
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{
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bool should_skip_sleep = false;
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#if !SOC_PM_SUPPORT_TOP_PD
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@@ -513,7 +517,7 @@ static bool light_sleep_uart_prepare(uint32_t pd_flags, int64_t sleep_duration)
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/**
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* These save-restore workaround should be moved to lower layer
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*/
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-inline static void IRAM_ATTR misc_modules_sleep_prepare(bool deep_sleep)
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+FORCE_INLINE_ATTR void misc_modules_sleep_prepare(bool deep_sleep)
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{
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if (deep_sleep){
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for (int n = 0; n < MAX_DSLP_HOOKS; n++) {
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@@ -548,7 +552,7 @@ inline static void IRAM_ATTR misc_modules_sleep_prepare(bool deep_sleep)
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/**
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* These save-restore workaround should be moved to lower layer
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*/
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-inline static void IRAM_ATTR misc_modules_wake_prepare(void)
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+FORCE_INLINE_ATTR void misc_modules_wake_prepare(void)
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{
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#if SOC_PM_RETENTION_HAS_REGDMA_POWER_BUG
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sleep_retention_do_system_retention(false);
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@@ -746,7 +750,7 @@ static esp_err_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags, esp_sleep_mode_t m
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In order to avoid the leakage of the SPI cs pin, hold it here */
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#if (CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP && CONFIG_ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND)
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#if !CONFIG_IDF_TARGET_ESP32H2 // ESP32H2 TODO IDF-7359: related rtcio ll func not supported yet
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- if(!(pd_flags & PMU_SLEEP_PD_VDDSDIO)) {
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+ if(!(pd_flags & RTC_SLEEP_PD_VDDSDIO)) {
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/* Cache Suspend 1: will wait cache idle in cache suspend, also means SPI bus IDLE, then we can hold SPI CS pin safely*/
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suspend_cache();
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gpio_ll_hold_en(&GPIO, SPI_CS0_GPIO_NUM);
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@@ -769,7 +773,7 @@ static esp_err_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags, esp_sleep_mode_t m
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/* Unhold the SPI CS pin */
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#if (CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP && CONFIG_ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND)
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#if !CONFIG_IDF_TARGET_ESP32H2 // ESP32H2 TODO IDF-7359: related rtcio ll func not supported yet
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- if(!(pd_flags & PMU_SLEEP_PD_VDDSDIO)) {
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+ if(!(pd_flags & RTC_SLEEP_PD_VDDSDIO)) {
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gpio_ll_hold_dis(&GPIO, SPI_CS0_GPIO_NUM);
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/* Cache Resume 1: Resume cache for continue running*/
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resume_cache();
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@@ -949,7 +953,7 @@ static esp_err_t esp_light_sleep_inner(uint32_t pd_flags,
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* x | 1 | pd flash with relaxed conditions(force_pd)
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* 1 | 0 | pd flash with strict conditions(safe_pd)
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*/
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-static inline bool can_power_down_vddsdio(uint32_t pd_flags, const uint32_t vddsdio_pd_sleep_duration)
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+FORCE_INLINE_ATTR bool can_power_down_vddsdio(uint32_t pd_flags, const uint32_t vddsdio_pd_sleep_duration)
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{
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bool force_pd = !(s_config.wakeup_triggers & RTC_TIMER_TRIG_EN) || (s_config.sleep_duration > vddsdio_pd_sleep_duration);
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bool safe_pd = (s_config.wakeup_triggers == RTC_TIMER_TRIG_EN) && (s_config.sleep_duration > vddsdio_pd_sleep_duration);
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@@ -1702,7 +1706,7 @@ esp_err_t esp_sleep_pd_config(esp_sleep_pd_domain_t domain, esp_sleep_pd_option_
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* the XTAL clock control of some chips(esp32c6/esp32h2) depends on the top domain.
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*/
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#if SOC_PM_SUPPORT_TOP_PD
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-static inline bool top_domain_pd_allowed(void) {
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+FORCE_INLINE_ATTR bool top_domain_pd_allowed(void) {
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return (cpu_domain_pd_allowed() && \
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clock_domain_pd_allowed() && \
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peripheral_domain_pd_allowed() && \
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@@ -1794,7 +1798,7 @@ static uint32_t get_power_down_flags(void)
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s_config.domain[ESP_PD_DOMAIN_XTAL].pd_option = ESP_PD_OPTION_OFF;
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#endif
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- const __attribute__((unused)) char *option_str[] = {"OFF", "ON", "AUTO(OFF)" /* Auto works as OFF */};
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+ const __attribute__((unused)) char *option_str[] = {DRAM_STR("OFF"), DRAM_STR("ON"), DRAM_STR("AUTO(OFF)") /* Auto works as OFF */};
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/* This function is called from a critical section, log with ESP_EARLY_LOGD. */
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#if SOC_PM_SUPPORT_RTC_PERIPH_PD
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ESP_EARLY_LOGD(TAG, "RTC_PERIPH: %s", option_str[s_config.domain[ESP_PD_DOMAIN_RTC_PERIPH].pd_option]);
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wuzhenghui