change(soc): remove / move rom only mmu defs

components/soc/esp32c2/include/soc/ext_mem_defs.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -43,42 +43,11 @@ extern "C" {
 #define ADDRESS_IN_DRAM0(vaddr)            ADDRESS_IN_BUS(DRAM0, vaddr)
 #define ADDRESS_IN_DRAM0_CACHE(vaddr)      ADDRESS_IN_BUS(DRAM0_CACHE, vaddr)
 
-#define BUS_IRAM0_CACHE_SIZE              BUS_SIZE(IRAM0_CACHE)
-#define BUS_DRAM0_CACHE_SIZE              BUS_SIZE(DRAM0_CACHE)
-
-#define CACHE_IBUS                      0
-#define CACHE_IBUS_MMU_START            0
-#define CACHE_IBUS_MMU_END              0x100
-
-#define CACHE_DBUS                      1
-#define CACHE_DBUS_MMU_START            0
-#define CACHE_DBUS_MMU_END              0x100
-
-//TODO, remove these cache function dependencies
-#define CACHE_IROM_MMU_START            0
-#define CACHE_IROM_MMU_END              Cache_Get_IROM_MMU_End()
-#define CACHE_IROM_MMU_SIZE             (CACHE_IROM_MMU_END - CACHE_IROM_MMU_START)
-
-#define CACHE_DROM_MMU_START            CACHE_IROM_MMU_END
-#define CACHE_DROM_MMU_END              Cache_Get_DROM_MMU_End()
-#define CACHE_DROM_MMU_SIZE             (CACHE_DROM_MMU_END - CACHE_DROM_MMU_START)
-
-#define CACHE_DROM_MMU_MAX_END          0x100
-
-#define ICACHE_MMU_SIZE                 0x100
-#define DCACHE_MMU_SIZE                 0x100
-
-#define MMU_BUS_START(i)                0
-#define MMU_BUS_SIZE(i)                 0x100
-
 #define MMU_INVALID                     BIT(6)
 #define MMU_VALID                       0
 #define MMU_TYPE                        0
 #define MMU_ACCESS_FLASH                0
 
-#define CACHE_MAX_SYNC_NUM 0x400000
-#define CACHE_MAX_LOCK_NUM 0x8000
-
 /**
  * MMU entry valid bit mask for mapping value. For an entry:
  * valid bit + value bits
@@ -168,6 +137,36 @@ extern "C" {
 _Static_assert(SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW == SOC_MMU_DRAM0_LINEAR_ADDRESS_LOW, "IRAM0 and DRAM0 linear address should be same");
 
 
+/**
+ * ROM flash mmap driver needs below definitions
+ */
+#define BUS_IRAM0_CACHE_SIZE              BUS_SIZE(IRAM0_CACHE)
+#define BUS_DRAM0_CACHE_SIZE              BUS_SIZE(DRAM0_CACHE)
+
+#define CACHE_IBUS                      0
+#define CACHE_IBUS_MMU_START            0
+#define CACHE_IBUS_MMU_END              0x100
+
+#define CACHE_DBUS                      1
+#define CACHE_DBUS_MMU_START            0
+#define CACHE_DBUS_MMU_END              0x100
+
+#define CACHE_IROM_MMU_START            0
+#define CACHE_IROM_MMU_END              Cache_Get_IROM_MMU_End()
+#define CACHE_IROM_MMU_SIZE             (CACHE_IROM_MMU_END - CACHE_IROM_MMU_START)
+
+#define CACHE_DROM_MMU_START            CACHE_IROM_MMU_END
+#define CACHE_DROM_MMU_END              Cache_Get_DROM_MMU_End()
+#define CACHE_DROM_MMU_SIZE             (CACHE_DROM_MMU_END - CACHE_DROM_MMU_START)
+
+#define CACHE_DROM_MMU_MAX_END          0x100
+
+#define ICACHE_MMU_SIZE                 0x100
+#define DCACHE_MMU_SIZE                 0x100
+
+#define MMU_BUS_START(i)                0
+#define MMU_BUS_SIZE(i)                 0x100
+
 #ifdef __cplusplus
 }
 #endif

components/soc/esp32c3/include/soc/ext_mem_defs.h

@@ -1,10 +1,9 @@
 /*
- * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
-#ifndef _CACHE_MEMORY_H_
-#define _CACHE_MEMORY_H_
+#pragma once
 
 #include "esp_bit_defs.h"
 
@@ -33,42 +32,11 @@ extern "C" {
 #define ADDRESS_IN_DRAM0(vaddr)            ADDRESS_IN_BUS(DRAM0, vaddr)
 #define ADDRESS_IN_DRAM0_CACHE(vaddr)      ADDRESS_IN_BUS(DRAM0_CACHE, vaddr)
 
-#define BUS_IRAM0_CACHE_SIZE              BUS_SIZE(IRAM0_CACHE)
-#define BUS_DRAM0_CACHE_SIZE              BUS_SIZE(DRAM0_CACHE)
-
-#define CACHE_IBUS                      0
-#define CACHE_IBUS_MMU_START            0
-#define CACHE_IBUS_MMU_END              0x200
-
-#define CACHE_DBUS                      1
-#define CACHE_DBUS_MMU_START            0
-#define CACHE_DBUS_MMU_END              0x200
-
-//TODO, remove these cache function dependencies
-#define CACHE_IROM_MMU_START            0
-#define CACHE_IROM_MMU_END              Cache_Get_IROM_MMU_End()
-#define CACHE_IROM_MMU_SIZE             (CACHE_IROM_MMU_END - CACHE_IROM_MMU_START)
-
-#define CACHE_DROM_MMU_START            CACHE_IROM_MMU_END
-#define CACHE_DROM_MMU_END              Cache_Get_DROM_MMU_End()
-#define CACHE_DROM_MMU_SIZE             (CACHE_DROM_MMU_END - CACHE_DROM_MMU_START)
-
-#define CACHE_DROM_MMU_MAX_END          0x200
-
-#define ICACHE_MMU_SIZE                 0x200
-#define DCACHE_MMU_SIZE                 0x200
-
-#define MMU_BUS_START(i)                0
-#define MMU_BUS_SIZE(i)                 0x200
-
 #define MMU_INVALID                     BIT(8)
 #define MMU_VALID                       0
 #define MMU_TYPE                        0
 #define MMU_ACCESS_FLASH                0
 
-#define CACHE_MAX_SYNC_NUM 0x400000
-#define CACHE_MAX_LOCK_NUM 0x8000
-
 /**
  * MMU entry valid bit mask for mapping value. For an entry:
  * valid bit + value bits
@@ -135,8 +103,36 @@ extern "C" {
 _Static_assert(SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW == SOC_MMU_DRAM0_LINEAR_ADDRESS_LOW, "IRAM0 and DRAM0 linear address should be same");
 
 
+/**
+ * ROM flash mmap driver needs below definitions
+ */
+#define BUS_IRAM0_CACHE_SIZE              BUS_SIZE(IRAM0_CACHE)
+#define BUS_DRAM0_CACHE_SIZE              BUS_SIZE(DRAM0_CACHE)
+
+#define CACHE_IBUS                      0
+#define CACHE_IBUS_MMU_START            0
+#define CACHE_IBUS_MMU_END              0x200
+
+#define CACHE_DBUS                      1
+#define CACHE_DBUS_MMU_START            0
+#define CACHE_DBUS_MMU_END              0x200
+
+#define CACHE_IROM_MMU_START            0
+#define CACHE_IROM_MMU_END              Cache_Get_IROM_MMU_End()
+#define CACHE_IROM_MMU_SIZE             (CACHE_IROM_MMU_END - CACHE_IROM_MMU_START)
+
+#define CACHE_DROM_MMU_START            CACHE_IROM_MMU_END
+#define CACHE_DROM_MMU_END              Cache_Get_DROM_MMU_End()
+#define CACHE_DROM_MMU_SIZE             (CACHE_DROM_MMU_END - CACHE_DROM_MMU_START)
+
+#define CACHE_DROM_MMU_MAX_END          0x200
+
+#define ICACHE_MMU_SIZE                 0x200
+#define DCACHE_MMU_SIZE                 0x200
+
+#define MMU_BUS_START(i)                0
+#define MMU_BUS_SIZE(i)                 0x200
+
 #ifdef __cplusplus
 }
 #endif
-
-#endif /*_CACHE_MEMORY_H_ */

components/soc/esp32c6/include/soc/ext_mem_defs.h

@@ -35,25 +35,6 @@ extern "C" {
 #define ADDRESS_IN_DRAM0(vaddr)            ADDRESS_IN_BUS(DRAM0, vaddr)
 #define ADDRESS_IN_DRAM0_CACHE(vaddr)      ADDRESS_IN_BUS(DRAM0_CACHE, vaddr)
 
-#define BUS_IRAM0_CACHE_SIZE              BUS_SIZE(IRAM0_CACHE)
-#define BUS_DRAM0_CACHE_SIZE              BUS_SIZE(DRAM0_CACHE)
-
-//TODO, remove these cache function dependencies
-#define CACHE_IROM_MMU_START            0
-#define CACHE_IROM_MMU_END              Cache_Get_IROM_MMU_End()
-#define CACHE_IROM_MMU_SIZE             (CACHE_IROM_MMU_END - CACHE_IROM_MMU_START)
-
-#define CACHE_DROM_MMU_START            CACHE_IROM_MMU_END
-#define CACHE_DROM_MMU_END              Cache_Get_DROM_MMU_End()
-#define CACHE_DROM_MMU_SIZE             (CACHE_DROM_MMU_END - CACHE_DROM_MMU_START)
-
-#define CACHE_DROM_MMU_MAX_END          0x400
-
-#define ICACHE_MMU_SIZE                 0x200
-#define DCACHE_MMU_SIZE                 0x200
-
-#define MMU_BUS_START(i)                0
-#define MMU_BUS_SIZE(i)                 0x200
 
 #define MMU_MSPI_ACCESS_FLASH           0
 #define MMU_MSPI_VALID                  BIT(9)
@@ -67,11 +48,6 @@ extern "C" {
 #define MMU_INVALID_MASK                MMU_MSPI_VALID
 #define MMU_INVALID                     MMU_MSPI_INVALID
 
-
-
-#define CACHE_MAX_SYNC_NUM 0x400000
-#define CACHE_MAX_LOCK_NUM 0x8000
-
 /**
  * MMU entry valid bit mask for mapping value. For an entry:
  * valid bit + value bits
@@ -155,6 +131,25 @@ extern "C" {
 _Static_assert(SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW == SOC_MMU_DRAM0_LINEAR_ADDRESS_LOW, "IRAM0 and DRAM0 linear address should be same");
 
 
+/**
+ * ROM flash mmap driver needs below definitions
+ */
+#define CACHE_IROM_MMU_START            0
+#define CACHE_IROM_MMU_END              Cache_Get_IROM_MMU_End()
+#define CACHE_IROM_MMU_SIZE             (CACHE_IROM_MMU_END - CACHE_IROM_MMU_START)
+
+#define CACHE_DROM_MMU_START            CACHE_IROM_MMU_END
+#define CACHE_DROM_MMU_END              Cache_Get_DROM_MMU_End()
+#define CACHE_DROM_MMU_SIZE             (CACHE_DROM_MMU_END - CACHE_DROM_MMU_START)
+
+#define CACHE_DROM_MMU_MAX_END          0x400
+
+#define ICACHE_MMU_SIZE                 0x200
+#define DCACHE_MMU_SIZE                 0x200
+
+#define MMU_BUS_START(i)                0
+#define MMU_BUS_SIZE(i)                 0x200
+
 #ifdef __cplusplus
 }
 #endif

components/soc/esp32h2/include/soc/ext_mem_defs.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -35,26 +35,6 @@ extern "C" {
 #define ADDRESS_IN_DRAM0(vaddr)            ADDRESS_IN_BUS(DRAM0, vaddr)
 #define ADDRESS_IN_DRAM0_CACHE(vaddr)      ADDRESS_IN_BUS(DRAM0_CACHE, vaddr)
 
-#define BUS_IRAM0_CACHE_SIZE(page_size)              BUS_SIZE(IRAM0_CACHE)
-#define BUS_DRAM0_CACHE_SIZE(page_size)              BUS_SIZE(DRAM0_CACHE)
-
-//TODO, remove these cache function dependencies
-#define CACHE_IROM_MMU_START            0
-#define CACHE_IROM_MMU_END              Cache_Get_IROM_MMU_End()
-#define CACHE_IROM_MMU_SIZE             (CACHE_IROM_MMU_END - CACHE_IROM_MMU_START)
-
-#define CACHE_DROM_MMU_START            CACHE_IROM_MMU_END
-#define CACHE_DROM_MMU_END              Cache_Get_DROM_MMU_End()
-#define CACHE_DROM_MMU_SIZE             (CACHE_DROM_MMU_END - CACHE_DROM_MMU_START)
-
-#define CACHE_DROM_MMU_MAX_END          0x400
-
-#define ICACHE_MMU_SIZE                 0x200
-#define DCACHE_MMU_SIZE                 0x200
-
-#define MMU_BUS_START(i)                0
-#define MMU_BUS_SIZE(i)                 0x200
-
 #define MMU_MSPI_ACCESS_FLASH           0
 #define MMU_MSPI_VALID                  BIT(9)
 #define MMU_MSPI_INVALID                0
@@ -67,11 +47,6 @@ extern "C" {
 #define MMU_INVALID_MASK                MMU_MSPI_VALID
 #define MMU_INVALID                     MMU_MSPI_INVALID
 
-
-
-#define CACHE_MAX_SYNC_NUM 0x400000
-#define CACHE_MAX_LOCK_NUM 0x8000
-
 /**
  * MMU entry valid bit mask for mapping value. For an entry:
  * valid bit + value bits
@@ -155,6 +130,28 @@ extern "C" {
 _Static_assert(SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW == SOC_MMU_DRAM0_LINEAR_ADDRESS_LOW, "IRAM0 and DRAM0 linear address should be same");
 
 
+/**
+ * ROM flash mmap driver needs below definitions
+ */
+#define BUS_IRAM0_CACHE_SIZE(page_size)              BUS_SIZE(IRAM0_CACHE)
+#define BUS_DRAM0_CACHE_SIZE(page_size)              BUS_SIZE(DRAM0_CACHE)
+
+#define CACHE_IROM_MMU_START            0
+#define CACHE_IROM_MMU_END              Cache_Get_IROM_MMU_End()
+#define CACHE_IROM_MMU_SIZE             (CACHE_IROM_MMU_END - CACHE_IROM_MMU_START)
+
+#define CACHE_DROM_MMU_START            CACHE_IROM_MMU_END
+#define CACHE_DROM_MMU_END              Cache_Get_DROM_MMU_End()
+#define CACHE_DROM_MMU_SIZE             (CACHE_DROM_MMU_END - CACHE_DROM_MMU_START)
+
+#define CACHE_DROM_MMU_MAX_END          0x400
+
+#define ICACHE_MMU_SIZE                 0x200
+#define DCACHE_MMU_SIZE                 0x200
+
+#define MMU_BUS_START(i)                0
+#define MMU_BUS_SIZE(i)                 0x200
+
 #ifdef __cplusplus
 }
 #endif

components/soc/esp32p4/include/soc/ext_mem_defs.h

@@ -40,23 +40,6 @@ extern "C" {
 #define ADDRESS_IN_DRAM_FLASH(vaddr)       ADDRESS_IN_BUS(DRAM_FLASH, vaddr)
 #define ADDRESS_IN_DRAM_PSRAM(vaddr)       ADDRESS_IN_BUS(DRAM_PSRAM, vaddr)
 
-//TODO, remove these cache function dependencies
-#define CACHE_IROM_MMU_START            0
-#define CACHE_IROM_MMU_END              Cache_Get_IROM_MMU_End()
-#define CACHE_IROM_MMU_SIZE             (CACHE_IROM_MMU_END - CACHE_IROM_MMU_START)
-
-#define CACHE_DROM_MMU_START            CACHE_IROM_MMU_END
-#define CACHE_DROM_MMU_END              Cache_Get_DROM_MMU_End()
-#define CACHE_DROM_MMU_SIZE             (CACHE_DROM_MMU_END - CACHE_DROM_MMU_START)
-
-#define CACHE_DROM_MMU_MAX_END          0x400
-
-#define ICACHE_MMU_SIZE                 (0x400 * 4)
-#define DCACHE_MMU_SIZE                 (0x400 * 4)
-
-#define MMU_BUS_START(i)                0
-#define MMU_BUS_SIZE(i)                 (0x400 * 4)
-
 
 #define MMU_FLASH_VALID                 BIT(12)
 #define MMU_FLASH_INVALID               0
@@ -70,9 +53,6 @@ extern "C" {
 #define MMU_PSRAM_SENSITIVE             BIT(12)
 
 
-#define CACHE_MAX_SYNC_NUM 0x400000
-#define CACHE_MAX_LOCK_NUM 0x8000
-
 /**
  * MMU entry valid bit mask for mapping value.
  * - For a Flash MMU entry:

components/soc/esp32s3/include/soc/ext_mem_defs.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -32,43 +32,12 @@ extern "C" {
 #define ADDRESS_IN_DRAM0(vaddr)            ADDRESS_IN_BUS(DRAM0, vaddr)
 #define ADDRESS_IN_DRAM0_CACHE(vaddr)      ADDRESS_IN_BUS(DRAM0_CACHE, vaddr)
 
-#define BUS_IRAM0_CACHE_SIZE              BUS_SIZE(IRAM0_CACHE)
-#define BUS_DRAM0_CACHE_SIZE              BUS_SIZE(DRAM0_CACHE)
-
-#define CACHE_IBUS                      0
-#define CACHE_IBUS_MMU_START            0
-#define CACHE_IBUS_MMU_END              0x800
-
-#define CACHE_DBUS                      1
-#define CACHE_DBUS_MMU_START            0
-#define CACHE_DBUS_MMU_END              0x800
-
-//TODO, remove these cache function dependencies
-#define CACHE_IROM_MMU_START            0
-#define CACHE_IROM_MMU_END              Cache_Get_IROM_MMU_End()
-#define CACHE_IROM_MMU_SIZE             (CACHE_IROM_MMU_END - CACHE_IROM_MMU_START)
-
-#define CACHE_DROM_MMU_START            CACHE_IROM_MMU_END
-#define CACHE_DROM_MMU_END              Cache_Get_DROM_MMU_End()
-#define CACHE_DROM_MMU_SIZE             (CACHE_DROM_MMU_END - CACHE_DROM_MMU_START)
-
-#define CACHE_DROM_MMU_MAX_END          0x400
-
-#define ICACHE_MMU_SIZE                 0x800
-#define DCACHE_MMU_SIZE                 0x800
-
-#define MMU_BUS_START(i)                0
-#define MMU_BUS_SIZE(i)                 0x800
-
 #define MMU_INVALID                     BIT(14)
 #define MMU_VALID                       0
 #define MMU_TYPE                        BIT(15)
 #define MMU_ACCESS_FLASH                0
 #define MMU_ACCESS_SPIRAM               BIT(15)
 
-#define CACHE_MAX_SYNC_NUM 0x400000
-#define CACHE_MAX_LOCK_NUM 0x8000
-
 /**
  * MMU entry valid bit mask for mapping value. For an entry:
  * valid bit + value bits
@@ -141,6 +110,37 @@ extern "C" {
 _Static_assert(SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW == SOC_MMU_DRAM0_LINEAR_ADDRESS_LOW, "IRAM0 and DRAM0 linear address should be same");
 #endif
 
+
+/**
+ * ROM flash mmap driver needs below definitions
+ */
+#define BUS_IRAM0_CACHE_SIZE              BUS_SIZE(IRAM0_CACHE)
+#define BUS_DRAM0_CACHE_SIZE              BUS_SIZE(DRAM0_CACHE)
+
+#define CACHE_IBUS                      0
+#define CACHE_IBUS_MMU_START            0
+#define CACHE_IBUS_MMU_END              0x800
+
+#define CACHE_DBUS                      1
+#define CACHE_DBUS_MMU_START            0
+#define CACHE_DBUS_MMU_END              0x800
+
+#define CACHE_IROM_MMU_START            0
+#define CACHE_IROM_MMU_END              Cache_Get_IROM_MMU_End()
+#define CACHE_IROM_MMU_SIZE             (CACHE_IROM_MMU_END - CACHE_IROM_MMU_START)
+
+#define CACHE_DROM_MMU_START            CACHE_IROM_MMU_END
+#define CACHE_DROM_MMU_END              Cache_Get_DROM_MMU_End()
+#define CACHE_DROM_MMU_SIZE             (CACHE_DROM_MMU_END - CACHE_DROM_MMU_START)
+
+#define CACHE_DROM_MMU_MAX_END          0x400
+
+#define ICACHE_MMU_SIZE                 0x800
+#define DCACHE_MMU_SIZE                 0x800
+
+#define MMU_BUS_START(i)                0
+#define MMU_BUS_SIZE(i)                 0x800
+
 #ifdef __cplusplus
 }
 #endif