bugfix(gpio):fix esp32 s2 rtc io issue

* Modify the function implementation of ESP32-S2 RTC GPIO
  On ESP32 those PADs which have RTC functions must set pullup/down/capability via RTC register.
  On ESP32-S2, Digital IOs have their own registers to control pullup/down/capability, independent with RTC registers.
* Add ESP32-S2 support of unit test
* Modify the pull-up test of unit test
* Modify the interrupt test of unit test
* Modify input and output mode test of unit test

components/driver/gpio.c

@@ -75,12 +75,12 @@ esp_err_t gpio_pullup_en(gpio_num_t gpio_num)
 {
     GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG);
 
-    if (rtc_gpio_is_valid_gpio(gpio_num)) {
-        rtc_gpio_pullup_en(gpio_num);
-    } else {
+    if (!rtc_gpio_is_valid_gpio(gpio_num) || GPIO_SUPPORTS_RTC_INDEPENDENT) {
         portENTER_CRITICAL(&gpio_context.gpio_spinlock);
         gpio_hal_pullup_en(gpio_context.gpio_hal, gpio_num);
         portEXIT_CRITICAL(&gpio_context.gpio_spinlock);
+    } else {
+        rtc_gpio_pullup_en(gpio_num);
     }
 
     return ESP_OK;
@@ -90,12 +90,12 @@ esp_err_t gpio_pullup_dis(gpio_num_t gpio_num)
 {
     GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG);
 
-    if (rtc_gpio_is_valid_gpio(gpio_num)) {
-        rtc_gpio_pullup_dis(gpio_num);
-    } else {
+    if (!rtc_gpio_is_valid_gpio(gpio_num) || GPIO_SUPPORTS_RTC_INDEPENDENT) {
         portENTER_CRITICAL(&gpio_context.gpio_spinlock);
         gpio_hal_pullup_dis(gpio_context.gpio_hal, gpio_num);
         portEXIT_CRITICAL(&gpio_context.gpio_spinlock);
+    } else {
+        rtc_gpio_pullup_dis(gpio_num);
     }
 
     return ESP_OK;
@@ -105,12 +105,12 @@ esp_err_t gpio_pulldown_en(gpio_num_t gpio_num)
 {
     GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG);
 
-    if (rtc_gpio_is_valid_gpio(gpio_num)) {
-        rtc_gpio_pulldown_en(gpio_num);
-    } else {
+    if (!rtc_gpio_is_valid_gpio(gpio_num) || GPIO_SUPPORTS_RTC_INDEPENDENT) {
         portENTER_CRITICAL(&gpio_context.gpio_spinlock);
         gpio_hal_pulldown_en(gpio_context.gpio_hal, gpio_num);
         portEXIT_CRITICAL(&gpio_context.gpio_spinlock);
+    } else {
+        rtc_gpio_pulldown_en(gpio_num);
     }
 
     return ESP_OK;
@@ -120,12 +120,12 @@ esp_err_t gpio_pulldown_dis(gpio_num_t gpio_num)
 {
     GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG);
 
-    if (rtc_gpio_is_valid_gpio(gpio_num)) {
-        rtc_gpio_pulldown_dis(gpio_num);
-    } else {
+    if (!rtc_gpio_is_valid_gpio(gpio_num) || GPIO_SUPPORTS_RTC_INDEPENDENT) {
         portENTER_CRITICAL(&gpio_context.gpio_spinlock);
         gpio_hal_pulldown_dis(gpio_context.gpio_hal, gpio_num);
         portEXIT_CRITICAL(&gpio_context.gpio_spinlock);
+    } else {
+        rtc_gpio_pulldown_dis(gpio_num);
     }
 
     return ESP_OK;
@@ -429,7 +429,7 @@ static void IRAM_ATTR gpio_intr_service(void *arg)
 
     if (gpio_intr_status_h) {
         gpio_isr_loop(gpio_intr_status_h, 32);
-        gpio_hal_clear_intr_status_high(gpio_context.gpio_hal, gpio_intr_status);
+        gpio_hal_clear_intr_status_high(gpio_context.gpio_hal, gpio_intr_status_h);
     }
 }
 
@@ -569,13 +569,14 @@ esp_err_t gpio_set_drive_capability(gpio_num_t gpio_num, gpio_drive_cap_t streng
     GPIO_CHECK(strength < GPIO_DRIVE_CAP_MAX, "GPIO drive capability error", ESP_ERR_INVALID_ARG);
     esp_err_t ret = ESP_OK;
 
-    if (rtc_gpio_is_valid_gpio(gpio_num)) {
-        ret = rtc_gpio_set_drive_capability(gpio_num, strength);
-    } else {
+    if (!rtc_gpio_is_valid_gpio(gpio_num) || GPIO_SUPPORTS_RTC_INDEPENDENT) {
         portENTER_CRITICAL(&gpio_context.gpio_spinlock);
         gpio_hal_set_drive_capability(gpio_context.gpio_hal, gpio_num, strength);
         portEXIT_CRITICAL(&gpio_context.gpio_spinlock);
+    } else {
+        ret = rtc_gpio_set_drive_capability(gpio_num, strength);
     }
+
     return ret;
 }
 
@@ -585,13 +586,14 @@ esp_err_t gpio_get_drive_capability(gpio_num_t gpio_num, gpio_drive_cap_t *stren
     GPIO_CHECK(strength != NULL, "GPIO drive capability pointer error", ESP_ERR_INVALID_ARG);
     esp_err_t ret = ESP_OK;
 
-    if (rtc_gpio_is_valid_gpio(gpio_num)) {
-        ret = rtc_gpio_get_drive_capability(gpio_num, strength);
-    } else {
+    if (!rtc_gpio_is_valid_gpio(gpio_num) || GPIO_SUPPORTS_RTC_INDEPENDENT) {
         portENTER_CRITICAL(&gpio_context.gpio_spinlock);
         gpio_hal_get_drive_capability(gpio_context.gpio_hal, gpio_num, strength);
         portEXIT_CRITICAL(&gpio_context.gpio_spinlock);
+    } else {
+        ret = rtc_gpio_get_drive_capability(gpio_num, strength);
     }
+
     return ret;
 }
 
@@ -645,14 +647,13 @@ void gpio_deep_sleep_hold_dis(void)
     portEXIT_CRITICAL(&gpio_context.gpio_spinlock);
 }
 
-#if CONFIG_IDF_TARGET_ESP32S2BETA
+#if GPIO_SUPPORTS_FORCE_HOLD
 
 esp_err_t gpio_force_hold_all()
 {
     rtc_gpio_force_hold_all();
     portENTER_CRITICAL(&gpio_context.gpio_spinlock);
-    CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD);
-    SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_HOLD);
+    gpio_hal_force_hold_all(gpio_context.gpio_hal);
     portEXIT_CRITICAL(&gpio_context.gpio_spinlock);
     return ESP_OK;
 }
@@ -661,9 +662,7 @@ esp_err_t gpio_force_unhold_all()
 {
     rtc_gpio_force_hold_dis_all();
     portENTER_CRITICAL(&gpio_context.gpio_spinlock);
-    CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_HOLD);
-    SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD);
-    SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_CLR_DG_PAD_AUTOHOLD);
+    gpio_hal_force_unhold_all(gpio_context.gpio_hal);
     portEXIT_CRITICAL(&gpio_context.gpio_spinlock);
     return ESP_OK;
 }

components/driver/include/driver/gpio.h

@@ -411,7 +411,7 @@ void gpio_iomux_in(uint32_t gpio_num, uint32_t signal_idx);
   */
 void gpio_iomux_out(uint8_t gpio_num, int func, bool oen_inv);
 
-#if CONFIG_IDF_TARGET_ESP32S2BETA
+#if GPIO_SUPPORTS_FORCE_HOLD
 /**
   * @brief Force hold digital and rtc gpio pad. 
   * @note GPIO force hold, whether the chip in sleep mode or wakeup mode. 

components/driver/test/esp32/test_gpio.c

@@ -21,9 +21,16 @@
 #endif
 
 #define WAKE_UP_IGNORE 1  // gpio_wakeup function development is not completed yet, set it deprecated.
+#if CONFIG_IDF_TARGET_ESP32
 #define GPIO_OUTPUT_IO   18  // default output GPIO
 #define GPIO_INPUT_IO   19  // default input GPIO
 #define GPIO_OUTPUT_MAX GPIO_NUM_34
+#elif CONFIG_IDF_TARGET_ESP32S2BETA
+// ESP32_S2 DEVKIC uses IO19 and IO20 as USB functions, so it is necessary to avoid using IO19, otherwise GPIO io pull up/down function cannot pass
+#define GPIO_OUTPUT_IO   18  // default output GPIO
+#define GPIO_INPUT_IO   21  // default input GPIO
+#define GPIO_OUTPUT_MAX GPIO_NUM_46
+#endif
 static volatile int disable_intr_times = 0;  // use this to calculate how many times it go into interrupt
 static volatile int level_intr_times = 0;  // use this to get how many times the level interrupt happened
 static volatile int edge_intr_times = 0;   // use this to get how many times the edge interrupt happened
@@ -135,8 +142,9 @@ static void drive_capability_set_get(gpio_num_t num, gpio_drive_cap_t capability
 TEST_CASE("GPIO config parameters test", "[gpio]")
 {
     //error param test
-    //test 41 bit
+    //ESP32 test 41 bit, ESP32-S2 test 48 bit
     gpio_config_t io_config;
+    io_config.intr_type = GPIO_PIN_INTR_DISABLE;
     io_config.pin_bit_mask = ((uint64_t)1<<(GPIO_NUM_MAX+1));
     TEST_ASSERT(gpio_config(&io_config) == ESP_ERR_INVALID_ARG);
 
@@ -144,10 +152,11 @@ TEST_CASE("GPIO config parameters test", "[gpio]")
     io_config.pin_bit_mask = 0;
     TEST_ASSERT(gpio_config(&io_config) == ESP_ERR_INVALID_ARG);
 
-    //test 40 bit
+    //ESP32 test 40 bit, ESP32-S2 test 47 bit
     io_config.pin_bit_mask = ((uint64_t)1<<GPIO_NUM_MAX);
     TEST_ASSERT(gpio_config(&io_config) == ESP_ERR_INVALID_ARG);
 
+#if CONFIG_IDF_TARGET_ESP32
     io_config.pin_bit_mask = (uint64_t)1<<23;
     TEST_ESP_OK(gpio_config(&io_config));
 
@@ -155,8 +164,20 @@ TEST_CASE("GPIO config parameters test", "[gpio]")
     io_config.mode = GPIO_MODE_INPUT;
     TEST_ESP_OK(gpio_config(&io_config));
     io_config.mode = GPIO_MODE_OUTPUT;
-    // 34-39 input only, once set as output should log something
+    // ESP32 34-39 input only, once set as output should log something
+    TEST_ASSERT(gpio_config(&io_config) == ESP_ERR_INVALID_ARG);
+#elif CONFIG_IDF_TARGET_ESP32S2BETA
+    io_config.pin_bit_mask = (uint64_t)1<<26;
+    TEST_ESP_OK(gpio_config(&io_config));
+
+    io_config.pin_bit_mask = ((uint64_t)1 << 46);
+    io_config.mode = GPIO_MODE_INPUT;
+    TEST_ESP_OK(gpio_config(&io_config));
+    io_config.mode = GPIO_MODE_OUTPUT;
+    // ESP32-S2 46 input only, once set as output should log something
     TEST_ASSERT(gpio_config(&io_config) == ESP_ERR_INVALID_ARG);
+#endif
+
 }
 
 TEST_CASE("GPIO rising edge interrupt test", "[gpio][test_env=UT_T1_GPIO]")
@@ -321,6 +342,7 @@ TEST_CASE("GPIO multi-level interrupt test, to cut the interrupt source exit int
 
 TEST_CASE("GPIO enable and disable interrupt test", "[gpio][test_env=UT_T1_GPIO]")
 {
+    disable_intr_times = 0;
     gpio_config_t output_io = init_io(GPIO_OUTPUT_IO);
     gpio_config_t input_io = init_io(GPIO_INPUT_IO);
     input_io.intr_type = GPIO_INTR_POSEDGE;
@@ -329,6 +351,7 @@ TEST_CASE("GPIO enable and disable interrupt test", "[gpio][test_env=UT_T1_GPIO]
     TEST_ESP_OK(gpio_config(&output_io));
     TEST_ESP_OK(gpio_config(&input_io));
 
+    TEST_ESP_OK(gpio_set_level(GPIO_OUTPUT_IO, 0)); // Because of GPIO_INTR_HIGH_LEVEL interrupt, 0 must be set first
     TEST_ESP_OK(gpio_set_intr_type(GPIO_INPUT_IO, GPIO_INTR_HIGH_LEVEL));
     TEST_ESP_OK(gpio_install_isr_service(0));
     TEST_ESP_OK(gpio_isr_handler_add(GPIO_INPUT_IO, gpio_isr_level_handler, (void*) GPIO_INPUT_IO));
@@ -348,7 +371,7 @@ TEST_CASE("GPIO enable and disable interrupt test", "[gpio][test_env=UT_T1_GPIO]
     TEST_ASSERT(gpio_isr_handler_remove(GPIO_INPUT_IO) == ESP_ERR_INVALID_STATE);
 }
 
-// Connect GPIO18 with GPIO19
+// ESP32 Connect GPIO18 with GPIO19, ESP32-S2 Connect GPIO18 with GPIO21
 // use multimeter to test the voltage, so it is ignored in CI
 TEST_CASE("GPIO set gpio output level test", "[gpio][ignore]")
 {
@@ -372,12 +395,20 @@ TEST_CASE("GPIO set gpio output level test", "[gpio][ignore]")
     // tested voltage is around 3.3v
     TEST_ASSERT_EQUAL_INT_MESSAGE(gpio_get_level(GPIO_INPUT_IO), 1, "get level error! the level should be high!");
 
-    //IO34-39 are just used for input
+
+#if CONFIG_IDF_TARGET_ESP32
+    //ESP32 IO34-39 are just used for input
     io_conf.pin_bit_mask = ((uint64_t)1<<34);
     io_conf.mode = GPIO_MODE_OUTPUT;
     gpio_config(&io_conf);
     TEST_ASSERT(gpio_config(&io_conf) == ESP_ERR_INVALID_ARG);
-
+#elif CONFIG_IDF_TARGET_ESP32S2BETA
+    //ESP32-S2 IO46 are just used for input
+    io_conf.pin_bit_mask = ((uint64_t)1<<46);
+    io_conf.mode = GPIO_MODE_OUTPUT;
+    gpio_config(&io_conf);
+    TEST_ASSERT(gpio_config(&io_conf) == ESP_ERR_INVALID_ARG);
+#endif
 }
 
 // gpio17 connects to 3.3v pin, gpio19 connects to the GND pin
@@ -405,7 +436,11 @@ TEST_CASE("GPIO get input level test", "[gpio][ignore]")
 
 TEST_CASE("GPIO io pull up/down function", "[gpio]")
 {
-    gpio_config_t  io_conf = init_io(GPIO_INPUT_IO);
+    // First, ensure that the output IO will not affect the level
+    gpio_config_t  io_conf = init_io(GPIO_OUTPUT_IO);
+    gpio_config(&io_conf);
+    gpio_set_direction(GPIO_OUTPUT_IO, GPIO_MODE_INPUT);
+    io_conf = init_io(GPIO_INPUT_IO);
     gpio_config(&io_conf);
     gpio_set_direction(GPIO_INPUT_IO, GPIO_MODE_INPUT);
     TEST_ESP_OK(gpio_pullup_en(GPIO_INPUT_IO));  // pull up first
@@ -424,7 +459,7 @@ TEST_CASE("GPIO io pull up/down function", "[gpio]")
 
 TEST_CASE("GPIO output and input mode test", "[gpio][test_env=UT_T1_GPIO]")
 {
-    //connect io18 and io5
+    //ESP32 connect io18 and io19, ESP32-S2 connect io18 and io21
     gpio_config_t output_io = init_io(GPIO_OUTPUT_IO);
     gpio_config_t input_io = init_io(GPIO_INPUT_IO);
     gpio_config(&output_io);
@@ -469,12 +504,6 @@ TEST_CASE("GPIO output and input mode test", "[gpio][test_env=UT_T1_GPIO]")
     gpio_set_direction(GPIO_INPUT_IO, GPIO_MODE_INPUT);
     gpio_set_level(GPIO_OUTPUT_IO, !level);
     TEST_ASSERT_EQUAL_INT_MESSAGE(gpio_get_level(GPIO_INPUT_IO), !level, "direction set error, it can't output");
-    // input test
-    gpio_set_direction(GPIO_OUTPUT_IO, GPIO_MODE_OUTPUT);
-    gpio_set_direction(GPIO_INPUT_IO, GPIO_MODE_INPUT_OUTPUT);
-    level = gpio_get_level(GPIO_INPUT_IO);
-    gpio_set_level(GPIO_OUTPUT_IO, !level);
-    TEST_ASSERT_EQUAL_INT_MESSAGE(gpio_get_level(GPIO_INPUT_IO), !level, "direction set error, it can't output");
 }
 
 TEST_CASE("GPIO repeate call service and isr has no memory leak test","[gpio][test_env=UT_T1_GPIO][timeout=90]")
@@ -692,10 +721,10 @@ static void gpio_isr_handler(void* arg)
  * But this will incorrectly handle the interrupt disabled GPIOs, because the raw interrupt status register can still be set when
  * the trigger signal arrives, even if the interrupt is disabled.
  * First on the core 0:
- *     1. Configure the GPIO18 and GPIO19 input_output mode.
- *     2. Enable GPIO18 dual edge triggered interrupt, enable GPIO19 falling edge triggered interrupt.
+ *     1. Configure the GPIO18 and GPIO19(ESP32)/GPIO21(ESP32-S2) input_output mode.
+ *     2. Enable GPIO18 dual edge triggered interrupt, enable GPIO19(ESP32)/GPIO21(ESP32-S2) falling edge triggered interrupt.
  *     3. Trigger GPIO18 interrupt, than disable the GPIO8 interrupt, and than trigger GPIO18 again(This time will not respond to the interrupt).
- *     4. Trigger GPIO19 interrupt.
+ *     4. Trigger GPIO19(ESP32)/GPIO21(ESP32-S2) interrupt.
  * If the bug is not fixed, you will see, in the step 4, the interrupt of GPIO18 will also respond.
  */
 TEST_CASE("GPIO ISR service test", "[gpio][ignore]")

components/soc/esp32/include/soc/gpio_caps.h

@@ -19,90 +19,14 @@ extern "C" {
 #endif
 
 // ESP32 has 1 GPIO peripheral
-#define GPIO_PORT_0             (0) /*!< GPIO port 0 */
-#define GPIO_PORT_MAX           (1) /*!< GPIO port max */
-#define SOC_GPIO_PORT           (GPIO_PORT_MAX)
+#define SOC_GPIO_PORT           (1)
 #define GPIO_PIN_COUNT          (40)
 
-#define GPIO_SEL_0              (BIT(0))                         /*!< Pin 0 selected */
-#define GPIO_SEL_1              (BIT(1))                         /*!< Pin 1 selected */
-#define GPIO_SEL_2              (BIT(2))                         /*!< Pin 2 selected
-                                                                      @note There are more macros
-                                                                      like that up to pin 39,
-                                                                      excluding pins 20, 24 and 28..31.
-                                                                      They are not shown here
-                                                                      to reduce redundant information. */
-/** @cond */
-#define GPIO_SEL_3              (BIT(3))                         /*!< Pin 3 selected */
-#define GPIO_SEL_4              (BIT(4))                         /*!< Pin 4 selected */
-#define GPIO_SEL_5              (BIT(5))                         /*!< Pin 5 selected */
-#define GPIO_SEL_6              (BIT(6))                         /*!< Pin 6 selected */
-#define GPIO_SEL_7              (BIT(7))                         /*!< Pin 7 selected */
-#define GPIO_SEL_8              (BIT(8))                         /*!< Pin 8 selected */
-#define GPIO_SEL_9              (BIT(9))                         /*!< Pin 9 selected */
-#define GPIO_SEL_10             (BIT(10))                        /*!< Pin 10 selected */
-#define GPIO_SEL_11             (BIT(11))                        /*!< Pin 11 selected */
-#define GPIO_SEL_12             (BIT(12))                        /*!< Pin 12 selected */
-#define GPIO_SEL_13             (BIT(13))                        /*!< Pin 13 selected */
-#define GPIO_SEL_14             (BIT(14))                        /*!< Pin 14 selected */
-#define GPIO_SEL_15             (BIT(15))                        /*!< Pin 15 selected */
-#define GPIO_SEL_16             (BIT(16))                        /*!< Pin 16 selected */
-#define GPIO_SEL_17             (BIT(17))                        /*!< Pin 17 selected */
-#define GPIO_SEL_18             (BIT(18))                        /*!< Pin 18 selected */
-#define GPIO_SEL_19             (BIT(19))                        /*!< Pin 19 selected */
-
-#define GPIO_SEL_21             (BIT(21))                        /*!< Pin 21 selected */
-#define GPIO_SEL_22             (BIT(22))                        /*!< Pin 22 selected */
-#define GPIO_SEL_23             (BIT(23))                        /*!< Pin 23 selected */
-
-#define GPIO_SEL_25             (BIT(25))                        /*!< Pin 25 selected */
-#define GPIO_SEL_26             (BIT(26))                        /*!< Pin 26 selected */
-#define GPIO_SEL_27             (BIT(27))                        /*!< Pin 27 selected */
-
-#define GPIO_SEL_32             ((uint64_t)(((uint64_t)1)<<32))  /*!< Pin 32 selected */
-#define GPIO_SEL_33             ((uint64_t)(((uint64_t)1)<<33))  /*!< Pin 33 selected */
-#define GPIO_SEL_34             ((uint64_t)(((uint64_t)1)<<34))  /*!< Pin 34 selected */
-#define GPIO_SEL_35             ((uint64_t)(((uint64_t)1)<<35))  /*!< Pin 35 selected */
-#define GPIO_SEL_36             ((uint64_t)(((uint64_t)1)<<36))  /*!< Pin 36 selected */
-#define GPIO_SEL_37             ((uint64_t)(((uint64_t)1)<<37))  /*!< Pin 37 selected */
-#define GPIO_SEL_38             ((uint64_t)(((uint64_t)1)<<38))  /*!< Pin 38 selected */
-#define GPIO_SEL_39             ((uint64_t)(((uint64_t)1)<<39))  /*!< Pin 39 selected */
-
-#define GPIO_PIN_REG_0          IO_MUX_GPIO0_REG
-#define GPIO_PIN_REG_1          IO_MUX_GPIO1_REG
-#define GPIO_PIN_REG_2          IO_MUX_GPIO2_REG
-#define GPIO_PIN_REG_3          IO_MUX_GPIO3_REG
-#define GPIO_PIN_REG_4          IO_MUX_GPIO4_REG
-#define GPIO_PIN_REG_5          IO_MUX_GPIO5_REG
-#define GPIO_PIN_REG_6          IO_MUX_GPIO6_REG
-#define GPIO_PIN_REG_7          IO_MUX_GPIO7_REG
-#define GPIO_PIN_REG_8          IO_MUX_GPIO8_REG
-#define GPIO_PIN_REG_9          IO_MUX_GPIO9_REG
-#define GPIO_PIN_REG_10         IO_MUX_GPIO10_REG
-#define GPIO_PIN_REG_11         IO_MUX_GPIO11_REG
-#define GPIO_PIN_REG_12         IO_MUX_GPIO12_REG
-#define GPIO_PIN_REG_13         IO_MUX_GPIO13_REG
-#define GPIO_PIN_REG_14         IO_MUX_GPIO14_REG
-#define GPIO_PIN_REG_15         IO_MUX_GPIO15_REG
-#define GPIO_PIN_REG_16         IO_MUX_GPIO16_REG
-#define GPIO_PIN_REG_17         IO_MUX_GPIO17_REG
-#define GPIO_PIN_REG_18         IO_MUX_GPIO18_REG
-#define GPIO_PIN_REG_19         IO_MUX_GPIO19_REG
-#define GPIO_PIN_REG_20         IO_MUX_GPIO20_REG
-#define GPIO_PIN_REG_21         IO_MUX_GPIO21_REG
-#define GPIO_PIN_REG_22         IO_MUX_GPIO22_REG
-#define GPIO_PIN_REG_23         IO_MUX_GPIO23_REG
-#define GPIO_PIN_REG_25         IO_MUX_GPIO25_REG
-#define GPIO_PIN_REG_26         IO_MUX_GPIO26_REG
-#define GPIO_PIN_REG_27         IO_MUX_GPIO27_REG
-#define GPIO_PIN_REG_32         IO_MUX_GPIO32_REG
-#define GPIO_PIN_REG_33         IO_MUX_GPIO33_REG
-#define GPIO_PIN_REG_34         IO_MUX_GPIO34_REG
-#define GPIO_PIN_REG_35         IO_MUX_GPIO35_REG
-#define GPIO_PIN_REG_36         IO_MUX_GPIO36_REG
-#define GPIO_PIN_REG_37         IO_MUX_GPIO37_REG
-#define GPIO_PIN_REG_38         IO_MUX_GPIO38_REG
-#define GPIO_PIN_REG_39         IO_MUX_GPIO39_REG
+// On ESP32 those PADs which have RTC functions must set pullup/down/capability via RTC register. 
+// On ESP32-S2, Digital IOs have their own registers to control pullup/down/capability, independent with RTC registers.
+#define GPIO_SUPPORTS_RTC_INDEPENDENT (0)
+// Force hold is a new function of ESP32-S2
+#define GPIO_SUPPORTS_FORCE_HOLD      (0)
 
 #define GPIO_APP_CPU_INTR_ENA      (BIT(0))
 #define GPIO_APP_CPU_NMI_INTR_ENA  (BIT(1))
@@ -115,58 +39,10 @@ extern "C" {
 #define GPIO_MODE_DEF_OUTPUT          (BIT1)
 #define GPIO_MODE_DEF_OD              (BIT2)
 
-/** @endcond */
-
 #define GPIO_IS_VALID_GPIO(gpio_num)              ((gpio_num < GPIO_PIN_COUNT && GPIO_PIN_MUX_REG[gpio_num] != 0))                                     /*!< Check whether it is a valid GPIO number */
 #define GPIO_IS_VALID_OUTPUT_GPIO(gpio_num)       ((GPIO_IS_VALID_GPIO(gpio_num)) && (gpio_num < 34))                                                  /*!< Check whether it can be a valid GPIO number of output mode */
 #define GPIO_MASK_CONTAIN_INPUT_GPIO(gpio_mask)   ((gpio_mask & (GPIO_SEL_34 | GPIO_SEL_35 | GPIO_SEL_36 | GPIO_SEL_37 | GPIO_SEL_38 | GPIO_SEL_39)))  /*!< Check whether it contains input io */
 
-#define GPIO_NUM_NC (-1)    /*!< Use to signal not connected to S/W */
-#define GPIO_NUM_0 (0)     /*!< GPIO0, input and output */
-#define GPIO_NUM_1 (1)     /*!< GPIO1, input and output */
-#define GPIO_NUM_2 (2)     /*!< GPIO2, input and output
-                             @note There are more enumerations like that
-                             up to GPIO39, excluding GPIO20, GPIO24 and GPIO28..31.
-                             They are not shown here to reduce redundant information.
-                             @note GPIO34..39 are input mode only. */
-    /** @cond */
-#define GPIO_NUM_3 (3)     /*!< GPIO3, input and output */
-#define GPIO_NUM_4 (4)     /*!< GPIO4, input and output */
-#define GPIO_NUM_5 (5)     /*!< GPIO5, input and output */
-#define GPIO_NUM_6 (6)     /*!< GPIO6, input and output */
-#define GPIO_NUM_7 (7)     /*!< GPIO7, input and output */
-#define GPIO_NUM_8 (8)     /*!< GPIO8, input and output */
-#define GPIO_NUM_9 (9)     /*!< GPIO9, input and output */
-#define GPIO_NUM_10 (10)   /*!< GPIO10, input and output */
-#define GPIO_NUM_11 (11)   /*!< GPIO11, input and output */
-#define GPIO_NUM_12 (12)   /*!< GPIO12, input and output */
-#define GPIO_NUM_13 (13)   /*!< GPIO13, input and output */
-#define GPIO_NUM_14 (14)   /*!< GPIO14, input and output */
-#define GPIO_NUM_15 (15)   /*!< GPIO15, input and output */
-#define GPIO_NUM_16 (16)   /*!< GPIO16, input and output */
-#define GPIO_NUM_17 (17)   /*!< GPIO17, input and output */
-#define GPIO_NUM_18 (18)   /*!< GPIO18, input and output */
-#define GPIO_NUM_19 (19)   /*!< GPIO19, input and output */
-
-#define GPIO_NUM_21 (21)   /*!< GPIO21, input and output */
-#define GPIO_NUM_22 (22)   /*!< GPIO22, input and output */
-#define GPIO_NUM_23 (23)   /*!< GPIO23, input and output */
-
-#define GPIO_NUM_25 (25)   /*!< GPIO25, input and output */
-#define GPIO_NUM_26 (26)   /*!< GPIO26, input and output */
-#define GPIO_NUM_27 (27)   /*!< GPIO27, input and output */
-
-#define GPIO_NUM_32 (32)   /*!< GPIO32, input and output */
-#define GPIO_NUM_33 (33)   /*!< GPIO33, input and output */
-#define GPIO_NUM_34 (34)   /*!< GPIO34, input mode only */
-#define GPIO_NUM_35 (35)   /*!< GPIO35, input mode only */
-#define GPIO_NUM_36 (36)   /*!< GPIO36, input mode only */
-#define GPIO_NUM_37 (37)   /*!< GPIO37, input mode only */
-#define GPIO_NUM_38 (38)   /*!< GPIO38, input mode only */
-#define GPIO_NUM_39 (39)   /*!< GPIO39, input mode only */
-#define GPIO_NUM_MAX (40)
-    /** @endcond */
-
 #ifdef __cplusplus
 }
 #endif

components/soc/esp32s2beta/include/hal/gpio_ll.h

@@ -404,6 +404,19 @@ static inline void gpio_ll_iomux_out(gpio_dev_t *hw, uint8_t gpio_num, int func,
     PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[gpio_num], func);
 }
 
+static inline void gpio_ll_force_hold_all(gpio_dev_t *hw)
+{
+    CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD);
+    SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_HOLD);
+}
+
+static inline void gpio_ll_force_unhold_all(gpio_dev_t *hw)
+{
+    CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_HOLD);
+    SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD);
+    SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_CLR_DG_PAD_AUTOHOLD);
+}
+
 #ifdef __cplusplus
 }
 #endif

components/soc/esp32s2beta/include/soc/gpio_caps.h

@@ -19,104 +19,14 @@ extern "C" {
 #endif
 
 // ESP32-S2 has 1 GPIO peripheral
-#define GPIO_PORT_0             (0) /*!< GPIO port 0 */
-#define GPIO_PORT_MAX           (1) /*!< GPIO port max */
-#define SOC_GPIO_PORT           (GPIO_PORT_MAX)
+#define SOC_GPIO_PORT           (1)
 #define GPIO_PIN_COUNT          (48)
 
-#define GPIO_SEL_0              (BIT(0))                         /*!< Pin 0 selected */
-#define GPIO_SEL_1              (BIT(1))                         /*!< Pin 1 selected */
-#define GPIO_SEL_2              (BIT(2))                         /*!< Pin 2 selected */
-#define GPIO_SEL_3              (BIT(3))                         /*!< Pin 3 selected */
-#define GPIO_SEL_4              (BIT(4))                         /*!< Pin 4 selected */
-#define GPIO_SEL_5              (BIT(5))                         /*!< Pin 5 selected */
-#define GPIO_SEL_6              (BIT(6))                         /*!< Pin 6 selected */
-#define GPIO_SEL_7              (BIT(7))                         /*!< Pin 7 selected */
-#define GPIO_SEL_8              (BIT(8))                         /*!< Pin 8 selected */
-#define GPIO_SEL_9              (BIT(9))                         /*!< Pin 9 selected */
-#define GPIO_SEL_10             (BIT(10))                        /*!< Pin 10 selected */
-#define GPIO_SEL_11             (BIT(11))                        /*!< Pin 11 selected */
-#define GPIO_SEL_12             (BIT(12))                        /*!< Pin 12 selected */
-#define GPIO_SEL_13             (BIT(13))                        /*!< Pin 13 selected */
-#define GPIO_SEL_14             (BIT(14))                        /*!< Pin 14 selected */
-#define GPIO_SEL_15             (BIT(15))                        /*!< Pin 15 selected */
-#define GPIO_SEL_16             (BIT(16))                        /*!< Pin 16 selected */
-#define GPIO_SEL_17             (BIT(17))                        /*!< Pin 17 selected */
-#define GPIO_SEL_18             (BIT(18))                        /*!< Pin 18 selected */
-#define GPIO_SEL_19             (BIT(19))                        /*!< Pin 19 selected */
-#define GPIO_SEL_20             (BIT(20))                        /*!< Pin 20 selected */
-#define GPIO_SEL_21             (BIT(21))                        /*!< Pin 21 selected */
-
-#define GPIO_SEL_26             (BIT(26))                        /*!< Pin 26 selected */
-#define GPIO_SEL_27             (BIT(27))                        /*!< Pin 27 selected */
-#define GPIO_SEL_28             (BIT(28))                        /*!< Pin 28 selected */
-#define GPIO_SEL_29             (BIT(29))                        /*!< Pin 29 selected */
-#define GPIO_SEL_30             (BIT(30))                        /*!< Pin 30 selected */
-#define GPIO_SEL_31             (BIT(31))                        /*!< Pin 31 selected */
-#define GPIO_SEL_32             ((uint64_t)(((uint64_t)1)<<32))  /*!< Pin 32 selected */
-#define GPIO_SEL_33             ((uint64_t)(((uint64_t)1)<<33))  /*!< Pin 33 selected */
-#define GPIO_SEL_34             ((uint64_t)(((uint64_t)1)<<34))  /*!< Pin 34 selected */
-#define GPIO_SEL_35             ((uint64_t)(((uint64_t)1)<<35))  /*!< Pin 35 selected */
-#define GPIO_SEL_36             ((uint64_t)(((uint64_t)1)<<36))  /*!< Pin 36 selected */
-#define GPIO_SEL_37             ((uint64_t)(((uint64_t)1)<<37))  /*!< Pin 37 selected */
-#define GPIO_SEL_38             ((uint64_t)(((uint64_t)1)<<38))  /*!< Pin 38 selected */
-#define GPIO_SEL_39             ((uint64_t)(((uint64_t)1)<<39))  /*!< Pin 39 selected */
-#define GPIO_SEL_40             ((uint64_t)(((uint64_t)1)<<40))  /*!< Pin 40 selected */
-#define GPIO_SEL_41             ((uint64_t)(((uint64_t)1)<<41))  /*!< Pin 41 selected */
-#define GPIO_SEL_42             ((uint64_t)(((uint64_t)1)<<42))  /*!< Pin 42 selected */
-#define GPIO_SEL_43             ((uint64_t)(((uint64_t)1)<<43))  /*!< Pin 43 selected */
-#define GPIO_SEL_44             ((uint64_t)(((uint64_t)1)<<44))  /*!< Pin 44 selected */
-#define GPIO_SEL_45             ((uint64_t)(((uint64_t)1)<<45))  /*!< Pin 45 selected */
-#define GPIO_SEL_46             ((uint64_t)(((uint64_t)1)<<46))  /*!< Pin 46 selected */
-
-#define GPIO_PIN_REG_0          IO_MUX_GPIO0_REG
-#define GPIO_PIN_REG_1          IO_MUX_GPIO1_REG
-#define GPIO_PIN_REG_2          IO_MUX_GPIO2_REG
-#define GPIO_PIN_REG_3          IO_MUX_GPIO3_REG
-#define GPIO_PIN_REG_4          IO_MUX_GPIO4_REG
-#define GPIO_PIN_REG_5          IO_MUX_GPIO5_REG
-#define GPIO_PIN_REG_6          IO_MUX_GPIO6_REG
-#define GPIO_PIN_REG_7          IO_MUX_GPIO7_REG
-#define GPIO_PIN_REG_8          IO_MUX_GPIO8_REG
-#define GPIO_PIN_REG_9          IO_MUX_GPIO9_REG
-#define GPIO_PIN_REG_10          IO_MUX_GPIO10_REG
-#define GPIO_PIN_REG_11          IO_MUX_GPIO11_REG
-#define GPIO_PIN_REG_12          IO_MUX_GPIO12_REG
-#define GPIO_PIN_REG_13          IO_MUX_GPIO13_REG
-#define GPIO_PIN_REG_14          IO_MUX_GPIO14_REG
-#define GPIO_PIN_REG_15          IO_MUX_GPIO15_REG
-#define GPIO_PIN_REG_16          IO_MUX_GPIO16_REG
-#define GPIO_PIN_REG_17          IO_MUX_GPIO17_REG
-#define GPIO_PIN_REG_18          IO_MUX_GPIO18_REG
-#define GPIO_PIN_REG_19          IO_MUX_GPIO19_REG
-#define GPIO_PIN_REG_20          IO_MUX_GPIO20_REG
-#define GPIO_PIN_REG_21          IO_MUX_GPIO21_REG
-#define GPIO_PIN_REG_22          IO_MUX_GPIO22_REG
-#define GPIO_PIN_REG_23          IO_MUX_GPIO23_REG
-#define GPIO_PIN_REG_24          IO_MUX_GPIO24_REG
-#define GPIO_PIN_REG_25          IO_MUX_GPIO25_REG
-#define GPIO_PIN_REG_26          IO_MUX_GPIO26_REG
-#define GPIO_PIN_REG_27          IO_MUX_GPIO27_REG
-#define GPIO_PIN_REG_28          IO_MUX_GPIO28_REG
-#define GPIO_PIN_REG_29          IO_MUX_GPIO29_REG
-#define GPIO_PIN_REG_30          IO_MUX_GPIO30_REG
-#define GPIO_PIN_REG_31          IO_MUX_GPIO31_REG
-#define GPIO_PIN_REG_32          IO_MUX_GPIO32_REG
-#define GPIO_PIN_REG_33          IO_MUX_GPIO33_REG
-#define GPIO_PIN_REG_34          IO_MUX_GPIO34_REG
-#define GPIO_PIN_REG_35          IO_MUX_GPIO35_REG
-#define GPIO_PIN_REG_36          IO_MUX_GPIO36_REG
-#define GPIO_PIN_REG_37          IO_MUX_GPIO37_REG
-#define GPIO_PIN_REG_38          IO_MUX_GPIO38_REG
-#define GPIO_PIN_REG_39          IO_MUX_GPIO39_REG
-#define GPIO_PIN_REG_40          IO_MUX_GPIO40_REG
-#define GPIO_PIN_REG_41          IO_MUX_GPIO41_REG
-#define GPIO_PIN_REG_42          IO_MUX_GPIO42_REG
-#define GPIO_PIN_REG_43          IO_MUX_GPIO43_REG
-#define GPIO_PIN_REG_44          IO_MUX_GPIO44_REG
-#define GPIO_PIN_REG_45          IO_MUX_GPIO45_REG
-#define GPIO_PIN_REG_46          IO_MUX_GPIO46_REG
-#define GPIO_PIN_REG_47          IO_MUX_GPIO47_REG
+// On ESP32 those PADs which have RTC functions must set pullup/down/capability via RTC register. 
+// On ESP32-S2, Digital IOs have their own registers to control pullup/down/capability, independent with RTC registers.
+#define GPIO_SUPPORTS_RTC_INDEPENDENT (1)
+// Force hold is a new function of ESP32-S2
+#define GPIO_SUPPORTS_FORCE_HOLD      (1)
 
 #define GPIO_PRO_CPU_INTR_ENA      (BIT(0))
 #define GPIO_PRO_CPU_NMI_INTR_ENA  (BIT(1))
@@ -126,64 +36,10 @@ extern "C" {
 #define GPIO_MODE_DEF_OUTPUT          (BIT1)
 #define GPIO_MODE_DEF_OD              (BIT2)
 
-
 #define GPIO_IS_VALID_GPIO(gpio_num)             ((gpio_num < GPIO_PIN_COUNT && GPIO_PIN_MUX_REG[gpio_num] != 0)) /*!< Check whether it is a valid GPIO number */
 #define GPIO_IS_VALID_OUTPUT_GPIO(gpio_num)      ((GPIO_IS_VALID_GPIO(gpio_num)) && (gpio_num < 46))              /*!< Check whether it can be a valid GPIO number of output mode */
 #define GPIO_MASK_CONTAIN_INPUT_GPIO(gpio_mask)  ((gpio_mask & (GPIO_SEL_46)))                                    /*!< Check whether it contains input io */
 
-#define GPIO_NUM_NC (-1)    /*!< Use to signal not connected to S/W */
-#define GPIO_NUM_0 (0)     /*!< GPIO0, input and output */
-#define GPIO_NUM_1 (1)     /*!< GPIO1, input and output */
-#define GPIO_NUM_2 (2)     /*!< GPIO2, input and output
-                             @note There are more enumerations like that
-                             up to GPIO39, excluding GPIO20, GPIO24 and GPIO28..31.
-                             They are not shown here to reduce redundant information.
-                             @note GPIO34..39 are input mode only. */
-    /** @cond */
-#define GPIO_NUM_3 (3)     /*!< GPIO3, input and output */
-#define GPIO_NUM_4 (4)     /*!< GPIO4, input and output */
-#define GPIO_NUM_5 (5)     /*!< GPIO5, input and output */
-#define GPIO_NUM_6 (6)     /*!< GPIO6, input and output */
-#define GPIO_NUM_7 (7)     /*!< GPIO7, input and output */
-#define GPIO_NUM_8 (8)     /*!< GPIO8, input and output */
-#define GPIO_NUM_9 (9)     /*!< GPIO9, input and output */
-#define GPIO_NUM_10 (10)   /*!< GPIO10, input and output */
-#define GPIO_NUM_11 (11)   /*!< GPIO11, input and output */
-#define GPIO_NUM_12 (12)   /*!< GPIO12, input and output */
-#define GPIO_NUM_13 (13)   /*!< GPIO13, input and output */
-#define GPIO_NUM_14 (14)   /*!< GPIO14, input and output */
-#define GPIO_NUM_15 (15)   /*!< GPIO15, input and output */
-#define GPIO_NUM_16 (16)   /*!< GPIO16, input and output */
-#define GPIO_NUM_17 (17)   /*!< GPIO17, input and output */
-#define GPIO_NUM_18 (18)   /*!< GPIO18, input and output */
-#define GPIO_NUM_19 (19)   /*!< GPIO19, input and output */
-
-#define GPIO_NUM_21 (21)   /*!< GPIO21, input and output */
-#define GPIO_NUM_22 (22)   /*!< GPIO22, input and output */
-#define GPIO_NUM_23 (23)   /*!< GPIO23, input and output */
-
-#define GPIO_NUM_25 (25)   /*!< GPIO25, input and output */
-#define GPIO_NUM_26 (26)   /*!< GPIO26, input and output */
-#define GPIO_NUM_27 (27)   /*!< GPIO27, input and output */
-
-#define GPIO_NUM_32 (32)   /*!< GPIO32, input and output */
-#define GPIO_NUM_33 (33)   /*!< GPIO33, input and output */
-#define GPIO_NUM_34 (34)   /*!< GPIO34, input mode only */
-#define GPIO_NUM_35 (35)   /*!< GPIO35, input mode only */
-#define GPIO_NUM_36 (36)   /*!< GPIO36, input mode only */
-#define GPIO_NUM_37 (37)   /*!< GPIO37, input mode only */
-#define GPIO_NUM_38 (38)   /*!< GPIO38, input mode only */
-#define GPIO_NUM_39 (39)   /*!< GPIO39, input mode only */
-#define GPIO_NUM_40 (40)   /*!< GPIO40, input and output */
-#define GPIO_NUM_41 (41)   /*!< GPIO41, input and output */
-#define GPIO_NUM_42 (42)   /*!< GPIO42, input and output */
-#define GPIO_NUM_43 (43)   /*!< GPIO43, input and output */
-#define GPIO_NUM_44 (44)   /*!< GPIO44, input and output */
-#define GPIO_NUM_45 (45)   /*!< GPIO45, input and output */
-#define GPIO_NUM_46 (46)   /*!< GPIO46, input mode only */
-#define GPIO_NUM_MAX (47)
-    /** @endcond */
-
 #ifdef __cplusplus
 }
 #endif

components/soc/include/hal/gpio_hal.h

@@ -319,6 +319,24 @@ void gpio_hal_intr_disable(gpio_hal_context_t *hal, gpio_num_t gpio_num);
   */
 #define gpio_hal_iomux_out(hal, gpio_num, func, oen_inv) gpio_ll_iomux_out((hal)->dev, gpio_num, func, oen_inv)
 
+#if GPIO_SUPPORTS_FORCE_HOLD
+/**
+  * @brief Force hold digital and rtc gpio pad. 
+  * @note GPIO force hold, whether the chip in sleep mode or wakeup mode. 
+  * 
+  * @param hal Context of the HAL layer
+  * */
+#define gpio_hal_force_hold_all(hal) gpio_ll_force_hold_all((hal)->dev)
+
+/**
+  * @brief Force unhold digital and rtc gpio pad. 
+  * @note GPIO force unhold, whether the chip in sleep mode or wakeup mode. 
+  * 
+  * @param hal Context of the HAL layer
+  * */
+#define gpio_hal_force_unhold_all(hal) gpio_ll_force_unhold_all((hal)->dev)
+#endif
+
 #ifdef __cplusplus
 }
 #endif

components/soc/include/hal/gpio_types.h

@@ -21,7 +21,172 @@
 extern "C" {
 #endif
 
-typedef int gpio_num_t;
+typedef enum {
+    GPIO_PORT_0 = 0,
+    GPIO_PORT_MAX,
+} gpio_port_t;
+
+#define GPIO_SEL_0              (BIT(0))                         /*!< Pin 0 selected */
+#define GPIO_SEL_1              (BIT(1))                         /*!< Pin 1 selected */
+#define GPIO_SEL_2              (BIT(2))                         /*!< Pin 2 selected */
+#define GPIO_SEL_3              (BIT(3))                         /*!< Pin 3 selected */
+#define GPIO_SEL_4              (BIT(4))                         /*!< Pin 4 selected */
+#define GPIO_SEL_5              (BIT(5))                         /*!< Pin 5 selected */
+#define GPIO_SEL_6              (BIT(6))                         /*!< Pin 6 selected */
+#define GPIO_SEL_7              (BIT(7))                         /*!< Pin 7 selected */
+#define GPIO_SEL_8              (BIT(8))                         /*!< Pin 8 selected */
+#define GPIO_SEL_9              (BIT(9))                         /*!< Pin 9 selected */
+#define GPIO_SEL_10             (BIT(10))                        /*!< Pin 10 selected */
+#define GPIO_SEL_11             (BIT(11))                        /*!< Pin 11 selected */
+#define GPIO_SEL_12             (BIT(12))                        /*!< Pin 12 selected */
+#define GPIO_SEL_13             (BIT(13))                        /*!< Pin 13 selected */
+#define GPIO_SEL_14             (BIT(14))                        /*!< Pin 14 selected */
+#define GPIO_SEL_15             (BIT(15))                        /*!< Pin 15 selected */
+#define GPIO_SEL_16             (BIT(16))                        /*!< Pin 16 selected */
+#define GPIO_SEL_17             (BIT(17))                        /*!< Pin 17 selected */
+#define GPIO_SEL_18             (BIT(18))                        /*!< Pin 18 selected */
+#define GPIO_SEL_19             (BIT(19))                        /*!< Pin 19 selected */
+#define GPIO_SEL_20             (BIT(20))                        /*!< Pin 20 selected */
+#define GPIO_SEL_21             (BIT(21))                        /*!< Pin 21 selected */
+#if CONFIG_IDF_TARGET_ESP32
+#define GPIO_SEL_22             (BIT(22))                        /*!< Pin 22 selected */
+#define GPIO_SEL_23             (BIT(23))                        /*!< Pin 23 selected */
+
+#define GPIO_SEL_25             (BIT(25))                        /*!< Pin 25 selected */
+#endif
+#define GPIO_SEL_26             (BIT(26))                        /*!< Pin 26 selected */
+#define GPIO_SEL_27             (BIT(27))                        /*!< Pin 27 selected */
+#define GPIO_SEL_28             (BIT(28))                        /*!< Pin 28 selected */
+#define GPIO_SEL_29             (BIT(29))                        /*!< Pin 29 selected */
+#define GPIO_SEL_30             (BIT(30))                        /*!< Pin 30 selected */
+#define GPIO_SEL_31             (BIT(31))                        /*!< Pin 31 selected */
+#define GPIO_SEL_32             ((uint64_t)(((uint64_t)1)<<32))  /*!< Pin 32 selected */
+#define GPIO_SEL_33             ((uint64_t)(((uint64_t)1)<<33))  /*!< Pin 33 selected */
+#define GPIO_SEL_34             ((uint64_t)(((uint64_t)1)<<34))  /*!< Pin 34 selected */
+#define GPIO_SEL_35             ((uint64_t)(((uint64_t)1)<<35))  /*!< Pin 35 selected */
+#define GPIO_SEL_36             ((uint64_t)(((uint64_t)1)<<36))  /*!< Pin 36 selected */
+#define GPIO_SEL_37             ((uint64_t)(((uint64_t)1)<<37))  /*!< Pin 37 selected */
+#define GPIO_SEL_38             ((uint64_t)(((uint64_t)1)<<38))  /*!< Pin 38 selected */
+#define GPIO_SEL_39             ((uint64_t)(((uint64_t)1)<<39))  /*!< Pin 39 selected */
+#if GPIO_PIN_COUNT > 40
+#define GPIO_SEL_40             ((uint64_t)(((uint64_t)1)<<40))  /*!< Pin 40 selected */
+#define GPIO_SEL_41             ((uint64_t)(((uint64_t)1)<<41))  /*!< Pin 41 selected */
+#define GPIO_SEL_42             ((uint64_t)(((uint64_t)1)<<42))  /*!< Pin 42 selected */
+#define GPIO_SEL_43             ((uint64_t)(((uint64_t)1)<<43))  /*!< Pin 43 selected */
+#define GPIO_SEL_44             ((uint64_t)(((uint64_t)1)<<44))  /*!< Pin 44 selected */
+#define GPIO_SEL_45             ((uint64_t)(((uint64_t)1)<<45))  /*!< Pin 45 selected */
+#define GPIO_SEL_46             ((uint64_t)(((uint64_t)1)<<46))  /*!< Pin 46 selected */
+#endif
+
+#define GPIO_PIN_REG_0          IO_MUX_GPIO0_REG
+#define GPIO_PIN_REG_1          IO_MUX_GPIO1_REG
+#define GPIO_PIN_REG_2          IO_MUX_GPIO2_REG
+#define GPIO_PIN_REG_3          IO_MUX_GPIO3_REG
+#define GPIO_PIN_REG_4          IO_MUX_GPIO4_REG
+#define GPIO_PIN_REG_5          IO_MUX_GPIO5_REG
+#define GPIO_PIN_REG_6          IO_MUX_GPIO6_REG
+#define GPIO_PIN_REG_7          IO_MUX_GPIO7_REG
+#define GPIO_PIN_REG_8          IO_MUX_GPIO8_REG
+#define GPIO_PIN_REG_9          IO_MUX_GPIO9_REG
+#define GPIO_PIN_REG_10          IO_MUX_GPIO10_REG
+#define GPIO_PIN_REG_11          IO_MUX_GPIO11_REG
+#define GPIO_PIN_REG_12          IO_MUX_GPIO12_REG
+#define GPIO_PIN_REG_13          IO_MUX_GPIO13_REG
+#define GPIO_PIN_REG_14          IO_MUX_GPIO14_REG
+#define GPIO_PIN_REG_15          IO_MUX_GPIO15_REG
+#define GPIO_PIN_REG_16          IO_MUX_GPIO16_REG
+#define GPIO_PIN_REG_17          IO_MUX_GPIO17_REG
+#define GPIO_PIN_REG_18          IO_MUX_GPIO18_REG
+#define GPIO_PIN_REG_19          IO_MUX_GPIO19_REG
+#define GPIO_PIN_REG_20          IO_MUX_GPIO20_REG
+#define GPIO_PIN_REG_21          IO_MUX_GPIO21_REG
+#define GPIO_PIN_REG_22          IO_MUX_GPIO22_REG
+#define GPIO_PIN_REG_23          IO_MUX_GPIO23_REG
+#define GPIO_PIN_REG_24          IO_MUX_GPIO24_REG
+#define GPIO_PIN_REG_25          IO_MUX_GPIO25_REG
+#define GPIO_PIN_REG_26          IO_MUX_GPIO26_REG
+#define GPIO_PIN_REG_27          IO_MUX_GPIO27_REG
+#if CONFIG_IDF_TARGET_ESP32S2BETA
+#define GPIO_PIN_REG_28          IO_MUX_GPIO28_REG
+#define GPIO_PIN_REG_29          IO_MUX_GPIO29_REG
+#define GPIO_PIN_REG_30          IO_MUX_GPIO30_REG
+#define GPIO_PIN_REG_31          IO_MUX_GPIO31_REG
+#endif
+#define GPIO_PIN_REG_32          IO_MUX_GPIO32_REG
+#define GPIO_PIN_REG_33          IO_MUX_GPIO33_REG
+#define GPIO_PIN_REG_34          IO_MUX_GPIO34_REG
+#define GPIO_PIN_REG_35          IO_MUX_GPIO35_REG
+#define GPIO_PIN_REG_36          IO_MUX_GPIO36_REG
+#define GPIO_PIN_REG_37          IO_MUX_GPIO37_REG
+#define GPIO_PIN_REG_38          IO_MUX_GPIO38_REG
+#define GPIO_PIN_REG_39          IO_MUX_GPIO39_REG
+#if GPIO_PIN_COUNT > 40
+#define GPIO_PIN_REG_40          IO_MUX_GPIO40_REG
+#define GPIO_PIN_REG_41          IO_MUX_GPIO41_REG
+#define GPIO_PIN_REG_42          IO_MUX_GPIO42_REG
+#define GPIO_PIN_REG_43          IO_MUX_GPIO43_REG
+#define GPIO_PIN_REG_44          IO_MUX_GPIO44_REG
+#define GPIO_PIN_REG_45          IO_MUX_GPIO45_REG
+#define GPIO_PIN_REG_46          IO_MUX_GPIO46_REG
+#endif
+
+typedef enum {
+    GPIO_NUM_NC = -1,    /*!< Use to signal not connected to S/W */
+    GPIO_NUM_0 = 0,     /*!< GPIO0, input and output */
+    GPIO_NUM_1 = 1,     /*!< GPIO1, input and output */
+    GPIO_NUM_2 = 2,     /*!< GPIO2, input and output */
+    GPIO_NUM_3 = 3,     /*!< GPIO3, input and output */
+    GPIO_NUM_4 = 4,     /*!< GPIO4, input and output */
+    GPIO_NUM_5 = 5,     /*!< GPIO5, input and output */
+    GPIO_NUM_6 = 6,     /*!< GPIO6, input and output */
+    GPIO_NUM_7 = 7,     /*!< GPIO7, input and output */
+    GPIO_NUM_8 = 8,     /*!< GPIO8, input and output */
+    GPIO_NUM_9 = 9,     /*!< GPIO9, input and output */
+    GPIO_NUM_10 = 10,   /*!< GPIO10, input and output */
+    GPIO_NUM_11 = 11,   /*!< GPIO11, input and output */
+    GPIO_NUM_12 = 12,   /*!< GPIO12, input and output */
+    GPIO_NUM_13 = 13,   /*!< GPIO13, input and output */
+    GPIO_NUM_14 = 14,   /*!< GPIO14, input and output */
+    GPIO_NUM_15 = 15,   /*!< GPIO15, input and output */
+    GPIO_NUM_16 = 16,   /*!< GPIO16, input and output */
+    GPIO_NUM_17 = 17,   /*!< GPIO17, input and output */
+    GPIO_NUM_18 = 18,   /*!< GPIO18, input and output */
+    GPIO_NUM_19 = 19,   /*!< GPIO19, input and output */
+    GPIO_NUM_20 = 20,   /*!< GPIO20, input and output */
+    GPIO_NUM_21 = 21,   /*!< GPIO21, input and output */
+#if CONFIG_IDF_TARGET_ESP32
+    GPIO_NUM_22 = 22,   /*!< GPIO22, input and output */
+    GPIO_NUM_23 = 23,   /*!< GPIO23, input and output */
+
+    GPIO_NUM_25 = 25,   /*!< GPIO25, input and output */
+#endif
+    /* Note: The missing IO is because it is used inside the chip. */
+    GPIO_NUM_26 = 26,   /*!< GPIO26, input and output */
+    GPIO_NUM_27 = 27,   /*!< GPIO27, input and output */
+    GPIO_NUM_28 = 28,   /*!< GPIO28, input and output */
+    GPIO_NUM_29 = 29,   /*!< GPIO29, input and output */
+    GPIO_NUM_30 = 30,   /*!< GPIO30, input and output */
+    GPIO_NUM_31 = 31,   /*!< GPIO31, input and output */
+    GPIO_NUM_32 = 32,   /*!< GPIO32, input and output */
+    GPIO_NUM_33 = 33,   /*!< GPIO33, input and output */
+    GPIO_NUM_34 = 34,   /*!< GPIO34, input mode only(ESP32) / input and output(ESP32-S2) */
+    GPIO_NUM_35 = 35,   /*!< GPIO35, input mode only(ESP32) / input and output(ESP32-S2) */
+    GPIO_NUM_36 = 36,   /*!< GPIO36, input mode only(ESP32) / input and output(ESP32-S2) */
+    GPIO_NUM_37 = 37,   /*!< GPIO37, input mode only(ESP32) / input and output(ESP32-S2) */
+    GPIO_NUM_38 = 38,   /*!< GPIO38, input mode only(ESP32) / input and output(ESP32-S2) */
+    GPIO_NUM_39 = 39,   /*!< GPIO39, input mode only(ESP32) / input and output(ESP32-S2) */
+#if GPIO_PIN_COUNT > 40
+    GPIO_NUM_40 = 40,   /*!< GPIO40, input and output */
+    GPIO_NUM_41 = 41,   /*!< GPIO41, input and output */
+    GPIO_NUM_42 = 42,   /*!< GPIO42, input and output */
+    GPIO_NUM_43 = 43,   /*!< GPIO43, input and output */
+    GPIO_NUM_44 = 44,   /*!< GPIO44, input and output */
+    GPIO_NUM_45 = 45,   /*!< GPIO45, input and output */
+    GPIO_NUM_46 = 46,   /*!< GPIO46, input mode only */
+#endif
+    GPIO_NUM_MAX,
+/** @endcond */
+} gpio_num_t;
 
 typedef enum {
     GPIO_INTR_DISABLE = 0,     /*!< Disable GPIO interrupt                             */