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@@ -36,7 +36,11 @@ Offset should be in hex format. To reset to the default behaviour you can specif
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Since GDB requests memory map from OpenOCD only once when connecting to it, this command should be specified in one of the TCL configuration files, or passed to OpenOCD via its command line. In the latter case command line should look like below:
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- ``openocd -f board/esp32-wrover-kit-3.3v.cfg.cfg -c "init; halt; esp32 appimage_offset 0x210000"``
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+ .. highlight:: bash
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+
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+ .. include:: {IDF_TARGET_TOOLCHAIN_NAME}.inc
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+ :start-after: run-openocd-appimage-offset
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+ :end-before: ---
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Another option is to execute that command via OpenOCD telnet session and then connect GDB, but it seems to be less handy.
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@@ -79,9 +83,9 @@ OpenOCD has explicit support for the ESP-IDF FreeRTOS. GDB can see FreeRTOS task
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The MTDI pin of ESP32, being among four pins used for JTAG communication, is also one of ESP32's bootstrapping pins. On power up ESP32 is sampling binary level on MTDI to set it's internal voltage regulator used to supply power to external SPI flash chip. If binary level on MDTI pin on power up is low, the voltage regulator is set to deliver 3.3 V, if it is high, then the voltage is set to 1.8 V. The MTDI pin should have a pull-up or may rely on internal weak pull down resistor (see `ESP32 Series Datasheet <https://www.espressif.com/sites/default/files/documentation/esp32_datasheet_en.pdf>`_ for details), depending on the type of SPI chip used. Once JTAG is connected, it overrides the pull-up or pull-down resistor that is supposed to do the bootstrapping.
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- To handle this issue OpenOCD's board configuration file (e.g. ``boards\esp-wroom-32.cfg`` for ESP32-WROOM-32 module) provides ``ESP32_FLASH_VOLTAGE`` parameter to set the idle state of the ``TDO`` line to a specified binary level, therefore reducing the chance of a bad bootup of application due to incorrect flash voltage.
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+ To handle this issue OpenOCD's board configuration file (e.g. ``board\esp32-wrover-kit-3.3v.cfg`` for ESP-WROVER-KIT board) provides ``ESP32_FLASH_VOLTAGE`` parameter to set the idle state of the ``TDO`` line to a specified binary level, therefore reducing the chance of a bad bootup of application due to incorrect flash voltage.
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- Check specification of ESP32 module connected to JTAG, what is the power supply voltage of SPI flash chip. Then set ``ESP32_FLASH_VOLTAGE`` accordingly. Most WROOM modules use 3.3 V flash, while WROVER modules use 1.8 V flash.
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+ Check specification of ESP32 module connected to JTAG, what is the power supply voltage of SPI flash chip. Then set ``ESP32_FLASH_VOLTAGE`` accordingly. Most WROOM modules use 3.3 V flash. WROVER earlier than ESP32-WROVER-B use 1.8 V flash, while ESP32-WROVER-B and -E modules use 3.3 V flash.
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.. _jtag-debugging-tip-optimize-jtag-speed:
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@@ -120,88 +124,65 @@ On startup, debugger is issuing sequence of commands to reset the chip and halt
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Configuration of OpenOCD for specific target
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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-OpenOCD needs to be told what JTAG adapter to use and processor the JTAG adapter is connected to. To do so, use existing **board** configuration files located in OpenOCD's ``share/openocd/scripts/board`` folder.
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-
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-For example, if you connect to ESP-WROVER-KIT with ESP-WROOM-32 module installed, use the following configuration files:
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-
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-* ``board/esp32-wrover-kit-3.3v.cfg``
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-
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-Optionally prepare configuration by yourself. To do so, you can check existing files and modify them to match you specific hardware. Below is the summary of available configuration parameters for **board** configuration.
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+There are several kinds of OpenOCD configuration files (``*.cfg``). All configuration files are located in subdirectories of ``share/openocd/scripts`` directory of OpenOCD distribution (or ``tcl/scripts`` directory of the source repository). For the purposes of this guide, the most important ones are ``board``, ``interface`` and ``target``.
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+* ``interface`` configuration files describe the JTAG adapter. Examples of JTAG adapters are ESP-Prog and J-Link.
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+* ``target`` configuration files describe specific chips, or in some cases, modules.
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+* ``board`` configuration files are provided for development boards with a built-in JTAG adapter. Such files include an ``interface`` configuration file to choose the adapter, and ``target`` configuration file to choose the chip/module.
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-.. highlight:: none
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-
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-Adapter's clock speed
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-""""""""""""""""""""""
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+The following configuration files are available for {IDF_TARGET_NAME}:
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-::
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+.. include:: {IDF_TARGET_TOOLCHAIN_NAME}.inc
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+ :start-after: openocd-cfg-files
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+ :end-before: ---
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- adapter_khz 20000
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-See :ref:`jtag-debugging-tip-optimize-jtag-speed` for guidance how to set this value.
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-
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-.. only:: esp32
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+If you are using one of the boards which have a pre-defined configuration file, you only need to pass one ``-f`` argument to OpenOCD, specifying that file.
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- Single core debugging
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- """""""""""""""""""""
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+If you are using a board not listed here, you need to specify both the interface configuration file and target configuration file.
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- ::
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+Custom configuration files
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+""""""""""""""""""""""""""
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- set ESP32_ONLYCPU 1
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+OpenOCD configuration files are written in TCL, and include a variety of choices for customization and scripting. This can be useful for non-standard debugging situations. Please refer to `OpenOCD Manual`_ for the TCL scripting reference.
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- Comment out this line for dual core debugging.
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-
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-
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-Disable RTOS support
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-""""""""""""""""""""
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-
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-::
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-
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- set ESP32_RTOS none
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-
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-Comment out this line to have RTOS support.
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-
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-.. only:: esp32
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+.. _jtag-debugging-tip-openocd-config-vars:
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- Power supply voltage of ESP32's SPI flash chip
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- """"""""""""""""""""""""""""""""""""""""""""""
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+OpenOCD configuration variables
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+"""""""""""""""""""""""""""""""
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- ::
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+The following variables can be optionally set before including the ESP-specific target configuration file. This can be done either in a custom configuration file, or from the command line.
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- set ESP32_FLASH_VOLTAGE 1.8
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+The syntax for setting a variable in TCL is:
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- Comment out this line to set 3.3 V, ref: :ref:`jtag-debugging-tip-code-flash-voltage`
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+.. code-block:: tcl
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+ set VARIABLE_NAME value
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- Configuration file for ESP32 targets
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- """"""""""""""""""""""""""""""""""""
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+To set a variable from the command line (replace the name of .cfg file with the correct file for your board):
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- ::
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+.. code-block:: bash
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- source [find target/esp32.cfg]
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+ openocd -c 'set VARIABLE_NAME value' -f board/esp-xxxxx-kit.cfg
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- .. note::
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+It is important to set the variable before including the ESP-specific configuration file, otherwise the variable will not have effect. You can set multiple variables by repeating the ``-c`` option.
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- Do not change ``source [find target/esp32.cfg]`` line unless you are familiar with OpenOCD internals.
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+.. list-table:: Common ESP-related OpenOCD variables
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+ :widths: 25 75
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+ :header-rows: 1
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- Currently ``target/esp32.cfg`` remains the only configuration file for ESP32 targets (esp108 and esp32). The matrix of supported configurations is as follows:
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-
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- +---------------+---------------+---------------+
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- | Dual/single | RTOS | Target used |
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- +===============+===============+===============+
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- | dual | FreeRTOS | esp32 |
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- +---------------+---------------+---------------+
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- | single | FreeRTOS | esp108 (*) |
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- +---------------+---------------+---------------+
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- | dual | none | esp108 |
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- +---------------+---------------+---------------+
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- | single | none | esp108 |
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- +---------------+---------------+---------------+
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-
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- (*) — we plan to fix this and add support for single core debugging with esp32 target in a subsequent commits.
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-
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- Look inside ``board/esp-wroom-32.cfg`` for additional information provided in comments besides each configuration parameter.
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+ * - Variable
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+ - Description
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+ * - ``ESP_RTOS``
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+ - Set to ``none`` to disable RTOS support. In this case, thread list will not be available in GDB. Can be useful when debugging FreeRTOS itself, and stepping through the scheduler code.
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+ * - ``ESP_FLASH_SIZE``
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+ - Set to ``0`` to disable Flash breakpoints support.
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+ * - ``ESP_SEMIHOST_BASEDIR``
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+ - Set to the path (on the host) which will be the default directory for semihosting functions.
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+.. include:: {IDF_TARGET_TOOLCHAIN_NAME}.inc
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+ :start-after: openocd-target-specific-config-vars
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+ :end-before: ---
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.. _jtag-debugging-tip-reset-by-debugger:
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@@ -218,39 +199,15 @@ Do not use JTAG pins for something else
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Operation of JTAG may be disturbed, if some other h/w is connected to JTAG pins besides {IDF_TARGET_NAME} module and JTAG adapter. {IDF_TARGET_NAME} JTAG us using the following pins:
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-.. only:: esp32
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-
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- +---+-----------------------+-------------+
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- | | ESP32 Pin | JTAG Signal |
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- +===+=======================+=============+
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- | 1 | MTDO / GPIO15 | TDO |
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- +---+-----------------------+-------------+
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- | 2 | MTDI / GPIO12 | TDI |
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- +---+-----------------------+-------------+
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- | 3 | MTCK / GPIO13 | TCK |
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- +---+-----------------------+-------------+
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- | 4 | MTMS / GPIO14 | TMS |
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- +---+-----------------------+-------------+
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-
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-.. only:: esp32s2
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-
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- +---+-----------------------+-------------+
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- | | ESP32-S2 Pin | JTAG Signal |
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- +===+=======================+=============+
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- | 1 | MTDO / GPIO40 | TDO |
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- +---+-----------------------+-------------+
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- | 2 | MTDI / GPIO41 | TDI |
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- +---+-----------------------+-------------+
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- | 3 | MTCK / GPIO39 | TCK |
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- +---+-----------------------+-------------+
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- | 4 | MTMS / GPIO42 | TMS |
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- +---+-----------------------+-------------+
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+.. include:: {IDF_TARGET_TOOLCHAIN_NAME}.inc
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+ :start-after: jtag-pins
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+ :end-before: ---
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JTAG communication will likely fail, if configuration of JTAG pins is changed by user application. If OpenOCD initializes correctly (detects the two Tensilica cores), but loses sync and spews out a lot of DTR/DIR errors when the program is ran, it is likely that the application reconfigures the JTAG pins to something else, or the user forgot to connect Vtar to a JTAG adapter that needed it.
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.. highlight:: none
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-Below is an excerpt from series of errors reported by GDB after the application stepped into the code that reconfigured MTDO / GPIO15 to be an input::
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+Below is an excerpt from series of errors reported by GDB after the application stepped into the code that reconfigured MTDO pin to be an input::
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cpu0: xtensa_resume (line 431): DSR (FFFFFFFF) indicates target still busy!
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cpu0: xtensa_resume (line 431): DSR (FFFFFFFF) indicates DIR instruction generated an exception!
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@@ -273,9 +230,7 @@ However, OpenOCD may attempt to automatically read and write the flash in order
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- Software breakpoints are incompatible with Flash Encryption, OpenOCD currently has no support for encrypting or decrypting flash contents.
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- If Secure Boot is enabled, setting a software breakpoint will change the digest of a signed app and make the signature invalid. This means if a software breakpoint is set and then a reset occurs, the signature verification will fail on boot.
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-To disable software breakpoints while using JTAG, add an extra argument ``-c 'set ESP_FLASH_SIZE 0'`` to the start of the OpenOCD command line. For example::
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-
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- openocd -c 'set ESP_FLASH_SIZE 0' -f board/esp32-wrover-kit-3.3v.cfg
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+To disable software breakpoints while using JTAG, add an extra argument ``-c 'set ESP_FLASH_SIZE 0'`` to the start of the OpenOCD command line, see :ref:`jtag-debugging-tip-openocd-config-vars`.
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.. note::
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@@ -312,23 +267,26 @@ In case you encounter a problem with OpenOCD or GDB programs itself and do not f
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OpenOCD:
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- ::
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-
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- openocd -l openocd_log.txt -d3 -f board/esp32-wrover-kit-3.3v.cfg
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-
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- Logging to a file this way will prevent information displayed on the terminal. This may be a good thing taken amount of information provided, when increased debug level ``-d3`` is set. If you still like to see the log on the screen, then use another command instead:
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+ .. include:: {IDF_TARGET_TOOLCHAIN_NAME}.inc
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+ :start-after: run-openocd-d3
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+ :end-before: ---
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- ::
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+ Logging to a file this way will prevent information displayed on the terminal. This may be a good thing taken amount of information provided, when increased debug level ``-d3`` is set. If you still like to see the log on the screen, then use another command instead:
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- openocd -d3 -f board/esp32-wrover-kit-3.3v.cfg 2>&1 | tee openocd.log
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+ .. include:: {IDF_TARGET_TOOLCHAIN_NAME}.inc
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+ :start-after: run-openocd-d3-tee
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+ :end-before: ---
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Debugger:
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- ::
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+ .. include:: {IDF_TARGET_TOOLCHAIN_NAME}.inc
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+ :start-after: run-gdb-remotelog
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+ :end-before: ---
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- xtensa-esp32-elf-gdb -ex "set remotelogfile gdb_log.txt" <all other options>
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-
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- Optionally add command ``remotelogfile gdb_log.txt`` to the ``gdbinit`` file.
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+ Optionally add command ``remotelogfile gdb_log.txt`` to the ``gdbinit`` file.
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4. Attach both ``openocd_log.txt`` and ``gdb_log.txt`` files to your issue report.
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+
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+
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+.. _OpenOCD Manual: http://openocd.org/doc/html/index.html
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