fix(uart): Fixed C++ type conversion compile error in uart_ll_get_sclk

Closes https://github.com/espressif/esp-idf/issues/11813

components/hal/esp32/include/hal/uart_ll.h

@@ -92,10 +92,10 @@ FORCE_INLINE_ATTR void uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *source
     switch (hw->conf0.tick_ref_always_on) {
         default:
         case 0:
-            *source_clk = UART_SCLK_REF_TICK;
+            *source_clk = (soc_module_clk_t)UART_SCLK_REF_TICK;
             break;
         case 1:
-            *source_clk = UART_SCLK_APB;
+            *source_clk = (soc_module_clk_t)UART_SCLK_APB;
             break;
     }
 }

components/hal/esp32c2/include/hal/uart_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -135,13 +135,13 @@ FORCE_INLINE_ATTR void uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *source
     switch (hw->clk_conf.sclk_sel) {
         default:
         case 1:
-            *source_clk = UART_SCLK_PLL_F40M;
+            *source_clk = (soc_module_clk_t)UART_SCLK_PLL_F40M;
             break;
         case 2:
-            *source_clk = UART_SCLK_RTC;
+            *source_clk = (soc_module_clk_t)UART_SCLK_RTC;
             break;
         case 3:
-            *source_clk = UART_SCLK_XTAL;
+            *source_clk = (soc_module_clk_t)UART_SCLK_XTAL;
             break;
     }
 }

components/hal/esp32c3/include/hal/uart_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -137,13 +137,13 @@ FORCE_INLINE_ATTR void uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *source
     switch (hw->clk_conf.sclk_sel) {
         default:
         case 1:
-            *source_clk = UART_SCLK_APB;
+            *source_clk = (soc_module_clk_t)UART_SCLK_APB;
             break;
         case 2:
-            *source_clk = UART_SCLK_RTC;
+            *source_clk = (soc_module_clk_t)UART_SCLK_RTC;
             break;
         case 3:
-            *source_clk = UART_SCLK_XTAL;
+            *source_clk = (soc_module_clk_t)UART_SCLK_XTAL;
             break;
     }
 }

components/hal/esp32c6/include/hal/uart_ll.h

@@ -96,10 +96,10 @@ static inline void lp_uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *source_
     switch (LP_CLKRST.lpperi.lp_uart_clk_sel) {
     default:
     case 0:
-        *source_clk = LP_UART_SCLK_LP_FAST;
+        *source_clk = (soc_module_clk_t)LP_UART_SCLK_LP_FAST;
         break;
     case 1:
-        *source_clk = LP_UART_SCLK_XTAL_D2;
+        *source_clk = (soc_module_clk_t)LP_UART_SCLK_XTAL_D2;
         break;
     }
 }
@@ -224,13 +224,13 @@ static inline void uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *source_clk
         switch (UART_LL_PCR_REG_GET(hw, sclk_conf, sclk_sel)) {
         default:
         case 1:
-            *source_clk = UART_SCLK_PLL_F80M;
+            *source_clk = (soc_module_clk_t)UART_SCLK_PLL_F80M;
             break;
         case 2:
-            *source_clk = UART_SCLK_RTC;
+            *source_clk = (soc_module_clk_t)UART_SCLK_RTC;
             break;
         case 3:
-            *source_clk = UART_SCLK_XTAL;
+            *source_clk = (soc_module_clk_t)UART_SCLK_XTAL;
             break;
         }
     } else {

components/hal/esp32h2/include/hal/uart_ll.h

@@ -169,13 +169,13 @@ static inline void uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *source_clk
     switch (UART_LL_PCR_REG_GET(hw, sclk_conf, sclk_sel)) {
         default:
         case 1:
-            *source_clk = UART_SCLK_PLL_F48M;
+            *source_clk = (soc_module_clk_t)UART_SCLK_PLL_F48M;
             break;
         case 2:
-            *source_clk = UART_SCLK_RTC;
+            *source_clk = (soc_module_clk_t)UART_SCLK_RTC;
             break;
         case 3:
-            *source_clk = UART_SCLK_XTAL;
+            *source_clk = (soc_module_clk_t)UART_SCLK_XTAL;
             break;
     }
 }

components/hal/esp32s2/include/hal/uart_ll.h

@@ -90,10 +90,10 @@ FORCE_INLINE_ATTR void uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *source
     switch (hw->conf0.tick_ref_always_on) {
         default:
         case 0:
-            *source_clk = UART_SCLK_REF_TICK;
+            *source_clk = (soc_module_clk_t)UART_SCLK_REF_TICK;
             break;
         case 1:
-            *source_clk = UART_SCLK_APB;
+            *source_clk = (soc_module_clk_t)UART_SCLK_APB;
             break;
     }
 }

components/hal/esp32s3/include/hal/uart_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -109,13 +109,13 @@ FORCE_INLINE_ATTR void uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *source
     switch (hw->clk_conf.sclk_sel) {
         default:
         case 1:
-            *source_clk = UART_SCLK_APB;
+            *source_clk = (soc_module_clk_t)UART_SCLK_APB;
             break;
         case 2:
-            *source_clk = UART_SCLK_RTC;
+            *source_clk = (soc_module_clk_t)UART_SCLK_RTC;
             break;
         case 3:
-            *source_clk = UART_SCLK_XTAL;
+            *source_clk = (soc_module_clk_t)UART_SCLK_XTAL;
             break;
     }
 }
@@ -552,7 +552,6 @@ FORCE_INLINE_ATTR void uart_ll_set_data_bit_num(uart_dev_t *hw, uart_word_length
 }
 
 /**
-FORCE_INLINE_ATTR void uart_ll_get_sclk(uart_dev_t *hw, uart_sclk_t *source_clk)
  * @brief  Set the rts active level.
  *
  * @param  hw Beginning address of the peripheral registers.