i2c: fix the controller count in the header description

Closes https://github.com/espressif/esp-idf/issues/8133

components/soc/esp32/include/soc/soc_caps.h

@@ -1,6 +1,6 @@
 
 /*
- * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -150,7 +150,7 @@
 #define SOC_GPIO_SUPPORT_SLP_SWITCH  (1)
 
 /*-------------------------- I2C CAPS ----------------------------------------*/
-// ESP32 have 2 I2C.
+// ESP32 has 2 I2C
 #define SOC_I2C_NUM             (2)
 
 #define SOC_I2C_FIFO_LEN        (32) /*!< I2C hardware FIFO depth */
@@ -166,7 +166,7 @@
 #define SOC_APLL_MAX_HZ    (125000000) // 125MHz, refer to 'periph_rtc_apll_freq_set' for the calculation
 
 /*-------------------------- I2S CAPS ----------------------------------------*/
-// ESP32 have 2 I2S
+// ESP32 has 2 I2S
 #define SOC_I2S_NUM                 (2U)
 #define SOC_I2S_SUPPORTS_APLL       (1) // ESP32 support APLL
 #define SOC_I2S_SUPPORTS_PDM_TX     (1)

components/soc/esp32c3/include/soc/soc_caps.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -140,7 +140,7 @@
 #define SOC_DEDIC_PERIPH_ALWAYS_ENABLE  (1) /*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */
 
 /*-------------------------- I2C CAPS ----------------------------------------*/
-// ESP32-C3 have 2 I2C.
+// ESP32-C3 has 1 I2C
 #define SOC_I2C_NUM                 (1U)
 
 #define SOC_I2C_FIFO_LEN            (32) /*!< I2C hardware FIFO depth */

components/soc/esp32h2/include/soc/soc_caps.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -134,7 +134,7 @@
 #define SOC_DEDIC_PERIPH_ALWAYS_ENABLE  (1) /*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */
 
 /*-------------------------- I2C CAPS ----------------------------------------*/
-// ESP32-C3 have 2 I2C.
+// ESP32-H2 has 1 I2C
 #define SOC_I2C_NUM                 (1U)
 
 #define SOC_I2C_FIFO_LEN            (32) /*!< I2C hardware FIFO depth */

components/soc/esp32s2/include/soc/soc_caps.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -140,7 +140,7 @@
 #define SOC_DEDIC_GPIO_OUT_AUTO_ENABLE  (1) /*!< Dedicated GPIO output attribution is enabled automatically */
 
 /*-------------------------- I2C CAPS ----------------------------------------*/
-// ESP32-S2 have 2 I2C.
+// ESP32-S2 has 2 I2C
 #define SOC_I2C_NUM            (2)
 
 #define SOC_I2C_FIFO_LEN       (32) /*!< I2C hardware FIFO depth */
@@ -162,7 +162,7 @@
 #define SOC_APLL_MAX_HZ    (125000000) // 125MHz, refer to 'periph_rtc_apll_freq_set' for the calculation
 
 /*-------------------------- I2S CAPS ----------------------------------------*/
-// ESP32-S2 have 1 I2S
+// ESP32-S2 has 1 I2S
 #define SOC_I2S_NUM                (1U)
 #define SOC_I2S_SUPPORTS_APLL      (1) // ESP32-S2 support APLL
 #define SOC_I2S_SUPPORTS_DMA_EQUAL (1)

components/soc/esp32s3/include/soc/Kconfig.soc_caps.in

@@ -47,30 +47,6 @@ config SOC_GPIO_SUPPORT_SLP_SWITCH
     bool
     default y
 
-config SOC_I2C_NUM
-    int
-    default 2
-
-config SOC_I2C_FIFO_LEN
-    int
-    default 32
-
-config SOC_I2C_SUPPORT_HW_FSM_RST
-    bool
-    default y
-
-config SOC_I2C_SUPPORT_HW_CLR_BUS
-    bool
-    default y
-
-config SOC_I2C_SUPPORT_XTAL
-    bool
-    default y
-
-config SOC_I2C_SUPPORT_RTC
-    bool
-    default y
-
 config SOC_LEDC_SUPPORT_XTAL_CLOCK
     bool
     default y
@@ -359,6 +335,30 @@ config SOC_DEDIC_GPIO_OUT_AUTO_ENABLE
     bool
     default y
 
+config SOC_I2C_NUM
+    int
+    default 2
+
+config SOC_I2C_FIFO_LEN
+    int
+    default 32
+
+config SOC_I2C_SUPPORT_HW_FSM_RST
+    bool
+    default y
+
+config SOC_I2C_SUPPORT_HW_CLR_BUS
+    bool
+    default y
+
+config SOC_I2C_SUPPORT_XTAL
+    bool
+    default y
+
+config SOC_I2C_SUPPORT_RTC
+    bool
+    default y
+
 config SOC_I2S_NUM
     int
     default 2

components/soc/esp32s3/include/soc/i2c_caps.h

@@ -1,36 +0,0 @@
-// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#pragma once
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-// ESP32-S3 have 2 I2C.
-#define SOC_I2C_NUM            (2)
-
-#define SOC_I2C_FIFO_LEN       (32) /*!< I2C hardware FIFO depth */
-
-//ESP32-S3 support hardware FSM reset
-#define SOC_I2C_SUPPORT_HW_FSM_RST  (1)
-//ESP32-S3 support hardware clear bus
-#define SOC_I2C_SUPPORT_HW_CLR_BUS  (1)
-
-#define SOC_I2C_SUPPORT_XTAL       (1)
-#define SOC_I2C_SUPPORT_RTC        (1)
-
-#ifdef __cplusplus
-}
-#endif

components/soc/esp32s3/include/soc/soc_caps.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -122,7 +122,18 @@
 #define SOC_DEDIC_GPIO_OUT_AUTO_ENABLE  (1) /*!< Dedicated GPIO output attribution is enabled automatically */
 
 /*-------------------------- I2C CAPS ----------------------------------------*/
-#include "i2c_caps.h"
+// ESP32-S3 has 2 I2C
+#define SOC_I2C_NUM            (2)
+
+#define SOC_I2C_FIFO_LEN       (32) /*!< I2C hardware FIFO depth */
+
+//ESP32-S3 support hardware FSM reset
+#define SOC_I2C_SUPPORT_HW_FSM_RST  (1)
+//ESP32-S3 support hardware clear bus
+#define SOC_I2C_SUPPORT_HW_CLR_BUS  (1)
+
+#define SOC_I2C_SUPPORT_XTAL       (1)
+#define SOC_I2C_SUPPORT_RTC        (1)
 
 /*-------------------------- I2S CAPS ----------------------------------------*/
 #define SOC_I2S_NUM                 (2)

docs/en/api-reference/peripherals/i2c.rst

@@ -3,6 +3,8 @@ Inter-Integrated Circuit (I2C)
 
 :link_to_translation:`zh_CN:[中文]`
 
+{IDF_TARGET_I2C_NUM:default="2", esp32c3="1", esp32h2="1", esp328684="1"}
+
 Overview
 --------
 
@@ -10,13 +12,7 @@ I2C is a serial, synchronous, half-duplex communication protocol that allows co-
 
 With such advantages as simplicity and low manufacturing cost, I2C is mostly used for communication of low-speed peripheral devices over short distances (within one foot).
 
-.. only:: esp32c3
-
-    {IDF_TARGET_NAME} has only one I2C controller (also referred to as port) which is responsible for handling communications on I2C bus. The I2C controller can operate as master or slave.
-
-.. only:: not esp32c3
-
-    {IDF_TARGET_NAME} has two I2C controllers (also referred to as ports) which are responsible for handling communications on the I2C bus. Each I2C controller can operate as master or slave. As an example, one controller can act as a master and the other as a slave at the same time.
+{IDF_TARGET_NAME} has {IDF_TARGET_I2C_NUM} I2C controller (also referred to as port), responsible for handling communications on the I2C bus. A single I2C controller can operate as master or slave.
 
 Driver Features
 ---------------

docs/zh_CN/api-reference/peripherals/i2c.rst

@@ -3,6 +3,8 @@ I2C 驱动程序
 
 :link_to_translation:`en:[English]`
 
+{IDF_TARGET_I2C_NUM:default="2", esp32c3="1", esp32h2="1", esp328684="1"}
+
 概述
 ---------
 
@@ -10,13 +12,7 @@ I2C 是一种串行同步半双工通信协议，总线上可以同时挂载多
 
 I2C 具有简单且制造成本低廉等优点，主要用于低速外围设备的短距离通信（一英尺以内）。
 
-.. only:: esp32c3
-
-    {IDF_TARGET_NAME} 只有一个 I2C 控制器（也称为端口），负责处理在 I2C 总线上的通信。每个控制器都可以设置为主机或从机。
-
-.. only:: not esp32c3
-
-    {IDF_TARGET_NAME} 有两个 I2C 控制器（也称为端口），负责处理在 I2C 两根总线上的通信。每个控制器都可以设置为主机或从机。例如，可以同时让一个控制器用作主机，另一个用作从机。
+{IDF_TARGET_NAME} 有{IDF_TARGET_I2C_NUM}个 I2C 控制器（也称为端口），负责处理在 I2C 总线上的通信。每个控制器都可以设置为主机或从机。
 
 驱动程序的功能
 ---------------

tools/ci/check_copyright_ignore.txt

@@ -1883,7 +1883,6 @@ components/soc/esp32s3/include/soc/hinf_reg.h
 components/soc/esp32s3/include/soc/hinf_struct.h
 components/soc/esp32s3/include/soc/host_reg.h
 components/soc/esp32s3/include/soc/host_struct.h
-components/soc/esp32s3/include/soc/i2c_caps.h
 components/soc/esp32s3/include/soc/i2c_reg.h
 components/soc/esp32s3/include/soc/i2c_struct.h
 components/soc/esp32s3/include/soc/i2s_reg.h