Initial public version

.gitignore

@@ -0,0 +1,14 @@
+.config
+*.o
+*.pyc
+
+# gtags
+GTAGS
+GRTAGS
+GPATH
+
+# emacs temp file suffixes
+*~
+.#*
+\#*#
+

.gitmodules

@@ -0,0 +1,3 @@
+[submodule "components/esp32/lib"]
+	path = components/esp32/lib
+	url = ssh://git@github.com:espressif/esp32-wifi-lib.git

Kconfig

@@ -0,0 +1,63 @@
+#
+# For a description of the syntax of this configuration file,
+# see kconfig/kconfig-language.txt.
+#
+mainmenu "Espressif ESP32 SDK Configuration"
+
+
+menu "SDK tool configuration"
+config TOOLPREFIX
+	string "Compiler toolchain path/prefix"
+	default "xtensa-esp32-elf-"
+	help
+		The prefix/path that is used to call the toolchain. The default setting assumes
+		a crosstool-ng gcc setup that is in your PATH.
+
+config PYTHON
+    string "Python 2 interpreter"
+	default "python"
+	help
+	    The executable name/path that is used to run python. On some systems Python 2.x
+		may need to be invoked as python2.
+
+config MEMMAP_BT
+	bool "Reserve space for Bluetooth stack"
+	default "n"
+	help
+		The Bluetooth stack uses memory that cannot be used as generic memory anymore. This
+		reserves the space for that within the memory map of the compiled binary.
+
+config MEMMAP_SMP
+	bool "Reserve memory for two cores"
+	default "y"
+	help
+		The ESP32 contains two cores. If you plan to only use one, you can disable this item
+		to save some memory. (ToDo: Make this automatically depend on unicore support)
+
+config MEMMAP_TRACEMEM
+	bool "Use TRAX tracing feature"
+	default "n"
+	help
+		The ESP32 contains a feature which allows you to trace the execution path the processor
+		has taken through the program. This is stored in a chunk of 32K (16K for single-processor)
+		of memory that can't be used for general purposes anymore. Disable this if you do not know
+		what this is.
+
+config MEMMAP_SPISRAM
+	bool "Use external SPI SRAM chip as main memory"
+	default "n"
+	help
+		The ESP32 can control an external SPI SRAM chip, adding the memory it contains to the 
+		main memory map. Enable this if you have this hardware and want to use it in the same
+		way as on-chip RAM.
+
+endmenu
+
+source "$COMPONENT_KCONFIGS_PROJBUILD"
+
+menu "Component config"
+source "$COMPONENT_KCONFIGS"
+endmenu
+
+
+

LICENSE

@@ -0,0 +1,202 @@
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README.buildenv

@@ -0,0 +1,265 @@
+The build structure of the Espressif IoT Development Framework explained.
+
+An ESP-IDF project can be seen as an almagation of a number of components.
+For example, for a webserver that shows the current humidity, we would
+have:
+- The ESP32 base libraries (libc, rom bindings etc)
+- The WiFi drivers
+- A TCP/IP stack
+- The FreeRTOS operating system
+- A webserver
+- A driver for an humidity sensor
+- Main code tying it all together
+
+ESP-IDF makes these components explicit and configurable. To do that, when a project
+is compiled, the build environment will look up all the components in the
+SDK directories, the project directories and optionally custom other component
+directories. It then allows the user to configure compile-time options using
+a friendly text-based menu system to customize the SDK as well as other components
+to the requirements of the project. After the components are customized, the
+build process will compile everything into an output file, which can then be uploaded
+into a board in a way that can also be defined by components.
+
+A project in this sense is defined as a directory under which all the files required
+to build it live, excluding the SDK files and the toolchain. A simple project
+tree looks like this:
+
+- myProject/ - build/
+             - components/ - component1/ - Makefile
+                                         - Kconfig
+                                         - src1.c
+                           - component2/ - Makefile
+                                         - Kconfig
+                                         - src1.c
+             - main/       - src1.c
+                           - src2.c
+             - Makefile
+
+
+As we can see, a project consists of a components/ subdirectory containing its
+components as well as one or more directories containing the project-specific
+sources; by default a single directory called 'main' is assumed. The project
+directory will also have a Makefile where the projects name as well as optionally
+other options are defined. After compilation, the project directory will contain
+a 'build'-directory containing all of the objects, libraries and other generated 
+files as well as the final binary.
+
+Components also have a Makefile containing various definititions influencing
+the build process of the component as well as the project it's used in, as
+well as a Kconfig file defining the compile-time options that are settable 
+by means of the menu system.
+
+
+Project makefile variables that can be set by the programmer:
+PROJECT_NAME: Mandatory. Name for the project
+BUILD_DIR_BASE: Set the directory where all objects/libraries/binaries end up in.
+	Defaults to $(PROJECT_PATH)/build
+COMPONENT_DIRS: Search path for components. Defaults to the component/ directories
+	in the SDK path and the project path.
+COMPONENTS: A list of component names. Defaults to all the component found in the
+	COMPONENT_DIRS directory
+EXTRA_COMPONENT_DIRS: Defaults to unset. Use this to add directories to the default
+	COMPONENT_DIRS.
+SRCDIRS: Directories under the project dir containing project-specific sources. 
+	Defaults to 'main'. These are treated as 'lite' components: they do not have
+	include directories that are passed to the compilation pass of all components and
+	they do not have a Kconfig option.
+
+
+Component makefile variables that can be set by the programmer:
+COMPONENT_ADD_INCLUDEDIRS: Relative path to include directories to be added to
+	the entire project
+COMPONENT_PRIV_INCLUDEDIRS: Relative path to include directories that are only used
+	when compiling this specific component
+COMPONENT_DEPENDS: Names of any components that need to be compiled before this component.
+COMPONENT_ADD_LDFLAGS: Ld flags to add for this project. Defaults to -l$(COMPONENT_NAME).
+	Add libraries etc in the current directory as $(abspath libwhatever.a)
+COMPONENT_EXTRA_INCLUDES: Any extra include paths. These will be prefixed with '-I' and
+	passed to the compiler; please put absolute paths here.
+COMPONENT_SRCDIRS: Relative directories to look in for sources. Defaults to '.', the current 
+	directory (the root of the component) only. Use this to specify any subdirectories. Note
+	that specifying this overwrites the default action of compiling everything in the 
+	components root dir; to keep this behaviour please also add '.' as a directory in this
+	list.
+COMPONENT_OBJS: Object files to compile. Defaults to the .o variants of all .c and .S files
+	that are found in COMPONENT_SRCDIRS.
+COMPONENT_EXTRA_CLEAN: Files that are generated using rules in the components Makefile
+	that also need to be cleaned
+COMPONENT_BUILDRECIPE: Recipe to build the component. Optional. Defaults to building all
+	COMPONENT_OBJS and linking them into lib(componentname).a
+COMPONENT_CLEANRECIPE: Recipe to clean the component. Optional. Defaults to removing
+	all built objects and libraries.
+COMPONENT_BUILD_DIR: Equals the cwd of the component build, which is the build dir
+	of the component (where all the .o etc files should be created).
+
+
+These variables are already set early on in the Makefile and the values in it will
+be usable in component or project Makefiles:
+CC, LD, AR, OBJCOPY: Xtensa gcc tools
+HOSTCC, HOSTLD etc: Host gcc tools
+LDFLAGS, CFLAGS: Set to usable values as defined in SDK Makefile
+PROJECT_NAME: Name of the project, as set in project makefile
+PROJECT_PATH: Path to the root of the project folder
+COMPONENTS: Name of the components to be included
+CONFIG_*: Values set by 'make menuconfig' also have corresponding Makefile variables.
+
+For components, there also are these defines:
+COMPONENT_PATH: Absolute path to the root of the source tree of the component we're
+	compiling
+COMPONENT_LIBRARY: The full path to the static library the components compilation pass
+	is supposed to generate
+
+
+How this works:
+The Make process is always invoked from the project directory by the
+user; invoking it anywhere else gives an error. This is what happens if
+we build a binary:
+
+The Makefile first determines how it was included. It determines it was
+included as a  project file in this case and will continue to figure out
+various paths as well as the components available to it. It will also
+collect the ldflags and includes that the components specify they need.
+It does this by running a dummy Make on the components with a target that
+will output these values.
+
+The Makefile will then create targets to build the lib*.a libraries of
+all components and make the elf target depend on this. The targets
+invoke Make on the makefiles of the components in a subshell: this way
+the components have full freedom to do whatever is necessary to build
+the library without influencing other components. By default, the
+component includes the utility makefile $(SDK_PATH)/make/component.mk.
+This provides default targets and configurations that will work
+out-of-the-box for most projects.
+
+For components that have parts that need to be run when building of the
+project is done, you can create a file called Makefile.projbuild in the
+component root directory. This  file will be included in the main
+Makefile. For the menu, there's an equivalent: if you want to include
+options not in the 'components' submenu, create a Kconfig.projbuild and
+it will be included in the main menu of menuconfig. Take good care when
+(re)defining stuff here: because it's included with all the other
+.projbuild files, it's possible to overwrite variables or re-declare
+targets defined in the SDK makefile/Kconfig and  other .projbuild files
+
+
+WRITING COMPONENT MAKEFILES
+
+A component consists of a directory which doubles as the name for the
+component: a component named 'httpd' lives in a directory called 'httpd'
+Because components usually live under the project directory (although
+they can also reside in an other folder), the path to this may be
+something like  /home/myuser/projects/myprojects/components/httpd .
+
+One of the things that most components will have is a Makefile,
+containing instructions on how to build the component. Because the
+build environment tries to set reasonable defaults that will work most
+of the time, a component Makefile can be pretty small. At the absolute
+minimum, it will just include the SDK component makefile, which adds
+component functionality:
+
+----8<----
+include $(SDK_PATH)/make/component.mk
+---->8----
+
+This will take all the .c and .S files in the component root and compile
+them into  object files, finally linking them into a library.
+Subdirectories are ignored; if your project has sources in subdirectories
+instead of in the root of the component, you can tell that to the build
+system by setting COMPONENT_SRCDIRS:
+
+----8<----
+COMPONENT_SRCDIRS := src1 src2
+include $(SDK_PATH)/make/component.mk
+---->8----
+
+This will compile all source files in the src1/ and src2/ subdirectories
+instead.
+
+The standard component.mk logic adds all .S and .c files in the source
+directories as sources to be compiled unconditionally. It is possible
+to circumvent that logic and hardcode the objects to be compiled by
+manually setting the COMPONENT_OBJS variable to the name of the
+objects that need to be generated:
+
+----8<----
+COMPONENT_OBJS := file1.o file2.o thing/filea.o thing/fileb.o anotherthing/main.o
+include $(SDK_PATH)/make/component.mk
+---->8----
+
+This can also be used in order to conditionally compile some files
+dependent on the options selected in the Makefile:
+
+Kconfig:
+----8<----
+config FOO_ENABLE_BAR
+	bool "Enable the BAR feature."
+	help
+		This enables the BAR feature of the FOO component.
+---->8----
+
+Makefile:
+----8<----
+COMPONENT_OBJS := foo_a.o foo_b.o $(if $(CONFIG_FOO_ENABLE_BAR),foo_bar.o foo_bar_interface.o)
+include $(SDK_PATH)/make/component.mk
+---->8----
+
+Some components will have a situation where a source file isn't supplied
+with the  component itself but has to be generated from another file. Say
+our component has a header file that consists of the converted binary
+data of a BMP file, converted using a hypothetical tool called bmp2h. The
+header file is then included in as C source file called graphics_lib.c.
+
+----8<----
+COMPONENT_EXTRA_CLEAN := logo.h
+
+graphics_lib.o: logo.h
+
+logo.h: $(COMPONENT_PATH)/logo.bmp
+	bmp2h -i $^ -o $@
+
+include $(SDK_PATH)/make/component.mk
+---->8----
+
+In this example, graphics_lib.o and logo.h will be generated in the
+current directory (the build directory) while logo.bmp comes with the
+component and resides under the component path. Because logo.h is a
+generated file, it needs to be cleaned when make clean is called which
+why it is added to the COMPONENT_EXTRA_CLEAN variable.
+
+
+This will work just fine, but there's one last cosmetic improvement that
+can be done. The SDK make system tries to make the make process somewhat
+easier on the  eyes by hiding the commands (unless you run make with the
+V=1 switch) and this does  not do that yet. Here's an improved version
+that will output in the same style as  the rest of the make process:
+
+----8<----
+COMPONENT_EXTRA_CLEAN := test_tjpgd_logo.h
+
+graphics_lib.o: logo.h
+
+logo.h: $(COMPONENT_PATH)/logo.bmp
+	$(vecho) BMP2H $@
+	$(Q) bmp2h -i $^ -o $@
+
+include $(SDK_PATH)/make/component.mk
+---->8----
+
+Obviously, there are cases where all these recipes are insufficient for a
+certain component, for example when the component is basically a wrapper
+around another third-party component not originally intended to be
+compiled under this build system. In that case, it's possible to forego
+the build  system entirely by setting COMPONENT_OWNBUILDTARGET and
+possibly  COMPONENT_OWNCLEANTARGET and defining your own build- and clean
+target. The build target can do anything as long as it creates
+$(COMPONENT_LIBRARY) for the main file to link into the project binary, 
+and even that is not necessary: if the COMPONENT_ADD_LDFLAGS variable
+is set, the component can instruct the linker to do anything else as well.
+
+
+
+
+
+
+
+

README.md

@@ -0,0 +1,151 @@
+# Using Espressif IoT Development Framework with the ESP32
+
+# Prerequisites
+
+# Configuring your project
+
+`make menuconfig`
+
+# Compiling your project
+
+`make app`
+
+# Flashing the Bootloader
+
+ESP32 has a bootloader in ROM which runs after reset, but ESP-IDF also uses a second stage software bootloader. The ROM bootloader loads the software bootloader, which then loads the firmware app of the ESP32. The software bootloader must be flashed to offset 0x5000 in the flash.
+
+To build the software bootloader, navigate to your project's top-level directory and run:
+
+``` shell
+make bootloader
+```
+
+If you've configured the serial port details in `make menuconfig`, then
+
+``` shell
+make bootloader-flash
+```
+
+... will automatically run esptool.py to flash the image. Otherwise, you can customise the `esptool.py` command that is printed out as part of `make bootloader`.
+
+You only need to flash the ESP32 bootloader once.
+
+# The Partition Table
+
+Once you've compiled your project, the "build" directory will contain a binary file with a name like "my_app.bin". This is an ESP32 image binary that can be loaded by the bootloader.
+
+A single ESP32's flash can contain multiple apps, as well as many different kinds of data (calibration data, filesystems, parameter storage, etc). For this reason a partition table is flashed to offset 0x4000 in the flash.
+
+Each entry in the partition table has a name (label), type (app, data, or something else), subtype and the offset in flash where the partition is loaded.
+
+The simplest way to use the partition table is to `make menuconfig` and choose one of the simple predefined partition tables:
+
+* "Single factory app, no OTA"
+* "Factory app, two OTA definitions"
+
+In both cases the factory app is flashed at offset 0x10000. If you `make partition_table` then it will print a summary of the partition table.
+
+Here is the summary printed for the "Single factory app, no OTA" configuration:
+
+```
+# Espressif ESP32 Partition Table
+# Name,  Type, SubType, Offset,  Size
+factory, app,  factory, 0x10000, 1M
+rfdata,  data, rf,     0x110000, 256K
+wifidata,data, wifi,   0x150000, 256K
+```
+
+* At a 0x10000 (64KB) offset in the flash is the app labelled "factory". The bootloader will run this app by default.
+* There are also two data regions defined in the partition table for storing RF & Wifi calibration data.
+
+Here is the summary printed for the "Factory app, two OTA definitions" configuration:
+
+```
+# Espressif ESP32 Partition Table
+# Name,  Type, SubType, Offset,  Size
+factory, app,  factory,  0x10000, 1M
+ota_0,   app,  ota_0,   0x110000, 1M
+ota_1,   app,  ota_1,   0x210000, 1M
+rfdata,  data, rf,      0x310000, 256K
+wifidata,data, wifi,    0x350000, 256K
+otadata, data, ota,     0x390000, 256K
+```
+
+* There are now three app partition definitions.
+* The type of all three are set as "app", but the subtype varies between the factory app at 0x10000 and the next two "OTA" apps.
+* There is also a new "ota data" slot, which holds the data for OTA updates. The bootloader consults this data in order to know which app to execute. If "ota data" is empty, it will execute the factory app.
+
+
+## Creating Custom Tables
+
+If you choose "Custom partition table CSV" in menuconfig then you can also enter the name of a CSV file (in the project directory) to use for your partition table. The CSV file can describe any number of definitions for the table you need.
+
+The CSV format is the same format as printed in the summaries shown above. However, not all fields are required in the CSV. For example, here is the "input" CSV for the OTA partition table:
+
+```
+# Name,   Type, SubType, Offset,   Size
+factory,  app,  factory, 0x10000,  1M
+ota_0,    app,  ota_0,   ,         1M
+ota_1,    app,  ota_1,   ,         1M
+rfdata,   data, rf,      ,         256K
+wifidata, data, wifi,    ,         256K
+otadata,  data, ota,     ,         256K
+```
+
+* Whitespace between fields is ignored, and so is any line starting with # (comments).
+* Each non-comment line in the CSV file is a partition definition.
+* Only the offset for the first partition is supplied. The gen_esp32part.py tool fills in each remaining offset to start after the preceding partition.
+
+### Name field
+
+Name field can be any meaningful name. It is not significant to the ESP32. Names longer than 16 characters will be truncated.
+
+### Type field
+
+Type field can be specified as app (0) or data (1). Or it can be a number 0-254 (or as hex 0x00-0xFE). Types 0x00-0x3F are reserved for Espressif. If your application needs to store data, please add a custom partition type in the range 0x40-0xFE.
+
+The bootloader ignores any types other than 0 & 1.
+
+### Subtype
+
+When type is "app", the subtype field can be specified as factory (0), ota_0 (0x10) ... ota_15 (0x1F) and test (0x20). Or it can be any number 0-255 (0x00-0xFF). The bootloader will execute the factory app unless there it sees a partition of type data/ota, in which case it reads this partition to determine which OTA image to boot
+
+When type is "data", the subtype field can be specified as ota (0), rf (1), wifi (2). Or it can be a number 0x00-0xFF. The bootloader ignores all data subtypes except for ota. Other "data" subtypes are reserved for Espressif use. To create custom data partition subtypes then use a custom type value, and choose any subtype 0x00-0xFF.
+
+### Offset & Size
+
+Only the first offset field is required (we recommend using 0x10000). Partitions with blank offsets will start after the previous partition.
+
+App partitions have to be at offsets aligned to 0x10000 (64K). If you leave the offset field blank, the tool will automatically align the partition. If you specify an unaligned offset for an app partition, the tool will return an error.
+
+Sizes and offsets can be specified as decimal numbers, hex numbers with the prefix 0x, or size multipliers M or K (1024 and 1024*1024 bytes).
+
+## Generating Binary Partition Table
+
+The partition table which is flashed to the ESP32 is in a binary format, not CSV. The tool components/partition_table/gen_esp32part.py is used to convert between CSV and binary formats.
+
+If you configure the partition table CSV name in `make menuconfig` and then `make partition_table`, this conversion is done for you.
+
+To convert CSV to Binary manually:
+
+``` shell
+python components/partition_table/gen_esp32part.py --verify input_partitions.csv binary_partitions.bin
+```
+
+To convert binary format back to CSV:
+
+``` shell
+python components/partition_table/gen_esp32part.py --verify binary_partitions.bin input_partitions.csv
+```
+
+To display the contents of a binary partition table on stdout (this is how the summaries displayed when running `make partition_table` are generated:
+
+``` shell
+python components/partition_table/gen_esp32part.py binary_partitions.bin
+```
+
+`gen_esp32part.py` takes one optional argument, `--verify`, which will also verify the partition table during conversion (checking for overlapping partitions, unaligned partitions, etc.)
+
+# Flashing the partition table
+
+The command `make partition_table-flash` will flash the partition table with esptool.py. However a manual flashing command is printed as part of `make partition_table`.

bin/eclipse_windows_make.sh

@@ -0,0 +1,9 @@
+#!/bin/bash
+# A wrapper for make on Windows with Eclipse
+#
+# Eclipse's output parser expects to see output of the form C:/dir/dir/file but our Make
+# process uses MinGW paths of the form /c/dir/dir/file. So parse these out...
+#
+# (regexp deliberate only matches after a space character to try and avoid false-positives.)
+echo "Running make in $(dirname $0)"
+make $@ V=1 | sed -E "s@ /([a-z])/(.+)/@ \1:/\2/@g" | sed -E "s@-I/([a-z])/(.+)/@-I\1:/\2/@g" | sed -E "s@-L/([a-z])/(.+)/@-L\1:/\2/@g"

bin/esptool.py

@@ -0,0 +1,1800 @@
+#!/usr/bin/env python
+# NB: Before sending a PR to change the above line to '#!/usr/bin/env python2', please read https://github.com/themadinventor/esptool/issues/21
+#
+# ESP8266 ROM Bootloader Utility
+# https://github.com/themadinventor/esptool
+#
+# Copyright (C) 2014-2016 Fredrik Ahlberg, Angus Gratton, other contributors as noted.
+# ESP31/32 support Copyright (C) 2016 Angus Gratton, based in part on work Copyright
+# (C) 2015-2016 Espressif Systems.
+#
+# This program is free software; you can redistribute it and/or modify it under
+# the terms of the GNU General Public License as published by the Free Software
+# Foundation; either version 2 of the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+# FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License along with
+# this program; if not, write to the Free Software Foundation, Inc., 51 Franklin
+# Street, Fifth Floor, Boston, MA 02110-1301 USA.
+
+import argparse
+import hashlib
+import inspect
+import json
+import os
+import serial
+import struct
+import subprocess
+import sys
+import time
+import zlib
+
+__version__ = "2.0-dev"
+
+
+MAX_UINT32 = 0xffffffff
+MAX_UINT24 = 0xffffff
+
+
+class ESPROM(object):
+    """ Base class providing access to ESP ROM bootloader. Subclasses provide
+    ESP8266, ESP31 & ESP32 specific functionality.
+
+    Don't instantiate this base class directly, either instantiate a subclass or
+    call ESPROM.detect_chip() which will interrogate the chip and return the
+    appropriate subclass instance.
+
+    """
+    CHIP_NAME = "Espressif device"
+
+    DEFAULT_PORT = "/dev/ttyUSB0"
+
+    # These are the currently known commands supported by the ROM
+    ESP_FLASH_BEGIN = 0x02
+    ESP_FLASH_DATA  = 0x03
+    ESP_FLASH_END   = 0x04
+    ESP_MEM_BEGIN   = 0x05
+    ESP_MEM_END     = 0x06
+    ESP_MEM_DATA    = 0x07
+    ESP_SYNC        = 0x08
+    ESP_WRITE_REG   = 0x09
+    ESP_READ_REG    = 0x0a
+
+    # Maximum block sized for RAM and Flash writes, respectively.
+    ESP_RAM_BLOCK   = 0x1800
+    ESP_FLASH_BLOCK = 0x400
+
+    # Default baudrate. The ROM auto-bauds, so we can use more or less whatever we want.
+    ESP_ROM_BAUD    = 115200
+
+    # First byte of the application image
+    ESP_IMAGE_MAGIC = 0xe9
+
+    # Initial state for the checksum routine
+    ESP_CHECKSUM_MAGIC = 0xef
+
+    # Flash sector size, minimum unit of erase.
+    ESP_FLASH_SECTOR = 0x1000
+
+    UART_DATA_REG_ADDR = 0x60000078
+
+    # SPI peripheral "command" bitmasks
+    SPI_CMD_READ_ID = 0x10000000
+
+    # Memory addresses
+    IROM_MAP_START = 0x40200000
+    IROM_MAP_END = 0x40300000
+
+    # The number of bytes in the response that signify command status
+    STATUS_BYTES_LENGTH = 2
+
+    def __init__(self, port=DEFAULT_PORT, baud=ESP_ROM_BAUD, do_connect=True):
+        """Base constructor for ESPROM objects
+
+        Don't call this constructor, either instantiate ESP8266ROM,
+        ESP31ROM, or ESP32ROM, or use ESPROM.detect_chip().
+
+        """
+        self._port = serial.Serial(port)
+        self._slip_reader = slip_reader(self._port)
+        # setting baud rate in a separate step is a workaround for
+        # CH341 driver on some Linux versions (this opens at 9600 then
+        # sets), shouldn't matter for other platforms/drivers. See
+        # https://github.com/themadinventor/esptool/issues/44#issuecomment-107094446
+        self._port.baudrate = baud
+        if do_connect:
+            self.connect()
+
+    @staticmethod
+    def detect_chip(port=DEFAULT_PORT, baud=ESP_ROM_BAUD):
+        """Use serial access to detect the chip type.
+
+        We use the UART's datecode register for this, it's mapped at
+        the same address on ESP8266 & ESP31/32 so we can use one
+        memory read and compare to the datecode register for each chip
+        type.
+
+        """
+        detect_port = ESPROM(port, baud, True)
+        sys.stdout.write('Detecting chip type... ')
+        date_reg = detect_port.read_reg(ESPROM.UART_DATA_REG_ADDR)
+        for cls in [ESP8266ROM, ESP31ROM, ESP32ROM]:
+            if date_reg == cls.DATE_REG_VALUE:
+                inst = cls(port, baud, False)  # don't connect a second time
+                print '%s' % inst.CHIP_NAME
+                return inst
+        print ''
+        raise FatalError("Unexpected UART datecode value 0x%08x. Failed to autodetect chip type." % date_reg)
+
+    """ Read a SLIP packet from the serial port """
+    def read(self):
+        return self._slip_reader.next()
+
+    """ Write bytes to the serial port while performing SLIP escaping """
+    def write(self, packet):
+        buf = '\xc0' \
+              + (packet.replace('\xdb','\xdb\xdd').replace('\xc0','\xdb\xdc')) \
+              + '\xc0'
+        self._port.write(buf)
+
+    """ Calculate checksum of a blob, as it is defined by the ROM """
+    @staticmethod
+    def checksum(data, state=ESP_CHECKSUM_MAGIC):
+        for b in data:
+            state ^= ord(b)
+        return state
+
+    """ Send a request and read the response """
+    def command(self, op=None, data=None, chk=0):
+        if op is not None:
+            pkt = struct.pack('<BBHI', 0x00, op, len(data), chk) + data
+            self.write(pkt)
+
+        # tries to get a response until that response has the
+        # same operation as the request or a retries limit has
+        # exceeded. This is needed for some esp8266s that
+        # reply with more sync responses than expected.
+        for retry in xrange(100):
+            p = self.read()
+            if len(p) < 8:
+                continue
+            (resp, op_ret, len_ret, val) = struct.unpack('<BBHI', p[:8])
+            if resp != 1:
+                continue
+            data = p[8:]
+            if op is None or op_ret == op:
+                return val, data
+
+        raise FatalError("Response doesn't match request")
+
+    def check_command(self, op_description, op=None, data=None, chk=0):
+        """
+        Execute a command with 'command', check the result code and throw an appropriate
+        FatalError if it fails.
+
+        Returns the "result" of a successful command.
+        """
+        val, data = self.command(op, data, chk)
+
+        # things are a bit weird here, bear with us
+
+        # the status bytes are the last 2/4 bytes in the data (depending on chip)
+        if len(data) < self.STATUS_BYTES_LENGTH:
+            raise FatalError("Failed to %s. Only got %d byte status response." % op_description, len(data))
+        status_bytes = data[-self.STATUS_BYTES_LENGTH:]
+        # we only care if the first one is non-zero. If it is, the second byte is a reason.
+        if status_bytes[0] != '\0':
+            raise FatalError.WithResult('Failed to %s' % op_description, status_bytes)
+
+        # if we had more data than just the status bytes, return it as the result
+        # (this is used by the md5sum command, maybe other commands?)
+        if len(data) > self.STATUS_BYTES_LENGTH:
+            return data[:-self.STATUS_BYTES_LENGTH]
+        else:  # otherwise, just return the 'val' field which comes from the reply header (this is used by read_reg)
+            return val
+
+    def sync(self):
+        """ Perform a connection test """
+        self.command(ESPROM.ESP_SYNC, '\x07\x07\x12\x20' + 32 * '\x55')
+        for i in xrange(7):
+            self.command()
+
+    def connect(self):
+        """ Try connecting repeatedly until successful, or giving up """
+        print 'Connecting...'
+
+        for _ in xrange(4):
+            # issue reset-to-bootloader:
+            # RTS = either CH_PD or nRESET (both active low = chip in reset)
+            # DTR = GPIO0 (active low = boot to flasher)
+            self._port.setDTR(False)
+            self._port.setRTS(True)
+            time.sleep(0.05)
+            self._port.setDTR(True)
+            self._port.setRTS(False)
+            time.sleep(0.05)
+            self._port.setDTR(False)
+
+            # worst-case latency timer should be 255ms (probably <20ms)
+            self._port.timeout = 0.3
+            last_exception = None
+            for _ in xrange(4):
+                try:
+                    self._port.flushInput()
+                    self._slip_reader = slip_reader(self._port)
+                    self._port.flushOutput()
+                    self.sync()
+                    self._port.timeout = 5
+                    return
+                except FatalError as e:
+                    last_exception = e
+                    time.sleep(0.05)
+        raise FatalError('Failed to connect to %s: %s' % (self.CHIP_NAME, last_exception))
+
+    """ Read memory address in target """
+    def read_reg(self, addr):
+        # we don't call check_command here because read_reg() function is called
+        # when detecting chip type, and the way we check for success (STATUS_BYTES_LENGTH) is different
+        # for different chip types (!)
+        val, data = self.command(ESPROM.ESP_READ_REG, struct.pack('<I', addr))
+        if data[0] != '\0':
+            raise FatalError.WithResult("Failed to read register address %08x" % addr, data)
+        return val
+
+    """ Write to memory address in target """
+    def write_reg(self, addr, value, mask, delay_us=0):
+        return self.check_command("write target memory", ESPROM.ESP_WRITE_REG,
+                                  struct.pack('<IIII', addr, value, mask, delay_us))
+
+    """ Start downloading an application image to RAM """
+    def mem_begin(self, size, blocks, blocksize, offset):
+        return self.check_command("enter RAM download mode", ESPROM.ESP_MEM_BEGIN,
+                                  struct.pack('<IIII', size, blocks, blocksize, offset))
+
+    """ Send a block of an image to RAM """
+    def mem_block(self, data, seq):
+        return self.check_command("write to target RAM", ESPROM.ESP_MEM_DATA,
+                                  struct.pack('<IIII', len(data), seq, 0, 0) + data,
+                                  ESPROM.checksum(data))
+
+    """ Leave download mode and run the application """
+    def mem_finish(self, entrypoint=0):
+        return self.check_command("leave RAM download mode", ESPROM.ESP_MEM_END,
+                                  struct.pack('<II', int(entrypoint == 0), entrypoint))
+
+    """ Start downloading to Flash (performs an erase) """
+    def flash_begin(self, size, offset):
+        old_tmo = self._port.timeout
+        num_blocks = (size + ESPROM.ESP_FLASH_BLOCK - 1) / ESPROM.ESP_FLASH_BLOCK
+        erase_size = self.get_erase_size(size)
+
+        self._port.timeout = 20
+        t = time.time()
+        self.check_command("enter Flash download mode", ESPROM.ESP_FLASH_BEGIN,
+                           struct.pack('<IIII', erase_size, num_blocks, ESPROM.ESP_FLASH_BLOCK, offset))
+        if size != 0:
+            print "Took %.2fs to erase flash block" % (time.time() - t)
+        self._port.timeout = old_tmo
+
+    """ Write block to flash """
+    def flash_block(self, data, seq):
+        self.check_command("write to target Flash after seq %d" % seq,
+                           ESPROM.ESP_FLASH_DATA,
+                           struct.pack('<IIII', len(data), seq, 0, 0) + data,
+                           ESPROM.checksum(data))
+
+    """ Leave flash mode and run/reboot """
+    def flash_finish(self, reboot=False):
+        pkt = struct.pack('<I', int(not reboot))
+        self.check_command("leave Flash mode", ESPROM.ESP_FLASH_END, pkt)
+
+    """ Run application code in flash """
+    def run(self, reboot=False):
+        # Fake flash begin immediately followed by flash end
+        self.flash_begin(0, 0)
+        self.flash_finish(reboot)
+
+    """ Read SPI flash manufacturer and device id """
+    def flash_id(self):
+        self.flash_begin(0, 0)
+        self.write_reg(self.SPI_W0_REG_ADDR, 0x0, MAX_UINT32)
+        self.write_reg(self.SPI_CMD_REG_ADDR, self.SPI_CMD_READ_ID, MAX_UINT32)
+        flash_id = self.read_reg(self.SPI_W0_REG_ADDR)
+        self.flash_finish(False)
+        return flash_id
+
+    def parse_flash_size_arg(self, arg):
+        try:
+            return self.FLASH_SIZES[arg]
+        except KeyError:
+            raise FatalError("Flash size '%s' is not supported by this chip type. Supported sizes: %s"
+                             % (arg, ", ".join(self.FLASH_SIZES.keys())))
+
+    """ Abuse the loader protocol to force flash to be left in write mode """
+    def flash_unlock_dio(self):
+        # Enable flash write mode
+        self.flash_begin(0, 0)
+        # Reset the chip rather than call flash_finish(), which would have
+        # write protected the chip again (why oh why does it do that?!)
+        self.mem_begin(0,0,0,0x40100000)
+        self.mem_finish(0x40000080)
+
+    def run_stub(self, stub, params, read_output=False):
+        stub = dict(stub)
+        stub['code'] = unhexify(stub['code'])
+        if 'data' in stub:
+            stub['data'] = unhexify(stub['data'])
+
+        if stub['num_params'] != len(params):
+            raise FatalError('Stub requires %d params, %d provided'
+                             % (stub['num_params'], len(params)))
+
+        params = struct.pack('<' + ('I' * stub['num_params']), *params)
+        pc = params + stub['code']
+
+        # Upload
+        self.mem_begin(len(pc), 1, len(pc), stub['params_start'])
+        self.mem_block(pc, 0)
+        if 'data' in stub:
+            self.mem_begin(len(stub['data']), 1, len(stub['data']), stub['data_start'])
+            self.mem_block(stub['data'], 0)
+        self.mem_finish(stub['entry'])
+
+        if read_output:
+            print 'Stub executed, reading response:'
+            while True:
+                p = self.read()
+                print hexify(p)
+                if p == '':
+                    return
+
+
+class ESP8266ROM(ESPROM):
+    """ Access class for ESP8266 ROM bootloader
+    """
+    CHIP_NAME = "ESP8266EX"
+
+    DATE_REG_VALUE = 0x00062000
+
+    # OTP ROM addresses
+    ESP_OTP_MAC0    = 0x3ff00050
+    ESP_OTP_MAC1    = 0x3ff00054
+    ESP_OTP_MAC3    = 0x3ff0005c
+
+    SPI_CMD_REG_ADDR = 0x60000200
+    SPI_W0_REG_ADDR = 0x60000240
+
+    FLASH_SIZES = {
+        '512KB':0x00,
+        '256KB':0x10,
+        '1MB':0x20,
+        '2MB':0x30,
+        '4MB':0x40,
+        '2MB-c1': 0x50,
+        '4MB-c1':0x60,
+        '4MB-c2':0x70}
+
+    def chip_id(self):
+        """ Read Chip ID from OTP ROM - see http://esp8266-re.foogod.com/wiki/System_get_chip_id_%28IoT_RTOS_SDK_0.9.9%29 """
+        id0 = self.read_reg(self.ESP_OTP_MAC0)
+        id1 = self.read_reg(self.ESP_OTP_MAC1)
+        return (id0 >> 24) | ((id1 & MAX_UINT24) << 8)
+
+    def read_mac(self):
+        """ Read MAC from OTP ROM """
+        mac0 = self.read_reg(self.ESP_OTP_MAC0)
+        mac1 = self.read_reg(self.ESP_OTP_MAC1)
+        mac3 = self.read_reg(self.ESP_OTP_MAC3)
+        if (mac3 != 0):
+            oui = ((mac3 >> 16) & 0xff, (mac3 >> 8) & 0xff, mac3 & 0xff)
+        elif ((mac1 >> 16) & 0xff) == 0:
+            oui = (0x18, 0xfe, 0x34)
+        elif ((mac1 >> 16) & 0xff) == 1:
+            oui = (0xac, 0xd0, 0x74)
+        else:
+            raise FatalError("Unknown OUI")
+        return oui + ((mac1 >> 8) & 0xff, mac1 & 0xff, (mac0 >> 24) & 0xff)
+
+    def get_erase_size(self, size):
+        """ Calculate an erase size given a specific size in bytes.
+
+        Provides a workaround for the bootloader erase bug."""
+
+        sectors_per_block = 16
+        sector_size = self.ESP_FLASH_SECTOR
+        num_sectors = (size + sector_size - 1) / sector_size
+        start_sector = offset / sector_size
+
+        head_sectors = sectors_per_block - (start_sector % sectors_per_block)
+        if num_sectors < head_sectors:
+            head_sectors = num_sectors
+
+        if num_sectors < 2 * head_sectors:
+            return (num_sectors + 1) / 2 * sector_size
+        else:
+            return (num_sectors - head_sectors) * sector_size
+
+class ESP31ROM(ESPROM):
+    """ Access class for ESP31 ROM bootloader
+    """
+    CHIP_NAME = "ESP31"
+
+    DATE_REG_VALUE = 0x15052100
+
+    SPI_CMD_REG_ADDR = 0x60003000
+    SPI_W0_REG_ADDR = 0x60003040
+
+    EFUSE_BASE = 0x6001a000
+
+    FLASH_SIZES = {
+        '1MB':0x00,
+        '2MB':0x10,
+        '4MB':0x20,
+        '8MB':0x30,
+        '16MB':0x40
+    }
+
+    def read_efuse(self, n):
+        """ Read the nth word of the ESP3x EFUSE region. """
+        return self.read_reg(self.EFUSE_BASE + (4 * n))
+
+    def chip_id(self):
+        word16 = self.read_efuse(16)
+        word17 = self.read_efuse(17)
+        return ((word17 & MAX_UINT24) << 24) | (word16 >> 8) & MAX_UINT24
+
+    def read_mac(self):
+        """ Read MAC from EFUSE region """
+        word16 = self.read_efuse(16)
+        word17 = self.read_efuse(17)
+        word18 = self.read_efuse(18)
+        word19 = self.read_efuse(19)
+        wifi_mac = (((word17 >> 16) & 0xff), ((word17 >> 8) & 0xff), ((word17 >> 0) & 0xff),
+                    ((word16 >> 24) & 0xff), ((word16 >> 16) & 0xff), ((word16 >> 8) & 0xff))
+        bt_mac = (((word19 >> 16) & 0xff), ((word19 >> 8) & 0xff), ((word19 >> 0) & 0xff),
+                  ((word18 >> 24) & 0xff), ((word18 >> 16) & 0xff), ((word18 >> 8) & 0xff))
+        return (wifi_mac,bt_mac)
+
+    def get_erase_size(self, size):
+        return size
+
+class ESP32ROM(ESP31ROM):
+    """Access class for ESP32 ROM bootloader
+
+    """
+    CHIP_NAME = "ESP32"
+
+    DATE_REG_VALUE = 0x15122500
+
+    # ESP32-only commands
+    ESP_SPI_FLASH_SET = 0xb
+
+    ESP_SPI_ATTACH_REQ = 0xD
+
+    ESP_CHANGE_BAUDRATE = 0x0F
+    ESP_FLASH_DEFL_BEGIN = 0x10
+    ESP_FLASH_DEFL_DATA  = 0x11
+    ESP_FLASH_DEFL_END   = 0x12
+
+    ESP_SPI_FLASH_MD5    = 0x13
+
+    IROM_MAP_START = 0x400d0000
+    IROM_MAP_END   = 0x40400000
+    DROM_MAP_START = 0x3F400000
+    DROM_MAP_END   = 0x3F700000
+
+    # ESP32 uses a 4 byte status reply
+    STATUS_BYTES_LENGTH = 4
+
+    def flash_defl_begin(self, size, compsize, offset):
+        """ Start downloading compressed data to Flash (performs an erase) """
+        old_tmo = self._port.timeout
+        num_blocks = (compsize + self.ESP_FLASH_BLOCK - 1) / self.ESP_FLASH_BLOCK
+        erase_blocks = (size + self.ESP_FLASH_BLOCK - 1) / self.ESP_FLASH_BLOCK
+
+        erase_size = size
+        if erase_size > 0 and (offset + erase_size) >= (16 / 8) * 1024 * 1024:
+            self.flash_spi_param_set()
+
+        self._port.timeout = 20
+        t = time.time()
+        print "Unc size %d comp size %d comp blocks %d" % (size, compsize, num_blocks)
+        self.check_command("enter compressed flash mode", self.ESP_FLASH_DEFL_BEGIN,
+                           struct.pack('<IIII', erase_blocks * self.ESP_FLASH_BLOCK, num_blocks, self.ESP_FLASH_BLOCK, offset))
+        if size != 0:
+            print "Took %.2fs to erase flash block" % (time.time() - t)
+        self._port.timeout = old_tmo
+
+    """ Write block to flash, send compressed """
+    def flash_defl_block(self, data, seq):
+        self.check_command("write compressed data to flash after seq %d" % seq,
+                           self.ESP_FLASH_DEFL_DATA, struct.pack('<IIII', len(data), seq, 0, 0) + data, ESPROM.checksum(data))
+
+    """ Leave compressed flash mode and run/reboot """
+    def flash_defl_finish(self, reboot=False):
+        pkt = struct.pack('<I', int(not reboot))
+        self.check_command("leave compressed flash mode", self.ESP_FLASH_DEFL_END, pkt)
+        self.in_bootloader = False
+
+    def flash_md5sum(self, addr, size):
+        # the MD5 command is special (
+        return self.check_command('calculate md5sum', self.ESP_SPI_FLASH_MD5, struct.pack('<IIII', addr, size, 0, 0))
+
+    def changebaud(self, baud):
+        print "Changing baud rate to %d" % baud
+        self.command(self.ESP_CHANGE_BAUDRATE, struct.pack('<II', baud, 0))
+        print "Changed."
+        time.sleep(0.05)  # get rid of crap sent during baud rate change
+        self._port.flushInput()
+        self._port.baudrate = baud
+
+    def flash_spi_attach_req(self,ucIsHspi,ucIsLegacy):
+        """Send SPI attach command
+
+        Internal Espressif function. Deprecate?
+        """
+        print "SEND ESP SPI ATTACH CMD"
+        # last 3 bytes in ESP_SPI_ATTACH_REQ argument are reserved values
+        arg = struct.pack('<IBBBB', ucIsHspi, ucIsLegacy, 0, 0, 0)
+        self.check_command("configure SPI Flash attachment", ESP32ROM.ESP_SPI_ATTACH_REQ,
+                           arg)
+
+    def flash_spi_param_set(self):
+        """Set the flash params for ESP booter
+
+        I think this means writing a "flash_chip" type structure to RAM, so the ESP32 knows we have a larger flash size.
+        """
+        # FOR ESP32, SET FLASH INFO FOR ROM CODE, DEFAULT IS 16Mbits, WE NEED TO RE-SET IT TO A BIGGER SIZE.
+        print("SET FLASH PARAMS")
+        fl_id = 0
+        total_size = (128 / 8) * 1024 * 1024
+        block_size = 64 * 1024
+        sector_size = 4 * 1024
+        page_size = 256
+        status_mask = 0xffff
+
+        err = self.command(ESP32ROM.ESP_SPI_FLASH_SET,
+                           struct.pack('<IIIIII', fl_id, total_size, block_size, sector_size, page_size, status_mask))[1]
+        if err:  # Should be checking one part of this tuple or the other, I think
+            raise FatalError.WithResult('Failed to config flash', err)
+
+
+class ESPBOOTLOADER(object):
+    """ These are constants related to software ESP bootloader, working with 'v2' image files """
+
+    # First byte of the "v2" application image
+    IMAGE_V2_MAGIC = 0xea
+
+    # First 'segment' value in a "v2" application image, appears to be a constant version value?
+    IMAGE_V2_SEGMENT = 4
+
+
+def LoadFirmwareImage(chip, filename):
+    """ Load a firmware image. Can be for ESP8266 or ESP32. ESP8266 images will be examined to determine if they are
+        original ROM firmware images (ESPFirmwareImage) or "v2" OTA bootloader images.
+
+        Returns a BaseFirmwareImage subclass, either ESPFirmwareImage (v1) or OTAFirmwareImage (v2).
+    """
+    with open(filename, 'rb') as f:
+        if chip == 'esp32':
+            return ESP32FirmwareImage(f)
+        else:  # Otherwise, ESP8266 so look at magic to determine the image type
+            magic = ord(f.read(1))
+            f.seek(0)
+            if magic == ESPROM.ESP_IMAGE_MAGIC:
+                return ESPFirmwareImage(f)
+            elif magic == ESPBOOTLOADER.IMAGE_V2_MAGIC:
+                return OTAFirmwareImage(f)
+            else:
+                raise FatalError("Invalid image magic number: %d" % magic)
+
+
+class ImageSegment(object):
+    """ Wrapper class for a segment in an ESP image
+    (very similar to a section in an ELFImage also) """
+    def __init__(self, addr, data, file_offs=None):
+        self.addr = addr
+        # pad all ImageSegments to at least 4 bytes length
+        pad_mod = len(data) % 4
+        if pad_mod != 0:
+            data += "\x00" * (4 - pad_mod)
+        self.data = data
+        self.file_offs = file_offs
+
+    def copy_with_new_addr(self, new_addr):
+        """ Return a new ImageSegment with same data, but mapped at
+        a new address. """
+        return ImageSegment(new_addr, self.data, 0)
+
+    def __repr__(self):
+        r = "len 0x%05x load 0x%08x" % (len(self.data), self.addr)
+        if self.file_offs is not None:
+            r += " file_offs 0x%08x" % (self.file_offs)
+        return r
+
+class ELFSection(ImageSegment):
+    """ Wrapper class for a section in an ELF image, has a section
+    name as well as the common properties of an ImageSegment. """
+    def __init__(self, name, addr, data):
+        super(ELFSection, self).__init__(addr, data)
+        self.name = name
+
+    def __repr__(self):
+        return "%s %s" % (self.name, super(ELFSection, self).__repr__())
+
+
+class BaseFirmwareImage(object):
+    SEG_HEADER_LEN = 8
+
+    """ Base class with common firmware image functions """
+    def __init__(self):
+        self.segments = []
+        self.entrypoint = 0
+
+    def load_common_header(self, load_file, expected_magic):
+            (magic, segments, self.flash_mode, self.flash_size_freq, self.entrypoint) = struct.unpack('<BBBBI', load_file.read(8))
+
+            if magic != expected_magic or segments > 16:
+                raise FatalError('Invalid firmware image magic=%d segments=%d' % (magic, segments))
+            return segments
+
+    def load_segment(self, f, is_irom_segment=False):
+        """ Load the next segment from the image file """
+        file_offs = f.tell()
+        (offset, size) = struct.unpack('<II', f.read(8))
+        if not is_irom_segment:
+            if offset > 0x40200000 or offset < 0x3ffe0000 or size > 65536:
+                print('WARNING: Suspicious segment 0x%x, length %d' % (offset, size))
+        segment_data = f.read(size)
+        if len(segment_data) < size:
+            raise FatalError('End of file reading segment 0x%x, length %d (actual length %d)' % (offset, size, len(segment_data)))
+        segment = ImageSegment(offset, segment_data, file_offs)
+        self.segments.append(segment)
+        return segment
+
+    def save_segment(self, f, segment, checksum=None):
+        """ Save the next segment to the image file, return next checksum value if provided """
+        f.write(struct.pack('<II', segment.addr, len(segment.data)))
+        f.write(segment.data)
+        if checksum is not None:
+            return ESPROM.checksum(segment.data, checksum)
+
+    def read_checksum(self, f):
+        """ Return ESPROM checksum from end of just-read image """
+        # Skip the padding. The checksum is stored in the last byte so that the
+        # file is a multiple of 16 bytes.
+        align_file_position(f, 16)
+        return ord(f.read(1))
+
+    def append_checksum(self, f, checksum):
+        """ Append ESPROM checksum to the just-written image """
+        align_file_position(f, 16)
+        f.write(struct.pack('B', checksum))
+
+    def write_common_header(self, f, segments):
+        f.write(struct.pack('<BBBBI', ESPROM.ESP_IMAGE_MAGIC, len(segments),
+                            self.flash_mode, self.flash_size_freq, self.entrypoint))
+
+    def is_irom_addr(self, addr):
+        """ Returns True if an address starts in the irom region.
+        Valid for ESP8266 only.
+        """
+        return ESPROM.IROM_MAP_START <= addr < ESPROM.IROM_MAP_END
+
+    def get_irom_segment(self):
+            irom_segments = [s for s in self.segments if self.is_irom_addr(s.addr)]
+            if len(irom_segments) > 0:
+                if len(irom_segments) != 1:
+                    raise FatalError('Found %d segments that could be irom0. Bad ELF file?' % len(irom_segments))
+                return irom_segments[0]
+            return None
+
+    def get_non_irom_segments(self):
+        irom_segment = self.get_irom_segment()
+        return [s for s in self.segments if s != irom_segment]
+
+
+class ESPFirmwareImage(BaseFirmwareImage):
+    """ 'Version 1' firmware image, segments loaded directly by the ROM bootloader. """
+    def __init__(self, load_file=None):
+        super(ESPFirmwareImage, self).__init__()
+        self.flash_mode = 0
+        self.flash_size_freq = 0
+        self.version = 1
+
+        if load_file is not None:
+            segments = self.load_common_header(load_file, ESPROM.ESP_IMAGE_MAGIC)
+
+            for _ in xrange(segments):
+                self.load_segment(load_file)
+            self.checksum = self.read_checksum(load_file)
+
+    def default_output_name(self, input_file):
+        """ Derive a default output name from the ELF name. """
+        return input_file + '-'
+
+    def save(self, basename):
+        """ Save a set of V1 images for flashing. Parameter is a base filename. """
+        # IROM data goes in its own plain binary file
+        irom_segment = self.get_irom_segment()
+        if irom_segment is not None:
+            with open("%s0x%05x.bin" % (basename, irom_segment.addr), "wb") as f:
+                f.write(irom_segment.data)
+
+        # everything but IROM goes at 0x00000 in an image file
+        normal_segments = self.get_non_irom_segments()
+        with open("%s0x00000.bin" % basename, 'wb') as f:
+            self.write_common_header(f, normal_segments)
+            checksum = ESPROM.ESP_CHECKSUM_MAGIC
+            for segment in self.segments:
+                checksum = self.save_segment(f, segment, checksum)
+            self.append_checksum(f, checksum)
+
+
+class OTAFirmwareImage(BaseFirmwareImage):
+    """ 'Version 2' firmware image, segments loaded by software bootloader stub
+        (ie Espressif bootloader or rboot)
+    """
+    def __init__(self, load_file=None):
+        super(OTAFirmwareImage, self).__init__()
+        self.version = 2
+        if load_file is not None:
+            segments = self.load_common_header(load_file, ESPBOOTLOADER.IMAGE_V2_MAGIC)
+            if segments != ESPBOOTLOADER.IMAGE_V2_SEGMENT:
+                # segment count is not really segment count here, but we expect to see '4'
+                print 'Warning: V2 header has unexpected "segment" count %d (usually 4)' % segments
+
+            # irom segment comes before the second header
+            #
+            # the file is saved in the image with a zero load address
+            # in the header, so we need to calculate a load address
+            irom_offs = load_file.tell()
+            irom_segment = self.load_segment(load_file, True)
+            irom_segment.addr = irom_offs + ESPROM.IROM_MAP_START
+
+            first_flash_mode = self.flash_mode
+            first_flash_size_freq = self.flash_size_freq
+            first_entrypoint = self.entrypoint
+            # load the second header
+            self.load_common_header(load_file, ESPROM.ESP_IMAGE_MAGIC)
+            (magic, segments, self.flash_mode, self.flash_size_freq, self.entrypoint) = struct.unpack('<BBBBI', load_file.read(8))
+
+            if first_flash_mode != self.flash_mode:
+                print('WARNING: Flash mode value in first header (0x%02x) disagrees with second (0x%02x). Using second value.'
+                      % (first_flash_mode, self.flash_mode))
+            if first_flash_size_freq != self.flash_size_freq:
+                print('WARNING: Flash size/freq value in first header (0x%02x) disagrees with second (0x%02x). Using second value.'
+                      % (first_flash_size_freq, self.flash_size_freq))
+            if first_entrypoint != self.entrypoint:
+                print('WARNING: Entrypoint address in first header (0x%08x) disagrees with second header (0x%08x). Using second value.'
+                      % (first_entrypoint, self.entrypoint))
+
+            # load all the usual segments
+            for _ in xrange(segments):
+                self.load_segment(load_file)
+            self.checksum = self.read_checksum(load_file)
+
+    def default_output_name(self, input_file):
+        """ Derive a default output name from the ELF name. """
+        irom_segment = self.get_irom_segment()
+        if irom_segment is not None:
+            irom_offs = irom_segment.addr - ESPROM.IROM_MAP_START
+        else:
+            irom_offs = 0
+        return "%s-0x%05x.bin" % (os.path.splitext(input_file)[0],
+                                  irom_offs & ~(ESPROM.ESP_FLASH_SECTOR - 1))
+
+    def save(self, filename):
+        with open(filename, 'wb') as f:
+            # Save first header for irom0 segment
+            f.write(struct.pack('<BBBBI', ESPBOOTLOADER.IMAGE_V2_MAGIC, ESPBOOTLOADER.IMAGE_V2_SEGMENT,
+                                self.flash_mode, self.flash_size_freq, self.entrypoint))
+
+            irom_segment = self.get_irom_segment()
+            if irom_segment is not None:
+                # save irom0 segment, make sure it has load addr 0 in the file
+                irom_segment = irom_segment.copy_with_new_addr(0)
+                self.save_segment(f, irom_segment)
+
+            # second header, matches V1 header and contains loadable segments
+            normal_segments = self.get_non_irom_segments()
+            self.write_common_header(f, normal_segments)
+            checksum = ESPROM.ESP_CHECKSUM_MAGIC
+            for segment in normal_segments:
+                checksum = self.save_segment(f, segment, checksum)
+            self.append_checksum(f, checksum)
+
+
+class ESP32FirmwareImage(BaseFirmwareImage):
+    """ ESP32 firmware image is very similar to V1 ESP8266 image,
+    except with an additional 16 byte reserved header at top of image,
+    and because of new flash mapping capabilities the flash-mapped regions
+    can be placed in the normal image (just @ 64kB padded offsets).
+    """
+    def __init__(self, load_file=None):
+        super(ESP32FirmwareImage, self).__init__()
+        self.flash_mode = 0
+        self.flash_size_freq = 0
+        self.version = 1
+        self.additional_header = '\x00' * 16
+
+        if load_file is not None:
+            segments = self.load_common_header(load_file, ESPROM.ESP_IMAGE_MAGIC)
+            self.additional_header = load_file.read(16)
+
+            for i in xrange(segments):
+                self.load_segment(load_file)
+            self.checksum = self.read_checksum(load_file)
+
+    def is_flash_addr(self, addr):
+        return (ESP32ROM.IROM_MAP_START <= addr < ESP32ROM.IROM_MAP_END) \
+            or (ESP32ROM.DROM_MAP_START <= addr < ESP32ROM.DROM_MAP_END)
+
+    def default_output_name(self, input_file):
+        """ Derive a default output name from the ELF name. """
+        return "%s.bin" % (os.path.splitext(input_file)[0])
+
+    def save(self, filename):
+        padding_segments = 0
+        with open(filename, 'wb') as f:
+            self.write_common_header(f, self.segments)
+            f.write(self.additional_header)
+
+            checksum = ESPROM.ESP_CHECKSUM_MAGIC
+            last_addr = None
+            for segment in sorted(self.segments, key=lambda s:s.addr):
+                #print("Writing %s file @ 0x%x" % (segment, f.tell()))
+
+                # IROM/DROM segment flash mappings need to align on
+                # 64kB boundaries.
+                #
+                # TODO: intelligently order segments to reduce wastage
+                # by squeezing smaller DRAM/IRAM segments into the
+                # 64kB padding space.
+                IROM_ALIGN = 65536
+
+                # check for multiple ELF sections that live in the same flash mapping region.
+                # this is usually a sign of a broken linker script, but if you have a legitimate
+                # use case then let us know (we can merge segments here, but as a rule you probably
+                # want to merge them in your linker script.)
+                if last_addr is not None and self.is_flash_addr(last_addr) \
+                   and self.is_flash_addr(segment.addr) and segment.addr // IROM_ALIGN == last_addr // IROM_ALIGN:
+                    raise FatalError(("Segment loaded at 0x%08x lands in same 64KB flash mapping as segment loaded at 0x%08x. "+
+                                     "Can't generate binary. Suggest changing linker script or ELF to merge sections.") %
+                                     (segment.addr, last_addr))
+                last_addr = segment.addr
+
+                if self.is_flash_addr(segment.addr):
+                    #print("Padding from offset %08x" % f.tell())
+                    # Actual alignment required for the segment header: positioned so that
+                    # after we write the next 8 byte header, file_offs % IROM_ALIGN == segment.addr % IROM_ALIGN
+                    #
+                    # (this is because the segment's vaddr may not be IROM_ALIGNed, more likely is aligned
+                    # IROM_ALIGN+0x10 to account for longest possible header.
+                    align_past = (segment.addr % IROM_ALIGN) - self.SEG_HEADER_LEN
+                    #print "segment starts 0x%x so aligning header at +0x%x" % (segment.addr, align_past)
+                    assert (align_past + self.SEG_HEADER_LEN) == (segment.addr % IROM_ALIGN)
+
+                    # subtract SEG_HEADER_LEN a second time, as the padding block has a header as well
+                    pad_len = ( IROM_ALIGN - (f.tell() % IROM_ALIGN) ) + align_past - self.SEG_HEADER_LEN
+                    if pad_len < 0:
+                        pad_len += IROM_ALIGN
+                    if pad_len > 0:
+                        #print("Calculated pad length %08x to place next header @ %08x" % (pad_len, f.tell()+pad_len))
+                        null = ImageSegment(0, '\x00' * pad_len, f.tell())
+                        checksum = self.save_segment(f, null, checksum)
+                        #print("After padding, at file offset %08x" % f.tell())
+                        padding_segments += 1
+                    #print "Comparing file offs %x (data @ %x) with segment load addr %x" % (f.tell(), f.tell() + 8, segment.addr)
+                    # verify that after the 8 byte header is added, were are at the correct offset relative to the segment's vaddr
+                    assert (f.tell() + 8) % IROM_ALIGN == segment.addr % IROM_ALIGN
+                checksum = self.save_segment(f, segment, checksum)
+            self.append_checksum(f, checksum)
+            # kinda hacky: go back to the initial header and write the new segment count
+            # that includes padding segments. Luckily(?) this header is not checksummed
+            f.seek(1)
+            f.write(chr(len(self.segments) + padding_segments))
+
+
+class ELFFile(object):
+    SEC_TYPE_PROGBITS = 0x01
+    SEC_TYPE_STRTAB = 0x03
+
+    def __init__(self, name):
+        # Load sections from the ELF file
+        self.name = name
+        with open(self.name, 'rb') as f:
+            self._read_elf_file(f)
+
+    def _read_elf_file(self, f):
+        # read the ELF file header
+        LEN_FILE_HEADER = 0x34
+        try:
+            (ident,_type,machine,_version,
+             self.entrypoint,_phoff,shoff,_flags,
+             _ehsize, _phentsize,_phnum,_shentsize,
+             _shnum,shstrndx) = struct.unpack("<16sHHLLLLLHHHHHH", f.read(LEN_FILE_HEADER))
+        except struct.error as e:
+            raise FatalError("Failed to read a valid ELF header from %s: %s" % (self.name, e))
+
+        if ident[0] != '\x7f' or ident[1:4] != 'ELF':
+            raise FatalError("%s has invalid ELF magic header" % self.name)
+        if machine != 0x5e:
+            raise FatalError("%s does not appear to be an Xtensa ELF file. e_machine=%04x" % (self.name, machine))
+        self._read_sections(f, shoff, shstrndx)
+
+    def _read_sections(self, f, section_header_offs, shstrndx):
+        f.seek(section_header_offs)
+        section_header = f.read()
+        LEN_SEC_HEADER = 0x28
+        if len(section_header) == 0:
+            raise FatalError("No section header found at offset %04x in ELF file." % section_header_offs)
+        if len(section_header) % LEN_SEC_HEADER != 0:
+            print 'WARNING: Unexpected ELF section header length %04x is not mod-%02x' % (len(section_header),LEN_SEC_HEADER)
+
+        # walk through the section header and extract all sections
+        section_header_offsets = range(0, len(section_header), LEN_SEC_HEADER)
+
+        def read_section_header(offs):
+            name_offs,sec_type,_flags,lma,sec_offs,size = struct.unpack_from("<LLLLLL", section_header[offs:])
+            return (name_offs, sec_type, lma, size, sec_offs)
+        all_sections = [read_section_header(offs) for offs in section_header_offsets]
+        prog_sections = [s for s in all_sections if s[1] == ELFFile.SEC_TYPE_PROGBITS]
+
+        # search for the string table section
+        if not shstrndx * LEN_SEC_HEADER in section_header_offsets:
+            raise FatalError("ELF file has no STRTAB section at shstrndx %d" % shstrndx)
+        _,sec_type,_,sec_size,sec_offs = read_section_header(shstrndx * LEN_SEC_HEADER)
+        if sec_type != ELFFile.SEC_TYPE_STRTAB:
+            print 'WARNING: ELF file has incorrect STRTAB section type 0x%02x' % sec_type
+        f.seek(sec_offs)
+        string_table = f.read(sec_size)
+
+        # build the real list of ELFSections by reading the actual section names from the
+        # string table section, and actual data for each section from the ELF file itself
+        def lookup_string(offs):
+            raw = string_table[offs:]
+            return raw[:raw.index('\x00')]
+
+        def read_data(offs,size):
+            f.seek(offs)
+            return f.read(size)
+
+        prog_sections = [ELFSection(lookup_string(n_offs), lma, read_data(offs, size)) for (n_offs, _type, lma, size, offs) in prog_sections
+                         if lma != 0]
+        self.sections = prog_sections
+
+
+class CesantaFlasher(object):
+
+    # From stub_flasher.h
+    CMD_FLASH_WRITE = 1
+    CMD_FLASH_READ = 2
+    CMD_FLASH_DIGEST = 3
+    CMD_FLASH_ERASE_CHIP = 5
+    CMD_BOOT_FW = 6
+
+    def __init__(self, esp, baud_rate=0):
+        print 'Running Cesanta flasher stub...'
+        if baud_rate <= ESPROM.ESP_ROM_BAUD:  # don't change baud rates if we already synced at that rate
+            baud_rate = 0
+        self._esp = esp
+        esp.run_stub(json.loads(_CESANTA_FLASHER_STUB), [baud_rate])
+        if baud_rate > 0:
+            esp._port.baudrate = baud_rate
+        # Read the greeting.
+        p = esp.read()
+        if p != 'OHAI':
+            raise FatalError('Failed to connect to the flasher (got %s)' % hexify(p))
+
+    def flash_write(self, addr, data, show_progress=False):
+        assert addr % self._esp.ESP_FLASH_SECTOR == 0, 'Address must be sector-aligned'
+        assert len(data) % self._esp.ESP_FLASH_SECTOR == 0, 'Length must be sector-aligned'
+        sys.stdout.write('Writing %d @ 0x%x... ' % (len(data), addr))
+        sys.stdout.flush()
+        self._esp.write(struct.pack('<B', self.CMD_FLASH_WRITE))
+        self._esp.write(struct.pack('<III', addr, len(data), 1))
+        num_sent, num_written = 0, 0
+        while num_written < len(data):
+            p = self._esp.read()
+            if len(p) == 4:
+                num_written = struct.unpack('<I', p)[0]
+            elif len(p) == 1:
+                status_code = struct.unpack('<B', p)[0]
+                raise FatalError('Write failure, status: %x' % status_code)
+            else:
+                raise FatalError('Unexpected packet while writing: %s' % hexify(p))
+            if show_progress:
+                progress = '%d (%d %%)' % (num_written, num_written * 100.0 / len(data))
+                sys.stdout.write(progress + '\b' * len(progress))
+                sys.stdout.flush()
+            while num_sent - num_written < 5120:
+                self._esp._port.write(data[num_sent:num_sent + 1024])
+                num_sent += 1024
+        p = self._esp.read()
+        if len(p) != 16:
+            raise FatalError('Expected digest, got: %s' % hexify(p))
+        digest = hexify(p).upper()
+        expected_digest = hashlib.md5(data).hexdigest().upper()
+        print
+        if digest != expected_digest:
+            raise FatalError('Digest mismatch: expected %s, got %s' % (expected_digest, digest))
+        p = self._esp.read()
+        if len(p) != 1:
+            raise FatalError('Expected status, got: %s' % hexify(p))
+        status_code = struct.unpack('<B', p)[0]
+        if status_code != 0:
+            raise FatalError('Write failure, status: %x' % status_code)
+
+    def flash_read(self, addr, length, show_progress=False):
+        sys.stdout.write('Reading %d @ 0x%x... ' % (length, addr))
+        sys.stdout.flush()
+        self._esp.write(struct.pack('<B', self.CMD_FLASH_READ))
+        # USB may not be able to keep up with the read rate, especially at
+        # higher speeds. Since we don't have flow control, this will result in
+        # data loss. Hence, we use small packet size and only allow small
+        # number of bytes in flight, which we can reasonably expect to fit in
+        # the on-chip FIFO. max_in_flight = 64 works for CH340G, other chips may
+        # have longer FIFOs and could benefit from increasing max_in_flight.
+        self._esp.write(struct.pack('<IIII', addr, length, 32, 64))
+        data = ''
+        while True:
+            p = self._esp.read()
+            data += p
+            self._esp.write(struct.pack('<I', len(data)))
+            if show_progress and (len(data) % 1024 == 0 or len(data) == length):
+                progress = '%d (%d %%)' % (len(data), len(data) * 100.0 / length)
+                sys.stdout.write(progress + '\b' * len(progress))
+                sys.stdout.flush()
+            if len(data) == length:
+                break
+            if len(data) > length:
+                raise FatalError('Read more than expected')
+        p = self._esp.read()
+        if len(p) != 16:
+            raise FatalError('Expected digest, got: %s' % hexify(p))
+        expected_digest = hexify(p).upper()
+        digest = hashlib.md5(data).hexdigest().upper()
+        print
+        if digest != expected_digest:
+            raise FatalError('Digest mismatch: expected %s, got %s' % (expected_digest, digest))
+        p = self._esp.read()
+        if len(p) != 1:
+            raise FatalError('Expected status, got: %s' % hexify(p))
+        status_code = struct.unpack('<B', p)[0]
+        if status_code != 0:
+            raise FatalError('Write failure, status: %x' % status_code)
+        return data
+
+    def flash_digest(self, addr, length, digest_block_size=0):
+        self._esp.write(struct.pack('<B', self.CMD_FLASH_DIGEST))
+        self._esp.write(struct.pack('<III', addr, length, digest_block_size))
+        digests = []
+        while True:
+            p = self._esp.read()
+            if len(p) == 16:
+                digests.append(p)
+            elif len(p) == 1:
+                status_code = struct.unpack('<B', p)[0]
+                if status_code != 0:
+                    raise FatalError('Write failure, status: %x' % status_code)
+                break
+            else:
+                raise FatalError('Unexpected packet: %s' % hexify(p))
+        return digests[-1], digests[:-1]
+
+    def boot_fw(self):
+        self._esp.write(struct.pack('<B', self.CMD_BOOT_FW))
+        p = self._esp.read()
+        if len(p) != 1:
+            raise FatalError('Expected status, got: %s' % hexify(p))
+        status_code = struct.unpack('<B', p)[0]
+        if status_code != 0:
+            raise FatalError('Boot failure, status: %x' % status_code)
+
+    def flash_erase(self):
+        self._esp.write(struct.pack('<B', self.CMD_FLASH_ERASE_CHIP))
+        p = self._esp.read()
+        if len(p) != 1:
+            raise FatalError('Expected status, got: %s' % hexify(p))
+        status_code = struct.unpack('<B', p)[0]
+        if status_code != 0:
+            raise FatalError('Chip erase failure, status: %x' % status_code)
+
+
+def slip_reader(port):
+    """Generator to read SLIP packets from a serial port.
+    Yields one full SLIP packet at a time, raises exception on timeout or invalid data.
+
+    Designed to avoid too many calls to serial.read(1), which can bog
+    down on slow systems.
+    """
+    partial_packet = None
+    in_escape = False
+    while True:
+        waiting = port.inWaiting()
+        read_bytes = port.read(1 if waiting == 0 else waiting)
+        if read_bytes == '':
+            raise FatalError("Timed out waiting for packet %s" % ("header" if partial_packet is None else "content"))
+
+        for b in read_bytes:
+            if partial_packet is None:  # waiting for packet header
+                if b == '\xc0':
+                    partial_packet = ""
+                else:
+                    raise FatalError('Invalid head of packet (%r)' % b)
+            elif in_escape:  # part-way through escape sequence
+                in_escape = False
+                if b == '\xdc':
+                    partial_packet += '\xc0'
+                elif b == '\xdd':
+                    partial_packet += '\xdb'
+                else:
+                    raise FatalError('Invalid SLIP escape (%r%r)' % ('\xdb', b))
+            elif b == '\xdb':  # start of escape sequence
+                in_escape = True
+            elif b == '\xc0':  # end of packet
+                yield partial_packet
+                partial_packet = None
+            else:  # normal byte in packet
+                partial_packet += b
+
+
+def arg_auto_int(x):
+    return int(x, 0)
+
+
+def div_roundup(a, b):
+    """ Return a/b rounded up to nearest integer,
+    equivalent result to int(math.ceil(float(int(a)) / float(int(b))), only
+    without possible floating point accuracy errors.
+    """
+    return (int(a) + int(b) - 1) / int(b)
+
+
+def binutils_safe_path(p):
+    """Returns a 'safe' version of path 'p' to pass to binutils
+
+    Only does anything under Cygwin Python, where cygwin paths need to
+    be translated to Windows paths if the binutils wasn't compiled
+    using Cygwin (should also work with binutils compiled using
+    Cygwin, see #73.)
+    """
+    if sys.platform == "cygwin":
+        try:
+            return subprocess.check_output(["cygpath", "-w", p]).rstrip('\n')
+        except subprocess.CalledProcessError:
+            print "WARNING: Failed to call cygpath to sanitise Cygwin path."
+    return p
+
+
+def align_file_position(f, size):
+    """ Align the position in the file to the next block of specified size """
+    align = (size - 1) - (f.tell() % size)
+    f.seek(align, 1)
+
+
+def hexify(s):
+    return ''.join('%02X' % ord(c) for c in s)
+
+
+def unhexify(hs):
+    s = ''
+    for i in range(0, len(hs) - 1, 2):
+        s += chr(int(hs[i] + hs[i + 1], 16))
+    return s
+
+
+class FatalError(RuntimeError):
+    """
+    Wrapper class for runtime errors that aren't caused by internal bugs, but by
+    ESP8266 responses or input content.
+    """
+    def __init__(self, message):
+        RuntimeError.__init__(self, message)
+
+    @staticmethod
+    def WithResult(message, result):
+        """
+        Return a fatal error object that appends the hex values of
+        'result' as a string formatted argument.
+        """
+        message += " (result was %s)" % ", ".join(hex(ord(x)) for x in result)
+        return FatalError(message)
+
+
+# "Operation" commands, executable at command line. One function each
+#
+# Each function takes either two args (<ESPROM instance>, <args>) or a single <args>
+# argument.
+
+def load_ram(esp, args):
+    image = LoadFirmwareImage(esp, args.filename)
+
+    print 'RAM boot...'
+    for (offset, size, data) in image.segments:
+        print 'Downloading %d bytes at %08x...' % (size, offset),
+        sys.stdout.flush()
+        esp.mem_begin(size, div_roundup(size, esp.ESP_RAM_BLOCK), esp.ESP_RAM_BLOCK, offset)
+
+        seq = 0
+        while len(data) > 0:
+            esp.mem_block(data[0:esp.ESP_RAM_BLOCK], seq)
+            data = data[esp.ESP_RAM_BLOCK:]
+            seq += 1
+        print 'done!'
+
+    print 'All segments done, executing at %08x' % image.entrypoint
+    esp.mem_finish(image.entrypoint)
+
+
+def read_mem(esp, args):
+    print '0x%08x = 0x%08x' % (args.address, esp.read_reg(args.address))
+
+
+def write_mem(esp, args):
+    esp.write_reg(args.address, args.value, args.mask, 0)
+    print 'Wrote %08x, mask %08x to %08x' % (args.value, args.mask, args.address)
+
+
+def dump_mem(esp, args):
+    f = file(args.filename, 'wb')
+    for i in xrange(args.size / 4):
+        d = esp.read_reg(args.address + (i * 4))
+        f.write(struct.pack('<I', d))
+        if f.tell() % 1024 == 0:
+            print '\r%d bytes read... (%d %%)' % (f.tell(),
+                                                  f.tell() * 100 / args.size),
+        sys.stdout.flush()
+    print 'Done!'
+
+
+def write_flash(esp, args):
+    # This splitting of functionality will go away eventually,
+    # but for now this is the easiest way :|
+    if isinstance(esp, ESP32ROM):
+        write_flash_no_stub(esp, args)
+    else:
+        write_flash_via_stub(esp, args)
+
+
+def write_flash_via_stub(esp, args):
+    flash_mode = {'qio':0, 'qout':1, 'dio':2, 'dout': 3}[args.flash_mode]
+    flash_size_freq = esp.parse_flash_size_arg(args.flash_size)
+    flash_size_freq += {'40m':0, '26m':1, '20m':2, '80m': 0xf}[args.flash_freq]
+    flash_params = struct.pack('BB', flash_mode, flash_size_freq)
+
+    flasher = CesantaFlasher(esp, args.baud)
+
+    for address, argfile in args.addr_filename:
+        image = argfile.read()
+        argfile.seek(0)  # rewind in case we need it again
+        # Fix sflash config data.
+        if address == 0 and image[0] == '\xe9':
+            print 'Flash params set to 0x%02x%02x' % (flash_mode, flash_size_freq)
+            image = image[0:2] + flash_params + image[4:]
+        # Pad to sector size, which is the minimum unit of writing (erasing really).
+        if len(image) % esp.ESP_FLASH_SECTOR != 0:
+            image += '\xff' * (esp.ESP_FLASH_SECTOR - (len(image) % esp.ESP_FLASH_SECTOR))
+        t = time.time()
+        flasher.flash_write(address, image, not args.no_progress)
+        t = time.time() - t
+        print ('\rWrote %d bytes at 0x%x in %.1f seconds (%.1f kbit/s)...'
+               % (len(image), address, t, len(image) / t * 8 / 1000))
+    print 'Leaving...'
+    if args.verify:
+        print 'Verifying just-written flash...'
+        _verify_flash(flasher, args, flash_params)
+    flasher.boot_fw()
+
+
+def write_flash_no_stub(esp, args):
+    """Write flash directly via the bootloader, no stub
+
+    The existence of this function is a hack. Before this is done,
+    the stub needs to speak the ESP bootloader protocol so
+    we can roll all this code up into the write_flash().
+
+    This function also includes some support for Espressif internal
+    testing functions that probably aren't useful for most people, and
+    need to go live somewhere... maybe a generic "bootloader command"
+    function or something?
+
+    """
+    flash_mode = {'qio':0, 'qout':1, 'dio':2, 'dout': 3}[args.flash_mode]
+    flash_size_freq = esp.parse_flash_size_arg(args.flash_size)
+    flash_size_freq += {'40m':0, '26m':1, '20m':2, '80m': 0xf}[args.flash_freq]
+    flash_info = struct.pack('BB', flash_mode, flash_size_freq)
+
+    print "\n\n"
+    print "********************************"
+    uc_is_hspi = int(args.ucIsHspi,16)
+    uc_is_legacy = int(args.ucIsLegacy,16) & 0xff
+    print "IS HSPI: 0x%08x" % (uc_is_hspi),type(uc_is_hspi)
+    print "--------------------------"
+    print "IS LEGACY: 0x%02x" % uc_is_legacy,type(uc_is_legacy)
+    print "*********************************"
+    print "SENDING SPI ATTACH COMMAND"
+    print "--------------"
+    esp.flash_spi_attach_req(uc_is_hspi,uc_is_legacy)
+    print "START DOWNLOADING..."
+
+    for address, argfile in args.addr_filename:
+        print 'Erasing flash...'
+        if args.compress:
+            uncimage = argfile.read()
+            calcmd5 = hashlib.md5(uncimage).hexdigest()
+            uncsize = len(uncimage)
+            image = zlib.compress(uncimage, 9)
+            blocks = div_roundup(len(image), esp.ESP_FLASH_BLOCK)
+            esp.flash_defl_begin(len(uncimage),len(image), address)
+        else:
+            image = argfile.read()
+            calcmd5 = hashlib.md5(image).hexdigest()
+            uncsize = len(image)
+            blocks = div_roundup(len(image), esp.ESP_FLASH_BLOCK)
+            esp.flash_begin(blocks * esp.ESP_FLASH_BLOCK, address)
+        argfile.seek(0)  # in case we need it again
+        seq = 0
+        written = 0
+        t = time.time()
+        header_block = None
+        while len(image) > 0:
+            print '\rWriting at 0x%08x... (%d %%)' % (address + seq * esp.ESP_FLASH_BLOCK, 100 * (seq + 1) / blocks),
+            sys.stdout.flush()
+            block = image[0:esp.ESP_FLASH_BLOCK]
+            if args.compress:
+                esp.flash_defl_block(block, seq)
+            else:
+                # Pad the last block
+                block = block + '\xff' * (esp.ESP_FLASH_BLOCK - len(block))
+                # Fix sflash config data
+                if address == 0 and seq == 0 and block[0] == '\xe9':
+                    block = block[0:2] + flash_info + block[4:]
+                    header_block = block
+                esp.flash_block(block, seq)
+            image = image[esp.ESP_FLASH_BLOCK:]
+            seq += 1
+            written += len(block)
+        t = time.time() - t
+        print '\rWrote %d bytes at 0x%08x in %.1f seconds (%.1f kbit/s)...' % (written, address, t, written / t * 8 / 1000)
+        res = esp.flash_md5sum(address, uncsize)
+        if res != calcmd5:
+            print 'File  md5: %s' % calcmd5
+            print 'Flash md5: %s' % res
+            raise FatalError("MD5 of file does not match data in flash!")
+        else:
+            print 'Hash of data verified.'
+    print '\nLeaving...'
+    if args.flash_mode == 'dio':
+        esp.flash_unlock_dio()
+    else:
+        esp.flash_begin(0, 0)
+        if args.compress:
+            esp.flash_defl_finish(False)
+        else:
+            esp.flash_finish(False)
+    if args.verify:
+        print 'Verifying just-written flash...'
+        verify_flash(esp, args, header_block)
+
+
+def image_info(args):
+    image = LoadFirmwareImage(args.chip, args.filename)
+    print('Image version: %d' % image.version)
+    print('Entry point: %08x' % image.entrypoint) if image.entrypoint != 0 else 'Entry point not set'
+    print '%d segments' % len(image.segments)
+    print
+    checksum = ESPROM.ESP_CHECKSUM_MAGIC
+    idx = 0
+    for seg in image.segments:
+        idx += 1
+        print 'Segment %d: %r' % (idx, seg)
+        checksum = ESPROM.checksum(seg.data, checksum)
+    print
+    print 'Checksum: %02x (%s)' % (image.checksum, 'valid' if image.checksum == checksum else 'invalid!')
+
+
+def make_image(args):
+    image = ESPFirmwareImage()
+    if len(args.segfile) == 0:
+        raise FatalError('No segments specified')
+    if len(args.segfile) != len(args.segaddr):
+        raise FatalError('Number of specified files does not match number of specified addresses')
+    for (seg, addr) in zip(args.segfile, args.segaddr):
+        data = file(seg, 'rb').read()
+        image.segments.append(ImageSegment(addr, data))
+    image.entrypoint = args.entrypoint
+    image.save(args.output)
+
+
+def elf2image(args):
+    e = ELFFile(args.input)
+    if args.chip == 'auto':  # Default to ESP8266 for backwards compatibility
+        print "Creating image for ESP8266..."
+        args.chip == 'esp8266'
+
+    if args.chip == 'esp31':
+        raise FatalError("No elf2image support for ESP31. Use gen_appimage.py from the ESP31 SDK")
+    elif args.chip == 'esp32':
+        image = ESP32FirmwareImage()
+    elif args.version == '1':  # ESP8266
+        image = ESPFirmwareImage()
+    else:
+        image = OTAFirmwareImage()
+    image.entrypoint = e.entrypoint
+    image.segments = e.sections  # ELFSection is a subclass of ImageSegment
+    image.flash_mode = {'qio':0, 'qout':1, 'dio':2, 'dout': 3}[args.flash_mode]
+    image.flash_size_freq = ESP8266ROM.FLASH_SIZES[args.flash_size]
+    image.flash_size_freq += {'40m':0, '26m':1, '20m':2, '80m': 0xf}[args.flash_freq]
+
+    if args.output is None:
+        args.output = image.default_output_name(args.input)
+    image.save(args.output)
+
+
+def read_mac(esp, args):
+    mac = esp.read_mac()
+    print 'MAC: %s' % ':'.join(map(lambda x: '%02x' % x, mac))
+
+
+def chip_id(esp, args):
+    chipid = esp.chip_id()
+    print 'Chip ID: 0x%08x' % chipid
+
+
+def erase_flash(esp, args):
+    print 'Erasing flash (this may take a while)...'
+    flasher = CesantaFlasher(esp, args.baud)
+    flasher.flash_erase()
+    print 'Erase completed successfully.'
+
+
+def run(esp, args):
+    esp.run()
+
+
+def flash_id(esp, args):
+    flash_id = esp.flash_id()
+    print 'Manufacturer: %02x' % (flash_id & 0xff)
+    print 'Device: %02x%02x' % ((flash_id >> 8) & 0xff, (flash_id >> 16) & 0xff)
+
+
+def read_flash(esp, args):
+    flasher = CesantaFlasher(esp, args.baud)
+    t = time.time()
+    data = flasher.flash_read(args.address, args.size, not args.no_progress)
+    t = time.time() - t
+    print ('\rRead %d bytes at 0x%x in %.1f seconds (%.1f kbit/s)...'
+           % (len(data), args.address, t, len(data) / t * 8 / 1000))
+    file(args.filename, 'wb').write(data)
+
+
+def _verify_flash(flasher, args, flash_params=None):
+    differences = False
+    for address, argfile in args.addr_filename:
+        image = argfile.read()
+        argfile.seek(0)  # rewind in case we need it again
+        if address == 0 and image[0] == '\xe9' and flash_params is not None:
+            image = image[0:2] + flash_params + image[4:]
+        image_size = len(image)
+        print 'Verifying 0x%x (%d) bytes @ 0x%08x in flash against %s...' % (image_size, image_size, address, argfile.name)
+        # Try digest first, only read if there are differences.
+        digest, _ = flasher.flash_digest(address, image_size)
+        digest = hexify(digest).upper()
+        expected_digest = hashlib.md5(image).hexdigest().upper()
+        if digest == expected_digest:
+            print '-- verify OK (digest matched)'
+            continue
+        else:
+            differences = True
+            if getattr(args, 'diff', 'no') != 'yes':
+                print '-- verify FAILED (digest mismatch)'
+                continue
+
+        flash = flasher.flash_read(address, image_size)
+        assert flash != image
+        diff = [i for i in xrange(image_size) if flash[i] != image[i]]
+        print '-- verify FAILED: %d differences, first @ 0x%08x' % (len(diff), address + diff[0])
+        for d in diff:
+            print '   %08x %02x %02x' % (address + d, ord(flash[d]), ord(image[d]))
+    if differences:
+        raise FatalError("Verify failed.")
+
+
+def verify_flash(esp, args, flash_params=None):
+    flasher = CesantaFlasher(esp)
+    _verify_flash(flasher, args, flash_params)
+
+
+def version(args):
+    print __version__
+
+#
+# End of operations functions
+#
+
+
+def main():
+    parser = argparse.ArgumentParser(description='esptool.py v%s - ESP8266 ROM Bootloader Utility' % __version__, prog='esptool')
+
+    parser.add_argument('--chip', '-c',
+                        help='Target chip type',
+                        choices=['auto', 'esp8266', 'esp31', 'esp32'],
+                        default=os.environ.get('ESPTOOL_CHIP', 'auto'))
+
+    parser.add_argument(
+        '--port', '-p',
+        help='Serial port device',
+        default=os.environ.get('ESPTOOL_PORT', ESPROM.DEFAULT_PORT))
+
+    parser.add_argument(
+        '--baud', '-b',
+        help='Serial port baud rate used when flashing/reading',
+        type=arg_auto_int,
+        default=os.environ.get('ESPTOOL_BAUD', ESPROM.ESP_ROM_BAUD))
+
+    subparsers = parser.add_subparsers(
+        dest='operation',
+        help='Run esptool {command} -h for additional help')
+
+    parser_load_ram = subparsers.add_parser(
+        'load_ram',
+        help='Download an image to RAM and execute')
+    parser_load_ram.add_argument('filename', help='Firmware image')
+
+    parser_dump_mem = subparsers.add_parser(
+        'dump_mem',
+        help='Dump arbitrary memory to disk')
+    parser_dump_mem.add_argument('address', help='Base address', type=arg_auto_int)
+    parser_dump_mem.add_argument('size', help='Size of region to dump', type=arg_auto_int)
+    parser_dump_mem.add_argument('filename', help='Name of binary dump')
+
+    parser_read_mem = subparsers.add_parser(
+        'read_mem',
+        help='Read arbitrary memory location')
+    parser_read_mem.add_argument('address', help='Address to read', type=arg_auto_int)
+
+    parser_write_mem = subparsers.add_parser(
+        'write_mem',
+        help='Read-modify-write to arbitrary memory location')
+    parser_write_mem.add_argument('address', help='Address to write', type=arg_auto_int)
+    parser_write_mem.add_argument('value', help='Value', type=arg_auto_int)
+    parser_write_mem.add_argument('mask', help='Mask of bits to write', type=arg_auto_int)
+
+    def add_spi_flash_subparsers(parent):
+        """ Add common parser arguments for SPI flash properties """
+        parent.add_argument('--flash_freq', '-ff', help='SPI Flash frequency',
+                            choices=['40m', '26m', '20m', '80m'],
+                            default=os.environ.get('ESPTOOL_FF', '40m'))
+        parent.add_argument('--flash_mode', '-fm', help='SPI Flash mode',
+                            choices=['qio', 'qout', 'dio', 'dout'],
+                            default=os.environ.get('ESPTOOL_FM', 'qio'))
+        parent.add_argument('--flash_size', '-fs', help='SPI Flash size in MegaBytes (1MB, 2MB, 4MB, 8MB, 16M)'
+                            ' plus ESP8266-only (256KB, 512KB, 2MB-c1, 4MB-c1, 4MB-2)',
+                            action=FlashSizeAction,
+                            default=os.environ.get('ESPTOOL_FS', '1MB'))
+
+    parser_write_flash = subparsers.add_parser(
+        'write_flash',
+        help='Write a binary blob to flash')
+    parser_write_flash.add_argument('addr_filename', metavar='<address> <filename>', help='Address followed by binary filename, separated by space',
+                                    action=AddrFilenamePairAction)
+    add_spi_flash_subparsers(parser_write_flash)
+    parser_write_flash.add_argument('--no-progress', '-p', help='Suppress progress output', action="store_true")
+    parser_write_flash.add_argument('--verify', help='Verify just-written data (only necessary if very cautious, data is already CRCed', action='store_true')
+    parser_write_flash.add_argument('--ucIsHspi', '-ih', help='Config SPI PORT/PINS (Espressif internal feature)',default='0')
+    parser_write_flash.add_argument('--ucIsLegacy', '-il', help='Config SPI LEGACY (Espressif internal feature)',default='0')
+    parser_write_flash.add_argument('--compress', '-z', help='Compress data in transfer',action="store_true")
+
+    subparsers.add_parser(
+        'run',
+        help='Run application code in flash')
+
+    parser_image_info = subparsers.add_parser(
+        'image_info',
+        help='Dump headers from an application image')
+    parser_image_info.add_argument('filename', help='Image file to parse')
+
+    parser_make_image = subparsers.add_parser(
+        'make_image',
+        help='Create an application image from binary files')
+    parser_make_image.add_argument('output', help='Output image file')
+    parser_make_image.add_argument('--segfile', '-f', action='append', help='Segment input file')
+    parser_make_image.add_argument('--segaddr', '-a', action='append', help='Segment base address', type=arg_auto_int)
+    parser_make_image.add_argument('--entrypoint', '-e', help='Address of entry point', type=arg_auto_int, default=0)
+
+    parser_elf2image = subparsers.add_parser(
+        'elf2image',
+        help='Create an application image from ELF file')
+    parser_elf2image.add_argument('input', help='Input ELF file')
+    parser_elf2image.add_argument('--output', '-o', help='Output filename prefix (for version 1 image), or filename (for version 2 single image)', type=str)
+    parser_elf2image.add_argument('--version', '-e', help='Output image version', choices=['1','2'], default='1')
+    add_spi_flash_subparsers(parser_elf2image)
+
+    subparsers.add_parser(
+        'read_mac',
+        help='Read MAC address from OTP ROM')
+
+    subparsers.add_parser(
+        'chip_id',
+        help='Read Chip ID from OTP ROM')
+
+    subparsers.add_parser(
+        'flash_id',
+        help='Read SPI flash manufacturer and device ID')
+
+    parser_read_flash = subparsers.add_parser(
+        'read_flash',
+        help='Read SPI flash content')
+    parser_read_flash.add_argument('address', help='Start address', type=arg_auto_int)
+    parser_read_flash.add_argument('size', help='Size of region to dump', type=arg_auto_int)
+    parser_read_flash.add_argument('filename', help='Name of binary dump')
+    parser_read_flash.add_argument('--no-progress', '-p', help='Suppress progress output', action="store_true")
+
+    parser_verify_flash = subparsers.add_parser(
+        'verify_flash',
+        help='Verify a binary blob against flash')
+    parser_verify_flash.add_argument('addr_filename', help='Address and binary file to verify there, separated by space',
+                                     action=AddrFilenamePairAction)
+    parser_verify_flash.add_argument('--diff', '-d', help='Show differences',
+                                     choices=['no', 'yes'], default='no')
+
+    subparsers.add_parser(
+        'erase_flash',
+        help='Perform Chip Erase on SPI flash')
+
+    subparsers.add_parser(
+        'version', help='Print esptool version')
+
+    # internal sanity check - every operation matches a module function of the same name
+    for operation in subparsers.choices.keys():
+        assert operation in globals(), "%s should be a module function" % operation
+
+    args = parser.parse_args()
+
+    print 'esptool.py v%s' % __version__
+
+    # operation function can take 1 arg (args), 2 args (esp, arg)
+    # or be a member function of the ESPROM class.
+
+    operation_func = globals()[args.operation]
+    operation_args,_,_,_ = inspect.getargspec(operation_func)
+    if operation_args[0] == 'esp':  # operation function takes an ESPROM connection object
+        initial_baud = min(ESPROM.ESP_ROM_BAUD, args.baud)  # don't sync faster than the default baud rate
+        chip_constructor_fun = {
+            'auto': ESPROM.detect_chip,
+            'esp8266': ESP8266ROM,
+            'esp31': ESP31ROM,
+            'esp32': ESP32ROM,
+        }[args.chip]
+        esp = chip_constructor_fun(args.port, initial_baud)
+        operation_func(esp, args)
+    else:
+        operation_func(args)
+
+
+class FlashSizeAction(argparse.Action):
+    """ Custom flash size parser class to support backwards compatibility with megabit size arguments.
+
+    (At next major relase, remove deprecated sizes and this can become a 'normal' choices= argument again.)
+    """
+    def __init__(self, option_strings, dest, nargs=1, **kwargs):
+        super(FlashSizeAction, self).__init__(option_strings, dest, nargs, **kwargs)
+
+    def __call__(self, parser, namespace, values, option_string=None):
+        try:
+            value = {
+                '2m': '256KB',
+                '4m': '512KB',
+                '8m': '1MB',
+                '16m': '2MB',
+                '32m': '4MB',
+                '16m-c1': '2MB-c1',
+                '32m-c1': '4MB-c1',
+                '32m-c2': '4MB-c2'
+            }[values[0]]
+            print("WARNING: Flash size arguments in megabits like '%s' are deprecated." % (values[0]))
+            print("Please use the equivalent size '%s'." % (value))
+            print("Megabit arguments may be removed in a future release.")
+        except KeyError:
+            values = values[0]
+
+        known_sizes = dict(ESP8266ROM.FLASH_SIZES)
+        known_sizes.update(ESP32ROM.FLASH_SIZES)
+        if value not in known_sizes:
+            raise argparse.ArgumentError(self, '%s is not a known flash size. Known sizes: %s' % (value, ", ".join(known_sizes.keys())))
+        setattr(namespace, self.dest, value)
+
+
+class AddrFilenamePairAction(argparse.Action):
+    """ Custom parser class for the address/filename pairs passed as arguments """
+    def __init__(self, option_strings, dest, nargs='+', **kwargs):
+        super(AddrFilenamePairAction, self).__init__(option_strings, dest, nargs, **kwargs)
+
+    def __call__(self, parser, namespace, values, option_string=None):
+        # validate pair arguments
+        pairs = []
+        for i in range(0,len(values),2):
+            try:
+                address = int(values[i],0)
+            except ValueError as e:
+                raise argparse.ArgumentError(self,'Address "%s" must be a number' % values[i])
+            try:
+                argfile = open(values[i + 1], 'rb')
+            except IOError as e:
+                raise argparse.ArgumentError(self, e)
+            except IndexError:
+                raise argparse.ArgumentError(self,'Must be pairs of an address and the binary filename to write there')
+            pairs.append((address, argfile))
+        setattr(namespace, self.dest, pairs)
+
+# This is "wrapped" stub_flasher.c, to  be loaded using run_stub.
+_CESANTA_FLASHER_STUB = """\
+{"code_start": 1074790404, "code": "080000601C000060000000601000006031FCFF71FCFF\
+81FCFFC02000680332D218C020004807404074DCC48608005823C0200098081BA5A9239245005803\
+1B555903582337350129230B446604DFC6F3FF21EEFFC0200069020DF0000000010078480040004A\
+0040B449004012C1F0C921D911E901DD0209312020B4ED033C2C56C2073020B43C3C56420701F5FF\
+C000003C4C569206CD0EEADD860300202C4101F1FFC0000056A204C2DCF0C02DC0CC6CCAE2D1EAFF\
+0606002030F456D3FD86FBFF00002020F501E8FFC00000EC82D0CCC0C02EC0C73DEB2ADC46030020\
+2C4101E1FFC00000DC42C2DCF0C02DC056BCFEC602003C5C8601003C6C4600003C7C08312D0CD811\
+C821E80112C1100DF0000C180000140010400C0000607418000064180000801800008C1800008418\
+0000881800009018000018980040880F0040A80F0040349800404C4A0040740F0040800F0040980F\
+00400099004012C1E091F5FFC961CD0221EFFFE941F9310971D9519011C01A223902E2D1180C0222\
+6E1D21E4FF31E9FF2AF11A332D0F42630001EAFFC00000C030B43C2256A31621E1FF1A2228022030\
+B43C3256B31501ADFFC00000DD023C4256ED1431D6FF4D010C52D90E192E126E0101DDFFC0000021\
+D2FF32A101C020004802303420C0200039022C0201D7FFC00000463300000031CDFF1A333803D023\
+C03199FF27B31ADC7F31CBFF1A3328030198FFC0000056C20E2193FF2ADD060E000031C6FF1A3328\
+030191FFC0000056820DD2DD10460800000021BEFF1A2228029CE231BCFFC020F51A33290331BBFF\
+C02C411A332903C0F0F4222E1D22D204273D9332A3FFC02000280E27B3F721ABFF381E1A2242A400\
+01B5FFC00000381E2D0C42A40001B3FFC0000056120801B2FFC00000C02000280EC2DC0422D2FCC0\
+2000290E01ADFFC00000222E1D22D204226E1D281E22D204E7B204291E860000126E012198FF32A0\
+042A21C54C003198FF222E1D1A33380337B202C6D6FF2C02019FFFC000002191FF318CFF1A223A31\
+019CFFC00000218DFF1C031A22C549000C02060300003C528601003C624600003C72918BFF9A1108\
+71C861D851E841F83112C1200DF00010000068100000581000007010000074100000781000007C10\
+0000801000001C4B0040803C004091FDFF12C1E061F7FFC961E941F9310971D9519011C01A662906\
+21F3FFC2D1101A22390231F2FF0C0F1A33590331EAFFF26C1AED045C2247B3028636002D0C016DFF\
+C0000021E5FF41EAFF2A611A4469040622000021E4FF1A222802F0D2C0D7BE01DD0E31E0FF4D0D1A\
+3328033D0101E2FFC00000561209D03D2010212001DFFFC000004D0D2D0C3D01015DFFC0000041D5\
+FFDAFF1A444804D0648041D2FF1A4462640061D1FF106680622600673F1331D0FF10338028030C43\
+853A002642164613000041CAFF222C1A1A444804202FC047328006F6FF222C1A273F3861C2FF222C\
+1A1A6668066732B921BDFF3D0C1022800148FFC0000021BAFF1C031A2201BFFFC000000C02460300\
+5C3206020000005C424600005C5291B7FF9A110871C861D851E841F83112C1200DF0B0100000C010\
+0000D010000012C1E091FEFFC961D951E9410971F931CD039011C0ED02DD0431A1FF9C1422A06247\
+B302062D0021F4FF1A22490286010021F1FF1A223902219CFF2AF12D0F011FFFC00000461C0022D1\
+10011CFFC0000021E9FFFD0C1A222802C7B20621E6FF1A22F8022D0E3D014D0F0195FFC000008C52\
+22A063C6180000218BFF3D01102280F04F200111FFC00000AC7D22D1103D014D0F010DFFC0000021\
+D6FF32D110102280010EFFC0000021D3FF1C031A220185FFC00000FAEEF0CCC056ACF821CDFF317A\
+FF1A223A310105FFC0000021C9FF1C031A22017CFFC000002D0C91C8FF9A110871C861D851E841F8\
+3112C1200DF0000200600000001040020060FFFFFF0012C1E00C02290131FAFF21FAFF026107C961\
+C02000226300C02000C80320CC10564CFF21F5FFC02000380221F4FF20231029010C432D010163FF\
+C0000008712D0CC86112C1200DF00080FE3F8449004012C1D0C9A109B17CFC22C1110C13C51C0026\
+1202463000220111C24110B68202462B0031F5FF3022A02802A002002D011C03851A0066820A2801\
+32210105A6FF0607003C12C60500000010212032A01085180066A20F2221003811482105B3FF2241\
+10861A004C1206FDFF2D011C03C5160066B20E280138114821583185CFFF06F7FF005C1286F5FF00\
+10212032A01085140066A20D2221003811482105E1FF06EFFF0022A06146EDFF45F0FFC6EBFF0000\
+01D2FFC0000006E9FF000C022241100C1322C110C50F00220111060600000022C1100C13C50E0022\
+011132C2FA303074B6230206C8FF08B1C8A112C1300DF0000000000010404F484149007519031027\
+000000110040A8100040BC0F0040583F0040CC2E00401CE20040D83900408000004021F4FF12C1E0\
+C961C80221F2FF097129010C02D951C91101F4FFC0000001F3FFC00000AC2C22A3E801F2FFC00000\
+21EAFFC031412A233D0C01EFFFC000003D0222A00001EDFFC00000C1E4FF2D0C01E8FFC000002D01\
+32A004450400C5E7FFDD022D0C01E3FFC00000666D1F4B2131DCFF4600004B22C0200048023794F5\
+31D9FFC0200039023DF08601000001DCFFC000000871C861D85112C1200DF000000012C1F0026103\
+01EAFEC00000083112C1100DF000643B004012C1D0E98109B1C9A1D991F97129013911E2A0C001FA\
+FFC00000CD02E792F40C0DE2A0C0F2A0DB860D00000001F4FFC00000204220E71240F7921C226102\
+01EFFFC0000052A0DC482157120952A0DD571205460500004D0C3801DA234242001BDD3811379DC5\
+C6000000000C0DC2A0C001E3FFC00000C792F608B12D0DC8A1D891E881F87112C1300DF00000", "\
+entry": 1074792180, "num_params": 1, "params_start": 1074790400, "data": "FE0510\
+401A0610403B0610405A0610407A061040820610408C0610408C061040", "data_start": 10736\
+43520}
+"""
+
+if __name__ == '__main__':
+    try:
+        main()
+    except FatalError as e:
+        print '\nA fatal error occurred: %s' % e
+        sys.exit(2)

bin/gen_esp32part.py

@@ -0,0 +1,308 @@
+#!/usr/bin/env python
+#
+# ESP32 partition table generation tool
+#
+# Converts partition tables to/from CSV and binary formats.
+#
+# See the sdkng README.md file for details about how to use this tool.
+import struct
+import argparse
+import sys
+
+__version__ = '1.0'
+
+quiet = False
+
+def status(msg):
+    """ Print status message to stderr """
+    if not quiet:
+        critical(msg)
+
+def critical(msg):
+    """ Print critical message to stderr """
+    if not quiet:
+        sys.stderr.write(msg)
+        sys.stderr.write('\n')
+
+class PartitionTable(list):
+    def __init__(self):
+        super(PartitionTable, self).__init__(self)
+
+    @classmethod
+    def from_csv(cls, csv_contents):
+        res = PartitionTable()
+        lines = csv_contents.split("\n")
+        for line_no in range(len(lines)):
+            line = lines[line_no].strip()
+            if line.startswith("#") or len(line) == 0:
+                continue
+            try:
+                res.append(PartitionDefinition.from_csv(line))
+            except InputError as e:
+                raise InputError("Error at line %d: %s" % (line_no+1, e))
+            except Exception:
+                critical("Unexpected error parsing line %d: %s" % (line_no+1, line))
+                raise
+
+        # fix up missing offsets & negative sizes
+        last_end = 0x5000 # first offset after partition table
+        for e in res:
+            if e.offset is None:
+                pad_to = 0x10000 if e.type == PartitionDefinition.APP_TYPE else 4
+                if last_end % pad_to != 0:
+                    last_end += pad_to - (last_end % pad_to)
+                e.offset = last_end
+            if e.size < 0:
+                e.size = -e.size - e.offset
+            last_end = e.offset + e.size
+
+        return res
+
+    def __getitem__(self, item):
+        """ Allow partition table access via name as well as by
+        numeric index. """
+        if isinstance(item, str):
+            for x in self:
+                if x.name == item:
+                    return x
+            raise ValueError("No partition entry named '%s'" % item)
+        else:
+            return super(PartitionTable, self).__getitem__(item)
+
+    def verify(self):
+        # verify each partition individually
+        for p in self:
+            p.verify()
+        # check for overlaps
+        last = None
+        for p in sorted(self):
+            if p.offset < 0x5000:
+                raise InputError("Partition offset 0x%x is below 0x5000" % p.offset)
+            if last is not None and p.offset < last.offset + last.size:
+                raise InputError("Partition at 0x%x overlaps 0x%x-0x%x" % (p.offset, last.offset, last.offset+last.size-1))
+            last = p
+
+    @classmethod
+    def from_binary(cls, b):
+        if len(b) % 32 != 0:
+            raise InputError("Partition table length must be a multiple of 32 bytes. Got %d bytes." % len(b))
+        result = cls()
+        for o in range(0,len(b),32):
+            result.append(PartitionDefinition.from_binary(b[o:o+32]))
+        return result
+
+    def to_binary(self):
+        return "".join(e.to_binary() for e in self)
+
+    def to_csv(self, simple_formatting=False):
+        rows = [ "# Espressif ESP32 Partition Table",
+                 "# Name, Type, SubType, Offset, Size" ]
+        rows += [ x.to_csv(simple_formatting) for x in self ]
+        return "\n".join(rows) + "\n"
+
+class PartitionDefinition(object):
+    APP_TYPE = 0x00
+    DATA_TYPE = 0x01
+    TYPES = {
+        "app" : APP_TYPE,
+        "data" : DATA_TYPE,
+    }
+
+    SUBTYPES = {
+        APP_TYPE : {
+            "factory" : 0x00,
+            "test" : 0x20,
+            },
+        DATA_TYPE : {
+            "ota" : 0x00,
+            "rf" : 0x01,
+            "wifi" : 0x02,
+            },
+    }
+
+    MAGIC_BYTES = "\xAA\x50"
+
+    ALIGNMENT = {
+        APP_TYPE : 0x1000,
+        DATA_TYPE : 0x04,
+    }
+
+    # add subtypes for the 16 OTA slot values ("ota_XXX, etc.")
+    for ota_slot in range(16):
+        SUBTYPES[TYPES["app"]]["ota_%d" % ota_slot] = 0x10 + ota_slot
+
+    def __init__(self):
+        self.name = ""
+        self.type = None
+        self.subtype = None
+        self.offset = None
+        self.size = None
+
+    @classmethod
+    def from_csv(cls, line):
+        """ Parse a line from the CSV """
+        line_w_defaults = line + ",,,"  # lazy way to support default fields
+        fields = [ f.strip() for f in line_w_defaults.split(",") ]
+
+        res = PartitionDefinition()
+        res.name = fields[0]
+        res.type = res.parse_type(fields[1])
+        res.subtype = res.parse_subtype(fields[2])
+        res.offset = res.parse_address(fields[3])
+        res.size = res.parse_address(fields[4])
+        if res.size is None:
+            raise InputError("Size field can't be empty")
+        return res
+
+    def __eq__(self, other):
+        return self.name == other.name and self.type == other.type \
+            and self.subtype == other.subtype and self.offset == other.offset \
+            and self.size == other.size
+
+    def __repr__(self):
+        def maybe_hex(x):
+            return "0x%x" % x if x is not None else "None"
+        return "PartitionDefinition('%s', 0x%x, 0x%x, %s, %s)" % (self.name, self.type, self.subtype or 0,
+                                                              maybe_hex(self.offset), maybe_hex(self.size))
+
+    def __str__(self):
+        return "Part '%s' %d/%d @ 0x%x size 0x%x" % (self.name, self.type, self.subtype, self.offset or -1, self.size or -1)
+
+    def __cmp__(self, other):
+        return self.offset - other.offset
+
+    def parse_type(self, strval):
+        if strval == "":
+            raise InputError("Field 'type' can't be left empty.")
+        return parse_int(strval, self.TYPES)
+
+    def parse_subtype(self, strval):
+        if strval == "":
+            return 0 # default
+        return parse_int(strval, self.SUBTYPES.get(self.type, {}))
+
+    def parse_address(self, strval):
+        if strval == "":
+            return None  # PartitionTable will fill in default
+        return parse_int(strval)
+
+    def verify(self):
+        if self.type is None:
+            raise ValidationError("Type field is not set")
+        if self.subtype is None:
+            raise ValidationError("Subtype field is not set")
+        if self.offset is None:
+            raise ValidationError("Offset field is not set")
+        align = self.ALIGNMENT.get(self.type, 4)
+        if self.offset % align:
+            raise ValidationError("%s offset 0x%x is not aligned to 0x%x" % (self.name, self.offset, align))
+        if self.size is None:
+            raise ValidationError("Size field is not set")
+
+    STRUCT_FORMAT = "<2sBBLL16sL"
+
+    @classmethod
+    def from_binary(cls, b):
+        if len(b) != 32:
+            raise InputError("Partition definition length must be exactly 32 bytes. Got %d bytes." % len(b))
+        res = cls()
+        (magic, res.type, res.subtype, res.offset,
+         res.size, res.name, reserved) = struct.unpack(cls.STRUCT_FORMAT, b)
+        if "\x00" in res.name: # strip null byte padding from name string
+            res.name = res.name[:res.name.index("\x00")]
+        if magic != cls.MAGIC_BYTES:
+            raise InputError("Invalid magic bytes (%r) for partition definition" % magic)
+        if reserved != 0:
+            critical("WARNING: Partition definition had unexpected reserved value 0x%08x. Newer binary format?" % reserved)
+        return res
+
+    def to_binary(self):
+        return struct.pack(self.STRUCT_FORMAT,
+                           self.MAGIC_BYTES,
+                           self.type, self.subtype,
+                           self.offset, self.size,
+                           self.name,
+                           0) # reserved
+
+    def to_csv(self, simple_formatting=False):
+        def addr_format(a, include_sizes):
+            if not simple_formatting and include_sizes:
+                for (val, suffix) in [ (0x100000, "M"), (0x400, "K") ]:
+                    if a % val == 0:
+                        return "%d%s" % (a / val, suffix)
+            return "0x%x" % a
+
+        def lookup_keyword(t, keywords):
+            for k,v in keywords.items():
+                if simple_formatting == False and t == v:
+                    return k
+            return "%d" % t
+
+        return ",".join([ self.name,
+                          lookup_keyword(self.type, self.TYPES),
+                          lookup_keyword(self.subtype, self.SUBTYPES.get(self.type, {})),
+                          addr_format(self.offset, False),
+                          addr_format(self.size, True) ])
+
+class InputError(RuntimeError):
+    def __init__(self, e):
+        super(InputError, self).__init__(e)
+
+def parse_int(v, keywords={}):
+    """Generic parser for integer fields - int(x,0) with provision for
+    k/m/K/M suffixes and 'keyword' value lookup.
+    """
+    try:
+        for letter, multiplier in [ ("k",1024), ("m",1024*1024) ]:
+            if v.lower().endswith(letter):
+                return parse_int(v[:-1], keywords) * multiplier
+        return int(v, 0)
+    except ValueError:
+        if len(keywords) == 0:
+            raise InputError("Invalid field value %s" % v)
+        try:
+            return keywords[v.lower()]
+        except KeyError:
+            raise InputError("Value '%s' is not valid. Known keywords: %s" % (v, ", ".join(keywords)))
+
+def main():
+    global quiet
+    parser = argparse.ArgumentParser(description='ESP32 partition table utility')
+
+    parser.add_argument('--verify', '-v', help='Verify partition table fields', default=True, action='store_false')
+    parser.add_argument('--quiet', '-q', help="Don't print status messages to stderr", action='store_true')
+
+    parser.add_argument('input', help='Path to CSV or binary file to parse. Will use stdin if omitted.', type=argparse.FileType('r'), default=sys.stdin)
+    parser.add_argument('output', help='Path to output converted binary or CSV file. Will use stdout if omitted, unless the --display argument is also passed (in which case only the summary is printed.)',
+                        nargs='?',
+                        default='-')
+
+    args = parser.parse_args()
+
+    quiet = args.quiet
+    input = args.input.read()
+    input_is_binary = input[0:2] == PartitionDefinition.MAGIC_BYTES
+    if input_is_binary:
+        status("Parsing binary partition input...")
+        table = PartitionTable.from_binary(input)
+    else:
+        status("Parsing CSV input...")
+        table = PartitionTable.from_csv(input)
+
+    if args.verify:
+        status("Verifying table...")
+        table.verify()
+
+    if input_is_binary:
+        output = table.to_csv()
+    else:
+        output = table.to_binary()
+    with sys.stdout if args.output == '-' else open(args.output, 'w') as f:
+        f.write(output)
+
+if __name__ == '__main__':
+    try:
+        main()
+    except InputError as e:
+        print(e)
+        sys.exit(2)

components/bootloader/Makefile.projbuild

@@ -0,0 +1,45 @@
+#
+# Bootloader component
+#
+# The bootloader is not a real component that gets linked into the project.
+# Instead it is an entire standalone project ( in src/) that gets built in 
+# the upper projects build directory. This Makefile.projbuild provides the 
+# glue to  build the bootloader project from the original project. It 
+# basically runs Make in the src/ directory but it needs to zero some variables
+# the SDK makefile exports first, to not let them interfere.
+#
+
+BOOTLOADER_COMPONENT_PATH := $(COMPONENT_PATH)
+EXTRA_CLEAN_TARGETS+=bootloader-clean
+BOOTLOADER_BIN=$(BUILD_DIR_BASE)/bootloader.bin
+
+.PHONY: bootloader-clean bootloader-flash bootloader
+
+$(BOOTLOADER_BIN): $(COMPONENT_PATH)/src/sdkconfig
+	$(Q) PROJECT_PATH= \
+	COMPONENT_LDFLAGS= \
+	COMPONENT_INCLUDES= \
+	LDFLAGS= \
+	CFLAGS= \
+	BUILD_DIR_BASE=$(BUILD_DIR_BASE)/bootloader \
+	make -C $(BOOTLOADER_COMPONENT_PATH)/src MAKEFLAGS= V=$(V) TARGET_BIN_LAYOUT="$(BOOTLOADER_TARGET_BIN_LAYOUT)"
+
+bootloader-clean:
+	$(Q) PROJECT_PATH= \
+	COMPONENT_LDFLAGS= \
+	COMPONENT_INCLUDES= \
+	LDFLAGS= \
+	CFLAGS= \
+	BUILD_DIR_BASE=$(BUILD_DIR_BASE)/bootloader \
+	make -C $(BOOTLOADER_COMPONENT_PATH)/src clean MAKEFLAGS= V=$(V)
+
+bootloader: $(BUILD_DIR_BASE)/bootloader.bin
+
+# synchronise the project level config to the component's
+# config
+$(COMPONENT_PATH)/src/sdkconfig: $(PROJECT_PATH)/sdkconfig
+	$(Q) cp $< $@
+
+# bootloader-flash calls flash in the bootloader dummy project
+bootloader-flash: $(BOOTLOADER_BIN)
+	make -C $(BOOTLOADER_COMPONENT_PATH)/src flash MAKEFLAGS= V=$(V) CONFIG_APP_OFFSET=0x1000

components/bootloader/src/.gitignore

@@ -0,0 +1,2 @@
+build
+sdkconfig

components/bootloader/src/Makefile

@@ -0,0 +1,12 @@
+#
+# This is a project Makefile. It is assumed the directory this Makefile resides in is a
+# project subdirectory.
+#
+
+PROJECT_NAME := bootloader
+COMPONENTS := esptool_py
+
+#We cannot include the esp32 component directly but we need its includes. This is fixed by
+#adding it in the main/Makefile directory.
+
+include $(SDK_PATH)/make/project.mk

components/bootloader/src/main/Makefile

@@ -0,0 +1,13 @@
+#
+# Main Makefile. This is basically the same as a component makefile.
+#
+# This Makefile should, at the very least, just include $(SDK_PATH)/make/component.mk. By default, 
+# this will take the sources in the src/ directory, compile them and link them into 
+# lib(subdirectory_name).a in the build directory. This behaviour is entirely configurable,
+# please read the SDK documents if you need to do this.
+#
+
+COMPONENT_ADD_LDFLAGS := -L $(abspath .) -lmain -T eagle.bootloader.ld -T $(SDK_PATH)/components/esp32/ld/eagle.fpga32.rom.addr.v7.ld 
+COMPONENT_EXTRA_INCLUDES := $(SDK_PATH)/components/esp32/include 
+
+include $(SDK_PATH)/make/component.mk

components/bootloader/src/main/bootloader_config.h

@@ -0,0 +1,138 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef __BOOT_CONFIG_H__
+#define __BOOT_CONFIG_H__
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+#define BOOT_VERSION "V0.1"
+#define SPI_SEC_SIZE 0x1000
+#define MEM_CACHE(offset)   (uint8_t *)(0x3f400000 + (offset))
+#define CACHE_READ_32(offset)   ((uint32_t *)(0x3f400000 + (offset)))
+#define PARTITION_ADD 0x4000
+#define PARTITION_MAGIC 0x50AA
+#define IROM_LOW    0x400D0000
+#define IROM_HIGH   0x40400000
+#define DROM_LOW    0x3F400000
+#define DROM_HIGH   0x3F800000
+
+/*spi mode,saved in third byte in flash */
+enum {
+    SPI_MODE_QIO,
+    SPI_MODE_QOUT,
+    SPI_MODE_DIO,
+    SPI_MODE_DOUT,
+    SPI_MODE_FAST_READ,
+    SPI_MODE_SLOW_READ
+};
+/* spi speed*/
+enum {
+    SPI_SPEED_40M,
+    SPI_SPEED_26M,
+    SPI_SPEED_20M,
+    SPI_SPEED_80M = 0xF
+};
+/*suppport flash size in esp32 */
+enum {
+    SPI_SIZE_1MB = 0,
+    SPI_SIZE_2MB,
+    SPI_SIZE_4MB,
+    SPI_SIZE_8MB,
+    SPI_SIZE_16MB,
+    SPI_SIZE_MAX
+};
+
+
+struct flash_hdr {
+    char magic;
+    char blocks;
+    char spi_mode;      /* flag of flash read mode in unpackage and usage in future */
+    char spi_speed: 4;  /* low bit */
+    char spi_size: 4;
+    unsigned int entry_addr;
+    uint8_t encrypt_flag;    /* encrypt flag */
+    uint8_t secury_boot_flag; /* secury boot flag */
+    char extra_header[14]; /* ESP32 additional header, unused by second bootloader */
+};
+
+/* each header of flash bin block */
+struct block_hdr {
+    unsigned int load_addr;
+    unsigned int data_len;
+};
+
+/* OTA selection structure (two copies in the OTA data partition.)
+
+   Size of 32 bytes is friendly to flash encryption */
+typedef struct {
+    uint32_t ota_seq;
+    uint8_t  seq_label[24];
+    uint32_t crc; /* CRC32 of ota_seq field only */
+} ota_select;
+
+typedef struct {
+    uint32_t offset;
+    uint32_t size;
+} partition_pos_t;
+
+typedef struct {
+	uint16_t magic;
+	uint8_t  type;        /* partition Type */
+    uint8_t  subtype;     /* part_subtype */
+    partition_pos_t pos;
+	uint8_t  label[16];    /* label for the partition */
+    uint8_t  reserved[4];     /* reserved */
+} partition_info_t;
+
+#define PART_TYPE_APP 0x00
+#define PART_SUBTYPE_FACTORY  0x00
+#define PART_SUBTYPE_OTA_FLAG 0x10
+#define PART_SUBTYPE_OTA_MASK 0x0f
+#define PART_SUBTYPE_TEST     0x20
+
+#define PART_TYPE_DATA 0x01
+#define PART_SUBTYPE_DATA_OTA 0x00
+#define PART_SUBTYPE_DATA_RF  0x01
+#define PART_SUBTYPE_DATA_WIFI 0x02
+
+#define PART_TYPE_END 0xff
+#define PART_SUBTYPE_END 0xff
+
+#define SPI_ERROR_LOG "spi flash error"
+
+typedef struct {
+    partition_pos_t ota_info;
+    partition_pos_t factory;
+    partition_pos_t test;
+    partition_pos_t ota[16];
+    uint32_t app_count;
+    uint32_t selected_subtype;
+} bootloader_state_t;
+
+void boot_cache_redirect( uint32_t pos, size_t size );
+uint32_t get_bin_len(uint32_t pos);
+
+bool flash_encrypt(bootloader_state_t *bs);
+bool secure_boot(void);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __BOOT_CONFIG_H__ */

components/bootloader/src/main/bootloader_log.h

@@ -0,0 +1,89 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef __BOOT_LOG_H__
+#define __BOOT_LOG_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+#define BOOT_LOG_LEVEL_ERROR      (1)
+#define BOOT_LOG_LEVEL_WARN       (2)
+#define BOOT_LOG_LEVEL_INFO       (3)
+#define BOOT_LOG_LEVEL_NOTICE     (4)
+#define BOOT_LOG_LEVEL_DEBUG      (5)
+
+#define Black   0;30
+#define Red     0;31
+#define Green   0;32
+#define Brown   0;33
+#define Blue    0;34
+#define Purple  0;35
+#define Cyan    0;36
+
+// TODO: move BOOT_LOG_LEVEL into menuconfig
+//#define BOOT_LOG_LEVEL  BOOT_LOG_LEVEL_ERROR
+#define BOOT_LOG_LEVEL  BOOT_LOG_LEVEL_NOTICE
+
+//printf("\033[0;36m[NOTICE][%s][%s][%d]\n" format "\r\n", __FILE__, __FUNCTION__, __LINE__, ##__VA_ARGS__);
+#define log_notice(format, ...) \
+    do{\
+        if(BOOT_LOG_LEVEL >= BOOT_LOG_LEVEL_NOTICE){\
+            ets_printf("\033[0;36m" format "\r\n", ##__VA_ARGS__);\
+            ets_printf("\033[0m"); \
+        }\
+    }while(0)
+
+#define log_info(format, ...) \
+    do{\
+        if(BOOT_LOG_LEVEL >= BOOT_LOG_LEVEL_INFO){\
+            ets_printf("\033[1;36m" format "\r\n", ##__VA_ARGS__);\
+            ets_printf("\033[0m"); \
+        }\
+    }while(0)
+
+//printf("\033[0;31m[ERROR][%s][%s][%d]\n" format "\r\n", __FILE__, __FUNCTION__, __LINE__, ##__VA_ARGS__);
+#define log_error(format, ...) \
+    do{\
+        if(BOOT_LOG_LEVEL >= BOOT_LOG_LEVEL_ERROR){\
+            ets_printf("\033[0;31m[ERROR][%s][%s][%d]\n" format "\r\n", __FILE__, __FUNCTION__, __LINE__, ##__VA_ARGS__);\
+            ets_printf("\033[0m"); \
+        }\
+    }while(0)
+
+//printf("\033[1;33m[WARN][%s][%s][%d]\n" format "\r\n", __FILE__, __FUNCTION__, __LINE__, ##__VA_ARGS__);
+#define log_warn(format, ...) \
+    do{\
+        if(BOOT_LOG_LEVEL >= BOOT_LOG_LEVEL_WARN){\
+            ets_printf("\033[1;33m[WARN][%s][%s][%d]\n" format "\r\n", __FILE__, __FUNCTION__, __LINE__, ##__VA_ARGS__);\
+            ets_printf("\033[0m"); \
+        }\
+    }while(0)
+
+//printf("\033[1;32m[DEBUG][%s][%s][%d]\n" format "\r\n", __FILE__, __FUNCTION__, __LINE__, ##__VA_ARGS__);
+#define log_debug(format, ...) \
+    do{\
+        if(BOOT_LOG_LEVEL >= BOOT_LOG_LEVEL_DEBUG){\
+	   		ets_printf("\033[1;32m[DEBUG][%s][%s][%d]\n" format "\r\n", __FILE__, __FUNCTION__, __LINE__, ##__VA_ARGS__);  \
+            ets_printf("\033[0m"); \
+        }\
+    }while(0)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __BOOT_LOGGING_H__ */

components/bootloader/src/main/bootloader_start.c

@@ -0,0 +1,597 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#include <string.h>
+#include <stdint.h>
+#include <limits.h>
+
+#include "esp_attr.h"
+
+#include "rom/cache.h"
+#include "rom/ets_sys.h"
+#include "rom/spi_flash.h"
+#include "rom/crc.h"
+
+#include "soc/soc.h"
+#include "soc/dport_reg.h"
+#include "soc/io_mux_reg.h"
+#include "soc/efuse_reg.h"
+#include "soc/rtc_cntl_reg.h"
+#include "soc/timers_reg.h"
+
+#include "sdkconfig.h"
+
+#include "bootloader_log.h"
+#include "bootloader_config.h"
+
+extern int _bss_start;
+extern int _bss_end;
+/*
+We arrive here after the bootloader finished loading the program from flash. The hardware is mostly uninitialized,
+flash cache is down and the app CPU is in reset. We do have a stack, so we can do the initialization in C.
+*/
+
+// TODO: make a nice header file for ROM functions instead of adding externs all over the place
+extern void Cache_Flush(int);
+
+void bootloader_main();
+void unpack_load_app(const partition_pos_t *app_node);
+void print_flash_info(struct flash_hdr* pfhdr);
+void IRAM_ATTR set_cache_and_start_app(uint32_t drom_addr,
+    uint32_t drom_load_addr,
+    uint32_t drom_size,
+    uint32_t irom_addr,
+    uint32_t irom_load_addr,
+    uint32_t irom_size,
+    uint32_t entry_addr);
+
+
+void IRAM_ATTR call_start_cpu0()
+{
+    //Make page 0 access raise an exception
+    //Also some other unused pages so we can catch weirdness
+    //ToDo: this but nicer.
+    asm volatile (\
+                  "movi a4,0x00000000\n" \
+                  "movi a5,0xf\n" \
+                  "wdtlb a5,a4\n" \
+                  "witlb a5,a4\n" \
+                  "movi a4,0x80000000\n" \
+                  "wdtlb a5,a4\n" \
+                  "witlb a5,a4\n" \
+                  "movi a4,0xa0000000\n" \
+                  "wdtlb a5,a4\n" \
+                  "witlb a5,a4\n" \
+                  "movi a4,0xc0000000\n" \
+                  "wdtlb a5,a4\n" \
+                  "witlb a5,a4\n" \
+                  "movi a4,0xe0000000\n" \
+                  "wdtlb a5,a4\n" \
+                  "witlb a5,a4\n" \
+                  "movi a4,0x20000000\n" \
+                  "movi a5,0x0\n" \
+                  "wdtlb a5,a4\n" \
+                  "witlb a5,a4\n" \
+                  "movi a4,0x40000000\n" \
+                  "movi a5,0x2\n" \
+                  "wdtlb a5,a4\n" \
+                  "witlb a5,a4\n" \
+                  "isync\n" \
+                  :::"a4","a5");
+
+    //Clear bss
+    memset(&_bss_start, 0, (&_bss_end - &_bss_start) * sizeof(_bss_start));
+
+	/* completely reset MMU for both CPUs
+	   (in case serial bootloader was running) */
+	Cache_Read_Disable(0);
+	Cache_Read_Disable(1);
+	Cache_Flush(0);
+	Cache_Flush(1);
+	mmu_init(0);
+	mmu_init(1);
+	/* (above steps probably unnecessary for most serial bootloader
+	   usage, all that's absolutely needed is that we unmask DROM0
+	   cache on the following two lines - normal ROM boot exits with
+	   DROM0 cache unmasked, but serial bootloader exits with it
+	   masked. However can't hurt to be thorough and reset
+	   everything.)
+	*/
+	REG_CLR_BIT(PRO_CACHE_CTRL1_REG, DPORT_PRO_CACHE_MASK_DROM0);
+	REG_CLR_BIT(APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MASK_DROM0);
+
+    bootloader_main();
+}
+
+/**
+ *  @function :     get_bin_len
+ *  @description:   get bin's length 
+ *
+ *  @inputs:        pos     bin locate address in flash
+ *  @return:        uint32  length of bin,if bin MAGIC error return 0
+ */
+
+uint32_t get_bin_len(uint32_t pos)
+{   
+    uint32_t len = 8 + 16;
+    uint8_t i;
+    log_debug("pos %d %x\n",pos,*(uint8_t *)pos);
+    if(0xE9 != *(uint8_t *)pos) {
+        return 0;
+    }
+    for (i = 0; i < *(uint8_t *)(pos + 1); i++) {
+        len += *(uint32_t *)(pos + len + 4) + 8;
+    }
+    if (len % 16 != 0) {
+        len = (len / 16 + 1) * 16;
+    } else {
+        len += 16;
+    }
+    log_debug("bin length = %d\n", len);
+    return len;
+}
+
+/** 
+ *  @function :     boot_cache_redirect
+ *  @description:   Configure several pages in flash map so that `size` bytes 
+ *                  starting at `pos` are mapped to 0x3f400000.
+ *                  This sets up mapping only for PRO CPU.
+ *
+ *  @inputs:        pos     address in flash
+ *                  size    size of the area to map, in bytes
+ */
+void boot_cache_redirect( uint32_t pos, size_t size )
+{
+    uint32_t pos_aligned = pos & 0xffff0000;
+    uint32_t count = (size + 0xffff) / 0x10000;
+    Cache_Read_Disable( 0 );
+    Cache_Flush( 0 );
+    log_debug( "mmu set paddr=%08x count=%d", pos_aligned, count );
+    cache_flash_mmu_set( 0, 0, 0x3f400000, pos_aligned, 64, count );
+    Cache_Read_Enable( 0 );
+}
+
+/**
+ *  @function :     load_partition_table
+ *  @description:   Parse partition table, get useful data such as location of 
+ *                  OTA info sector, factory app sector, and test app sector.
+ *
+ *  @inputs:        bs     bootloader state structure used to save the data
+ *                  addr   address of partition table in flash
+ *  @return:        return true, if the partition table is loaded (and MD5 checksum is valid)
+ *
+ */
+bool load_partition_table(bootloader_state_t* bs, uint32_t addr)
+{
+    partition_info_t partition;
+    uint32_t end = addr + 0x1000;
+    int index = 0;
+    char *partition_usage;
+
+    log_info("Partition Table:");
+    log_info("## Label            Usage          Type ST Offset   Length");
+
+    while (addr < end) {
+        log_debug("load partition table entry from %x(%08x)", addr, MEM_CACHE(addr));
+        memcpy(&partition, MEM_CACHE(addr), sizeof(partition));
+        log_debug("type=%x subtype=%x", partition.type, partition.subtype);
+        partition_usage = "unknown";
+
+        if (partition.magic == PARTITION_MAGIC) { /* valid partition definition */
+            switch(partition.type) {
+            case PART_TYPE_APP: /* app partition */
+                switch(partition.subtype) {
+                case PART_SUBTYPE_FACTORY: /* factory binary */
+                    bs->factory = partition.pos;
+                    partition_usage = "factory app";
+                    break;
+                case PART_SUBTYPE_TEST: /* test binary */
+                    bs->test = partition.pos;
+                    partition_usage = "test app";
+                    break;
+                default:
+                    /* OTA binary */
+                    if ((partition.subtype & ~PART_SUBTYPE_OTA_MASK) == PART_SUBTYPE_OTA_FLAG) {
+                        bs->ota[partition.subtype & PART_SUBTYPE_OTA_MASK] = partition.pos;
+                        ++bs->app_count;
+                        partition_usage = "OTA app";
+                    }
+                    else {
+                        partition_usage = "Unknown app";
+                    }
+                    break;
+                }
+                break; /* PART_TYPE_APP */
+            case PART_TYPE_DATA: /* data partition */
+                switch(partition.subtype) {
+                case PART_SUBTYPE_DATA_OTA: /* ota data */
+                    bs->ota_info = partition.pos;
+                    partition_usage = "OTA data";
+                    break;
+                case PART_SUBTYPE_DATA_RF:
+                    partition_usage = "RF data";
+                    break;
+                case PART_SUBTYPE_DATA_WIFI:
+                    partition_usage = "WiFi data";
+                    break;
+                default:
+                    partition_usage = "Unknown data";
+                    break;
+                }
+                break; /* PARTITION_USAGE_DATA */
+            default: /* other partition type */
+                break;
+            }
+        }
+        /* invalid partition magic number */
+        else {
+            break; /* todo: validate md5 */
+        }
+
+        /* print partition type info */
+        log_info("%2d %-16s %-16s %02x %02x %08x %08x", index, partition.label, partition_usage,
+                 partition.type, partition.subtype,
+                 partition.pos.offset, partition.pos.size);
+        index++;
+        addr += sizeof(partition);
+    }
+
+    log_info("End of partition table");
+    return true;
+}
+
+static uint32_t ota_select_crc(const ota_select *s)
+{
+  return crc32_le(UINT32_MAX, (uint8_t*)&s->ota_seq, 4);
+}
+
+static bool ota_select_valid(const ota_select *s)
+{
+  return s->ota_seq != UINT32_MAX && s->crc == ota_select_crc(s);
+}
+
+/**
+ *  @function :     bootloader_main
+ *  @description:   entry function of 2nd bootloader
+ *
+ *  @inputs:        void
+ */
+
+void bootloader_main()
+{
+    //Run start routine.
+    /*ESP32 2ND bootload start here*/
+
+
+    log_info( "\n" );
+    log_info( "**************************************" );
+    log_info( "*       hello espressif ESP32!       *" );
+    log_info( "*        2nd boot is running!        *" );
+    log_info( "*            version (%s)          *", BOOT_VERSION);
+    log_info( "**************************************");
+
+    struct flash_hdr    fhdr;
+    bootloader_state_t bs;
+    SpiFlashOpResult spiRet1,spiRet2;    
+    ota_select sa,sb;
+    memset(&bs, 0, sizeof(bs));
+
+    log_notice( "compile time %s\n", __TIME__ );
+    /* close watch dog here */
+    REG_CLR_BIT( RTC_WDTCONFIG0, RTC_CNTL_WDT_FLASHBOOT_MOD_EN );
+    REG_CLR_BIT( WDTCONFIG0, TIMERS_WDT_FLASHBOOT_MOD_EN );
+    SPIUnlock();
+    /*register first sector in drom0 page 0 */
+    boot_cache_redirect( 0, 0x5000 );
+
+    memcpy((unsigned int *) &fhdr, MEM_CACHE(0x1000), sizeof(struct flash_hdr) );
+
+    print_flash_info(&fhdr);
+
+    if (!load_partition_table(&bs, PARTITION_ADD)) {
+        log_error("load partition table error!");
+        return;
+    }
+
+    partition_pos_t load_part_pos;
+
+    if (bs.ota_info.offset != 0) {              // check if partition table has OTA info partition
+        //log_error("OTA info sector handling is not implemented");
+        boot_cache_redirect(bs.ota_info.offset, bs.ota_info.size );
+        memcpy(&sa,MEM_CACHE(bs.ota_info.offset & 0x0000ffff),sizeof(sa));
+        memcpy(&sb,MEM_CACHE((bs.ota_info.offset + 0x1000)&0x0000ffff) ,sizeof(sb));
+        if(sa.ota_seq == 0xFFFFFFFF && sb.ota_seq == 0xFFFFFFFF) {
+            // init status flash
+            load_part_pos = bs.ota[0];
+            sa.ota_seq = 0x01;
+            sa.crc = ota_select_crc(&sa);
+            sb.ota_seq = 0x00;
+            sb.crc = ota_select_crc(&sb);
+
+            Cache_Read_Disable(0);  
+            spiRet1 = SPIEraseSector(bs.ota_info.offset/0x1000);       
+            spiRet2 = SPIEraseSector(bs.ota_info.offset/0x1000+1);       
+            if (spiRet1 != SPI_FLASH_RESULT_OK || spiRet2 != SPI_FLASH_RESULT_OK ) {  
+                log_error(SPI_ERROR_LOG);
+                return;
+            } 
+            spiRet1 = SPIWrite(bs.ota_info.offset,(uint32_t *)&sa,sizeof(ota_select));
+            spiRet2 = SPIWrite(bs.ota_info.offset + 0x1000,(uint32_t *)&sb,sizeof(ota_select));
+            if (spiRet1 != SPI_FLASH_RESULT_OK || spiRet2 != SPI_FLASH_RESULT_OK ) {  
+                log_error(SPI_ERROR_LOG);
+                return;
+            } 
+            Cache_Read_Enable(0);  
+            //TODO:write data in ota info
+        } else  {
+            if(ota_select_valid(&sa) && ota_select_valid(&sb)) {
+                load_part_pos = bs.ota[(((sa.ota_seq > sb.ota_seq)?sa.ota_seq:sb.ota_seq) - 1)%bs.app_count];
+            }else if(ota_select_valid(&sa)) {
+                load_part_pos = bs.ota[(sa.ota_seq - 1) % bs.app_count];
+            }else if(ota_select_valid(&sb)) {
+                load_part_pos = bs.ota[(sb.ota_seq - 1) % bs.app_count];
+            }else {
+                log_error("ota data partition info error");
+                return;
+            }
+        }
+    } else if (bs.factory.offset != 0) {        // otherwise, look for factory app partition
+        load_part_pos = bs.factory;
+    } else if (bs.test.offset != 0) {           // otherwise, look for test app parition
+        load_part_pos = bs.test;
+    } else {                                    // nothing to load, bail out
+        log_error("nothing to load");
+        return;
+    }
+
+    log_info("Loading app partition at offset %08x", load_part_pos);
+    if(fhdr.secury_boot_flag == 0x01) {
+        /* protect the 2nd_boot  */    
+        if(false == secure_boot()){
+            log_error("secure boot failed");
+            return;
+        }
+    }
+
+    if(fhdr.encrypt_flag == 0x01) {
+        /* encrypt flash */            
+        if (false == flash_encrypt(&bs)) {
+           log_error("flash encrypt failed");
+           return;
+        }
+    }
+
+    // copy sections to RAM, set up caches, and start application
+    unpack_load_app(&load_part_pos);
+}
+
+
+void unpack_load_app(const partition_pos_t* partition)
+{
+    boot_cache_redirect(partition->offset, partition->size);
+
+    uint32_t pos = 0;
+    struct flash_hdr image_header;
+    memcpy(&image_header, MEM_CACHE(pos), sizeof(image_header));
+    pos += sizeof(image_header);
+
+    uint32_t drom_addr = 0;
+    uint32_t drom_load_addr = 0;
+    uint32_t drom_size = 0;
+    uint32_t irom_addr = 0;
+    uint32_t irom_load_addr = 0;
+    uint32_t irom_size = 0;
+
+    log_debug("bin_header: %u %u %u %u %08x\n", image_header.magic,
+              image_header.blocks,
+              image_header.spi_mode,
+              image_header.spi_size,
+              (unsigned)image_header.entry_addr);
+
+    for (uint32_t section_index = 0;
+            section_index < image_header.blocks;
+            ++section_index) {
+        struct block_hdr section_header = {0};
+        memcpy(&section_header, MEM_CACHE(pos), sizeof(section_header));
+        pos += sizeof(section_header);
+
+        const uint32_t address = section_header.load_addr;
+        bool load = true;
+        bool map = false;
+        if (address == 0x00000000) {        // padding, ignore block
+            load = false;
+        }
+        if (address == 0x00000004) {
+            load = false;                   // md5 checksum block
+            // TODO: actually check md5
+        }
+
+        if (address >= DROM_LOW && address < DROM_HIGH) {
+            log_debug("found drom section, map from %08x to %08x\n", pos,
+                      section_header.load_addr);
+            drom_addr = partition->offset + pos - sizeof(section_header);
+            drom_load_addr = section_header.load_addr;
+            drom_size = section_header.data_len + sizeof(section_header);
+            load = false;
+            map = true;
+        }
+
+        if (address >= IROM_LOW && address < IROM_HIGH) {
+            log_debug("found irom section, map from %08x to %08x\n", pos,
+                      section_header.load_addr);
+            irom_addr = partition->offset + pos - sizeof(section_header);
+            irom_load_addr = section_header.load_addr;
+            irom_size = section_header.data_len + sizeof(section_header);
+            load = false;
+            map = true;
+        }
+
+        log_notice("section %d: paddr=0x%08x vaddr=0x%08x size=0x%05x (%6d) %s", section_index, pos, section_header.load_addr, section_header.data_len, section_header.data_len, (load)?"load":(map)?"map":"");
+
+        if (!load) {
+            pos += section_header.data_len;
+            continue;
+        }
+
+        memcpy((void*) section_header.load_addr, MEM_CACHE(pos), section_header.data_len);
+        pos += section_header.data_len;
+    }
+    
+    set_cache_and_start_app(drom_addr,
+        drom_load_addr,
+        drom_size,
+        irom_addr,
+        irom_load_addr,
+        irom_size,
+        image_header.entry_addr);
+}
+
+void IRAM_ATTR set_cache_and_start_app(
+    uint32_t drom_addr,
+    uint32_t drom_load_addr,
+    uint32_t drom_size,
+    uint32_t irom_addr,
+    uint32_t irom_load_addr,
+    uint32_t irom_size, 
+    uint32_t entry_addr)
+{
+    log_debug("configure drom and irom and start\n");
+    Cache_Read_Disable( 0 );
+    Cache_Read_Disable( 1 );
+    Cache_Flush( 0 );
+    Cache_Flush( 1 );
+    uint32_t drom_page_count = (drom_size + 64*1024 - 1) / (64*1024); // round up to 64k
+    log_debug( "d mmu set paddr=%08x vaddr=%08x size=%d n=%d \n", drom_addr & 0xffff0000, drom_load_addr & 0xffff0000, drom_size, drom_page_count );
+    int rc = cache_flash_mmu_set( 0, 0, drom_load_addr & 0xffff0000, drom_addr & 0xffff0000, 64, drom_page_count );
+    log_debug( "rc=%d", rc );
+    rc = cache_flash_mmu_set( 1, 0, drom_load_addr & 0xffff0000, drom_addr & 0xffff0000, 64, drom_page_count );
+    log_debug( "rc=%d", rc );
+    uint32_t irom_page_count = (irom_size + 64*1024 - 1) / (64*1024); // round up to 64k
+    log_debug( "i mmu set paddr=%08x vaddr=%08x size=%d n=%d\n", irom_addr & 0xffff0000, irom_load_addr & 0xffff0000, irom_size, irom_page_count );
+    rc = cache_flash_mmu_set( 0, 0, irom_load_addr & 0xffff0000, irom_addr & 0xffff0000, 64, irom_page_count );
+    log_debug( "rc=%d", rc );
+    rc = cache_flash_mmu_set( 1, 0, irom_load_addr & 0xffff0000, irom_addr & 0xffff0000, 64, irom_page_count );
+    log_debug( "rc=%d", rc );
+    REG_CLR_BIT( PRO_CACHE_CTRL1_REG, (DPORT_PRO_CACHE_MASK_IRAM0) | (DPORT_PRO_CACHE_MASK_IRAM1 & 0) | (DPORT_PRO_CACHE_MASK_IROM0 & 0) | DPORT_PRO_CACHE_MASK_DROM0 | DPORT_PRO_CACHE_MASK_DRAM1 );
+    REG_CLR_BIT( APP_CACHE_CTRL1_REG, (DPORT_APP_CACHE_MASK_IRAM0) | (DPORT_APP_CACHE_MASK_IRAM1 & 0) | (DPORT_APP_CACHE_MASK_IROM0 & 0) | DPORT_APP_CACHE_MASK_DROM0 | DPORT_APP_CACHE_MASK_DRAM1 );
+    Cache_Read_Enable( 0 );
+    Cache_Read_Enable( 1 );
+
+    log_notice("start: 0x%08x\n", entry_addr);
+    typedef void (*entry_t)(void);
+    entry_t entry = ((entry_t) entry_addr);
+
+    // TODO: we have used quite a bit of stack at this point.
+    // use "movsp" instruction to reset stack back to where ROM stack starts.
+    (*entry)();
+}
+
+
+void print_flash_info(struct flash_hdr* pfhdr)
+{
+#if (BOOT_LOG_LEVEL >= BOOT_LOG_LEVEL_NOTICE)
+
+    struct flash_hdr fhdr = *pfhdr;
+
+    log_debug( "[D]: magic %02x\n", fhdr.magic );
+    log_debug( "[D]: blocks %02x\n", fhdr.blocks );
+    log_debug( "[D]: spi_mode %02x\n", fhdr.spi_mode );
+    log_debug( "[D]: spi_speed %02x\n", fhdr.spi_speed );
+    log_debug( "[D]: spi_size %02x\n", fhdr.spi_size );
+
+    const char* str;
+    switch ( fhdr.spi_speed ) {
+    case SPI_SPEED_40M:
+        str = "40MHz";
+        break;
+
+    case SPI_SPEED_26M:
+        str = "26.7MHz";
+        break;
+
+    case SPI_SPEED_20M:
+        str = "20MHz";
+        break;
+
+    case SPI_SPEED_80M:
+        str = "80MHz";
+        break;
+
+    default:
+        str = "20MHz";
+        break;
+    }
+    log_notice( "  SPI Speed      : %s", str );
+
+    
+
+    switch ( fhdr.spi_mode ) {
+    case SPI_MODE_QIO:
+        str = "QIO";
+        break;
+
+    case SPI_MODE_QOUT:
+        str = "QOUT";
+        break;
+
+    case SPI_MODE_DIO:
+        str = "DIO";
+        break;
+
+    case SPI_MODE_DOUT:
+        str = "DOUT";
+        break;
+
+    case SPI_MODE_FAST_READ:
+        str = "FAST READ";
+        break;
+
+    case SPI_MODE_SLOW_READ:
+        str = "SLOW READ";
+        break;
+    default:
+        str = "DIO";
+        break;
+    }
+    log_notice( "  SPI Mode       : %s", str );
+
+    
+
+    switch ( fhdr.spi_size ) {
+    case SPI_SIZE_1MB:
+        str = "1MB";
+        break;
+
+    case SPI_SIZE_2MB:
+        str = "2MB";
+        break;
+
+    case SPI_SIZE_4MB:
+        str = "4MB";
+        break;
+
+    case SPI_SIZE_8MB:
+        str = "8MB";
+        break;
+
+    case SPI_SIZE_16MB:
+        str = "16MB";
+        break;
+
+    default:
+        str = "1MB";
+        break;
+    }
+    log_notice( "  SPI Flash Size : %s", str );
+#endif
+}

components/bootloader/src/main/eagle.bootloader.ld

@@ -0,0 +1,148 @@
+/*
+Linker file used to link the bootloader.
+
+*WARNING* For now this linker dumps everything into IRAM/DRAM. ToDo: move
+some/most stuff to DROM/IROM.
+
+*/
+
+
+/* THESE ARE THE VIRTUAL RUNTIME ADDRESSES  */
+/* The load addresses are defined later using the AT statements. */
+MEMORY
+{
+  /* All these values assume the flash cache is on, and have the blocks this uses subtracted from the length
+  of the various regions. The 'data access port' dram/drom regions map to the same iram/irom regions but
+  are connected to the data port of the CPU and eg allow bytewise access. */
+  dport0_seg (RW) :                 	org = 0x3FF00000, len = 0x10		/* IO */
+  iram_seg (RWX) :                 	org = 0x40098000, len = 0x1000		
+  iram_pool_1_seg (RWX) :           org = 0x40078000, len = 0x8000    /* IRAM POOL1, used for APP CPU cache. We can abuse it in bootloader because APP CPU is still held in reset, until we enable APP CPU cache */
+  dram_seg (RW) :                  	org = 0x3FFC0000, len = 0x20000		/* Shared RAM, minus rom bss/data/stack.*/
+}
+
+/*  Default entry point:  */
+ENTRY(call_start_cpu0);
+
+
+SECTIONS
+{
+  .iram1.text :
+  {
+    _init_start = ABSOLUTE(.);
+    *(.UserEnter.literal);
+    *(.UserEnter.text);
+    . = ALIGN (16);
+    *(.entry.text)
+    *(.init.literal)
+    *(.init)
+    _init_end = ABSOLUTE(.);
+
+	  /* Code marked as runnning out of IRAM */
+	  _iram_text_start = ABSOLUTE(.);
+    *(.iram1 .iram1.*)
+	  _iram_text_end = ABSOLUTE(.);
+  } > iram_seg
+
+
+  /* Shared RAM */
+  .dram0.bss (NOLOAD) :
+  {
+    . = ALIGN (8);
+    _bss_start = ABSOLUTE(.);
+    *(.dynsbss)
+    *(.sbss)
+    *(.sbss.*)
+    *(.gnu.linkonce.sb.*)
+    *(.scommon)
+    *(.sbss2)
+    *(.sbss2.*)
+    *(.gnu.linkonce.sb2.*)
+    *(.dynbss)
+    KEEP(*(.bss))
+    *(.bss.*)
+    *(.gnu.linkonce.b.*)
+    *(COMMON)
+    . = ALIGN (8);
+    _bss_end = ABSOLUTE(.);
+  } >dram_seg
+
+
+  .dram0.data :
+  {
+    _data_start = ABSOLUTE(.);
+    KEEP(*(.data))
+    KEEP(*(.data.*))
+    KEEP(*(.gnu.linkonce.d.*))
+    KEEP(*(.data1))
+    KEEP(*(.sdata))
+    KEEP(*(.sdata.*))
+    KEEP(*(.gnu.linkonce.s.*))
+    KEEP(*(.sdata2))
+    KEEP(*(.sdata2.*))
+    KEEP(*(.gnu.linkonce.s2.*))
+    KEEP(*(.jcr))
+    _data_end = ABSOLUTE(.);
+  } >dram_seg
+
+
+
+
+  .dram0.rodata :
+  {
+    _rodata_start = ABSOLUTE(.);
+    *(.rodata)
+    *(.rodata.*)
+	*(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */
+    *(.gnu.linkonce.r.*)
+    *(.rodata1)
+    __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);
+    *(.xt_except_table)
+    *(.gcc_except_table)
+    *(.gnu.linkonce.e.*)
+    *(.gnu.version_r)
+    *(.eh_frame)
+    . = (. + 3) & ~ 3;
+    /*  C++ constructor and destructor tables, properly ordered:  */
+    __init_array_start = ABSOLUTE(.);
+    KEEP (*crtbegin.o(.ctors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+    __init_array_end = ABSOLUTE(.);
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+    /*  C++ exception handlers table:  */
+    __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);
+    *(.xt_except_desc)
+    *(.gnu.linkonce.h.*)
+    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
+    *(.xt_except_desc_end)
+    *(.dynamic)
+    *(.gnu.version_d)
+    _rodata_end = ABSOLUTE(.);
+	/* Literals are also RO data. */
+    _lit4_start = ABSOLUTE(.);
+    *(*.lit4)
+    *(.lit4.*)
+    *(.gnu.linkonce.lit4.*)
+    _lit4_end = ABSOLUTE(.);
+    . = ALIGN(4);
+    _heap_start = ABSOLUTE(.);
+  } >dram_seg
+
+  .iram_pool_1.text :
+  {
+    _stext = .;
+    _text_start = ABSOLUTE(.);
+    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
+	*(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */
+    *(.fini.literal)
+    *(.fini)
+    *(.gnu.version)
+    _text_end = ABSOLUTE(.);
+    _etext = .;
+  } >iram_pool_1_seg
+
+}

components/bootloader/src/main/flash_encrypt.c

@@ -0,0 +1,190 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#include <string.h>
+
+#include "esp_types.h"
+#include "esp_attr.h"
+
+#include "rom/cache.h"
+#include "rom/ets_sys.h"
+#include "rom/spi_flash.h"
+
+#include "soc/dport_reg.h"
+#include "soc/io_mux_reg.h"
+#include "soc/efuse_reg.h"
+#include "soc/rtc_cntl_reg.h"
+
+#include "sdkconfig.h"
+
+#include "bootloader_log.h"
+#include "bootloader_config.h"
+
+/**
+ *  @function :     bitcount
+ *  @description:   caculate bit 1 in flash_crypt_cnt 
+ *                  if it's even number ,need encrypt flash data,and burn efuse 
+ *
+ *  @inputs:        n     flash_crypt_cnt               
+ *  @return:        number of 1 in flash_crypt_cnt
+ *                  
+ */
+int bitcount(int n){
+   int count = 0;  
+   while (n > 0) {   
+       count += n & 1;  
+       n >>= 1;  
+   }   
+   return count;
+
+}
+/**
+ *  @function :     flash_encrypt_write
+ *  @description:   write encrypted data in flash
+ *
+ *  @inputs:        pos     address in flash
+ *                  len    size of data need encrypt                
+ *  @return:        return true, if the write flash success
+ *                  
+ */
+bool flash_encrypt_write(uint32_t pos, uint32_t len)
+{
+   SpiFlashOpResult spiRet;    
+   uint32_t buf[1024];
+   int i = 0;
+   Cache_Read_Disable(0);  
+   for (i = 0;i<((len-1)/0x1000 + 1);i++) {
+       spiRet = SPIRead(pos, buf, SPI_SEC_SIZE);     
+       if (spiRet != SPI_FLASH_RESULT_OK) {   
+           Cache_Read_Enable(0); 
+           log_error(SPI_ERROR_LOG);
+           return false;    
+       }    
+       spiRet = SPIEraseSector(pos/SPI_SEC_SIZE);    
+       if (spiRet != SPI_FLASH_RESULT_OK) { 
+           Cache_Read_Enable(0);
+           log_error(SPI_ERROR_LOG);
+           return false;      
+       }
+       spiRet = SPI_Encrypt_Write(pos, buf, SPI_SEC_SIZE);
+       if (spiRet != SPI_FLASH_RESULT_OK) {    
+           Cache_Read_Enable(0); 
+           log_error(SPI_ERROR_LOG);
+           return false;       
+       }   
+       pos += SPI_SEC_SIZE;
+   }
+   Cache_Read_Enable(0); 
+   return true;
+}
+/**
+ *  @function :     flash_encrypt
+ *  @description:   encrypt 2nd boot ,partition table ,factory bin ��test bin (if use)��ota bin
+ *                  ��OTA info sector.
+ *
+ *  @inputs:        bs     bootloader state structure used to save the data
+ *                 
+ *  @return:        return true, if the encrypt flash success
+ *                  
+ */
+bool flash_encrypt(bootloader_state_t *bs)
+{
+   uint32_t bin_len = 0;
+   uint32_t flash_crypt_cnt = REG_GET_FIELD(EFUSE_BLK0_RDATA0, EFUSE_FLASH_CRYPT_CNT);
+   uint8_t count = bitcount(flash_crypt_cnt);
+   int i = 0;
+   log_debug("flash crypt cnt %x, count %d\n", flash_crypt_cnt, count); 
+
+   if ((count % 2) == 0) {    
+       boot_cache_redirect( 0, 64*1024);
+        /* encrypt iv and abstruct */ 
+       if (false == flash_encrypt_write(0,SPI_SEC_SIZE)) {
+           log_error("encrypt iv and abstruct error"); 
+           return false;
+       }
+
+        /* encrypt write boot bin*/
+       bin_len = get_bin_len((uint32_t)MEM_CACHE(0x1000));
+       if(bin_len != 0) {
+           if (false == flash_encrypt_write(0x1000,bin_len)) {
+               log_error("encrypt 2nd boot error"); 
+               return false;
+           }
+       } else {
+           log_error("2nd boot len error"); 
+           return false;
+       }
+        /* encrypt partition table */
+       if (false ==  flash_encrypt_write(PARTITION_ADD,SPI_SEC_SIZE)) {
+           log_error("encrypt partition table error"); 
+           return false;
+       }
+
+        /* encrypt write factory bin  */
+       if(bs->factory.offset != 0x00) {
+           log_debug("have factory bin\n");
+           boot_cache_redirect(bs->factory.offset,bs->factory.size);
+           bin_len = get_bin_len((uint32_t)MEM_CACHE(bs->factory.offset&0xffff));
+           if(bin_len != 0) {           
+               if (false ==  flash_encrypt_write(bs->factory.offset,bin_len)) {
+                   log_error("encrypt factory bin error"); 
+                   return false;
+               }
+           }
+       }
+        /* encrypt write test bin  */
+       if(bs->test.offset != 0x00) {
+           ets_printf("have test bin\n");
+           boot_cache_redirect(bs->test.offset,bs->test.size);
+           bin_len = get_bin_len((uint32_t)MEM_CACHE(bs->test.offset&0xffff));
+           if(bin_len != 0) {
+               if (false ==  flash_encrypt_write(bs->test.offset,bin_len)) {
+                   log_error("encrypt test bin error"); 
+                   return false;
+               }
+           }
+       }
+        /* encrypt write ota bin  */
+       for (i = 0;i<16;i++) {
+           if(bs->ota[i].offset != 0x00) {
+               log_debug("have ota[%d] bin\n",i);
+               boot_cache_redirect(bs->ota[i].offset,bs->ota[i].size);
+               bin_len = get_bin_len((uint32_t)MEM_CACHE(bs->ota[i].offset&0xffff));
+               if(bin_len != 0) {    
+                   if (false == flash_encrypt_write(bs->ota[i].offset,bin_len)) {
+                       log_error("encrypt ota bin error"); 
+                       return false;
+                   }
+               }
+           }
+       }
+        /* encrypt write ota info bin  */
+       if (false == flash_encrypt_write(bs->ota_info.offset,2*SPI_SEC_SIZE)) {
+           log_error("encrypt ota binfo error"); 
+           return false;
+       }  
+       REG_SET_FIELD(EFUSE_BLK0_WDATA0, EFUSE_FLASH_CRYPT_CNT, 0x04);   
+       REG_WRITE(EFUSE_CONF, 0x5A5A);  /* efuse_pgm_op_ena, force no rd/wr disable */     
+       REG_WRITE(EFUSE_CMD,  0x02);    /* efuse_pgm_cmd */     
+       while (REG_READ(EFUSE_CMD));    /* wait for efuse_pagm_cmd=0 */
+       log_warn("burn  flash_crypt_cnt\n");   
+       REG_WRITE(EFUSE_CONF, 0x5AA5);  /* efuse_read_op_ena, release force */   
+       REG_WRITE(EFUSE_CMD,  0x01);    /* efuse_read_cmd */     
+       while (REG_READ(EFUSE_CMD));    /* wait for efuse_read_cmd=0 */  
+       return true;
+   } else {   
+       log_info("flash already encrypted.\n"); 
+       return true;
+   }
+}

components/bootloader/src/main/secure_boot.c

@@ -0,0 +1,125 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#include <string.h>
+
+#include "esp_attr.h"
+#include "esp_types.h"
+
+#include "rom/cache.h"
+#include "rom/ets_sys.h"
+#include "rom/spi_flash.h"
+#include "rom/secure_boot.h"
+
+#include "soc/dport_reg.h"
+#include "soc/io_mux_reg.h"
+#include "soc/efuse_reg.h"
+#include "soc/rtc_cntl_reg.h"
+
+#include "sdkconfig.h"
+
+#include "bootloader_log.h"
+#include "bootloader_config.h"
+
+/**
+ *  @function :     secure_boot_generate
+ *  @description:   generate boot abstruct & iv 
+ *
+ *  @inputs:        bool
+ */
+bool secure_boot_generate(uint32_t bin_len){
+	SpiFlashOpResult spiRet;
+	uint16_t i;
+	uint32_t buf[32];
+	if (bin_len % 128 != 0) {  
+		bin_len = (bin_len / 128 + 1) * 128; 
+	} 
+	ets_secure_boot_start();
+	ets_secure_boot_rd_iv(buf);
+	ets_secure_boot_hash(NULL);
+	Cache_Read_Disable(0);
+	/* iv stored in sec 0 */ 
+	spiRet = SPIEraseSector(0);
+	if (spiRet != SPI_FLASH_RESULT_OK)
+	{   
+		log_error(SPI_ERROR_LOG);
+		return false;
+	}
+	/* write iv to flash, 0x0000, 128 bytes (1024 bits) */
+	spiRet = SPIWrite(0, buf, 128);
+	if (spiRet != SPI_FLASH_RESULT_OK) 
+	{
+		log_error(SPI_ERROR_LOG);
+		return false;
+	}
+	log_debug("write iv to flash.\n");
+	Cache_Read_Enable(0);
+	/* read 4K code image from flash, for test */
+	for (i = 0; i < bin_len; i+=128) {
+		ets_secure_boot_hash((uint32_t *)(0x3f400000 + 0x1000 + i));
+	}
+
+	ets_secure_boot_obtain();
+	ets_secure_boot_rd_abstract(buf);
+	ets_secure_boot_finish();
+	Cache_Read_Disable(0);
+	/* write abstract to flash, 0x0080, 64 bytes (512 bits) */
+	spiRet = SPIWrite(0x80, buf, 64);
+	if (spiRet != SPI_FLASH_RESULT_OK) {
+		log_error(SPI_ERROR_LOG);
+		return false;
+	}
+	log_debug("write abstract to flash.\n");
+	Cache_Read_Enable(0);
+	return true;
+}
+
+
+/**
+ *  @function :     secure_boot
+ *  @description:   protect boot code inflash
+ *
+ *  @inputs:        bool
+ */
+bool secure_boot(void){ 
+	uint32_t bin_len = 0;
+	if (REG_READ(EFUSE_BLK0_RDATA6) & EFUSE_RD_ABS_DONE_0)
+	{     
+		log_info("already secure boot !\n"); 
+		return true;
+	} else {  
+		boot_cache_redirect( 0, 64*1024);
+		bin_len = get_bin_len((uint32_t)MEM_CACHE(0x1000));
+		if (bin_len == 0) {
+			log_error("boot len is error");
+			return false;
+		}
+		if (false == secure_boot_generate(bin_len)){
+			log_error("secure boot generate failed");
+			return false;
+		}  
+	}  
+
+	REG_SET_BIT(EFUSE_BLK0_WDATA6, EFUSE_RD_ABS_DONE_0); 
+	REG_WRITE(EFUSE_CONF, 0x5A5A);  /* efuse_pgm_op_ena, force no rd/wr disable */     
+	REG_WRITE(EFUSE_CMD,  0x02);    /* efuse_pgm_cmd */    
+	while (REG_READ(EFUSE_CMD));    /* wait for efuse_pagm_cmd=0 */   
+	log_warn("burn abstract_done_0\n");   
+	REG_WRITE(EFUSE_CONF, 0x5AA5);  /* efuse_read_op_ena, release force */   
+	REG_WRITE(EFUSE_CMD,  0x01);    /* efuse_read_cmd */     
+	while (REG_READ(EFUSE_CMD));    /* wait for efuse_read_cmd=0 */       
+	log_debug("read EFUSE_BLK0_RDATA6 %x\n", REG_READ(EFUSE_BLK0_RDATA6)); 
+	return true;
+
+}

components/bt/Kconfig

@@ -0,0 +1,23 @@
+menu "BT config"
+visible if MEMMAP_BT
+
+
+config BT_ENABLED
+	bool "Enable low-level BT stack"
+	depends on MEMMAP_BT
+	help
+		This compiles in the low-level BT stack.
+
+config BT_BTLE
+	bool "Enable BTLE"
+	depends on BT_ENABLED
+	help
+		This compiles BTLE support
+
+config BT_BT
+	bool "Enable classic BT"
+	depends on BT_ENABLED
+	help
+		This enables classic BT support
+
+endmenu

components/esp32/Kconfig

@@ -0,0 +1,39 @@
+menu "WiFi config"
+
+config WIFI_ENABLED
+    bool "Enable low-level WiFi stack"
+    default "y"
+    help
+        This compiles in the low-level WiFi stack.
+
+config WIFI_AUTO_STARTUP
+    bool "Start WiFi with system startup"
+    default "y"
+    depends on WIFI_ENABLED
+    help
+        By default, WiFi is started with system startup, you can turn off this
+        feature and start by yourself.
+
+config WIFI_AUTO_CONNECT
+    bool "Enable auto connect"
+    default "y"
+    depends on WIFI_ENABLED
+    help
+        If station is enabled, and station config is set, this will enable WiFi
+        station auto connect when WiFi startup.
+
+config WIFI_ENENT_QUEUE_SIZE
+    int "WiFi event queue size"
+    default 32
+    depends on WIFI_ENABLED
+    help
+        Config WiFi event queue size in different application.
+
+config WIFI_EVENT_TASK_STACK_SIZE
+    int "WiFi event task stack size"
+    default 2048
+    depends on WIFI_ENABLED
+    help
+        Config WiFi event task stack size in different application.
+
+endmenu

components/esp32/Makefile

@@ -0,0 +1,20 @@
+#
+# Component Makefile
+#
+# This Makefile should, at the very least, just include $(SDK_PATH)/make/component.mk. By default, 
+# this will take the sources in this directory, compile them and link them into 
+# lib(subdirectory_name).a in the build directory. This behaviour is entirely configurable,
+# please read the SDK documents if you need to do this.
+#
+
+LIBS := crypto core net80211 phy rtc pp wpa wps
+                           
+COMPONENT_ADD_LDFLAGS := -lesp32 \
+                           $(abspath libhal.a) \
+                           -L$(abspath lib) \
+                           $(addprefix -l,$(LIBS)) \
+                          -L $(abspath ld) \
+                          -T eagle.fpga32.v7.ld \
+                          -T eagle.fpga32.rom.addr.v7.ld 
+
+include $(SDK_PATH)/make/component.mk

components/esp32/abi.cpp

@@ -0,0 +1,114 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#include <stdlib.h>
+#include <assert.h>
+#include <cxxabi.h>
+#include <stdint.h>
+
+// using __cxxabiv1::__guard;
+
+void *operator new(size_t size)
+{
+    return malloc(size);
+}
+
+void *operator new[](size_t size)
+{
+    return malloc(size);
+}
+
+void operator delete(void * ptr)
+{
+    free(ptr);
+}
+
+void operator delete[](void * ptr)
+{
+    free(ptr);
+}
+
+extern "C" void __cxa_pure_virtual(void) __attribute__ ((__noreturn__));
+extern "C" void __cxa_deleted_virtual(void) __attribute__ ((__noreturn__));
+
+void __cxa_pure_virtual(void)
+{
+    abort();
+}
+
+void __cxa_deleted_virtual(void)
+{
+    abort();
+}
+
+#if 0
+typedef struct {
+    uint8_t guard;
+    uint8_t ps;
+} guard_t;
+
+extern "C" int __cxa_guard_acquire(__guard* pg)
+{
+    uint8_t ps = xt_rsil(15);
+    if (reinterpret_cast<guard_t*>(pg)->guard) {
+        xt_wsr_ps(ps);
+        return 0;
+    }
+    reinterpret_cast<guard_t*>(pg)->ps = ps;
+    return 1;
+}
+
+extern "C" void __cxa_guard_release(__guard* pg)
+{
+    reinterpret_cast<guard_t*>(pg)->guard = 1;
+    xt_wsr_ps(reinterpret_cast<guard_t*>(pg)->ps);
+}
+
+extern "C" void __cxa_guard_abort(__guard* pg)
+{
+    xt_wsr_ps(reinterpret_cast<guard_t*>(pg)->ps);
+}
+#endif
+
+extern "C" void __cxa_throw_bad_array_new_length()
+{
+    abort();
+}
+
+namespace std
+{
+void __throw_bad_function_call()
+{
+    abort();
+}
+
+void __throw_length_error(char const*)
+{
+    abort();
+}
+
+void __throw_bad_alloc()
+{
+    abort();
+}
+
+void __throw_logic_error(const char* str)
+{
+    abort();
+}
+
+void __throw_out_of_range(const char* str)
+{
+    abort();
+}
+}

components/esp32/cpu_start.c

@@ -0,0 +1,259 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#include <stdint.h>
+#include <string.h>
+
+#include "esp_attr.h"
+#include "esp_err.h"
+
+#include "rom/ets_sys.h"
+
+#include "soc/dport_reg.h"
+#include "soc/io_mux_reg.h"
+
+#include "freertos/FreeRTOS.h"
+#include "freertos/task.h"
+#include "freertos/semphr.h"
+#include "freertos/queue.h"
+#include "freertos/portmacro.h"
+
+#include "tcpip_adapter.h"
+
+#include "heap_alloc_caps.h"
+#include "sdkconfig.h"
+#include "esp_system.h"
+#include "esp_spi_flash.h"
+#include "nvs_flash.h"
+#include "esp_event.h"
+
+static void IRAM_ATTR user_start_cpu0(void);
+static void IRAM_ATTR call_user_start_cpu1();
+static void IRAM_ATTR user_start_cpu1(void);
+void Cache_Read_Enable();
+extern void ets_setup_syscalls(void);
+
+
+extern int __cpu1_entry_point;
+extern int _bss_start;
+extern int _bss_end;
+extern int _init_start;
+extern int _init_end;
+extern int _iram_romjumptable_start;
+extern int _iram_romjumptable_end;
+extern int _iram_text_start;
+extern int _iram_text_end;
+
+/*
+We arrive here after the bootloader finished loading the program from flash. The hardware is mostly uninitialized,
+flash cache is down and the app CPU is in reset. We do have a stack, so we can do the initialization in C.
+*/
+
+void Uart_Init(int no);
+void uartAttach();
+void ets_set_appcpu_boot_addr(uint32_t ent);
+int ets_getAppEntry();
+
+void IRAM_ATTR call_user_start_cpu0() {
+	//Kill wdt
+	REG_CLR_BIT(0x3ff4808c, BIT(10)); //RTCCNTL+8C RTC_WDTCONFIG0 RTC_
+	REG_CLR_BIT(0x6001f048, BIT(14)); //DR_REG_BB_BASE+48
+
+	//Move exception vectors to IRAM
+	asm volatile (\
+		"wsr	%0, vecbase\n" \
+		::"r"(&_init_start));
+
+	uartAttach();
+	ets_install_uart_printf();
+
+	//Make page 0 access raise an exception
+	//Also some other unused pages so we can catch weirdness
+	//ToDo: this but nicer.
+	asm volatile (\
+		"movi a4,0x00000000\n" \
+		"movi a5,0xf\n" \
+		"wdtlb a5,a4\n" \
+		"witlb a5,a4\n" \
+		"movi a4,0x80000000\n" \
+		"wdtlb a5,a4\n" \
+		"witlb a5,a4\n" \
+		"movi a4,0xa0000000\n" \
+		"wdtlb a5,a4\n" \
+		"witlb a5,a4\n" \
+		"movi a4,0xc0000000\n" \
+		"wdtlb a5,a4\n" \
+		"witlb a5,a4\n" \
+		"movi a4,0xe0000000\n" \
+		"wdtlb a5,a4\n" \
+		"witlb a5,a4\n" \
+		"movi a4,0x20000000\n" \
+		"movi a5,0x0\n" \
+		"wdtlb a5,a4\n" \
+		"witlb a5,a4\n" \
+		"movi a4,0x40000000\n" \
+		"movi a5,0x2\n" \
+		"wdtlb a5,a4\n" \
+		"witlb a5,a4\n" \
+		"isync\n" \
+		:::"a4","a5");
+
+	memset(&_bss_start, 0, (&_bss_end - &_bss_start) * sizeof(_bss_start));
+
+	//Initialize heap allocator
+	heap_alloc_caps_init();
+
+	ets_printf("Pro cpu up.\n");
+#ifndef CONFIG_FREERTOS_UNICORE
+	ets_printf("Running app cpu, entry point is %p\n", call_user_start_cpu1);
+	ets_delay_us(60000);
+
+	SET_PERI_REG_MASK(APPCPU_CTRL_REG_B, DPORT_APPCPU_CLKGATE_EN);
+	SET_PERI_REG_MASK(APPCPU_CTRL_REG_A, DPORT_APPCPU_RESETTING);
+	CLEAR_PERI_REG_MASK(APPCPU_CTRL_REG_A, DPORT_APPCPU_RESETTING);
+
+
+	for (int i=0; i<20; i++) ets_delay_us(40000);
+	ets_set_appcpu_boot_addr((uint32_t)call_user_start_cpu1);
+
+	ets_delay_us(10000);
+	
+//	while (ets_getAppEntry()==(int)call_user_start_cpu1) ;
+	//Because of Reasons (tm), the pro cpu cannot use the SPI flash while the app cpu is booting.
+//	while(((READ_PERI_REG(RTC_STORE7))&BIT(31)) == 0) ; // check APP boot complete flag
+	ets_delay_us(50000);
+	ets_delay_us(50000);
+	ets_printf("\n\nBack to pro cpu.\n");
+#else
+	CLEAR_PERI_REG_MASK(APPCPU_CTRL_REG_B, DPORT_APPCPU_CLKGATE_EN);
+#endif
+	user_start_cpu0();
+}
+
+
+extern int xPortGetCoreID();
+
+extern int _init_start;
+
+/*
+We arrive here because the pro CPU pulled us from reset. IRAM is in place, cache is still disabled, we can execute C code.
+*/
+void IRAM_ATTR call_user_start_cpu1() {
+	//We need to do this ASAP because otherwise the structure to catch the SYSCALL instruction, which
+	//we abuse to do ROM calls, won't work.
+
+	asm volatile (\
+		"wsr	%0, vecbase\n" \
+		::"r"(&_init_start));
+
+	//Enable SPI flash
+//	PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA3_U, FUNC_SD_DATA3_SPIWP); // swap PIN SDDATA3 from uart1 to spi, because cache need spi
+
+	ets_printf("App cpu up\n");
+	
+	//Make page 0 access raise an exception
+	//Also some other unused pages so we can catch weirdness
+	//ToDo: this but nicer.
+	asm volatile (\
+		"movi a4,0x00000000\n" \
+		"movi a5,0xf\n" \
+		"wdtlb a5,a4\n" \
+		"witlb a5,a4\n" \
+		"movi a4,0x80000000\n" \
+		"wdtlb a5,a4\n" \
+		"witlb a5,a4\n" \
+		"movi a4,0xa0000000\n" \
+		"wdtlb a5,a4\n" \
+		"witlb a5,a4\n" \
+		"movi a4,0xc0000000\n" \
+		"wdtlb a5,a4\n" \
+		"witlb a5,a4\n" \
+		"movi a4,0xe0000000\n" \
+		"wdtlb a5,a4\n" \
+		"witlb a5,a4\n" \
+		"movi a4,0x20000000\n" \
+		"movi a5,0x0\n" \
+		"wdtlb a5,a4\n" \
+		"witlb a5,a4\n" \
+		"movi a4,0x40000000\n" \
+		"movi a5,0x2\n" \
+		"wdtlb a5,a4\n" \
+		"witlb a5,a4\n" \
+		"isync\n" \
+		:::"a4","a5");
+	
+	user_start_cpu1();
+}
+
+
+
+extern volatile int port_xSchedulerRunning;
+extern int xPortStartScheduler();
+
+void user_start_cpu1(void) {
+	ets_printf("App cpu is running!\n");
+	//Wait for the freertos initialization is finished on CPU0
+	while (port_xSchedulerRunning == 0) ;
+	ets_printf("Core0 started initializing FreeRTOS. Jumping to scheduler.\n");
+	//Okay, start the scheduler!
+	xPortStartScheduler();
+}
+
+extern void (*__init_array_start)(void);
+extern void (*__init_array_end)(void);
+
+extern esp_err_t app_main();
+static void do_global_ctors(void) {
+    void (**p)(void);
+    for(p = &__init_array_start; p != &__init_array_end; ++p)
+        (*p)();
+}
+
+
+void user_start_cpu0(void) {
+	esp_err_t ret;
+
+	ets_setup_syscalls();
+	do_global_ctors();
+
+#if 1 //workaround
+    for (uint8_t i = 5; i < 8; i++) {
+        ets_printf("erase sector %d\n", i);
+        spi_flash_erase_sector(i);
+    }
+#endif
+    ets_printf("nvs_flash_init\n");
+    ret = nvs_flash_init(5, 3);
+    if (ESP_OK != ret) {
+        ets_printf("nvs_flash_init fail, ret=%d\n", ret);
+    }
+
+    system_init();
+
+    esp_event_init(NULL);
+
+	// TODO: consider ethernet interface
+#if CONFIG_WIFI_ENABLED
+    tcpip_adapter_init();
+#endif
+
+#if CONFIG_WIFI_ENABLED && CONFIG_WIFI_AUTO_STARTUP
+#include "esp_wifi.h"
+	esp_wifi_startup(app_main);
+#else
+	app_main();
+#endif
+
+	vTaskStartScheduler();
+}
+

components/esp32/event.c

@@ -0,0 +1,306 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#include <stddef.h>
+#include <stdlib.h>
+
+#include "esp_err.h"
+#include "esp_wifi.h"
+#include "esp_event.h"
+
+#include "freertos/FreeRTOS.h"
+#include "freertos/task.h"
+#include "freertos/queue.h"
+#include "freertos/semphr.h"
+
+#include "tcpip_adapter.h"
+
+#define ESP32_WORKAROUND 1
+
+#if CONFIG_WIFI_ENABLED
+
+#ifdef ESP32_WORKAROUND
+
+extern SemaphoreHandle_t stdio_mutex_tx;
+#define os_printf(fmt, ...) do {\
+    if (!stdio_mutex_tx) {\
+        stdio_mutex_tx = xSemaphoreCreateMutex();\
+    }\
+\
+    xSemaphoreTake(stdio_mutex_tx, portMAX_DELAY);\
+    ets_printf(fmt, ##__VA_ARGS__);\
+    xSemaphoreGive(stdio_mutex_tx);\
+} while (0)
+
+#endif
+
+static xQueueHandle g_event_handler = NULL;
+static system_event_cb_t g_event_handler_cb;
+
+#define WIFI_DEBUG  os_printf
+#define WIFI_API_CALL_CHECK(info, api_call, ret) \
+do{\
+    esp_err_t __err = (api_call);\
+    if ((ret) != __err) {\
+        WIFI_DEBUG("%s %d %s ret=%d\n", __FUNCTION__, __LINE__, (info), __err);\
+        return __err;\
+    }\
+} while(0)
+
+typedef esp_err_t (*system_event_handle_fn_t)(system_event_t *e);
+typedef struct {
+    system_event_id_t event_id;
+    system_event_handle_fn_t event_handle;
+} system_event_handle_t;
+
+
+static esp_err_t system_event_ap_start_handle_default(system_event_t *event);
+static esp_err_t system_event_ap_stop_handle_default(system_event_t *event);
+static esp_err_t system_event_sta_start_handle_default(system_event_t *event);
+static esp_err_t system_event_sta_stop_handle_default(system_event_t *event);
+static esp_err_t system_event_sta_connected_handle_default(system_event_t *event);
+static esp_err_t system_event_sta_disconnected_handle_default(system_event_t *event);
+
+static system_event_handle_t g_system_event_handle_table[] = {
+    {SYSTEM_EVENT_WIFI_READY,          NULL},
+    {SYSTEM_EVENT_SCAN_DONE,           NULL},
+    {SYSTEM_EVENT_STA_START,           system_event_sta_start_handle_default},
+    {SYSTEM_EVENT_STA_STOP,            system_event_sta_stop_handle_default},
+    {SYSTEM_EVENT_STA_CONNECTED,       system_event_sta_connected_handle_default},
+    {SYSTEM_EVENT_STA_DISCONNECTED,    system_event_sta_disconnected_handle_default},
+    {SYSTEM_EVENT_STA_AUTHMODE_CHANGE, NULL},
+    {SYSTEM_EVENT_AP_START,            system_event_ap_start_handle_default},
+    {SYSTEM_EVENT_AP_STOP,             system_event_ap_stop_handle_default},
+    {SYSTEM_EVENT_AP_STACONNECTED,     NULL},
+    {SYSTEM_EVENT_AP_STADISCONNECTED,  NULL},
+    {SYSTEM_EVENT_AP_PROBEREQRECVED,   NULL},
+    {SYSTEM_EVENT_MAX,                 NULL},
+};
+
+esp_err_t system_event_ap_start_handle_default(system_event_t *event)
+{
+    struct ip_info ap_ip;
+    uint8_t ap_mac[6];
+
+    WIFI_API_CALL_CHECK("esp_wifi_reg_rxcb", esp_wifi_reg_rxcb(WIFI_IF_AP, (wifi_rxcb_t)tcpip_adapter_ap_input), ESP_OK);
+    WIFI_API_CALL_CHECK("esp_wifi_mac_get",  esp_wifi_get_mac(WIFI_IF_AP, ap_mac), ESP_OK);
+
+    tcpip_adapter_get_ip_info(TCPIP_ADAPTER_IF_AP, &ap_ip);
+    tcpip_adapter_start(TCPIP_ADAPTER_IF_AP, ap_mac, &ap_ip);
+
+    return ESP_OK;
+}
+
+esp_err_t system_event_ap_stop_handle_default(system_event_t *event)
+{
+    WIFI_API_CALL_CHECK("esp_wifi_reg_rxcb", esp_wifi_reg_rxcb(WIFI_IF_AP, NULL), ESP_OK);
+
+    tcpip_adapter_stop(TCPIP_ADAPTER_IF_AP);
+
+    return ESP_OK;
+}
+
+esp_err_t system_event_sta_start_handle_default(system_event_t *event)
+{
+    struct ip_info sta_ip;
+    uint8_t sta_mac[6];
+
+    WIFI_API_CALL_CHECK("esp_wifi_mac_get",  esp_wifi_get_mac(WIFI_IF_STA, sta_mac), ESP_OK);
+    tcpip_adapter_get_ip_info(TCPIP_ADAPTER_IF_STA, &sta_ip);
+    tcpip_adapter_start(TCPIP_ADAPTER_IF_STA, sta_mac, &sta_ip);
+
+    return ESP_OK;
+}
+
+esp_err_t system_event_sta_stop_handle_default(system_event_t *event)
+{
+    tcpip_adapter_stop(TCPIP_ADAPTER_IF_STA);
+
+    return ESP_OK;
+}
+
+esp_err_t system_event_sta_connected_handle_default(system_event_t *event)
+{
+    WIFI_API_CALL_CHECK("esp_wifi_reg_rxcb", esp_wifi_reg_rxcb(WIFI_IF_STA, (wifi_rxcb_t)tcpip_adapter_sta_input), ESP_OK);
+
+    tcpip_adapter_up(TCPIP_ADAPTER_IF_STA);
+    tcpip_adapter_dhcpc_start(TCPIP_ADAPTER_IF_STA);
+
+    return ESP_OK;
+}
+
+esp_err_t system_event_sta_disconnected_handle_default(system_event_t *event)
+{
+    tcpip_adapter_down(TCPIP_ADAPTER_IF_STA);
+    WIFI_API_CALL_CHECK("esp_wifi_reg_rxcb", esp_wifi_reg_rxcb(WIFI_IF_STA, NULL), ESP_OK);
+    return ESP_OK;
+}
+
+static esp_err_t esp_wifi_post_event_to_user(system_event_t *event)
+{
+    if (g_event_handler_cb) {
+        return (*g_event_handler_cb)(event);
+    }
+
+    return ESP_OK;
+}
+
+static esp_err_t esp_system_event_debug(system_event_t *event)
+{
+    system_event_sta_scan_done_t *scan_done;
+    system_event_sta_connected_t *connected; 
+    system_event_sta_disconnected_t *disconnected;
+    system_event_sta_authmode_change_t *auth_change;
+    system_event_ap_staconnected_t *staconnected;
+    system_event_ap_stadisconnected_t *stadisconnected;
+    system_event_ap_probe_req_rx_t *ap_probereqrecved;
+
+    if (event == NULL) {
+        os_printf("Error: event is null!\n");
+        return ESP_FAIL;
+    }
+
+    os_printf("received event: ");
+    switch (event->event_id) {
+        case SYSTEM_EVENT_WIFI_READY:
+            os_printf("SYSTEM_EVENT_WIFI_READY\n");
+            break;
+        case SYSTEM_EVENT_SCAN_DONE:
+            scan_done = &event->event_info.scan_done;
+            os_printf("SYSTEM_EVENT_SCAN_DONE\nstatus:%d, number:%d\n", \
+                scan_done->status, scan_done->number);
+            break;
+        case SYSTEM_EVENT_STA_START:
+            os_printf("SYSTEM_EVENT_STA_START\n");
+            break;
+        case SYSTEM_EVENT_STA_STOP:
+            os_printf("SYSTEM_EVENT_STA_STOP\n");
+            break;
+        case SYSTEM_EVENT_STA_CONNECTED:
+            connected = &event->event_info.connected;
+            os_printf("SYSTEM_EVENT_STA_CONNECTED\nssid:%s, ssid_len:%d, bssid:%02x:%02x:%02x:%02x:%02x:%02x, channel:%d\n", \
+                connected->ssid, connected->ssid_len, connected->bssid[0], connected->bssid[0], connected->bssid[1], \
+                connected->bssid[3], connected->bssid[4], connected->bssid[5], connected->channel);
+            break;
+        case SYSTEM_EVENT_STA_DISCONNECTED:
+            disconnected = &event->event_info.disconnected;
+            os_printf("SYSTEM_EVENT_STA_DISCONNECTED\nssid:%s, ssid_len:%d, bssid:%02x:%02x:%02x:%02x:%02x:%02x, reason:%d\n", \
+                disconnected->ssid, disconnected->ssid_len, disconnected->bssid[0], disconnected->bssid[0], disconnected->bssid[1], \
+                disconnected->bssid[3], disconnected->bssid[4], disconnected->bssid[5], disconnected->reason);
+            break;
+        case SYSTEM_EVENT_STA_AUTHMODE_CHANGE:
+            auth_change = &event->event_info.auth_change;
+            os_printf("SYSTEM_EVENT_STA_AUTHMODE_CHNAGE\nold_mode:%d, new_mode:%d\n", auth_change->old_mode, auth_change->new_mode);
+            break;
+        case SYSTEM_EVENT_AP_START:
+            os_printf("SYSTEM_EVENT_AP_START\n");
+            break;
+        case SYSTEM_EVENT_AP_STOP:
+            os_printf("SYSTEM_EVENT_AP_STOP\n");
+            break;
+        case SYSTEM_EVENT_AP_STACONNECTED:
+            staconnected = &event->event_info.sta_connected;
+            os_printf("SYSTEM_EVENT_AP_STACONNECTED\nmac:%02x:%02x:%02x:%02x:%02x:%02x, aid:%d\n", \
+                staconnected->mac[0], staconnected->mac[0], staconnected->mac[1], \
+                staconnected->mac[3], staconnected->mac[4], staconnected->mac[5], staconnected->aid);
+            break;
+        case SYSTEM_EVENT_AP_STADISCONNECTED:
+            stadisconnected = &event->event_info.sta_disconnected;
+            os_printf("SYSTEM_EVENT_AP_STADISCONNECTED\nmac:%02x:%02x:%02x:%02x:%02x:%02x, aid:%d\n", \
+                stadisconnected->mac[0], stadisconnected->mac[0], stadisconnected->mac[1], \
+                stadisconnected->mac[3], stadisconnected->mac[4], stadisconnected->mac[5], stadisconnected->aid);
+            break;
+        case SYSTEM_EVENT_AP_PROBEREQRECVED:
+            ap_probereqrecved = &event->event_info.ap_probereqrecved;
+            os_printf("SYSTEM_EVENT_AP_PROBEREQRECVED\nrssi:%d, mac:%02x:%02x:%02x:%02x:%02x:%02x\n", \
+                ap_probereqrecved->rssi, ap_probereqrecved->mac[0], ap_probereqrecved->mac[0], ap_probereqrecved->mac[1], \
+                ap_probereqrecved->mac[3], ap_probereqrecved->mac[4], ap_probereqrecved->mac[5]);
+            break;
+        default:
+            os_printf("Error: no such kind of event!\n");
+            break;
+    }
+
+    return ESP_OK;
+}
+
+static esp_err_t esp_system_event_handler(system_event_t *event)
+{
+    if (event == NULL) {
+        os_printf("Error: event is null!\n");
+        return ESP_FAIL;
+    }
+
+    esp_system_event_debug(event);
+    if ((event->event_id < SYSTEM_EVENT_MAX) && (event->event_id == g_system_event_handle_table[event->event_id].event_id)){
+        if (g_system_event_handle_table[event->event_id].event_handle){
+            os_printf("enter default callback\n");
+            g_system_event_handle_table[event->event_id].event_handle(event);
+            os_printf("exit default callback\n");
+        }
+    } else {
+        os_printf("mismatch or invalid event, id=%d\n", event->event_id);
+    }
+
+    return esp_wifi_post_event_to_user(event);
+}
+
+static void esp_system_event_task(void *pvParameters)
+{
+    system_event_t evt;
+    esp_err_t ret;
+
+    while (1) {
+        if (xQueueReceive(g_event_handler, &evt, portMAX_DELAY) == pdPASS) {
+            ret = esp_system_event_handler(&evt);
+            if (ret == ESP_FAIL)
+                os_printf("esp wifi post event to user fail!\n");
+        }
+    }
+}
+
+system_event_cb_t esp_event_set_cb(system_event_cb_t cb)
+{
+    system_event_cb_t old_cb = g_event_handler_cb;
+    g_event_handler_cb = cb;
+    return old_cb;
+}
+
+esp_err_t esp_event_send(system_event_t *event)
+{
+    portBASE_TYPE ret;
+    
+    ret = xQueueSendToBack((xQueueHandle)g_event_handler, event, 0);
+    if (pdPASS != ret){
+        if (event) ets_printf("e=%d f\n", event->event_id);
+        else ets_printf("e null\n");
+        return ESP_FAIL;
+    }
+
+    return ESP_OK;
+}
+
+void* esp_event_get_handler(void)
+{
+    return (void*)g_event_handler;
+}
+
+esp_err_t esp_event_init(system_event_cb_t cb)
+{
+    g_event_handler_cb = (system_event_cb_t)cb;
+    g_event_handler = xQueueCreate(CONFIG_WIFI_ENENT_QUEUE_SIZE, sizeof(system_event_t));
+    xTaskCreatePinnedToCore(esp_system_event_task, "eventTask", CONFIG_WIFI_EVENT_TASK_STACK_SIZE, NULL, 5, NULL, 0); // TODO: rearrange task priority
+    return ESP_OK;
+}
+
+#endif

components/esp32/heap_alloc_caps.c

@@ -0,0 +1,246 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#include <rom/ets_sys.h>
+
+#include <freertos/heap_regions.h>
+
+#include "heap_alloc_caps.h"
+#include "spiram.h"
+
+/*
+This file, combined with a region allocator that supports tags, solves the problem that the ESP32 has RAM that's 
+slightly heterogeneous. Some RAM can be byte-accessed, some allows only 32-bit accesses, some can execute memory,
+some can be remapped by the MMU to only be accessed by a certain PID etc. In order to allow the most flexible
+memory allocation possible, this code makes it possible to request memory that has certain capabilities. The
+code will then use its knowledge of how the memory is configured along with a priority scheme to allocate that
+memory in the most sane way possible. This should optimize the amount of RAM accessible to the code without
+hardwiring addresses.
+*/
+
+
+//Amount of priority slots for the tag descriptors.
+#define NO_PRIOS 3
+
+/*
+Tag descriptors. These describe the capabilities of a bit of memory that's tagged with the index into this table.
+Each tag contains NO_PRIOS entries; later entries are only taken if earlier ones can't fulfill the memory request.
+*/
+static const uint32_t tagDesc[][NO_PRIOS]={
+	{ MALLOC_CAP_DMA|MALLOC_CAP_8BIT, MALLOC_CAP_32BIT, 0 },					//Tag 0: Plain ole D-port RAM
+	{ 0, MALLOC_CAP_DMA|MALLOC_CAP_8BIT, MALLOC_CAP_32BIT|MALLOC_CAP_EXEC },	//Tag 1: Plain ole D-port RAM which has an alias on the I-port
+	{ MALLOC_CAP_EXEC|MALLOC_CAP_32BIT, 0, 0 },									//Tag 2: IRAM
+	{ MALLOC_CAP_PID2, 0, MALLOC_CAP_EXEC|MALLOC_CAP_32BIT },					//Tag 3-8: PID 2-7 IRAM
+	{ MALLOC_CAP_PID3, 0, MALLOC_CAP_EXEC|MALLOC_CAP_32BIT },					//
+	{ MALLOC_CAP_PID4, 0, MALLOC_CAP_EXEC|MALLOC_CAP_32BIT },					//
+	{ MALLOC_CAP_PID5, 0, MALLOC_CAP_EXEC|MALLOC_CAP_32BIT },					//
+	{ MALLOC_CAP_PID6, 0, MALLOC_CAP_EXEC|MALLOC_CAP_32BIT },					//
+	{ MALLOC_CAP_PID7, 0, MALLOC_CAP_EXEC|MALLOC_CAP_32BIT },					//
+	{ MALLOC_CAP_PID2, MALLOC_CAP_8BIT, MALLOC_CAP_32BIT },						//Tag 9-14: PID 2-7 DRAM
+	{ MALLOC_CAP_PID3, MALLOC_CAP_8BIT, MALLOC_CAP_32BIT },						//
+	{ MALLOC_CAP_PID4, MALLOC_CAP_8BIT, MALLOC_CAP_32BIT },						//
+	{ MALLOC_CAP_PID5, MALLOC_CAP_8BIT, MALLOC_CAP_32BIT },						//
+	{ MALLOC_CAP_PID6, MALLOC_CAP_8BIT, MALLOC_CAP_32BIT },						//
+	{ MALLOC_CAP_PID7, MALLOC_CAP_8BIT, MALLOC_CAP_32BIT },						//
+	{ MALLOC_CAP_SPISRAM, 0, MALLOC_CAP_DMA|MALLOC_CAP_8BIT|MALLOC_CAP_32BIT}, //Tag 15: SPI SRAM data
+	{ MALLOC_CAP_INVALID, MALLOC_CAP_INVALID, MALLOC_CAP_INVALID } //End
+};
+
+/*
+Region descriptors. These describe all regions of memory available, and tag them according to the
+capabilities the hardware has. This array is not marked constant; the initialization code may want to
+change the tags of some regions because eg BT is detected, applications are loaded etc.
+
+The priorities here roughly work like this:
+- For a normal malloc (MALLOC_CAP_8BIT), give away the DRAM-only memory first, then pass off any dual-use IRAM regions,
+  finally eat into the application memory.
+- For a malloc where 32-bit-aligned-only access is okay, first allocate IRAM, then DRAM, finally application IRAM.
+- Application mallocs (PIDx) will allocate IRAM first, if possible, then DRAM.
+- Most other malloc caps only fit in one region anyway.
+
+These region descriptors are very ESP32 specific, because they describe the memory pools available there.
+
+Because of requirements in the coalescing code as well as the heap allocator itself, this list should always
+be sorted from low to high start address.
+
+This array is *NOT* const because it gets modified depending on what pools are/aren't available.
+*/
+static HeapRegionTagged_t regions[]={
+	{ (uint8_t *)0x3F800000, 0x20000, 15, 0}, //SPI SRAM, if available
+//	{ (uint8_t *)0x3FFAE000, 0x2000, 0, 0}, //pool 16 <- can be used for BT <- THIS POOL DOESN'T WORK for some reason! Hw seems fine. ToDo: Figure out.
+	{ (uint8_t *)0x3FFB0000, 0x8000, 0, 0}, //pool 15 <- can be used for BT
+	{ (uint8_t *)0x3FFB8000, 0x8000, 0, 0}, //pool 14
+	{ (uint8_t *)0x3FFC0000, 0x2000, 0, 0}, //pool 10-13, mmu page 0
+	{ (uint8_t *)0x3FFC2000, 0x2000, 0, 0}, //pool 10-13, mmu page 1
+	{ (uint8_t *)0x3FFC4000, 0x2000, 0, 0}, //pool 10-13, mmu page 2
+	{ (uint8_t *)0x3FFC6000, 0x2000, 0, 0}, //pool 10-13, mmu page 3
+	{ (uint8_t *)0x3FFC8000, 0x2000, 0, 0}, //pool 10-13, mmu page 4
+	{ (uint8_t *)0x3FFCA000, 0x2000, 0, 0}, //pool 10-13, mmu page 5
+	{ (uint8_t *)0x3FFCC000, 0x2000, 0, 0}, //pool 10-13, mmu page 6
+	{ (uint8_t *)0x3FFCE000, 0x2000, 0, 0}, //pool 10-13, mmu page 7
+	{ (uint8_t *)0x3FFD0000, 0x2000, 0, 0}, //pool 10-13, mmu page 8
+	{ (uint8_t *)0x3FFD2000, 0x2000, 0, 0}, //pool 10-13, mmu page 9
+	{ (uint8_t *)0x3FFD4000, 0x2000, 0, 0}, //pool 10-13, mmu page 10
+	{ (uint8_t *)0x3FFD6000, 0x2000, 0, 0}, //pool 10-13, mmu page 11
+	{ (uint8_t *)0x3FFD8000, 0x2000, 0, 0}, //pool 10-13, mmu page 12
+	{ (uint8_t *)0x3FFDA000, 0x2000, 0, 0}, //pool 10-13, mmu page 13
+	{ (uint8_t *)0x3FFDC000, 0x2000, 0, 0}, //pool 10-13, mmu page 14
+	{ (uint8_t *)0x3FFDE000, 0x2000, 0, 0}, //pool 10-13, mmu page 15
+	{ (uint8_t *)0x3FFE0000, 0x4000, 1, 0x400BC000}, //pool 9 blk 1
+	{ (uint8_t *)0x3FFE4000, 0x4000, 1, 0x400B8000}, //pool 9 blk 0
+	{ (uint8_t *)0x3FFE8000, 0x8000, 1, 0x400B0000}, //pool 8 <- can be remapped to ROM, used for MAC dump
+	{ (uint8_t *)0x3FFF0000, 0x8000, 1, 0x400A8000}, //pool 7 <- can be used for MAC dump
+	{ (uint8_t *)0x3FFF8000, 0x4000, 1, 0x400A4000}, //pool 6 blk 1 <- can be used as trace memory
+	{ (uint8_t *)0x3FFFC000, 0x4000, 1, 0x400A0000}, //pool 6 blk 0 <- can be used as trace memory
+	{ (uint8_t *)0x40070000, 0x8000, 2, 0}, //pool 0
+	{ (uint8_t *)0x40078000, 0x8000, 2, 0}, //pool 1
+	{ (uint8_t *)0x40080000, 0x2000, 2, 0}, //pool 2-5, mmu page 0
+	{ (uint8_t *)0x40082000, 0x2000, 2, 0}, //pool 2-5, mmu page 1
+	{ (uint8_t *)0x40084000, 0x2000, 2, 0}, //pool 2-5, mmu page 2
+	{ (uint8_t *)0x40086000, 0x2000, 2, 0}, //pool 2-5, mmu page 3
+	{ (uint8_t *)0x40088000, 0x2000, 2, 0}, //pool 2-5, mmu page 4
+	{ (uint8_t *)0x4008A000, 0x2000, 2, 0}, //pool 2-5, mmu page 5
+	{ (uint8_t *)0x4008C000, 0x2000, 2, 0}, //pool 2-5, mmu page 6
+	{ (uint8_t *)0x4008E000, 0x2000, 2, 0}, //pool 2-5, mmu page 7
+	{ (uint8_t *)0x40090000, 0x2000, 2, 0}, //pool 2-5, mmu page 8
+	{ (uint8_t *)0x40092000, 0x2000, 2, 0}, //pool 2-5, mmu page 9
+	{ (uint8_t *)0x40094000, 0x2000, 2, 0}, //pool 2-5, mmu page 10
+	{ (uint8_t *)0x40096000, 0x2000, 2, 0}, //pool 2-5, mmu page 11
+	{ (uint8_t *)0x40098000, 0x2000, 2, 0}, //pool 2-5, mmu page 12
+	{ (uint8_t *)0x4009A000, 0x2000, 2, 0}, //pool 2-5, mmu page 13
+	{ (uint8_t *)0x4009C000, 0x2000, 2, 0}, //pool 2-5, mmu page 14
+	{ (uint8_t *)0x4009E000, 0x2000, 2, 0}, //pool 2-5, mmu page 15
+	{ NULL, 0, 0, 0} //end
+};
+
+
+//Modify regions array to disable the given range of memory.
+static void disable_mem_region(void *from, void *to) {
+	int i;
+	//Align from and to on word boundaries
+	from=(void*)((uint32_t)from&~3);
+	to=(void*)(((uint32_t)to+3)&~3);
+	for (i=0; regions[i].xSizeInBytes!=0; i++) {
+		void *regStart=regions[i].pucStartAddress;
+		void *regEnd=regions[i].pucStartAddress+regions[i].xSizeInBytes;
+		if (regStart>=from && regEnd<=to) {
+			//Entire region falls in the range. Disable entirely.
+			regions[i].xTag=-1;
+		} else if (regStart>=from && regEnd>to && regStart<to) {
+			//Start of the region falls in the range. Modify address/len.
+			int overlap=(uint8_t *)to-(uint8_t *)regStart;
+			regions[i].pucStartAddress+=overlap;
+			regions[i].xSizeInBytes-=overlap;
+			if (regions[i].xExecAddr) regions[i].xExecAddr+=overlap;
+		} else if (regStart<from && regEnd>from && regEnd<=to) {
+			//End of the region falls in the range. Modify length.
+			regions[i].xSizeInBytes-=(uint8_t *)regEnd-(uint8_t *)from;
+		} else if (regStart<from && regEnd>to) {
+			//Range punches a hole in the region! We do not support this.
+			ets_printf("%s: region %d: hole punching is not supported!\n", i);
+			regions[i].xTag=-1; //Just disable memory region. That'll teach them!
+		}
+	}
+}
+
+
+/*
+ToDo: These are very dependent on the linker script, and the logic involving this works only
+because we're not using the SPI flash yet! If we enable that, this will break. ToDo: Rewrite by then.
+*/
+extern int _init_start, _text_end;
+extern int _bss_start, _heap_start;
+
+/*
+Initialize the heap allocator. We pass it a bunch of region descriptors, but we need to modify those first to accommodate for 
+the data as loaded by the bootloader.
+ToDo: The regions are different when stuff like trace memory, BT, ... is used. Modify the regions struct on the fly for this.
+Same with loading of apps. Same with using SPI RAM.
+*/
+void heap_alloc_caps_init() {
+	int i;
+	//Disable the bits of memory where this code is loaded.
+	disable_mem_region(&_init_start, &_text_end);
+	disable_mem_region(&_bss_start, &_heap_start);
+	disable_mem_region((void*)0x3ffae000, (void*)0x3ffb0000); //knock out ROM data region
+	disable_mem_region((void*)0x3ffe0000, (void*)0x3ffe8000); //knock out ROM data region
+	disable_mem_region((void*)0x40070000, (void*)0x40078000); //CPU0 cache region
+	disable_mem_region((void*)0x40078000, (void*)0x40080000); //CPU1 cache region
+#if 0
+	enable_spi_sram();
+#else
+	disable_mem_region((void*)0x3f800000, (void*)0x3f820000); //SPI SRAM not installed
+#endif
+
+	//The heap allocator will treat every region given to it as separate. In order to get bigger ranges of contiguous memory,
+	//it's useful to coalesce adjacent regions that have the same tag.
+
+	for (i=1; regions[i].xSizeInBytes!=0; i++) {
+		if (regions[i].pucStartAddress == (regions[i-1].pucStartAddress + regions[i-1].xSizeInBytes) &&
+									regions[i].xTag == regions[i-1].xTag ) {
+			regions[i-1].xTag=-1;
+			regions[i].pucStartAddress=regions[i-1].pucStartAddress;
+			regions[i].xSizeInBytes+=regions[i-1].xSizeInBytes;
+		}
+	}
+
+#if 1 //Change to 1 to show the regions the heap allocator is initialized with.
+	ets_printf("Initializing heap allocator:\n");
+	for (i=0; regions[i].xSizeInBytes!=0; i++) {
+		if ( regions[i].xTag != -1 ) ets_printf("Region %02d: %08X len %08X tag %d\n", i, (int)regions[i].pucStartAddress, regions[i].xSizeInBytes, regions[i].xTag);
+	}
+#endif
+	//Initialize the malloc implementation.
+	vPortDefineHeapRegionsTagged( regions );
+}
+
+/*
+Standard malloc() implementation. Will return ho-hum byte-accessible data memory.
+*/
+void *pvPortMalloc( size_t xWantedSize )
+{
+	return pvPortMallocCaps( xWantedSize, MALLOC_CAP_8BIT );
+}
+
+/*
+Routine to allocate a bit of memory with certain capabilities. caps is a bitfield of MALLOC_CAP_* bits.
+*/
+void *pvPortMallocCaps( size_t xWantedSize, uint32_t caps ) 
+{
+	int prio;
+	int tag, j;
+	void *ret=NULL;
+	uint32_t remCaps;
+	for (prio=0; prio<NO_PRIOS; prio++) {
+		//Iterate over tag descriptors for this priority
+		for (tag=0; tagDesc[tag][prio]!=MALLOC_CAP_INVALID; tag++) {
+			if ((tagDesc[tag][prio]&caps)!=0) {
+				//Tag has at least one of the caps requested. If caps has other bits set that this prio
+				//doesn't cover, see if they're available in other prios.
+				remCaps=caps&(~tagDesc[tag][prio]); //Remaining caps to be fulfilled
+				j=prio+1;
+				while (remCaps!=0 && j<NO_PRIOS) {
+					remCaps=remCaps&(~tagDesc[tag][j]);
+					j++;
+				}
+				if (remCaps==0) {
+					//This tag can satisfy all the requested capabilities. See if we can grab some memory using it.
+					ret=pvPortMallocTagged(xWantedSize, tag);
+					if (ret!=NULL) return ret;
+				}
+			}
+		}
+	}
+	//Nothing usable found.
+	return NULL;
+}

components/esp32/heap_alloc_caps.h

@@ -0,0 +1,34 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef HEAP_ALLOC_CAPS_H
+#define HEAP_ALLOC_CAPS_H
+
+#define MALLOC_CAP_EXEC				(1<<0)	//Memory must be able to run executable code
+#define MALLOC_CAP_32BIT			(1<<1)	//Memory must allow for aligned 32-bit data accesses
+#define MALLOC_CAP_8BIT				(1<<2)	//Memory must allow for 8/16/...-bit data accesses
+#define MALLOC_CAP_DMA				(1<<3)	//Memory must be able to accessed by DMA
+#define MALLOC_CAP_PID2				(1<<4)	//Memory must be mapped to PID2 memory space
+#define MALLOC_CAP_PID3				(1<<5)	//Memory must be mapped to PID3 memory space
+#define MALLOC_CAP_PID4				(1<<6)	//Memory must be mapped to PID4 memory space
+#define MALLOC_CAP_PID5				(1<<7)	//Memory must be mapped to PID5 memory space
+#define MALLOC_CAP_PID6				(1<<8)	//Memory must be mapped to PID6 memory space
+#define MALLOC_CAP_PID7				(1<<9)	//Memory must be mapped to PID7 memory space
+#define MALLOC_CAP_SPISRAM			(1<<10)	//Memory must be in SPI SRAM
+#define MALLOC_CAP_INVALID			(1<<31)	//Memory can't be used / list end marker
+
+
+void heap_alloc_caps_init();
+void *pvPortMallocCaps(size_t xWantedSize, uint32_t caps);
+
+#endif

components/esp32/include/esp_attr.h

@@ -0,0 +1,35 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef __ESP_ATTR_H__
+#define __ESP_ATTR_H__
+
+#define ROMFN_ATTR
+
+//Normally, the linker script will put all code and rodata in flash,
+//and all variables in shared RAM. This can be redirected to IRAM if
+//needed using these macros.
+
+//Forces data and flash into IRAM instead of flash / shared RAM
+#define IRAM_ATTR __attribute__((section(".iram1")))
+#define DRAM_ATTR __attribute__((section(".dram1")))
+
+//Forces data and flash into the IRAM section of a specific core.
+//Normally, you shouldn't have to use this: the linker will take care of
+//only linking in the functions for that specific core.
+#define IRAM_C0_ATTR __attribute__((section(".iram1pro")))
+#define DRAM_C0_ATTR __attribute__((section(".iram1pro")))
+#define IRAM_C1_ATTR __attribute__((section(".dram1app")))
+#define DRAM_C1_ATTR __attribute__((section(".dram1app")))
+
+#endif /* __ESP_ATTR_H__ */

components/esp32/include/esp_err.h

@@ -0,0 +1,36 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef __ESP_ERR_H__
+#define __ESP_ERR_H__
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef int32_t esp_err_t;
+
+/* Definitions for error constants. */
+
+#define ESP_OK          0
+#define ESP_FAIL        -1
+
+#define ESP_ERR_NO_MEM  0x101
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ESP_ERR_H__ */

components/esp32/include/esp_event.h

@@ -0,0 +1,107 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef __ESP_EVENT_H__
+#define __ESP_EVENT_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#include "esp_err.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    SYSTEM_EVENT_WIFI_READY = 0,           /**< ESP32 wifi ready */
+    SYSTEM_EVENT_SCAN_DONE,                /**< ESP32 finish scanning AP */
+    SYSTEM_EVENT_STA_START,                /**< ESP32 station start */
+    SYSTEM_EVENT_STA_STOP,                 /**< ESP32 station start */
+    SYSTEM_EVENT_STA_CONNECTED,            /**< ESP32 station connected to AP */
+    SYSTEM_EVENT_STA_DISCONNECTED,         /**< ESP32 station disconnected to AP */
+    SYSTEM_EVENT_STA_AUTHMODE_CHANGE,      /**< the auth mode of AP connected by ESP32 station changed */
+    SYSTEM_EVENT_AP_START,                 /**< ESP32 softap start */
+    SYSTEM_EVENT_AP_STOP,                  /**< ESP32 softap start */
+    SYSTEM_EVENT_AP_STACONNECTED,          /**< a station connected to ESP32 soft-AP */
+    SYSTEM_EVENT_AP_STADISCONNECTED,       /**< a station disconnected to ESP32 soft-AP */
+    SYSTEM_EVENT_AP_PROBEREQRECVED,        /**< Receive probe request packet in soft-AP interface */
+    SYSTEM_EVENT_MAX
+} system_event_id_t;
+
+typedef struct {
+    uint32_t status;          /**< status of scanning APs*/
+    uint8_t  number;
+} system_event_sta_scan_done_t;
+
+typedef struct {
+    uint8_t ssid[32];         /**< SSID of connected AP */
+    uint8_t ssid_len;         /**< SSID length of connected AP */
+    uint8_t bssid[6];         /**< BSSID of connected AP*/
+    uint8_t channel;          /**< channel of connected AP*/
+} system_event_sta_connected_t;
+
+typedef struct {
+    uint8_t ssid[32];         /**< SSID of disconnected AP */
+    uint8_t ssid_len;         /**< SSID length of disconnected AP */
+    uint8_t bssid[6];         /**< BSSID of disconnected AP */
+    uint8_t reason;           /**< reason of disconnection */
+} system_event_sta_disconnected_t;
+
+typedef struct {
+    uint8_t old_mode;         /**< the old auth mode of AP */
+    uint8_t new_mode;         /**< the new auth mode of AP */
+} system_event_sta_authmode_change_t;
+
+typedef struct {
+    uint8_t mac[6];           /**< MAC address of the station connected to ESP32 soft-AP */
+    uint8_t aid;              /**< the aid that ESP32 soft-AP gives to the station connected to  */
+} system_event_ap_staconnected_t;
+
+typedef struct {
+    uint8_t mac[6];           /**< MAC address of the station disconnects to ESP32 soft-AP */
+    uint8_t aid;              /**< the aid that ESP32 soft-AP gave to the station disconnects to  */
+} system_event_ap_stadisconnected_t;
+
+typedef struct {
+    int rssi;                 /**< Received probe request signal strength */
+    uint8_t mac[6];           /**< MAC address of the station which send probe request */
+} system_event_ap_probe_req_rx_t;
+
+typedef union {
+    system_event_sta_connected_t               connected;          /**< ESP32 station connected to AP */
+    system_event_sta_disconnected_t            disconnected;       /**< ESP32 station disconnected to AP */
+    system_event_sta_scan_done_t               scan_done;          /**< ESP32 station scan (APs) done */
+    system_event_sta_authmode_change_t         auth_change;        /**< the auth mode of AP ESP32 station connected to changed */
+    system_event_ap_staconnected_t             sta_connected;      /**< a station connected to ESP32 soft-AP */
+    system_event_ap_stadisconnected_t          sta_disconnected;   /**< a station disconnected to ESP32 soft-AP */
+    system_event_ap_probe_req_rx_t             ap_probereqrecved;  /**< ESP32 softAP receive probe request packet */
+} system_event_info_t;
+
+typedef struct {
+    system_event_id_t     event_id;      /**< even ID */
+    system_event_info_t   event_info;    /**< event information */
+} system_event_t;
+
+typedef esp_err_t (*system_event_cb_t)(system_event_t *event);
+system_event_cb_t esp_event_set_cb(system_event_cb_t cb);
+esp_err_t esp_event_send(system_event_t * event);
+void* esp_event_get_handler(void);
+esp_err_t esp_event_init(system_event_cb_t cb);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ESP_EVENT_H__ */

components/esp32/include/esp_ssc.h

@@ -0,0 +1,119 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef __ESP_SSC_H__
+#define __ESP_SSC_H__
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define CMD_T_ASYNC   0x01
+#define CMD_T_SYNC    0x02
+
+typedef struct cmd_s {
+    char *cmd_str;
+    uint8_t flag;
+    uint8_t id;
+    void (* cmd_func)(void);
+    void (* cmd_callback)(void *arg);
+} ssc_cmd_t;
+
+#define MAX_LINE_N  127
+
+typedef enum {
+    SSC_BR_9600   = 9600,
+    SSC_BR_19200  = 19200,
+    SSC_BR_38400  = 38400,
+    SSC_BR_57600  = 57600,
+    SSC_BR_74880  = 74880,
+    SSC_BR_115200 = 115200,
+    SSC_BR_230400 = 230400,
+    SSC_BR_460800 = 460800,
+    SSC_BR_921600 = 921600
+} SscBaudRate;
+
+/** \defgroup SSC_APIs SSC APIs
+  * @brief SSC APIs
+  *
+  * SSC means simple serial command.
+  * SSC APIs allows users to define their own command, users can refer to spiffs_test/test_main.c.
+  *
+  */
+
+/** @addtogroup SSC_APIs
+  * @{
+  */
+
+/**
+  * @brief  Initial the ssc function.
+  *
+  * @attention param is no use, just compatible with ESP8266, default bandrate is 115200
+  *
+  * @param  SscBaudRate bandrate : baud rate
+  *
+  * @return null
+  */
+void ssc_attach(SscBaudRate bandrate);
+
+/**
+  * @brief   Get the length of the simple serial command.
+  *
+  * @param   null
+  *
+  * @return  length of the command.
+  */
+int ssc_param_len(void);
+
+/**
+  * @brief   Get the simple serial command string.
+  *
+  * @param   null
+  *
+  * @return  the command.
+  */
+char *ssc_param_str(void);
+
+/**
+  * @brief   Parse the simple serial command (ssc).
+  *
+  * @param   char *pLine  : [input] the ssc string
+  * @param   char *argv[] : [output] parameters of the ssc
+  *
+  * @return  the number of parameters.
+  */
+int ssc_parse_param(char *pLine, char *argv[]);
+
+/**
+  * @brief  Register the user-defined simple serial command (ssc) set.
+  *
+  * @param  ssc_cmd_t *cmdset   : the ssc set
+  * @param  uint8 cmdnum        : number of commands
+  * @param  void (* help)(void) : callback of user-guide
+  *
+  * @return  null
+  */
+void ssc_register(ssc_cmd_t *cmdset, uint8_t cmdnum, void (* help)(void));
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ESP_SSC_H__ */

components/esp32/include/esp_system.h

@@ -0,0 +1,364 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef __ESP_SYSTEM_H__
+#define __ESP_SYSTEM_H__
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \defgroup System_APIs System APIs
+  * @brief System APIs
+  */
+
+/** @addtogroup System_APIs
+  * @{
+  */
+
+/**
+  * @brief  Get information of the SDK version.
+  *
+  * @param  null
+  *
+  * @return Information of the SDK version.
+  */
+const char *system_get_sdk_version(void);
+
+/**
+  * @brief  Reset to default settings.
+  *
+  *         Reset to default settings of the following APIs : wifi_station_set_auto_connect,
+  *         wifi_set_phy_mode, wifi_softap_set_config related, wifi_station_set_config
+  *         related, and wifi_set_opmode.
+  *
+  * @param  null
+  *
+  * @return null
+  */
+void system_restore(void);
+
+/**
+  * @brief  Restart system.
+  *
+  * @param  null
+  *
+  * @return null
+  */
+void system_restart(void);
+
+/**
+  * @brief     Set the chip to deep-sleep mode.
+  *
+  *            The device will automatically wake up after the deep-sleep time set
+  *            by the users. Upon waking up, the device boots up from user_init.
+  *
+  * @attention  The parameter time_in_us to be "uint64" is for further development. 
+  *                  Only the low 32 bits of parameter time_in_us are avalable now.
+  *
+  * @param     uint64 time_in_us : deep-sleep time, only the low 32bits are avalable now. unit: microsecond
+  *
+  * @return    null
+  */
+void system_deep_sleep(uint64_t time_in_us);
+
+/**
+  * @brief  Get system time, unit: microsecond.
+  *
+  * @param  null
+  *
+  * @return System time, unit: microsecond.
+  */
+uint32_t system_get_time(void);
+
+/**
+  * @brief  Print the system memory distribution, including data/rodata/bss/heap.
+  *
+  * @param  null
+  *
+  * @return null
+  */
+void system_print_meminfo(void);
+
+/**
+  * @brief  Get the size of available heap.
+  *
+  * @param  null
+  *
+  * @return Available heap size.
+  */
+uint32_t system_get_free_heap_size(void);
+
+/**
+  * @brief  Get the chip ID.
+  *
+  * Example:          
+  * <pre> 
+  *         uint8 chip_id[6];
+  *         system_get_chip_id(chip_id);
+  * </pre>
+  *
+  * @param  uint8 *chip_id : the chip ID
+  *
+  * @return    true  : succeed
+  * @return    false : fail
+  */
+bool system_get_chip_id(uint8_t *chip_id);
+
+/**
+  * @brief     Get RTC time, unit: RTC clock cycle.
+  *
+  * @param     null
+  *
+  * @return    RTC time.
+  */
+uint64_t system_get_rtc_time(void);
+
+/**
+  * @brief     Read user data from the RTC memory.
+  *
+  *            The user data segment (1024 bytes, as shown below) is used to store user data.
+  *
+  *             |<---- system data(512 bytes) ---->|<----------- user data(1024 bytes) --------->|
+  *
+  * @attention Read and write unit for data stored in the RTC memory is 4 bytes.
+  * @attention src_addr is the block number (4 bytes per block). So when reading data
+  *            at the beginning of the user data segment, src_addr will be 512/4 = 128,
+  *            n will be data length.
+  *
+  * @param     uint16 src : source address of rtc memory, src_addr >= 128
+  * @param     void *dst : data pointer
+  * @param     uint16 n : data length, unit: byte
+  *
+  * @return    true  : succeed
+  * @return    false : fail
+  */
+bool system_rtc_mem_read(uint16_t src, void *dst, uint16_t n);
+
+/**
+  * @brief     Write user data to  the RTC memory.
+  *
+  *            During deep-sleep, only RTC is working. So users can store their data
+  *            in RTC memory if it is needed. The user data segment below (1024 bytes)
+  *            is used to store the user data.
+  *
+  *            |<---- system data(512 bytes) ---->|<----------- user data(1024 bytes) --------->|
+  *
+  * @attention Read and write unit for data stored in the RTC memory is 4 bytes.
+  * @attention src_addr is the block number (4 bytes per block). So when storing data
+  *            at the beginning of the user data segment, src_addr will be 512/4 = 128,
+  *            n will be data length.
+  *
+  * @param     uint16 src : source address of rtc memory, src_addr >= 128
+  * @param     void *dst : data pointer
+  * @param     uint16 n : data length, unit: byte
+  *
+  * @return    true  : succeed
+  * @return    false : fail
+  */
+bool system_rtc_mem_write(uint16_t dst, const void *src, uint16_t n);
+
+typedef enum {
+    ADC1_PAD_GPIO36 = 0,
+    ADC1_PAD_GPIO37,
+    ADC1_PAD_GPIO38,
+    ADC1_PAD_GPIO39,
+    ADC1_PAD_GPIO32,
+    ADC1_PAD_GPIO33,
+    ADC1_PAD_GPIO34,
+    ADC1_PAD_GPIO35
+} adc1_read_pad_t;
+
+typedef enum {
+    ADC1_ATTEN_0DB = 0,
+    ADC1_ATTEN_3DB,
+    ADC1_ATTEN_6DB,
+    ADC1_ATTEN_12DB
+} adc1_read_atten_t;
+
+/**
+  * @brief    Read ADC1.
+  *
+  * @param     adc1_read_pad pad : the corresponding GPIO
+  * @param     adc1_read_atten atten :  value of attenuation 
+  *
+  * @return    range of the return value is [0, 4096].
+  *    - If atten == 0, the range of voltage can be measured is  [0, 1] V.
+  *    - If atten == 1, the range of voltage can be measured is  [0, 1.4] V.
+  *    - If atten == 2, the range of voltage can be measured is  [0, 2] V.
+  *    - If atten == 3, the range of voltage can be measured is  [0, 4] V.
+  */
+uint16_t system_adc1_read(adc1_read_pad_t pad, adc1_read_atten_t atten);
+
+/**
+  * @brief     Measure the power voltage of VDD3P3 pin 3 and 4, unit : 1/1024 V.
+  *
+  * @attention system_get_vdd33 depends on RF, please do not use it if RF is disabled.
+  *
+  * @param     null
+  *
+  * @return    Power voltage of VDD33, unit : 1/1024 V
+  */
+uint16_t system_get_vdd33(void);
+
+/**
+  * @brief  Write data into flash with protection.
+  *
+  *         Flash read/write has to be 4-bytes aligned.
+  *
+  *         Protection of flash read/write :
+  *             use 3 sectors (4KBytes per sector) to save  4KB data with protect,
+  *             sector 0 and sector 1 are data sectors, back up each other,
+  *             save data alternately, sector 2 is flag sector, point out which sector
+  *             is keeping the latest data, sector 0 or sector 1.
+  *
+  * @param  uint16 start_sec : start sector (sector 0) of the 3 sectors which are
+  *                            used for flash read/write protection.
+  *    - For example, in IOT_Demo we can use the 3 sectors (3 * 4KB) starting from flash
+  *      0x3D000 for flash read/write protection, so the parameter start_sec should be 0x3D
+  * @param  void *param : pointer of the data to be written
+  * @param  uint16 len : data length, should be less than a sector, which is 4 * 1024
+  *
+  * @return true  : succeed
+  * @return false : fail
+  */
+bool system_param_save_with_protect(uint16_t start_sec, void *param, uint16_t len);
+
+/**
+  * @brief  Read the data saved into flash with the read/write protection.
+  *
+  *         Flash read/write has to be 4-bytes aligned.
+  *
+  *         Read/write protection of flash:
+  *             use 3 sectors (4KB per sector) to save  4KB data with protect, sector
+  *             0 and sector 1 are data sectors, back up each other, save data alternately,
+  *             sector 2 is flag sector, point out which sector is keeping the latest data,
+  *             sector 0 or sector 1.
+  *
+  * @param  uint16 start_sec : start sector (sector 0) of the 3 sectors used for
+  *                            flash read/write protection. It cannot be sector 1 or sector 2.
+  *    - For example, in IOT_Demo, the 3 sectors (3 * 4KB) starting from flash 0x3D000
+  *      can be used for flash read/write protection.
+  *      The parameter start_sec is 0x3D, and it cannot be 0x3E or 0x3F.
+  * @param  uint16 offset : offset of data saved in sector
+  * @param  void *param : data pointer
+  * @param  uint16 len : data length, offset + len =< 4 * 1024
+  *
+  * @return true  : succeed
+  * @return false : fail
+  */
+bool system_param_load(uint16_t start_sec, uint16_t offset, void *param, uint16_t len);
+
+
+/** \defgroup System_boot_APIs Boot APIs
+  * @brief boot APIs
+  */
+
+/** @addtogroup System_boot_APIs
+  * @{
+  */
+
+/**
+  * @}
+  */
+  
+/** \defgroup Hardware_MAC_APIs Hardware MAC APIs
+  * @brief Hardware MAC address APIs
+  *
+  * In WiFi MAC, only ESP32 station MAC is the hardware MAC, ESP32 softAP MAC is a software MAC 
+  * calculated from ESP32 station MAC. 
+  * So users need to call wifi_get_macaddr to query the ESP32 softAP MAC if ESP32 station MAC changed.
+  *
+  */
+
+/** @addtogroup Hardware_MAC_APIs
+  * @{
+  */
+
+typedef enum {
+    DEFAULT_MAC = 0,    /**< Default hardware MAC provided by Espressif Systems */
+    USER_MAC,           /**< User-define hardware MAC  */
+} mac_group_t;
+
+typedef enum {
+    WIFI_MAC = 0,       /**< Hardware MAC address of ESP32 WiFi  */
+    BT_MAC,             /**< Hardware MAC address of ESP32 bluetooth  */
+} mac_type_t;
+
+/**
+  * @brief  Set user-define hardware MAC address.
+  *
+  * @attention  Hardware MAC address can only be set ONCE for each ESP32 chip.
+  *
+  * @param  mac_type type : type of hardware MAC address.
+  * @param  uint8 *mac : user-define hardware MAC address, length: 6 bytes.
+  *
+  * @return  0 : succeed to set.
+  * @return  1 : the hardware MAC has been set once, users can not set it any more.
+  * @return  2 : fail to set.
+  * @return  3 : invalid parameter.
+  */
+int system_efuse_program_user_mac(mac_type_t type, uint8_t *mac);
+
+/**
+  * @brief  Read hardware MAC address.
+  *
+  * @param  mac_group group : default MAC or user-defined MAC.
+  * @param  mac_type type : type of hardware MAC address.
+  * @param  uint8 *mac : the hardware MAC address, length: 6 bytes.
+  *
+  * @return  true  : succeed
+  * @return  false : fail
+  */
+bool system_efuse_read_mac(mac_group_t group, mac_type_t type, uint8_t *mac);
+
+/**
+  * @brief  Set hardware MAC group, default MAC or user-defined MAC.
+  *
+  * @attention  This API needs system_restart to take effect.
+  *
+  * @param  mac_group group : default MAC or user-defined MAC.
+  *
+  * @return  true  : succeed
+  * @return  false : fail
+  */
+bool system_efuse_set_mac_group(mac_group_t group);
+
+/**
+  * @brief  Get hardware MAC group, default MAC or user-defined MAC.
+  *
+  * @param  null
+  *
+  * @return  mac_group, the hardware MAC group.
+  */
+mac_group_t system_efuse_get_mac_group(void);
+
+void system_init(void);
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ESP_SYSTEM_H__ */

components/esp32/include/esp_types.h

@@ -0,0 +1,73 @@
+// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef __ESP_TYPES_H__
+#define __ESP_TYPES_H__
+
+#ifdef __GNUC__
+#include <sys/cdefs.h>
+#endif /*__GNUC__*/
+#include <stdint.h>
+#include <stdbool.h>
+#include <stddef.h>
+
+#define __ATTRIB_PACK           __attribute__ ((packed))
+#define __ATTRIB_PRINTF         __attribute__ ((format (printf, 1, 2)))
+#define __ATTRIB_NORETURN       __attribute__ ((noreturn))
+#define __ATTRIB_ALIGN(x)       __attribute__ ((aligned((x))))
+#define INLINE                  __inline__
+
+#define LOCAL       static
+
+/* probably should not put STATUS here */
+typedef enum {
+    OK = 0,
+    FAIL,
+    PENDING,
+    BUSY,
+    CANCEL,
+} STATUS;
+
+//#define _LITTLE_ENDIAN  1234
+//#define _BYTE_ORDER == _LITTLE_ENDIAN
+
+#define ASSERT( x ) do { \
+    if (!(x)) {          \
+        printf("%s %u\n", __FILE__, __LINE__); \
+        while (1) { \
+            asm volatile("nop"); \
+        };              \
+    }                   \
+} while (0)
+
+/* #if __GNUC_PREREQ__(4, 1) */
+#ifndef __GNUC__
+#if 1
+#define __offsetof(type, field)  __builtin_offsetof(type, field)
+#else
+#define __offsetof(type, field) ((size_t)(&((type *)0)->field))
+#endif
+#endif /* __GNUC__ */
+
+
+/* Macros for counting and rounding. */
+#ifndef howmany
+#define howmany(x, y)   (((x)+((y)-1))/(y))
+#endif
+
+#define container_of(ptr, type, member) ({                      \
+        const typeof( ((type *)0)->member ) *__mptr = (ptr);    \
+        (type *)( (char *)__mptr - __offsetof(type,member) );})
+
+#endif /* __ESP_TYPES_H__ */

components/esp32/include/esp_wifi.h

@@ -0,0 +1,231 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef __ESP_WIFI_H__
+#define __ESP_WIFI_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#include "esp_err.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    WIFI_MODE_NULL = 0,  /**< null mode */
+    WIFI_MODE_STA,       /**< WiFi station mode */
+    WIFI_MODE_AP,        /**< WiFi soft-AP mode */
+    WIFI_MODE_APSTA,     /**< WiFi station + soft-AP mode */
+    WIFI_MODE_MAX
+} wifi_mode_t;
+
+typedef enum {
+    WIFI_IF_STA = 0,     /**< ESP32 station interface */
+    WIFI_IF_AP,          /**< ESP32 soft-AP interface */
+    WIFI_IF_MAX
+} wifi_interface_t;
+
+typedef enum {
+    WIFI_COUNTRY_CN = 0,
+    WIFI_COUNTRY_JP,
+    WIFI_COUNTRY_US,
+    WIFI_COUNTRY_EU,
+    WIFI_COUNTRY_MAX
+} wifi_country_t;
+
+typedef enum {
+    WIFI_AUTH_OPEN = 0,      /**< authenticate mode : open */
+    WIFI_AUTH_WEP,           /**< authenticate mode : WEP */
+    WIFI_AUTH_WPA_PSK,       /**< authenticate mode : WPA_PSK */
+    WIFI_AUTH_WPA2_PSK,      /**< authenticate mode : WPA2_PSK */
+    WIFI_AUTH_WPA_WPA2_PSK,  /**< authenticate mode : WPA_WPA2_PSK */
+    WIFI_AUTH_MAX
+} wifi_auth_mode_t;
+
+enum {
+    WIFI_REASON_UNSPECIFIED              = 1,
+    WIFI_REASON_AUTH_EXPIRE              = 2,
+    WIFI_REASON_AUTH_LEAVE               = 3,
+    WIFI_REASON_ASSOC_EXPIRE             = 4,
+    WIFI_REASON_ASSOC_TOOMANY            = 5,
+    WIFI_REASON_NOT_AUTHED               = 6,
+    WIFI_REASON_NOT_ASSOCED              = 7,
+    WIFI_REASON_ASSOC_LEAVE              = 8,
+    WIFI_REASON_ASSOC_NOT_AUTHED         = 9,
+    WIFI_REASON_DISASSOC_PWRCAP_BAD      = 10,
+    WIFI_REASON_DISASSOC_SUPCHAN_BAD     = 11,
+    WIFI_REASON_IE_INVALID               = 13,
+    WIFI_REASON_MIC_FAILURE              = 14,
+    WIFI_REASON_4WAY_HANDSHAKE_TIMEOUT   = 15,
+    WIFI_REASON_GROUP_KEY_UPDATE_TIMEOUT = 16,
+    WIFI_REASON_IE_IN_4WAY_DIFFERS       = 17,
+    WIFI_REASON_GROUP_CIPHER_INVALID     = 18,
+    WIFI_REASON_PAIRWISE_CIPHER_INVALID  = 19,
+    WIFI_REASON_AKMP_INVALID             = 20,
+    WIFI_REASON_UNSUPP_RSN_IE_VERSION    = 21,
+    WIFI_REASON_INVALID_RSN_IE_CAP       = 22,
+    WIFI_REASON_802_1X_AUTH_FAILED       = 23,
+    WIFI_REASON_CIPHER_SUITE_REJECTED    = 24,
+
+    WIFI_REASON_BEACON_TIMEOUT           = 200,
+    WIFI_REASON_NO_AP_FOUND              = 201,
+    WIFI_REASON_AUTH_FAIL                = 202,
+    WIFI_REASON_ASSOC_FAIL               = 203,
+    WIFI_REASON_HANDSHAKE_TIMEOUT        = 204,
+};
+
+typedef enum {
+    WIFI_SECOND_CHAN_NONE = 0,
+    WIFI_SECOND_CHAN_ABOVE,
+    WIFI_SECOND_CHAN_BELOW,
+} wifi_second_chan_t;
+
+typedef esp_err_t (* wifi_startup_cb_t)(void);
+
+void esp_wifi_startup(wifi_startup_cb_t cb);
+
+typedef struct {
+    void    *event_q;
+    uint8_t rx_ba_win;                /**< TBC */
+    uint8_t tx_ba_win;                /**< TBC */
+    uint8_t rx_buf_cnt;               /**< TBC */
+    uint8_t tx_buf_cnt;               /**< TBC */
+} wifi_init_config_t;
+
+esp_err_t esp_wifi_init(wifi_init_config_t *config);
+
+esp_err_t esp_wifi_deinit(void);
+
+esp_err_t esp_wifi_set_mode(wifi_mode_t mode);
+
+esp_err_t esp_wifi_get_mode(wifi_mode_t *mode);
+
+esp_err_t esp_wifi_start(void);
+
+esp_err_t esp_wifi_stop(void);
+
+esp_err_t esp_wifi_connect(void);
+
+esp_err_t esp_wifi_disconnect(void);
+
+typedef struct {
+    char *ssid;          /**< SSID of AP */
+    uint8_t *bssid;      /**< MAC address of AP */
+    uint8_t channel;     /**< channel, scan the specific channel */
+    bool show_hidden;   /**< enable to scan AP whose SSID is hidden */
+} wifi_scan_config_t;
+
+esp_err_t esp_wifi_scan_start(wifi_scan_config_t *conf);
+
+esp_err_t esp_wifi_scan_stop(void);
+
+esp_err_t esp_wifi_get_ap_num(uint16_t *number);
+
+typedef struct {
+    uint8_t bssid[6];                     /**< MAC address of AP */
+    uint8_t ssid[32];                     /**< SSID of AP */
+    uint8_t primary;                      /**< channel of AP */
+    wifi_second_chan_t second;            /**< second channel of AP */
+    char    rssi;                         /**< single strength of AP */
+    wifi_auth_mode_t authmode;            /**< authmode of AP */
+}wifi_ap_list_t;
+
+esp_err_t esp_wifi_get_ap_list(uint16_t *number, wifi_ap_list_t *ap_list);
+
+typedef enum {
+    WIFI_PS_NONE,
+    WIFI_PS_MODEM,
+    WIFI_PS_LIGHT,
+    WIFI_PS_MAC,
+} wifi_ps_type_t;
+
+esp_err_t esp_wifi_set_ps(wifi_ps_type_t type);
+
+esp_err_t esp_wifi_get_ps(wifi_ps_type_t *type);
+
+#define WIFI_PROTOCOL_11B         1
+#define WIFI_PROTOCOL_11G         2
+#define WIFI_PROTOCOL_11N         4
+
+esp_err_t esp_wifi_set_protocol(wifi_interface_t ifx, uint8_t protocol);
+
+esp_err_t esp_wifi_get_protocol(wifi_interface_t ifx, uint8_t *protocol);
+
+typedef enum {
+    WIFI_BW_HT20 = 0,
+    WIFI_BW_HT40,
+} wifi_bandwidth_t;
+
+esp_err_t esp_wifi_set_bandwidth(wifi_interface_t ifx, wifi_bandwidth_t bw);
+
+esp_err_t esp_wifi_get_bandwidth(wifi_interface_t ifx, wifi_bandwidth_t *bw);
+
+esp_err_t esp_wifi_set_channel(uint8_t primary, wifi_second_chan_t second);
+
+esp_err_t esp_wifi_get_channel(uint8_t *primary, wifi_second_chan_t *second);
+
+esp_err_t esp_wifi_set_country(wifi_country_t country);
+
+esp_err_t esp_wifi_get_country(wifi_country_t *country);
+
+esp_err_t esp_wifi_set_mac(wifi_interface_t ifx, uint8_t mac[6]);
+
+esp_err_t esp_wifi_get_mac(wifi_interface_t ifx, uint8_t mac[6]);
+
+typedef void (* wifi_promiscuous_cb_t)(void *buf, uint16_t len);
+
+wifi_promiscuous_cb_t wifi_set_promiscuous_rx_cb(wifi_promiscuous_cb_t cb);
+
+esp_err_t esp_wifi_set_promiscuous(uint8_t enable);
+
+esp_err_t esp_wifi_get_promiscuous(uint8_t *enable);
+
+typedef struct {
+    char ssid[32];              /**< SSID of ESP32 soft-AP */
+    char password[64];          /**< Password of ESP32 soft-AP */
+    uint8_t ssid_len;           /**< Length of SSID. If softap_config.ssid_len==0, check the SSID until there is a termination character; otherwise, set the SSID length according to softap_config.ssid_len. */
+    uint8_t channel;            /**< Channel of ESP32 soft-AP */
+    wifi_auth_mode_t authmode;  /**< Auth mode of ESP32 soft-AP. Do not support AUTH_WEP in soft-AP mode */
+    uint8_t ssid_hidden;        /**< Broadcast SSID or not, default 0, broadcast the SSID */
+    uint8_t max_connection;     /**< Max number of stations allowed to connect in, default 4, max 4 */
+    uint16_t beacon_interval;   /**< Beacon interval, 100 ~ 60000 ms, default 100 */
+} wifi_ap_config_t;
+
+typedef struct {
+    char ssid[32];         /**< SSID of target AP*/
+    char password[64];     /**< password of target AP*/
+    bool bssid_set;        /**< whether set MAC address of target AP or not. Generally, station_config.bssid_set needs to be 0; and it needs to be 1 only when users need to check the MAC address of the AP.*/
+    uint8_t bssid[6];     /**< MAC address of target AP*/
+} wifi_sta_config_t;
+
+typedef union {
+    wifi_ap_config_t  ap;
+    wifi_sta_config_t sta;
+} wifi_config_t;
+
+esp_err_t esp_wifi_set_config(wifi_interface_t ifx, wifi_config_t *conf);
+
+esp_err_t esp_wifi_get_config(wifi_interface_t ifx, wifi_config_t *conf);
+
+typedef esp_err_t (*wifi_rxcb_t)(void *buffer, uint16_t len, void* eb);
+
+esp_err_t esp_wifi_reg_rxcb(wifi_interface_t ifx, wifi_rxcb_t fn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ESP_WIFI_H__ */

components/esp32/include/esp_wps.h

@@ -0,0 +1,131 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef __ESP_WPS_H__
+#define __ESP_WPS_H__
+
+#include <stdbool.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \defgroup WiFi_APIs WiFi Related APIs
+  * @brief WiFi APIs
+  */
+
+/** @addtogroup WiFi_APIs
+  * @{
+  */
+
+/** \defgroup WPS_APIs  WPS APIs
+  * @brief ESP32 WPS APIs
+  *
+  * WPS can only be used when ESP32 station is enabled.
+  *
+  */
+
+/** @addtogroup WPS_APIs
+  * @{
+  */
+
+typedef enum wps_type {
+    WPS_TYPE_DISABLE = 0,
+    WPS_TYPE_PBC,
+    WPS_TYPE_PIN,
+    WPS_TYPE_DISPLAY,
+    WPS_TYPE_MAX,
+} WPS_TYPE_t;
+
+enum wps_cb_status {
+    WPS_CB_ST_SUCCESS = 0,     /**< WPS succeed */
+    WPS_CB_ST_FAILED,          /**< WPS fail */
+    WPS_CB_ST_TIMEOUT,         /**< WPS timeout, fail */
+    WPS_CB_ST_WEP,             /**< WPS failed because that WEP is not supported */
+    WPS_CB_ST_SCAN_ERR,        /**< can not find the target WPS AP */
+};
+
+/**
+  * @brief     Enable Wi-Fi WPS function.
+  *
+  * @attention WPS can only be used when ESP32 station is enabled.
+  *
+  * @param     WPS_TYPE_t wps_type : WPS type, so far only WPS_TYPE_PBC is supported
+  *
+  * @return    true  : succeed
+  * @return    false : fail
+  */
+bool wifi_wps_enable(WPS_TYPE_t wps_type);
+
+/**
+  * @brief  Disable Wi-Fi WPS function and release resource it taken.
+  *
+  * @param  null
+  *
+  * @return true  : succeed
+  * @return false : fail
+  */
+bool wifi_wps_disable(void);
+
+/**
+  * @brief     WPS starts to work.
+  *
+  * @attention WPS can only be used when ESP32 station is enabled.
+  *
+  * @param     null
+  *
+  * @return    true  : WPS starts to work successfully, but does not mean WPS succeed.
+  * @return    false : fail
+  */
+bool wifi_wps_start(void);
+
+/**
+  * @brief  WPS callback.
+  *
+  * @param  int status : status of WPS, enum wps_cb_status.
+  *    -  If parameter status == WPS_CB_ST_SUCCESS in WPS callback, it means WPS got AP's
+  *       information, user can call wifi_wps_disable to disable WPS and release resource,
+  *       then call wifi_station_connect to connect to target AP.
+  *    -  Otherwise, it means that WPS fail, user can create a timer to retry WPS by
+  *       wifi_wps_start after a while, or call wifi_wps_disable to disable WPS and release resource.
+  *
+  * @return null
+  */
+typedef void (*wps_st_cb_t)(int status);
+
+/**
+  * @brief     Set WPS callback.
+  *
+  * @attention WPS can only be used when ESP32 station is enabled.
+  *
+  * @param     wps_st_cb_t cb : callback.
+  *
+  * @return    true  : WPS starts to work successfully, but does not mean WPS succeed.
+  * @return    false : fail
+  */
+bool wifi_set_wps_cb(wps_st_cb_t cb);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ESP_WPS_H__ */

components/esp32/include/rom/aes.h

@@ -0,0 +1,48 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _ROM_AES_H_
+#define _ROM_AES_H_
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+enum AES_BITS {
+    AES128,
+    AES192,
+    AES256
+};
+
+void ets_aes_enable(void);
+
+void ets_aes_disable(void);
+
+void ets_set_endian(bool key_word_swap, bool key_byte_swap,
+                    bool in_word_swap, bool in_byte_swap,
+                    bool out_word_swap, bool out_byte_swap);
+
+bool ets_aes_setkey_enc(const uint8_t *key, enum AES_BITS bits);
+
+bool ets_aes_setkey_dec(const uint8_t *key, enum AES_BITS bits);
+
+void ets_aes_crypt(const uint8_t input[16], uint8_t output[16]);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _ROM_AES_H_ */

components/esp32/include/rom/bigint.h

@@ -0,0 +1,53 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _ROM_BIGINT_H_
+#define _ROM_BIGINT_H_
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void ets_bigint_enable(void);
+
+void ets_bigint_disable(void);
+
+void ets_bigint_wait_finish(void);
+
+bool ets_bigint_mod_power_prepare(uint32_t *x, uint32_t *y, uint32_t *m,
+                                  uint32_t m_dash, uint32_t *rb, uint32_t len, bool again);
+
+bool ets_bigint_mod_power_getz(uint32_t *z, uint32_t len);
+
+bool ets_bigint_mult_prepare(uint32_t *x, uint32_t *y, uint32_t len);
+
+bool ets_bigint_mult_getz(uint32_t *z, uint32_t len);
+
+bool ets_bigint_montgomery_mult_prepare(uint32_t *x, uint32_t *y, uint32_t *m,
+                                        uint32_t m_dash, uint32_t len, bool again);
+
+bool ets_bigint_montgomery_mult_getz(uint32_t *z, uint32_t len);
+
+bool ets_bigint_mod_mult_prepare(uint32_t *x, uint32_t *y, uint32_t *m,
+                                 uint32_t m_dash, uint32_t *rb, uint32_t len, bool again);
+
+bool ets_bigint_mod_mult_getz(uint32_t *m, uint32_t *z, uint32_t len);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _ROM_BIGINT_H_ */

components/esp32/include/rom/cache.h

@@ -0,0 +1,69 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _ROM_CACHE_H_
+#define _ROM_CACHE_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//===========================================
+//  function :     cache_init
+//  description:   initialise cache mmu, mark all entries as invalid.
+//  conditions:
+//                 Call Cache_Read_Disable() before calling this function.
+//  inputs:
+//                 cpu_no is CPU number,0(PRO CPU) or 1(APP CPU),
+//  output:        NONE
+//===========================================
+void mmu_init(int cpu_no);
+
+//===========================================
+//  function :     cache_flash_mmu_set
+//  description:   Configure MMU to cache a flash region.
+//  conditions:
+//                 Call this function to configure the flash cache before enabling it.
+//                 Check return value to verify MMU was set correctly.
+//  inputs:
+//                 cpu_no is CPU number,0(PRO CPU) or 1(APP CPU),
+//                 pid    is process identifier. Range 0~7
+//                 vaddr  is "virtual" address in CPU address space. Can be IRam0, IRam1, IRom0 and DRom0 memory address.
+//                        Should be aligned by psize
+//                 paddr  is "physical" address in flash controller's address space.
+//                        ie for 16M flash the range is 0x000000~0xFFFFFF. Should be aligned by psize
+//                 psize  is page size of flash, in kilobytes. Can be 64, 32, 16.
+//                 num    is number of pages to be set, valid range 0 ~ (flash size)/(page size)
+//  output:        error status
+//                 0 : mmu set success
+//                 1 : vaddr or paddr is not aligned
+//                 2 : pid error
+//                 3 : psize error
+//                 4 : mmu table to be written is out of range
+//                 5 : vaddr is out of range
+//===========================================
+unsigned int cache_flash_mmu_set(int cpu_no, int pid, unsigned int vaddr, unsigned int paddr,  int psize, int num);
+
+unsigned int cache_sram_mmu_set(int cpu_no, int pid,unsigned int vaddr, unsigned int paddr, int psize, int num);
+
+void Cache_Read_Init(int cpu_no);
+
+void Cache_Read_Disable(int cpu_no);
+
+void Cache_Read_Enable(int cpu_no);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _ROM_CACHE_H_ */

components/esp32/include/rom/crc.h

@@ -0,0 +1,34 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef ROM_CRC_H
+#define ROM_CRC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Standard CRC8/16/32 algorithms. */
+uint32_t crc32_le(uint32_t crc, uint8_t const * buf, uint32_t len);
+uint32_t crc32_be(uint32_t crc, uint8_t const * buf, uint32_t len);
+uint16_t crc16_le(uint16_t crc, uint8_t const * buf, uint32_t len);
+uint16_t crc16_be(uint16_t crc, uint8_t const * buf, uint32_t len);
+uint8_t crc8_le(uint8_t crc, uint8_t const * buf, uint32_t len);
+uint8_t crc8_be(uint8_t crc, uint8_t const * buf, uint32_t len);
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif

components/esp32/include/rom/efuse.h

@@ -0,0 +1,29 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _ROM_EFUSE_H_
+#define _ROM_EFUSE_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void ets_efuse_read_op(void);
+
+void ets_efuse_program_op(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _ROM_EFUSE_H_ */

components/esp32/include/rom/ets_sys.h

@@ -0,0 +1,329 @@
+// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef _ROM_ETS_SYS_H_
+#define _ROM_ETS_SYS_H_
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#include "soc/soc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define ETS_DEBUG
+#define ETS_SERIAL_ENABLED()  (1)
+
+typedef enum {
+    ETS_OK     = 0,
+    ETS_FAILED = 1
+} ETS_STATUS;
+
+typedef uint32_t ETSSignal;
+typedef uint32_t ETSParam;
+
+typedef struct ETSEventTag ETSEvent;
+
+struct ETSEventTag {
+    ETSSignal sig;
+    ETSParam  par;
+};
+
+typedef void (*ETSTask)(ETSEvent *e);
+
+enum ETS_User_Priorities {
+    /* task priorities... */
+    TICK_TASK_A_PRIO      = 2,
+    KBD_TASK_PRIO         = 5,
+    MAX_ETS_USER_PRIO     = 16,
+
+    /* ISR priorities... */
+    MAX_ETS_USER_ISR_PRIO = 0xFF - 16
+};
+
+/* ETS interrupt entry and exit */
+/* actually we don't need the following 2 macros any more since we won't exit
+ * isr until it is finised, more over, we don't do nest interrupt
+ */
+
+void ets_run(void);
+
+void ets_task(ETSTask task, uint8_t prio, ETSEvent *queue, uint8_t qlen);
+
+ETS_STATUS ets_post(uint8_t prio, ETSSignal sig, ETSParam  par);
+
+/*
+ * now things become complicated, print could be directed to uart and/or SDIO
+ */
+int ets_printf(const char *fmt, ...);
+
+/* by default it's UART, just install_uart_printf, set putc1 to NULL to disable */
+void ets_install_putc1(void (*p)(char c));
+void ets_install_uart_printf(void);
+
+/* no need to install, call directly */
+int ets_uart_printf(const char *fmt, ...);
+
+/* usually we don't need to call this, unless we want to disable SDIO print */
+void ets_install_putc2(void (*p)(char c));
+/* @prepare_buf: allocate buffer for printf internal writting 
+ * @putc: just set to NULL, let printf write to to buffer, unless if you want more fancy stuff
+ * @post_printf: will be called every time printf finish write buffer
+ *
+ * main idea of external printf is re-directing content to an external buffer.
+ *  e.g. sip module allocates an event buffer in prepare_buf() and send the event to host in post_printf()
+ *  moreover, you can check printf_buf_remain_len in post_printf(), send the event to host till buf is
+ *  about to full.
+ * 
+ * TBD: Another approach is sending printf parameter to host and let host to decode, which could save some bytes.
+ */
+void ets_install_external_printf(void (*prepare_buf)(char ** bufptr, uint16_t *buflen, uint32_t *cookie),
+                                  void (*putc)(char c),
+                                  void (*post_printf)(uint32_t cookie));
+
+uint16_t est_get_printf_buf_remain_len(void);
+void est_reset_printf_buf_len(void);
+
+/* external (SDIO) printf only, still need to install*/
+int ets_external_printf(const char *fmt, ...);
+
+
+#define ETS_PRINTF(...) ets_printf(...)
+
+#define ETS_ASSERT(v) do { \
+    if (!(v)) {             \
+        ets_printf("%s %u \n", __FILE__, __LINE__); \
+        while (1) {};   \
+    }                   \
+} while (0);
+
+/* memory and string support */
+int8_t ets_char2xdigit(char ch);
+uint8_t * ets_str2macaddr(uint8_t *macaddr, char *str);
+void ets_getc(char *c);
+void ets_putc(char c);
+
+/* timer related */
+typedef uint32_t ETSHandle;
+typedef void ETSTimerFunc(void *timer_arg);
+
+typedef struct _ETSTIMER_ {
+    struct _ETSTIMER_    *timer_next;
+    uint32_t              timer_expire;
+    uint32_t              timer_period;
+    ETSTimerFunc         *timer_func;
+    void                 *timer_arg;
+} ETSTimer;
+
+void ets_timer_init(void);
+void ets_timer_arm(ETSTimer *timer, uint32_t tmout, bool repeat);
+void ets_timer_disarm(ETSTimer *timer);
+void ets_timer_done(ETSTimer *ptimer);
+void ets_timer_setfn(ETSTimer *ptimer, ETSTimerFunc *pfunction, void *parg);
+
+/* watchdog related */
+typedef enum {
+    WDT_NONE                  = -1,
+    WDT_DISABLED              = 0,
+    WDT_CONTROL_RESET         = 1,
+    WDT_CONTROL_INTR          = 2, /* usually we use this mode? */
+    WDT_CONTROL_EXTERNAL_FEED = 3,
+    WDT_TESET_OVERFLOW        = 4, // intend to make watchdog overflow to test
+} WDT_MODE;
+
+typedef enum{
+    WDT_INTERVAL_THREE_SEC      = 3,
+    WDT_INTERVAL_SIX_SEC        = 6,
+    WDT_INTERVAL_TWELVE_SEC     = 12,
+} WDT_INTERVAL_TIME;
+
+void ets_wdt_init(void);
+WDT_MODE ets_wdt_get_mode(void);
+void ets_wdt_enable(WDT_MODE mode, WDT_INTERVAL_TIME feed_interval, 
+		WDT_INTERVAL_TIME expire_interval);
+WDT_MODE ets_wdt_disable(void);
+void ets_wdt_restore(WDT_MODE old_mode);
+
+/* interrupt related */
+typedef void (* ets_isr_t)(void *);
+
+#define ETS_WMAC_SOURCE       0
+#define ETS_SLC_SOURCE        1
+#define ETS_UART_SOURCE       13
+#define ETS_UART1_SOURCE      14
+#define ETS_FRC_TIMER2_SOURCE 43
+
+#define ETS_WMAC_INUM       0
+#define ETS_SLC_INUM        1
+#define ETS_SPI_INUM        2
+#define ETS_HSIP_INUM       2
+#define ETS_I2S_INUM        2
+#define ETS_RTC_INUM        3
+#define ETS_FRC_TIMER1_INUM 9  /* use edge*/
+#define ETS_FRC_TIMER2_INUM 10 /* use edge*/
+#define ETS_WDT_INUM        8  /* use edge*/
+#define ETS_GPIO_INUM       4
+#define ETS_UART_INUM       5
+#define ETS_UART1_INUM      5
+#define ETS_MAX_INUM        6
+
+
+void ets_isr_attach(int i, ets_isr_t func, void *arg);
+void ets_isr_mask(uint32_t mask);
+void ets_isr_unmask(uint32_t unmask);
+void ets_intr_lock(void);
+void ets_intr_unlock(void);
+void intr_matrix_set(int cpu_no, uint32_t model_num, uint32_t intr_num);
+
+#define _ETSTR(v) # v
+#define _ETS_SET_INTLEVEL(intlevel)        ({ unsigned __tmp; \
+            __asm__ __volatile__(   "rsil   %0, " _ETSTR(intlevel) "\n" \
+                        : "=a" (__tmp) : : "memory" ); \
+            })
+
+#define ETS_INTR_LOCK() \
+    ets_intr_lock()
+
+#define ETS_INTR_UNLOCK() \
+    ets_intr_unlock()
+
+#define ETS_CCOMPARE_INTR_ATTACH(func, arg) \
+	ets_isr_attach(ETS_CCOMPARE_INUM, (func), (void *)(arg))
+
+#define ETS_PWM_INTR_ATTACH(func, arg) \
+	ets_isr_attach(ETS_PWM_INUM, (func), (void *)(arg))
+
+#define ETS_WMAC_INTR_ATTACH(func, arg) \
+	ets_isr_attach(ETS_WMAC_INUM, (func), (void *)(arg))
+
+#define ETS_FRC_TIMER1_INTR_ATTACH(func, arg) \
+    ets_isr_attach(ETS_FRC_TIMER1_INUM, (func), (void *)(arg))
+
+#define ETS_FRC_TIMER2_INTR_ATTACH(func, arg) \
+    ets_isr_attach(ETS_FRC_TIMER2_INUM, (func), (void *)(arg))
+        
+#define ETS_GPIO_INTR_ATTACH(func, arg) \
+    ets_isr_attach(ETS_GPIO_INUM, (func), (void *)(arg))
+
+#define ETS_UART_INTR_ATTACH(func, arg) \
+    ets_isr_attach(ETS_UART_INUM, (func), (void *)(arg))
+
+#define ETS_WDT_INTR_ATTACH(func, arg) \
+    ets_isr_attach(ETS_WDT_INUM, (func), (void *)(arg))
+    
+#define ETS_RTC_INTR_ATTACH(func, arg) \
+    ets_isr_attach(ETS_RTC_INUM, (func), (void *)(arg))
+
+#define ETS_SLC_INTR_ATTACH(func, arg) \
+    ets_isr_attach(ETS_SLC_INUM, (func), (void *)(arg))
+
+
+#define ETS_INTR_ENABLE(inum) \
+	ets_isr_unmask((1<<inum))
+
+#define ETS_INTR_DISABLE(inum) \
+	ets_isr_mask((1<<inum))
+
+#define ETS_CCOMPARE_INTR_ENBALE() \
+    ETS_INTR_ENABLE(ETS_CCOMPARE_INUM)
+
+#define ETS_CCOMPARE_INTR_DISBALE() \
+    ETS_INTR_DISABLE(ETS_CCOMPARE_INUM)
+
+#define ETS_PWM_INTR_ENABLE() \
+	ETS_INTR_ENABLE(ETS_PWM_INUM)
+
+#define ETS_PWM_INTR_DISABLE() \
+	ETS_INTR_DISABLE(ETS_PWM_INUM)
+
+#define ETS_BB_INTR_ENABLE() \
+	ETS_INTR_ENABLE(ETS_BB_INUM)
+
+#define ETS_BB_INTR_DISABLE() \
+	ETS_INTR_DISABLE(ETS_BB_INUM)
+
+#define ETS_UART_INTR_ENABLE() \
+	ETS_INTR_ENABLE(ETS_UART_INUM)
+
+#define ETS_UART_INTR_DISABLE() \
+	ETS_INTR_DISABLE(ETS_UART_INUM)
+
+#define ETS_GPIO_INTR_ENABLE() \
+	ETS_INTR_ENABLE(ETS_GPIO_INUM)
+
+#define ETS_GPIO_INTR_DISABLE() \
+	ETS_INTR_DISABLE(ETS_GPIO_INUM)
+       
+#define ETS_WDT_INTR_ENABLE() \
+	ETS_INTR_ENABLE(ETS_WDT_INUM)
+
+#define ETS_WDT_INTR_DISABLE() \
+	ETS_INTR_DISABLE(ETS_WDT_INUM)
+
+#define ETS_FRC1_INTR_ENABLE() \
+	ETS_INTR_ENABLE(ETS_FRC_TIMER1_INUM)
+
+#define ETS_FRC1_INTR_DISABLE() \
+	ETS_INTR_DISABLE(ETS_FRC_TIMER1_INUM)
+
+#define ETS_FRC2_INTR_ENABLE() \
+	ETS_INTR_ENABLE(ETS_FRC_TIMER2_INUM)
+
+#define ETS_FRC2_INTR_DISABLE() \
+	ETS_INTR_DISABLE(ETS_FRC_TIMER2_INUM)
+
+#define ETS_RTC_INTR_ENABLE() \
+	ETS_INTR_ENABLE(ETS_RTC_INUM)
+
+#define ETS_RTC_INTR_DISABLE() \
+	ETS_INTR_DISABLE(ETS_RTC_INUM)
+
+#define ETS_SLC_INTR_ENABLE() \
+    ETS_INTR_ENABLE(ETS_SLC_INUM)
+
+#define ETS_SLC_INTR_DISABLE() \
+    ETS_INTR_DISABLE(ETS_SLC_INUM)
+
+void ets_delay_us(uint32_t us);
+void ets_update_cpu_frequency(uint32_t ticks_per_us);
+uint32_t ets_get_xtal_scale();
+uint32_t ets_get_detected_xtal_freq();
+
+#if 0
+#define isdigit(c) ((c >= '0') && (c <= '9'))
+
+#define isxdigit(c) (((c >= '0') && (c <= '9')) ||   \
+                        ((c >= 'a') && (c <= 'f')) || \
+                        ((c >= 'A') && (c <= 'F')) )
+
+#define isblank(c) ((c == ' ') || (c == '\t'))
+
+#define isupper(c) ((c >= 'A') && (c <= 'Z'))
+#endif
+
+
+#ifndef MAC2STR
+#define MAC2STR(a) (a)[0], (a)[1], (a)[2], (a)[3], (a)[4], (a)[5]
+#define MACSTR "%02x:%02x:%02x:%02x:%02x:%02x"
+#endif
+
+#define ETS_MEM_BAR() asm volatile ( "" : : : "memory" )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _ROM_ETS_SYS_H_ */

components/esp32/include/rom/gpio.h

@@ -0,0 +1,142 @@
+// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef _ROM_GPIO_H_
+#define _ROM_GPIO_H_
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#include "esp_attr.h"
+#include "soc/gpio_reg.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define GPIO_REG_READ(reg)              READ_PERI_REG(reg)
+#define GPIO_REG_WRITE(reg, val)        WRITE_PERI_REG(reg, val)
+#define GPIO_PIN_COUNT                  40
+#define GPIO_ID_PIN0                    0
+#define GPIO_ID_PIN(n)                  (GPIO_ID_PIN0+(n))
+#define GPIO_PIN_ADDR(i)                (GPIO_PIN0 + i*4)
+
+#define GPIO_ID_IS_PIN_REGISTER(reg_id) \
+    ((reg_id >= GPIO_ID_PIN0) && (reg_id <= GPIO_ID_PIN(GPIO_PIN_COUNT-1)))
+
+#define GPIO_REGID_TO_PINIDX(reg_id) ((reg_id) - GPIO_ID_PIN0)
+
+typedef enum{
+      GPIO_PIN_INTR_DISABLE = 0,
+      GPIO_PIN_INTR_POSEDGE = 1,
+      GPIO_PIN_INTR_NEGEDGE = 2,
+      GPIO_PIN_INTR_ANYEGDE = 3,
+      GPIO_PIN_INTR_LOLEVEL = 4,
+      GPIO_PIN_INTR_HILEVEL = 5
+}GPIO_INT_TYPE;
+
+#define GREEN_LED_ON()  GPIO_OUTPUT_SET(GPIO_ID_PIN(1) , 0)
+#define GREEN_LED_OFF() GPIO_OUTPUT_SET(GPIO_ID_PIN(1) , 1)
+
+#define GPIO_OUTPUT_SET(gpio_no, bit_value) \
+        ((gpio_no < 32) ? gpio_output_set(bit_value<<gpio_no, (bit_value ? 0 : 1)<<gpio_no, 1<<gpio_no,0) : \
+                         gpio_output_set_high(bit_value<<(gpio_no - 32), (bit_value ? 0 : 1)<<(gpio_no - 32), 1<<(gpio_no -32),0))
+#define GPIO_DIS_OUTPUT(gpio_no)    ((gpio_no < 32) ? gpio_output_set(0,0,0, 1<<gpio_no) : gpio_output_set_high(0,0,0, 1<<gpio_no))
+#define GPIO_INPUT_GET(gpio_no)     ((gpio_no < 32)? ((gpio_input_get()>>gpio_no)&BIT0) : ((gpio_input_get_high()>>(gpio_no - 32))&BIT0))
+
+/* GPIO interrupt handler, registered through gpio_intr_handler_register */
+typedef void (* gpio_intr_handler_fn_t)(uint32_t intr_mask, bool high, void *arg);
+
+
+/*
+ * Initialize GPIO.  This includes reading the GPIO Configuration DataSet
+ * to initialize "output enables" and pin configurations for each gpio pin.
+ * Must be called once during startup.
+ */
+void gpio_init(void) ROMFN_ATTR;
+
+/*
+ * Change GPIO pin output by setting, clearing, or disabling pins.
+ * In general, it is expected that a bit will be set in at most one
+ * of these masks.  If a bit is clear in all masks, the output state
+ * remains unchanged.
+ *
+ * There is no particular ordering guaranteed; so if the order of
+ * writes is significant, calling code should divide a single call
+ * into multiple calls.
+ */
+void gpio_output_set(uint32_t set_mask,
+        uint32_t clear_mask,
+        uint32_t enable_mask,
+        uint32_t disable_mask) ROMFN_ATTR;
+void gpio_output_set_high(uint32_t set_mask,
+        uint32_t clear_mask,
+        uint32_t enable_mask,
+        uint32_t disable_mask) ROMFN_ATTR;
+/*
+ * Sample the value of GPIO input pins and returns a bitmask.
+ */
+uint32_t gpio_input_get(void) ROMFN_ATTR;
+uint32_t gpio_input_get_high(void) ROMFN_ATTR;
+
+/*
+ * Set the specified GPIO register to the specified value.
+ * This is a very general and powerful interface that is not
+ * expected to be used during normal operation.  It is intended
+ * mainly for debug, or for unusual requirements.
+ */
+void gpio_register_set(uint32_t reg_id, uint32_t value) ROMFN_ATTR;
+
+/* Get the current value of the specified GPIO register. */
+uint32_t gpio_register_get(uint32_t reg_id) ROMFN_ATTR;
+
+/*
+ * Register an application-specific interrupt handler for GPIO pin
+ * interrupts.  Once the interrupt handler is called, it will not 
+ * be called again until after a call to gpio_intr_ack.  Any GPIO
+ * interrupts that occur during the interim are masked.
+ *
+ * The application-specific handler is called with a mask of
+ * pending GPIO interrupts.  After processing pin interrupts, the
+ * application-specific handler may wish to use gpio_intr_pending
+ * to check for any additional pending interrupts before it returns.
+ */
+void gpio_intr_handler_register(gpio_intr_handler_fn_t fn, void *arg) ROMFN_ATTR;
+
+/* Determine which GPIO interrupts are pending. */
+uint32_t gpio_intr_pending(void) ROMFN_ATTR;
+uint32_t gpio_intr_pending_high(void) ROMFN_ATTR;
+
+/*
+ * Acknowledge GPIO interrupts.
+ * Intended to be called from the gpio_intr_handler_fn.
+ */
+void gpio_intr_ack(uint32_t ack_mask) ROMFN_ATTR;
+void gpio_intr_ack_high(uint32_t ack_mask) ROMFN_ATTR;
+
+void gpio_pin_wakeup_enable(uint32_t i, GPIO_INT_TYPE intr_state) ROMFN_ATTR;
+
+void gpio_pin_wakeup_disable() ROMFN_ATTR;
+
+//extern void gpio_module_install(struct gpio_api *api);
+
+void gpio_matrix_in(uint32_t gpio, uint32_t signal_idx, bool inv) ROMFN_ATTR;
+
+void gpio_matrix_out(uint32_t gpio, uint32_t signal_idx, bool out_inv, bool oen_inv) ROMFN_ATTR;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _ROM_GPIO_H_ */

components/esp32/include/rom/libc_stubs.h

@@ -0,0 +1,89 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _ROM_LIBC_STUBS_H_
+#define _ROM_LIBC_STUBS_H_
+
+#include <stddef.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <stdarg.h>
+#include <reent.h>
+#include <errno.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* 
+ESP32 ROM code contains implementations of some of C library functions.
+Whenever a function in ROM needs to use a syscall, it calls a pointer to the corresponding syscall
+implementation defined in the following struct.
+
+The table itself, by default, is not allocated in RAM. There are two pointers, `syscall_table_ptr_pro` and
+`syscall_table_ptr_app`, which can be set to point to the locations of syscall tables of CPU 0 (aka PRO CPU)
+and CPU 1 (aka APP CPU). Location of these pointers in .bss segment of ROM code is defined in linker script.
+
+So, before using any of the C library functions (except for pure functions and memcpy/memset functions),
+application must allocate syscall table structure for each CPU being used, and populate it with pointers
+to actual implementations of corresponding syscalls.
+*/
+
+struct syscall_stub_table 
+{
+    struct _reent* (*__getreent)(void);
+    void* (*_malloc_r)(struct _reent *r, size_t);
+    void (*_free_r)(struct _reent *r, void*);
+    void* (*_realloc_r)(struct _reent *r, void*, size_t);
+    void* (*_calloc_r)(struct _reent *r, size_t, size_t);
+    void (*_abort)(void);
+    int (*_system_r)(struct _reent *r, const char*);
+    int (*_rename_r)(struct _reent *r, const char*, const char*);
+    clock_t (*_times_r)(struct _reent *r, struct tms *);
+    int (*_gettimeofday_r) (struct _reent *r, struct timeval *, void *);
+    void (*_raise_r)(struct _reent *r);
+    int (*_unlink_r)(struct _reent *r, const char*);
+    int (*_link_r)(struct _reent *r, const char*, const char*);
+    int (*_stat_r)(struct _reent *r, const char*, struct stat *);
+    int (*_fstat_r)(struct _reent *r, int, struct stat *);
+    void* (*_sbrk_r)(struct _reent *r, ptrdiff_t);
+    int (*_getpid_r)(struct _reent *r);
+    int (*_kill_r)(struct _reent *r, int, int);
+    void (*_exit_r)(struct _reent *r, int);
+    int (*_close_r)(struct _reent *r, int);
+    int (*_open_r)(struct _reent *r, const char *, int, int);
+    int (*_write_r)(struct _reent *r, int, const void *, int);
+    int (*_lseek_r)(struct _reent *r, int, int, int);
+    int (*_read_r)(struct _reent *r, int, void *, int);
+    void (*_lock_init)(_lock_t *lock);
+    void (*_lock_init_recursive)(_lock_t *lock);
+    void (*_lock_close)(_lock_t *lock);
+    void (*_lock_close_recursive)(_lock_t *lock);
+    void (*_lock_acquire)(_lock_t *lock);
+    void (*_lock_acquire_recursive)(_lock_t *lock);
+    int (*_lock_try_acquire)(_lock_t *lock);
+    int (*_lock_try_acquire_recursive)(_lock_t *lock);
+    void (*_lock_release)(_lock_t *lock);
+    void (*_lock_release_recursive)(_lock_t *lock);
+    int (*_printf_float)(struct _reent *data, void *pdata, FILE * fp, int (*pfunc) (struct _reent *, FILE *, _CONST char *, size_t len), va_list * ap);
+    int (*_scanf_float) (struct _reent *rptr, void *pdata, FILE *fp, va_list *ap);
+};
+
+extern struct syscall_stub_table* syscall_table_ptr_pro;
+extern struct syscall_stub_table* syscall_table_ptr_app;
+
+#ifdef __cplusplus
+} // extern "C"
+#endif
+
+#endif /* _ROM_LIBC_STUBS_H_ */

components/esp32/include/rom/lldesc.h

@@ -0,0 +1,176 @@
+// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef _ROM_LLDESC_H_
+#define _ROM_LLDESC_H_
+
+#include <stdint.h>
+
+#include "queue.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define LLDESC_TX_MBLK_SIZE                 268 /* */
+#define LLDESC_RX_SMBLK_SIZE                64  /* small block size, for small mgmt frame */
+#define LLDESC_RX_MBLK_SIZE                 524 /* rx is large sinec we want to contain mgmt frame in one block*/
+#define LLDESC_RX_AMPDU_ENTRY_MBLK_SIZE    64  /* it is a small buffer which is a cycle link*/
+#define LLDESC_RX_AMPDU_LEN_MBLK_SIZE      256 /*for ampdu entry*/
+#ifdef ESP_MAC_5
+#define LLDESC_TX_MBLK_NUM                  116  /* 64K / 256 */
+#define LLDESC_RX_MBLK_NUM                  82 /* 64K / 512 MAX 172*/
+#define LLDESC_RX_AMPDU_ENTRY_MBLK_NUM     4
+#define LLDESC_RX_AMPDU_LEN_MLBK_NUM       12
+#else
+#ifdef SBUF_RXTX
+#define LLDESC_TX_MBLK_NUM_MAX    (2 * 48) /* 23K / 260 - 8 */
+#define LLDESC_RX_MBLK_NUM_MAX    (2 * 48) /* 23K / 524 */
+#define LLDESC_TX_MBLK_NUM_MIN    (2 * 16) /* 23K / 260 - 8 */
+#define LLDESC_RX_MBLK_NUM_MIN    (2 * 16) /* 23K / 524 */
+#endif
+#define LLDESC_TX_MBLK_NUM      10      //(2 * 32) /* 23K / 260 - 8 */
+
+#ifdef IEEE80211_RX_AMPDU
+#define LLDESC_RX_MBLK_NUM      30
+#else
+#define LLDESC_RX_MBLK_NUM      10
+#endif /*IEEE80211_RX_AMPDU*/
+
+#define LLDESC_RX_AMPDU_ENTRY_MBLK_NUM  4
+#define LLDESC_RX_AMPDU_LEN_MLBK_NUM    8
+#endif /* !ESP_MAC_5 */
+/*
+ *  SLC2 DMA Desc struct, aka lldesc_t
+ * 
+ * -------------------------------------------------------------- 
+ * | own | EoF | sub_sof | 5'b0   | length [11:0] | size [11:0] |
+ * --------------------------------------------------------------
+ * |            buf_ptr [31:0]                                  |
+ * --------------------------------------------------------------
+ * |            next_desc_ptr [31:0]                            |
+ * --------------------------------------------------------------
+ */
+
+/* this bitfield is start from the LSB!!! */
+typedef struct lldesc_s {
+    volatile uint32_t size  :12,
+                        length:12,
+                        offset: 5, /* h/w reserved 5bit, s/w use it as offset in buffer */
+                        sosf  : 1, /* start of sub-frame */
+                        eof   : 1, /* end of frame */
+                        owner : 1; /* hw or sw */
+    volatile uint8_t *buf;       /* point to buffer data */
+    union{
+        volatile uint32_t empty;
+        STAILQ_ENTRY(lldesc_s) qe;  /* pointing to the next desc */
+    };
+} lldesc_t;
+
+typedef struct tx_ampdu_entry_s{
+    uint32_t sub_len  :12,
+              dili_num : 7,
+                       : 1,
+              null_byte: 2,
+              data     : 1,
+              enc      : 1,
+              seq      : 8;
+} tx_ampdu_entry_t;
+
+typedef struct lldesc_chain_s {
+    lldesc_t *head;
+    lldesc_t *tail;
+} lldesc_chain_t;
+
+#ifdef SBUF_RXTX
+enum sbuf_mask_s  {
+    SBUF_MOVE_NO = 0,
+    SBUF_MOVE_TX2RX,
+    SBUF_MOVE_RX2TX,
+} ;
+
+#define SBUF_MOVE_STEP 8
+#endif
+#define LLDESC_SIZE  sizeof(struct lldesc_s)
+
+/* SLC Descriptor  */
+#define LLDESC_OWNER_MASK                  0x80000000
+#define LLDESC_OWNER_SHIFT                         31
+#define LLDESC_SW_OWNED                             0
+#define LLDESC_HW_OWNED                             1
+
+#define LLDESC_EOF_MASK                    0x40000000
+#define LLDESC_EOF_SHIFT                           30
+
+#define LLDESC_SOSF_MASK                   0x20000000
+#define LLDESC_SOSF_SHIFT                          29
+
+#define LLDESC_LENGTH_MASK                 0x00fff000
+#define LLDESC_LENGTH_SHIFT                        12
+
+#define LLDESC_SIZE_MASK                   0x00000fff
+#define LLDESC_SIZE_SHIFT                           0
+
+#define LLDESC_ADDR_MASK                    0x000fffff
+
+void lldesc_build_chain(uint8_t *descptr, uint32_t desclen, uint8_t * mblkptr, uint32_t buflen, uint32_t blksz, uint8_t owner,
+                          lldesc_t **head,
+#ifdef TO_HOST_RESTART
+                          lldesc_t ** one_before_tail,
+#endif
+                          lldesc_t **tail);
+
+lldesc_t *lldesc_num2link(lldesc_t * head, uint16_t nblks);
+
+lldesc_t *lldesc_set_owner(lldesc_t * head, uint16_t nblks, uint8_t owner);
+
+static inline uint32_t lldesc_get_chain_length(lldesc_t *head)
+{
+    lldesc_t *ds = head;
+    uint32_t len = 0;
+    
+    while (ds) {
+        len += ds->length;
+        ds = STAILQ_NEXT(ds, qe);
+    }
+    
+    return len;
+}
+
+static inline void lldesc_config(lldesc_t *ds, uint8_t owner, uint8_t eof, uint8_t sosf, uint16_t len)
+{
+    ds->owner  = owner;
+    ds->eof    = eof;
+    ds->sosf   = sosf;
+    ds->length = len;
+}
+
+#define LLDESC_CONFIG(_desc, _owner, _eof, _sosf, _len)        do { \
+        (_desc)->owner  = (_owner); \
+        (_desc)->eof    = (_eof);   \
+        (_desc)->sosf   = (_sosf);  \
+        (_desc)->length = (_len);   \
+} while(0)
+
+#define LLDESC_FROM_HOST_CLEANUP(ds) LLDESC_CONFIG((ds), LLDESC_HW_OWNED, 0, 0, 0)
+
+#define LLDESC_MAC_RX_CLEANUP(ds) LLDESC_CONFIG((ds), LLDESC_HW_OWNED, 0, 0, (ds)->size)
+
+#define LLDESC_TO_HOST_CLEANUP(ds) LLDESC_CONFIG((ds), LLDESC_HW_OWNED, 0, 0, 0)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _ROM_LLDESC_H_ */

components/esp32/include/rom/md5_hash.h

@@ -0,0 +1,36 @@
+/*
+ * MD5 internal definitions
+ * Copyright (c) 2003-2005, Jouni Malinen <j@w1.fi>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Alternatively, this software may be distributed under the terms of BSD
+ * license.
+ *
+ * See README and COPYING for more details.
+ */
+
+#ifndef _ROM_MD5_HASH_H_
+#define _ROM_MD5_HASH_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct MD5Context {
+	uint32 buf[4];
+	uint32 bits[2];
+	uint8 in[64];
+};
+
+void MD5Init(struct MD5Context *context);
+void MD5Update(struct MD5Context *context, unsigned char const *buf, unsigned len);
+void MD5Final(unsigned char digest[16], struct MD5Context *context);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _ROM_MD5_HASH_H_ */

components/esp32/include/rom/miniz.h

@@ -0,0 +1,777 @@
+#ifndef MINIZ_HEADER_INCLUDED
+#define MINIZ_HEADER_INCLUDED
+
+#include <stdlib.h>
+
+// Defines to completely disable specific portions of miniz.c:
+// If all macros here are defined the only functionality remaining will be CRC-32, adler-32, tinfl, and tdefl.
+
+// Define MINIZ_NO_STDIO to disable all usage and any functions which rely on stdio for file I/O.
+#define MINIZ_NO_STDIO
+
+// If MINIZ_NO_TIME is specified then the ZIP archive functions will not be able to get the current time, or
+// get/set file times, and the C run-time funcs that get/set times won't be called.
+// The current downside is the times written to your archives will be from 1979.
+#define MINIZ_NO_TIME
+
+// Define MINIZ_NO_ARCHIVE_APIS to disable all ZIP archive API's.
+#define MINIZ_NO_ARCHIVE_APIS
+
+// Define MINIZ_NO_ARCHIVE_APIS to disable all writing related ZIP archive API's.
+#define MINIZ_NO_ARCHIVE_WRITING_APIS
+
+// Define MINIZ_NO_ZLIB_APIS to remove all ZLIB-style compression/decompression API's.
+#define MINIZ_NO_ZLIB_APIS
+
+// Define MINIZ_NO_ZLIB_COMPATIBLE_NAME to disable zlib names, to prevent conflicts against stock zlib.
+#define MINIZ_NO_ZLIB_COMPATIBLE_NAMES
+
+// Define MINIZ_NO_MALLOC to disable all calls to malloc, free, and realloc.
+// Note if MINIZ_NO_MALLOC is defined then the user must always provide custom user alloc/free/realloc
+// callbacks to the zlib and archive API's, and a few stand-alone helper API's which don't provide custom user
+// functions (such as tdefl_compress_mem_to_heap() and tinfl_decompress_mem_to_heap()) won't work.
+#define MINIZ_NO_MALLOC
+
+#if defined(__TINYC__) && (defined(__linux) || defined(__linux__))
+  // TODO: Work around "error: include file 'sys\utime.h' when compiling with tcc on Linux
+  #define MINIZ_NO_TIME
+#endif
+
+#if !defined(MINIZ_NO_TIME) && !defined(MINIZ_NO_ARCHIVE_APIS)
+  #include <time.h>
+#endif
+
+//Hardcoded options for Xtensa - JD
+#define MINIZ_X86_OR_X64_CPU 0
+#define MINIZ_LITTLE_ENDIAN 1
+#define MINIZ_USE_UNALIGNED_LOADS_AND_STORES 0
+#define MINIZ_HAS_64BIT_REGISTERS 0
+#define TINFL_USE_64BIT_BITBUF 0
+
+
+#if defined(_M_IX86) || defined(_M_X64) || defined(__i386__) || defined(__i386) || defined(__i486__) || defined(__i486) || defined(i386) || defined(__ia64__) || defined(__x86_64__)
+// MINIZ_X86_OR_X64_CPU is only used to help set the below macros.
+#define MINIZ_X86_OR_X64_CPU 1
+#endif
+
+#if (__BYTE_ORDER__==__ORDER_LITTLE_ENDIAN__) || MINIZ_X86_OR_X64_CPU
+// Set MINIZ_LITTLE_ENDIAN to 1 if the processor is little endian.
+#define MINIZ_LITTLE_ENDIAN 1
+#endif
+
+#if MINIZ_X86_OR_X64_CPU
+// Set MINIZ_USE_UNALIGNED_LOADS_AND_STORES to 1 on CPU's that permit efficient integer loads and stores from unaligned addresses.
+#define MINIZ_USE_UNALIGNED_LOADS_AND_STORES 1
+#endif
+
+#if defined(_M_X64) || defined(_WIN64) || defined(__MINGW64__) || defined(_LP64) || defined(__LP64__) || defined(__ia64__) || defined(__x86_64__)
+// Set MINIZ_HAS_64BIT_REGISTERS to 1 if operations on 64-bit integers are reasonably fast (and don't involve compiler generated calls to helper functions).
+#define MINIZ_HAS_64BIT_REGISTERS 1
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// ------------------- zlib-style API Definitions.
+
+// For more compatibility with zlib, miniz.c uses unsigned long for some parameters/struct members. Beware: mz_ulong can be either 32 or 64-bits!
+typedef unsigned long mz_ulong;
+
+// mz_free() internally uses the MZ_FREE() macro (which by default calls free() unless you've modified the MZ_MALLOC macro) to release a block allocated from the heap.
+void mz_free(void *p);
+
+#define MZ_ADLER32_INIT (1)
+// mz_adler32() returns the initial adler-32 value to use when called with ptr==NULL.
+mz_ulong mz_adler32(mz_ulong adler, const unsigned char *ptr, size_t buf_len);
+
+#define MZ_CRC32_INIT (0)
+// mz_crc32() returns the initial CRC-32 value to use when called with ptr==NULL.
+mz_ulong mz_crc32(mz_ulong crc, const unsigned char *ptr, size_t buf_len);
+
+// Compression strategies.
+enum { MZ_DEFAULT_STRATEGY = 0, MZ_FILTERED = 1, MZ_HUFFMAN_ONLY = 2, MZ_RLE = 3, MZ_FIXED = 4 };
+
+// Method
+#define MZ_DEFLATED 8
+
+#ifndef MINIZ_NO_ZLIB_APIS
+
+// Heap allocation callbacks.
+// Note that mz_alloc_func parameter types purpsosely differ from zlib's: items/size is size_t, not unsigned long.
+typedef void *(*mz_alloc_func)(void *opaque, size_t items, size_t size);
+typedef void (*mz_free_func)(void *opaque, void *address);
+typedef void *(*mz_realloc_func)(void *opaque, void *address, size_t items, size_t size);
+
+#define MZ_VERSION          "9.1.15"
+#define MZ_VERNUM           0x91F0
+#define MZ_VER_MAJOR        9
+#define MZ_VER_MINOR        1
+#define MZ_VER_REVISION     15
+#define MZ_VER_SUBREVISION  0
+
+// Flush values. For typical usage you only need MZ_NO_FLUSH and MZ_FINISH. The other values are for advanced use (refer to the zlib docs).
+enum { MZ_NO_FLUSH = 0, MZ_PARTIAL_FLUSH = 1, MZ_SYNC_FLUSH = 2, MZ_FULL_FLUSH = 3, MZ_FINISH = 4, MZ_BLOCK = 5 };
+
+// Return status codes. MZ_PARAM_ERROR is non-standard.
+enum { MZ_OK = 0, MZ_STREAM_END = 1, MZ_NEED_DICT = 2, MZ_ERRNO = -1, MZ_STREAM_ERROR = -2, MZ_DATA_ERROR = -3, MZ_MEM_ERROR = -4, MZ_BUF_ERROR = -5, MZ_VERSION_ERROR = -6, MZ_PARAM_ERROR = -10000 };
+
+// Compression levels: 0-9 are the standard zlib-style levels, 10 is best possible compression (not zlib compatible, and may be very slow), MZ_DEFAULT_COMPRESSION=MZ_DEFAULT_LEVEL.
+enum { MZ_NO_COMPRESSION = 0, MZ_BEST_SPEED = 1, MZ_BEST_COMPRESSION = 9, MZ_UBER_COMPRESSION = 10, MZ_DEFAULT_LEVEL = 6, MZ_DEFAULT_COMPRESSION = -1 };
+
+// Window bits
+#define MZ_DEFAULT_WINDOW_BITS 15
+
+struct mz_internal_state;
+
+// Compression/decompression stream struct.
+typedef struct mz_stream_s
+{
+  const unsigned char *next_in;     // pointer to next byte to read
+  unsigned int avail_in;            // number of bytes available at next_in
+  mz_ulong total_in;                // total number of bytes consumed so far
+
+  unsigned char *next_out;          // pointer to next byte to write
+  unsigned int avail_out;           // number of bytes that can be written to next_out
+  mz_ulong total_out;               // total number of bytes produced so far
+
+  char *msg;                        // error msg (unused)
+  struct mz_internal_state *state;  // internal state, allocated by zalloc/zfree
+
+  mz_alloc_func zalloc;             // optional heap allocation function (defaults to malloc)
+  mz_free_func zfree;               // optional heap free function (defaults to free)
+  void *opaque;                     // heap alloc function user pointer
+
+  int data_type;                    // data_type (unused)
+  mz_ulong adler;                   // adler32 of the source or uncompressed data
+  mz_ulong reserved;                // not used
+} mz_stream;
+
+typedef mz_stream *mz_streamp;
+
+// Returns the version string of miniz.c.
+const char *mz_version(void);
+
+// mz_deflateInit() initializes a compressor with default options:
+// Parameters:
+//  pStream must point to an initialized mz_stream struct.
+//  level must be between [MZ_NO_COMPRESSION, MZ_BEST_COMPRESSION].
+//  level 1 enables a specially optimized compression function that's been optimized purely for performance, not ratio.
+//  (This special func. is currently only enabled when MINIZ_USE_UNALIGNED_LOADS_AND_STORES and MINIZ_LITTLE_ENDIAN are defined.)
+// Return values:
+//  MZ_OK on success.
+//  MZ_STREAM_ERROR if the stream is bogus.
+//  MZ_PARAM_ERROR if the input parameters are bogus.
+//  MZ_MEM_ERROR on out of memory.
+int mz_deflateInit(mz_streamp pStream, int level);
+
+// mz_deflateInit2() is like mz_deflate(), except with more control:
+// Additional parameters:
+//   method must be MZ_DEFLATED
+//   window_bits must be MZ_DEFAULT_WINDOW_BITS (to wrap the deflate stream with zlib header/adler-32 footer) or -MZ_DEFAULT_WINDOW_BITS (raw deflate/no header or footer)
+//   mem_level must be between [1, 9] (it's checked but ignored by miniz.c)
+int mz_deflateInit2(mz_streamp pStream, int level, int method, int window_bits, int mem_level, int strategy);
+
+// Quickly resets a compressor without having to reallocate anything. Same as calling mz_deflateEnd() followed by mz_deflateInit()/mz_deflateInit2().
+int mz_deflateReset(mz_streamp pStream);
+
+// mz_deflate() compresses the input to output, consuming as much of the input and producing as much output as possible.
+// Parameters:
+//   pStream is the stream to read from and write to. You must initialize/update the next_in, avail_in, next_out, and avail_out members.
+//   flush may be MZ_NO_FLUSH, MZ_PARTIAL_FLUSH/MZ_SYNC_FLUSH, MZ_FULL_FLUSH, or MZ_FINISH.
+// Return values:
+//   MZ_OK on success (when flushing, or if more input is needed but not available, and/or there's more output to be written but the output buffer is full).
+//   MZ_STREAM_END if all input has been consumed and all output bytes have been written. Don't call mz_deflate() on the stream anymore.
+//   MZ_STREAM_ERROR if the stream is bogus.
+//   MZ_PARAM_ERROR if one of the parameters is invalid.
+//   MZ_BUF_ERROR if no forward progress is possible because the input and/or output buffers are empty. (Fill up the input buffer or free up some output space and try again.)
+int mz_deflate(mz_streamp pStream, int flush);
+
+// mz_deflateEnd() deinitializes a compressor:
+// Return values:
+//  MZ_OK on success.
+//  MZ_STREAM_ERROR if the stream is bogus.
+int mz_deflateEnd(mz_streamp pStream);
+
+// mz_deflateBound() returns a (very) conservative upper bound on the amount of data that could be generated by deflate(), assuming flush is set to only MZ_NO_FLUSH or MZ_FINISH.
+mz_ulong mz_deflateBound(mz_streamp pStream, mz_ulong source_len);
+
+// Single-call compression functions mz_compress() and mz_compress2():
+// Returns MZ_OK on success, or one of the error codes from mz_deflate() on failure.
+int mz_compress(unsigned char *pDest, mz_ulong *pDest_len, const unsigned char *pSource, mz_ulong source_len);
+int mz_compress2(unsigned char *pDest, mz_ulong *pDest_len, const unsigned char *pSource, mz_ulong source_len, int level);
+
+// mz_compressBound() returns a (very) conservative upper bound on the amount of data that could be generated by calling mz_compress().
+mz_ulong mz_compressBound(mz_ulong source_len);
+
+// Initializes a decompressor.
+int mz_inflateInit(mz_streamp pStream);
+
+// mz_inflateInit2() is like mz_inflateInit() with an additional option that controls the window size and whether or not the stream has been wrapped with a zlib header/footer:
+// window_bits must be MZ_DEFAULT_WINDOW_BITS (to parse zlib header/footer) or -MZ_DEFAULT_WINDOW_BITS (raw deflate).
+int mz_inflateInit2(mz_streamp pStream, int window_bits);
+
+// Decompresses the input stream to the output, consuming only as much of the input as needed, and writing as much to the output as possible.
+// Parameters:
+//   pStream is the stream to read from and write to. You must initialize/update the next_in, avail_in, next_out, and avail_out members.
+//   flush may be MZ_NO_FLUSH, MZ_SYNC_FLUSH, or MZ_FINISH.
+//   On the first call, if flush is MZ_FINISH it's assumed the input and output buffers are both sized large enough to decompress the entire stream in a single call (this is slightly faster).
+//   MZ_FINISH implies that there are no more source bytes available beside what's already in the input buffer, and that the output buffer is large enough to hold the rest of the decompressed data.
+// Return values:
+//   MZ_OK on success. Either more input is needed but not available, and/or there's more output to be written but the output buffer is full.
+//   MZ_STREAM_END if all needed input has been consumed and all output bytes have been written. For zlib streams, the adler-32 of the decompressed data has also been verified.
+//   MZ_STREAM_ERROR if the stream is bogus.
+//   MZ_DATA_ERROR if the deflate stream is invalid.
+//   MZ_PARAM_ERROR if one of the parameters is invalid.
+//   MZ_BUF_ERROR if no forward progress is possible because the input buffer is empty but the inflater needs more input to continue, or if the output buffer is not large enough. Call mz_inflate() again
+//   with more input data, or with more room in the output buffer (except when using single call decompression, described above).
+int mz_inflate(mz_streamp pStream, int flush);
+
+// Deinitializes a decompressor.
+int mz_inflateEnd(mz_streamp pStream);
+
+// Single-call decompression.
+// Returns MZ_OK on success, or one of the error codes from mz_inflate() on failure.
+int mz_uncompress(unsigned char *pDest, mz_ulong *pDest_len, const unsigned char *pSource, mz_ulong source_len);
+
+// Returns a string description of the specified error code, or NULL if the error code is invalid.
+const char *mz_error(int err);
+
+// Redefine zlib-compatible names to miniz equivalents, so miniz.c can be used as a drop-in replacement for the subset of zlib that miniz.c supports.
+// Define MINIZ_NO_ZLIB_COMPATIBLE_NAMES to disable zlib-compatibility if you use zlib in the same project.
+#ifndef MINIZ_NO_ZLIB_COMPATIBLE_NAMES
+  typedef unsigned char Byte;
+  typedef unsigned int uInt;
+  typedef mz_ulong uLong;
+  typedef Byte Bytef;
+  typedef uInt uIntf;
+  typedef char charf;
+  typedef int intf;
+  typedef void *voidpf;
+  typedef uLong uLongf;
+  typedef void *voidp;
+  typedef void *const voidpc;
+  #define Z_NULL                0
+  #define Z_NO_FLUSH            MZ_NO_FLUSH
+  #define Z_PARTIAL_FLUSH       MZ_PARTIAL_FLUSH
+  #define Z_SYNC_FLUSH          MZ_SYNC_FLUSH
+  #define Z_FULL_FLUSH          MZ_FULL_FLUSH
+  #define Z_FINISH              MZ_FINISH
+  #define Z_BLOCK               MZ_BLOCK
+  #define Z_OK                  MZ_OK
+  #define Z_STREAM_END          MZ_STREAM_END
+  #define Z_NEED_DICT           MZ_NEED_DICT
+  #define Z_ERRNO               MZ_ERRNO
+  #define Z_STREAM_ERROR        MZ_STREAM_ERROR
+  #define Z_DATA_ERROR          MZ_DATA_ERROR
+  #define Z_MEM_ERROR           MZ_MEM_ERROR
+  #define Z_BUF_ERROR           MZ_BUF_ERROR
+  #define Z_VERSION_ERROR       MZ_VERSION_ERROR
+  #define Z_PARAM_ERROR         MZ_PARAM_ERROR
+  #define Z_NO_COMPRESSION      MZ_NO_COMPRESSION
+  #define Z_BEST_SPEED          MZ_BEST_SPEED
+  #define Z_BEST_COMPRESSION    MZ_BEST_COMPRESSION
+  #define Z_DEFAULT_COMPRESSION MZ_DEFAULT_COMPRESSION
+  #define Z_DEFAULT_STRATEGY    MZ_DEFAULT_STRATEGY
+  #define Z_FILTERED            MZ_FILTERED
+  #define Z_HUFFMAN_ONLY        MZ_HUFFMAN_ONLY
+  #define Z_RLE                 MZ_RLE
+  #define Z_FIXED               MZ_FIXED
+  #define Z_DEFLATED            MZ_DEFLATED
+  #define Z_DEFAULT_WINDOW_BITS MZ_DEFAULT_WINDOW_BITS
+  #define alloc_func            mz_alloc_func
+  #define free_func             mz_free_func
+  #define internal_state        mz_internal_state
+  #define z_stream              mz_stream
+  #define deflateInit           mz_deflateInit
+  #define deflateInit2          mz_deflateInit2
+  #define deflateReset          mz_deflateReset
+  #define deflate               mz_deflate
+  #define deflateEnd            mz_deflateEnd
+  #define deflateBound          mz_deflateBound
+  #define compress              mz_compress
+  #define compress2             mz_compress2
+  #define compressBound         mz_compressBound
+  #define inflateInit           mz_inflateInit
+  #define inflateInit2          mz_inflateInit2
+  #define inflate               mz_inflate
+  #define inflateEnd            mz_inflateEnd
+  #define uncompress            mz_uncompress
+  #define crc32                 mz_crc32
+  #define adler32               mz_adler32
+  #define MAX_WBITS             15
+  #define MAX_MEM_LEVEL         9
+  #define zError                mz_error
+  #define ZLIB_VERSION          MZ_VERSION
+  #define ZLIB_VERNUM           MZ_VERNUM
+  #define ZLIB_VER_MAJOR        MZ_VER_MAJOR
+  #define ZLIB_VER_MINOR        MZ_VER_MINOR
+  #define ZLIB_VER_REVISION     MZ_VER_REVISION
+  #define ZLIB_VER_SUBREVISION  MZ_VER_SUBREVISION
+  #define zlibVersion           mz_version
+  #define zlib_version          mz_version()
+#endif // #ifndef MINIZ_NO_ZLIB_COMPATIBLE_NAMES
+
+#endif // MINIZ_NO_ZLIB_APIS
+
+// ------------------- Types and macros
+
+typedef unsigned char mz_uint8;
+typedef signed short mz_int16;
+typedef unsigned short mz_uint16;
+typedef unsigned int mz_uint32;
+typedef unsigned int mz_uint;
+typedef long long mz_int64;
+typedef unsigned long long mz_uint64;
+typedef int mz_bool;
+
+#define MZ_FALSE (0)
+#define MZ_TRUE (1)
+
+// An attempt to work around MSVC's spammy "warning C4127: conditional expression is constant" message.
+#ifdef _MSC_VER
+   #define MZ_MACRO_END while (0, 0)
+#else
+   #define MZ_MACRO_END while (0)
+#endif
+
+// ------------------- ZIP archive reading/writing
+
+#ifndef MINIZ_NO_ARCHIVE_APIS
+
+enum
+{
+  MZ_ZIP_MAX_IO_BUF_SIZE = 64*1024,
+  MZ_ZIP_MAX_ARCHIVE_FILENAME_SIZE = 260,
+  MZ_ZIP_MAX_ARCHIVE_FILE_COMMENT_SIZE = 256
+};
+
+typedef struct
+{
+  mz_uint32 m_file_index;
+  mz_uint32 m_central_dir_ofs;
+  mz_uint16 m_version_made_by;
+  mz_uint16 m_version_needed;
+  mz_uint16 m_bit_flag;
+  mz_uint16 m_method;
+#ifndef MINIZ_NO_TIME
+  time_t m_time;
+#endif
+  mz_uint32 m_crc32;
+  mz_uint64 m_comp_size;
+  mz_uint64 m_uncomp_size;
+  mz_uint16 m_internal_attr;
+  mz_uint32 m_external_attr;
+  mz_uint64 m_local_header_ofs;
+  mz_uint32 m_comment_size;
+  char m_filename[MZ_ZIP_MAX_ARCHIVE_FILENAME_SIZE];
+  char m_comment[MZ_ZIP_MAX_ARCHIVE_FILE_COMMENT_SIZE];
+} mz_zip_archive_file_stat;
+
+typedef size_t (*mz_file_read_func)(void *pOpaque, mz_uint64 file_ofs, void *pBuf, size_t n);
+typedef size_t (*mz_file_write_func)(void *pOpaque, mz_uint64 file_ofs, const void *pBuf, size_t n);
+
+struct mz_zip_internal_state_tag;
+typedef struct mz_zip_internal_state_tag mz_zip_internal_state;
+
+typedef enum
+{
+  MZ_ZIP_MODE_INVALID = 0,
+  MZ_ZIP_MODE_READING = 1,
+  MZ_ZIP_MODE_WRITING = 2,
+  MZ_ZIP_MODE_WRITING_HAS_BEEN_FINALIZED = 3
+} mz_zip_mode;
+
+typedef struct mz_zip_archive_tag
+{
+  mz_uint64 m_archive_size;
+  mz_uint64 m_central_directory_file_ofs;
+  mz_uint m_total_files;
+  mz_zip_mode m_zip_mode;
+
+  mz_uint m_file_offset_alignment;
+
+  mz_alloc_func m_pAlloc;
+  mz_free_func m_pFree;
+  mz_realloc_func m_pRealloc;
+  void *m_pAlloc_opaque;
+
+  mz_file_read_func m_pRead;
+  mz_file_write_func m_pWrite;
+  void *m_pIO_opaque;
+
+  mz_zip_internal_state *m_pState;
+
+} mz_zip_archive;
+
+typedef enum
+{
+  MZ_ZIP_FLAG_CASE_SENSITIVE                = 0x0100,
+  MZ_ZIP_FLAG_IGNORE_PATH                   = 0x0200,
+  MZ_ZIP_FLAG_COMPRESSED_DATA               = 0x0400,
+  MZ_ZIP_FLAG_DO_NOT_SORT_CENTRAL_DIRECTORY = 0x0800
+} mz_zip_flags;
+
+// ZIP archive reading
+
+// Inits a ZIP archive reader.
+// These functions read and validate the archive's central directory.
+mz_bool mz_zip_reader_init(mz_zip_archive *pZip, mz_uint64 size, mz_uint32 flags);
+mz_bool mz_zip_reader_init_mem(mz_zip_archive *pZip, const void *pMem, size_t size, mz_uint32 flags);
+
+#ifndef MINIZ_NO_STDIO
+mz_bool mz_zip_reader_init_file(mz_zip_archive *pZip, const char *pFilename, mz_uint32 flags);
+#endif
+
+// Returns the total number of files in the archive.
+mz_uint mz_zip_reader_get_num_files(mz_zip_archive *pZip);
+
+// Returns detailed information about an archive file entry.
+mz_bool mz_zip_reader_file_stat(mz_zip_archive *pZip, mz_uint file_index, mz_zip_archive_file_stat *pStat);
+
+// Determines if an archive file entry is a directory entry.
+mz_bool mz_zip_reader_is_file_a_directory(mz_zip_archive *pZip, mz_uint file_index);
+mz_bool mz_zip_reader_is_file_encrypted(mz_zip_archive *pZip, mz_uint file_index);
+
+// Retrieves the filename of an archive file entry.
+// Returns the number of bytes written to pFilename, or if filename_buf_size is 0 this function returns the number of bytes needed to fully store the filename.
+mz_uint mz_zip_reader_get_filename(mz_zip_archive *pZip, mz_uint file_index, char *pFilename, mz_uint filename_buf_size);
+
+// Attempts to locates a file in the archive's central directory.
+// Valid flags: MZ_ZIP_FLAG_CASE_SENSITIVE, MZ_ZIP_FLAG_IGNORE_PATH
+// Returns -1 if the file cannot be found.
+int mz_zip_reader_locate_file(mz_zip_archive *pZip, const char *pName, const char *pComment, mz_uint flags);
+
+// Extracts a archive file to a memory buffer using no memory allocation.
+mz_bool mz_zip_reader_extract_to_mem_no_alloc(mz_zip_archive *pZip, mz_uint file_index, void *pBuf, size_t buf_size, mz_uint flags, void *pUser_read_buf, size_t user_read_buf_size);
+mz_bool mz_zip_reader_extract_file_to_mem_no_alloc(mz_zip_archive *pZip, const char *pFilename, void *pBuf, size_t buf_size, mz_uint flags, void *pUser_read_buf, size_t user_read_buf_size);
+
+// Extracts a archive file to a memory buffer.
+mz_bool mz_zip_reader_extract_to_mem(mz_zip_archive *pZip, mz_uint file_index, void *pBuf, size_t buf_size, mz_uint flags);
+mz_bool mz_zip_reader_extract_file_to_mem(mz_zip_archive *pZip, const char *pFilename, void *pBuf, size_t buf_size, mz_uint flags);
+
+// Extracts a archive file to a dynamically allocated heap buffer.
+void *mz_zip_reader_extract_to_heap(mz_zip_archive *pZip, mz_uint file_index, size_t *pSize, mz_uint flags);
+void *mz_zip_reader_extract_file_to_heap(mz_zip_archive *pZip, const char *pFilename, size_t *pSize, mz_uint flags);
+
+// Extracts a archive file using a callback function to output the file's data.
+mz_bool mz_zip_reader_extract_to_callback(mz_zip_archive *pZip, mz_uint file_index, mz_file_write_func pCallback, void *pOpaque, mz_uint flags);
+mz_bool mz_zip_reader_extract_file_to_callback(mz_zip_archive *pZip, const char *pFilename, mz_file_write_func pCallback, void *pOpaque, mz_uint flags);
+
+#ifndef MINIZ_NO_STDIO
+// Extracts a archive file to a disk file and sets its last accessed and modified times.
+// This function only extracts files, not archive directory records.
+mz_bool mz_zip_reader_extract_to_file(mz_zip_archive *pZip, mz_uint file_index, const char *pDst_filename, mz_uint flags);
+mz_bool mz_zip_reader_extract_file_to_file(mz_zip_archive *pZip, const char *pArchive_filename, const char *pDst_filename, mz_uint flags);
+#endif
+
+// Ends archive reading, freeing all allocations, and closing the input archive file if mz_zip_reader_init_file() was used.
+mz_bool mz_zip_reader_end(mz_zip_archive *pZip);
+
+// ZIP archive writing
+
+#ifndef MINIZ_NO_ARCHIVE_WRITING_APIS
+
+// Inits a ZIP archive writer.
+mz_bool mz_zip_writer_init(mz_zip_archive *pZip, mz_uint64 existing_size);
+mz_bool mz_zip_writer_init_heap(mz_zip_archive *pZip, size_t size_to_reserve_at_beginning, size_t initial_allocation_size);
+
+#ifndef MINIZ_NO_STDIO
+mz_bool mz_zip_writer_init_file(mz_zip_archive *pZip, const char *pFilename, mz_uint64 size_to_reserve_at_beginning);
+#endif
+
+// Converts a ZIP archive reader object into a writer object, to allow efficient in-place file appends to occur on an existing archive.
+// For archives opened using mz_zip_reader_init_file, pFilename must be the archive's filename so it can be reopened for writing. If the file can't be reopened, mz_zip_reader_end() will be called.
+// For archives opened using mz_zip_reader_init_mem, the memory block must be growable using the realloc callback (which defaults to realloc unless you've overridden it).
+// Finally, for archives opened using mz_zip_reader_init, the mz_zip_archive's user provided m_pWrite function cannot be NULL.
+// Note: In-place archive modification is not recommended unless you know what you're doing, because if execution stops or something goes wrong before
+// the archive is finalized the file's central directory will be hosed.
+mz_bool mz_zip_writer_init_from_reader(mz_zip_archive *pZip, const char *pFilename);
+
+// Adds the contents of a memory buffer to an archive. These functions record the current local time into the archive.
+// To add a directory entry, call this method with an archive name ending in a forwardslash with empty buffer.
+// level_and_flags - compression level (0-10, see MZ_BEST_SPEED, MZ_BEST_COMPRESSION, etc.) logically OR'd with zero or more mz_zip_flags, or just set to MZ_DEFAULT_COMPRESSION.
+mz_bool mz_zip_writer_add_mem(mz_zip_archive *pZip, const char *pArchive_name, const void *pBuf, size_t buf_size, mz_uint level_and_flags);
+mz_bool mz_zip_writer_add_mem_ex(mz_zip_archive *pZip, const char *pArchive_name, const void *pBuf, size_t buf_size, const void *pComment, mz_uint16 comment_size, mz_uint level_and_flags, mz_uint64 uncomp_size, mz_uint32 uncomp_crc32);
+
+#ifndef MINIZ_NO_STDIO
+// Adds the contents of a disk file to an archive. This function also records the disk file's modified time into the archive.
+// level_and_flags - compression level (0-10, see MZ_BEST_SPEED, MZ_BEST_COMPRESSION, etc.) logically OR'd with zero or more mz_zip_flags, or just set to MZ_DEFAULT_COMPRESSION.
+mz_bool mz_zip_writer_add_file(mz_zip_archive *pZip, const char *pArchive_name, const char *pSrc_filename, const void *pComment, mz_uint16 comment_size, mz_uint level_and_flags);
+#endif
+
+// Adds a file to an archive by fully cloning the data from another archive.
+// This function fully clones the source file's compressed data (no recompression), along with its full filename, extra data, and comment fields.
+mz_bool mz_zip_writer_add_from_zip_reader(mz_zip_archive *pZip, mz_zip_archive *pSource_zip, mz_uint file_index);
+
+// Finalizes the archive by writing the central directory records followed by the end of central directory record.
+// After an archive is finalized, the only valid call on the mz_zip_archive struct is mz_zip_writer_end().
+// An archive must be manually finalized by calling this function for it to be valid.
+mz_bool mz_zip_writer_finalize_archive(mz_zip_archive *pZip);
+mz_bool mz_zip_writer_finalize_heap_archive(mz_zip_archive *pZip, void **pBuf, size_t *pSize);
+
+// Ends archive writing, freeing all allocations, and closing the output file if mz_zip_writer_init_file() was used.
+// Note for the archive to be valid, it must have been finalized before ending.
+mz_bool mz_zip_writer_end(mz_zip_archive *pZip);
+
+// Misc. high-level helper functions:
+
+// mz_zip_add_mem_to_archive_file_in_place() efficiently (but not atomically) appends a memory blob to a ZIP archive.
+// level_and_flags - compression level (0-10, see MZ_BEST_SPEED, MZ_BEST_COMPRESSION, etc.) logically OR'd with zero or more mz_zip_flags, or just set to MZ_DEFAULT_COMPRESSION.
+mz_bool mz_zip_add_mem_to_archive_file_in_place(const char *pZip_filename, const char *pArchive_name, const void *pBuf, size_t buf_size, const void *pComment, mz_uint16 comment_size, mz_uint level_and_flags);
+
+// Reads a single file from an archive into a heap block.
+// Returns NULL on failure.
+void *mz_zip_extract_archive_file_to_heap(const char *pZip_filename, const char *pArchive_name, size_t *pSize, mz_uint zip_flags);
+
+#endif // #ifndef MINIZ_NO_ARCHIVE_WRITING_APIS
+
+#endif // #ifndef MINIZ_NO_ARCHIVE_APIS
+
+// ------------------- Low-level Decompression API Definitions
+
+// Decompression flags used by tinfl_decompress().
+// TINFL_FLAG_PARSE_ZLIB_HEADER: If set, the input has a valid zlib header and ends with an adler32 checksum (it's a valid zlib stream). Otherwise, the input is a raw deflate stream.
+// TINFL_FLAG_HAS_MORE_INPUT: If set, there are more input bytes available beyond the end of the supplied input buffer. If clear, the input buffer contains all remaining input.
+// TINFL_FLAG_USING_NON_WRAPPING_OUTPUT_BUF: If set, the output buffer is large enough to hold the entire decompressed stream. If clear, the output buffer is at least the size of the dictionary (typically 32KB).
+// TINFL_FLAG_COMPUTE_ADLER32: Force adler-32 checksum computation of the decompressed bytes.
+enum
+{
+  TINFL_FLAG_PARSE_ZLIB_HEADER = 1,
+  TINFL_FLAG_HAS_MORE_INPUT = 2,
+  TINFL_FLAG_USING_NON_WRAPPING_OUTPUT_BUF = 4,
+  TINFL_FLAG_COMPUTE_ADLER32 = 8
+};
+
+// High level decompression functions:
+// tinfl_decompress_mem_to_heap() decompresses a block in memory to a heap block allocated via malloc().
+// On entry:
+//  pSrc_buf, src_buf_len: Pointer and size of the Deflate or zlib source data to decompress.
+// On return:
+//  Function returns a pointer to the decompressed data, or NULL on failure.
+//  *pOut_len will be set to the decompressed data's size, which could be larger than src_buf_len on uncompressible data.
+//  The caller must call mz_free() on the returned block when it's no longer needed.
+void *tinfl_decompress_mem_to_heap(const void *pSrc_buf, size_t src_buf_len, size_t *pOut_len, int flags);
+
+// tinfl_decompress_mem_to_mem() decompresses a block in memory to another block in memory.
+// Returns TINFL_DECOMPRESS_MEM_TO_MEM_FAILED on failure, or the number of bytes written on success.
+#define TINFL_DECOMPRESS_MEM_TO_MEM_FAILED ((size_t)(-1))
+size_t tinfl_decompress_mem_to_mem(void *pOut_buf, size_t out_buf_len, const void *pSrc_buf, size_t src_buf_len, int flags);
+
+// tinfl_decompress_mem_to_callback() decompresses a block in memory to an internal 32KB buffer, and a user provided callback function will be called to flush the buffer.
+// Returns 1 on success or 0 on failure.
+typedef int (*tinfl_put_buf_func_ptr)(const void* pBuf, int len, void *pUser);
+int tinfl_decompress_mem_to_callback(const void *pIn_buf, size_t *pIn_buf_size, tinfl_put_buf_func_ptr pPut_buf_func, void *pPut_buf_user, int flags);
+
+struct tinfl_decompressor_tag; typedef struct tinfl_decompressor_tag tinfl_decompressor;
+
+// Max size of LZ dictionary.
+#define TINFL_LZ_DICT_SIZE 32768
+
+// Return status.
+typedef enum
+{
+  TINFL_STATUS_BAD_PARAM = -3,
+  TINFL_STATUS_ADLER32_MISMATCH = -2,
+  TINFL_STATUS_FAILED = -1,
+  TINFL_STATUS_DONE = 0,
+  TINFL_STATUS_NEEDS_MORE_INPUT = 1,
+  TINFL_STATUS_HAS_MORE_OUTPUT = 2
+} tinfl_status;
+
+// Initializes the decompressor to its initial state.
+#define tinfl_init(r) do { (r)->m_state = 0; } MZ_MACRO_END
+#define tinfl_get_adler32(r) (r)->m_check_adler32
+
+// Main low-level decompressor coroutine function. This is the only function actually needed for decompression. All the other functions are just high-level helpers for improved usability.
+// This is a universal API, i.e. it can be used as a building block to build any desired higher level decompression API. In the limit case, it can be called once per every byte input or output.
+tinfl_status tinfl_decompress(tinfl_decompressor *r, const mz_uint8 *pIn_buf_next, size_t *pIn_buf_size, mz_uint8 *pOut_buf_start, mz_uint8 *pOut_buf_next, size_t *pOut_buf_size, const mz_uint32 decomp_flags);
+
+// Internal/private bits follow.
+enum
+{
+  TINFL_MAX_HUFF_TABLES = 3, TINFL_MAX_HUFF_SYMBOLS_0 = 288, TINFL_MAX_HUFF_SYMBOLS_1 = 32, TINFL_MAX_HUFF_SYMBOLS_2 = 19,
+  TINFL_FAST_LOOKUP_BITS = 10, TINFL_FAST_LOOKUP_SIZE = 1 << TINFL_FAST_LOOKUP_BITS
+};
+
+typedef struct
+{
+  mz_uint8 m_code_size[TINFL_MAX_HUFF_SYMBOLS_0];
+  mz_int16 m_look_up[TINFL_FAST_LOOKUP_SIZE], m_tree[TINFL_MAX_HUFF_SYMBOLS_0 * 2];
+} tinfl_huff_table;
+
+#if MINIZ_HAS_64BIT_REGISTERS
+  #define TINFL_USE_64BIT_BITBUF 1
+#endif
+
+#if TINFL_USE_64BIT_BITBUF
+  typedef mz_uint64 tinfl_bit_buf_t;
+  #define TINFL_BITBUF_SIZE (64)
+#else
+  typedef mz_uint32 tinfl_bit_buf_t;
+  #define TINFL_BITBUF_SIZE (32)
+#endif
+
+struct tinfl_decompressor_tag
+{
+  mz_uint32 m_state, m_num_bits, m_zhdr0, m_zhdr1, m_z_adler32, m_final, m_type, m_check_adler32, m_dist, m_counter, m_num_extra, m_table_sizes[TINFL_MAX_HUFF_TABLES];
+  tinfl_bit_buf_t m_bit_buf;
+  size_t m_dist_from_out_buf_start;
+  tinfl_huff_table m_tables[TINFL_MAX_HUFF_TABLES];
+  mz_uint8 m_raw_header[4], m_len_codes[TINFL_MAX_HUFF_SYMBOLS_0 + TINFL_MAX_HUFF_SYMBOLS_1 + 137];
+};
+
+// ------------------- Low-level Compression API Definitions
+
+// Set TDEFL_LESS_MEMORY to 1 to use less memory (compression will be slightly slower, and raw/dynamic blocks will be output more frequently).
+#define TDEFL_LESS_MEMORY 1
+
+// tdefl_init() compression flags logically OR'd together (low 12 bits contain the max. number of probes per dictionary search):
+// TDEFL_DEFAULT_MAX_PROBES: The compressor defaults to 128 dictionary probes per dictionary search. 0=Huffman only, 1=Huffman+LZ (fastest/crap compression), 4095=Huffman+LZ (slowest/best compression).
+enum
+{
+  TDEFL_HUFFMAN_ONLY = 0, TDEFL_DEFAULT_MAX_PROBES = 128, TDEFL_MAX_PROBES_MASK = 0xFFF
+};
+
+// TDEFL_WRITE_ZLIB_HEADER: If set, the compressor outputs a zlib header before the deflate data, and the Adler-32 of the source data at the end. Otherwise, you'll get raw deflate data.
+// TDEFL_COMPUTE_ADLER32: Always compute the adler-32 of the input data (even when not writing zlib headers).
+// TDEFL_GREEDY_PARSING_FLAG: Set to use faster greedy parsing, instead of more efficient lazy parsing.
+// TDEFL_NONDETERMINISTIC_PARSING_FLAG: Enable to decrease the compressor's initialization time to the minimum, but the output may vary from run to run given the same input (depending on the contents of memory).
+// TDEFL_RLE_MATCHES: Only look for RLE matches (matches with a distance of 1)
+// TDEFL_FILTER_MATCHES: Discards matches <= 5 chars if enabled.
+// TDEFL_FORCE_ALL_STATIC_BLOCKS: Disable usage of optimized Huffman tables.
+// TDEFL_FORCE_ALL_RAW_BLOCKS: Only use raw (uncompressed) deflate blocks.
+// The low 12 bits are reserved to control the max # of hash probes per dictionary lookup (see TDEFL_MAX_PROBES_MASK).
+enum
+{
+  TDEFL_WRITE_ZLIB_HEADER             = 0x01000,
+  TDEFL_COMPUTE_ADLER32               = 0x02000,
+  TDEFL_GREEDY_PARSING_FLAG           = 0x04000,
+  TDEFL_NONDETERMINISTIC_PARSING_FLAG = 0x08000,
+  TDEFL_RLE_MATCHES                   = 0x10000,
+  TDEFL_FILTER_MATCHES                = 0x20000,
+  TDEFL_FORCE_ALL_STATIC_BLOCKS       = 0x40000,
+  TDEFL_FORCE_ALL_RAW_BLOCKS          = 0x80000
+};
+
+// High level compression functions:
+// tdefl_compress_mem_to_heap() compresses a block in memory to a heap block allocated via malloc().
+// On entry:
+//  pSrc_buf, src_buf_len: Pointer and size of source block to compress.
+//  flags: The max match finder probes (default is 128) logically OR'd against the above flags. Higher probes are slower but improve compression.
+// On return:
+//  Function returns a pointer to the compressed data, or NULL on failure.
+//  *pOut_len will be set to the compressed data's size, which could be larger than src_buf_len on uncompressible data.
+//  The caller must free() the returned block when it's no longer needed.
+void *tdefl_compress_mem_to_heap(const void *pSrc_buf, size_t src_buf_len, size_t *pOut_len, int flags);
+
+// tdefl_compress_mem_to_mem() compresses a block in memory to another block in memory.
+// Returns 0 on failure.
+size_t tdefl_compress_mem_to_mem(void *pOut_buf, size_t out_buf_len, const void *pSrc_buf, size_t src_buf_len, int flags);
+
+// Compresses an image to a compressed PNG file in memory.
+// On entry:
+//  pImage, w, h, and num_chans describe the image to compress. num_chans may be 1, 2, 3, or 4. 
+//  The image pitch in bytes per scanline will be w*num_chans. The leftmost pixel on the top scanline is stored first in memory.
+//  level may range from [0,10], use MZ_NO_COMPRESSION, MZ_BEST_SPEED, MZ_BEST_COMPRESSION, etc. or a decent default is MZ_DEFAULT_LEVEL
+//  If flip is true, the image will be flipped on the Y axis (useful for OpenGL apps).
+// On return:
+//  Function returns a pointer to the compressed data, or NULL on failure.
+//  *pLen_out will be set to the size of the PNG image file.
+//  The caller must mz_free() the returned heap block (which will typically be larger than *pLen_out) when it's no longer needed.
+void *tdefl_write_image_to_png_file_in_memory_ex(const void *pImage, int w, int h, int num_chans, size_t *pLen_out, mz_uint level, mz_bool flip);
+void *tdefl_write_image_to_png_file_in_memory(const void *pImage, int w, int h, int num_chans, size_t *pLen_out);
+
+// Output stream interface. The compressor uses this interface to write compressed data. It'll typically be called TDEFL_OUT_BUF_SIZE at a time.
+typedef mz_bool (*tdefl_put_buf_func_ptr)(const void* pBuf, int len, void *pUser);
+
+// tdefl_compress_mem_to_output() compresses a block to an output stream. The above helpers use this function internally.
+mz_bool tdefl_compress_mem_to_output(const void *pBuf, size_t buf_len, tdefl_put_buf_func_ptr pPut_buf_func, void *pPut_buf_user, int flags);
+
+enum { TDEFL_MAX_HUFF_TABLES = 3, TDEFL_MAX_HUFF_SYMBOLS_0 = 288, TDEFL_MAX_HUFF_SYMBOLS_1 = 32, TDEFL_MAX_HUFF_SYMBOLS_2 = 19, TDEFL_LZ_DICT_SIZE = 32768, TDEFL_LZ_DICT_SIZE_MASK = TDEFL_LZ_DICT_SIZE - 1, TDEFL_MIN_MATCH_LEN = 3, TDEFL_MAX_MATCH_LEN = 258 };
+
+// TDEFL_OUT_BUF_SIZE MUST be large enough to hold a single entire compressed output block (using static/fixed Huffman codes).
+#if TDEFL_LESS_MEMORY
+enum { TDEFL_LZ_CODE_BUF_SIZE = 24 * 1024, TDEFL_OUT_BUF_SIZE = (TDEFL_LZ_CODE_BUF_SIZE * 13 ) / 10, TDEFL_MAX_HUFF_SYMBOLS = 288, TDEFL_LZ_HASH_BITS = 12, TDEFL_LEVEL1_HASH_SIZE_MASK = 4095, TDEFL_LZ_HASH_SHIFT = (TDEFL_LZ_HASH_BITS + 2) / 3, TDEFL_LZ_HASH_SIZE = 1 << TDEFL_LZ_HASH_BITS };
+#else
+enum { TDEFL_LZ_CODE_BUF_SIZE = 64 * 1024, TDEFL_OUT_BUF_SIZE = (TDEFL_LZ_CODE_BUF_SIZE * 13 ) / 10, TDEFL_MAX_HUFF_SYMBOLS = 288, TDEFL_LZ_HASH_BITS = 15, TDEFL_LEVEL1_HASH_SIZE_MASK = 4095, TDEFL_LZ_HASH_SHIFT = (TDEFL_LZ_HASH_BITS + 2) / 3, TDEFL_LZ_HASH_SIZE = 1 << TDEFL_LZ_HASH_BITS };
+#endif
+
+// The low-level tdefl functions below may be used directly if the above helper functions aren't flexible enough. The low-level functions don't make any heap allocations, unlike the above helper functions.
+typedef enum
+{
+  TDEFL_STATUS_BAD_PARAM = -2,
+  TDEFL_STATUS_PUT_BUF_FAILED = -1,
+  TDEFL_STATUS_OKAY = 0,
+  TDEFL_STATUS_DONE = 1,
+} tdefl_status;
+
+// Must map to MZ_NO_FLUSH, MZ_SYNC_FLUSH, etc. enums
+typedef enum
+{
+  TDEFL_NO_FLUSH = 0,
+  TDEFL_SYNC_FLUSH = 2,
+  TDEFL_FULL_FLUSH = 3,
+  TDEFL_FINISH = 4
+} tdefl_flush;
+
+// tdefl's compression state structure.
+typedef struct
+{
+  tdefl_put_buf_func_ptr m_pPut_buf_func;
+  void *m_pPut_buf_user;
+  mz_uint m_flags, m_max_probes[2];
+  int m_greedy_parsing;
+  mz_uint m_adler32, m_lookahead_pos, m_lookahead_size, m_dict_size;
+  mz_uint8 *m_pLZ_code_buf, *m_pLZ_flags, *m_pOutput_buf, *m_pOutput_buf_end;
+  mz_uint m_num_flags_left, m_total_lz_bytes, m_lz_code_buf_dict_pos, m_bits_in, m_bit_buffer;
+  mz_uint m_saved_match_dist, m_saved_match_len, m_saved_lit, m_output_flush_ofs, m_output_flush_remaining, m_finished, m_block_index, m_wants_to_finish;
+  tdefl_status m_prev_return_status;
+  const void *m_pIn_buf;
+  void *m_pOut_buf;
+  size_t *m_pIn_buf_size, *m_pOut_buf_size;
+  tdefl_flush m_flush;
+  const mz_uint8 *m_pSrc;
+  size_t m_src_buf_left, m_out_buf_ofs;
+  mz_uint8 m_dict[TDEFL_LZ_DICT_SIZE + TDEFL_MAX_MATCH_LEN - 1];
+  mz_uint16 m_huff_count[TDEFL_MAX_HUFF_TABLES][TDEFL_MAX_HUFF_SYMBOLS];
+  mz_uint16 m_huff_codes[TDEFL_MAX_HUFF_TABLES][TDEFL_MAX_HUFF_SYMBOLS];
+  mz_uint8 m_huff_code_sizes[TDEFL_MAX_HUFF_TABLES][TDEFL_MAX_HUFF_SYMBOLS];
+  mz_uint8 m_lz_code_buf[TDEFL_LZ_CODE_BUF_SIZE];
+  mz_uint16 m_next[TDEFL_LZ_DICT_SIZE];
+  mz_uint16 m_hash[TDEFL_LZ_HASH_SIZE];
+  mz_uint8 m_output_buf[TDEFL_OUT_BUF_SIZE];
+} tdefl_compressor;
+
+// Initializes the compressor.
+// There is no corresponding deinit() function because the tdefl API's do not dynamically allocate memory.
+// pBut_buf_func: If NULL, output data will be supplied to the specified callback. In this case, the user should call the tdefl_compress_buffer() API for compression.
+// If pBut_buf_func is NULL the user should always call the tdefl_compress() API.
+// flags: See the above enums (TDEFL_HUFFMAN_ONLY, TDEFL_WRITE_ZLIB_HEADER, etc.)
+tdefl_status tdefl_init(tdefl_compressor *d, tdefl_put_buf_func_ptr pPut_buf_func, void *pPut_buf_user, int flags);
+
+// Compresses a block of data, consuming as much of the specified input buffer as possible, and writing as much compressed data to the specified output buffer as possible.
+tdefl_status tdefl_compress(tdefl_compressor *d, const void *pIn_buf, size_t *pIn_buf_size, void *pOut_buf, size_t *pOut_buf_size, tdefl_flush flush);
+
+// tdefl_compress_buffer() is only usable when the tdefl_init() is called with a non-NULL tdefl_put_buf_func_ptr.
+// tdefl_compress_buffer() always consumes the entire input buffer.
+tdefl_status tdefl_compress_buffer(tdefl_compressor *d, const void *pIn_buf, size_t in_buf_size, tdefl_flush flush);
+
+tdefl_status tdefl_get_prev_return_status(tdefl_compressor *d);
+mz_uint32 tdefl_get_adler32(tdefl_compressor *d);
+
+// Can't use tdefl_create_comp_flags_from_zip_params if MINIZ_NO_ZLIB_APIS isn't defined, because it uses some of its macros.
+#ifndef MINIZ_NO_ZLIB_APIS
+// Create tdefl_compress() flags given zlib-style compression parameters.
+// level may range from [0,10] (where 10 is absolute max compression, but may be much slower on some files)
+// window_bits may be -15 (raw deflate) or 15 (zlib)
+// strategy may be either MZ_DEFAULT_STRATEGY, MZ_FILTERED, MZ_HUFFMAN_ONLY, MZ_RLE, or MZ_FIXED
+mz_uint tdefl_create_comp_flags_from_zip_params(int level, int window_bits, int strategy);
+#endif // #ifndef MINIZ_NO_ZLIB_APIS
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // MINIZ_HEADER_INCLUDED
+

components/esp32/include/rom/queue.h

@@ -0,0 +1,645 @@
+/*-
+ * Copyright (c) 1991, 1993
+ *	The Regents of the University of California.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 4. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ *	@(#)queue.h	8.5 (Berkeley) 8/20/94
+ * $FreeBSD$
+ */
+
+#ifndef _SYS_QUEUE_H_
+#define _SYS_QUEUE_H_
+
+#include <sys/cdefs.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * This file defines four types of data structures: singly-linked lists,
+ * singly-linked tail queues, lists and tail queues.
+ *
+ * A singly-linked list is headed by a single forward pointer. The elements
+ * are singly linked for minimum space and pointer manipulation overhead at
+ * the expense of O(n) removal for arbitrary elements. New elements can be
+ * added to the list after an existing element or at the head of the list.
+ * Elements being removed from the head of the list should use the explicit
+ * macro for this purpose for optimum efficiency. A singly-linked list may
+ * only be traversed in the forward direction.  Singly-linked lists are ideal
+ * for applications with large datasets and few or no removals or for
+ * implementing a LIFO queue.
+ *
+ * A singly-linked tail queue is headed by a pair of pointers, one to the
+ * head of the list and the other to the tail of the list. The elements are
+ * singly linked for minimum space and pointer manipulation overhead at the
+ * expense of O(n) removal for arbitrary elements. New elements can be added
+ * to the list after an existing element, at the head of the list, or at the
+ * end of the list. Elements being removed from the head of the tail queue
+ * should use the explicit macro for this purpose for optimum efficiency.
+ * A singly-linked tail queue may only be traversed in the forward direction.
+ * Singly-linked tail queues are ideal for applications with large datasets
+ * and few or no removals or for implementing a FIFO queue.
+ *
+ * A list is headed by a single forward pointer (or an array of forward
+ * pointers for a hash table header). The elements are doubly linked
+ * so that an arbitrary element can be removed without a need to
+ * traverse the list. New elements can be added to the list before
+ * or after an existing element or at the head of the list. A list
+ * may only be traversed in the forward direction.
+ *
+ * A tail queue is headed by a pair of pointers, one to the head of the
+ * list and the other to the tail of the list. The elements are doubly
+ * linked so that an arbitrary element can be removed without a need to
+ * traverse the list. New elements can be added to the list before or
+ * after an existing element, at the head of the list, or at the end of
+ * the list. A tail queue may be traversed in either direction.
+ *
+ * For details on the use of these macros, see the queue(3) manual page.
+ *
+ *
+ *				SLIST	LIST	STAILQ	TAILQ
+ * _HEAD			+	+	+	+
+ * _HEAD_INITIALIZER		+	+	+	+
+ * _ENTRY			+	+	+	+
+ * _INIT			+	+	+	+
+ * _EMPTY			+	+	+	+
+ * _FIRST			+	+	+	+
+ * _NEXT			+	+	+	+
+ * _PREV			-	-	-	+
+ * _LAST			-	-	+	+
+ * _FOREACH			+	+	+	+
+ * _FOREACH_SAFE		+	+	+	+
+ * _FOREACH_REVERSE		-	-	-	+
+ * _FOREACH_REVERSE_SAFE	-	-	-	+
+ * _INSERT_HEAD			+	+	+	+
+ * _INSERT_BEFORE		-	+	-	+
+ * _INSERT_AFTER		+	+	+	+
+ * _INSERT_TAIL			-	-	+	+
+ * _CONCAT			-	-	+	+
+ * _REMOVE_AFTER		+	-	+	-
+ * _REMOVE_HEAD			+	-	+	-
+ * _REMOVE			+	+	+	+
+ *
+ */
+#ifdef QUEUE_MACRO_DEBUG
+/* Store the last 2 places the queue element or head was altered */
+struct qm_trace {
+	char * lastfile;
+	int lastline;
+	char * prevfile;
+	int prevline;
+};
+
+#define	TRACEBUF	struct qm_trace trace;
+#define	TRASHIT(x)	do {(x) = (void *)-1;} while (0)
+#define	QMD_SAVELINK(name, link)	void **name = (void *)&(link)
+
+#define	QMD_TRACE_HEAD(head) do {					\
+	(head)->trace.prevline = (head)->trace.lastline;		\
+	(head)->trace.prevfile = (head)->trace.lastfile;		\
+	(head)->trace.lastline = __LINE__;				\
+	(head)->trace.lastfile = __FILE__;				\
+} while (0)
+
+#define	QMD_TRACE_ELEM(elem) do {					\
+	(elem)->trace.prevline = (elem)->trace.lastline;		\
+	(elem)->trace.prevfile = (elem)->trace.lastfile;		\
+	(elem)->trace.lastline = __LINE__;				\
+	(elem)->trace.lastfile = __FILE__;				\
+} while (0)
+
+#else
+#define	QMD_TRACE_ELEM(elem)
+#define	QMD_TRACE_HEAD(head)
+#define	QMD_SAVELINK(name, link)
+#define	TRACEBUF
+#define	TRASHIT(x)
+#endif	/* QUEUE_MACRO_DEBUG */
+
+/*
+ * Singly-linked List declarations.
+ */
+#define	SLIST_HEAD(name, type)						\
+struct name {								\
+	struct type *slh_first;	/* first element */			\
+}
+
+#define	SLIST_HEAD_INITIALIZER(head)					\
+	{ NULL }
+
+#define	SLIST_ENTRY(type)						\
+struct {								\
+	struct type *sle_next;	/* next element */			\
+}
+
+/*
+ * Singly-linked List functions.
+ */
+#define	SLIST_EMPTY(head)	((head)->slh_first == NULL)
+
+#define	SLIST_FIRST(head)	((head)->slh_first)
+
+#define	SLIST_FOREACH(var, head, field)					\
+	for ((var) = SLIST_FIRST((head));				\
+	    (var);							\
+	    (var) = SLIST_NEXT((var), field))
+
+#define	SLIST_FOREACH_SAFE(var, head, field, tvar)			\
+	for ((var) = SLIST_FIRST((head));				\
+	    (var) && ((tvar) = SLIST_NEXT((var), field), 1);		\
+	    (var) = (tvar))
+
+#define	SLIST_FOREACH_PREVPTR(var, varp, head, field)			\
+	for ((varp) = &SLIST_FIRST((head));				\
+	    ((var) = *(varp)) != NULL;					\
+	    (varp) = &SLIST_NEXT((var), field))
+
+#define	SLIST_INIT(head) do {						\
+	SLIST_FIRST((head)) = NULL;					\
+} while (0)
+
+#define	SLIST_INSERT_AFTER(slistelm, elm, field) do {			\
+	SLIST_NEXT((elm), field) = SLIST_NEXT((slistelm), field);	\
+	SLIST_NEXT((slistelm), field) = (elm);				\
+} while (0)
+
+#define	SLIST_INSERT_HEAD(head, elm, field) do {			\
+	SLIST_NEXT((elm), field) = SLIST_FIRST((head));			\
+	SLIST_FIRST((head)) = (elm);					\
+} while (0)
+
+#define	SLIST_NEXT(elm, field)	((elm)->field.sle_next)
+
+#define	SLIST_REMOVE(head, elm, type, field) do {			\
+	QMD_SAVELINK(oldnext, (elm)->field.sle_next);			\
+	if (SLIST_FIRST((head)) == (elm)) {				\
+		SLIST_REMOVE_HEAD((head), field);			\
+	}								\
+	else {								\
+		struct type *curelm = SLIST_FIRST((head));		\
+		while (SLIST_NEXT(curelm, field) != (elm))		\
+			curelm = SLIST_NEXT(curelm, field);		\
+		SLIST_REMOVE_AFTER(curelm, field);			\
+	}								\
+	TRASHIT(*oldnext);						\
+} while (0)
+
+#define SLIST_REMOVE_AFTER(elm, field) do {				\
+	SLIST_NEXT(elm, field) =					\
+	    SLIST_NEXT(SLIST_NEXT(elm, field), field);			\
+} while (0)
+
+#define	SLIST_REMOVE_HEAD(head, field) do {				\
+	SLIST_FIRST((head)) = SLIST_NEXT(SLIST_FIRST((head)), field);	\
+} while (0)
+
+/*
+ * Singly-linked Tail queue declarations.
+ */
+#define	STAILQ_HEAD(name, type)						\
+struct name {								\
+	struct type *stqh_first;/* first element */			\
+	struct type **stqh_last;/* addr of last next element */		\
+}
+
+#define	STAILQ_HEAD_INITIALIZER(head)					\
+	{ NULL, &(head).stqh_first }
+
+#define	STAILQ_ENTRY(type)						\
+struct {								\
+	struct type *stqe_next;	/* next element */			\
+}
+
+/*
+ * Singly-linked Tail queue functions.
+ */
+#define	STAILQ_CONCAT(head1, head2) do {				\
+	if (!STAILQ_EMPTY((head2))) {					\
+		*(head1)->stqh_last = (head2)->stqh_first;		\
+		(head1)->stqh_last = (head2)->stqh_last;		\
+		STAILQ_INIT((head2));					\
+	}								\
+} while (0)
+
+#define	STAILQ_EMPTY(head)	((head)->stqh_first == NULL)
+
+#define	STAILQ_FIRST(head)	((head)->stqh_first)
+
+#define	STAILQ_FOREACH(var, head, field)				\
+	for((var) = STAILQ_FIRST((head));				\
+	   (var);							\
+	   (var) = STAILQ_NEXT((var), field))
+
+
+#define	STAILQ_FOREACH_SAFE(var, head, field, tvar)			\
+	for ((var) = STAILQ_FIRST((head));				\
+	    (var) && ((tvar) = STAILQ_NEXT((var), field), 1);		\
+	    (var) = (tvar))
+
+#define	STAILQ_INIT(head) do {						\
+	STAILQ_FIRST((head)) = NULL;					\
+	(head)->stqh_last = &STAILQ_FIRST((head));			\
+} while (0)
+
+#define	STAILQ_INSERT_AFTER(head, tqelm, elm, field) do {		\
+	if ((STAILQ_NEXT((elm), field) = STAILQ_NEXT((tqelm), field)) == NULL)\
+		(head)->stqh_last = &STAILQ_NEXT((elm), field);		\
+	STAILQ_NEXT((tqelm), field) = (elm);				\
+} while (0)
+
+#define	STAILQ_INSERT_HEAD(head, elm, field) do {			\
+	if ((STAILQ_NEXT((elm), field) = STAILQ_FIRST((head))) == NULL)	\
+		(head)->stqh_last = &STAILQ_NEXT((elm), field);		\
+	STAILQ_FIRST((head)) = (elm);					\
+} while (0)
+
+#define	STAILQ_INSERT_TAIL(head, elm, field) do {			\
+	STAILQ_NEXT((elm), field) = NULL;				\
+	*(head)->stqh_last = (elm);					\
+	(head)->stqh_last = &STAILQ_NEXT((elm), field);			\
+} while (0)
+
+#define	STAILQ_LAST(head, type, field)					\
+	(STAILQ_EMPTY((head)) ?						\
+		NULL :							\
+	        ((struct type *)(void *)				\
+		((char *)((head)->stqh_last) - __offsetof(struct type, field))))
+
+#define	STAILQ_NEXT(elm, field)	((elm)->field.stqe_next)
+
+#define	STAILQ_REMOVE(head, elm, type, field) do {			\
+	QMD_SAVELINK(oldnext, (elm)->field.stqe_next);			\
+	if (STAILQ_FIRST((head)) == (elm)) {				\
+		STAILQ_REMOVE_HEAD((head), field);			\
+	}								\
+	else {								\
+		struct type *curelm = STAILQ_FIRST((head));		\
+		while (STAILQ_NEXT(curelm, field) != (elm))		\
+			curelm = STAILQ_NEXT(curelm, field);		\
+		STAILQ_REMOVE_AFTER(head, curelm, field);		\
+	}								\
+	TRASHIT(*oldnext);						\
+} while (0)
+
+#define	STAILQ_REMOVE_HEAD(head, field) do {				\
+	if ((STAILQ_FIRST((head)) =					\
+	     STAILQ_NEXT(STAILQ_FIRST((head)), field)) == NULL)		\
+		(head)->stqh_last = &STAILQ_FIRST((head));		\
+} while (0)
+
+#define STAILQ_REMOVE_AFTER(head, elm, field) do {			\
+	if ((STAILQ_NEXT(elm, field) =					\
+	     STAILQ_NEXT(STAILQ_NEXT(elm, field), field)) == NULL)	\
+		(head)->stqh_last = &STAILQ_NEXT((elm), field);		\
+} while (0)
+
+#define STAILQ_SWAP(head1, head2, type) do {				\
+	struct type *swap_first = STAILQ_FIRST(head1);			\
+	struct type **swap_last = (head1)->stqh_last;			\
+	STAILQ_FIRST(head1) = STAILQ_FIRST(head2);			\
+	(head1)->stqh_last = (head2)->stqh_last;			\
+	STAILQ_FIRST(head2) = swap_first;				\
+	(head2)->stqh_last = swap_last;					\
+	if (STAILQ_EMPTY(head1))					\
+		(head1)->stqh_last = &STAILQ_FIRST(head1);		\
+	if (STAILQ_EMPTY(head2))					\
+		(head2)->stqh_last = &STAILQ_FIRST(head2);		\
+} while (0)
+
+#define STAILQ_INSERT_CHAIN_HEAD(head, elm_chead, elm_ctail, field) do {   \
+    if ((STAILQ_NEXT(elm_ctail, field) = STAILQ_FIRST(head)) == NULL ) { \
+        (head)->stqh_last = &STAILQ_NEXT(elm_ctail, field);            \
+    }                                                                      \
+    STAILQ_FIRST(head) = (elm_chead);                                    \
+} while (0)
+
+
+/*
+ * List declarations.
+ */
+#define	LIST_HEAD(name, type)						\
+struct name {								\
+	struct type *lh_first;	/* first element */			\
+}
+
+#define	LIST_HEAD_INITIALIZER(head)					\
+	{ NULL }
+
+#define	LIST_ENTRY(type)						\
+struct {								\
+	struct type *le_next;	/* next element */			\
+	struct type **le_prev;	/* address of previous next element */	\
+}
+
+/*
+ * List functions.
+ */
+
+#if (defined(_KERNEL) && defined(INVARIANTS))
+#define	QMD_LIST_CHECK_HEAD(head, field) do {				\
+	if (LIST_FIRST((head)) != NULL &&				\
+	    LIST_FIRST((head))->field.le_prev !=			\
+	     &LIST_FIRST((head)))					\
+		panic("Bad list head %p first->prev != head", (head));	\
+} while (0)
+
+#define	QMD_LIST_CHECK_NEXT(elm, field) do {				\
+	if (LIST_NEXT((elm), field) != NULL &&				\
+	    LIST_NEXT((elm), field)->field.le_prev !=			\
+	     &((elm)->field.le_next))					\
+	     	panic("Bad link elm %p next->prev != elm", (elm));	\
+} while (0)
+
+#define	QMD_LIST_CHECK_PREV(elm, field) do {				\
+	if (*(elm)->field.le_prev != (elm))				\
+		panic("Bad link elm %p prev->next != elm", (elm));	\
+} while (0)
+#else
+#define	QMD_LIST_CHECK_HEAD(head, field)
+#define	QMD_LIST_CHECK_NEXT(elm, field)
+#define	QMD_LIST_CHECK_PREV(elm, field)
+#endif /* (_KERNEL && INVARIANTS) */
+
+#define	LIST_EMPTY(head)	((head)->lh_first == NULL)
+
+#define	LIST_FIRST(head)	((head)->lh_first)
+
+#define	LIST_FOREACH(var, head, field)					\
+	for ((var) = LIST_FIRST((head));				\
+	    (var);							\
+	    (var) = LIST_NEXT((var), field))
+
+#define	LIST_FOREACH_SAFE(var, head, field, tvar)			\
+	for ((var) = LIST_FIRST((head));				\
+	    (var) && ((tvar) = LIST_NEXT((var), field), 1);		\
+	    (var) = (tvar))
+
+#define	LIST_INIT(head) do {						\
+	LIST_FIRST((head)) = NULL;					\
+} while (0)
+
+#define	LIST_INSERT_AFTER(listelm, elm, field) do {			\
+	QMD_LIST_CHECK_NEXT(listelm, field);				\
+	if ((LIST_NEXT((elm), field) = LIST_NEXT((listelm), field)) != NULL)\
+		LIST_NEXT((listelm), field)->field.le_prev =		\
+		    &LIST_NEXT((elm), field);				\
+	LIST_NEXT((listelm), field) = (elm);				\
+	(elm)->field.le_prev = &LIST_NEXT((listelm), field);		\
+} while (0)
+
+#define	LIST_INSERT_BEFORE(listelm, elm, field) do {			\
+	QMD_LIST_CHECK_PREV(listelm, field);				\
+	(elm)->field.le_prev = (listelm)->field.le_prev;		\
+	LIST_NEXT((elm), field) = (listelm);				\
+	*(listelm)->field.le_prev = (elm);				\
+	(listelm)->field.le_prev = &LIST_NEXT((elm), field);		\
+} while (0)
+
+#define	LIST_INSERT_HEAD(head, elm, field) do {				\
+	QMD_LIST_CHECK_HEAD((head), field);				\
+	if ((LIST_NEXT((elm), field) = LIST_FIRST((head))) != NULL)	\
+		LIST_FIRST((head))->field.le_prev = &LIST_NEXT((elm), field);\
+	LIST_FIRST((head)) = (elm);					\
+	(elm)->field.le_prev = &LIST_FIRST((head));			\
+} while (0)
+
+#define	LIST_NEXT(elm, field)	((elm)->field.le_next)
+
+#define	LIST_REMOVE(elm, field) do {					\
+	QMD_SAVELINK(oldnext, (elm)->field.le_next);			\
+	QMD_SAVELINK(oldprev, (elm)->field.le_prev);			\
+	QMD_LIST_CHECK_NEXT(elm, field);				\
+	QMD_LIST_CHECK_PREV(elm, field);				\
+	if (LIST_NEXT((elm), field) != NULL)				\
+		LIST_NEXT((elm), field)->field.le_prev = 		\
+		    (elm)->field.le_prev;				\
+	*(elm)->field.le_prev = LIST_NEXT((elm), field);		\
+	TRASHIT(*oldnext);						\
+	TRASHIT(*oldprev);						\
+} while (0)
+
+#define LIST_SWAP(head1, head2, type, field) do {			\
+	struct type *swap_tmp = LIST_FIRST((head1));			\
+	LIST_FIRST((head1)) = LIST_FIRST((head2));			\
+	LIST_FIRST((head2)) = swap_tmp;					\
+	if ((swap_tmp = LIST_FIRST((head1))) != NULL)			\
+		swap_tmp->field.le_prev = &LIST_FIRST((head1));		\
+	if ((swap_tmp = LIST_FIRST((head2))) != NULL)			\
+		swap_tmp->field.le_prev = &LIST_FIRST((head2));		\
+} while (0)
+
+/*
+ * Tail queue declarations.
+ */
+#define	TAILQ_HEAD(name, type)						\
+struct name {								\
+	struct type *tqh_first;	/* first element */			\
+	struct type **tqh_last;	/* addr of last next element */		\
+	TRACEBUF							\
+}
+
+#define	TAILQ_HEAD_INITIALIZER(head)					\
+	{ NULL, &(head).tqh_first }
+
+#define	TAILQ_ENTRY(type)						\
+struct {								\
+	struct type *tqe_next;	/* next element */			\
+	struct type **tqe_prev;	/* address of previous next element */	\
+	TRACEBUF							\
+}
+
+/*
+ * Tail queue functions.
+ */
+#if (defined(_KERNEL) && defined(INVARIANTS))
+#define	QMD_TAILQ_CHECK_HEAD(head, field) do {				\
+	if (!TAILQ_EMPTY(head) &&					\
+	    TAILQ_FIRST((head))->field.tqe_prev !=			\
+	     &TAILQ_FIRST((head)))					\
+		panic("Bad tailq head %p first->prev != head", (head));	\
+} while (0)
+
+#define	QMD_TAILQ_CHECK_TAIL(head, field) do {				\
+	if (*(head)->tqh_last != NULL)					\
+	    	panic("Bad tailq NEXT(%p->tqh_last) != NULL", (head)); 	\
+} while (0)
+
+#define	QMD_TAILQ_CHECK_NEXT(elm, field) do {				\
+	if (TAILQ_NEXT((elm), field) != NULL &&				\
+	    TAILQ_NEXT((elm), field)->field.tqe_prev !=			\
+	     &((elm)->field.tqe_next))					\
+		panic("Bad link elm %p next->prev != elm", (elm));	\
+} while (0)
+
+#define	QMD_TAILQ_CHECK_PREV(elm, field) do {				\
+	if (*(elm)->field.tqe_prev != (elm))				\
+		panic("Bad link elm %p prev->next != elm", (elm));	\
+} while (0)
+#else
+#define	QMD_TAILQ_CHECK_HEAD(head, field)
+#define	QMD_TAILQ_CHECK_TAIL(head, headname)
+#define	QMD_TAILQ_CHECK_NEXT(elm, field)
+#define	QMD_TAILQ_CHECK_PREV(elm, field)
+#endif /* (_KERNEL && INVARIANTS) */
+
+#define	TAILQ_CONCAT(head1, head2, field) do {				\
+	if (!TAILQ_EMPTY(head2)) {					\
+		*(head1)->tqh_last = (head2)->tqh_first;		\
+		(head2)->tqh_first->field.tqe_prev = (head1)->tqh_last;	\
+		(head1)->tqh_last = (head2)->tqh_last;			\
+		TAILQ_INIT((head2));					\
+		QMD_TRACE_HEAD(head1);					\
+		QMD_TRACE_HEAD(head2);					\
+	}								\
+} while (0)
+
+#define	TAILQ_EMPTY(head)	((head)->tqh_first == NULL)
+
+#define	TAILQ_FIRST(head)	((head)->tqh_first)
+
+#define	TAILQ_FOREACH(var, head, field)					\
+	for ((var) = TAILQ_FIRST((head));				\
+	    (var);							\
+	    (var) = TAILQ_NEXT((var), field))
+
+#define	TAILQ_FOREACH_SAFE(var, head, field, tvar)			\
+	for ((var) = TAILQ_FIRST((head));				\
+	    (var) && ((tvar) = TAILQ_NEXT((var), field), 1);		\
+	    (var) = (tvar))
+
+#define	TAILQ_FOREACH_REVERSE(var, head, headname, field)		\
+	for ((var) = TAILQ_LAST((head), headname);			\
+	    (var);							\
+	    (var) = TAILQ_PREV((var), headname, field))
+
+#define	TAILQ_FOREACH_REVERSE_SAFE(var, head, headname, field, tvar)	\
+	for ((var) = TAILQ_LAST((head), headname);			\
+	    (var) && ((tvar) = TAILQ_PREV((var), headname, field), 1);	\
+	    (var) = (tvar))
+
+#define	TAILQ_INIT(head) do {						\
+	TAILQ_FIRST((head)) = NULL;					\
+	(head)->tqh_last = &TAILQ_FIRST((head));			\
+	QMD_TRACE_HEAD(head);						\
+} while (0)
+
+#define	TAILQ_INSERT_AFTER(head, listelm, elm, field) do {		\
+	QMD_TAILQ_CHECK_NEXT(listelm, field);				\
+	if ((TAILQ_NEXT((elm), field) = TAILQ_NEXT((listelm), field)) != NULL)\
+		TAILQ_NEXT((elm), field)->field.tqe_prev = 		\
+		    &TAILQ_NEXT((elm), field);				\
+	else {								\
+		(head)->tqh_last = &TAILQ_NEXT((elm), field);		\
+		QMD_TRACE_HEAD(head);					\
+	}								\
+	TAILQ_NEXT((listelm), field) = (elm);				\
+	(elm)->field.tqe_prev = &TAILQ_NEXT((listelm), field);		\
+	QMD_TRACE_ELEM(&(elm)->field);					\
+	QMD_TRACE_ELEM(&listelm->field);				\
+} while (0)
+
+#define	TAILQ_INSERT_BEFORE(listelm, elm, field) do {			\
+	QMD_TAILQ_CHECK_PREV(listelm, field);				\
+	(elm)->field.tqe_prev = (listelm)->field.tqe_prev;		\
+	TAILQ_NEXT((elm), field) = (listelm);				\
+	*(listelm)->field.tqe_prev = (elm);				\
+	(listelm)->field.tqe_prev = &TAILQ_NEXT((elm), field);		\
+	QMD_TRACE_ELEM(&(elm)->field);					\
+	QMD_TRACE_ELEM(&listelm->field);				\
+} while (0)
+
+#define	TAILQ_INSERT_HEAD(head, elm, field) do {			\
+	QMD_TAILQ_CHECK_HEAD(head, field);				\
+	if ((TAILQ_NEXT((elm), field) = TAILQ_FIRST((head))) != NULL)	\
+		TAILQ_FIRST((head))->field.tqe_prev =			\
+		    &TAILQ_NEXT((elm), field);				\
+	else								\
+		(head)->tqh_last = &TAILQ_NEXT((elm), field);		\
+	TAILQ_FIRST((head)) = (elm);					\
+	(elm)->field.tqe_prev = &TAILQ_FIRST((head));			\
+	QMD_TRACE_HEAD(head);						\
+	QMD_TRACE_ELEM(&(elm)->field);					\
+} while (0)
+
+#define	TAILQ_INSERT_TAIL(head, elm, field) do {			\
+	QMD_TAILQ_CHECK_TAIL(head, field);				\
+	TAILQ_NEXT((elm), field) = NULL;				\
+	(elm)->field.tqe_prev = (head)->tqh_last;			\
+	*(head)->tqh_last = (elm);					\
+	(head)->tqh_last = &TAILQ_NEXT((elm), field);			\
+	QMD_TRACE_HEAD(head);						\
+	QMD_TRACE_ELEM(&(elm)->field);					\
+} while (0)
+
+#define	TAILQ_LAST(head, headname)					\
+	(*(((struct headname *)((head)->tqh_last))->tqh_last))
+
+#define	TAILQ_NEXT(elm, field) ((elm)->field.tqe_next)
+
+#define	TAILQ_PREV(elm, headname, field)				\
+	(*(((struct headname *)((elm)->field.tqe_prev))->tqh_last))
+
+#define	TAILQ_REMOVE(head, elm, field) do {				\
+	QMD_SAVELINK(oldnext, (elm)->field.tqe_next);			\
+	QMD_SAVELINK(oldprev, (elm)->field.tqe_prev);			\
+	QMD_TAILQ_CHECK_NEXT(elm, field);				\
+	QMD_TAILQ_CHECK_PREV(elm, field);				\
+	if ((TAILQ_NEXT((elm), field)) != NULL)				\
+		TAILQ_NEXT((elm), field)->field.tqe_prev = 		\
+		    (elm)->field.tqe_prev;				\
+	else {								\
+		(head)->tqh_last = (elm)->field.tqe_prev;		\
+		QMD_TRACE_HEAD(head);					\
+	}								\
+	*(elm)->field.tqe_prev = TAILQ_NEXT((elm), field);		\
+	TRASHIT(*oldnext);						\
+	TRASHIT(*oldprev);						\
+	QMD_TRACE_ELEM(&(elm)->field);					\
+} while (0)
+
+#define TAILQ_SWAP(head1, head2, type, field) do {			\
+	struct type *swap_first = (head1)->tqh_first;			\
+	struct type **swap_last = (head1)->tqh_last;			\
+	(head1)->tqh_first = (head2)->tqh_first;			\
+	(head1)->tqh_last = (head2)->tqh_last;				\
+	(head2)->tqh_first = swap_first;				\
+	(head2)->tqh_last = swap_last;					\
+	if ((swap_first = (head1)->tqh_first) != NULL)			\
+		swap_first->field.tqe_prev = &(head1)->tqh_first;	\
+	else								\
+		(head1)->tqh_last = &(head1)->tqh_first;		\
+	if ((swap_first = (head2)->tqh_first) != NULL)			\
+		swap_first->field.tqe_prev = &(head2)->tqh_first;	\
+	else								\
+		(head2)->tqh_last = &(head2)->tqh_first;		\
+} while (0)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* !_SYS_QUEUE_H_ */

components/esp32/include/rom/rtc.h

@@ -0,0 +1,168 @@
+// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef _ROM_RTC_H_
+#define _ROM_RTC_H_
+
+#include "ets_sys.h"
+
+#include <stdbool.h>
+#include <stdint.h>
+
+#include "soc/soc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    AWAKE = 0,              //CPU ON
+    LIGHT_SLEEP = BIT0,    //CPU waiti, PLL ON.  We don't need explicitly set this mode.
+    DEEP_SLEEP  = BIT1     //CPU OFF, PLL OFF, only specific timer could wake up
+} SLEEP_MODE;
+
+typedef enum {
+    NO_MEAN                =  0,
+    POWERON_RESET          =  1,    //1  Vbat power on reset, RTC reset
+//    EXT_SYS_RESET        =  2,    //4  External System reset, RTC reset
+    SW_RESET               =  3,    //6  Software warm reset
+    OWDT_RESET             =  4,    //5  Watch dog reset
+    DEEPSLEEP_RESET        =  5,    //2  Deep sleep timer reach reset.
+    SDIO_RESET             =  6,    //3  Deep sleep Pbint power on reset [boot]
+    TG0WDT_SYS_RESET       =  7,
+    TG1WDT_SYS_RESET       =  8,
+    RTCWDT_SYS_RESET       =  9,
+    INTRUSION_RESET        = 10,
+    TGWDT_CPU_RESET        = 11,
+    SW_CPU_RESET           = 12,
+    RTCWDT_CPU_RESET       = 13,
+    EXT_CPU_RESET          = 14,
+    RTCWDT_BROWN_OUT_RESET = 15,
+    RTCWDT_RTC_RESET = 16
+} RESET_REASON;
+
+typedef enum {
+    NO_SLEEP        = 0,
+    EXT_EVENT0_TRIG = BIT0,
+    EXT_EVENT1_TRIG = BIT1,
+    GPIO_TRIG       = BIT2,
+    TIMER_EXPIRE    = BIT3,
+    SDIO_TRIG       = BIT4,
+    MAC_TRIG        = BIT5,
+    UART0_TRIG      = BIT6,
+    UART1_TRIG      = BIT7,
+    TOUCH_TRIG      = BIT8,
+    SAR_TRIG        = BIT9,
+    BT_TRIG         = BIT10
+} WAKEUP_REASON;
+
+typedef enum {
+    DISEN_WAKEUP       = NO_SLEEP,
+    EXT_EVENT0_TRIG_EN = EXT_EVENT0_TRIG,
+    EXT_EVENT1_TRIG_EN = EXT_EVENT1_TRIG,
+    GPIO_TRIG_EN       = GPIO_TRIG,
+    TIMER_EXPIRE_EN    = TIMER_EXPIRE,
+    SDIO_TRIG_EN       = SDIO_TRIG,
+    MAC_TRIG_EN        = MAC_TRIG,
+    UART0_TRIG_EN      = UART0_TRIG,
+    UART1_TRIG_EN      = UART1_TRIG,
+    TOUCH_TRIG_EN      = TOUCH_TRIG,
+    SAR_TRIG_EN        = SAR_TRIG,
+    BT_TRIG_EN         = BT_TRIG
+} WAKEUP_ENABLE;
+
+typedef enum {
+    NO_INT             = 0,
+    WAKEUP_INT         = BIT0,
+    REJECT_INT         = BIT1,
+    SDIO_IDLE_INT      = BIT2,
+    RTC_WDT_INT        = BIT3,
+    RTC_TIME_VALID_INT = BIT4
+} RTC_INT_REASON;
+
+typedef enum {
+    DISEN_INT             = 0,
+    WAKEUP_INT_EN         = WAKEUP_INT,
+    REJECT_INT_EN         = REJECT_INT,
+    SDIO_IDLE_INT_EN      = SDIO_IDLE_INT,
+    RTC_WDT_INT_EN        = RTC_WDT_INT,
+    RTC_TIME_VALID_INT_EN = RTC_TIME_VALID_INT
+}RTC_INT_EN;
+
+
+
+// Alive memory is a special memory block which could restore data during system
+// deep sleep.  power management and wlan profile data may need put into this
+// memory area.
+// Should create a dram segment in link script.
+#define ALIVE_MEMORY_ADDR
+#define ALIVE_MEMORY_SIZE       (1024 * 2)
+
+void rtc_hw_init(void);
+
+RESET_REASON rtc_get_reset_reason(int cpu_no);
+void software_reset(void);
+void software_reset_cpu(int cpu_no);
+void rtc_select_apb_bridge(bool sel);
+void rtc_set_sleep_mode(SLEEP_MODE mode, uint32_t sleep_sec, uint32_t wakeup_mode);
+
+uint8_t ets_rtc_recovery(void);
+
+#define MAX_DEEPSLEEP_DURATION      (0xffffffff / RTC_CLK_FREQ)  
+#define SECOND_TO_RTC_TICK(second) ((second)*RTC_CLK_FREQ)  //32KHz
+#define CALIB_VALUE_TO_RTC_TICK(microsecond, clk_mkz, n_rtc,nclk) ((microsecond)*(clk_mkz)*(n_rtc)/(nclk))  //32KHz
+#define RTC_TICK_TO_SECOND(tick) ((tick)/RTC_CLK_FREQ )
+#define GET_CURRENT_TICK() (READ_PERI_REG(RTC_TIME))
+#define SET_WAKEUP_TICK(tick) (WRITE_PERI_REG(RTC_TIMER0, tick))
+
+//#define GET_WAKEUP_CAUSE()              GET_PERI_REG_BITS2(RTC_STATE1, RTC_CNTL_WAKEUP_CAUSE, RTC_CNTL_WAKEUP_CAUSE_S)
+#define DISABLE_RTC_INT(int_type)       CLEAR_PERI_REG_MASK(RTC_INT_ENA, int_type)
+#define ENABLE_RTC_INT(int_type)        SET_PERI_REG_MASK(RTC_INT_ENA, int_type)
+#define CLR_RTC_INT(int_type)           SET_PERI_REG_MASK(RTC_INT_CLR, int_type)
+#define GET_RTC_INT_CAUSE()             GET_PERI_REG_BITS(RTC_INT_RAW, RTC_INT_RAW_MSB,RTC_INT_RAW_LSB)
+
+void rtc_register_deepsleep_timer(ETSTimer *timer, uint32_t tmout);
+void rtc_disable_deepsleep_timer(void);
+
+void rtc_enter_sleep(void);
+void ets_rtc_int_register(void);
+void dtm_set_intr_mask(uint32_t mask);
+uint32_t dtm_get_intr_mask(void);
+void dtm_set_params(uint32_t sleep_mode, uint32_t sleep_tm_ms, uint32_t wakeup_tm_ms, uint32_t sleep_times, uint32_t rxbcn_len);
+void save_rxbcn_mactime(uint32_t rxbcn_mactime);
+void save_tsf_us(uint32_t tsf_us);
+
+typedef void (* ets_idle_cb_t)(void *arg);
+
+typedef uint32_t (* ETS_GET_MACTIME)(void);
+typedef void   (* ETS_WAKEUP_INIT)(void);
+
+void dtm_params_init(ETS_GET_MACTIME get_mactime, ETS_WAKEUP_INIT wakeup_init);
+
+void ets_set_idle_cb(ets_idle_cb_t func, void *arg);
+
+void ets_enter_sleep(void);
+
+void rtc_intr_handler(void *);
+ 
+#define ETS_SLEEP_START(pfunc, parg) ets_set_idle_cb((pfunc), (parg));
+
+#define ETS_SLEEP_END() ets_set_idle_cb(NULL, NULL);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _ROM_RTC_H_ */
+

components/esp32/include/rom/secure_boot.h

@@ -0,0 +1,41 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _ROM_SECURE_BOOT_H_
+#define _ROM_SECURE_BOOT_H_
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void ets_secure_boot_start(void);
+
+void ets_secure_boot_finish(void);
+
+void ets_secure_boot_hash(uint32_t *buf);
+
+void ets_secure_boot_obtain(void);
+
+int ets_secure_boot_check(uint32_t *buf);
+
+void ets_secure_boot_rd_iv(uint32_t *buf);
+
+void ets_secure_boot_rd_abstract(uint32_t *buf);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _ROM_SECURE_BOOT_H_ */

components/esp32/include/rom/sha.h

@@ -0,0 +1,50 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _ROM_SHA_H_
+#define _ROM_SHA_H_
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct SHAContext {
+    bool start;
+    uint32_t total_input_bits[4];
+} SHA_CTX;
+
+enum SHA_TYPE {
+    SHA1 = 0,
+    SHA2_256,
+    SHA2_384,
+    SHA2_512
+};
+
+void ets_sha_init(SHA_CTX *ctx);
+
+void ets_sha_enable(void);
+
+void ets_sha_disable(void);
+
+void ets_sha_update(SHA_CTX *ctx, enum SHA_TYPE type, const uint8_t *input, size_t input_bits);
+
+void ets_sha_finish(SHA_CTX *ctx, enum SHA_TYPE type, uint8_t *output);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _ROM_SHA_H_ */

components/esp32/include/rom/spi_flash.h

@@ -0,0 +1,145 @@
+// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _ROM_SPI_FLASH_H_
+#define _ROM_SPI_FLASH_H_
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#include "esp_attr.h"
+
+#include "soc/spi_register.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define PERIPHS_SPI_FLASH_CMD               SPI_CMD(1)
+#define PERIPHS_SPI_FLASH_ADDR              SPI_ADDR(1)
+#define PERIPHS_SPI_FLASH_CTRL              SPI_CTRL(1)
+#define PERIPHS_SPI_FLASH_CTRL1             SPI_CTRL1(1)
+#define PERIPHS_SPI_FLASH_STATUS            SPI_RD_STATUS(1)
+#define PERIPHS_SPI_FLASH_USRREG            SPI_USER(1)
+#define PERIPHS_SPI_FLASH_USRREG1           SPI_USER1(1)
+#define PERIPHS_SPI_FLASH_USRREG2           SPI_USER2(1)
+#define PERIPHS_SPI_FLASH_C0                SPI_W0(1)
+#define PERIPHS_SPI_FLASH_C1                SPI_W1(1)
+#define PERIPHS_SPI_FLASH_C2                SPI_W2(1)
+#define PERIPHS_SPI_FLASH_C3                SPI_W3(1)
+#define PERIPHS_SPI_FLASH_C4                SPI_W4(1)
+#define PERIPHS_SPI_FLASH_C5                SPI_W5(1)
+#define PERIPHS_SPI_FLASH_C6                SPI_W6(1)
+#define PERIPHS_SPI_FLASH_C7                SPI_W7(1)
+#define PERIPHS_SPI_FLASH_TX_CRC            SPI_TX_CRC(1)
+
+#define SPI0_R_QIO_DUMMY_CYCLELEN           3
+#define SPI0_R_QIO_ADDR_BITSLEN             31
+#define SPI0_R_FAST_DUMMY_CYCLELEN          7
+#define SPI0_R_DIO_DUMMY_CYCLELEN           3
+#define SPI0_R_FAST_ADDR_BITSLEN            23
+#define SPI0_R_SIO_ADDR_BITSLEN             23
+
+#define SPI1_R_QIO_DUMMY_CYCLELEN           3
+#define SPI1_R_QIO_ADDR_BITSLEN             31
+#define SPI1_R_FAST_DUMMY_CYCLELEN          7
+#define SPI1_R_DIO_DUMMY_CYCLELEN           3
+#define SPI1_R_DIO_ADDR_BITSLEN             31
+#define SPI1_R_FAST_ADDR_BITSLEN            23
+#define SPI1_R_SIO_ADDR_BITSLEN             23
+
+#define SPI_W_SIO_ADDR_BITSLEN              23
+
+#define TWO_BYTE_STATUS_EN                  SPI_WRSR_2B
+
+//SPI address register
+#define SPI_FLASH_BYTES_LEN                 24
+#define SPI_BUFF_BYTE_WRITE_NUM             32
+#define SPI_BUFF_BYTE_READ_NUM              64
+#define SPI_BUFF_BYTE_READ_BITS             0x3f
+
+//SPI status register
+#define  SPI_FLASH_BUSY_FLAG                BIT0
+#define  SPI_FLASH_WRENABLE_FLAG            BIT1
+#define  SPI_FLASH_BP0                      BIT2
+#define  SPI_FLASH_BP1                      BIT3
+#define  SPI_FLASH_BP2                      BIT4
+#define  FLASH_WR_PROTECT                   (SPI_FLASH_BP0|SPI_FLASH_BP1|SPI_FLASH_BP2)
+#define  SPI_FLASH_QE                       BIT9
+
+typedef enum {
+    SPI_FLASH_QIO_MODE = 0,
+    SPI_FLASH_QOUT_MODE,
+    SPI_FLASH_DIO_MODE,
+    SPI_FLASH_DOUT_MODE,
+    SPI_FLASH_FASTRD_MODE,
+    SPI_FLASH_SLOWRD_MODE
+} SpiFlashRdMode;
+
+typedef enum {
+    SPI_FLASH_RESULT_OK,
+    SPI_FLASH_RESULT_ERR,
+    SPI_FLASH_RESULT_TIMEOUT
+} SpiFlashOpResult;
+
+typedef struct{
+    uint32_t deviceId;
+    uint32_t chip_size;    // chip size in bytes
+    uint32_t block_size;
+    uint32_t sector_size;
+    uint32_t page_size;
+    uint32_t status_mask;
+} SpiFlashChip;
+
+typedef struct {
+    uint8_t  data_length;
+    uint8_t  read_cmd0;
+    uint8_t  read_cmd1;
+    uint8_t  write_cmd;
+    uint16_t data_mask;
+    uint16_t data;
+} SpiCommonCmd;
+
+void SelectSpiQIO(uint8_t wp_gpio_num, uint32_t ishspi) ROMFN_ATTR;
+void SetSpiDrvs(uint8_t wp_gpio_num, uint32_t ishspi, uint8_t* drvs) ROMFN_ATTR;
+void SelectSpiFunction(uint32_t ishspi) ROMFN_ATTR;
+SpiFlashOpResult SPIEraseChip(void) ROMFN_ATTR;
+SpiFlashOpResult SPIEraseBlock(uint32_t block_num) ROMFN_ATTR;
+SpiFlashOpResult SPIEraseSector(uint32_t sector_num) ROMFN_ATTR;
+SpiFlashOpResult SPIWrite(uint32_t dest_addr, const uint32_t* src, int32_t len) ROMFN_ATTR;
+void SPI_Write_Encrypt_Enable() ROMFN_ATTR;
+SpiFlashOpResult SPI_Prepare_Encrypt_Data(uint32_t flash_addr, uint32_t* data) ROMFN_ATTR;
+void SPI_Write_Encrypt_Disable() ROMFN_ATTR;
+SpiFlashOpResult SPI_Encrypt_Write(uint32_t flash_addr, uint32_t* data, uint32_t len) ROMFN_ATTR;
+SpiFlashOpResult SPIRead(uint32_t src_addr, uint32_t* dest, int32_t len) ROMFN_ATTR;
+SpiFlashOpResult SPIReadModeCnfig(SpiFlashRdMode mode, bool legacy) ROMFN_ATTR;
+SpiFlashOpResult SPIMasterReadModeCnfig(SpiFlashRdMode mode) ROMFN_ATTR;
+SpiFlashOpResult SPIClkConfig(uint8_t freqdiv, uint8_t spi) ROMFN_ATTR;
+uint16_t SPI_Common_Command(SpiCommonCmd * cmd) ROMFN_ATTR;
+SpiFlashOpResult SPIUnlock() ROMFN_ATTR;
+SpiFlashOpResult SPIEraseArea(uint32_t start_addr, uint32_t area_len) ROMFN_ATTR;
+SpiFlashOpResult SPILock() ROMFN_ATTR;
+SpiFlashOpResult SPIParamCfg(uint32_t deviceId, uint32_t chip_size, uint32_t block_size, uint32_t sector_size, uint32_t page_size, uint32_t status_mask) ROMFN_ATTR;
+SpiFlashOpResult SPI_user_command_read(uint32_t * status, uint8_t cmd) ROMFN_ATTR;
+void spi_cache_sram_init() ROMFN_ATTR;
+
+//ETS_STATUS ets_unpack_flash_code(uint32_t pos, uint32_t *entry_addr, bool jump, bool sb_need_check, bool config) ROMFN_ATTR;
+//ETS_STATUS ets_unpack_flash_code_legacy(uint32_t pos, uint32_t *entry_addr, bool jump, bool config) ROMFN_ATTR;
+
+void spi_flash_attach(uint32_t ishspi, bool legacy) ROMFN_ATTR;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _ROM_SPI_FLASH_H_ */

components/esp32/include/rom/ssc.h

@@ -0,0 +1,85 @@
+// Copyright 2011-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef _ROM_SSC_H_
+#define _ROM_SSC_H_
+
+#include "esp_types.h"
+
+#include "esp_attr.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct cmd_s {
+    char *cmd_str;
+#define CMD_T_ASYNC   0x01
+#define CMD_T_SYNC    0x02
+    uint8_t flag;
+    uint8_t id;
+    void    (* cmd_func)(void);
+    void    (* cmd_callback)(void *arg);
+} ssc_cmd_t;
+
+#define ssc_printf ets_printf
+#define SSC_CMD_N  10   //since the command not added in ssc_cmd.c
+#define MAX_LINE_N  40
+#define PROMPT  ":>"
+#define SSC_EVT_N   4
+
+
+#define SSC_PRIO   30
+enum {
+    CMD_SET_SSID = 0,
+    CMD_SCAN,
+    CMD_CONNECT,
+    CMD_DISCONNECT,
+    CMD_SET_MACADDR,
+    CMD_PING,
+    CMD_PING_COUNT,
+    CMD_PING_LENGTH,
+    CMD_SET_IP,
+//    CMD_RD_I2C, 
+//    CMD_SET_NULL, it's just for solving the old rom bug 
+//    CMD_SET_I2C,
+//    CMD_RD_I2CM,
+//    CMD_SET_I2CM,
+//    CMD_SET_PBUS,
+//    CMD_SET_TXTONE,
+//    CMD_SET_STOPTONE,
+    CMD_END,
+};
+
+enum {
+    SIG_SSC_RUNCMD,
+    SIG_SSC_CMDDONE,
+    SIG_SSC_RESTART,
+    SIG_SSC_UART_RX_CHAR,
+};
+
+void ssc_attach(void) ROMFN_ATTR;
+void ssc_cmd_done(int cmd_id, STATUS status) ROMFN_ATTR;
+int ssc_param_len(void) ROMFN_ATTR;
+char * ssc_param_str(void) ROMFN_ATTR;
+void ssc_register(ssc_cmd_t *cmdset, uint8_t cmdnum, void (* help)(void)) ROMFN_ATTR;
+
+extern ssc_cmd_t sscCmdSet[];
+void ssc_help(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _ROM_SSC_H_ */

components/esp32/include/rom/tbconsole.h

@@ -0,0 +1,27 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _ROM_TBCONSOLE_H_
+#define _ROM_TBCONSOLE_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void start_tb_console();
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _ROM_TBCONSOLE_H_ */

components/esp32/include/rom/tjpgd.h

@@ -0,0 +1,99 @@
+/*----------------------------------------------------------------------------/
+/ TJpgDec - Tiny JPEG Decompressor include file               (C)ChaN, 2012
+/----------------------------------------------------------------------------*/
+#ifndef _TJPGDEC
+#define _TJPGDEC
+/*---------------------------------------------------------------------------*/
+/* System Configurations */
+
+#define	JD_SZBUF		512	/* Size of stream input buffer */
+#define JD_FORMAT		0	/* Output pixel format 0:RGB888 (3 BYTE/pix), 1:RGB565 (1 WORD/pix) */
+#define	JD_USE_SCALE	1	/* Use descaling feature for output */
+#define JD_TBLCLIP		1	/* Use table for saturation (might be a bit faster but increases 1K bytes of code size) */
+
+/*---------------------------------------------------------------------------*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* These types must be 16-bit, 32-bit or larger integer */
+typedef int				INT;
+typedef unsigned int	UINT;
+
+/* These types must be 8-bit integer */
+typedef char			CHAR;
+typedef unsigned char	UCHAR;
+typedef unsigned char	BYTE;
+
+/* These types must be 16-bit integer */
+typedef short			SHORT;
+typedef unsigned short	USHORT;
+typedef unsigned short	WORD;
+typedef unsigned short	WCHAR;
+
+/* These types must be 32-bit integer */
+typedef long			LONG;
+typedef unsigned long	ULONG;
+typedef unsigned long	DWORD;
+
+
+/* Error code */
+typedef enum {
+	JDR_OK = 0,	/* 0: Succeeded */
+	JDR_INTR,	/* 1: Interrupted by output function */	
+	JDR_INP,	/* 2: Device error or wrong termination of input stream */
+	JDR_MEM1,	/* 3: Insufficient memory pool for the image */
+	JDR_MEM2,	/* 4: Insufficient stream input buffer */
+	JDR_PAR,	/* 5: Parameter error */
+	JDR_FMT1,	/* 6: Data format error (may be damaged data) */
+	JDR_FMT2,	/* 7: Right format but not supported */
+	JDR_FMT3	/* 8: Not supported JPEG standard */
+} JRESULT;
+
+
+
+/* Rectangular structure */
+typedef struct {
+	WORD left, right, top, bottom;
+} JRECT;
+
+
+
+/* Decompressor object structure */
+typedef struct JDEC JDEC;
+struct JDEC {
+	UINT dctr;				/* Number of bytes available in the input buffer */
+	BYTE* dptr;				/* Current data read ptr */
+	BYTE* inbuf;			/* Bit stream input buffer */
+	BYTE dmsk;				/* Current bit in the current read byte */
+	BYTE scale;				/* Output scaling ratio */
+	BYTE msx, msy;			/* MCU size in unit of block (width, height) */
+	BYTE qtid[3];			/* Quantization table ID of each component */
+	SHORT dcv[3];			/* Previous DC element of each component */
+	WORD nrst;				/* Restart inverval */
+	UINT width, height;		/* Size of the input image (pixel) */
+	BYTE* huffbits[2][2];	/* Huffman bit distribution tables [id][dcac] */
+	WORD* huffcode[2][2];	/* Huffman code word tables [id][dcac] */
+	BYTE* huffdata[2][2];	/* Huffman decoded data tables [id][dcac] */
+	LONG* qttbl[4];			/* Dequaitizer tables [id] */
+	void* workbuf;			/* Working buffer for IDCT and RGB output */
+	BYTE* mcubuf;			/* Working buffer for the MCU */
+	void* pool;				/* Pointer to available memory pool */
+	UINT sz_pool;			/* Size of momory pool (bytes available) */
+	UINT (*infunc)(JDEC*, BYTE*, UINT);/* Pointer to jpeg stream input function */
+	void* device;			/* Pointer to I/O device identifiler for the session */
+};
+
+
+
+/* TJpgDec API functions */
+JRESULT jd_prepare (JDEC*, UINT(*)(JDEC*,BYTE*,UINT), void*, UINT, void*);
+JRESULT jd_decomp (JDEC*, UINT(*)(JDEC*,void*,JRECT*), BYTE);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _TJPGDEC */

components/esp32/include/rom/uart.h

@@ -0,0 +1,187 @@
+// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef _ROM_UART_H_
+#define _ROM_UART_H_
+
+#include "esp_types.h"
+#include "esp_attr.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define RX_BUFF_SIZE                     0x100
+#define TX_BUFF_SIZE                     100
+
+//uart int enalbe register ctrl bits
+#define UART_RCV_INTEN                   BIT0
+#define UART_TRX_INTEN                   BIT1
+#define UART_LINE_STATUS_INTEN           BIT2
+
+//uart int identification ctrl bits
+#define UART_INT_FLAG_MASK               0x0E
+
+//uart fifo ctrl bits
+#define UART_CLR_RCV_FIFO                BIT1
+#define UART_CLR_TRX_FIFO                BIT2
+#define UART_RCVFIFO_TRG_LVL_BITS        BIT6
+
+//uart line control bits
+#define  UART_DIV_LATCH_ACCESS_BIT       BIT7
+
+//uart line status bits
+#define  UART_RCV_DATA_RDY_FLAG          BIT0
+#define  UART_RCV_OVER_FLOW_FLAG         BIT1
+#define  UART_RCV_PARITY_ERR_FLAG        BIT2
+#define  UART_RCV_FRAME_ERR_FLAG         BIT3
+#define  UART_BRK_INT_FLAG               BIT4
+#define  UART_TRX_FIFO_EMPTY_FLAG        BIT5
+#define  UART_TRX_ALL_EMPTY_FLAG         BIT6   // include fifo and shift reg
+#define  UART_RCV_ERR_FLAG               BIT7
+
+//send and receive message frame head
+#define FRAME_FLAG                         0x7E
+
+typedef enum{
+    UART_LINE_STATUS_INT_FLAG  = 0x06,
+    UART_RCV_FIFO_INT_FLAG     = 0x04,
+    UART_RCV_TMOUT_INT_FLAG    = 0x0C,
+    UART_TXBUFF_EMPTY_INT_FLAG = 0x02
+} UartIntType;   //consider bit0 for int_flag
+
+typedef enum {
+    RCV_ONE_BYTE      = 0x0,
+    RCV_FOUR_BYTE     = 0x1,
+    RCV_EIGHT_BYTE    = 0x2,
+    RCV_FOURTEEN_BYTE = 0x3
+} UartRcvFifoTrgLvl;
+
+typedef enum {
+    FIVE_BITS  = 0x0,
+    SIX_BITS   = 0x1,
+    SEVEN_BITS = 0x2,
+    EIGHT_BITS = 0x3
+} UartBitsNum4Char;
+
+typedef enum {
+    ONE_STOP_BIT      = 1,
+    ONE_HALF_STOP_BIT = 2,
+    TWO_STOP_BIT      = 3
+} UartStopBitsNum;
+
+typedef enum {
+     NONE_BITS = 0,
+     ODD_BITS  = 2,
+     EVEN_BITS = 3
+
+} UartParityMode;
+
+typedef enum {
+    STICK_PARITY_DIS = 0,
+    STICK_PARITY_EN  = 2
+} UartExistParity;
+
+typedef enum {
+    BIT_RATE_9600   = 9600,
+    BIT_RATE_19200  = 19200,
+    BIT_RATE_38400  = 38400,
+    BIT_RATE_57600  = 57600,
+    BIT_RATE_115200 = 115200,
+    BIT_RATE_230400 = 230400,
+    BIT_RATE_460800 = 460800,
+    BIT_RATE_921600 = 921600
+} UartBautRate;
+
+typedef enum {
+    NONE_CTRL,
+    HARDWARE_CTRL,
+    XON_XOFF_CTRL
+} UartFlowCtrl;
+
+typedef enum {
+    EMPTY,
+    UNDER_WRITE,
+    WRITE_OVER 
+} RcvMsgBuffState;
+
+typedef struct {
+//    uint32_t     RcvBuffSize;
+    uint8_t *pRcvMsgBuff;
+    uint8_t *pWritePos;
+    uint8_t *pReadPos;
+    uint8_t  TrigLvl; //JLU: may need to pad
+    RcvMsgBuffState BuffState;
+}RcvMsgBuff;
+
+typedef struct {
+    uint32_t  TrxBuffSize;
+    uint8_t  *pTrxBuff;
+} TrxMsgBuff;
+
+typedef enum {
+    BAUD_RATE_DET,
+    WAIT_SYNC_FRM,
+    SRCH_MSG_HEAD,
+    RCV_MSG_BODY,
+    RCV_ESC_CHAR,
+} RcvMsgState;
+
+typedef struct{
+    UartBautRate     baut_rate;
+    UartBitsNum4Char data_bits;
+    UartExistParity  exist_parity;
+    UartParityMode   parity;    // chip size in byte
+    UartStopBitsNum  stop_bits;
+    UartFlowCtrl     flow_ctrl;
+    uint8_t          buff_uart_no;  //indicate which uart use tx/rx buffer
+    uint8_t          tx_uart_no;
+    RcvMsgBuff       rcv_buff;
+//    TrxMsgBuff       trx_buff;
+    RcvMsgState      rcv_state;
+    int              received;
+} UartDevice;
+
+void Uart_Init(uint8_t uart_no, uint32_t clock) ROMFN_ATTR;
+STATUS UartTxString(uint8_t* pString) ROMFN_ATTR;
+STATUS UartRxString(uint8_t* pString, uint8_t MaxStrlen) ROMFN_ATTR;
+
+STATUS uart_tx_one_char(uint8_t TxChar) ROMFN_ATTR;//for print
+STATUS uart_tx_one_char2(uint8_t TxChar) ROMFN_ATTR;//for send message
+STATUS uart_rx_one_char(uint8_t* pRxChar) ROMFN_ATTR;
+char uart_rx_one_char_block(void) ROMFN_ATTR;
+void uart_rx_intr_handler(void * para) ROMFN_ATTR;
+STATUS uart_rx_readbuff( RcvMsgBuff* pRxBuff, uint8_t* pRxByte) ROMFN_ATTR;
+STATUS UartGetCmdLn(uint8_t * pCmdLn) ROMFN_ATTR;
+UartDevice * GetUartDevice() ROMFN_ATTR;
+
+void uartToggleInterrupt(bool en) ROMFN_ATTR;
+
+STATUS SendMsg(uint8_t *pData, uint16_t DataLen) ROMFN_ATTR;
+
+STATUS RcvMsg(uint8_t *pData, uint16_t MaxDataLen, uint8_t is_sync) ROMFN_ATTR;
+
+void uartAttach() ROMFN_ATTR;
+void uart_div_modify(uint8_t uart_no, uint32_t DivLatchValue) ROMFN_ATTR;
+int uart_baudrate_detect(uint8_t uart_no, uint8_t is_sync) ROMFN_ATTR;
+void uart_buff_switch(uint8_t uart_no)  ROMFN_ATTR;
+void uart_tx_flush(uint8_t uart_no) ROMFN_ATTR;
+void uart_tx_wait_idle(uint8_t uart_no) ROMFN_ATTR;
+extern UartDevice UartDev;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _ROM_UART_H_ */

components/esp32/include/rom/wdt.h

@@ -0,0 +1,40 @@
+// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef _ROM_WDT_H_
+#define _ROM_WDT_H_
+
+#include "soc.h"
+#include "ets_sys.h"
+
+#define WDT_RESET_VALUE         0x73
+#define WDT_RESET_LEN           7             //real time: (1<<(WDT_RESET_LEN+1))*pclk
+#define WDT_CONTROL_ENABLED     BIT0
+#define WDT_MODE_SET(v)         (v)
+#define WDT_TARGET_SET(v)       (v)
+#define WDT_ADDRESS             0
+
+#define SEC_TO_WDT_TICK(s) (s * WDT_CLK_FREQ)  //it's Pclk clock,44MHz
+
+typedef enum{
+    NEXT_OVERFLOW_RESET        = 0,
+    NEXT_OVERFLOW_NO_RESET     = 1,
+    EACH_OVERFLOW_RESET        = 2,
+} WDT_RESP_MODE;
+
+#define WDT_DEFAULT_FEED_INTERVAL       WDT_INTERVAL_SIX_SEC        /* 6 seconds */
+#define WDT_DEFAULT_EXPIRE_INTERVAL     WDT_INTERVAL_TWELVE_SEC     /* 12 seconds */
+
+#endif /* _ROM_WDT_H_ */
+

components/esp32/include/soc/bb_reg.h

@@ -0,0 +1,102 @@
+// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef _SOC_BB_REG_H_
+#define _SOC_BB_REG_H_
+
+#define apb_bb_offset 0x6001c000
+
+#define BB_DLY                 apb_bb_offset + 0x00009b00  // reg 00
+#define BB_TEST                 apb_bb_offset + 0x00009b08  // reg 02
+#define BB_TM1                 apb_bb_offset + 0x00009b0c  // reg 03
+#define BB_TM_CNTL             apb_bb_offset + 0x00009b14  // reg 05
+#define BB_DEL_CNTL          apb_bb_offset + 0x00009b28  // reg 10
+#define BB_PARAL_CNTL          apb_bb_offset + 0x00009b2c  // reg 11
+#define BB_FSM1                 apb_bb_offset + 0x00009b44  // reg 17
+#define BB_MXG                 apb_bb_offset + 0x00009b48  // reg 18
+#define BB_MNOF                apb_bb_offset + 0x00009b4c  // reg 19
+#define BB_SIZE                apb_bb_offset + 0x00009b50  // reg 20
+#define BB_TM3a                apb_bb_offset + 0x00009b54  // reg 21
+#define BB_TM4a                apb_bb_offset + 0x00009b58  // reg 22
+#define BB_GAIN                apb_bb_offset + 0x00009b5c  // reg 23
+#define BB_CNTL                apb_bb_offset + 0x00009b60  // reg 24
+#define BB_CAD                 apb_bb_offset + 0x00009b64  // reg 25
+#define BB_DET                 apb_bb_offset + 0x00009b68  // reg 26
+#define BB_DETL                apb_bb_offset + 0x00009b6c  // reg 27
+
+#define BB_MASK_PCLL               apb_bb_offset + 0x00009d08  // reg 66
+#define BB_MASK_PCLH               apb_bb_offset + 0x00009d0c  // reg 67
+#define BB_RX_CTRL4                apb_bb_offset + 0x00009d10  // reg 68
+#define BB_RX_CTRL                apb_bb_offset + 0x00009d1c  // reg 71
+#define BB_RX_CTRL2                apb_bb_offset + 0x00009d20  // reg 72
+#define BB_RX_CTRL3                apb_bb_offset + 0x00009d24  // reg 73
+#define BB_DEL4                 apb_bb_offset + 0x00009d40  // reg 80
+#define BB_TM5                 apb_bb_offset + 0x00009d44  // reg 81
+#define BB_TM6                 apb_bb_offset + 0x00009d48  // reg 82
+#define BB_PMCTRL                 apb_bb_offset + 0x00009d4c  // reg 83
+#define BB_PWR                 apb_bb_offset + 0x00009d68  // reg 90
+#define BB_BCTRL2                 apb_bb_offset + 0x00009d70  // reg 92
+
+#define BB_MASK_PL               apb_bb_offset + 0x00009884  // reg 97
+#define BB_MASK_PCHL               apb_bb_offset + 0x00009888  // reg 98
+#define BB_MASK_PCHH               apb_bb_offset + 0x0000988c  // reg 99
+
+#define BB_MASK_CL               apb_bb_offset + 0x0000989c  // reg 103
+#define BB_TONE               apb_bb_offset + 0x000098a0  // reg 104
+#define BB_MASK_CH               apb_bb_offset + 0x000098d4  // reg 117
+#define BB_SER               apb_bb_offset + 0x000098ec  // reg 123
+#define BB_GN_TB               apb_bb_offset + 0x00009e00  // reg 128
+
+#define BB_MODE                apb_bb_offset + 0x00009c00  // reg 640
+#define BB_TXCTRL               apb_bb_offset + 0x00009c04  // reg 641
+#define BB_BCTRL3                apb_bb_offset + 0x00009c08  // reg 642
+#define BB_BCTRL                apb_bb_offset + 0x00009c28  // reg 650
+#define BB_SMCTRL               apb_bb_offset + 0x00009c48  // reg 658
+#define BB_SMCTRL2               apb_bb_offset + 0x00009c4C  // reg 659
+#define BB_TXCNT               apb_bb_offset + 0x00009c58  // reg 662
+#define BB_RXCTRL               apb_bb_offset + 0x00009c68  // reg 666
+
+#define BB_TXGAIN               apb_bb_offset + 0x00009900  // reg 704
+
+#define BB_RXS_CNTL        apb_bb_offset + 0x00009988  // reg 738
+#define BB_MASK2_PCLL               apb_bb_offset + 0x000099a8  // reg 746
+#define BB_MASK2_PCLH               apb_bb_offset + 0x000099ac  // reg 747
+#define BB_MASK_PH               apb_bb_offset + 0x000099b0  // reg 748
+#define BB_MASK2_PCHL               apb_bb_offset + 0x000099b8  // reg 750
+#define BB_MASK2_PCHH               apb_bb_offset + 0x000099bc  // reg 751
+//
+#define BB_TX_TONE_CNTL        apb_bb_offset + 0x000099f0  // reg 764
+#define BB_ADD_CNTL0        apb_bb_offset + 0x00009a28  // reg 778
+#define BB_ADD_CNTL2        apb_bb_offset + 0x00009a2c  // reg 779
+#define BB_GAIN_CNTL0        apb_bb_offset + 0x00009a34  // reg 781
+#define BB_GAIN_CNTL1        apb_bb_offset + 0x00009a38  // reg 782
+#define BB_GAIN_CNTL2        apb_bb_offset + 0x00009a3c  // reg 783
+#define BB_AGCMEM_CTRL         apb_bb_offset + 0x00009a68  // reg 794
+
+#define BB_11B_RECORD          apb_bb_offset + 0x00009808  // reg 802
+#define BB_FILTER_CNTL         apb_bb_offset + 0x0000980c  // reg 803
+#define BB_ANALOG_CTRL1        apb_bb_offset + 0x00009838
+#define BB_ANALOG_CTRL2         apb_bb_offset + 0x0000983c  //reg 815
+#define BB_ANALOG_CTRL3         apb_bb_offset + 0x00009840  //reg 816
+#define BB_RFCFG_CTRL0          apb_bb_offset + 0x00009844  //reg 817
+#define BB_RFCFG_CTRL1          apb_bb_offset + 0x00009848  //reg 818
+
+#define BB_ADD_CNTL1             apb_bb_offset + 0x00009860  //reg824
+#define BB_PA_CNTL             apb_bb_offset + 0x00009864  //reg825
+#define BB_RFCFG_CTRL2          apb_bb_offset + 0x0000986c  //reg827
+#define BB_RXDEL_CTRL        apb_bb_offset + 0x00009d18
+#define BB_RXLENGTH_CTRL        apb_bb_offset + 0x00009d1c
+
+#endif /* _SOC_BB_REG_H_ */
+

components/esp32/include/soc/boot_mode.h

@@ -0,0 +1,104 @@
+// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef _SOC_BOOT_MODE_H_
+#define _SOC_BOOT_MODE_H_
+
+#include "soc.h"
+
+/*SPI Boot*/
+#define IS_1XXXX(v)				(((v)&0x10)==0x10)
+
+/*HSPI Boot*/
+#define IS_010XX(v)				(((v)&0x1c)==0x08)
+
+/*Download Boot, SDIO/UART0/UART1*/
+#define IS_00XXX(v)				(((v)&0x18)==0x00)
+
+/*Download Boot, SDIO/UART0/UART1,FEI_FEO V2*/
+#define IS_00X00(v)				(((v)&0x1b)==0x00)
+
+/*Download Boot, SDIO/UART0/UART1,FEI_REO V2*/
+#define IS_00X01(v)				(((v)&0x1b)==0x01)
+
+/*Download Boot, SDIO/UART0/UART1,REI_FEO V2*/
+#define IS_00X10(v)				(((v)&0x1b)==0x02)
+
+/*Download Boot, SDIO/UART0/UART1,REI_FEO V2*/
+#define IS_00X11(v)				(((v)&0x1b)==0x03)
+
+/*ATE/ANALOG Mode*/
+#define IS_01110(v)				(((v)&0x1f)==0x0e)
+
+/*Diagnostic Mode+UART0 download Mode*/
+#define IS_01111(v)				(((v)&0x1f)==0x0f)
+
+/*legacy SPI Boot*/
+#define IS_01100(v)				(((v)&0x1f)==0x0c)
+
+/*SDIO_Slave download Mode V1.1*/
+#define IS_01101(v)				(((v)&0x1f)==0x0d)
+
+
+
+#define BOOT_MODE_GET()                                 (GPIO_REG_READ(GPIO_STRAP))
+
+/*do not include download mode*/
+#define ETS_IS_UART_BOOT()				IS_01111(BOOT_MODE_GET())
+
+/*all spi boot including spi/hspi/legacy*/
+#define ETS_IS_FLASH_BOOT()				(IS_1XXXX(BOOT_MODE_GET()) || IS_010XX(BOOT_MODE_GET()) || IS_01100(BOOT_MODE_GET()))
+
+/*all faster spi boot including spi/hspi*/
+#define ETS_IS_FAST_FLASH_BOOT()				(IS_1XXXX(BOOT_MODE_GET()) || IS_010XX(BOOT_MODE_GET()))
+
+/*all spi boot including spi/legacy*/
+#define ETS_IS_SPI_FLASH_BOOT()				(IS_1XXXX(BOOT_MODE_GET()) || IS_01100(BOOT_MODE_GET()))
+
+/*all spi boot including hspi/legacy*/
+#define ETS_IS_HSPI_FLASH_BOOT()				IS_010XX(BOOT_MODE_GET())
+
+/*all sdio V2 of failing edge input, failing edge output*/
+#define ETS_IS_SDIO_FEI_FEO_V2_BOOT()				IS_00X00(BOOT_MODE_GET())
+
+/*all sdio V2 of failing edge input, raising edge output*/
+#define ETS_IS_SDIO_FEI_REO_V2_BOOT()				IS_00X01(BOOT_MODE_GET())
+
+/*all sdio V2 of raising edge input, failing edge output*/
+#define ETS_IS_SDIO_REI_FEO_V2_BOOT()				IS_00X10(BOOT_MODE_GET())
+
+/*all sdio V2 of raising edge input, raising edge output*/
+#define ETS_IS_SDIO_REI_REO_V2_BOOT()				IS_00X11(BOOT_MODE_GET())
+
+/*all sdio V1 of raising edge input, failing edge output*/
+#define ETS_IS_SDIO_REI_FEO_V1_BOOT()				IS_01101(BOOT_MODE_GET())
+
+/*do not include download mode*/
+#define ETS_IS_SDIO_BOOT()				IS_01101(BOOT_MODE_GET())
+
+/*joint download boot*/
+#define ETS_IS_SDIO_UART_BOOT()				IS_00XXX(BOOT_MODE_GET())
+
+/*ATE mode*/
+#define ETS_IS_ATE_BOOT()				IS_01110(BOOT_MODE_GET())
+
+/*A bit to control flash boot print*/
+#define ETS_IS_PRINT_BOOT()                             (BOOT_MODE_GET() & 0x2)
+
+/*used by  ETS_IS_SDIO_UART_BOOT*/
+#define SEL_NO_BOOT                                    0
+#define SEL_SDIO_BOOT                                 BIT0
+#define SEL_UART_BOOT                                BIT1
+
+#endif /* _SOC_BOOT_MODE_H_ */

components/esp32/include/soc/dport_reg.h

@@ -0,0 +1,1766 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_DPORT_REG_H_
+#define _SOC_DPORT_REG_H_
+
+#include "soc.h"
+
+#define PRO_BOOT_REMAP_CTRL_REG (DR_REG_DPORT_BASE + 0x000)
+#define DPORT_PRO_BOOT_REMAP (BIT(0))
+#define DPORT_PRO_BOOT_REMAP_S 0
+
+#define APP_BOOT_REMAP_CTRL_REG (DR_REG_DPORT_BASE + 0x004)
+#define DPORT_APP_BOOT_REMAP (BIT(0))
+#define DPORT_APP_BOOT_REMAP_S 0
+
+#define DPORT_ACCESS_CHECK (DR_REG_DPORT_BASE + 0x008)
+#define DPORT_DPORT_ACCESS_CHECK_APP (BIT(8))
+#define DPORT_DPORT_ACCESS_CHECK_APP_S 8
+#define DPORT_DPORT_ACCESS_CHECK_PRO (BIT(0))
+#define DPORT_DPORT_ACCESS_CHECK_PRO_S 0
+
+#define PRO_DPORT_APB_MASK0 (DR_REG_DPORT_BASE + 0x00C)
+#define DPORT_PRODPORT_APB_MASK0 0xFFFFFFFF
+#define DPORT_PRODPORT_APB_MASK0_S 0
+
+#define PRO_DPORT_APB_MASK1 (DR_REG_DPORT_BASE + 0x010)
+#define DPORT_PRODPORT_APB_MASK1 0xFFFFFFFF
+#define DPORT_PRODPORT_APB_MASK1_S 0
+
+#define APP_DPORT_APB_MASK0 (DR_REG_DPORT_BASE + 0x014)
+#define DPORT_APPDPORT_APB_MASK0 0xFFFFFFFF
+#define DPORT_APPDPORT_APB_MASK0_S 0
+
+#define APP_DPORT_APB_MASK1 (DR_REG_DPORT_BASE + 0x018)
+#define DPORT_APPDPORT_APB_MASK1 0xFFFFFFFF
+#define DPORT_APPDPORT_APB_MASK1_S 0
+
+#define PERI_CLK_EN (DR_REG_DPORT_BASE + 0x01C)
+#define DPORT_PERI_CLK_EN 0xFFFFFFFF
+#define DPORT_PERI_CLK_EN_S 0
+
+#define PERI_RST_EN (DR_REG_DPORT_BASE + 0x020)
+#define DPORT_PERI_RST_EN 0xFFFFFFFF
+#define DPORT_PERI_RST_EN_S 0
+
+#define WIFI_BB_CFG (DR_REG_DPORT_BASE + 0x024)
+#define DPORT_WIFI_BB_CFG 0xFFFFFFFF
+#define DPORT_WIFI_BB_CFG_S 0
+
+#define WIFI_BB_CFG_2 (DR_REG_DPORT_BASE + 0x028)
+#define DPORT_WIFI_BB_CFG_2 0xFFFFFFFF
+#define DPORT_WIFI_BB_CFG_2_S 0
+
+#define APPCPU_CTRL_REG_A (DR_REG_DPORT_BASE + 0x02C)
+#define DPORT_APPCPU_RESETTING (BIT(0))
+#define DPORT_APPCPU_RESETTING_S 0
+
+#define APPCPU_CTRL_REG_B (DR_REG_DPORT_BASE + 0x030)
+#define DPORT_APPCPU_CLKGATE_EN (BIT(0))
+#define DPORT_APPCPU_CLKGATE_EN_S 0
+
+#define APPCPU_CTRL_REG_C (DR_REG_DPORT_BASE + 0x034)
+#define DPORT_APPCPU_RUNSTALL (BIT(0))
+#define DPORT_APPCPU_RUNSTALL_S 0
+
+#define APPCPU_CTRL_REG_D (DR_REG_DPORT_BASE + 0x038)
+#define DPORT_APPCPU_BOOT_ADDR 0xFFFFFFFF
+#define DPORT_APPCPU_BOOT_ADDR_S 0
+
+#define CPU_PER_CONF_REG (DR_REG_DPORT_BASE + 0x03C)
+#define DPORT_FAST_CLK_RTC_SEL (BIT(3))
+#define DPORT_FAST_CLK_RTC_SEL_S 3
+#define DPORT_LOWSPEED_CLK_SEL (BIT(2))
+#define DPORT_LOWSPEED_CLK_SEL_S 2
+#define DPORT_CPUPERIOD_SEL 0x00000003
+#define DPORT_CPUPERIOD_SEL_S 0
+
+#define PRO_CACHE_CTRL_REG (DR_REG_DPORT_BASE + 0x040)
+#define DPORT_PRO_DRAM_HL (BIT(16))
+#define DPORT_PRO_DRAM_HL_S 16
+#define DPORT_SLAVE_REQ (BIT(15))
+#define DPORT_SLAVE_REQ_S 15
+#define DPORT_AHB_SPI_REQ (BIT(14))
+#define DPORT_AHB_SPI_REQ_S 14
+#define DPORT_PRO_SLAVE_REQ (BIT(13))
+#define DPORT_PRO_SLAVE_REQ_S 13
+#define DPORT_PRO_AHB_SPI_REQ (BIT(12))
+#define DPORT_PRO_AHB_SPI_REQ_S 12
+#define DPORT_PRO_DRAM_SPLIT (BIT(11))
+#define DPORT_PRO_DRAM_SPLIT_S 11
+#define DPORT_PRO_SINGLE_IRAM_ENA (BIT(10))
+#define DPORT_PRO_SINGLE_IRAM_ENA_S 10
+#define DPORT_PRO_CACHE_LOCK_3_EN (BIT(9))
+#define DPORT_PRO_CACHE_LOCK_3_EN_S 9
+#define DPORT_PRO_CACHE_LOCK_2_EN (BIT(8))
+#define DPORT_PRO_CACHE_LOCK_2_EN_S 8
+#define DPORT_PRO_CACHE_LOCK_1_EN (BIT(7))
+#define DPORT_PRO_CACHE_LOCK_1_EN_S 7
+#define DPORT_PRO_CACHE_LOCK_0_EN (BIT(6))
+#define DPORT_PRO_CACHE_LOCK_0_EN_S 6
+#define DPORT_PRO_CACHE_FLUSH_DONE (BIT(5))
+#define DPORT_PRO_CACHE_FLUSH_DONE_S 5
+#define DPORT_PRO_CACHE_FLUSH_ENA (BIT(4))
+#define DPORT_PRO_CACHE_FLUSH_ENA_S 4
+#define DPORT_PRO_CACHE_ENABLE (BIT(3))
+#define DPORT_PRO_CACHE_ENABLE_S 3
+#define DPORT_PRO_CACHE_MODE (BIT(2))
+#define DPORT_PRO_CACHE_MODE_S 2
+
+#define PRO_CACHE_CTRL1_REG (DR_REG_DPORT_BASE + 0x044)
+#define DPORT_PRO_CACHE_MMU_IA_CLR (BIT(13))
+#define DPORT_PRO_CACHE_MMU_IA_CLR_S 13
+#define DPORT_PRO_CMMU_PD (BIT(12))
+#define DPORT_PRO_CMMU_PD_S 12
+#define DPORT_PRO_CMMU_FORCE_ON (BIT(11))
+#define DPORT_PRO_CMMU_FORCE_ON_S 11
+#define DPORT_PRO_CMMU_FLASH_PAGE_MODE 0x00000003
+#define DPORT_PRO_CMMU_FLASH_PAGE_MODE_S 9
+#define DPORT_PRO_CMMU_SRAM_PAGE_MODE 0x00000007
+#define DPORT_PRO_CMMU_SRAM_PAGE_MODE_S 6
+#define DPORT_PRO_CACHE_MASK_OPSDRAM (BIT(5))
+#define DPORT_PRO_CACHE_MASK_OPSDRAM_S 5
+#define DPORT_PRO_CACHE_MASK_DROM0 (BIT(4))
+#define DPORT_PRO_CACHE_MASK_DROM0_S 4
+#define DPORT_PRO_CACHE_MASK_DRAM1 (BIT(3))
+#define DPORT_PRO_CACHE_MASK_DRAM1_S 3
+#define DPORT_PRO_CACHE_MASK_IROM0 (BIT(2))
+#define DPORT_PRO_CACHE_MASK_IROM0_S 2
+#define DPORT_PRO_CACHE_MASK_IRAM1 (BIT(1))
+#define DPORT_PRO_CACHE_MASK_IRAM1_S 1
+#define DPORT_PRO_CACHE_MASK_IRAM0 (BIT(0))
+#define DPORT_PRO_CACHE_MASK_IRAM0_S 0
+
+#define PRO_CACHE_LOCK_0_ADDR_REG (DR_REG_DPORT_BASE + 0x048)
+#define DPORT_PRO_CACHE_LOCK_0_ADDR_MAX 0x0000000F
+#define DPORT_PRO_CACHE_LOCK_0_ADDR_MAX_S 18
+#define DPORT_PRO_CACHE_LOCK_0_ADDR_MIN 0x0000000F
+#define DPORT_PRO_CACHE_LOCK_0_ADDR_MIN_S 14
+#define DPORT_PRO_CACHE_LOCK_0_ADDR_PRE 0x00003FFF
+#define DPORT_PRO_CACHE_LOCK_0_ADDR_PRE_S 0
+
+#define PRO_CACHE_LOCK_1_ADDR_REG (DR_REG_DPORT_BASE + 0x04C)
+#define DPORT_PRO_CACHE_LOCK_1_ADDR_MAX 0x0000000F
+#define DPORT_PRO_CACHE_LOCK_1_ADDR_MAX_S 18
+#define DPORT_PRO_CACHE_LOCK_1_ADDR_MIN 0x0000000F
+#define DPORT_PRO_CACHE_LOCK_1_ADDR_MIN_S 14
+#define DPORT_PRO_CACHE_LOCK_1_ADDR_PRE 0x00003FFF
+#define DPORT_PRO_CACHE_LOCK_1_ADDR_PRE_S 0
+
+#define PRO_CACHE_LOCK_2_ADDR_REG (DR_REG_DPORT_BASE + 0x050)
+#define DPORT_PRO_CACHE_LOCK_2_ADDR_MAX 0x0000000F
+#define DPORT_PRO_CACHE_LOCK_2_ADDR_MAX_S 18
+#define DPORT_PRO_CACHE_LOCK_2_ADDR_MIN 0x0000000F
+#define DPORT_PRO_CACHE_LOCK_2_ADDR_MIN_S 14
+#define DPORT_PRO_CACHE_LOCK_2_ADDR_PRE 0x00003FFF
+#define DPORT_PRO_CACHE_LOCK_2_ADDR_PRE_S 0
+
+#define PRO_CACHE_LOCK_3_ADDR_REG (DR_REG_DPORT_BASE + 0x054)
+#define DPORT_PRO_CACHE_LOCK_3_ADDR_MAX 0x0000000F
+#define DPORT_PRO_CACHE_LOCK_3_ADDR_MAX_S 18
+#define DPORT_PRO_CACHE_LOCK_3_ADDR_MIN 0x0000000F
+#define DPORT_PRO_CACHE_LOCK_3_ADDR_MIN_S 14
+#define DPORT_PRO_CACHE_LOCK_3_ADDR_PRE 0x00003FFF
+#define DPORT_PRO_CACHE_LOCK_3_ADDR_PRE_S 0
+
+#define APP_CACHE_CTRL_REG (DR_REG_DPORT_BASE + 0x058)
+#define DPORT_APP_DRAM_HL (BIT(14))
+#define DPORT_APP_DRAM_HL_S 14
+#define DPORT_APP_SLAVE_REQ (BIT(13))
+#define DPORT_APP_SLAVE_REQ_S 13
+#define DPORT_APP_AHB_SPI_REQ (BIT(12))
+#define DPORT_APP_AHB_SPI_REQ_S 12
+#define DPORT_APP_DRAM_SPLIT (BIT(11))
+#define DPORT_APP_DRAM_SPLIT_S 11
+#define DPORT_APP_SINGLE_IRAM_ENA (BIT(10))
+#define DPORT_APP_SINGLE_IRAM_ENA_S 10
+#define DPORT_APP_CACHE_LOCK_3_EN (BIT(9))
+#define DPORT_APP_CACHE_LOCK_3_EN_S 9
+#define DPORT_APP_CACHE_LOCK_2_EN (BIT(8))
+#define DPORT_APP_CACHE_LOCK_2_EN_S 8
+#define DPORT_APP_CACHE_LOCK_1_EN (BIT(7))
+#define DPORT_APP_CACHE_LOCK_1_EN_S 7
+#define DPORT_APP_CACHE_LOCK_0_EN (BIT(6))
+#define DPORT_APP_CACHE_LOCK_0_EN_S 6
+#define DPORT_APP_CACHE_FLUSH_DONE (BIT(5))
+#define DPORT_APP_CACHE_FLUSH_DONE_S 5
+#define DPORT_APP_CACHE_FLUSH_ENA (BIT(4))
+#define DPORT_APP_CACHE_FLUSH_ENA_S 4
+#define DPORT_APP_CACHE_ENABLE (BIT(3))
+#define DPORT_APP_CACHE_ENABLE_S 3
+#define DPORT_APP_CACHE_MODE (BIT(2))
+#define DPORT_APP_CACHE_MODE_S 2
+
+#define APP_CACHE_CTRL1_REG (DR_REG_DPORT_BASE + 0x05C)
+#define DPORT_APP_CACHE_MMU_IA_CLR (BIT(13))
+#define DPORT_APP_CACHE_MMU_IA_CLR_S 13
+#define DPORT_APP_CMMU_PD (BIT(12))
+#define DPORT_APP_CMMU_PD_S 12
+#define DPORT_APP_CMMU_FORCE_ON (BIT(11))
+#define DPORT_APP_CMMU_FORCE_ON_S 11
+#define DPORT_APP_CMMU_FLASH_PAGE_MODE 0x00000003
+#define DPORT_APP_CMMU_FLASH_PAGE_MODE_S 9
+#define DPORT_APP_CMMU_SRAM_PAGE_MODE 0x00000007
+#define DPORT_APP_CMMU_SRAM_PAGE_MODE_S 6
+#define DPORT_APP_CACHE_MASK_OPSDRAM (BIT(5))
+#define DPORT_APP_CACHE_MASK_OPSDRAM_S 5
+#define DPORT_APP_CACHE_MASK_DROM0 (BIT(4))
+#define DPORT_APP_CACHE_MASK_DROM0_S 4
+#define DPORT_APP_CACHE_MASK_DRAM1 (BIT(3))
+#define DPORT_APP_CACHE_MASK_DRAM1_S 3
+#define DPORT_APP_CACHE_MASK_IROM0 (BIT(2))
+#define DPORT_APP_CACHE_MASK_IROM0_S 2
+#define DPORT_APP_CACHE_MASK_IRAM1 (BIT(1))
+#define DPORT_APP_CACHE_MASK_IRAM1_S 1
+#define DPORT_APP_CACHE_MASK_IRAM0 (BIT(0))
+#define DPORT_APP_CACHE_MASK_IRAM0_S 0
+
+#define APP_CACHE_LOCK_0_ADDR_REG (DR_REG_DPORT_BASE + 0x060)
+#define DPORT_APP_CACHE_LOCK_0_ADDR_MAX 0x0000000F
+#define DPORT_APP_CACHE_LOCK_0_ADDR_MAX_S 18
+#define DPORT_APP_CACHE_LOCK_0_ADDR_MIN 0x0000000F
+#define DPORT_APP_CACHE_LOCK_0_ADDR_MIN_S 14
+#define DPORT_APP_CACHE_LOCK_0_ADDR_PRE 0x00003FFF
+#define DPORT_APP_CACHE_LOCK_0_ADDR_PRE_S 0
+
+#define APP_CACHE_LOCK_1_ADDR_REG (DR_REG_DPORT_BASE + 0x064)
+#define DPORT_APP_CACHE_LOCK_1_ADDR_MAX 0x0000000F
+#define DPORT_APP_CACHE_LOCK_1_ADDR_MAX_S 18
+#define DPORT_APP_CACHE_LOCK_1_ADDR_MIN 0x0000000F
+#define DPORT_APP_CACHE_LOCK_1_ADDR_MIN_S 14
+#define DPORT_APP_CACHE_LOCK_1_ADDR_PRE 0x00003FFF
+#define DPORT_APP_CACHE_LOCK_1_ADDR_PRE_S 0
+
+#define APP_CACHE_LOCK_2_ADDR_REG (DR_REG_DPORT_BASE + 0x068)
+#define DPORT_APP_CACHE_LOCK_2_ADDR_MAX 0x0000000F
+#define DPORT_APP_CACHE_LOCK_2_ADDR_MAX_S 18
+#define DPORT_APP_CACHE_LOCK_2_ADDR_MIN 0x0000000F
+#define DPORT_APP_CACHE_LOCK_2_ADDR_MIN_S 14
+#define DPORT_APP_CACHE_LOCK_2_ADDR_PRE 0x00003FFF
+#define DPORT_APP_CACHE_LOCK_2_ADDR_PRE_S 0
+
+#define APP_CACHE_LOCK_3_ADDR_REG (DR_REG_DPORT_BASE + 0x06C)
+#define DPORT_APP_CACHE_LOCK_3_ADDR_MAX 0x0000000F
+#define DPORT_APP_CACHE_LOCK_3_ADDR_MAX_S 18
+#define DPORT_APP_CACHE_LOCK_3_ADDR_MIN 0x0000000F
+#define DPORT_APP_CACHE_LOCK_3_ADDR_MIN_S 14
+#define DPORT_APP_CACHE_LOCK_3_ADDR_PRE 0x00003FFF
+#define DPORT_APP_CACHE_LOCK_3_ADDR_PRE_S 0
+
+#define TRACEMEM_MUX_MODE (DR_REG_DPORT_BASE + 0x070)
+#define DPORT_TRACEMEM_MUX_MODE 0x00000003
+#define DPORT_TRACEMEM_MUX_MODE_S 0
+
+#define PRO_TRACEMEM_ENA (DR_REG_DPORT_BASE + 0x074)
+#define DPORT_PRO_TRACEMEM_ENA (BIT(0))
+#define DPORT_PRO_TRACEMEM_ENA_S 0
+
+#define APP_TRACEMEM_ENA (DR_REG_DPORT_BASE + 0x078)
+#define DPORT_APP_TRACEMEM_ENA (BIT(0))
+#define DPORT_APP_TRACEMEM_ENA_S 0
+
+#define CACHE_MUX_MODE (DR_REG_DPORT_BASE + 0x07C)
+#define DPORT_CACHE_MUX_MODE 0x00000003
+#define DPORT_CACHE_MUX_MODE_S 0
+
+#define IMMU_PAGE_MODE (DR_REG_DPORT_BASE + 0x080)
+#define DPORT_IMMU_PAGE_MODE 0x00000003
+#define DPORT_IMMU_PAGE_MODE_S 1
+#define DPORT_INTERNAL_SRAM_IMMU_ENA (BIT(0))
+#define DPORT_INTERNAL_SRAM_IMMU_ENA_S 0
+
+#define DMMU_PAGE_MODE (DR_REG_DPORT_BASE + 0x084)
+#define DPORT_DMMU_PAGE_MODE 0x00000003
+#define DPORT_DMMU_PAGE_MODE_S 1
+#define DPORT_INTERNAL_SRAM_DMMU_ENA (BIT(0))
+#define DPORT_INTERNAL_SRAM_DMMU_ENA_S 0
+
+#define ROM_MPU_ENA (DR_REG_DPORT_BASE + 0x088)
+#define DPORT_APP_ROM_MPU_ENA (BIT(2))
+#define DPORT_APP_ROM_MPU_ENA_S 2
+#define DPORT_PRO_ROM_MPU_ENA (BIT(1))
+#define DPORT_PRO_ROM_MPU_ENA_S 1
+#define DPORT_SHARE_ROM_MPU_ENA (BIT(0))
+#define DPORT_SHARE_ROM_MPU_ENA_S 0
+
+#define MEM_PD_MASK_REG (DR_REG_DPORT_BASE + 0x08C)
+#define DPORT_LSLP_MEM_PD_MASK (BIT(0))
+#define DPORT_LSLP_MEM_PD_MASK_S 0
+
+#define ROM_PD_CTRL_REG (DR_REG_DPORT_BASE + 0x090)
+#define DPORT_SHARE_ROM_PD 0x0000003F
+#define DPORT_SHARE_ROM_PD_S 2
+#define DPORT_APP_ROM_PD (BIT(1))
+#define DPORT_APP_ROM_PD_S 1
+#define DPORT_PRO_ROM_PD (BIT(0))
+#define DPORT_PRO_ROM_PD_S 0
+
+#define ROM_FO_CTRL_REG (DR_REG_DPORT_BASE + 0x094)
+#define DPORT_SHARE_ROM_FO 0x0000003F
+#define DPORT_SHARE_ROM_FO_S 2
+#define DPORT_APP_ROM_FO (BIT(1))
+#define DPORT_APP_ROM_FO_S 1
+#define DPORT_PRO_ROM_FO (BIT(0))
+#define DPORT_PRO_ROM_FO_S 0
+
+#define SRAM_PD_CTRL_REG_0 (DR_REG_DPORT_BASE + 0x098)
+#define DPORT_SRAM_PD_0 0xFFFFFFFF
+#define DPORT_SRAM_PD_0_S 0
+
+#define SRAM_PD_CTRL_REG_1 (DR_REG_DPORT_BASE + 0x09C)
+#define DPORT_SRAM_PD_1 (BIT(0))
+#define DPORT_SRAM_PD_1_S 0
+
+#define SRAM_FO_CTRL_REG_0 (DR_REG_DPORT_BASE + 0x0A0)
+#define DPORT_SRAM_FO_0 0xFFFFFFFF
+#define DPORT_SRAM_FO_0_S 0
+
+#define SRAM_FO_CTRL_REG_1 (DR_REG_DPORT_BASE + 0x0A4)
+#define DPORT_SRAM_FO_1 (BIT(0))
+#define DPORT_SRAM_FO_1_S 0
+
+#define IRAM_DRAM_AHB_SEL (DR_REG_DPORT_BASE + 0x0A8)
+#define DPORT_MAC_DUMP_MODE 0x00000003
+#define DPORT_MAC_DUMP_MODE_S 5
+#define DPORT_MASK_AHB (BIT(4))
+#define DPORT_MASK_AHB_S 4
+#define DPORT_MASK_APP_DRAM (BIT(3))
+#define DPORT_MASK_APP_DRAM_S 3
+#define DPORT_MASK_PRO_DRAM (BIT(2))
+#define DPORT_MASK_PRO_DRAM_S 2
+#define DPORT_MASK_APP_IRAM (BIT(1))
+#define DPORT_MASK_APP_IRAM_S 1
+#define DPORT_MASK_PRO_IRAM (BIT(0))
+#define DPORT_MASK_PRO_IRAM_S 0
+
+#define TAG_FO_CTRL_REG (DR_REG_DPORT_BASE + 0x0AC)
+#define DPORT_APP_CACHE_TAG_PD (BIT(9))
+#define DPORT_APP_CACHE_TAG_PD_S 9
+#define DPORT_APP_CACHE_TAG_FORCE_ON (BIT(8))
+#define DPORT_APP_CACHE_TAG_FORCE_ON_S 8
+#define DPORT_PRO_CACHE_TAG_PD (BIT(1))
+#define DPORT_PRO_CACHE_TAG_PD_S 1
+#define DPORT_PRO_CACHE_TAG_FORCE_ON (BIT(0))
+#define DPORT_PRO_CACHE_TAG_FORCE_ON_S 0
+
+#define AHB_LITE_MASK_REG (DR_REG_DPORT_BASE + 0x0B0)
+#define DPORT_AHB_LITE_SDHOST_PID_REG 0x00000007
+#define DPORT_AHB_LITE_SDHOST_PID_REG_S 11
+#define DPORT_AHB_LITE_MASK_APPDPORT (BIT(10))
+#define DPORT_AHB_LITE_MASK_APPDPORT_S 10
+#define DPORT_AHB_LITE_MASK_PRODPORT (BIT(9))
+#define DPORT_AHB_LITE_MASK_PRODPORT_S 9
+#define DPORT_AHB_LITE_MASK_SDIO (BIT(8))
+#define DPORT_AHB_LITE_MASK_SDIO_S 8
+#define DPORT_AHB_LITE_MASK_APP (BIT(4))
+#define DPORT_AHB_LITE_MASK_APP_S 4
+#define DPORT_AHB_LITE_MASK_PRO (BIT(0))
+#define DPORT_AHB_LITE_MASK_PRO_S 0
+
+#define AHB_MPU_TABLE_0 (DR_REG_DPORT_BASE + 0x0B4)
+#define DPORT_AHB_ACCESS_GRANT_0 0xFFFFFFFF
+#define DPORT_AHB_ACCESS_GRANT_0_S 0
+
+#define AHB_MPU_TABLE_1 (DR_REG_DPORT_BASE + 0x0B8)
+#define DPORT_AHB_ACCESS_GRANT_1 0x000001FF
+#define DPORT_AHB_ACCESS_GRANT_1_S 0
+
+#define HOST_INF_SEL (DR_REG_DPORT_BASE + 0x0BC)
+#define DPORT_LINK_DEVICE_SEL 0x000000FF
+#define DPORT_LINK_DEVICE_SEL_S 8
+#define DPORT_PERI_IO_SWAP 0x000000FF
+#define DPORT_PERI_IO_SWAP_S 0
+
+#define PERIP_CLK_EN (DR_REG_DPORT_BASE + 0x0C0)
+#define DPORT_PERIP_CLK_EN 0xFFFFFFFF
+#define DPORT_PERIP_CLK_EN_S 0
+
+#define PERIP_RST_EN (DR_REG_DPORT_BASE + 0x0C4)
+#define DPORT_PERIP_RST 0xFFFFFFFF
+#define DPORT_PERIP_RST_S 0
+
+#define SLAVE_SPI_CONFIG_REG (DR_REG_DPORT_BASE + 0x0C8)
+#define DPORT_SPI_DECRYPT_ENABLE (BIT(12))
+#define DPORT_SPI_DECRYPT_ENABLE_S 12
+#define DPORT_SPI_ENCRYPT_ENABLE (BIT(8))
+#define DPORT_SPI_ENCRYPT_ENABLE_S 8
+#define DPORT_SLAVE_SPI_MASK_APP (BIT(4))
+#define DPORT_SLAVE_SPI_MASK_APP_S 4
+#define DPORT_SLAVE_SPI_MASK_PRO (BIT(0))
+#define DPORT_SLAVE_SPI_MASK_PRO_S 0
+
+#define WIFI_CLK_EN (DR_REG_DPORT_BASE + 0x0CC)
+#define DPORT_WIFI_CLK_EN 0xFFFFFFFF
+#define DPORT_WIFI_CLK_EN_S 0
+
+#define WIFI_RST_EN (DR_REG_DPORT_BASE + 0x0D0)
+#define DPORT_SDIO_RST (BIT(5))
+#define DPORT_MAC_RST (BIT(2))
+#define DPORT_WIFI_RST 0xFFFFFFFF
+#define DPORT_WIFI_RST_S 0
+
+#define BT_LPCK_DIV_INT (DR_REG_DPORT_BASE + 0x0D4)
+#define DPORT_BTEXTWAKEUP_REQ (BIT(12))
+#define DPORT_BTEXTWAKEUP_REQ_S 12
+#define DPORT_BT_LPCK_DIV_NUM 0x00000FFF
+#define DPORT_BT_LPCK_DIV_NUM_S 0
+
+#define BT_LPCK_DIV_FRAC (DR_REG_DPORT_BASE + 0x0D8)
+#define DPORT_LPCLK_SEL_XTAL32K (BIT(27))
+#define DPORT_LPCLK_SEL_XTAL32K_S 27
+#define DPORT_LPCLK_SEL_XTAL (BIT(26))
+#define DPORT_LPCLK_SEL_XTAL_S 26
+#define DPORT_LPCLK_SEL_8M (BIT(25))
+#define DPORT_LPCLK_SEL_8M_S 25
+#define DPORT_LPCLK_SEL_RTC_SLOW (BIT(24))
+#define DPORT_LPCLK_SEL_RTC_SLOW_S 24
+#define DPORT_BT_LPCK_DIV_A 0x00000FFF
+#define DPORT_BT_LPCK_DIV_A_S 12
+#define DPORT_BT_LPCK_DIV_B 0x00000FFF
+#define DPORT_BT_LPCK_DIV_B_S 0
+
+#define CPU_INTR_FROM_CPU_0_REG (DR_REG_DPORT_BASE + 0x0DC)
+#define DPORT_CPU_INTR_FROM_CPU_0 (BIT(0))
+#define DPORT_CPU_INTR_FROM_CPU_0_S 0
+
+#define CPU_INTR_FROM_CPU_1_REG (DR_REG_DPORT_BASE + 0x0E0)
+#define DPORT_CPU_INTR_FROM_CPU_1 (BIT(0))
+#define DPORT_CPU_INTR_FROM_CPU_1_S 0
+
+#define CPU_INTR_FROM_CPU_2_REG (DR_REG_DPORT_BASE + 0x0E4)
+#define DPORT_CPU_INTR_FROM_CPU_2 (BIT(0))
+#define DPORT_CPU_INTR_FROM_CPU_2_S 0
+
+#define CPU_INTR_FROM_CPU_3_REG (DR_REG_DPORT_BASE + 0x0E8)
+#define DPORT_CPU_INTR_FROM_CPU_3 (BIT(0))
+#define DPORT_CPU_INTR_FROM_CPU_3_S 0
+
+#define PRO_INTR_STATUS_REG_0 (DR_REG_DPORT_BASE + 0x0EC)
+#define DPORT_PRO_INTR_STATUS_0 0xFFFFFFFF
+#define DPORT_PRO_INTR_STATUS_0_S 0
+
+#define PRO_INTR_STATUS_REG_1 (DR_REG_DPORT_BASE + 0x0F0)
+#define DPORT_PRO_INTR_STATUS_1 0xFFFFFFFF
+#define DPORT_PRO_INTR_STATUS_1_S 0
+
+#define PRO_INTR_STATUS_REG_2 (DR_REG_DPORT_BASE + 0x0F4)
+#define DPORT_PRO_INTR_STATUS_2 0xFFFFFFFF
+#define DPORT_PRO_INTR_STATUS_2_S 0
+
+#define APP_INTR_STATUS_REG_0 (DR_REG_DPORT_BASE + 0x0F8)
+#define DPORT_APP_INTR_STATUS_0 0xFFFFFFFF
+#define DPORT_APP_INTR_STATUS_0_S 0
+
+#define APP_INTR_STATUS_REG_1 (DR_REG_DPORT_BASE + 0x0FC)
+#define DPORT_APP_INTR_STATUS_1 0xFFFFFFFF
+#define DPORT_APP_INTR_STATUS_1_S 0
+
+#define APP_INTR_STATUS_REG_2 (DR_REG_DPORT_BASE + 0x100)
+#define DPORT_APP_INTR_STATUS_2 0xFFFFFFFF
+#define DPORT_APP_INTR_STATUS_2_S 0
+
+#define PRO_MAC_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x104)
+#define DPORT_PRO_MAC_INTR_MAP 0x0000001F
+#define DPORT_PRO_MAC_INTR_MAP_S 0
+
+#define PRO_MAC_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x108)
+#define DPORT_PRO_MAC_NMI_MAP 0x0000001F
+#define DPORT_PRO_MAC_NMI_MAP_S 0
+
+#define PRO_BB_INT_MAP_REG (DR_REG_DPORT_BASE + 0x10C)
+#define DPORT_PRO_BB_INT_MAP 0x0000001F
+#define DPORT_PRO_BB_INT_MAP_S 0
+
+#define PRO_BT_MAC_INT_MAP_REG (DR_REG_DPORT_BASE + 0x110)
+#define DPORT_PRO_BT_MAC_INT_MAP 0x0000001F
+#define DPORT_PRO_BT_MAC_INT_MAP_S 0
+
+#define PRO_BT_BB_INT_MAP_REG (DR_REG_DPORT_BASE + 0x114)
+#define DPORT_PRO_BT_BB_INT_MAP 0x0000001F
+#define DPORT_PRO_BT_BB_INT_MAP_S 0
+
+#define PRO_BT_BB_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x118)
+#define DPORT_PRO_BT_BB_NMI_MAP 0x0000001F
+#define DPORT_PRO_BT_BB_NMI_MAP_S 0
+
+#define PRO_RWBT_IRQ_MAP_REG (DR_REG_DPORT_BASE + 0x11C)
+#define DPORT_PRO_RWBT_IRQ_MAP 0x0000001F
+#define DPORT_PRO_RWBT_IRQ_MAP_S 0
+
+#define PRO_RWBLE_IRQ_MAP_REG (DR_REG_DPORT_BASE + 0x120)
+#define DPORT_PRO_RWBLE_IRQ_MAP 0x0000001F
+#define DPORT_PRO_RWBLE_IRQ_MAP_S 0
+
+#define PRO_RWBT_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x124)
+#define DPORT_PRO_RWBT_NMI_MAP 0x0000001F
+#define DPORT_PRO_RWBT_NMI_MAP_S 0
+
+#define PRO_RWBLE_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x128)
+#define DPORT_PRO_RWBLE_NMI_MAP 0x0000001F
+#define DPORT_PRO_RWBLE_NMI_MAP_S 0
+
+#define PRO_SLC0_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x12C)
+#define DPORT_PRO_SLC0_INTR_MAP 0x0000001F
+#define DPORT_PRO_SLC0_INTR_MAP_S 0
+
+#define PRO_SLC1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x130)
+#define DPORT_PRO_SLC1_INTR_MAP 0x0000001F
+#define DPORT_PRO_SLC1_INTR_MAP_S 0
+
+#define PRO_UHCI0_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x134)
+#define DPORT_PRO_UHCI0_INTR_MAP 0x0000001F
+#define DPORT_PRO_UHCI0_INTR_MAP_S 0
+
+#define PRO_UHCI1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x138)
+#define DPORT_PRO_UHCI1_INTR_MAP 0x0000001F
+#define DPORT_PRO_UHCI1_INTR_MAP_S 0
+
+#define PRO_TG_T0_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x13C)
+#define DPORT_PRO_TG_T0_LEVEL_INT_MAP 0x0000001F
+#define DPORT_PRO_TG_T0_LEVEL_INT_MAP_S 0
+
+#define PRO_TG_T1_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x140)
+#define DPORT_PRO_TG_T1_LEVEL_INT_MAP 0x0000001F
+#define DPORT_PRO_TG_T1_LEVEL_INT_MAP_S 0
+
+#define PRO_TG_WDT_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x144)
+#define DPORT_PRO_TG_WDT_LEVEL_INT_MAP 0x0000001F
+#define DPORT_PRO_TG_WDT_LEVEL_INT_MAP_S 0
+
+#define PRO_TG_LACT_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x148)
+#define DPORT_PRO_TG_LACT_LEVEL_INT_MAP 0x0000001F
+#define DPORT_PRO_TG_LACT_LEVEL_INT_MAP_S 0
+
+#define PRO_TG1_T0_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x14C)
+#define DPORT_PRO_TG1_T0_LEVEL_INT_MAP 0x0000001F
+#define DPORT_PRO_TG1_T0_LEVEL_INT_MAP_S 0
+
+#define PRO_TG1_T1_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x150)
+#define DPORT_PRO_TG1_T1_LEVEL_INT_MAP 0x0000001F
+#define DPORT_PRO_TG1_T1_LEVEL_INT_MAP_S 0
+
+#define PRO_TG1_WDT_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x154)
+#define DPORT_PRO_TG1_WDT_LEVEL_INT_MAP 0x0000001F
+#define DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_S 0
+
+#define PRO_TG1_LACT_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x158)
+#define DPORT_PRO_TG1_LACT_LEVEL_INT_MAP 0x0000001F
+#define DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_S 0
+
+#define PRO_GPIO_INTERRUPT_MAP_REG (DR_REG_DPORT_BASE + 0x15C)
+#define DPORT_PRO_GPIO_INTERRUPT_PRO_MAP 0x0000001F
+#define DPORT_PRO_GPIO_INTERRUPT_PRO_MAP_S 0
+
+#define PRO_GPIO_INTERRUPT_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x160)
+#define DPORT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP 0x0000001F
+#define DPORT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP_S 0
+
+#define PRO_CPU_INTR_FROM_CPU_0_MAP_REG (DR_REG_DPORT_BASE + 0x164)
+#define DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP 0x0000001F
+#define DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_S 0
+
+#define PRO_CPU_INTR_FROM_CPU_1_MAP_REG (DR_REG_DPORT_BASE + 0x168)
+#define DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP 0x0000001F
+#define DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_S 0
+
+#define PRO_CPU_INTR_FROM_CPU_2_MAP_REG (DR_REG_DPORT_BASE + 0x16C)
+#define DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP 0x0000001F
+#define DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_S 0
+
+#define PRO_CPU_INTR_FROM_CPU_3_MAP_REG (DR_REG_DPORT_BASE + 0x170)
+#define DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP 0x0000001F
+#define DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_S 0
+
+#define PRO_SPI_INTR_0_MAP_REG (DR_REG_DPORT_BASE + 0x174)
+#define DPORT_PRO_SPI_INTR_0_MAP 0x0000001F
+#define DPORT_PRO_SPI_INTR_0_MAP_S 0
+
+#define PRO_SPI_INTR_1_MAP_REG (DR_REG_DPORT_BASE + 0x178)
+#define DPORT_PRO_SPI_INTR_1_MAP 0x0000001F
+#define DPORT_PRO_SPI_INTR_1_MAP_S 0
+
+#define PRO_SPI_INTR_2_MAP_REG (DR_REG_DPORT_BASE + 0x17C)
+#define DPORT_PRO_SPI_INTR_2_MAP 0x0000001F
+#define DPORT_PRO_SPI_INTR_2_MAP_S 0
+
+#define PRO_SPI_INTR_3_MAP_REG (DR_REG_DPORT_BASE + 0x180)
+#define DPORT_PRO_SPI_INTR_3_MAP 0x0000001F
+#define DPORT_PRO_SPI_INTR_3_MAP_S 0
+
+#define PRO_I2S0_INT_MAP_REG (DR_REG_DPORT_BASE + 0x184)
+#define DPORT_PRO_I2S0_INT_MAP 0x0000001F
+#define DPORT_PRO_I2S0_INT_MAP_S 0
+
+#define PRO_I2S1_INT_MAP_REG (DR_REG_DPORT_BASE + 0x188)
+#define DPORT_PRO_I2S1_INT_MAP 0x0000001F
+#define DPORT_PRO_I2S1_INT_MAP_S 0
+
+#define PRO_UART_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x18C)
+#define DPORT_PRO_UART_INTR_MAP 0x0000001F
+#define DPORT_PRO_UART_INTR_MAP_S 0
+
+#define PRO_UART1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x190)
+#define DPORT_PRO_UART1_INTR_MAP 0x0000001F
+#define DPORT_PRO_UART1_INTR_MAP_S 0
+
+#define PRO_UART2_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x194)
+#define DPORT_PRO_UART2_INTR_MAP 0x0000001F
+#define DPORT_PRO_UART2_INTR_MAP_S 0
+
+#define PRO_SDIO_HOST_INTERRUPT_MAP_REG (DR_REG_DPORT_BASE + 0x198)
+#define DPORT_PRO_SDIO_HOST_INTERRUPT_MAP 0x0000001F
+#define DPORT_PRO_SDIO_HOST_INTERRUPT_MAP_S 0
+
+#define PRO_EMAC_INT_MAP_REG (DR_REG_DPORT_BASE + 0x19C)
+#define DPORT_PRO_EMAC_INT_MAP 0x0000001F
+#define DPORT_PRO_EMAC_INT_MAP_S 0
+
+#define PRO_PWM0_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1A0)
+#define DPORT_PRO_PWM0_INTR_MAP 0x0000001F
+#define DPORT_PRO_PWM0_INTR_MAP_S 0
+
+#define PRO_PWM1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1A4)
+#define DPORT_PRO_PWM1_INTR_MAP 0x0000001F
+#define DPORT_PRO_PWM1_INTR_MAP_S 0
+
+#define PRO_PWM2_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1A8)
+#define DPORT_PRO_PWM2_INTR_MAP 0x0000001F
+#define DPORT_PRO_PWM2_INTR_MAP_S 0
+
+#define PRO_PWM3_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1AC)
+#define DPORT_PRO_PWM3_INTR_MAP 0x0000001F
+#define DPORT_PRO_PWM3_INTR_MAP_S 0
+
+#define PRO_LEDC_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1B0)
+#define DPORT_PRO_LEDC_INT_MAP 0x0000001F
+#define DPORT_PRO_LEDC_INT_MAP_S 0
+
+#define PRO_EFUSE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1B4)
+#define DPORT_PRO_EFUSE_INT_MAP 0x0000001F
+#define DPORT_PRO_EFUSE_INT_MAP_S 0
+
+#define PRO_CAN_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1B8)
+#define DPORT_PRO_CAN_INT_MAP 0x0000001F
+#define DPORT_PRO_CAN_INT_MAP_S 0
+
+#define PRO_RTC_CORE_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1BC)
+#define DPORT_PRO_RTC_CORE_INTR_MAP 0x0000001F
+#define DPORT_PRO_RTC_CORE_INTR_MAP_S 0
+
+#define PRO_RMT_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1C0)
+#define DPORT_PRO_RMT_INTR_MAP 0x0000001F
+#define DPORT_PRO_RMT_INTR_MAP_S 0
+
+#define PRO_PCNT_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1C4)
+#define DPORT_PRO_PCNT_INTR_MAP 0x0000001F
+#define DPORT_PRO_PCNT_INTR_MAP_S 0
+
+#define PRO_I2C_EXT0_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1C8)
+#define DPORT_PRO_I2C_EXT0_INTR_MAP 0x0000001F
+#define DPORT_PRO_I2C_EXT0_INTR_MAP_S 0
+
+#define PRO_I2C_EXT1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1CC)
+#define DPORT_PRO_I2C_EXT1_INTR_MAP 0x0000001F
+#define DPORT_PRO_I2C_EXT1_INTR_MAP_S 0
+
+#define PRO_RSA_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x1D0)
+#define DPORT_PRO_RSA_INTR_MAP 0x0000001F
+#define DPORT_PRO_RSA_INTR_MAP_S 0
+
+#define PRO_SPI1_DMA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1D4)
+#define DPORT_PRO_SPI1_DMA_INT_MAP 0x0000001F
+#define DPORT_PRO_SPI1_DMA_INT_MAP_S 0
+
+#define PRO_SPI2_DMA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1D8)
+#define DPORT_PRO_SPI2_DMA_INT_MAP 0x0000001F
+#define DPORT_PRO_SPI2_DMA_INT_MAP_S 0
+
+#define PRO_SPI3_DMA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1DC)
+#define DPORT_PRO_SPI3_DMA_INT_MAP 0x0000001F
+#define DPORT_PRO_SPI3_DMA_INT_MAP_S 0
+
+#define PRO_WDG_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1E0)
+#define DPORT_PRO_WDG_INT_MAP 0x0000001F
+#define DPORT_PRO_WDG_INT_MAP_S 0
+
+#define PRO_TIMER_INT1_MAP_REG (DR_REG_DPORT_BASE + 0x1E4)
+#define DPORT_PRO_TIMER_INT1_MAP 0x0000001F
+#define DPORT_PRO_TIMER_INT1_MAP_S 0
+
+#define PRO_TIMER_INT2_MAP_REG (DR_REG_DPORT_BASE + 0x1E8)
+#define DPORT_PRO_TIMER_INT2_MAP 0x0000001F
+#define DPORT_PRO_TIMER_INT2_MAP_S 0
+
+#define PRO_TG_T0_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1EC)
+#define DPORT_PRO_TG_T0_EDGE_INT_MAP 0x0000001F
+#define DPORT_PRO_TG_T0_EDGE_INT_MAP_S 0
+
+#define PRO_TG_T1_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1F0)
+#define DPORT_PRO_TG_T1_EDGE_INT_MAP 0x0000001F
+#define DPORT_PRO_TG_T1_EDGE_INT_MAP_S 0
+
+#define PRO_TG_WDT_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1F4)
+#define DPORT_PRO_TG_WDT_EDGE_INT_MAP 0x0000001F
+#define DPORT_PRO_TG_WDT_EDGE_INT_MAP_S 0
+
+#define PRO_TG_LACT_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1F8)
+#define DPORT_PRO_TG_LACT_EDGE_INT_MAP 0x0000001F
+#define DPORT_PRO_TG_LACT_EDGE_INT_MAP_S 0
+
+#define PRO_TG1_T0_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x1FC)
+#define DPORT_PRO_TG1_T0_EDGE_INT_MAP 0x0000001F
+#define DPORT_PRO_TG1_T0_EDGE_INT_MAP_S 0
+
+#define PRO_TG1_T1_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x200)
+#define DPORT_PRO_TG1_T1_EDGE_INT_MAP 0x0000001F
+#define DPORT_PRO_TG1_T1_EDGE_INT_MAP_S 0
+
+#define PRO_TG1_WDT_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x204)
+#define DPORT_PRO_TG1_WDT_EDGE_INT_MAP 0x0000001F
+#define DPORT_PRO_TG1_WDT_EDGE_INT_MAP_S 0
+
+#define PRO_TG1_LACT_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x208)
+#define DPORT_PRO_TG1_LACT_EDGE_INT_MAP 0x0000001F
+#define DPORT_PRO_TG1_LACT_EDGE_INT_MAP_S 0
+
+#define PRO_MMU_IA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x20C)
+#define DPORT_PRO_MMU_IA_INT_MAP 0x0000001F
+#define DPORT_PRO_MMU_IA_INT_MAP_S 0
+
+#define PRO_MPU_IA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x210)
+#define DPORT_PRO_MPU_IA_INT_MAP 0x0000001F
+#define DPORT_PRO_MPU_IA_INT_MAP_S 0
+
+#define PRO_CACHE_IA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x214)
+#define DPORT_PRO_CACHE_IA_INT_MAP 0x0000001F
+#define DPORT_PRO_CACHE_IA_INT_MAP_S 0
+
+#define APP_MAC_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x218)
+#define DPORT_APP_MAC_INTR_MAP 0x0000001F
+#define DPORT_APP_MAC_INTR_MAP_S 0
+
+#define APP_MAC_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x21C)
+#define DPORT_APP_MAC_NMI_MAP 0x0000001F
+#define DPORT_APP_MAC_NMI_MAP_S 0
+
+#define APP_BB_INT_MAP_REG (DR_REG_DPORT_BASE + 0x220)
+#define DPORT_APP_BB_INT_MAP 0x0000001F
+#define DPORT_APP_BB_INT_MAP_S 0
+
+#define APP_BT_MAC_INT_MAP_REG (DR_REG_DPORT_BASE + 0x224)
+#define DPORT_APP_BT_MAC_INT_MAP 0x0000001F
+#define DPORT_APP_BT_MAC_INT_MAP_S 0
+
+#define APP_BT_BB_INT_MAP_REG (DR_REG_DPORT_BASE + 0x228)
+#define DPORT_APP_BT_BB_INT_MAP 0x0000001F
+#define DPORT_APP_BT_BB_INT_MAP_S 0
+
+#define APP_BT_BB_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x22C)
+#define DPORT_APP_BT_BB_NMI_MAP 0x0000001F
+#define DPORT_APP_BT_BB_NMI_MAP_S 0
+
+#define APP_RWBT_IRQ_MAP_REG (DR_REG_DPORT_BASE + 0x230)
+#define DPORT_APP_RWBT_IRQ_MAP 0x0000001F
+#define DPORT_APP_RWBT_IRQ_MAP_S 0
+
+#define APP_RWBLE_IRQ_MAP_REG (DR_REG_DPORT_BASE + 0x234)
+#define DPORT_APP_RWBLE_IRQ_MAP 0x0000001F
+#define DPORT_APP_RWBLE_IRQ_MAP_S 0
+
+#define APP_RWBT_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x238)
+#define DPORT_APP_RWBT_NMI_MAP 0x0000001F
+#define DPORT_APP_RWBT_NMI_MAP_S 0
+
+#define APP_RWBLE_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x23C)
+#define DPORT_APP_RWBLE_NMI_MAP 0x0000001F
+#define DPORT_APP_RWBLE_NMI_MAP_S 0
+
+#define APP_SLC0_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x240)
+#define DPORT_APP_SLC0_INTR_MAP 0x0000001F
+#define DPORT_APP_SLC0_INTR_MAP_S 0
+
+#define APP_SLC1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x244)
+#define DPORT_APP_SLC1_INTR_MAP 0x0000001F
+#define DPORT_APP_SLC1_INTR_MAP_S 0
+
+#define APP_UHCI0_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x248)
+#define DPORT_APP_UHCI0_INTR_MAP 0x0000001F
+#define DPORT_APP_UHCI0_INTR_MAP_S 0
+
+#define APP_UHCI1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x24C)
+#define DPORT_APP_UHCI1_INTR_MAP 0x0000001F
+#define DPORT_APP_UHCI1_INTR_MAP_S 0
+
+#define APP_TG_T0_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x250)
+#define DPORT_APP_TG_T0_LEVEL_INT_MAP 0x0000001F
+#define DPORT_APP_TG_T0_LEVEL_INT_MAP_S 0
+
+#define APP_TG_T1_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x254)
+#define DPORT_APP_TG_T1_LEVEL_INT_MAP 0x0000001F
+#define DPORT_APP_TG_T1_LEVEL_INT_MAP_S 0
+
+#define APP_TG_WDT_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x258)
+#define DPORT_APP_TG_WDT_LEVEL_INT_MAP 0x0000001F
+#define DPORT_APP_TG_WDT_LEVEL_INT_MAP_S 0
+
+#define APP_TG_LACT_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x25C)
+#define DPORT_APP_TG_LACT_LEVEL_INT_MAP 0x0000001F
+#define DPORT_APP_TG_LACT_LEVEL_INT_MAP_S 0
+
+#define APP_TG1_T0_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x260)
+#define DPORT_APP_TG1_T0_LEVEL_INT_MAP 0x0000001F
+#define DPORT_APP_TG1_T0_LEVEL_INT_MAP_S 0
+
+#define APP_TG1_T1_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x264)
+#define DPORT_APP_TG1_T1_LEVEL_INT_MAP 0x0000001F
+#define DPORT_APP_TG1_T1_LEVEL_INT_MAP_S 0
+
+#define APP_TG1_WDT_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x268)
+#define DPORT_APP_TG1_WDT_LEVEL_INT_MAP 0x0000001F
+#define DPORT_APP_TG1_WDT_LEVEL_INT_MAP_S 0
+
+#define APP_TG1_LACT_LEVEL_INT_MAP_REG (DR_REG_DPORT_BASE + 0x26C)
+#define DPORT_APP_TG1_LACT_LEVEL_INT_MAP 0x0000001F
+#define DPORT_APP_TG1_LACT_LEVEL_INT_MAP_S 0
+
+#define APP_GPIO_INTERRUPT_MAP_REG (DR_REG_DPORT_BASE + 0x270)
+#define DPORT_APP_GPIO_INTERRUPT_APP_MAP 0x0000001F
+#define DPORT_APP_GPIO_INTERRUPT_APP_MAP_S 0
+
+#define APP_GPIO_INTERRUPT_NMI_MAP_REG (DR_REG_DPORT_BASE + 0x274)
+#define DPORT_APP_GPIO_INTERRUPT_APP_NMI_MAP 0x0000001F
+#define DPORT_APP_GPIO_INTERRUPT_APP_NMI_MAP_S 0
+
+#define APP_CPU_INTR_FROM_CPU_0_MAP_REG (DR_REG_DPORT_BASE + 0x278)
+#define DPORT_APP_CPU_INTR_FROM_CPU_0_MAP 0x0000001F
+#define DPORT_APP_CPU_INTR_FROM_CPU_0_MAP_S 0
+
+#define APP_CPU_INTR_FROM_CPU_1_MAP_REG (DR_REG_DPORT_BASE + 0x27C)
+#define DPORT_APP_CPU_INTR_FROM_CPU_1_MAP 0x0000001F
+#define DPORT_APP_CPU_INTR_FROM_CPU_1_MAP_S 0
+
+#define APP_CPU_INTR_FROM_CPU_2_MAP_REG (DR_REG_DPORT_BASE + 0x280)
+#define DPORT_APP_CPU_INTR_FROM_CPU_2_MAP 0x0000001F
+#define DPORT_APP_CPU_INTR_FROM_CPU_2_MAP_S 0
+
+#define APP_CPU_INTR_FROM_CPU_3_MAP_REG (DR_REG_DPORT_BASE + 0x284)
+#define DPORT_APP_CPU_INTR_FROM_CPU_3_MAP 0x0000001F
+#define DPORT_APP_CPU_INTR_FROM_CPU_3_MAP_S 0
+
+#define APP_SPI_INTR_0_MAP_REG (DR_REG_DPORT_BASE + 0x288)
+#define DPORT_APP_SPI_INTR_0_MAP 0x0000001F
+#define DPORT_APP_SPI_INTR_0_MAP_S 0
+
+#define APP_SPI_INTR_1_MAP_REG (DR_REG_DPORT_BASE + 0x28C)
+#define DPORT_APP_SPI_INTR_1_MAP 0x0000001F
+#define DPORT_APP_SPI_INTR_1_MAP_S 0
+
+#define APP_SPI_INTR_2_MAP_REG (DR_REG_DPORT_BASE + 0x290)
+#define DPORT_APP_SPI_INTR_2_MAP 0x0000001F
+#define DPORT_APP_SPI_INTR_2_MAP_S 0
+
+#define APP_SPI_INTR_3_MAP_REG (DR_REG_DPORT_BASE + 0x294)
+#define DPORT_APP_SPI_INTR_3_MAP 0x0000001F
+#define DPORT_APP_SPI_INTR_3_MAP_S 0
+
+#define APP_I2S0_INT_MAP_REG (DR_REG_DPORT_BASE + 0x298)
+#define DPORT_APP_I2S0_INT_MAP 0x0000001F
+#define DPORT_APP_I2S0_INT_MAP_S 0
+
+#define APP_I2S1_INT_MAP_REG (DR_REG_DPORT_BASE + 0x29C)
+#define DPORT_APP_I2S1_INT_MAP 0x0000001F
+#define DPORT_APP_I2S1_INT_MAP_S 0
+
+#define APP_UART_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2A0)
+#define DPORT_APP_UART_INTR_MAP 0x0000001F
+#define DPORT_APP_UART_INTR_MAP_S 0
+
+#define APP_UART1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2A4)
+#define DPORT_APP_UART1_INTR_MAP 0x0000001F
+#define DPORT_APP_UART1_INTR_MAP_S 0
+
+#define APP_UART2_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2A8)
+#define DPORT_APP_UART2_INTR_MAP 0x0000001F
+#define DPORT_APP_UART2_INTR_MAP_S 0
+
+#define APP_SDIO_HOST_INTERRUPT_MAP_REG (DR_REG_DPORT_BASE + 0x2AC)
+#define DPORT_APP_SDIO_HOST_INTERRUPT_MAP 0x0000001F
+#define DPORT_APP_SDIO_HOST_INTERRUPT_MAP_S 0
+
+#define APP_EMAC_INT_MAP_REG (DR_REG_DPORT_BASE + 0x2B0)
+#define DPORT_APP_EMAC_INT_MAP 0x0000001F
+#define DPORT_APP_EMAC_INT_MAP_S 0
+
+#define APP_PWM0_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2B4)
+#define DPORT_APP_PWM0_INTR_MAP 0x0000001F
+#define DPORT_APP_PWM0_INTR_MAP_S 0
+
+#define APP_PWM1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2B8)
+#define DPORT_APP_PWM1_INTR_MAP 0x0000001F
+#define DPORT_APP_PWM1_INTR_MAP_S 0
+
+#define APP_PWM2_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2BC)
+#define DPORT_APP_PWM2_INTR_MAP 0x0000001F
+#define DPORT_APP_PWM2_INTR_MAP_S 0
+
+#define APP_PWM3_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2C0)
+#define DPORT_APP_PWM3_INTR_MAP 0x0000001F
+#define DPORT_APP_PWM3_INTR_MAP_S 0
+
+#define APP_LEDC_INT_MAP_REG (DR_REG_DPORT_BASE + 0x2C4)
+#define DPORT_APP_LEDC_INT_MAP 0x0000001F
+#define DPORT_APP_LEDC_INT_MAP_S 0
+
+#define APP_EFUSE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x2C8)
+#define DPORT_APP_EFUSE_INT_MAP 0x0000001F
+#define DPORT_APP_EFUSE_INT_MAP_S 0
+
+#define APP_CAN_INT_MAP_REG (DR_REG_DPORT_BASE + 0x2CC)
+#define DPORT_APP_CAN_INT_MAP 0x0000001F
+#define DPORT_APP_CAN_INT_MAP_S 0
+
+#define APP_RTC_CORE_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2D0)
+#define DPORT_APP_RTC_CORE_INTR_MAP 0x0000001F
+#define DPORT_APP_RTC_CORE_INTR_MAP_S 0
+
+#define APP_RMT_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2D4)
+#define DPORT_APP_RMT_INTR_MAP 0x0000001F
+#define DPORT_APP_RMT_INTR_MAP_S 0
+
+#define APP_PCNT_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2D8)
+#define DPORT_APP_PCNT_INTR_MAP 0x0000001F
+#define DPORT_APP_PCNT_INTR_MAP_S 0
+
+#define APP_I2C_EXT0_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2DC)
+#define DPORT_APP_I2C_EXT0_INTR_MAP 0x0000001F
+#define DPORT_APP_I2C_EXT0_INTR_MAP_S 0
+
+#define APP_I2C_EXT1_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2E0)
+#define DPORT_APP_I2C_EXT1_INTR_MAP 0x0000001F
+#define DPORT_APP_I2C_EXT1_INTR_MAP_S 0
+
+#define APP_RSA_INTR_MAP_REG (DR_REG_DPORT_BASE + 0x2E4)
+#define DPORT_APP_RSA_INTR_MAP 0x0000001F
+#define DPORT_APP_RSA_INTR_MAP_S 0
+
+#define APP_SPI1_DMA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x2E8)
+#define DPORT_APP_SPI1_DMA_INT_MAP 0x0000001F
+#define DPORT_APP_SPI1_DMA_INT_MAP_S 0
+
+#define APP_SPI2_DMA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x2EC)
+#define DPORT_APP_SPI2_DMA_INT_MAP 0x0000001F
+#define DPORT_APP_SPI2_DMA_INT_MAP_S 0
+
+#define APP_SPI3_DMA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x2F0)
+#define DPORT_APP_SPI3_DMA_INT_MAP 0x0000001F
+#define DPORT_APP_SPI3_DMA_INT_MAP_S 0
+
+#define APP_WDG_INT_MAP_REG (DR_REG_DPORT_BASE + 0x2F4)
+#define DPORT_APP_WDG_INT_MAP 0x0000001F
+#define DPORT_APP_WDG_INT_MAP_S 0
+
+#define APP_TIMER_INT1_MAP_REG (DR_REG_DPORT_BASE + 0x2F8)
+#define DPORT_APP_TIMER_INT1_MAP 0x0000001F
+#define DPORT_APP_TIMER_INT1_MAP_S 0
+
+#define APP_TIMER_INT2_MAP_REG (DR_REG_DPORT_BASE + 0x2FC)
+#define DPORT_APP_TIMER_INT2_MAP 0x0000001F
+#define DPORT_APP_TIMER_INT2_MAP_S 0
+
+#define APP_TG_T0_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x300)
+#define DPORT_APP_TG_T0_EDGE_INT_MAP 0x0000001F
+#define DPORT_APP_TG_T0_EDGE_INT_MAP_S 0
+
+#define APP_TG_T1_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x304)
+#define DPORT_APP_TG_T1_EDGE_INT_MAP 0x0000001F
+#define DPORT_APP_TG_T1_EDGE_INT_MAP_S 0
+
+#define APP_TG_WDT_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x308)
+#define DPORT_APP_TG_WDT_EDGE_INT_MAP 0x0000001F
+#define DPORT_APP_TG_WDT_EDGE_INT_MAP_S 0
+
+#define APP_TG_LACT_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x30C)
+#define DPORT_APP_TG_LACT_EDGE_INT_MAP 0x0000001F
+#define DPORT_APP_TG_LACT_EDGE_INT_MAP_S 0
+
+#define APP_TG1_T0_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x310)
+#define DPORT_APP_TG1_T0_EDGE_INT_MAP 0x0000001F
+#define DPORT_APP_TG1_T0_EDGE_INT_MAP_S 0
+
+#define APP_TG1_T1_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x314)
+#define DPORT_APP_TG1_T1_EDGE_INT_MAP 0x0000001F
+#define DPORT_APP_TG1_T1_EDGE_INT_MAP_S 0
+
+#define APP_TG1_WDT_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x318)
+#define DPORT_APP_TG1_WDT_EDGE_INT_MAP 0x0000001F
+#define DPORT_APP_TG1_WDT_EDGE_INT_MAP_S 0
+
+#define APP_TG1_LACT_EDGE_INT_MAP_REG (DR_REG_DPORT_BASE + 0x31C)
+#define DPORT_APP_TG1_LACT_EDGE_INT_MAP 0x0000001F
+#define DPORT_APP_TG1_LACT_EDGE_INT_MAP_S 0
+
+#define APP_MMU_IA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x320)
+#define DPORT_APP_MMU_IA_INT_MAP 0x0000001F
+#define DPORT_APP_MMU_IA_INT_MAP_S 0
+
+#define APP_MPU_IA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x324)
+#define DPORT_APP_MPU_IA_INT_MAP 0x0000001F
+#define DPORT_APP_MPU_IA_INT_MAP_S 0
+
+#define APP_CACHE_IA_INT_MAP_REG (DR_REG_DPORT_BASE + 0x328)
+#define DPORT_APP_CACHE_IA_INT_MAP 0x0000001F
+#define DPORT_APP_CACHE_IA_INT_MAP_S 0
+
+#define AHBLITE_MPU_TABLE_UART (DR_REG_DPORT_BASE + 0x32C)
+#define DPORT_UART_ACCESS_GRANT_CONFIG 0x0000003F
+#define DPORT_UART_ACCESS_GRANT_CONFIG_S 0
+
+#define AHBLITE_MPU_TABLE_SPI1 (DR_REG_DPORT_BASE + 0x330)
+#define DPORT_SPI1_ACCESS_GRANT_CONFIG 0x0000003F
+#define DPORT_SPI1_ACCESS_GRANT_CONFIG_S 0
+
+#define AHBLITE_MPU_TABLE_SPI0 (DR_REG_DPORT_BASE + 0x334)
+#define DPORT_SPI0_ACCESS_GRANT_CONFIG 0x0000003F
+#define DPORT_SPI0_ACCESS_GRANT_CONFIG_S 0
+
+#define AHBLITE_MPU_TABLE_GPIO (DR_REG_DPORT_BASE + 0x338)
+#define DPORT_GPIO_ACCESS_GRANT_CONFIG 0x0000003F
+#define DPORT_GPIO_ACCESS_GRANT_CONFIG_S 0
+
+#define AHBLITE_MPU_TABLE_FE2 (DR_REG_DPORT_BASE + 0x33C)
+#define DPORT_FE2_ACCESS_GRANT_CONFIG 0x0000003F
+#define DPORT_FE2_ACCESS_GRANT_CONFIG_S 0
+
+#define AHBLITE_MPU_TABLE_FE (DR_REG_DPORT_BASE + 0x340)
+#define DPORT_FE_ACCESS_GRANT_CONFIG 0x0000003F
+#define DPORT_FE_ACCESS_GRANT_CONFIG_S 0
+
+#define AHBLITE_MPU_TABLE_TIMER (DR_REG_DPORT_BASE + 0x344)
+#define DPORT_TIMER_ACCESS_GRANT_CONFIG 0x0000003F
+#define DPORT_TIMER_ACCESS_GRANT_CONFIG_S 0
+
+#define AHBLITE_MPU_TABLE_RTC (DR_REG_DPORT_BASE + 0x348)
+#define DPORT_RTC_ACCESS_GRANT_CONFIG 0x0000003F
+#define DPORT_RTC_ACCESS_GRANT_CONFIG_S 0
+
+#define AHBLITE_MPU_TABLE_IO_MUX (DR_REG_DPORT_BASE + 0x34C)
+#define DPORT_IOMUX_ACCESS_GRANT_CONFIG 0x0000003F
+#define DPORT_IOMUX_ACCESS_GRANT_CONFIG_S 0
+
+#define AHBLITE_MPU_TABLE_WDG (DR_REG_DPORT_BASE + 0x350)
+#define DPORT_WDG_ACCESS_GRANT_CONFIG 0x0000003F
+#define DPORT_WDG_ACCESS_GRANT_CONFIG_S 0
+
+#define AHBLITE_MPU_TABLE_HINF (DR_REG_DPORT_BASE + 0x354)
+#define DPORT_HINF_ACCESS_GRANT_CONFIG 0x0000003F
+#define DPORT_HINF_ACCESS_GRANT_CONFIG_S 0
+
+#define AHBLITE_MPU_TABLE_UHCI1 (DR_REG_DPORT_BASE + 0x358)
+#define DPORT_UHCI1_ACCESS_GRANT_CONFIG 0x0000003F
+#define DPORT_UHCI1_ACCESS_GRANT_CONFIG_S 0
+
+#define AHBLITE_MPU_TABLE_MISC (DR_REG_DPORT_BASE + 0x35C)
+#define DPORT_MISC_ACCESS_GRANT_CONFIG 0x0000003F
+#define DPORT_MISC_ACCESS_GRANT_CONFIG_S 0
+
+#define AHBLITE_MPU_TABLE_I2C (DR_REG_DPORT_BASE + 0x360)
+#define DPORT_I2C_ACCESS_GRANT_CONFIG 0x0000003F
+#define DPORT_I2C_ACCESS_GRANT_CONFIG_S 0
+
+#define AHBLITE_MPU_TABLE_I2S0 (DR_REG_DPORT_BASE + 0x364)
+#define DPORT_I2S0_ACCESS_GRANT_CONFIG 0x0000003F
+#define DPORT_I2S0_ACCESS_GRANT_CONFIG_S 0
+
+#define AHBLITE_MPU_TABLE_UART1 (DR_REG_DPORT_BASE + 0x368)
+#define DPORT_UART1_ACCESS_GRANT_CONFIG 0x0000003F
+#define DPORT_UART1_ACCESS_GRANT_CONFIG_S 0
+
+#define AHBLITE_MPU_TABLE_BT (DR_REG_DPORT_BASE + 0x36C)
+#define DPORT_BT_ACCESS_GRANT_CONFIG 0x0000003F
+#define DPORT_BT_ACCESS_GRANT_CONFIG_S 0
+
+#define AHBLITE_MPU_TABLE_BT_BUFFER (DR_REG_DPORT_BASE + 0x370)
+#define DPORT_BTBUFFER_ACCESS_GRANT_CONFIG 0x0000003F
+#define DPORT_BTBUFFER_ACCESS_GRANT_CONFIG_S 0
+
+#define AHBLITE_MPU_TABLE_I2C_EXT0 (DR_REG_DPORT_BASE + 0x374)
+#define DPORT_I2CEXT0_ACCESS_GRANT_CONFIG 0x0000003F
+#define DPORT_I2CEXT0_ACCESS_GRANT_CONFIG_S 0
+
+#define AHBLITE_MPU_TABLE_UHCI0 (DR_REG_DPORT_BASE + 0x378)
+#define DPORT_UHCI0_ACCESS_GRANT_CONFIG 0x0000003F
+#define DPORT_UHCI0_ACCESS_GRANT_CONFIG_S 0
+
+#define AHBLITE_MPU_TABLE_SLCHOST (DR_REG_DPORT_BASE + 0x37C)
+#define DPORT_SLCHOST_ACCESS_GRANT_CONFIG 0x0000003F
+#define DPORT_SLCHOST_ACCESS_GRANT_CONFIG_S 0
+
+#define AHBLITE_MPU_TABLE_RMT (DR_REG_DPORT_BASE + 0x380)
+#define DPORT_RMT_ACCESS_GRANT_CONFIG 0x0000003F
+#define DPORT_RMT_ACCESS_GRANT_CONFIG_S 0
+
+#define AHBLITE_MPU_TABLE_PCNT (DR_REG_DPORT_BASE + 0x384)
+#define DPORT_PCNT_ACCESS_GRANT_CONFIG 0x0000003F
+#define DPORT_PCNT_ACCESS_GRANT_CONFIG_S 0
+
+#define AHBLITE_MPU_TABLE_SLC (DR_REG_DPORT_BASE + 0x388)
+#define DPORT_SLC_ACCESS_GRANT_CONFIG 0x0000003F
+#define DPORT_SLC_ACCESS_GRANT_CONFIG_S 0
+
+#define AHBLITE_MPU_TABLE_LEDC (DR_REG_DPORT_BASE + 0x38C)
+#define DPORT_LEDC_ACCESS_GRANT_CONFIG 0x0000003F
+#define DPORT_LEDC_ACCESS_GRANT_CONFIG_S 0
+
+#define AHBLITE_MPU_TABLE_EFUSE (DR_REG_DPORT_BASE + 0x390)
+#define DPORT_EFUSE_ACCESS_GRANT_CONFIG 0x0000003F
+#define DPORT_EFUSE_ACCESS_GRANT_CONFIG_S 0
+
+#define AHBLITE_MPU_TABLE_SPI_ENCRYPT (DR_REG_DPORT_BASE + 0x394)
+#define DPORT_SPI_ENCRYPY_ACCESS_GRANT_CONFIG 0x0000003F
+#define DPORT_SPI_ENCRYPY_ACCESS_GRANT_CONFIG_S 0
+
+#define AHBLITE_MPU_TABLE_BB (DR_REG_DPORT_BASE + 0x398)
+#define DPORT_BB_ACCESS_GRANT_CONFIG 0x0000003F
+#define DPORT_BB_ACCESS_GRANT_CONFIG_S 0
+
+#define AHBLITE_MPU_TABLE_PWM0 (DR_REG_DPORT_BASE + 0x39C)
+#define DPORT_PWM0_ACCESS_GRANT_CONFIG 0x0000003F
+#define DPORT_PWM0_ACCESS_GRANT_CONFIG_S 0
+
+#define AHBLITE_MPU_TABLE_TIMERGROUP (DR_REG_DPORT_BASE + 0x3A0)
+#define DPORT_TIMERGROUP_ACCESS_GRANT_CONFIG 0x0000003F
+#define DPORT_TIMERGROUP_ACCESS_GRANT_CONFIG_S 0
+
+#define AHBLITE_MPU_TABLE_TIMERGROUP1 (DR_REG_DPORT_BASE + 0x3A4)
+#define DPORT_TIMERGROUP1_ACCESS_GRANT_CONFIG 0x0000003F
+#define DPORT_TIMERGROUP1_ACCESS_GRANT_CONFIG_S 0
+
+#define AHBLITE_MPU_TABLE_SPI2 (DR_REG_DPORT_BASE + 0x3A8)
+#define DPORT_SPI2_ACCESS_GRANT_CONFIG 0x0000003F
+#define DPORT_SPI2_ACCESS_GRANT_CONFIG_S 0
+
+#define AHBLITE_MPU_TABLE_SPI3 (DR_REG_DPORT_BASE + 0x3AC)
+#define DPORT_SPI3_ACCESS_GRANT_CONFIG 0x0000003F
+#define DPORT_SPI3_ACCESS_GRANT_CONFIG_S 0
+
+#define AHBLITE_MPU_TABLE_APB_CTRL (DR_REG_DPORT_BASE + 0x3B0)
+#define DPORT_APBCTRL_ACCESS_GRANT_CONFIG 0x0000003F
+#define DPORT_APBCTRL_ACCESS_GRANT_CONFIG_S 0
+
+#define AHBLITE_MPU_TABLE_I2C_EXT1 (DR_REG_DPORT_BASE + 0x3B4)
+#define DPORT_I2CEXT1_ACCESS_GRANT_CONFIG 0x0000003F
+#define DPORT_I2CEXT1_ACCESS_GRANT_CONFIG_S 0
+
+#define AHBLITE_MPU_TABLE_SDIO_HOST (DR_REG_DPORT_BASE + 0x3B8)
+#define DPORT_SDIOHOST_ACCESS_GRANT_CONFIG 0x0000003F
+#define DPORT_SDIOHOST_ACCESS_GRANT_CONFIG_S 0
+
+#define AHBLITE_MPU_TABLE_EMAC (DR_REG_DPORT_BASE + 0x3BC)
+#define DPORT_EMAC_ACCESS_GRANT_CONFIG 0x0000003F
+#define DPORT_EMAC_ACCESS_GRANT_CONFIG_S 0
+
+#define AHBLITE_MPU_TABLE_CAN (DR_REG_DPORT_BASE + 0x3C0)
+#define DPORT_CAN_ACCESS_GRANT_CONFIG 0x0000003F
+#define DPORT_CAN_ACCESS_GRANT_CONFIG_S 0
+
+#define AHBLITE_MPU_TABLE_PWM1 (DR_REG_DPORT_BASE + 0x3C4)
+#define DPORT_PWM1_ACCESS_GRANT_CONFIG 0x0000003F
+#define DPORT_PWM1_ACCESS_GRANT_CONFIG_S 0
+
+#define AHBLITE_MPU_TABLE_I2S1 (DR_REG_DPORT_BASE + 0x3C8)
+#define DPORT_I2S1_ACCESS_GRANT_CONFIG 0x0000003F
+#define DPORT_I2S1_ACCESS_GRANT_CONFIG_S 0
+
+#define AHBLITE_MPU_TABLE_UART2 (DR_REG_DPORT_BASE + 0x3CC)
+#define DPORT_UART2_ACCESS_GRANT_CONFIG 0x0000003F
+#define DPORT_UART2_ACCESS_GRANT_CONFIG_S 0
+
+#define AHBLITE_MPU_TABLE_PWM2 (DR_REG_DPORT_BASE + 0x3D0)
+#define DPORT_PWM2_ACCESS_GRANT_CONFIG 0x0000003F
+#define DPORT_PWM2_ACCESS_GRANT_CONFIG_S 0
+
+#define AHBLITE_MPU_TABLE_PWM3 (DR_REG_DPORT_BASE + 0x3D4)
+#define DPORT_PWM3_ACCESS_GRANT_CONFIG 0x0000003F
+#define DPORT_PWM3_ACCESS_GRANT_CONFIG_S 0
+
+#define AHBLITE_MPU_TABLE_RWBT (DR_REG_DPORT_BASE + 0x3D8)
+#define DPORT_RWBT_ACCESS_GRANT_CONFIG 0x0000003F
+#define DPORT_RWBT_ACCESS_GRANT_CONFIG_S 0
+
+#define AHBLITE_MPU_TABLE_BTMAC (DR_REG_DPORT_BASE + 0x3DC)
+#define DPORT_BTMAC_ACCESS_GRANT_CONFIG 0x0000003F
+#define DPORT_BTMAC_ACCESS_GRANT_CONFIG_S 0
+
+#define AHBLITE_MPU_TABLE_WIFIMAC (DR_REG_DPORT_BASE + 0x3E0)
+#define DPORT_WIFIMAC_ACCESS_GRANT_CONFIG 0x0000003F
+#define DPORT_WIFIMAC_ACCESS_GRANT_CONFIG_S 0
+
+#define AHBLITE_MPU_TABLE_PWR (DR_REG_DPORT_BASE + 0x3E4)
+#define DPORT_PWR_ACCESS_GRANT_CONFIG 0x0000003F
+#define DPORT_PWR_ACCESS_GRANT_CONFIG_S 0
+
+#define MEM_ACCESS_DBUG0 (DR_REG_DPORT_BASE + 0x3E8)
+#define DPORT_INTERNAL_SRAM_MMU_MULTI_HIT 0x0000000F
+#define DPORT_INTERNAL_SRAM_MMU_MULTI_HIT_S 26
+#define DPORT_INTERNAL_SRAM_IA 0x00000FFF
+#define DPORT_INTERNAL_SRAM_IA_S 14
+#define DPORT_INTERNAL_SRAM_MMU_AD 0x0000000F
+#define DPORT_INTERNAL_SRAM_MMU_AD_S 10
+#define DPORT_SHARE_ROM_IA 0x0000000F
+#define DPORT_SHARE_ROM_IA_S 6
+#define DPORT_SHARE_ROM_MPU_AD 0x00000003
+#define DPORT_SHARE_ROM_MPU_AD_S 4
+#define DPORT_APP_ROM_IA (BIT(3))
+#define DPORT_APP_ROM_IA_S 3
+#define DPORT_APP_ROM_MPU_AD (BIT(2))
+#define DPORT_APP_ROM_MPU_AD_S 2
+#define DPORT_PRO_ROM_IA (BIT(1))
+#define DPORT_PRO_ROM_IA_S 1
+#define DPORT_PRO_ROM_MPU_AD (BIT(0))
+#define DPORT_PRO_ROM_MPU_AD_S 0
+
+#define MEM_ACCESS_DBUG1 (DR_REG_DPORT_BASE + 0x3EC)
+#define DPORT_AHBLITE_IA (BIT(10))
+#define DPORT_AHBLITE_IA_S 10
+#define DPORT_AHBLITE_ACCESS_DENY (BIT(9))
+#define DPORT_AHBLITE_ACCESS_DENY_S 9
+#define DPORT_AHB_ACCESS_DENY (BIT(8))
+#define DPORT_AHB_ACCESS_DENY_S 8
+#define DPORT_DPORT_PIDGEN_IA 0x00000003
+#define DPORT_DPORT_PIDGEN_IA_S 6
+#define DPORT_DPORT_ARB_IA 0x00000003
+#define DPORT_DPORT_ARB_IA_S 4
+#define DPORT_INTERNAL_SRAM_MMU_MISS 0x0000000F
+#define DPORT_INTERNAL_SRAM_MMU_MISS_S 0
+
+#define PRO_DCACHE_DBUG_REG0 (DR_REG_DPORT_BASE + 0x3F0)
+#define DPORT_PRO_RX_END (BIT(23))
+#define DPORT_PRO_RX_END_S 23
+#define DPORT_PRO_SLAVE_WDATA_V (BIT(22))
+#define DPORT_PRO_SLAVE_WDATA_V_S 22
+#define DPORT_PRO_SLAVE_WR (BIT(21))
+#define DPORT_PRO_SLAVE_WR_S 21
+#define DPORT_PRO_TX_END (BIT(20))
+#define DPORT_PRO_TX_END_S 20
+#define DPORT_PRO_WR_BAK_TO_READ (BIT(19))
+#define DPORT_PRO_WR_BAK_TO_READ_S 19
+#define DPORT_PRO_CACHE_STATE 0x00000FFF
+#define DPORT_PRO_CACHE_STATE_S 7
+#define DPORT_PRO_CACHE_IA 0x0000003F
+#define DPORT_PRO_CACHE_IA_S 1
+#define DPORT_PRO_CACHE_MMU_IA (BIT(0))
+#define DPORT_PRO_CACHE_MMU_IA_S 0
+
+#define PRO_DCACHE_DBUG_REG1 (DR_REG_DPORT_BASE + 0x3F4)
+#define DPORT_PRO_CTAG_RAM_RDATA 0xFFFFFFFF
+#define DPORT_PRO_CTAG_RAM_RDATA_S 0
+
+#define PRO_DCACHE_DBUG_REG2 (DR_REG_DPORT_BASE + 0x3F8)
+#define DPORT_PRO_CACHE_VADDR 0x07FFFFFF
+#define DPORT_PRO_CACHE_VADDR_S 0
+
+#define PRO_DCACHE_DBUG_REG3 (DR_REG_DPORT_BASE + 0x3FC)
+#define DPORT_PRO_CACHE_IRAM0_PID_ERROR (BIT(15))
+#define DPORT_PRO_CACHE_IRAM0_PID_ERROR_S 15
+#define DPORT_PRO_CPU_DISABLED_CACHE_IA 0x0000003F
+#define DPORT_PRO_CPU_DISABLED_CACHE_IA_S 9
+#define DPORT_PRO_MMU_RDATA 0x000001FF
+#define DPORT_PRO_MMU_RDATA_S 0
+
+#define PRO_DCACHE_DBUG_REG4 (DR_REG_DPORT_BASE + 0x400)
+#define DPORT_PRO_DRAM1ADDR0_IA 0x000FFFFF
+#define DPORT_PRO_DRAM1ADDR0_IA_S 0
+
+#define PRO_DCACHE_DBUG_REG5 (DR_REG_DPORT_BASE + 0x404)
+#define DPORT_PRO_DROM0ADDR0_IA 0x000FFFFF
+#define DPORT_PRO_DROM0ADDR0_IA_S 0
+
+#define PRO_DCACHE_DBUG_REG6 (DR_REG_DPORT_BASE + 0x408)
+#define DPORT_PRO_IRAM0ADDR_IA 0x000FFFFF
+#define DPORT_PRO_IRAM0ADDR_IA_S 0
+
+#define PRO_DCACHE_DBUG_REG7 (DR_REG_DPORT_BASE + 0x40C)
+#define DPORT_PRO_IRAM1ADDR_IA 0x000FFFFF
+#define DPORT_PRO_IRAM1ADDR_IA_S 0
+
+#define PRO_DCACHE_DBUG_REG8 (DR_REG_DPORT_BASE + 0x410)
+#define DPORT_PRO_IROM0ADDR_IA 0x000FFFFF
+#define DPORT_PRO_IROM0ADDR_IA_S 0
+
+#define PRO_DCACHE_DBUG_REG9 (DR_REG_DPORT_BASE + 0x414)
+#define DPORT_PRO_OPSDRAMADDR_IA 0x000FFFFF
+#define DPORT_PRO_OPSDRAMADDR_IA_S 0
+
+#define APP_DCACHE_DBUG_REG0 (DR_REG_DPORT_BASE + 0x418)
+#define DPORT_APP_RX_END (BIT(23))
+#define DPORT_APP_RX_END_S 23
+#define DPORT_APP_SLAVE_WDATA_V (BIT(22))
+#define DPORT_APP_SLAVE_WDATA_V_S 22
+#define DPORT_APP_SLAVE_WR (BIT(21))
+#define DPORT_APP_SLAVE_WR_S 21
+#define DPORT_APP_TX_END (BIT(20))
+#define DPORT_APP_TX_END_S 20
+#define DPORT_APP_WR_BAK_TO_READ (BIT(19))
+#define DPORT_APP_WR_BAK_TO_READ_S 19
+#define DPORT_APP_CACHE_STATE 0x00000FFF
+#define DPORT_APP_CACHE_STATE_S 7
+#define DPORT_APP_CACHE_IA 0x0000003F
+#define DPORT_APP_CACHE_IA_S 1
+#define DPORT_APP_CACHE_MMU_IA (BIT(0))
+#define DPORT_APP_CACHE_MMU_IA_S 0
+
+#define APP_DCACHE_DBUG_REG1 (DR_REG_DPORT_BASE + 0x41C)
+#define DPORT_APP_CTAG_RAM_RDATA 0xFFFFFFFF
+#define DPORT_APP_CTAG_RAM_RDATA_S 0
+
+#define APP_DCACHE_DBUG_REG2 (DR_REG_DPORT_BASE + 0x420)
+#define DPORT_APP_CACHE_VADDR 0x07FFFFFF
+#define DPORT_APP_CACHE_VADDR_S 0
+
+#define APP_DCACHE_DBUG_REG3 (DR_REG_DPORT_BASE + 0x424)
+#define DPORT_APP_CACHE_IRAM0_PID_ERROR (BIT(15))
+#define DPORT_APP_CACHE_IRAM0_PID_ERROR_S 15
+#define DPORT_APP_CPU_DISABLED_CACHE_IA 0x0000003F
+#define DPORT_APP_CPU_DISABLED_CACHE_IA_S 9
+#define DPORT_APP_MMU_RDATA 0x000001FF
+#define DPORT_APP_MMU_RDATA_S 0
+
+#define APP_DCACHE_DBUG_REG4 (DR_REG_DPORT_BASE + 0x428)
+#define DPORT_APP_DRAM1ADDR0_IA 0x000FFFFF
+#define DPORT_APP_DRAM1ADDR0_IA_S 0
+
+#define APP_DCACHE_DBUG_REG5 (DR_REG_DPORT_BASE + 0x42C)
+#define DPORT_APP_DROM0ADDR0_IA 0x000FFFFF
+#define DPORT_APP_DROM0ADDR0_IA_S 0
+
+#define APP_DCACHE_DBUG_REG6 (DR_REG_DPORT_BASE + 0x430)
+#define DPORT_APP_IRAM0ADDR_IA 0x000FFFFF
+#define DPORT_APP_IRAM0ADDR_IA_S 0
+
+#define APP_DCACHE_DBUG_REG7 (DR_REG_DPORT_BASE + 0x434)
+#define DPORT_APP_IRAM1ADDR_IA 0x000FFFFF
+#define DPORT_APP_IRAM1ADDR_IA_S 0
+
+#define APP_DCACHE_DBUG_REG8 (DR_REG_DPORT_BASE + 0x438)
+#define DPORT_APP_IROM0ADDR_IA 0x000FFFFF
+#define DPORT_APP_IROM0ADDR_IA_S 0
+
+#define APP_DCACHE_DBUG_REG9 (DR_REG_DPORT_BASE + 0x43C)
+#define DPORT_APP_OPSDRAMADDR_IA 0x000FFFFF
+#define DPORT_APP_OPSDRAMADDR_IA_S 0
+
+#define PRO_CPU_RECORD_CTRL (DR_REG_DPORT_BASE + 0x440)
+#define DPORT_PRO_CPU_PDEBUG_ENABLE (BIT(8))
+#define DPORT_PRO_CPU_PDEBUG_ENABLE_S 8
+#define DPORT_PRO_CPU_RECORD_DISABLE (BIT(4))
+#define DPORT_PRO_CPU_RECORD_DISABLE_S 4
+#define DPORT_PRO_CPU_RECORD_ENABLE (BIT(0))
+#define DPORT_PRO_CPU_RECORD_ENABLE_S 0
+
+#define PRO_CPU_RECORD_STATUS (DR_REG_DPORT_BASE + 0x444)
+#define DPORT_PRO_CPU_RECORDING (BIT(0))
+#define DPORT_PRO_CPU_RECORDING_S 0
+
+#define PRO_CPU_RECORD_PID (DR_REG_DPORT_BASE + 0x448)
+#define DPORT_RECORD_PRO_PID 0x00000007
+#define DPORT_RECORD_PRO_PID_S 0
+
+#define PRO_CPU_RECORD_PDEBUGINST (DR_REG_DPORT_BASE + 0x44C)
+#define DPORT_RECORD_PRO_PDEBUGINST 0xFFFFFFFF
+#define DPORT_RECORD_PRO_PDEBUGINST_S 0
+
+#define PRO_CPU_RECORD_PDEBUGSTATUS (DR_REG_DPORT_BASE + 0x450)
+#define DPORT_RECORD_PRO_PDEBUGSTATUS 0x000000FF
+#define DPORT_RECORD_PRO_PDEBUGSTATUS_S 0
+
+#define PRO_CPU_RECORD_PDEBUGDATA (DR_REG_DPORT_BASE + 0x454)
+#define DPORT_RECORD_PRO_PDEBUGDATA 0xFFFFFFFF
+#define DPORT_RECORD_PRO_PDEBUGDATA_S 0
+
+#define PRO_CPU_RECORD_PDEBUGPC (DR_REG_DPORT_BASE + 0x458)
+#define DPORT_RECORD_PRO_PDEBUGPC 0xFFFFFFFF
+#define DPORT_RECORD_PRO_PDEBUGPC_S 0
+
+#define PRO_CPU_RECORD_PDEBUGLS0STAT (DR_REG_DPORT_BASE + 0x45C)
+#define DPORT_RECORD_PRO_PDEBUGLS0STAT 0xFFFFFFFF
+#define DPORT_RECORD_PRO_PDEBUGLS0STAT_S 0
+
+#define PRO_CPU_RECORD_PDEBUGLS0ADDR (DR_REG_DPORT_BASE + 0x460)
+#define DPORT_RECORD_PRO_PDEBUGLS0ADDR 0xFFFFFFFF
+#define DPORT_RECORD_PRO_PDEBUGLS0ADDR_S 0
+
+#define PRO_CPU_RECORD_PDEBUGLS0DATA (DR_REG_DPORT_BASE + 0x464)
+#define DPORT_RECORD_PRO_PDEBUGLS0DATA 0xFFFFFFFF
+#define DPORT_RECORD_PRO_PDEBUGLS0DATA_S 0
+
+#define APP_CPU_RECORD_CTRL (DR_REG_DPORT_BASE + 0x468)
+#define DPORT_APP_CPU_PDEBUG_ENABLE (BIT(8))
+#define DPORT_APP_CPU_PDEBUG_ENABLE_S 8
+#define DPORT_APP_CPU_RECORD_DISABLE (BIT(4))
+#define DPORT_APP_CPU_RECORD_DISABLE_S 4
+#define DPORT_APP_CPU_RECORD_ENABLE (BIT(0))
+#define DPORT_APP_CPU_RECORD_ENABLE_S 0
+
+#define APP_CPU_RECORD_STATUS (DR_REG_DPORT_BASE + 0x46C)
+#define DPORT_APP_CPU_RECORDING (BIT(0))
+#define DPORT_APP_CPU_RECORDING_S 0
+
+#define APP_CPU_RECORD_PID (DR_REG_DPORT_BASE + 0x470)
+#define DPORT_RECORD_APP_PID 0x00000007
+#define DPORT_RECORD_APP_PID_S 0
+
+#define APP_CPU_RECORD_PDEBUGINST (DR_REG_DPORT_BASE + 0x474)
+#define DPORT_RECORD_APP_PDEBUGINST 0xFFFFFFFF
+#define DPORT_RECORD_APP_PDEBUGINST_S 0
+
+#define APP_CPU_RECORD_PDEBUGSTATUS (DR_REG_DPORT_BASE + 0x478)
+#define DPORT_RECORD_APP_PDEBUGSTATUS 0x000000FF
+#define DPORT_RECORD_APP_PDEBUGSTATUS_S 0
+
+#define APP_CPU_RECORD_PDEBUGDATA (DR_REG_DPORT_BASE + 0x47C)
+#define DPORT_RECORD_APP_PDEBUGDATA 0xFFFFFFFF
+#define DPORT_RECORD_APP_PDEBUGDATA_S 0
+
+#define APP_CPU_RECORD_PDEBUGPC (DR_REG_DPORT_BASE + 0x480)
+#define DPORT_RECORD_APP_PDEBUGPC 0xFFFFFFFF
+#define DPORT_RECORD_APP_PDEBUGPC_S 0
+
+#define APP_CPU_RECORD_PDEBUGLS0STAT (DR_REG_DPORT_BASE + 0x484)
+#define DPORT_RECORD_APP_PDEBUGLS0STAT 0xFFFFFFFF
+#define DPORT_RECORD_APP_PDEBUGLS0STAT_S 0
+
+#define APP_CPU_RECORD_PDEBUGLS0ADDR (DR_REG_DPORT_BASE + 0x488)
+#define DPORT_RECORD_APP_PDEBUGLS0ADDR 0xFFFFFFFF
+#define DPORT_RECORD_APP_PDEBUGLS0ADDR_S 0
+
+#define APP_CPU_RECORD_PDEBUGLS0DATA (DR_REG_DPORT_BASE + 0x48C)
+#define DPORT_RECORD_APP_PDEBUGLS0DATA 0xFFFFFFFF
+#define DPORT_RECORD_APP_PDEBUGLS0DATA_S 0
+
+#define RSA_PD_CTRL_REG (DR_REG_DPORT_BASE + 0x490)
+#define DPORT_RSA_PD (BIT(0))
+#define DPORT_RSA_PD_S 0
+
+#define ROM_MPU_TABLE0 (DR_REG_DPORT_BASE + 0x494)
+#define DPORT_ROM_MPU_TABLE0 0x00000003
+#define DPORT_ROM_MPU_TABLE0_S 0
+
+#define ROM_MPU_TABLE1 (DR_REG_DPORT_BASE + 0x498)
+#define DPORT_ROM_MPU_TABLE1 0x00000003
+#define DPORT_ROM_MPU_TABLE1_S 0
+
+#define ROM_MPU_TABLE2 (DR_REG_DPORT_BASE + 0x49C)
+#define DPORT_ROM_MPU_TABLE2 0x00000003
+#define DPORT_ROM_MPU_TABLE2_S 0
+
+#define ROM_MPU_TABLE3 (DR_REG_DPORT_BASE + 0x4A0)
+#define DPORT_ROM_MPU_TABLE3 0x00000003
+#define DPORT_ROM_MPU_TABLE3_S 0
+
+#define SHROM_MPU_TABLE0 (DR_REG_DPORT_BASE + 0x4A4)
+#define DPORT_SHROM_MPU_TABLE0 0x00000003
+#define DPORT_SHROM_MPU_TABLE0_S 0
+
+#define SHROM_MPU_TABLE1 (DR_REG_DPORT_BASE + 0x4A8)
+#define DPORT_SHROM_MPU_TABLE1 0x00000003
+#define DPORT_SHROM_MPU_TABLE1_S 0
+
+#define SHROM_MPU_TABLE2 (DR_REG_DPORT_BASE + 0x4AC)
+#define DPORT_SHROM_MPU_TABLE2 0x00000003
+#define DPORT_SHROM_MPU_TABLE2_S 0
+
+#define SHROM_MPU_TABLE3 (DR_REG_DPORT_BASE + 0x4B0)
+#define DPORT_SHROM_MPU_TABLE3 0x00000003
+#define DPORT_SHROM_MPU_TABLE3_S 0
+
+#define SHROM_MPU_TABLE4 (DR_REG_DPORT_BASE + 0x4B4)
+#define DPORT_SHROM_MPU_TABLE4 0x00000003
+#define DPORT_SHROM_MPU_TABLE4_S 0
+
+#define SHROM_MPU_TABLE5 (DR_REG_DPORT_BASE + 0x4B8)
+#define DPORT_SHROM_MPU_TABLE5 0x00000003
+#define DPORT_SHROM_MPU_TABLE5_S 0
+
+#define SHROM_MPU_TABLE6 (DR_REG_DPORT_BASE + 0x4BC)
+#define DPORT_SHROM_MPU_TABLE6 0x00000003
+#define DPORT_SHROM_MPU_TABLE6_S 0
+
+#define SHROM_MPU_TABLE7 (DR_REG_DPORT_BASE + 0x4C0)
+#define DPORT_SHROM_MPU_TABLE7 0x00000003
+#define DPORT_SHROM_MPU_TABLE7_S 0
+
+#define SHROM_MPU_TABLE8 (DR_REG_DPORT_BASE + 0x4C4)
+#define DPORT_SHROM_MPU_TABLE8 0x00000003
+#define DPORT_SHROM_MPU_TABLE8_S 0
+
+#define SHROM_MPU_TABLE9 (DR_REG_DPORT_BASE + 0x4C8)
+#define DPORT_SHROM_MPU_TABLE9 0x00000003
+#define DPORT_SHROM_MPU_TABLE9_S 0
+
+#define SHROM_MPU_TABLE10 (DR_REG_DPORT_BASE + 0x4CC)
+#define DPORT_SHROM_MPU_TABLE10 0x00000003
+#define DPORT_SHROM_MPU_TABLE10_S 0
+
+#define SHROM_MPU_TABLE11 (DR_REG_DPORT_BASE + 0x4D0)
+#define DPORT_SHROM_MPU_TABLE11 0x00000003
+#define DPORT_SHROM_MPU_TABLE11_S 0
+
+#define SHROM_MPU_TABLE12 (DR_REG_DPORT_BASE + 0x4D4)
+#define DPORT_SHROM_MPU_TABLE12 0x00000003
+#define DPORT_SHROM_MPU_TABLE12_S 0
+
+#define SHROM_MPU_TABLE13 (DR_REG_DPORT_BASE + 0x4D8)
+#define DPORT_SHROM_MPU_TABLE13 0x00000003
+#define DPORT_SHROM_MPU_TABLE13_S 0
+
+#define SHROM_MPU_TABLE14 (DR_REG_DPORT_BASE + 0x4DC)
+#define DPORT_SHROM_MPU_TABLE14 0x00000003
+#define DPORT_SHROM_MPU_TABLE14_S 0
+
+#define SHROM_MPU_TABLE15 (DR_REG_DPORT_BASE + 0x4E0)
+#define DPORT_SHROM_MPU_TABLE15 0x00000003
+#define DPORT_SHROM_MPU_TABLE15_S 0
+
+#define SHROM_MPU_TABLE16 (DR_REG_DPORT_BASE + 0x4E4)
+#define DPORT_SHROM_MPU_TABLE16 0x00000003
+#define DPORT_SHROM_MPU_TABLE16_S 0
+
+#define SHROM_MPU_TABLE17 (DR_REG_DPORT_BASE + 0x4E8)
+#define DPORT_SHROM_MPU_TABLE17 0x00000003
+#define DPORT_SHROM_MPU_TABLE17_S 0
+
+#define SHROM_MPU_TABLE18 (DR_REG_DPORT_BASE + 0x4EC)
+#define DPORT_SHROM_MPU_TABLE18 0x00000003
+#define DPORT_SHROM_MPU_TABLE18_S 0
+
+#define SHROM_MPU_TABLE19 (DR_REG_DPORT_BASE + 0x4F0)
+#define DPORT_SHROM_MPU_TABLE19 0x00000003
+#define DPORT_SHROM_MPU_TABLE19_S 0
+
+#define SHROM_MPU_TABLE20 (DR_REG_DPORT_BASE + 0x4F4)
+#define DPORT_SHROM_MPU_TABLE20 0x00000003
+#define DPORT_SHROM_MPU_TABLE20_S 0
+
+#define SHROM_MPU_TABLE21 (DR_REG_DPORT_BASE + 0x4F8)
+#define DPORT_SHROM_MPU_TABLE21 0x00000003
+#define DPORT_SHROM_MPU_TABLE21_S 0
+
+#define SHROM_MPU_TABLE22 (DR_REG_DPORT_BASE + 0x4FC)
+#define DPORT_SHROM_MPU_TABLE22 0x00000003
+#define DPORT_SHROM_MPU_TABLE22_S 0
+
+#define SHROM_MPU_TABLE23 (DR_REG_DPORT_BASE + 0x500)
+#define DPORT_SHROM_MPU_TABLE23 0x00000003
+#define DPORT_SHROM_MPU_TABLE23_S 0
+
+#define IMMU_TABLE0 (DR_REG_DPORT_BASE + 0x504)
+#define DPORT_IMMU_TABLE0 0x0000007F
+#define DPORT_IMMU_TABLE0_S 0
+
+#define IMMU_TABLE1 (DR_REG_DPORT_BASE + 0x508)
+#define DPORT_IMMU_TABLE1 0x0000007F
+#define DPORT_IMMU_TABLE1_S 0
+
+#define IMMU_TABLE2 (DR_REG_DPORT_BASE + 0x50C)
+#define DPORT_IMMU_TABLE2 0x0000007F
+#define DPORT_IMMU_TABLE2_S 0
+
+#define IMMU_TABLE3 (DR_REG_DPORT_BASE + 0x510)
+#define DPORT_IMMU_TABLE3 0x0000007F
+#define DPORT_IMMU_TABLE3_S 0
+
+#define IMMU_TABLE4 (DR_REG_DPORT_BASE + 0x514)
+#define DPORT_IMMU_TABLE4 0x0000007F
+#define DPORT_IMMU_TABLE4_S 0
+
+#define IMMU_TABLE5 (DR_REG_DPORT_BASE + 0x518)
+#define DPORT_IMMU_TABLE5 0x0000007F
+#define DPORT_IMMU_TABLE5_S 0
+
+#define IMMU_TABLE6 (DR_REG_DPORT_BASE + 0x51C)
+#define DPORT_IMMU_TABLE6 0x0000007F
+#define DPORT_IMMU_TABLE6_S 0
+
+#define IMMU_TABLE7 (DR_REG_DPORT_BASE + 0x520)
+#define DPORT_IMMU_TABLE7 0x0000007F
+#define DPORT_IMMU_TABLE7_S 0
+
+#define IMMU_TABLE8 (DR_REG_DPORT_BASE + 0x524)
+#define DPORT_IMMU_TABLE8 0x0000007F
+#define DPORT_IMMU_TABLE8_S 0
+
+#define IMMU_TABLE9 (DR_REG_DPORT_BASE + 0x528)
+#define DPORT_IMMU_TABLE9 0x0000007F
+#define DPORT_IMMU_TABLE9_S 0
+
+#define IMMU_TABLE10 (DR_REG_DPORT_BASE + 0x52C)
+#define DPORT_IMMU_TABLE10 0x0000007F
+#define DPORT_IMMU_TABLE10_S 0
+
+#define IMMU_TABLE11 (DR_REG_DPORT_BASE + 0x530)
+#define DPORT_IMMU_TABLE11 0x0000007F
+#define DPORT_IMMU_TABLE11_S 0
+
+#define IMMU_TABLE12 (DR_REG_DPORT_BASE + 0x534)
+#define DPORT_IMMU_TABLE12 0x0000007F
+#define DPORT_IMMU_TABLE12_S 0
+
+#define IMMU_TABLE13 (DR_REG_DPORT_BASE + 0x538)
+#define DPORT_IMMU_TABLE13 0x0000007F
+#define DPORT_IMMU_TABLE13_S 0
+
+#define IMMU_TABLE14 (DR_REG_DPORT_BASE + 0x53C)
+#define DPORT_IMMU_TABLE14 0x0000007F
+#define DPORT_IMMU_TABLE14_S 0
+
+#define IMMU_TABLE15 (DR_REG_DPORT_BASE + 0x540)
+#define DPORT_IMMU_TABLE15 0x0000007F
+#define DPORT_IMMU_TABLE15_S 0
+
+#define DMMU_TABLE0 (DR_REG_DPORT_BASE + 0x544)
+#define DPORT_DMMU_TABLE0 0x0000007F
+#define DPORT_DMMU_TABLE0_S 0
+
+#define DMMU_TABLE1 (DR_REG_DPORT_BASE + 0x548)
+#define DPORT_DMMU_TABLE1 0x0000007F
+#define DPORT_DMMU_TABLE1_S 0
+
+#define DMMU_TABLE2 (DR_REG_DPORT_BASE + 0x54C)
+#define DPORT_DMMU_TABLE2 0x0000007F
+#define DPORT_DMMU_TABLE2_S 0
+
+#define DMMU_TABLE3 (DR_REG_DPORT_BASE + 0x550)
+#define DPORT_DMMU_TABLE3 0x0000007F
+#define DPORT_DMMU_TABLE3_S 0
+
+#define DMMU_TABLE4 (DR_REG_DPORT_BASE + 0x554)
+#define DPORT_DMMU_TABLE4 0x0000007F
+#define DPORT_DMMU_TABLE4_S 0
+
+#define DMMU_TABLE5 (DR_REG_DPORT_BASE + 0x558)
+#define DPORT_DMMU_TABLE5 0x0000007F
+#define DPORT_DMMU_TABLE5_S 0
+
+#define DMMU_TABLE6 (DR_REG_DPORT_BASE + 0x55C)
+#define DPORT_DMMU_TABLE6 0x0000007F
+#define DPORT_DMMU_TABLE6_S 0
+
+#define DMMU_TABLE7 (DR_REG_DPORT_BASE + 0x560)
+#define DPORT_DMMU_TABLE7 0x0000007F
+#define DPORT_DMMU_TABLE7_S 0
+
+#define DMMU_TABLE8 (DR_REG_DPORT_BASE + 0x564)
+#define DPORT_DMMU_TABLE8 0x0000007F
+#define DPORT_DMMU_TABLE8_S 0
+
+#define DMMU_TABLE9 (DR_REG_DPORT_BASE + 0x568)
+#define DPORT_DMMU_TABLE9 0x0000007F
+#define DPORT_DMMU_TABLE9_S 0
+
+#define DMMU_TABLE10 (DR_REG_DPORT_BASE + 0x56C)
+#define DPORT_DMMU_TABLE10 0x0000007F
+#define DPORT_DMMU_TABLE10_S 0
+
+#define DMMU_TABLE11 (DR_REG_DPORT_BASE + 0x570)
+#define DPORT_DMMU_TABLE11 0x0000007F
+#define DPORT_DMMU_TABLE11_S 0
+
+#define DMMU_TABLE12 (DR_REG_DPORT_BASE + 0x574)
+#define DPORT_DMMU_TABLE12 0x0000007F
+#define DPORT_DMMU_TABLE12_S 0
+
+#define DMMU_TABLE13 (DR_REG_DPORT_BASE + 0x578)
+#define DPORT_DMMU_TABLE13 0x0000007F
+#define DPORT_DMMU_TABLE13_S 0
+
+#define DMMU_TABLE14 (DR_REG_DPORT_BASE + 0x57C)
+#define DPORT_DMMU_TABLE14 0x0000007F
+#define DPORT_DMMU_TABLE14_S 0
+
+#define DMMU_TABLE15 (DR_REG_DPORT_BASE + 0x580)
+#define DPORT_DMMU_TABLE15 0x0000007F
+#define DPORT_DMMU_TABLE15_S 0
+
+#define PRO_INTRUSION_CTRL (DR_REG_DPORT_BASE + 0x584)
+#define DPORT_PRO_INTRUSION_RECORD_RESET_N (BIT(0))
+#define DPORT_PRO_INTRUSION_RECORD_RESET_N_S 0
+
+#define PRO_INTRUSION_STATUS (DR_REG_DPORT_BASE + 0x588)
+#define DPORT_PRO_INTRUSION_RECORD 0x0000000F
+#define DPORT_PRO_INTRUSION_RECORD_S 0
+
+#define APP_INTRUSION_CTRL (DR_REG_DPORT_BASE + 0x58C)
+#define DPORT_APP_INTRUSION_RECORD_RESET_N (BIT(0))
+#define DPORT_APP_INTRUSION_RECORD_RESET_N_S 0
+
+#define APP_INTRUSION_STATUS (DR_REG_DPORT_BASE + 0x590)
+#define DPORT_APP_INTRUSION_RECORD 0x0000000F
+#define DPORT_APP_INTRUSION_RECORD_S 0
+
+#define FRONT_END_MEM_PD (DR_REG_DPORT_BASE + 0x594)
+#define DPORT_PBUS_MEM_FORCE_PD (BIT(3))
+#define DPORT_PBUS_MEM_FORCE_PD_S 3
+#define DPORT_PBUS_MEM_FORCE_PU (BIT(2))
+#define DPORT_PBUS_MEM_FORCE_PU_S 2
+#define DPORT_AGC_MEM_FORCE_PD (BIT(1))
+#define DPORT_AGC_MEM_FORCE_PD_S 1
+#define DPORT_AGC_MEM_FORCE_PU (BIT(0))
+#define DPORT_AGC_MEM_FORCE_PU_S 0
+
+#define MMU_IA_INT_EN (DR_REG_DPORT_BASE + 0x598)
+#define DPORT_MMU_IA_INT_EN 0x00FFFFFF
+#define DPORT_MMU_IA_INT_EN_S 0
+
+#define MPU_IA_INT_EN (DR_REG_DPORT_BASE + 0x59C)
+#define DPORT_MPU_IA_INT_EN 0x0001FFFF
+#define DPORT_MPU_IA_INT_EN_S 0
+
+#define CACHE_IA_INT_EN (DR_REG_DPORT_BASE + 0x5A0)
+#define DPORT_CACHE_IA_INT_EN 0x0FFFFFFF
+#define DPORT_CACHE_IA_INT_EN_S 0
+
+#define SECURE_BOOT_CTRL (DR_REG_DPORT_BASE + 0x5A4)
+#define DPORT_SW_BOOTLOADER_SEL (BIT(0))
+#define DPORT_SW_BOOTLOADER_SEL_S 0
+
+#define SPI_DMA_CHAN_SEL (DR_REG_DPORT_BASE + 0x5A8)
+#define DPORT_SPI3_DMA_CHAN_SEL 0x00000003
+#define DPORT_SPI3_DMA_CHAN_SEL_S 4
+#define DPORT_SPI2_DMA_CHAN_SEL 0x00000003
+#define DPORT_SPI2_DMA_CHAN_SEL_S 2
+#define DPORT_SPI1_DMA_CHAN_SEL 0x00000003
+#define DPORT_SPI1_DMA_CHAN_SEL_S 0
+
+#define PRO_VECBASE_CTRL (DR_REG_DPORT_BASE + 0x5AC)
+#define DPORT_PRO_OUT_VECBASE_SEL 0x00000003
+#define DPORT_PRO_OUT_VECBASE_SEL_S 0
+
+#define PRO_VECBASE_SET (DR_REG_DPORT_BASE + 0x5B0)
+#define DPORT_PRO_OUT_VECBASE_REG 0x003FFFFF
+#define DPORT_PRO_OUT_VECBASE_REG_S 0
+
+#define APP_VECBASE_CTRL (DR_REG_DPORT_BASE + 0x5B4)
+#define DPORT_APP_OUT_VECBASE_SEL 0x00000003
+#define DPORT_APP_OUT_VECBASE_SEL_S 0
+
+#define APP_VECBASE_SET (DR_REG_DPORT_BASE + 0x5B8)
+#define DPORT_APP_OUT_VECBASE_REG 0x003FFFFF
+#define DPORT_APP_OUT_VECBASE_REG_S 0
+
+#define DPORT_REG_DATE (DR_REG_DPORT_BASE + 0xFFC)
+#define DPORT_DPORT_DATE 0x0FFFFFFF
+#define DPORT_DPORT_DATE_S 0
+#define DPORT_DPORT_DATE_VERSION 0x1605190
+
+#endif /* _SOC_DPORT_REG_H_ */

components/esp32/include/soc/efuse_reg.h

@@ -0,0 +1,422 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_EFUSE_REG_H_
+#define _SOC_EFUSE_REG_H_
+
+#include "soc.h"
+
+#define EFUSE_BLK0_RDATA0 (DR_REG_EFUSE_BASE + 0x000)
+#define EFUSE_RD_FLASH_CRYPT_CNT 0x000000FF
+#define EFUSE_RD_FLASH_CRYPT_CNT_S 20
+#define EFUSE_RD_EFUSE_RD_DIS 0x0000000F
+#define EFUSE_RD_EFUSE_RD_DIS_S 16
+#define EFUSE_RD_EFUSE_WR_DIS 0x0000FFFF
+#define EFUSE_RD_EFUSE_WR_DIS_S 0
+
+#define EFUSE_BLK0_RDATA1 (DR_REG_EFUSE_BASE + 0x004)
+#define EFUSE_RD_WIFI_MAC_CRC_LOW 0xFFFFFFFF
+#define EFUSE_RD_WIFI_MAC_CRC_LOW_S 0
+
+#define EFUSE_BLK0_RDATA2 (DR_REG_EFUSE_BASE + 0x008)
+#define EFUSE_RD_WIFI_MAC_CRC_HIGH 0x00FFFFFF
+#define EFUSE_RD_WIFI_MAC_CRC_HIGH_S 0
+
+#define EFUSE_BLK0_RDATA3 (DR_REG_EFUSE_BASE + 0x00c)
+#define EFUSE_RD_CHIP_VER_RESERVE 0x00001FFF
+#define EFUSE_RD_CHIP_VER_RESERVE_S 4
+#define EFUSE_RD_CHIP_VER_DIS_CACHE (BIT(3))
+#define EFUSE_RD_CHIP_VER_DIS_CACHE_S 3
+#define EFUSE_RD_CHIP_VER_32PAD (BIT(2))
+#define EFUSE_RD_CHIP_VER_32PAD_S 2
+#define EFUSE_RD_CHIP_VER_DIS_BT (BIT(1))
+#define EFUSE_RD_CHIP_VER_DIS_BT_S 1
+#define EFUSE_RD_CHIP_VER_DIS_APP_CPU (BIT(0))
+#define EFUSE_RD_CHIP_VER_DIS_APP_CPU_S 0
+
+#define EFUSE_BLK0_RDATA4 (DR_REG_EFUSE_BASE + 0x010)
+#define EFUSE_RD_SDIO_FORCE (BIT(16))
+#define EFUSE_RD_SDIO_FORCE_S 16
+#define EFUSE_RD_SDIO_TIEH (BIT(15))
+#define EFUSE_RD_SDIO_TIEH_S 15
+#define EFUSE_RD_XPD_SDIO_REG (BIT(14))
+#define EFUSE_RD_XPD_SDIO_REG_S 14
+#define EFUSE_RD_SDIO_DREFL 0x00000003
+#define EFUSE_RD_SDIO_DREFL_S 12
+#define EFUSE_RD_SDIO_DREFM 0x00000003
+#define EFUSE_RD_SDIO_DREFM_S 10
+#define EFUSE_RD_SDIO_DREFH 0x00000003
+#define EFUSE_RD_SDIO_DREFH_S 8
+#define EFUSE_RD_CK8M_FREQ 0x000000FF
+#define EFUSE_RD_CK8M_FREQ_S 0
+
+#define EFUSE_BLK0_RDATA5 (DR_REG_EFUSE_BASE + 0x014)
+#define EFUSE_RD_FLASH_CRYPT_CONFIG 0x0000000F
+#define EFUSE_RD_FLASH_CRYPT_CONFIG_S 28
+#define EFUSE_RD_INST_CONFIG 0x000000FF
+#define EFUSE_RD_INST_CONFIG_S 20
+#define EFUSE_RD_SPI_PAD_CONFIG 0x000FFFFF
+#define EFUSE_RD_SPI_PAD_CONFIG_S 0
+
+#define EFUSE_BLK0_RDATA6 (DR_REG_EFUSE_BASE + 0x018)
+#define EFUSE_RD_KEY_STATUS (BIT(10))
+#define EFUSE_RD_KEY_STATUS_S 10
+#define EFUSE_RD_DISABLE_DL_CACHE (BIT(9))
+#define EFUSE_RD_DISABLE_DL_CACHE_S 9
+#define EFUSE_RD_DISABLE_DL_DECRYPT (BIT(8))
+#define EFUSE_RD_DISABLE_DL_DECRYPT_S 8
+#define EFUSE_RD_DISABLE_DL_ENCRYPT (BIT(7))
+#define EFUSE_RD_DISABLE_DL_ENCRYPT_S 7
+#define EFUSE_RD_DISABLE_JTAG (BIT(6))
+#define EFUSE_RD_DISABLE_JTAG_S 6
+#define EFUSE_RD_ABS_DONE_1 (BIT(5))
+#define EFUSE_RD_ABS_DONE_1_S 5
+#define EFUSE_RD_ABS_DONE_0 (BIT(4))
+#define EFUSE_RD_ABS_DONE_0_S 4
+#define EFUSE_RD_DISABLE_SDIO_HOST (BIT(3))
+#define EFUSE_RD_DISABLE_SDIO_HOST_S 3
+#define EFUSE_RD_DIG_RESERVE (BIT(2))
+#define EFUSE_RD_DIG_RESERVE_S 2
+#define EFUSE_RD_CODING_SCHEME 0x00000003
+#define EFUSE_RD_CODING_SCHEME_S 0
+
+#define EFUSE_BLK0_WDATA0 (DR_REG_EFUSE_BASE + 0x01c)
+#define EFUSE_FLASH_CRYPT_CNT 0x000000FF
+#define EFUSE_FLASH_CRYPT_CNT_S 20
+#define EFUSE_EFUSE_RD_DIS 0x0000000F
+#define EFUSE_EFUSE_RD_DIS_S 16
+#define EFUSE_EFUSE_WR_DIS 0x0000FFFF
+#define EFUSE_EFUSE_WR_DIS_S 0
+
+#define EFUSE_BLK0_WDATA1 (DR_REG_EFUSE_BASE + 0x020)
+#define EFUSE_WIFI_MAC_CRC_LOW 0xFFFFFFFF
+#define EFUSE_WIFI_MAC_CRC_LOW_S 0
+
+#define EFUSE_BLK0_WDATA2 (DR_REG_EFUSE_BASE + 0x024)
+#define EFUSE_WIFI_MAC_CRC_HIGH 0x00FFFFFF
+#define EFUSE_WIFI_MAC_CRC_HIGH_S 0
+
+#define EFUSE_BLK0_WDATA3 (DR_REG_EFUSE_BASE + 0x028)
+#define EFUSE_CHIP_VER_RESERVE 0x00001FFF
+#define EFUSE_CHIP_VER_RESERVE_S 4
+#define EFUSE_CHIP_VER_DIS_CACHE (BIT(3))
+#define EFUSE_CHIP_VER_DIS_CACHE_S 3
+#define EFUSE_CHIP_VER_32PAD (BIT(2))
+#define EFUSE_CHIP_VER_32PAD_S 2
+#define EFUSE_CHIP_VER_DIS_BT (BIT(1))
+#define EFUSE_CHIP_VER_DIS_BT_S 1
+#define EFUSE_CHIP_VER_DIS_APP_CPU (BIT(0))
+#define EFUSE_CHIP_VER_DIS_APP_CPU_S 0
+
+#define EFUSE_BLK0_WDATA4 (DR_REG_EFUSE_BASE + 0x02c)
+#define EFUSE_SDIO_FORCE (BIT(16))
+#define EFUSE_SDIO_FORCE_S 16
+#define EFUSE_SDIO_TIEH (BIT(15))
+#define EFUSE_SDIO_TIEH_S 15
+#define EFUSE_XPD_SDIO_REG (BIT(14))
+#define EFUSE_XPD_SDIO_REG_S 14
+#define EFUSE_SDIO_DREFL 0x00000003
+#define EFUSE_SDIO_DREFL_S 12
+#define EFUSE_SDIO_DREFM 0x00000003
+#define EFUSE_SDIO_DREFM_S 10
+#define EFUSE_SDIO_DREFH 0x00000003
+#define EFUSE_SDIO_DREFH_S 8
+#define EFUSE_CK8M_FREQ 0x000000FF
+#define EFUSE_CK8M_FREQ_S 0
+
+#define EFUSE_BLK0_WDATA5 (DR_REG_EFUSE_BASE + 0x030)
+#define EFUSE_FLASH_CRYPT_CONFIG 0x0000000F
+#define EFUSE_FLASH_CRYPT_CONFIG_S 28
+#define EFUSE_INST_CONFIG 0x000000FF
+#define EFUSE_INST_CONFIG_S 20
+#define EFUSE_SPI_PAD_CONFIG 0x000FFFFF
+#define EFUSE_SPI_PAD_CONFIG_S 0
+
+#define EFUSE_BLK0_WDATA6 (DR_REG_EFUSE_BASE + 0x034)
+#define EFUSE_KEY_STATUS (BIT(10))
+#define EFUSE_KEY_STATUS_S 10
+#define EFUSE_DISABLE_DL_CACHE (BIT(9))
+#define EFUSE_DISABLE_DL_CACHE_S 9
+#define EFUSE_DISABLE_DL_DECRYPT (BIT(8))
+#define EFUSE_DISABLE_DL_DECRYPT_S 8
+#define EFUSE_DISABLE_DL_ENCRYPT (BIT(7))
+#define EFUSE_DISABLE_DL_ENCRYPT_S 7
+#define EFUSE_DISABLE_JTAG (BIT(6))
+#define EFUSE_DISABLE_JTAG_S 6
+#define EFUSE_ABS_DONE_1 (BIT(5))
+#define EFUSE_ABS_DONE_1_S 5
+#define EFUSE_ABS_DONE_0 (BIT(4))
+#define EFUSE_ABS_DONE_0_S 4
+#define EFUSE_DISABLE_SDIO_HOST (BIT(3))
+#define EFUSE_DISABLE_SDIO_HOST_S 3
+#define EFUSE_DIG_RESERVE (BIT(2))
+#define EFUSE_DIG_RESERVE_S 2
+#define EFUSE_CODING_SCHEME 0x00000003
+#define EFUSE_CODING_SCHEME_S 0
+
+#define EFUSE_BLK1_RDATA0 (DR_REG_EFUSE_BASE + 0x038)
+#define EFUSE_EFUSE_BLK1_DOUT0 0xFFFFFFFF
+#define EFUSE_EFUSE_BLK1_DOUT0_S 0
+
+#define EFUSE_BLK1_RDATA1 (DR_REG_EFUSE_BASE + 0x03c)
+#define EFUSE_EFUSE_BLK1_DOUT1 0xFFFFFFFF
+#define EFUSE_EFUSE_BLK1_DOUT1_S 0
+
+#define EFUSE_BLK1_RDATA2 (DR_REG_EFUSE_BASE + 0x040)
+#define EFUSE_EFUSE_BLK1_DOUT2 0xFFFFFFFF
+#define EFUSE_EFUSE_BLK1_DOUT2_S 0
+
+#define EFUSE_BLK1_RDATA3 (DR_REG_EFUSE_BASE + 0x044)
+#define EFUSE_EFUSE_BLK1_DOUT3 0xFFFFFFFF
+#define EFUSE_EFUSE_BLK1_DOUT3_S 0
+
+#define EFUSE_BLK1_RDATA4 (DR_REG_EFUSE_BASE + 0x048)
+#define EFUSE_EFUSE_BLK1_DOUT4 0xFFFFFFFF
+#define EFUSE_EFUSE_BLK1_DOUT4_S 0
+
+#define EFUSE_BLK1_RDATA5 (DR_REG_EFUSE_BASE + 0x04c)
+#define EFUSE_EFUSE_BLK1_DOUT5 0xFFFFFFFF
+#define EFUSE_EFUSE_BLK1_DOUT5_S 0
+
+#define EFUSE_BLK1_RDATA6 (DR_REG_EFUSE_BASE + 0x050)
+#define EFUSE_EFUSE_BLK1_DOUT6 0xFFFFFFFF
+#define EFUSE_EFUSE_BLK1_DOUT6_S 0
+
+#define EFUSE_BLK1_RDATA7 (DR_REG_EFUSE_BASE + 0x054)
+#define EFUSE_EFUSE_BLK1_DOUT7 0xFFFFFFFF
+#define EFUSE_EFUSE_BLK1_DOUT7_S 0
+
+#define EFUSE_BLK2_RDATA0 (DR_REG_EFUSE_BASE + 0x058)
+#define EFUSE_EFUSE_BLK2_DOUT0 0xFFFFFFFF
+#define EFUSE_EFUSE_BLK2_DOUT0_S 0
+
+#define EFUSE_BLK2_RDATA1 (DR_REG_EFUSE_BASE + 0x05c)
+#define EFUSE_EFUSE_BLK2_DOUT1 0xFFFFFFFF
+#define EFUSE_EFUSE_BLK2_DOUT1_S 0
+
+#define EFUSE_BLK2_RDATA2 (DR_REG_EFUSE_BASE + 0x060)
+#define EFUSE_EFUSE_BLK2_DOUT2 0xFFFFFFFF
+#define EFUSE_EFUSE_BLK2_DOUT2_S 0
+
+#define EFUSE_BLK2_RDATA3 (DR_REG_EFUSE_BASE + 0x064)
+#define EFUSE_EFUSE_BLK2_DOUT3 0xFFFFFFFF
+#define EFUSE_EFUSE_BLK2_DOUT3_S 0
+
+#define EFUSE_BLK2_RDATA4 (DR_REG_EFUSE_BASE + 0x068)
+#define EFUSE_EFUSE_BLK2_DOUT4 0xFFFFFFFF
+#define EFUSE_EFUSE_BLK2_DOUT4_S 0
+
+#define EFUSE_BLK2_RDATA5 (DR_REG_EFUSE_BASE + 0x06c)
+#define EFUSE_EFUSE_BLK2_DOUT5 0xFFFFFFFF
+#define EFUSE_EFUSE_BLK2_DOUT5_S 0
+
+#define EFUSE_BLK2_RDATA6 (DR_REG_EFUSE_BASE + 0x070)
+#define EFUSE_EFUSE_BLK2_DOUT6 0xFFFFFFFF
+#define EFUSE_EFUSE_BLK2_DOUT6_S 0
+
+#define EFUSE_BLK2_RDATA7 (DR_REG_EFUSE_BASE + 0x074)
+#define EFUSE_EFUSE_BLK2_DOUT7 0xFFFFFFFF
+#define EFUSE_EFUSE_BLK2_DOUT7_S 0
+
+#define EFUSE_BLK3_RDATA0 (DR_REG_EFUSE_BASE + 0x078)
+#define EFUSE_EFUSE_BLK3_DOUT0 0xFFFFFFFF
+#define EFUSE_EFUSE_BLK3_DOUT0_S 0
+
+#define EFUSE_BLK3_RDATA1 (DR_REG_EFUSE_BASE + 0x07c)
+#define EFUSE_EFUSE_BLK3_DOUT1 0xFFFFFFFF
+#define EFUSE_EFUSE_BLK3_DOUT1_S 0
+
+#define EFUSE_BLK3_RDATA2 (DR_REG_EFUSE_BASE + 0x080)
+#define EFUSE_EFUSE_BLK3_DOUT2 0xFFFFFFFF
+#define EFUSE_EFUSE_BLK3_DOUT2_S 0
+
+#define EFUSE_BLK3_RDATA3 (DR_REG_EFUSE_BASE + 0x084)
+#define EFUSE_EFUSE_BLK3_DOUT3 0xFFFFFFFF
+#define EFUSE_EFUSE_BLK3_DOUT3_S 0
+
+#define EFUSE_BLK3_RDATA4 (DR_REG_EFUSE_BASE + 0x088)
+#define EFUSE_EFUSE_BLK3_DOUT4 0xFFFFFFFF
+#define EFUSE_EFUSE_BLK3_DOUT4_S 0
+
+#define EFUSE_BLK3_RDATA5 (DR_REG_EFUSE_BASE + 0x08c)
+#define EFUSE_EFUSE_BLK3_DOUT5 0xFFFFFFFF
+#define EFUSE_EFUSE_BLK3_DOUT5_S 0
+
+#define EFUSE_BLK3_RDATA6 (DR_REG_EFUSE_BASE + 0x090)
+#define EFUSE_EFUSE_BLK3_DOUT6 0xFFFFFFFF
+#define EFUSE_EFUSE_BLK3_DOUT6_S 0
+
+#define EFUSE_BLK3_RDATA7 (DR_REG_EFUSE_BASE + 0x094)
+#define EFUSE_EFUSE_BLK3_DOUT7 0xFFFFFFFF
+#define EFUSE_EFUSE_BLK3_DOUT7_S 0
+
+#define EFUSE_BLK1_WDATA0 (DR_REG_EFUSE_BASE + 0x098)
+#define EFUSE_EFUSE_BLK1_DIN0 0xFFFFFFFF
+#define EFUSE_EFUSE_BLK1_DIN0_S 0
+
+#define EFUSE_BLK1_WDATA1 (DR_REG_EFUSE_BASE + 0x09c)
+#define EFUSE_EFUSE_BLK1_DIN1 0xFFFFFFFF
+#define EFUSE_EFUSE_BLK1_DIN1_S 0
+
+#define EFUSE_BLK1_WDATA2 (DR_REG_EFUSE_BASE + 0x0a0)
+#define EFUSE_EFUSE_BLK1_DIN2 0xFFFFFFFF
+#define EFUSE_EFUSE_BLK1_DIN2_S 0
+
+#define EFUSE_BLK1_WDATA3 (DR_REG_EFUSE_BASE + 0x0a4)
+#define EFUSE_EFUSE_BLK1_DIN3 0xFFFFFFFF
+#define EFUSE_EFUSE_BLK1_DIN3_S 0
+
+#define EFUSE_BLK1_WDATA4 (DR_REG_EFUSE_BASE + 0x0a8)
+#define EFUSE_EFUSE_BLK1_DIN4 0xFFFFFFFF
+#define EFUSE_EFUSE_BLK1_DIN4_S 0
+
+#define EFUSE_BLK1_WDATA5 (DR_REG_EFUSE_BASE + 0x0ac)
+#define EFUSE_EFUSE_BLK1_DIN5 0xFFFFFFFF
+#define EFUSE_EFUSE_BLK1_DIN5_S 0
+
+#define EFUSE_BLK1_WDATA6 (DR_REG_EFUSE_BASE + 0x0b0)
+#define EFUSE_EFUSE_BLK1_DIN6 0xFFFFFFFF
+#define EFUSE_EFUSE_BLK1_DIN6_S 0
+
+#define EFUSE_BLK1_WDATA7 (DR_REG_EFUSE_BASE + 0x0b4)
+#define EFUSE_EFUSE_BLK1_DIN7 0xFFFFFFFF
+#define EFUSE_EFUSE_BLK1_DIN7_S 0
+
+#define EFUSE_BLK2_WDATA0 (DR_REG_EFUSE_BASE + 0x0b8)
+#define EFUSE_EFUSE_BLK2_DIN0 0xFFFFFFFF
+#define EFUSE_EFUSE_BLK2_DIN0_S 0
+
+#define EFUSE_BLK2_WDATA1 (DR_REG_EFUSE_BASE + 0x0bc)
+#define EFUSE_EFUSE_BLK2_DIN1 0xFFFFFFFF
+#define EFUSE_EFUSE_BLK2_DIN1_S 0
+
+#define EFUSE_BLK2_WDATA2 (DR_REG_EFUSE_BASE + 0x0c0)
+#define EFUSE_EFUSE_BLK2_DIN2 0xFFFFFFFF
+#define EFUSE_EFUSE_BLK2_DIN2_S 0
+
+#define EFUSE_BLK2_WDATA3 (DR_REG_EFUSE_BASE + 0x0c4)
+#define EFUSE_EFUSE_BLK2_DIN3 0xFFFFFFFF
+#define EFUSE_EFUSE_BLK2_DIN3_S 0
+
+#define EFUSE_BLK2_WDATA4 (DR_REG_EFUSE_BASE + 0x0c8)
+#define EFUSE_EFUSE_BLK2_DIN4 0xFFFFFFFF
+#define EFUSE_EFUSE_BLK2_DIN4_S 0
+
+#define EFUSE_BLK2_WDATA5 (DR_REG_EFUSE_BASE + 0x0cc)
+#define EFUSE_EFUSE_BLK2_DIN5 0xFFFFFFFF
+#define EFUSE_EFUSE_BLK2_DIN5_S 0
+
+#define EFUSE_BLK2_WDATA6 (DR_REG_EFUSE_BASE + 0x0d0)
+#define EFUSE_EFUSE_BLK2_DIN6 0xFFFFFFFF
+#define EFUSE_EFUSE_BLK2_DIN6_S 0
+
+#define EFUSE_BLK2_WDATA7 (DR_REG_EFUSE_BASE + 0x0d4)
+#define EFUSE_EFUSE_BLK2_DIN7 0xFFFFFFFF
+#define EFUSE_EFUSE_BLK2_DIN7_S 0
+
+#define EFUSE_BLK3_WDATA0 (DR_REG_EFUSE_BASE + 0x0d8)
+#define EFUSE_EFUSE_BLK3_DIN0 0xFFFFFFFF
+#define EFUSE_EFUSE_BLK3_DIN0_S 0
+
+#define EFUSE_BLK3_WDATA1 (DR_REG_EFUSE_BASE + 0x0dc)
+#define EFUSE_EFUSE_BLK3_DIN1 0xFFFFFFFF
+#define EFUSE_EFUSE_BLK3_DIN1_S 0
+
+#define EFUSE_BLK3_WDATA2 (DR_REG_EFUSE_BASE + 0x0e0)
+#define EFUSE_EFUSE_BLK3_DIN2 0xFFFFFFFF
+#define EFUSE_EFUSE_BLK3_DIN2_S 0
+
+#define EFUSE_BLK3_WDATA3 (DR_REG_EFUSE_BASE + 0x0e4)
+#define EFUSE_EFUSE_BLK3_DIN3 0xFFFFFFFF
+#define EFUSE_EFUSE_BLK3_DIN3_S 0
+
+#define EFUSE_BLK3_WDATA4 (DR_REG_EFUSE_BASE + 0x0e8)
+#define EFUSE_EFUSE_BLK3_DIN4 0xFFFFFFFF
+#define EFUSE_EFUSE_BLK3_DIN4_S 0
+
+#define EFUSE_BLK3_WDATA5 (DR_REG_EFUSE_BASE + 0x0ec)
+#define EFUSE_EFUSE_BLK3_DIN5 0xFFFFFFFF
+#define EFUSE_EFUSE_BLK3_DIN5_S 0
+
+#define EFUSE_BLK3_WDATA6 (DR_REG_EFUSE_BASE + 0x0f0)
+#define EFUSE_EFUSE_BLK3_DIN6 0xFFFFFFFF
+#define EFUSE_EFUSE_BLK3_DIN6_S 0
+
+#define EFUSE_BLK3_WDATA7 (DR_REG_EFUSE_BASE + 0x0f4)
+#define EFUSE_EFUSE_BLK3_DIN7 0xFFFFFFFF
+#define EFUSE_EFUSE_BLK3_DIN7_S 0
+
+#define EFUSE_CLK (DR_REG_EFUSE_BASE + 0x0f8)
+#define EFUSE_CLK_EN (BIT(16))
+#define EFUSE_CLK_EN_S 16
+#define EFUSE_EFUSE_CLK_SEL1 0x000000FF
+#define EFUSE_EFUSE_CLK_SEL1_S 8
+#define EFUSE_EFUSE_CLK_SEL0 0x000000FF
+#define EFUSE_EFUSE_CLK_SEL0_S 0
+
+#define EFUSE_CONF (DR_REG_EFUSE_BASE + 0x0fc)
+#define EFUSE_EFUSE_FORCE_NO_WR_RD_DIS (BIT(16))
+#define EFUSE_EFUSE_FORCE_NO_WR_RD_DIS_S 16
+#define EFUSE_EFUSE_OP_CODE 0x0000FFFF
+#define EFUSE_EFUSE_OP_CODE_S 0
+
+#define EFUSE_STATUS (DR_REG_EFUSE_BASE + 0x100)
+#define EFUSE_EFUSE_DEBUG 0xFFFFFFFF
+#define EFUSE_EFUSE_DEBUG_S 0
+
+#define EFUSE_CMD (DR_REG_EFUSE_BASE + 0x104)
+#define EFUSE_EFUSE_PGM_CMD (BIT(1))
+#define EFUSE_EFUSE_PGM_CMD_S 1
+#define EFUSE_EFUSE_READ_CMD (BIT(0))
+#define EFUSE_EFUSE_READ_CMD_S 0
+
+#define EFUSE_INT_RAW (DR_REG_EFUSE_BASE + 0x108)
+#define EFUSE_EFUSE_PGM_DONE_INT_RAW (BIT(1))
+#define EFUSE_EFUSE_PGM_DONE_INT_RAW_S 1
+#define EFUSE_EFUSE_READ_DONE_INT_RAW (BIT(0))
+#define EFUSE_EFUSE_READ_DONE_INT_RAW_S 0
+
+#define EFUSE_INT_ST (DR_REG_EFUSE_BASE + 0x10c)
+#define EFUSE_EFUSE_PGM_DONE_INT_ST (BIT(1))
+#define EFUSE_EFUSE_PGM_DONE_INT_ST_S 1
+#define EFUSE_EFUSE_READ_DONE_INT_ST (BIT(0))
+#define EFUSE_EFUSE_READ_DONE_INT_ST_S 0
+
+#define EFUSE_INT_ENA (DR_REG_EFUSE_BASE + 0x110)
+#define EFUSE_EFUSE_PGM_DONE_INT_ENA (BIT(1))
+#define EFUSE_EFUSE_PGM_DONE_INT_ENA_S 1
+#define EFUSE_EFUSE_READ_DONE_INT_ENA (BIT(0))
+#define EFUSE_EFUSE_READ_DONE_INT_ENA_S 0
+
+#define EFUSE_INT_CLR (DR_REG_EFUSE_BASE + 0x114)
+#define EFUSE_EFUSE_PGM_DONE_INT_CLR (BIT(1))
+#define EFUSE_EFUSE_PGM_DONE_INT_CLR_S 1
+#define EFUSE_EFUSE_READ_DONE_INT_CLR (BIT(0))
+#define EFUSE_EFUSE_READ_DONE_INT_CLR_S 0
+
+#define EFUSE_DAC_CONF (DR_REG_EFUSE_BASE + 0x118)
+#define EFUSE_EFUSE_DAC_CLK_PAD_SEL (BIT(8))
+#define EFUSE_EFUSE_DAC_CLK_PAD_SEL_S 8
+#define EFUSE_EFUSE_DAC_CLK_DIV 0x000000FF
+#define EFUSE_EFUSE_DAC_CLK_DIV_S 0
+
+#define EFUSE_DEC_STATUS (DR_REG_EFUSE_BASE + 0x11c)
+#define EFUSE_EFUSE_DEC_WARNINGS 0x00000FFF
+#define EFUSE_EFUSE_DEC_WARNINGS_S 0
+
+#define EFUSE_DATE (DR_REG_EFUSE_BASE + 0x1FC)
+#define EFUSE_EFUSE_DATE 0xFFFFFFFF
+#define EFUSE_EFUSE_DATE_S 0
+#define EFUSE_EFUSE_DATE_VERSION 0x16042600
+
+#endif /* _SOC_EFUSE_REG_H_ */

components/esp32/include/soc/gpio_reg.h

@@ -0,0 +1,3124 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_GPIO_REG_H_
+#define _SOC_GPIO_REG_H_
+
+#include "soc.h"
+
+//for GPIO_PIN group
+#define GPIO_PIN_CONFIG_MSB			12
+#define GPIO_PIN_CONFIG_LSB                     11
+#define GPIO_PIN_CONFIG_MASK			0x00001800
+#define GPIO_PIN_CONFIG_GET(x)			(((x) & GPIO_PIN_CONFIG_MASK) >> GPIO_PIN_CONFIG_LSB)
+#define GPIO_PIN_CONFIG_SET(x)                  (((x) << GPIO_PIN_CONFIG_LSB) & GPIO_PIN_CONFIG_MASK)
+
+#define GPIO_WAKEUP_ENABLE			1
+#define GPIO_WAKEUP_DISABLE			(~GPIO_WAKEUP_ENABLE)
+#define GPIO_PIN_WAKEUP_ENABLE_MSB		10
+#define GPIO_PIN_WAKEUP_ENABLE_LSB              10
+#define GPIO_PIN_WAKEUP_ENABLE_MASK		0x00000400
+#define GPIO_PIN_WAKEUP_ENABLE_GET(x)		(((x) & GPIO_PIN_WAKEUP_ENABLE_MASK) >> GPIO_PIN_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN_WAKEUP_ENABLE_SET(x)           (((x) << GPIO_PIN_WAKEUP_ENABLE_LSB) & GPIO_PIN_WAKEUP_ENABLE_MASK)
+
+#define GPIO_PIN_INT_TYPE_MASK			0x380
+#define GPIO_PIN_INT_TYPE_MSB			9
+#define GPIO_PIN_INT_TYPE_LSB			7
+#define GPIO_PIN_INT_TYPE_GET(x)		(((x) & GPIO_PIN_INT_TYPE_MASK) >> GPIO_PIN_INT_TYPE_LSB)
+#define GPIO_PIN_INT_TYPE_SET(x)		(((x) << GPIO_PIN_INT_TYPE_LSB) & GPIO_PIN_INT_TYPE_MASK)
+
+#define GPIO_PAD_DRIVER_ENABLE			1
+#define GPIO_PAD_DRIVER_DISABLE			(~GPIO_PAD_DRIVER_ENABLE)
+#define GPIO_PIN_PAD_DRIVER_MSB			2
+#define GPIO_PIN_PAD_DRIVER_LSB			2
+#define GPIO_PIN_PAD_DRIVER_MASK		0x00000004
+#define GPIO_PIN_PAD_DRIVER_GET(x)		(((x) & GPIO_PIN_PAD_DRIVER_MASK) >> GPIO_PIN_PAD_DRIVER_LSB)
+#define GPIO_PIN_PAD_DRIVER_SET(x)		(((x) << GPIO_PIN_PAD_DRIVER_LSB) & GPIO_PIN_PAD_DRIVER_MASK)
+
+//end GPIO_PIN group
+
+#define GPIO_BT_SELECT (DR_REG_GPIO_BASE + 0x0000)
+#define GPIO_GPIO_BT_SEL 0xFFFFFFFF
+#define GPIO_GPIO_BT_SEL_S 0
+
+#define GPIO_OUT (DR_REG_GPIO_BASE + 0x0004)
+#define GPIO_GPIO_OUT_DATA 0xFFFFFFFF
+#define GPIO_GPIO_OUT_DATA_S 0
+
+#define GPIO_OUT_W1TS (DR_REG_GPIO_BASE + 0x0008)
+#define GPIO_GPIO_OUT_DATA 0xFFFFFFFF
+#define GPIO_GPIO_OUT_DATA_S 0
+
+#define GPIO_OUT_W1TC (DR_REG_GPIO_BASE + 0x000c)
+#define GPIO_GPIO_OUT_DATA 0xFFFFFFFF
+#define GPIO_GPIO_OUT_DATA_S 0
+
+#define GPIO_OUT1 (DR_REG_GPIO_BASE + 0x0010)
+#define GPIO_GPIO_OUT_DATA_H 0x000000FF
+#define GPIO_GPIO_OUT_DATA_H_S 0
+
+#define GPIO_OUT1_W1TS (DR_REG_GPIO_BASE + 0x0014)
+#define GPIO_GPIO_OUT_DATA_H 0x000000FF
+#define GPIO_GPIO_OUT_DATA_H_S 0
+
+#define GPIO_OUT1_W1TC (DR_REG_GPIO_BASE + 0x0018)
+#define GPIO_GPIO_OUT_DATA_H 0x000000FF
+#define GPIO_GPIO_OUT_DATA_H_S 0
+
+#define GPIO_SDIO_SELECT (DR_REG_GPIO_BASE + 0x001c)
+#define GPIO_GPIO_SDIO_SEL 0x000000FF
+#define GPIO_GPIO_SDIO_SEL_S 0
+
+#define GPIO_ENABLE (DR_REG_GPIO_BASE + 0x0020)
+#define GPIO_GPIO_ENABLE_DATA 0xFFFFFFFF
+#define GPIO_GPIO_ENABLE_DATA_S 0
+
+#define GPIO_ENABLE_W1TS (DR_REG_GPIO_BASE + 0x0024)
+#define GPIO_GPIO_ENABLE_DATA 0xFFFFFFFF
+#define GPIO_GPIO_ENABLE_DATA_S 0
+
+#define GPIO_ENABLE_W1TC (DR_REG_GPIO_BASE + 0x0028)
+#define GPIO_GPIO_ENABLE_DATA 0xFFFFFFFF
+#define GPIO_GPIO_ENABLE_DATA_S 0
+
+#define GPIO_ENABLE1 (DR_REG_GPIO_BASE + 0x002c)
+#define GPIO_GPIO_ENABLE_DATA_H 0x000000FF
+#define GPIO_GPIO_ENABLE_DATA_H_S 0
+
+#define GPIO_ENABLE1_W1TS (DR_REG_GPIO_BASE + 0x0030)
+#define GPIO_GPIO_ENABLE_DATA_H 0x000000FF
+#define GPIO_GPIO_ENABLE_DATA_H_S 0
+
+#define GPIO_ENABLE1_W1TC (DR_REG_GPIO_BASE + 0x0034)
+#define GPIO_GPIO_ENABLE_DATA_H 0x000000FF
+#define GPIO_GPIO_ENABLE_DATA_H_S 0
+
+#define GPIO_STRAP (DR_REG_GPIO_BASE + 0x0038)
+#define GPIO_GPIO_STRAPPING 0x0000FFFF
+#define GPIO_GPIO_STRAPPING_S 0
+
+#define GPIO_IN (DR_REG_GPIO_BASE + 0x003c)
+#define GPIO_GPIO_IN_DATA_NEXT 0xFFFFFFFF
+#define GPIO_GPIO_IN_DATA_NEXT_S 0
+
+#define GPIO_IN1 (DR_REG_GPIO_BASE + 0x0040)
+#define GPIO_GPIO_IN_DATA_NEXT_H 0x000000FF
+#define GPIO_GPIO_IN_DATA_NEXT_H_S 0
+
+#define GPIO_STATUS (DR_REG_GPIO_BASE + 0x0044)
+#define GPIO_GPIO_STATUS_INTERRUPT 0xFFFFFFFF
+#define GPIO_GPIO_STATUS_INTERRUPT_S 0
+
+#define GPIO_STATUS_W1TS (DR_REG_GPIO_BASE + 0x0048)
+#define GPIO_GPIO_STATUS_INTERRUPT 0xFFFFFFFF
+#define GPIO_GPIO_STATUS_INTERRUPT_S 0
+
+#define GPIO_STATUS_W1TC (DR_REG_GPIO_BASE + 0x004c)
+#define GPIO_GPIO_STATUS_INTERRUPT 0xFFFFFFFF
+#define GPIO_GPIO_STATUS_INTERRUPT_S 0
+
+#define GPIO_STATUS1 (DR_REG_GPIO_BASE + 0x0050)
+#define GPIO_GPIO_STATUS_INTERRUPT_H 0x000000FF
+#define GPIO_GPIO_STATUS_INTERRUPT_H_S 0
+
+#define GPIO_STATUS1_W1TS (DR_REG_GPIO_BASE + 0x0054)
+#define GPIO_GPIO_STATUS_INTERRUPT_H 0x000000FF
+#define GPIO_GPIO_STATUS_INTERRUPT_H_S 0
+
+#define GPIO_STATUS1_W1TC (DR_REG_GPIO_BASE + 0x0058)
+#define GPIO_GPIO_STATUS_INTERRUPT_H 0x000000FF
+#define GPIO_GPIO_STATUS_INTERRUPT_H_S 0
+
+#define GPIO_ACPU_INT (DR_REG_GPIO_BASE + 0x0060)
+#define GPIO_GPIO_APPCPU_INT 0xFFFFFFFF
+#define GPIO_GPIO_APPCPU_INT_S 0
+
+#define GPIO_ACPU_NMI_INT (DR_REG_GPIO_BASE + 0x0064)
+#define GPIO_GPIO_APPCPU_NMI_INT 0xFFFFFFFF
+#define GPIO_GPIO_APPCPU_NMI_INT_S 0
+
+#define GPIO_PCPU_INT (DR_REG_GPIO_BASE + 0x0068)
+#define GPIO_GPIO_PROCPU_INT 0xFFFFFFFF
+#define GPIO_GPIO_PROCPU_INT_S 0
+
+#define GPIO_PCPU_NMI_INT (DR_REG_GPIO_BASE + 0x006c)
+#define GPIO_GPIO_PROCPU_NMI_INT 0xFFFFFFFF
+#define GPIO_GPIO_PROCPU_NMI_INT_S 0
+
+#define GPIO_CPUSDIO_INT (DR_REG_GPIO_BASE + 0x0070)
+#define GPIO_GPIO_SDIO_INT 0xFFFFFFFF
+#define GPIO_GPIO_SDIO_INT_S 0
+
+#define GPIO_ACPU_INT1 (DR_REG_GPIO_BASE + 0x0074)
+#define GPIO_GPIO_APPCPU_INT_H 0x000000FF
+#define GPIO_GPIO_APPCPU_INT_H_S 0
+
+#define GPIO_ACPU_NMI_INT1 (DR_REG_GPIO_BASE + 0x0078)
+#define GPIO_GPIO_APPCPU_NMI_INT_H 0x000000FF
+#define GPIO_GPIO_APPCPU_NMI_INT_H_S 0
+
+#define GPIO_PCPU_INT1 (DR_REG_GPIO_BASE + 0x007c)
+#define GPIO_GPIO_PROCPU_INT_H 0x000000FF
+#define GPIO_GPIO_PROCPU_INT_H_S 0
+
+#define GPIO_PCPU_NMI_INT1 (DR_REG_GPIO_BASE + 0x0080)
+#define GPIO_GPIO_PROCPU_NMI_INT_H 0x000000FF
+#define GPIO_GPIO_PROCPU_NMI_INT_H_S 0
+
+#define GPIO_CPUSDIO_INT1 (DR_REG_GPIO_BASE + 0x0084)
+#define GPIO_GPIO_SDIO_INT_H 0x000000FF
+#define GPIO_GPIO_SDIO_INT_H_S 0
+
+#define GPIO_PIN0 (DR_REG_GPIO_BASE + 0x0088)
+#define GPIO_GPIO_PIN0_INT_ENA 0x0000001F
+#define GPIO_GPIO_PIN0_INT_ENA_S 13
+#define GPIO_GPIO_PIN0_CONFIG 0x00000003
+#define GPIO_GPIO_PIN0_CONFIG_S 11
+#define GPIO_GPIO_PIN0_WAKEUP_ENABLE (BIT(10))
+#define GPIO_GPIO_PIN0_WAKEUP_ENABLE_S 10
+#define GPIO_GPIO_PIN0_INT_TYPE 0x00000007
+#define GPIO_GPIO_PIN0_INT_TYPE_S 7
+#define GPIO_GPIO_PIN0_PAD_DRIVER (BIT(2))
+#define GPIO_GPIO_PIN0_PAD_DRIVER_S 2
+
+#define GPIO_PIN1 (DR_REG_GPIO_BASE + 0x008c)
+#define GPIO_GPIO_PIN1_INT_ENA 0x0000001F
+#define GPIO_GPIO_PIN1_INT_ENA_S 13
+#define GPIO_GPIO_PIN1_CONFIG 0x00000003
+#define GPIO_GPIO_PIN1_CONFIG_S 11
+#define GPIO_GPIO_PIN1_WAKEUP_ENABLE (BIT(10))
+#define GPIO_GPIO_PIN1_WAKEUP_ENABLE_S 10
+#define GPIO_GPIO_PIN1_INT_TYPE 0x00000007
+#define GPIO_GPIO_PIN1_INT_TYPE_S 7
+#define GPIO_GPIO_PIN1_PAD_DRIVER (BIT(2))
+#define GPIO_GPIO_PIN1_PAD_DRIVER_S 2
+
+#define GPIO_PIN2 (DR_REG_GPIO_BASE + 0x0090)
+#define GPIO_GPIO_PIN2_INT_ENA 0x0000001F
+#define GPIO_GPIO_PIN2_INT_ENA_S 13
+#define GPIO_GPIO_PIN2_CONFIG 0x00000003
+#define GPIO_GPIO_PIN2_CONFIG_S 11
+#define GPIO_GPIO_PIN2_WAKEUP_ENABLE (BIT(10))
+#define GPIO_GPIO_PIN2_WAKEUP_ENABLE_S 10
+#define GPIO_GPIO_PIN2_INT_TYPE 0x00000007
+#define GPIO_GPIO_PIN2_INT_TYPE_S 7
+#define GPIO_GPIO_PIN2_PAD_DRIVER (BIT(2))
+#define GPIO_GPIO_PIN2_PAD_DRIVER_S 2
+
+#define GPIO_PIN3 (DR_REG_GPIO_BASE + 0x0094)
+#define GPIO_GPIO_PIN3_INT_ENA 0x0000001F
+#define GPIO_GPIO_PIN3_INT_ENA_S 13
+#define GPIO_GPIO_PIN3_CONFIG 0x00000003
+#define GPIO_GPIO_PIN3_CONFIG_S 11
+#define GPIO_GPIO_PIN3_WAKEUP_ENABLE (BIT(10))
+#define GPIO_GPIO_PIN3_WAKEUP_ENABLE_S 10
+#define GPIO_GPIO_PIN3_INT_TYPE 0x00000007
+#define GPIO_GPIO_PIN3_INT_TYPE_S 7
+#define GPIO_GPIO_PIN3_PAD_DRIVER (BIT(2))
+#define GPIO_GPIO_PIN3_PAD_DRIVER_S 2
+
+#define GPIO_PIN4 (DR_REG_GPIO_BASE + 0x0098)
+#define GPIO_GPIO_PIN4_INT_ENA 0x0000001F
+#define GPIO_GPIO_PIN4_INT_ENA_S 13
+#define GPIO_GPIO_PIN4_CONFIG 0x00000003
+#define GPIO_GPIO_PIN4_CONFIG_S 11
+#define GPIO_GPIO_PIN4_WAKEUP_ENABLE (BIT(10))
+#define GPIO_GPIO_PIN4_WAKEUP_ENABLE_S 10
+#define GPIO_GPIO_PIN4_INT_TYPE 0x00000007
+#define GPIO_GPIO_PIN4_INT_TYPE_S 7
+#define GPIO_GPIO_PIN4_PAD_DRIVER (BIT(2))
+#define GPIO_GPIO_PIN4_PAD_DRIVER_S 2
+
+#define GPIO_PIN5 (DR_REG_GPIO_BASE + 0x009c)
+#define GPIO_GPIO_PIN5_INT_ENA 0x0000001F
+#define GPIO_GPIO_PIN5_INT_ENA_S 13
+#define GPIO_GPIO_PIN5_CONFIG 0x00000003
+#define GPIO_GPIO_PIN5_CONFIG_S 11
+#define GPIO_GPIO_PIN5_WAKEUP_ENABLE (BIT(10))
+#define GPIO_GPIO_PIN5_WAKEUP_ENABLE_S 10
+#define GPIO_GPIO_PIN5_INT_TYPE 0x00000007
+#define GPIO_GPIO_PIN5_INT_TYPE_S 7
+#define GPIO_GPIO_PIN5_PAD_DRIVER (BIT(2))
+#define GPIO_GPIO_PIN5_PAD_DRIVER_S 2
+
+#define GPIO_PIN6 (DR_REG_GPIO_BASE + 0x00a0)
+#define GPIO_GPIO_PIN6_INT_ENA 0x0000001F
+#define GPIO_GPIO_PIN6_INT_ENA_S 13
+#define GPIO_GPIO_PIN6_CONFIG 0x00000003
+#define GPIO_GPIO_PIN6_CONFIG_S 11
+#define GPIO_GPIO_PIN6_WAKEUP_ENABLE (BIT(10))
+#define GPIO_GPIO_PIN6_WAKEUP_ENABLE_S 10
+#define GPIO_GPIO_PIN6_INT_TYPE 0x00000007
+#define GPIO_GPIO_PIN6_INT_TYPE_S 7
+#define GPIO_GPIO_PIN6_PAD_DRIVER (BIT(2))
+#define GPIO_GPIO_PIN6_PAD_DRIVER_S 2
+
+#define GPIO_PIN7 (DR_REG_GPIO_BASE + 0x00a4)
+#define GPIO_GPIO_PIN7_INT_ENA 0x0000001F
+#define GPIO_GPIO_PIN7_INT_ENA_S 13
+#define GPIO_GPIO_PIN7_CONFIG 0x00000003
+#define GPIO_GPIO_PIN7_CONFIG_S 11
+#define GPIO_GPIO_PIN7_WAKEUP_ENABLE (BIT(10))
+#define GPIO_GPIO_PIN7_WAKEUP_ENABLE_S 10
+#define GPIO_GPIO_PIN7_INT_TYPE 0x00000007
+#define GPIO_GPIO_PIN7_INT_TYPE_S 7
+#define GPIO_GPIO_PIN7_PAD_DRIVER (BIT(2))
+#define GPIO_GPIO_PIN7_PAD_DRIVER_S 2
+
+#define GPIO_PIN8 (DR_REG_GPIO_BASE + 0x00a8)
+#define GPIO_GPIO_PIN8_INT_ENA 0x0000001F
+#define GPIO_GPIO_PIN8_INT_ENA_S 13
+#define GPIO_GPIO_PIN8_CONFIG 0x00000003
+#define GPIO_GPIO_PIN8_CONFIG_S 11
+#define GPIO_GPIO_PIN8_WAKEUP_ENABLE (BIT(10))
+#define GPIO_GPIO_PIN8_WAKEUP_ENABLE_S 10
+#define GPIO_GPIO_PIN8_INT_TYPE 0x00000007
+#define GPIO_GPIO_PIN8_INT_TYPE_S 7
+#define GPIO_GPIO_PIN8_PAD_DRIVER (BIT(2))
+#define GPIO_GPIO_PIN8_PAD_DRIVER_S 2
+
+#define GPIO_PIN9 (DR_REG_GPIO_BASE + 0x00ac)
+#define GPIO_GPIO_PIN9_INT_ENA 0x0000001F
+#define GPIO_GPIO_PIN9_INT_ENA_S 13
+#define GPIO_GPIO_PIN9_CONFIG 0x00000003
+#define GPIO_GPIO_PIN9_CONFIG_S 11
+#define GPIO_GPIO_PIN9_WAKEUP_ENABLE (BIT(10))
+#define GPIO_GPIO_PIN9_WAKEUP_ENABLE_S 10
+#define GPIO_GPIO_PIN9_INT_TYPE 0x00000007
+#define GPIO_GPIO_PIN9_INT_TYPE_S 7
+#define GPIO_GPIO_PIN9_PAD_DRIVER (BIT(2))
+#define GPIO_GPIO_PIN9_PAD_DRIVER_S 2
+
+#define GPIO_PIN10 (DR_REG_GPIO_BASE + 0x00b0)
+#define GPIO_GPIO_PIN10_INT_ENA 0x0000001F
+#define GPIO_GPIO_PIN10_INT_ENA_S 13
+#define GPIO_GPIO_PIN10_CONFIG 0x00000003
+#define GPIO_GPIO_PIN10_CONFIG_S 11
+#define GPIO_GPIO_PIN10_WAKEUP_ENABLE (BIT(10))
+#define GPIO_GPIO_PIN10_WAKEUP_ENABLE_S 10
+#define GPIO_GPIO_PIN10_INT_TYPE 0x00000007
+#define GPIO_GPIO_PIN10_INT_TYPE_S 7
+#define GPIO_GPIO_PIN10_PAD_DRIVER (BIT(2))
+#define GPIO_GPIO_PIN10_PAD_DRIVER_S 2
+
+#define GPIO_PIN11 (DR_REG_GPIO_BASE + 0x00b4)
+#define GPIO_GPIO_PIN11_INT_ENA 0x0000001F
+#define GPIO_GPIO_PIN11_INT_ENA_S 13
+#define GPIO_GPIO_PIN11_CONFIG 0x00000003
+#define GPIO_GPIO_PIN11_CONFIG_S 11
+#define GPIO_GPIO_PIN11_WAKEUP_ENABLE (BIT(10))
+#define GPIO_GPIO_PIN11_WAKEUP_ENABLE_S 10
+#define GPIO_GPIO_PIN11_INT_TYPE 0x00000007
+#define GPIO_GPIO_PIN11_INT_TYPE_S 7
+#define GPIO_GPIO_PIN11_PAD_DRIVER (BIT(2))
+#define GPIO_GPIO_PIN11_PAD_DRIVER_S 2
+
+#define GPIO_PIN12 (DR_REG_GPIO_BASE + 0x00b8)
+#define GPIO_GPIO_PIN12_INT_ENA 0x0000001F
+#define GPIO_GPIO_PIN12_INT_ENA_S 13
+#define GPIO_GPIO_PIN12_CONFIG 0x00000003
+#define GPIO_GPIO_PIN12_CONFIG_S 11
+#define GPIO_GPIO_PIN12_WAKEUP_ENABLE (BIT(10))
+#define GPIO_GPIO_PIN12_WAKEUP_ENABLE_S 10
+#define GPIO_GPIO_PIN12_INT_TYPE 0x00000007
+#define GPIO_GPIO_PIN12_INT_TYPE_S 7
+#define GPIO_GPIO_PIN12_PAD_DRIVER (BIT(2))
+#define GPIO_GPIO_PIN12_PAD_DRIVER_S 2
+
+#define GPIO_PIN13 (DR_REG_GPIO_BASE + 0x00bc)
+#define GPIO_GPIO_PIN13_INT_ENA 0x0000001F
+#define GPIO_GPIO_PIN13_INT_ENA_S 13
+#define GPIO_GPIO_PIN13_CONFIG 0x00000003
+#define GPIO_GPIO_PIN13_CONFIG_S 11
+#define GPIO_GPIO_PIN13_WAKEUP_ENABLE (BIT(10))
+#define GPIO_GPIO_PIN13_WAKEUP_ENABLE_S 10
+#define GPIO_GPIO_PIN13_INT_TYPE 0x00000007
+#define GPIO_GPIO_PIN13_INT_TYPE_S 7
+#define GPIO_GPIO_PIN13_PAD_DRIVER (BIT(2))
+#define GPIO_GPIO_PIN13_PAD_DRIVER_S 2
+
+#define GPIO_PIN14 (DR_REG_GPIO_BASE + 0x00c0)
+#define GPIO_GPIO_PIN14_INT_ENA 0x0000001F
+#define GPIO_GPIO_PIN14_INT_ENA_S 13
+#define GPIO_GPIO_PIN14_CONFIG 0x00000003
+#define GPIO_GPIO_PIN14_CONFIG_S 11
+#define GPIO_GPIO_PIN14_WAKEUP_ENABLE (BIT(10))
+#define GPIO_GPIO_PIN14_WAKEUP_ENABLE_S 10
+#define GPIO_GPIO_PIN14_INT_TYPE 0x00000007
+#define GPIO_GPIO_PIN14_INT_TYPE_S 7
+#define GPIO_GPIO_PIN14_PAD_DRIVER (BIT(2))
+#define GPIO_GPIO_PIN14_PAD_DRIVER_S 2
+
+#define GPIO_PIN15 (DR_REG_GPIO_BASE + 0x00c4)
+#define GPIO_GPIO_PIN15_INT_ENA 0x0000001F
+#define GPIO_GPIO_PIN15_INT_ENA_S 13
+#define GPIO_GPIO_PIN15_CONFIG 0x00000003
+#define GPIO_GPIO_PIN15_CONFIG_S 11
+#define GPIO_GPIO_PIN15_WAKEUP_ENABLE (BIT(10))
+#define GPIO_GPIO_PIN15_WAKEUP_ENABLE_S 10
+#define GPIO_GPIO_PIN15_INT_TYPE 0x00000007
+#define GPIO_GPIO_PIN15_INT_TYPE_S 7
+#define GPIO_GPIO_PIN15_PAD_DRIVER (BIT(2))
+#define GPIO_GPIO_PIN15_PAD_DRIVER_S 2
+
+#define GPIO_PIN16 (DR_REG_GPIO_BASE + 0x00c8)
+#define GPIO_GPIO_PIN16_INT_ENA 0x0000001F
+#define GPIO_GPIO_PIN16_INT_ENA_S 13
+#define GPIO_GPIO_PIN16_CONFIG 0x00000003
+#define GPIO_GPIO_PIN16_CONFIG_S 11
+#define GPIO_GPIO_PIN16_WAKEUP_ENABLE (BIT(10))
+#define GPIO_GPIO_PIN16_WAKEUP_ENABLE_S 10
+#define GPIO_GPIO_PIN16_INT_TYPE 0x00000007
+#define GPIO_GPIO_PIN16_INT_TYPE_S 7
+#define GPIO_GPIO_PIN16_PAD_DRIVER (BIT(2))
+#define GPIO_GPIO_PIN16_PAD_DRIVER_S 2
+
+#define GPIO_PIN17 (DR_REG_GPIO_BASE + 0x00cc)
+#define GPIO_GPIO_PIN17_INT_ENA 0x0000001F
+#define GPIO_GPIO_PIN17_INT_ENA_S 13
+#define GPIO_GPIO_PIN17_CONFIG 0x00000003
+#define GPIO_GPIO_PIN17_CONFIG_S 11
+#define GPIO_GPIO_PIN17_WAKEUP_ENABLE (BIT(10))
+#define GPIO_GPIO_PIN17_WAKEUP_ENABLE_S 10
+#define GPIO_GPIO_PIN17_INT_TYPE 0x00000007
+#define GPIO_GPIO_PIN17_INT_TYPE_S 7
+#define GPIO_GPIO_PIN17_PAD_DRIVER (BIT(2))
+#define GPIO_GPIO_PIN17_PAD_DRIVER_S 2
+
+#define GPIO_PIN18 (DR_REG_GPIO_BASE + 0x00d0)
+#define GPIO_GPIO_PIN18_INT_ENA 0x0000001F
+#define GPIO_GPIO_PIN18_INT_ENA_S 13
+#define GPIO_GPIO_PIN18_CONFIG 0x00000003
+#define GPIO_GPIO_PIN18_CONFIG_S 11
+#define GPIO_GPIO_PIN18_WAKEUP_ENABLE (BIT(10))
+#define GPIO_GPIO_PIN18_WAKEUP_ENABLE_S 10
+#define GPIO_GPIO_PIN18_INT_TYPE 0x00000007
+#define GPIO_GPIO_PIN18_INT_TYPE_S 7
+#define GPIO_GPIO_PIN18_PAD_DRIVER (BIT(2))
+#define GPIO_GPIO_PIN18_PAD_DRIVER_S 2
+
+#define GPIO_PIN19 (DR_REG_GPIO_BASE + 0x00d4)
+#define GPIO_GPIO_PIN19_INT_ENA 0x0000001F
+#define GPIO_GPIO_PIN19_INT_ENA_S 13
+#define GPIO_GPIO_PIN19_CONFIG 0x00000003
+#define GPIO_GPIO_PIN19_CONFIG_S 11
+#define GPIO_GPIO_PIN19_WAKEUP_ENABLE (BIT(10))
+#define GPIO_GPIO_PIN19_WAKEUP_ENABLE_S 10
+#define GPIO_GPIO_PIN19_INT_TYPE 0x00000007
+#define GPIO_GPIO_PIN19_INT_TYPE_S 7
+#define GPIO_GPIO_PIN19_PAD_DRIVER (BIT(2))
+#define GPIO_GPIO_PIN19_PAD_DRIVER_S 2
+
+#define GPIO_PIN20 (DR_REG_GPIO_BASE + 0x00d8)
+#define GPIO_GPIO_PIN20_INT_ENA 0x0000001F
+#define GPIO_GPIO_PIN20_INT_ENA_S 13
+#define GPIO_GPIO_PIN20_CONFIG 0x00000003
+#define GPIO_GPIO_PIN20_CONFIG_S 11
+#define GPIO_GPIO_PIN20_WAKEUP_ENABLE (BIT(10))
+#define GPIO_GPIO_PIN20_WAKEUP_ENABLE_S 10
+#define GPIO_GPIO_PIN20_INT_TYPE 0x00000007
+#define GPIO_GPIO_PIN20_INT_TYPE_S 7
+#define GPIO_GPIO_PIN20_PAD_DRIVER (BIT(2))
+#define GPIO_GPIO_PIN20_PAD_DRIVER_S 2
+
+#define GPIO_PIN21 (DR_REG_GPIO_BASE + 0x00dc)
+#define GPIO_GPIO_PIN21_INT_ENA 0x0000001F
+#define GPIO_GPIO_PIN21_INT_ENA_S 13
+#define GPIO_GPIO_PIN21_CONFIG 0x00000003
+#define GPIO_GPIO_PIN21_CONFIG_S 11
+#define GPIO_GPIO_PIN21_WAKEUP_ENABLE (BIT(10))
+#define GPIO_GPIO_PIN21_WAKEUP_ENABLE_S 10
+#define GPIO_GPIO_PIN21_INT_TYPE 0x00000007
+#define GPIO_GPIO_PIN21_INT_TYPE_S 7
+#define GPIO_GPIO_PIN21_PAD_DRIVER (BIT(2))
+#define GPIO_GPIO_PIN21_PAD_DRIVER_S 2
+
+#define GPIO_PIN22 (DR_REG_GPIO_BASE + 0x00e0)
+#define GPIO_GPIO_PIN22_INT_ENA 0x0000001F
+#define GPIO_GPIO_PIN22_INT_ENA_S 13
+#define GPIO_GPIO_PIN22_CONFIG 0x00000003
+#define GPIO_GPIO_PIN22_CONFIG_S 11
+#define GPIO_GPIO_PIN22_WAKEUP_ENABLE (BIT(10))
+#define GPIO_GPIO_PIN22_WAKEUP_ENABLE_S 10
+#define GPIO_GPIO_PIN22_INT_TYPE 0x00000007
+#define GPIO_GPIO_PIN22_INT_TYPE_S 7
+#define GPIO_GPIO_PIN22_PAD_DRIVER (BIT(2))
+#define GPIO_GPIO_PIN22_PAD_DRIVER_S 2
+
+#define GPIO_PIN23 (DR_REG_GPIO_BASE + 0x00e4)
+#define GPIO_GPIO_PIN23_INT_ENA 0x0000001F
+#define GPIO_GPIO_PIN23_INT_ENA_S 13
+#define GPIO_GPIO_PIN23_CONFIG 0x00000003
+#define GPIO_GPIO_PIN23_CONFIG_S 11
+#define GPIO_GPIO_PIN23_WAKEUP_ENABLE (BIT(10))
+#define GPIO_GPIO_PIN23_WAKEUP_ENABLE_S 10
+#define GPIO_GPIO_PIN23_INT_TYPE 0x00000007
+#define GPIO_GPIO_PIN23_INT_TYPE_S 7
+#define GPIO_GPIO_PIN23_PAD_DRIVER (BIT(2))
+#define GPIO_GPIO_PIN23_PAD_DRIVER_S 2
+
+#define GPIO_PIN24 (DR_REG_GPIO_BASE + 0x00e8)
+#define GPIO_GPIO_PIN24_INT_ENA 0x0000001F
+#define GPIO_GPIO_PIN24_INT_ENA_S 13
+#define GPIO_GPIO_PIN24_CONFIG 0x00000003
+#define GPIO_GPIO_PIN24_CONFIG_S 11
+#define GPIO_GPIO_PIN24_WAKEUP_ENABLE (BIT(10))
+#define GPIO_GPIO_PIN24_WAKEUP_ENABLE_S 10
+#define GPIO_GPIO_PIN24_INT_TYPE 0x00000007
+#define GPIO_GPIO_PIN24_INT_TYPE_S 7
+#define GPIO_GPIO_PIN24_PAD_DRIVER (BIT(2))
+#define GPIO_GPIO_PIN24_PAD_DRIVER_S 2
+
+#define GPIO_PIN25 (DR_REG_GPIO_BASE + 0x00ec)
+#define GPIO_GPIO_PIN25_INT_ENA 0x0000001F
+#define GPIO_GPIO_PIN25_INT_ENA_S 13
+#define GPIO_GPIO_PIN25_CONFIG 0x00000003
+#define GPIO_GPIO_PIN25_CONFIG_S 11
+#define GPIO_GPIO_PIN25_WAKEUP_ENABLE (BIT(10))
+#define GPIO_GPIO_PIN25_WAKEUP_ENABLE_S 10
+#define GPIO_GPIO_PIN25_INT_TYPE 0x00000007
+#define GPIO_GPIO_PIN25_INT_TYPE_S 7
+#define GPIO_GPIO_PIN25_PAD_DRIVER (BIT(2))
+#define GPIO_GPIO_PIN25_PAD_DRIVER_S 2
+
+#define GPIO_PIN26 (DR_REG_GPIO_BASE + 0x00f0)
+#define GPIO_GPIO_PIN26_INT_ENA 0x0000001F
+#define GPIO_GPIO_PIN26_INT_ENA_S 13
+#define GPIO_GPIO_PIN26_CONFIG 0x00000003
+#define GPIO_GPIO_PIN26_CONFIG_S 11
+#define GPIO_GPIO_PIN26_WAKEUP_ENABLE (BIT(10))
+#define GPIO_GPIO_PIN26_WAKEUP_ENABLE_S 10
+#define GPIO_GPIO_PIN26_INT_TYPE 0x00000007
+#define GPIO_GPIO_PIN26_INT_TYPE_S 7
+#define GPIO_GPIO_PIN26_PAD_DRIVER (BIT(2))
+#define GPIO_GPIO_PIN26_PAD_DRIVER_S 2
+
+#define GPIO_PIN27 (DR_REG_GPIO_BASE + 0x00f4)
+#define GPIO_GPIO_PIN27_INT_ENA 0x0000001F
+#define GPIO_GPIO_PIN27_INT_ENA_S 13
+#define GPIO_GPIO_PIN27_CONFIG 0x00000003
+#define GPIO_GPIO_PIN27_CONFIG_S 11
+#define GPIO_GPIO_PIN27_WAKEUP_ENABLE (BIT(10))
+#define GPIO_GPIO_PIN27_WAKEUP_ENABLE_S 10
+#define GPIO_GPIO_PIN27_INT_TYPE 0x00000007
+#define GPIO_GPIO_PIN27_INT_TYPE_S 7
+#define GPIO_GPIO_PIN27_PAD_DRIVER (BIT(2))
+#define GPIO_GPIO_PIN27_PAD_DRIVER_S 2
+
+#define GPIO_PIN28 (DR_REG_GPIO_BASE + 0x00f8)
+#define GPIO_GPIO_PIN28_INT_ENA 0x0000001F
+#define GPIO_GPIO_PIN28_INT_ENA_S 13
+#define GPIO_GPIO_PIN28_CONFIG 0x00000003
+#define GPIO_GPIO_PIN28_CONFIG_S 11
+#define GPIO_GPIO_PIN28_WAKEUP_ENABLE (BIT(10))
+#define GPIO_GPIO_PIN28_WAKEUP_ENABLE_S 10
+#define GPIO_GPIO_PIN28_INT_TYPE 0x00000007
+#define GPIO_GPIO_PIN28_INT_TYPE_S 7
+#define GPIO_GPIO_PIN28_PAD_DRIVER (BIT(2))
+#define GPIO_GPIO_PIN28_PAD_DRIVER_S 2
+
+#define GPIO_PIN29 (DR_REG_GPIO_BASE + 0x00fc)
+#define GPIO_GPIO_PIN29_INT_ENA 0x0000001F
+#define GPIO_GPIO_PIN29_INT_ENA_S 13
+#define GPIO_GPIO_PIN29_CONFIG 0x00000003
+#define GPIO_GPIO_PIN29_CONFIG_S 11
+#define GPIO_GPIO_PIN29_WAKEUP_ENABLE (BIT(10))
+#define GPIO_GPIO_PIN29_WAKEUP_ENABLE_S 10
+#define GPIO_GPIO_PIN29_INT_TYPE 0x00000007
+#define GPIO_GPIO_PIN29_INT_TYPE_S 7
+#define GPIO_GPIO_PIN29_PAD_DRIVER (BIT(2))
+#define GPIO_GPIO_PIN29_PAD_DRIVER_S 2
+
+#define GPIO_PIN30 (DR_REG_GPIO_BASE + 0x0100)
+#define GPIO_GPIO_PIN30_INT_ENA 0x0000001F
+#define GPIO_GPIO_PIN30_INT_ENA_S 13
+#define GPIO_GPIO_PIN30_CONFIG 0x00000003
+#define GPIO_GPIO_PIN30_CONFIG_S 11
+#define GPIO_GPIO_PIN30_WAKEUP_ENABLE (BIT(10))
+#define GPIO_GPIO_PIN30_WAKEUP_ENABLE_S 10
+#define GPIO_GPIO_PIN30_INT_TYPE 0x00000007
+#define GPIO_GPIO_PIN30_INT_TYPE_S 7
+#define GPIO_GPIO_PIN30_PAD_DRIVER (BIT(2))
+#define GPIO_GPIO_PIN30_PAD_DRIVER_S 2
+
+#define GPIO_PIN31 (DR_REG_GPIO_BASE + 0x0104)
+#define GPIO_GPIO_PIN31_INT_ENA 0x0000001F
+#define GPIO_GPIO_PIN31_INT_ENA_S 13
+#define GPIO_GPIO_PIN31_CONFIG 0x00000003
+#define GPIO_GPIO_PIN31_CONFIG_S 11
+#define GPIO_GPIO_PIN31_WAKEUP_ENABLE (BIT(10))
+#define GPIO_GPIO_PIN31_WAKEUP_ENABLE_S 10
+#define GPIO_GPIO_PIN31_INT_TYPE 0x00000007
+#define GPIO_GPIO_PIN31_INT_TYPE_S 7
+#define GPIO_GPIO_PIN31_PAD_DRIVER (BIT(2))
+#define GPIO_GPIO_PIN31_PAD_DRIVER_S 2
+
+#define GPIO_PIN32 (DR_REG_GPIO_BASE + 0x0108)
+#define GPIO_GPIO_PIN32_INT_ENA 0x0000001F
+#define GPIO_GPIO_PIN32_INT_ENA_S 13
+#define GPIO_GPIO_PIN32_CONFIG 0x00000003
+#define GPIO_GPIO_PIN32_CONFIG_S 11
+#define GPIO_GPIO_PIN32_WAKEUP_ENABLE (BIT(10))
+#define GPIO_GPIO_PIN32_WAKEUP_ENABLE_S 10
+#define GPIO_GPIO_PIN32_INT_TYPE 0x00000007
+#define GPIO_GPIO_PIN32_INT_TYPE_S 7
+#define GPIO_GPIO_PIN32_PAD_DRIVER (BIT(2))
+#define GPIO_GPIO_PIN32_PAD_DRIVER_S 2
+
+#define GPIO_PIN33 (DR_REG_GPIO_BASE + 0x010c)
+#define GPIO_GPIO_PIN33_INT_ENA 0x0000001F
+#define GPIO_GPIO_PIN33_INT_ENA_S 13
+#define GPIO_GPIO_PIN33_CONFIG 0x00000003
+#define GPIO_GPIO_PIN33_CONFIG_S 11
+#define GPIO_GPIO_PIN33_WAKEUP_ENABLE (BIT(10))
+#define GPIO_GPIO_PIN33_WAKEUP_ENABLE_S 10
+#define GPIO_GPIO_PIN33_INT_TYPE 0x00000007
+#define GPIO_GPIO_PIN33_INT_TYPE_S 7
+#define GPIO_GPIO_PIN33_PAD_DRIVER (BIT(2))
+#define GPIO_GPIO_PIN33_PAD_DRIVER_S 2
+
+#define GPIO_PIN34 (DR_REG_GPIO_BASE + 0x0110)
+#define GPIO_GPIO_PIN34_INT_ENA 0x0000001F
+#define GPIO_GPIO_PIN34_INT_ENA_S 13
+#define GPIO_GPIO_PIN34_CONFIG 0x00000003
+#define GPIO_GPIO_PIN34_CONFIG_S 11
+#define GPIO_GPIO_PIN34_WAKEUP_ENABLE (BIT(10))
+#define GPIO_GPIO_PIN34_WAKEUP_ENABLE_S 10
+#define GPIO_GPIO_PIN34_INT_TYPE 0x00000007
+#define GPIO_GPIO_PIN34_INT_TYPE_S 7
+#define GPIO_GPIO_PIN34_PAD_DRIVER (BIT(2))
+#define GPIO_GPIO_PIN34_PAD_DRIVER_S 2
+
+#define GPIO_PIN35 (DR_REG_GPIO_BASE + 0x0114)
+#define GPIO_GPIO_PIN35_INT_ENA 0x0000001F
+#define GPIO_GPIO_PIN35_INT_ENA_S 13
+#define GPIO_GPIO_PIN35_CONFIG 0x00000003
+#define GPIO_GPIO_PIN35_CONFIG_S 11
+#define GPIO_GPIO_PIN35_WAKEUP_ENABLE (BIT(10))
+#define GPIO_GPIO_PIN35_WAKEUP_ENABLE_S 10
+#define GPIO_GPIO_PIN35_INT_TYPE 0x00000007
+#define GPIO_GPIO_PIN35_INT_TYPE_S 7
+#define GPIO_GPIO_PIN35_PAD_DRIVER (BIT(2))
+#define GPIO_GPIO_PIN35_PAD_DRIVER_S 2
+
+#define GPIO_PIN36 (DR_REG_GPIO_BASE + 0x0118)
+#define GPIO_GPIO_PIN36_INT_ENA 0x0000001F
+#define GPIO_GPIO_PIN36_INT_ENA_S 13
+#define GPIO_GPIO_PIN36_CONFIG 0x00000003
+#define GPIO_GPIO_PIN36_CONFIG_S 11
+#define GPIO_GPIO_PIN36_WAKEUP_ENABLE (BIT(10))
+#define GPIO_GPIO_PIN36_WAKEUP_ENABLE_S 10
+#define GPIO_GPIO_PIN36_INT_TYPE 0x00000007
+#define GPIO_GPIO_PIN36_INT_TYPE_S 7
+#define GPIO_GPIO_PIN36_PAD_DRIVER (BIT(2))
+#define GPIO_GPIO_PIN36_PAD_DRIVER_S 2
+
+#define GPIO_PIN37 (DR_REG_GPIO_BASE + 0x011c)
+#define GPIO_GPIO_PIN37_INT_ENA 0x0000001F
+#define GPIO_GPIO_PIN37_INT_ENA_S 13
+#define GPIO_GPIO_PIN37_CONFIG 0x00000003
+#define GPIO_GPIO_PIN37_CONFIG_S 11
+#define GPIO_GPIO_PIN37_WAKEUP_ENABLE (BIT(10))
+#define GPIO_GPIO_PIN37_WAKEUP_ENABLE_S 10
+#define GPIO_GPIO_PIN37_INT_TYPE 0x00000007
+#define GPIO_GPIO_PIN37_INT_TYPE_S 7
+#define GPIO_GPIO_PIN37_PAD_DRIVER (BIT(2))
+#define GPIO_GPIO_PIN37_PAD_DRIVER_S 2
+
+#define GPIO_PIN38 (DR_REG_GPIO_BASE + 0x0120)
+#define GPIO_GPIO_PIN38_INT_ENA 0x0000001F
+#define GPIO_GPIO_PIN38_INT_ENA_S 13
+#define GPIO_GPIO_PIN38_CONFIG 0x00000003
+#define GPIO_GPIO_PIN38_CONFIG_S 11
+#define GPIO_GPIO_PIN38_WAKEUP_ENABLE (BIT(10))
+#define GPIO_GPIO_PIN38_WAKEUP_ENABLE_S 10
+#define GPIO_GPIO_PIN38_INT_TYPE 0x00000007
+#define GPIO_GPIO_PIN38_INT_TYPE_S 7
+#define GPIO_GPIO_PIN38_PAD_DRIVER (BIT(2))
+#define GPIO_GPIO_PIN38_PAD_DRIVER_S 2
+
+#define GPIO_PIN39 (DR_REG_GPIO_BASE + 0x0124)
+#define GPIO_GPIO_PIN39_INT_ENA 0x0000001F
+#define GPIO_GPIO_PIN39_INT_ENA_S 13
+#define GPIO_GPIO_PIN39_CONFIG 0x00000003
+#define GPIO_GPIO_PIN39_CONFIG_S 11
+#define GPIO_GPIO_PIN39_WAKEUP_ENABLE (BIT(10))
+#define GPIO_GPIO_PIN39_WAKEUP_ENABLE_S 10
+#define GPIO_GPIO_PIN39_INT_TYPE 0x00000007
+#define GPIO_GPIO_PIN39_INT_TYPE_S 7
+#define GPIO_GPIO_PIN39_PAD_DRIVER (BIT(2))
+#define GPIO_GPIO_PIN39_PAD_DRIVER_S 2
+
+#define CALI_CONF (DR_REG_GPIO_BASE + 0x0128)
+#define GPIO_CALI_START (BIT(31))
+#define GPIO_CALI_START_S 31
+#define GPIO_CALI_RTC_MAX 0x000003FF
+#define GPIO_CALI_RTC_MAX_S 0
+
+#define CALI_DATA (DR_REG_GPIO_BASE + 0x012c)
+#define GPIO_CALI_RDY_SYNC2 (BIT(31))
+#define GPIO_CALI_RDY_SYNC2_S 31
+#define GPIO_CALI_RDY_REAL (BIT(30))
+#define GPIO_CALI_RDY_REAL_S 30
+#define GPIO_CALI_VALUE_SYNC2 0x000FFFFF
+#define GPIO_CALI_VALUE_SYNC2_S 0
+
+#define GPIO_FUNC0_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0130)
+#define GPIO_GPIO_SIG0_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG0_IN_SEL_S 7
+#define GPIO_GPIO_FUNC0_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC0_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC0_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC0_IN_SEL_S 0
+
+#define GPIO_FUNC1_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0134)
+#define GPIO_GPIO_SIG1_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG1_IN_SEL_S 7
+#define GPIO_GPIO_FUNC1_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC1_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC1_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC1_IN_SEL_S 0
+
+#define GPIO_FUNC2_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0138)
+#define GPIO_GPIO_SIG2_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG2_IN_SEL_S 7
+#define GPIO_GPIO_FUNC2_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC2_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC2_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC2_IN_SEL_S 0
+
+#define GPIO_FUNC3_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x013c)
+#define GPIO_GPIO_SIG3_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG3_IN_SEL_S 7
+#define GPIO_GPIO_FUNC3_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC3_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC3_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC3_IN_SEL_S 0
+
+#define GPIO_FUNC4_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0140)
+#define GPIO_GPIO_SIG4_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG4_IN_SEL_S 7
+#define GPIO_GPIO_FUNC4_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC4_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC4_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC4_IN_SEL_S 0
+
+#define GPIO_FUNC5_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0144)
+#define GPIO_GPIO_SIG5_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG5_IN_SEL_S 7
+#define GPIO_GPIO_FUNC5_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC5_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC5_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC5_IN_SEL_S 0
+
+#define GPIO_FUNC6_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0148)
+#define GPIO_GPIO_SIG6_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG6_IN_SEL_S 7
+#define GPIO_GPIO_FUNC6_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC6_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC6_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC6_IN_SEL_S 0
+
+#define GPIO_FUNC7_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x014c)
+#define GPIO_GPIO_SIG7_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG7_IN_SEL_S 7
+#define GPIO_GPIO_FUNC7_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC7_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC7_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC7_IN_SEL_S 0
+
+#define GPIO_FUNC8_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0150)
+#define GPIO_GPIO_SIG8_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG8_IN_SEL_S 7
+#define GPIO_GPIO_FUNC8_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC8_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC8_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC8_IN_SEL_S 0
+
+#define GPIO_FUNC9_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0154)
+#define GPIO_GPIO_SIG9_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG9_IN_SEL_S 7
+#define GPIO_GPIO_FUNC9_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC9_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC9_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC9_IN_SEL_S 0
+
+#define GPIO_FUNC10_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0158)
+#define GPIO_GPIO_SIG10_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG10_IN_SEL_S 7
+#define GPIO_GPIO_FUNC10_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC10_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC10_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC10_IN_SEL_S 0
+
+#define GPIO_FUNC11_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x015c)
+#define GPIO_GPIO_SIG11_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG11_IN_SEL_S 7
+#define GPIO_GPIO_FUNC11_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC11_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC11_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC11_IN_SEL_S 0
+
+#define GPIO_FUNC12_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0160)
+#define GPIO_GPIO_SIG12_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG12_IN_SEL_S 7
+#define GPIO_GPIO_FUNC12_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC12_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC12_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC12_IN_SEL_S 0
+
+#define GPIO_FUNC13_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0164)
+#define GPIO_GPIO_SIG13_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG13_IN_SEL_S 7
+#define GPIO_GPIO_FUNC13_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC13_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC13_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC13_IN_SEL_S 0
+
+#define GPIO_FUNC14_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0168)
+#define GPIO_GPIO_SIG14_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG14_IN_SEL_S 7
+#define GPIO_GPIO_FUNC14_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC14_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC14_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC14_IN_SEL_S 0
+
+#define GPIO_FUNC15_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x016c)
+#define GPIO_GPIO_SIG15_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG15_IN_SEL_S 7
+#define GPIO_GPIO_FUNC15_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC15_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC15_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC15_IN_SEL_S 0
+
+#define GPIO_FUNC16_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0170)
+#define GPIO_GPIO_SIG16_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG16_IN_SEL_S 7
+#define GPIO_GPIO_FUNC16_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC16_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC16_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC16_IN_SEL_S 0
+
+#define GPIO_FUNC17_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0174)
+#define GPIO_GPIO_SIG17_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG17_IN_SEL_S 7
+#define GPIO_GPIO_FUNC17_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC17_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC17_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC17_IN_SEL_S 0
+
+#define GPIO_FUNC18_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0178)
+#define GPIO_GPIO_SIG18_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG18_IN_SEL_S 7
+#define GPIO_GPIO_FUNC18_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC18_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC18_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC18_IN_SEL_S 0
+
+#define GPIO_FUNC19_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x017c)
+#define GPIO_GPIO_SIG19_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG19_IN_SEL_S 7
+#define GPIO_GPIO_FUNC19_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC19_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC19_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC19_IN_SEL_S 0
+
+#define GPIO_FUNC20_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0180)
+#define GPIO_GPIO_SIG20_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG20_IN_SEL_S 7
+#define GPIO_GPIO_FUNC20_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC20_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC20_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC20_IN_SEL_S 0
+
+#define GPIO_FUNC21_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0184)
+#define GPIO_GPIO_SIG21_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG21_IN_SEL_S 7
+#define GPIO_GPIO_FUNC21_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC21_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC21_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC21_IN_SEL_S 0
+
+#define GPIO_FUNC22_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0188)
+#define GPIO_GPIO_SIG22_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG22_IN_SEL_S 7
+#define GPIO_GPIO_FUNC22_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC22_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC22_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC22_IN_SEL_S 0
+
+#define GPIO_FUNC23_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x018c)
+#define GPIO_GPIO_SIG23_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG23_IN_SEL_S 7
+#define GPIO_GPIO_FUNC23_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC23_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC23_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC23_IN_SEL_S 0
+
+#define GPIO_FUNC24_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0190)
+#define GPIO_GPIO_SIG24_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG24_IN_SEL_S 7
+#define GPIO_GPIO_FUNC24_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC24_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC24_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC24_IN_SEL_S 0
+
+#define GPIO_FUNC25_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0194)
+#define GPIO_GPIO_SIG25_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG25_IN_SEL_S 7
+#define GPIO_GPIO_FUNC25_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC25_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC25_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC25_IN_SEL_S 0
+
+#define GPIO_FUNC26_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0198)
+#define GPIO_GPIO_SIG26_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG26_IN_SEL_S 7
+#define GPIO_GPIO_FUNC26_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC26_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC26_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC26_IN_SEL_S 0
+
+#define GPIO_FUNC27_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x019c)
+#define GPIO_GPIO_SIG27_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG27_IN_SEL_S 7
+#define GPIO_GPIO_FUNC27_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC27_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC27_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC27_IN_SEL_S 0
+
+#define GPIO_FUNC28_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x01a0)
+#define GPIO_GPIO_SIG28_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG28_IN_SEL_S 7
+#define GPIO_GPIO_FUNC28_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC28_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC28_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC28_IN_SEL_S 0
+
+#define GPIO_FUNC29_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x01a4)
+#define GPIO_GPIO_SIG29_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG29_IN_SEL_S 7
+#define GPIO_GPIO_FUNC29_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC29_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC29_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC29_IN_SEL_S 0
+
+#define GPIO_FUNC30_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x01a8)
+#define GPIO_GPIO_SIG30_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG30_IN_SEL_S 7
+#define GPIO_GPIO_FUNC30_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC30_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC30_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC30_IN_SEL_S 0
+
+#define GPIO_FUNC31_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x01ac)
+#define GPIO_GPIO_SIG31_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG31_IN_SEL_S 7
+#define GPIO_GPIO_FUNC31_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC31_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC31_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC31_IN_SEL_S 0
+
+#define GPIO_FUNC32_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x01b0)
+#define GPIO_GPIO_SIG32_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG32_IN_SEL_S 7
+#define GPIO_GPIO_FUNC32_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC32_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC32_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC32_IN_SEL_S 0
+
+#define GPIO_FUNC33_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x01b4)
+#define GPIO_GPIO_SIG33_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG33_IN_SEL_S 7
+#define GPIO_GPIO_FUNC33_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC33_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC33_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC33_IN_SEL_S 0
+
+#define GPIO_FUNC34_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x01b8)
+#define GPIO_GPIO_SIG34_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG34_IN_SEL_S 7
+#define GPIO_GPIO_FUNC34_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC34_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC34_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC34_IN_SEL_S 0
+
+#define GPIO_FUNC35_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x01bc)
+#define GPIO_GPIO_SIG35_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG35_IN_SEL_S 7
+#define GPIO_GPIO_FUNC35_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC35_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC35_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC35_IN_SEL_S 0
+
+#define GPIO_FUNC36_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x01c0)
+#define GPIO_GPIO_SIG36_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG36_IN_SEL_S 7
+#define GPIO_GPIO_FUNC36_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC36_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC36_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC36_IN_SEL_S 0
+
+#define GPIO_FUNC37_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x01c4)
+#define GPIO_GPIO_SIG37_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG37_IN_SEL_S 7
+#define GPIO_GPIO_FUNC37_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC37_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC37_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC37_IN_SEL_S 0
+
+#define GPIO_FUNC38_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x01c8)
+#define GPIO_GPIO_SIG38_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG38_IN_SEL_S 7
+#define GPIO_GPIO_FUNC38_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC38_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC38_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC38_IN_SEL_S 0
+
+#define GPIO_FUNC39_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x01cc)
+#define GPIO_GPIO_SIG39_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG39_IN_SEL_S 7
+#define GPIO_GPIO_FUNC39_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC39_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC39_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC39_IN_SEL_S 0
+
+#define GPIO_FUNC40_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x01d0)
+#define GPIO_GPIO_SIG40_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG40_IN_SEL_S 7
+#define GPIO_GPIO_FUNC40_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC40_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC40_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC40_IN_SEL_S 0
+
+#define GPIO_FUNC41_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x01d4)
+#define GPIO_GPIO_SIG41_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG41_IN_SEL_S 7
+#define GPIO_GPIO_FUNC41_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC41_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC41_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC41_IN_SEL_S 0
+
+#define GPIO_FUNC42_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x01d8)
+#define GPIO_GPIO_SIG42_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG42_IN_SEL_S 7
+#define GPIO_GPIO_FUNC42_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC42_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC42_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC42_IN_SEL_S 0
+
+#define GPIO_FUNC43_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x01dc)
+#define GPIO_GPIO_SIG43_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG43_IN_SEL_S 7
+#define GPIO_GPIO_FUNC43_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC43_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC43_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC43_IN_SEL_S 0
+
+#define GPIO_FUNC44_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x01e0)
+#define GPIO_GPIO_SIG44_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG44_IN_SEL_S 7
+#define GPIO_GPIO_FUNC44_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC44_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC44_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC44_IN_SEL_S 0
+
+#define GPIO_FUNC45_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x01e4)
+#define GPIO_GPIO_SIG45_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG45_IN_SEL_S 7
+#define GPIO_GPIO_FUNC45_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC45_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC45_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC45_IN_SEL_S 0
+
+#define GPIO_FUNC46_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x01e8)
+#define GPIO_GPIO_SIG46_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG46_IN_SEL_S 7
+#define GPIO_GPIO_FUNC46_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC46_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC46_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC46_IN_SEL_S 0
+
+#define GPIO_FUNC47_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x01ec)
+#define GPIO_GPIO_SIG47_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG47_IN_SEL_S 7
+#define GPIO_GPIO_FUNC47_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC47_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC47_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC47_IN_SEL_S 0
+
+#define GPIO_FUNC48_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x01f0)
+#define GPIO_GPIO_SIG48_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG48_IN_SEL_S 7
+#define GPIO_GPIO_FUNC48_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC48_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC48_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC48_IN_SEL_S 0
+
+#define GPIO_FUNC49_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x01f4)
+#define GPIO_GPIO_SIG49_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG49_IN_SEL_S 7
+#define GPIO_GPIO_FUNC49_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC49_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC49_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC49_IN_SEL_S 0
+
+#define GPIO_FUNC50_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x01f8)
+#define GPIO_GPIO_SIG50_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG50_IN_SEL_S 7
+#define GPIO_GPIO_FUNC50_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC50_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC50_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC50_IN_SEL_S 0
+
+#define GPIO_FUNC51_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x01fc)
+#define GPIO_GPIO_SIG51_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG51_IN_SEL_S 7
+#define GPIO_GPIO_FUNC51_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC51_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC51_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC51_IN_SEL_S 0
+
+#define GPIO_FUNC52_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0200)
+#define GPIO_GPIO_SIG52_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG52_IN_SEL_S 7
+#define GPIO_GPIO_FUNC52_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC52_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC52_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC52_IN_SEL_S 0
+
+#define GPIO_FUNC53_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0204)
+#define GPIO_GPIO_SIG53_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG53_IN_SEL_S 7
+#define GPIO_GPIO_FUNC53_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC53_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC53_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC53_IN_SEL_S 0
+
+#define GPIO_FUNC54_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0208)
+#define GPIO_GPIO_SIG54_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG54_IN_SEL_S 7
+#define GPIO_GPIO_FUNC54_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC54_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC54_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC54_IN_SEL_S 0
+
+#define GPIO_FUNC55_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x020c)
+#define GPIO_GPIO_SIG55_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG55_IN_SEL_S 7
+#define GPIO_GPIO_FUNC55_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC55_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC55_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC55_IN_SEL_S 0
+
+#define GPIO_FUNC56_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0210)
+#define GPIO_GPIO_SIG56_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG56_IN_SEL_S 7
+#define GPIO_GPIO_FUNC56_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC56_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC56_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC56_IN_SEL_S 0
+
+#define GPIO_FUNC57_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0214)
+#define GPIO_GPIO_SIG57_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG57_IN_SEL_S 7
+#define GPIO_GPIO_FUNC57_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC57_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC57_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC57_IN_SEL_S 0
+
+#define GPIO_FUNC58_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0218)
+#define GPIO_GPIO_SIG58_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG58_IN_SEL_S 7
+#define GPIO_GPIO_FUNC58_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC58_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC58_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC58_IN_SEL_S 0
+
+#define GPIO_FUNC59_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x021c)
+#define GPIO_GPIO_SIG59_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG59_IN_SEL_S 7
+#define GPIO_GPIO_FUNC59_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC59_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC59_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC59_IN_SEL_S 0
+
+#define GPIO_FUNC60_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0220)
+#define GPIO_GPIO_SIG60_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG60_IN_SEL_S 7
+#define GPIO_GPIO_FUNC60_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC60_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC60_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC60_IN_SEL_S 0
+
+#define GPIO_FUNC61_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0224)
+#define GPIO_GPIO_SIG61_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG61_IN_SEL_S 7
+#define GPIO_GPIO_FUNC61_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC61_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC61_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC61_IN_SEL_S 0
+
+#define GPIO_FUNC62_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0228)
+#define GPIO_GPIO_SIG62_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG62_IN_SEL_S 7
+#define GPIO_GPIO_FUNC62_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC62_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC62_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC62_IN_SEL_S 0
+
+#define GPIO_FUNC63_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x022c)
+#define GPIO_GPIO_SIG63_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG63_IN_SEL_S 7
+#define GPIO_GPIO_FUNC63_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC63_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC63_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC63_IN_SEL_S 0
+
+#define GPIO_FUNC64_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0230)
+#define GPIO_GPIO_SIG64_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG64_IN_SEL_S 7
+#define GPIO_GPIO_FUNC64_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC64_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC64_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC64_IN_SEL_S 0
+
+#define GPIO_FUNC65_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0234)
+#define GPIO_GPIO_SIG65_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG65_IN_SEL_S 7
+#define GPIO_GPIO_FUNC65_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC65_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC65_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC65_IN_SEL_S 0
+
+#define GPIO_FUNC66_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0238)
+#define GPIO_GPIO_SIG66_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG66_IN_SEL_S 7
+#define GPIO_GPIO_FUNC66_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC66_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC66_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC66_IN_SEL_S 0
+
+#define GPIO_FUNC67_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x023c)
+#define GPIO_GPIO_SIG67_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG67_IN_SEL_S 7
+#define GPIO_GPIO_FUNC67_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC67_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC67_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC67_IN_SEL_S 0
+
+#define GPIO_FUNC68_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0240)
+#define GPIO_GPIO_SIG68_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG68_IN_SEL_S 7
+#define GPIO_GPIO_FUNC68_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC68_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC68_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC68_IN_SEL_S 0
+
+#define GPIO_FUNC69_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0244)
+#define GPIO_GPIO_SIG69_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG69_IN_SEL_S 7
+#define GPIO_GPIO_FUNC69_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC69_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC69_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC69_IN_SEL_S 0
+
+#define GPIO_FUNC70_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0248)
+#define GPIO_GPIO_SIG70_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG70_IN_SEL_S 7
+#define GPIO_GPIO_FUNC70_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC70_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC70_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC70_IN_SEL_S 0
+
+#define GPIO_FUNC71_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x024c)
+#define GPIO_GPIO_SIG71_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG71_IN_SEL_S 7
+#define GPIO_GPIO_FUNC71_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC71_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC71_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC71_IN_SEL_S 0
+
+#define GPIO_FUNC72_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0250)
+#define GPIO_GPIO_SIG72_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG72_IN_SEL_S 7
+#define GPIO_GPIO_FUNC72_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC72_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC72_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC72_IN_SEL_S 0
+
+#define GPIO_FUNC73_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0254)
+#define GPIO_GPIO_SIG73_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG73_IN_SEL_S 7
+#define GPIO_GPIO_FUNC73_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC73_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC73_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC73_IN_SEL_S 0
+
+#define GPIO_FUNC74_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0258)
+#define GPIO_GPIO_SIG74_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG74_IN_SEL_S 7
+#define GPIO_GPIO_FUNC74_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC74_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC74_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC74_IN_SEL_S 0
+
+#define GPIO_FUNC75_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x025c)
+#define GPIO_GPIO_SIG75_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG75_IN_SEL_S 7
+#define GPIO_GPIO_FUNC75_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC75_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC75_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC75_IN_SEL_S 0
+
+#define GPIO_FUNC76_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0260)
+#define GPIO_GPIO_SIG76_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG76_IN_SEL_S 7
+#define GPIO_GPIO_FUNC76_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC76_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC76_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC76_IN_SEL_S 0
+
+#define GPIO_FUNC77_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0264)
+#define GPIO_GPIO_SIG77_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG77_IN_SEL_S 7
+#define GPIO_GPIO_FUNC77_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC77_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC77_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC77_IN_SEL_S 0
+
+#define GPIO_FUNC78_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0268)
+#define GPIO_GPIO_SIG78_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG78_IN_SEL_S 7
+#define GPIO_GPIO_FUNC78_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC78_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC78_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC78_IN_SEL_S 0
+
+#define GPIO_FUNC79_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x026c)
+#define GPIO_GPIO_SIG79_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG79_IN_SEL_S 7
+#define GPIO_GPIO_FUNC79_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC79_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC79_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC79_IN_SEL_S 0
+
+#define GPIO_FUNC80_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0270)
+#define GPIO_GPIO_SIG80_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG80_IN_SEL_S 7
+#define GPIO_GPIO_FUNC80_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC80_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC80_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC80_IN_SEL_S 0
+
+#define GPIO_FUNC81_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0274)
+#define GPIO_GPIO_SIG81_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG81_IN_SEL_S 7
+#define GPIO_GPIO_FUNC81_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC81_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC81_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC81_IN_SEL_S 0
+
+#define GPIO_FUNC82_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0278)
+#define GPIO_GPIO_SIG82_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG82_IN_SEL_S 7
+#define GPIO_GPIO_FUNC82_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC82_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC82_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC82_IN_SEL_S 0
+
+#define GPIO_FUNC83_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x027c)
+#define GPIO_GPIO_SIG83_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG83_IN_SEL_S 7
+#define GPIO_GPIO_FUNC83_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC83_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC83_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC83_IN_SEL_S 0
+
+#define GPIO_FUNC84_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0280)
+#define GPIO_GPIO_SIG84_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG84_IN_SEL_S 7
+#define GPIO_GPIO_FUNC84_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC84_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC84_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC84_IN_SEL_S 0
+
+#define GPIO_FUNC85_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0284)
+#define GPIO_GPIO_SIG85_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG85_IN_SEL_S 7
+#define GPIO_GPIO_FUNC85_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC85_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC85_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC85_IN_SEL_S 0
+
+#define GPIO_FUNC86_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0288)
+#define GPIO_GPIO_SIG86_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG86_IN_SEL_S 7
+#define GPIO_GPIO_FUNC86_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC86_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC86_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC86_IN_SEL_S 0
+
+#define GPIO_FUNC87_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x028c)
+#define GPIO_GPIO_SIG87_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG87_IN_SEL_S 7
+#define GPIO_GPIO_FUNC87_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC87_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC87_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC87_IN_SEL_S 0
+
+#define GPIO_FUNC88_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0290)
+#define GPIO_GPIO_SIG88_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG88_IN_SEL_S 7
+#define GPIO_GPIO_FUNC88_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC88_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC88_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC88_IN_SEL_S 0
+
+#define GPIO_FUNC89_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0294)
+#define GPIO_GPIO_SIG89_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG89_IN_SEL_S 7
+#define GPIO_GPIO_FUNC89_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC89_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC89_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC89_IN_SEL_S 0
+
+#define GPIO_FUNC90_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0298)
+#define GPIO_GPIO_SIG90_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG90_IN_SEL_S 7
+#define GPIO_GPIO_FUNC90_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC90_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC90_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC90_IN_SEL_S 0
+
+#define GPIO_FUNC91_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x029c)
+#define GPIO_GPIO_SIG91_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG91_IN_SEL_S 7
+#define GPIO_GPIO_FUNC91_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC91_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC91_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC91_IN_SEL_S 0
+
+#define GPIO_FUNC92_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x02a0)
+#define GPIO_GPIO_SIG92_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG92_IN_SEL_S 7
+#define GPIO_GPIO_FUNC92_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC92_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC92_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC92_IN_SEL_S 0
+
+#define GPIO_FUNC93_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x02a4)
+#define GPIO_GPIO_SIG93_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG93_IN_SEL_S 7
+#define GPIO_GPIO_FUNC93_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC93_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC93_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC93_IN_SEL_S 0
+
+#define GPIO_FUNC94_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x02a8)
+#define GPIO_GPIO_SIG94_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG94_IN_SEL_S 7
+#define GPIO_GPIO_FUNC94_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC94_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC94_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC94_IN_SEL_S 0
+
+#define GPIO_FUNC95_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x02ac)
+#define GPIO_GPIO_SIG95_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG95_IN_SEL_S 7
+#define GPIO_GPIO_FUNC95_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC95_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC95_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC95_IN_SEL_S 0
+
+#define GPIO_FUNC96_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x02b0)
+#define GPIO_GPIO_SIG96_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG96_IN_SEL_S 7
+#define GPIO_GPIO_FUNC96_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC96_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC96_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC96_IN_SEL_S 0
+
+#define GPIO_FUNC97_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x02b4)
+#define GPIO_GPIO_SIG97_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG97_IN_SEL_S 7
+#define GPIO_GPIO_FUNC97_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC97_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC97_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC97_IN_SEL_S 0
+
+#define GPIO_FUNC98_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x02b8)
+#define GPIO_GPIO_SIG98_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG98_IN_SEL_S 7
+#define GPIO_GPIO_FUNC98_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC98_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC98_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC98_IN_SEL_S 0
+
+#define GPIO_FUNC99_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x02bc)
+#define GPIO_GPIO_SIG99_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG99_IN_SEL_S 7
+#define GPIO_GPIO_FUNC99_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC99_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC99_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC99_IN_SEL_S 0
+
+#define GPIO_FUNC100_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x02c0)
+#define GPIO_GPIO_SIG100_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG100_IN_SEL_S 7
+#define GPIO_GPIO_FUNC100_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC100_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC100_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC100_IN_SEL_S 0
+
+#define GPIO_FUNC101_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x02c4)
+#define GPIO_GPIO_SIG101_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG101_IN_SEL_S 7
+#define GPIO_GPIO_FUNC101_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC101_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC101_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC101_IN_SEL_S 0
+
+#define GPIO_FUNC102_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x02c8)
+#define GPIO_GPIO_SIG102_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG102_IN_SEL_S 7
+#define GPIO_GPIO_FUNC102_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC102_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC102_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC102_IN_SEL_S 0
+
+#define GPIO_FUNC103_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x02cc)
+#define GPIO_GPIO_SIG103_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG103_IN_SEL_S 7
+#define GPIO_GPIO_FUNC103_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC103_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC103_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC103_IN_SEL_S 0
+
+#define GPIO_FUNC104_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x02d0)
+#define GPIO_GPIO_SIG104_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG104_IN_SEL_S 7
+#define GPIO_GPIO_FUNC104_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC104_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC104_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC104_IN_SEL_S 0
+
+#define GPIO_FUNC105_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x02d4)
+#define GPIO_GPIO_SIG105_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG105_IN_SEL_S 7
+#define GPIO_GPIO_FUNC105_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC105_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC105_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC105_IN_SEL_S 0
+
+#define GPIO_FUNC106_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x02d8)
+#define GPIO_GPIO_SIG106_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG106_IN_SEL_S 7
+#define GPIO_GPIO_FUNC106_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC106_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC106_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC106_IN_SEL_S 0
+
+#define GPIO_FUNC107_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x02dc)
+#define GPIO_GPIO_SIG107_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG107_IN_SEL_S 7
+#define GPIO_GPIO_FUNC107_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC107_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC107_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC107_IN_SEL_S 0
+
+#define GPIO_FUNC108_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x02e0)
+#define GPIO_GPIO_SIG108_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG108_IN_SEL_S 7
+#define GPIO_GPIO_FUNC108_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC108_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC108_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC108_IN_SEL_S 0
+
+#define GPIO_FUNC109_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x02e4)
+#define GPIO_GPIO_SIG109_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG109_IN_SEL_S 7
+#define GPIO_GPIO_FUNC109_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC109_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC109_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC109_IN_SEL_S 0
+
+#define GPIO_FUNC110_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x02e8)
+#define GPIO_GPIO_SIG110_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG110_IN_SEL_S 7
+#define GPIO_GPIO_FUNC110_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC110_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC110_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC110_IN_SEL_S 0
+
+#define GPIO_FUNC111_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x02ec)
+#define GPIO_GPIO_SIG111_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG111_IN_SEL_S 7
+#define GPIO_GPIO_FUNC111_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC111_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC111_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC111_IN_SEL_S 0
+
+#define GPIO_FUNC112_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x02f0)
+#define GPIO_GPIO_SIG112_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG112_IN_SEL_S 7
+#define GPIO_GPIO_FUNC112_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC112_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC112_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC112_IN_SEL_S 0
+
+#define GPIO_FUNC113_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x02f4)
+#define GPIO_GPIO_SIG113_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG113_IN_SEL_S 7
+#define GPIO_GPIO_FUNC113_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC113_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC113_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC113_IN_SEL_S 0
+
+#define GPIO_FUNC114_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x02f8)
+#define GPIO_GPIO_SIG114_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG114_IN_SEL_S 7
+#define GPIO_GPIO_FUNC114_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC114_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC114_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC114_IN_SEL_S 0
+
+#define GPIO_FUNC115_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x02fc)
+#define GPIO_GPIO_SIG115_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG115_IN_SEL_S 7
+#define GPIO_GPIO_FUNC115_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC115_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC115_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC115_IN_SEL_S 0
+
+#define GPIO_FUNC116_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0300)
+#define GPIO_GPIO_SIG116_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG116_IN_SEL_S 7
+#define GPIO_GPIO_FUNC116_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC116_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC116_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC116_IN_SEL_S 0
+
+#define GPIO_FUNC117_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0304)
+#define GPIO_GPIO_SIG117_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG117_IN_SEL_S 7
+#define GPIO_GPIO_FUNC117_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC117_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC117_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC117_IN_SEL_S 0
+
+#define GPIO_FUNC118_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0308)
+#define GPIO_GPIO_SIG118_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG118_IN_SEL_S 7
+#define GPIO_GPIO_FUNC118_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC118_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC118_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC118_IN_SEL_S 0
+
+#define GPIO_FUNC119_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x030c)
+#define GPIO_GPIO_SIG119_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG119_IN_SEL_S 7
+#define GPIO_GPIO_FUNC119_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC119_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC119_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC119_IN_SEL_S 0
+
+#define GPIO_FUNC120_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0310)
+#define GPIO_GPIO_SIG120_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG120_IN_SEL_S 7
+#define GPIO_GPIO_FUNC120_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC120_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC120_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC120_IN_SEL_S 0
+
+#define GPIO_FUNC121_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0314)
+#define GPIO_GPIO_SIG121_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG121_IN_SEL_S 7
+#define GPIO_GPIO_FUNC121_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC121_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC121_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC121_IN_SEL_S 0
+
+#define GPIO_FUNC122_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0318)
+#define GPIO_GPIO_SIG122_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG122_IN_SEL_S 7
+#define GPIO_GPIO_FUNC122_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC122_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC122_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC122_IN_SEL_S 0
+
+#define GPIO_FUNC123_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x031c)
+#define GPIO_GPIO_SIG123_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG123_IN_SEL_S 7
+#define GPIO_GPIO_FUNC123_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC123_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC123_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC123_IN_SEL_S 0
+
+#define GPIO_FUNC124_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0320)
+#define GPIO_GPIO_SIG124_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG124_IN_SEL_S 7
+#define GPIO_GPIO_FUNC124_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC124_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC124_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC124_IN_SEL_S 0
+
+#define GPIO_FUNC125_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0324)
+#define GPIO_GPIO_SIG125_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG125_IN_SEL_S 7
+#define GPIO_GPIO_FUNC125_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC125_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC125_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC125_IN_SEL_S 0
+
+#define GPIO_FUNC126_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0328)
+#define GPIO_GPIO_SIG126_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG126_IN_SEL_S 7
+#define GPIO_GPIO_FUNC126_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC126_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC126_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC126_IN_SEL_S 0
+
+#define GPIO_FUNC127_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x032c)
+#define GPIO_GPIO_SIG127_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG127_IN_SEL_S 7
+#define GPIO_GPIO_FUNC127_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC127_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC127_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC127_IN_SEL_S 0
+
+#define GPIO_FUNC128_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0330)
+#define GPIO_GPIO_SIG128_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG128_IN_SEL_S 7
+#define GPIO_GPIO_FUNC128_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC128_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC128_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC128_IN_SEL_S 0
+
+#define GPIO_FUNC129_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0334)
+#define GPIO_GPIO_SIG129_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG129_IN_SEL_S 7
+#define GPIO_GPIO_FUNC129_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC129_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC129_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC129_IN_SEL_S 0
+
+#define GPIO_FUNC130_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0338)
+#define GPIO_GPIO_SIG130_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG130_IN_SEL_S 7
+#define GPIO_GPIO_FUNC130_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC130_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC130_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC130_IN_SEL_S 0
+
+#define GPIO_FUNC131_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x033c)
+#define GPIO_GPIO_SIG131_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG131_IN_SEL_S 7
+#define GPIO_GPIO_FUNC131_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC131_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC131_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC131_IN_SEL_S 0
+
+#define GPIO_FUNC132_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0340)
+#define GPIO_GPIO_SIG132_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG132_IN_SEL_S 7
+#define GPIO_GPIO_FUNC132_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC132_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC132_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC132_IN_SEL_S 0
+
+#define GPIO_FUNC133_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0344)
+#define GPIO_GPIO_SIG133_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG133_IN_SEL_S 7
+#define GPIO_GPIO_FUNC133_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC133_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC133_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC133_IN_SEL_S 0
+
+#define GPIO_FUNC134_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0348)
+#define GPIO_GPIO_SIG134_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG134_IN_SEL_S 7
+#define GPIO_GPIO_FUNC134_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC134_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC134_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC134_IN_SEL_S 0
+
+#define GPIO_FUNC135_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x034c)
+#define GPIO_GPIO_SIG135_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG135_IN_SEL_S 7
+#define GPIO_GPIO_FUNC135_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC135_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC135_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC135_IN_SEL_S 0
+
+#define GPIO_FUNC136_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0350)
+#define GPIO_GPIO_SIG136_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG136_IN_SEL_S 7
+#define GPIO_GPIO_FUNC136_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC136_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC136_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC136_IN_SEL_S 0
+
+#define GPIO_FUNC137_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0354)
+#define GPIO_GPIO_SIG137_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG137_IN_SEL_S 7
+#define GPIO_GPIO_FUNC137_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC137_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC137_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC137_IN_SEL_S 0
+
+#define GPIO_FUNC138_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0358)
+#define GPIO_GPIO_SIG138_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG138_IN_SEL_S 7
+#define GPIO_GPIO_FUNC138_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC138_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC138_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC138_IN_SEL_S 0
+
+#define GPIO_FUNC139_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x035c)
+#define GPIO_GPIO_SIG139_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG139_IN_SEL_S 7
+#define GPIO_GPIO_FUNC139_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC139_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC139_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC139_IN_SEL_S 0
+
+#define GPIO_FUNC140_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0360)
+#define GPIO_GPIO_SIG140_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG140_IN_SEL_S 7
+#define GPIO_GPIO_FUNC140_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC140_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC140_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC140_IN_SEL_S 0
+
+#define GPIO_FUNC141_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0364)
+#define GPIO_GPIO_SIG141_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG141_IN_SEL_S 7
+#define GPIO_GPIO_FUNC141_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC141_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC141_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC141_IN_SEL_S 0
+
+#define GPIO_FUNC142_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0368)
+#define GPIO_GPIO_SIG142_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG142_IN_SEL_S 7
+#define GPIO_GPIO_FUNC142_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC142_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC142_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC142_IN_SEL_S 0
+
+#define GPIO_FUNC143_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x036c)
+#define GPIO_GPIO_SIG143_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG143_IN_SEL_S 7
+#define GPIO_GPIO_FUNC143_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC143_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC143_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC143_IN_SEL_S 0
+
+#define GPIO_FUNC144_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0370)
+#define GPIO_GPIO_SIG144_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG144_IN_SEL_S 7
+#define GPIO_GPIO_FUNC144_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC144_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC144_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC144_IN_SEL_S 0
+
+#define GPIO_FUNC145_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0374)
+#define GPIO_GPIO_SIG145_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG145_IN_SEL_S 7
+#define GPIO_GPIO_FUNC145_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC145_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC145_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC145_IN_SEL_S 0
+
+#define GPIO_FUNC146_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0378)
+#define GPIO_GPIO_SIG146_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG146_IN_SEL_S 7
+#define GPIO_GPIO_FUNC146_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC146_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC146_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC146_IN_SEL_S 0
+
+#define GPIO_FUNC147_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x037c)
+#define GPIO_GPIO_SIG147_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG147_IN_SEL_S 7
+#define GPIO_GPIO_FUNC147_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC147_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC147_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC147_IN_SEL_S 0
+
+#define GPIO_FUNC148_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0380)
+#define GPIO_GPIO_SIG148_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG148_IN_SEL_S 7
+#define GPIO_GPIO_FUNC148_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC148_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC148_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC148_IN_SEL_S 0
+
+#define GPIO_FUNC149_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0384)
+#define GPIO_GPIO_SIG149_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG149_IN_SEL_S 7
+#define GPIO_GPIO_FUNC149_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC149_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC149_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC149_IN_SEL_S 0
+
+#define GPIO_FUNC150_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0388)
+#define GPIO_GPIO_SIG150_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG150_IN_SEL_S 7
+#define GPIO_GPIO_FUNC150_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC150_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC150_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC150_IN_SEL_S 0
+
+#define GPIO_FUNC151_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x038c)
+#define GPIO_GPIO_SIG151_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG151_IN_SEL_S 7
+#define GPIO_GPIO_FUNC151_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC151_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC151_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC151_IN_SEL_S 0
+
+#define GPIO_FUNC152_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0390)
+#define GPIO_GPIO_SIG152_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG152_IN_SEL_S 7
+#define GPIO_GPIO_FUNC152_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC152_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC152_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC152_IN_SEL_S 0
+
+#define GPIO_FUNC153_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0394)
+#define GPIO_GPIO_SIG153_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG153_IN_SEL_S 7
+#define GPIO_GPIO_FUNC153_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC153_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC153_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC153_IN_SEL_S 0
+
+#define GPIO_FUNC154_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0398)
+#define GPIO_GPIO_SIG154_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG154_IN_SEL_S 7
+#define GPIO_GPIO_FUNC154_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC154_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC154_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC154_IN_SEL_S 0
+
+#define GPIO_FUNC155_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x039c)
+#define GPIO_GPIO_SIG155_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG155_IN_SEL_S 7
+#define GPIO_GPIO_FUNC155_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC155_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC155_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC155_IN_SEL_S 0
+
+#define GPIO_FUNC156_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x03a0)
+#define GPIO_GPIO_SIG156_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG156_IN_SEL_S 7
+#define GPIO_GPIO_FUNC156_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC156_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC156_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC156_IN_SEL_S 0
+
+#define GPIO_FUNC157_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x03a4)
+#define GPIO_GPIO_SIG157_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG157_IN_SEL_S 7
+#define GPIO_GPIO_FUNC157_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC157_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC157_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC157_IN_SEL_S 0
+
+#define GPIO_FUNC158_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x03a8)
+#define GPIO_GPIO_SIG158_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG158_IN_SEL_S 7
+#define GPIO_GPIO_FUNC158_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC158_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC158_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC158_IN_SEL_S 0
+
+#define GPIO_FUNC159_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x03ac)
+#define GPIO_GPIO_SIG159_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG159_IN_SEL_S 7
+#define GPIO_GPIO_FUNC159_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC159_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC159_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC159_IN_SEL_S 0
+
+#define GPIO_FUNC160_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x03b0)
+#define GPIO_GPIO_SIG160_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG160_IN_SEL_S 7
+#define GPIO_GPIO_FUNC160_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC160_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC160_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC160_IN_SEL_S 0
+
+#define GPIO_FUNC161_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x03b4)
+#define GPIO_GPIO_SIG161_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG161_IN_SEL_S 7
+#define GPIO_GPIO_FUNC161_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC161_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC161_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC161_IN_SEL_S 0
+
+#define GPIO_FUNC162_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x03b8)
+#define GPIO_GPIO_SIG162_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG162_IN_SEL_S 7
+#define GPIO_GPIO_FUNC162_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC162_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC162_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC162_IN_SEL_S 0
+
+#define GPIO_FUNC163_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x03bc)
+#define GPIO_GPIO_SIG163_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG163_IN_SEL_S 7
+#define GPIO_GPIO_FUNC163_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC163_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC163_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC163_IN_SEL_S 0
+
+#define GPIO_FUNC164_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x03c0)
+#define GPIO_GPIO_SIG164_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG164_IN_SEL_S 7
+#define GPIO_GPIO_FUNC164_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC164_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC164_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC164_IN_SEL_S 0
+
+#define GPIO_FUNC165_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x03c4)
+#define GPIO_GPIO_SIG165_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG165_IN_SEL_S 7
+#define GPIO_GPIO_FUNC165_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC165_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC165_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC165_IN_SEL_S 0
+
+#define GPIO_FUNC166_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x03c8)
+#define GPIO_GPIO_SIG166_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG166_IN_SEL_S 7
+#define GPIO_GPIO_FUNC166_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC166_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC166_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC166_IN_SEL_S 0
+
+#define GPIO_FUNC167_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x03cc)
+#define GPIO_GPIO_SIG167_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG167_IN_SEL_S 7
+#define GPIO_GPIO_FUNC167_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC167_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC167_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC167_IN_SEL_S 0
+
+#define GPIO_FUNC168_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x03d0)
+#define GPIO_GPIO_SIG168_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG168_IN_SEL_S 7
+#define GPIO_GPIO_FUNC168_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC168_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC168_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC168_IN_SEL_S 0
+
+#define GPIO_FUNC169_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x03d4)
+#define GPIO_GPIO_SIG169_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG169_IN_SEL_S 7
+#define GPIO_GPIO_FUNC169_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC169_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC169_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC169_IN_SEL_S 0
+
+#define GPIO_FUNC170_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x03d8)
+#define GPIO_GPIO_SIG170_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG170_IN_SEL_S 7
+#define GPIO_GPIO_FUNC170_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC170_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC170_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC170_IN_SEL_S 0
+
+#define GPIO_FUNC171_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x03dc)
+#define GPIO_GPIO_SIG171_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG171_IN_SEL_S 7
+#define GPIO_GPIO_FUNC171_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC171_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC171_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC171_IN_SEL_S 0
+
+#define GPIO_FUNC172_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x03e0)
+#define GPIO_GPIO_SIG172_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG172_IN_SEL_S 7
+#define GPIO_GPIO_FUNC172_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC172_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC172_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC172_IN_SEL_S 0
+
+#define GPIO_FUNC173_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x03e4)
+#define GPIO_GPIO_SIG173_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG173_IN_SEL_S 7
+#define GPIO_GPIO_FUNC173_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC173_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC173_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC173_IN_SEL_S 0
+
+#define GPIO_FUNC174_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x03e8)
+#define GPIO_GPIO_SIG174_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG174_IN_SEL_S 7
+#define GPIO_GPIO_FUNC174_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC174_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC174_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC174_IN_SEL_S 0
+
+#define GPIO_FUNC175_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x03ec)
+#define GPIO_GPIO_SIG175_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG175_IN_SEL_S 7
+#define GPIO_GPIO_FUNC175_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC175_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC175_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC175_IN_SEL_S 0
+
+#define GPIO_FUNC176_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x03f0)
+#define GPIO_GPIO_SIG176_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG176_IN_SEL_S 7
+#define GPIO_GPIO_FUNC176_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC176_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC176_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC176_IN_SEL_S 0
+
+#define GPIO_FUNC177_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x03f4)
+#define GPIO_GPIO_SIG177_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG177_IN_SEL_S 7
+#define GPIO_GPIO_FUNC177_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC177_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC177_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC177_IN_SEL_S 0
+
+#define GPIO_FUNC178_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x03f8)
+#define GPIO_GPIO_SIG178_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG178_IN_SEL_S 7
+#define GPIO_GPIO_FUNC178_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC178_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC178_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC178_IN_SEL_S 0
+
+#define GPIO_FUNC179_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x03fc)
+#define GPIO_GPIO_SIG179_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG179_IN_SEL_S 7
+#define GPIO_GPIO_FUNC179_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC179_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC179_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC179_IN_SEL_S 0
+
+#define GPIO_FUNC180_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0400)
+#define GPIO_GPIO_SIG180_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG180_IN_SEL_S 7
+#define GPIO_GPIO_FUNC180_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC180_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC180_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC180_IN_SEL_S 0
+
+#define GPIO_FUNC181_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0404)
+#define GPIO_GPIO_SIG181_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG181_IN_SEL_S 7
+#define GPIO_GPIO_FUNC181_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC181_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC181_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC181_IN_SEL_S 0
+
+#define GPIO_FUNC182_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0408)
+#define GPIO_GPIO_SIG182_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG182_IN_SEL_S 7
+#define GPIO_GPIO_FUNC182_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC182_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC182_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC182_IN_SEL_S 0
+
+#define GPIO_FUNC183_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x040c)
+#define GPIO_GPIO_SIG183_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG183_IN_SEL_S 7
+#define GPIO_GPIO_FUNC183_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC183_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC183_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC183_IN_SEL_S 0
+
+#define GPIO_FUNC184_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0410)
+#define GPIO_GPIO_SIG184_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG184_IN_SEL_S 7
+#define GPIO_GPIO_FUNC184_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC184_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC184_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC184_IN_SEL_S 0
+
+#define GPIO_FUNC185_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0414)
+#define GPIO_GPIO_SIG185_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG185_IN_SEL_S 7
+#define GPIO_GPIO_FUNC185_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC185_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC185_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC185_IN_SEL_S 0
+
+#define GPIO_FUNC186_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0418)
+#define GPIO_GPIO_SIG186_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG186_IN_SEL_S 7
+#define GPIO_GPIO_FUNC186_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC186_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC186_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC186_IN_SEL_S 0
+
+#define GPIO_FUNC187_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x041c)
+#define GPIO_GPIO_SIG187_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG187_IN_SEL_S 7
+#define GPIO_GPIO_FUNC187_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC187_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC187_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC187_IN_SEL_S 0
+
+#define GPIO_FUNC188_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0420)
+#define GPIO_GPIO_SIG188_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG188_IN_SEL_S 7
+#define GPIO_GPIO_FUNC188_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC188_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC188_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC188_IN_SEL_S 0
+
+#define GPIO_FUNC189_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0424)
+#define GPIO_GPIO_SIG189_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG189_IN_SEL_S 7
+#define GPIO_GPIO_FUNC189_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC189_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC189_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC189_IN_SEL_S 0
+
+#define GPIO_FUNC190_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0428)
+#define GPIO_GPIO_SIG190_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG190_IN_SEL_S 7
+#define GPIO_GPIO_FUNC190_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC190_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC190_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC190_IN_SEL_S 0
+
+#define GPIO_FUNC191_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x042c)
+#define GPIO_GPIO_SIG191_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG191_IN_SEL_S 7
+#define GPIO_GPIO_FUNC191_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC191_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC191_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC191_IN_SEL_S 0
+
+#define GPIO_FUNC192_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0430)
+#define GPIO_GPIO_SIG192_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG192_IN_SEL_S 7
+#define GPIO_GPIO_FUNC192_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC192_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC192_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC192_IN_SEL_S 0
+
+#define GPIO_FUNC193_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0434)
+#define GPIO_GPIO_SIG193_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG193_IN_SEL_S 7
+#define GPIO_GPIO_FUNC193_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC193_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC193_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC193_IN_SEL_S 0
+
+#define GPIO_FUNC194_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0438)
+#define GPIO_GPIO_SIG194_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG194_IN_SEL_S 7
+#define GPIO_GPIO_FUNC194_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC194_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC194_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC194_IN_SEL_S 0
+
+#define GPIO_FUNC195_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x043c)
+#define GPIO_GPIO_SIG195_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG195_IN_SEL_S 7
+#define GPIO_GPIO_FUNC195_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC195_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC195_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC195_IN_SEL_S 0
+
+#define GPIO_FUNC196_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0440)
+#define GPIO_GPIO_SIG196_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG196_IN_SEL_S 7
+#define GPIO_GPIO_FUNC196_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC196_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC196_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC196_IN_SEL_S 0
+
+#define GPIO_FUNC197_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0444)
+#define GPIO_GPIO_SIG197_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG197_IN_SEL_S 7
+#define GPIO_GPIO_FUNC197_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC197_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC197_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC197_IN_SEL_S 0
+
+#define GPIO_FUNC198_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0448)
+#define GPIO_GPIO_SIG198_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG198_IN_SEL_S 7
+#define GPIO_GPIO_FUNC198_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC198_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC198_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC198_IN_SEL_S 0
+
+#define GPIO_FUNC199_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x044c)
+#define GPIO_GPIO_SIG199_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG199_IN_SEL_S 7
+#define GPIO_GPIO_FUNC199_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC199_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC199_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC199_IN_SEL_S 0
+
+#define GPIO_FUNC200_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0450)
+#define GPIO_GPIO_SIG200_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG200_IN_SEL_S 7
+#define GPIO_GPIO_FUNC200_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC200_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC200_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC200_IN_SEL_S 0
+
+#define GPIO_FUNC201_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0454)
+#define GPIO_GPIO_SIG201_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG201_IN_SEL_S 7
+#define GPIO_GPIO_FUNC201_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC201_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC201_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC201_IN_SEL_S 0
+
+#define GPIO_FUNC202_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0458)
+#define GPIO_GPIO_SIG202_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG202_IN_SEL_S 7
+#define GPIO_GPIO_FUNC202_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC202_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC202_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC202_IN_SEL_S 0
+
+#define GPIO_FUNC203_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x045c)
+#define GPIO_GPIO_SIG203_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG203_IN_SEL_S 7
+#define GPIO_GPIO_FUNC203_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC203_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC203_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC203_IN_SEL_S 0
+
+#define GPIO_FUNC204_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0460)
+#define GPIO_GPIO_SIG204_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG204_IN_SEL_S 7
+#define GPIO_GPIO_FUNC204_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC204_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC204_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC204_IN_SEL_S 0
+
+#define GPIO_FUNC205_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0464)
+#define GPIO_GPIO_SIG205_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG205_IN_SEL_S 7
+#define GPIO_GPIO_FUNC205_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC205_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC205_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC205_IN_SEL_S 0
+
+#define GPIO_FUNC206_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0468)
+#define GPIO_GPIO_SIG206_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG206_IN_SEL_S 7
+#define GPIO_GPIO_FUNC206_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC206_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC206_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC206_IN_SEL_S 0
+
+#define GPIO_FUNC207_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x046c)
+#define GPIO_GPIO_SIG207_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG207_IN_SEL_S 7
+#define GPIO_GPIO_FUNC207_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC207_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC207_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC207_IN_SEL_S 0
+
+#define GPIO_FUNC208_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0470)
+#define GPIO_GPIO_SIG208_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG208_IN_SEL_S 7
+#define GPIO_GPIO_FUNC208_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC208_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC208_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC208_IN_SEL_S 0
+
+#define GPIO_FUNC209_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0474)
+#define GPIO_GPIO_SIG209_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG209_IN_SEL_S 7
+#define GPIO_GPIO_FUNC209_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC209_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC209_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC209_IN_SEL_S 0
+
+#define GPIO_FUNC210_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0478)
+#define GPIO_GPIO_SIG210_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG210_IN_SEL_S 7
+#define GPIO_GPIO_FUNC210_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC210_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC210_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC210_IN_SEL_S 0
+
+#define GPIO_FUNC211_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x047c)
+#define GPIO_GPIO_SIG211_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG211_IN_SEL_S 7
+#define GPIO_GPIO_FUNC211_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC211_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC211_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC211_IN_SEL_S 0
+
+#define GPIO_FUNC212_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0480)
+#define GPIO_GPIO_SIG212_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG212_IN_SEL_S 7
+#define GPIO_GPIO_FUNC212_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC212_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC212_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC212_IN_SEL_S 0
+
+#define GPIO_FUNC213_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0484)
+#define GPIO_GPIO_SIG213_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG213_IN_SEL_S 7
+#define GPIO_GPIO_FUNC213_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC213_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC213_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC213_IN_SEL_S 0
+
+#define GPIO_FUNC214_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0488)
+#define GPIO_GPIO_SIG214_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG214_IN_SEL_S 7
+#define GPIO_GPIO_FUNC214_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC214_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC214_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC214_IN_SEL_S 0
+
+#define GPIO_FUNC215_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x048c)
+#define GPIO_GPIO_SIG215_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG215_IN_SEL_S 7
+#define GPIO_GPIO_FUNC215_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC215_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC215_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC215_IN_SEL_S 0
+
+#define GPIO_FUNC216_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0490)
+#define GPIO_GPIO_SIG216_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG216_IN_SEL_S 7
+#define GPIO_GPIO_FUNC216_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC216_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC216_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC216_IN_SEL_S 0
+
+#define GPIO_FUNC217_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0494)
+#define GPIO_GPIO_SIG217_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG217_IN_SEL_S 7
+#define GPIO_GPIO_FUNC217_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC217_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC217_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC217_IN_SEL_S 0
+
+#define GPIO_FUNC218_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0498)
+#define GPIO_GPIO_SIG218_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG218_IN_SEL_S 7
+#define GPIO_GPIO_FUNC218_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC218_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC218_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC218_IN_SEL_S 0
+
+#define GPIO_FUNC219_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x049c)
+#define GPIO_GPIO_SIG219_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG219_IN_SEL_S 7
+#define GPIO_GPIO_FUNC219_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC219_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC219_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC219_IN_SEL_S 0
+
+#define GPIO_FUNC220_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x04a0)
+#define GPIO_GPIO_SIG220_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG220_IN_SEL_S 7
+#define GPIO_GPIO_FUNC220_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC220_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC220_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC220_IN_SEL_S 0
+
+#define GPIO_FUNC221_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x04a4)
+#define GPIO_GPIO_SIG221_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG221_IN_SEL_S 7
+#define GPIO_GPIO_FUNC221_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC221_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC221_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC221_IN_SEL_S 0
+
+#define GPIO_FUNC222_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x04a8)
+#define GPIO_GPIO_SIG222_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG222_IN_SEL_S 7
+#define GPIO_GPIO_FUNC222_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC222_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC222_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC222_IN_SEL_S 0
+
+#define GPIO_FUNC223_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x04ac)
+#define GPIO_GPIO_SIG223_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG223_IN_SEL_S 7
+#define GPIO_GPIO_FUNC223_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC223_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC223_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC223_IN_SEL_S 0
+
+#define GPIO_FUNC224_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x04b0)
+#define GPIO_GPIO_SIG224_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG224_IN_SEL_S 7
+#define GPIO_GPIO_FUNC224_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC224_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC224_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC224_IN_SEL_S 0
+
+#define GPIO_FUNC225_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x04b4)
+#define GPIO_GPIO_SIG225_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG225_IN_SEL_S 7
+#define GPIO_GPIO_FUNC225_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC225_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC225_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC225_IN_SEL_S 0
+
+#define GPIO_FUNC226_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x04b8)
+#define GPIO_GPIO_SIG226_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG226_IN_SEL_S 7
+#define GPIO_GPIO_FUNC226_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC226_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC226_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC226_IN_SEL_S 0
+
+#define GPIO_FUNC227_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x04bc)
+#define GPIO_GPIO_SIG227_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG227_IN_SEL_S 7
+#define GPIO_GPIO_FUNC227_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC227_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC227_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC227_IN_SEL_S 0
+
+#define GPIO_FUNC228_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x04c0)
+#define GPIO_GPIO_SIG228_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG228_IN_SEL_S 7
+#define GPIO_GPIO_FUNC228_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC228_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC228_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC228_IN_SEL_S 0
+
+#define GPIO_FUNC229_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x04c4)
+#define GPIO_GPIO_SIG229_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG229_IN_SEL_S 7
+#define GPIO_GPIO_FUNC229_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC229_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC229_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC229_IN_SEL_S 0
+
+#define GPIO_FUNC230_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x04c8)
+#define GPIO_GPIO_SIG230_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG230_IN_SEL_S 7
+#define GPIO_GPIO_FUNC230_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC230_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC230_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC230_IN_SEL_S 0
+
+#define GPIO_FUNC231_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x04cc)
+#define GPIO_GPIO_SIG231_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG231_IN_SEL_S 7
+#define GPIO_GPIO_FUNC231_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC231_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC231_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC231_IN_SEL_S 0
+
+#define GPIO_FUNC232_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x04d0)
+#define GPIO_GPIO_SIG232_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG232_IN_SEL_S 7
+#define GPIO_GPIO_FUNC232_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC232_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC232_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC232_IN_SEL_S 0
+
+#define GPIO_FUNC233_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x04d4)
+#define GPIO_GPIO_SIG233_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG233_IN_SEL_S 7
+#define GPIO_GPIO_FUNC233_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC233_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC233_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC233_IN_SEL_S 0
+
+#define GPIO_FUNC234_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x04d8)
+#define GPIO_GPIO_SIG234_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG234_IN_SEL_S 7
+#define GPIO_GPIO_FUNC234_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC234_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC234_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC234_IN_SEL_S 0
+
+#define GPIO_FUNC235_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x04dc)
+#define GPIO_GPIO_SIG235_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG235_IN_SEL_S 7
+#define GPIO_GPIO_FUNC235_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC235_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC235_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC235_IN_SEL_S 0
+
+#define GPIO_FUNC236_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x04e0)
+#define GPIO_GPIO_SIG236_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG236_IN_SEL_S 7
+#define GPIO_GPIO_FUNC236_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC236_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC236_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC236_IN_SEL_S 0
+
+#define GPIO_FUNC237_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x04e4)
+#define GPIO_GPIO_SIG237_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG237_IN_SEL_S 7
+#define GPIO_GPIO_FUNC237_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC237_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC237_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC237_IN_SEL_S 0
+
+#define GPIO_FUNC238_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x04e8)
+#define GPIO_GPIO_SIG238_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG238_IN_SEL_S 7
+#define GPIO_GPIO_FUNC238_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC238_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC238_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC238_IN_SEL_S 0
+
+#define GPIO_FUNC239_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x04ec)
+#define GPIO_GPIO_SIG239_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG239_IN_SEL_S 7
+#define GPIO_GPIO_FUNC239_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC239_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC239_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC239_IN_SEL_S 0
+
+#define GPIO_FUNC240_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x04f0)
+#define GPIO_GPIO_SIG240_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG240_IN_SEL_S 7
+#define GPIO_GPIO_FUNC240_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC240_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC240_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC240_IN_SEL_S 0
+
+#define GPIO_FUNC241_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x04f4)
+#define GPIO_GPIO_SIG241_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG241_IN_SEL_S 7
+#define GPIO_GPIO_FUNC241_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC241_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC241_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC241_IN_SEL_S 0
+
+#define GPIO_FUNC242_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x04f8)
+#define GPIO_GPIO_SIG242_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG242_IN_SEL_S 7
+#define GPIO_GPIO_FUNC242_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC242_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC242_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC242_IN_SEL_S 0
+
+#define GPIO_FUNC243_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x04fc)
+#define GPIO_GPIO_SIG243_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG243_IN_SEL_S 7
+#define GPIO_GPIO_FUNC243_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC243_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC243_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC243_IN_SEL_S 0
+
+#define GPIO_FUNC244_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0500)
+#define GPIO_GPIO_SIG244_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG244_IN_SEL_S 7
+#define GPIO_GPIO_FUNC244_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC244_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC244_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC244_IN_SEL_S 0
+
+#define GPIO_FUNC245_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0504)
+#define GPIO_GPIO_SIG245_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG245_IN_SEL_S 7
+#define GPIO_GPIO_FUNC245_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC245_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC245_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC245_IN_SEL_S 0
+
+#define GPIO_FUNC246_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0508)
+#define GPIO_GPIO_SIG246_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG246_IN_SEL_S 7
+#define GPIO_GPIO_FUNC246_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC246_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC246_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC246_IN_SEL_S 0
+
+#define GPIO_FUNC247_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x050c)
+#define GPIO_GPIO_SIG247_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG247_IN_SEL_S 7
+#define GPIO_GPIO_FUNC247_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC247_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC247_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC247_IN_SEL_S 0
+
+#define GPIO_FUNC248_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0510)
+#define GPIO_GPIO_SIG248_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG248_IN_SEL_S 7
+#define GPIO_GPIO_FUNC248_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC248_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC248_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC248_IN_SEL_S 0
+
+#define GPIO_FUNC249_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0514)
+#define GPIO_GPIO_SIG249_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG249_IN_SEL_S 7
+#define GPIO_GPIO_FUNC249_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC249_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC249_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC249_IN_SEL_S 0
+
+#define GPIO_FUNC250_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0518)
+#define GPIO_GPIO_SIG250_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG250_IN_SEL_S 7
+#define GPIO_GPIO_FUNC250_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC250_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC250_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC250_IN_SEL_S 0
+
+#define GPIO_FUNC251_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x051c)
+#define GPIO_GPIO_SIG251_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG251_IN_SEL_S 7
+#define GPIO_GPIO_FUNC251_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC251_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC251_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC251_IN_SEL_S 0
+
+#define GPIO_FUNC252_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0520)
+#define GPIO_GPIO_SIG252_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG252_IN_SEL_S 7
+#define GPIO_GPIO_FUNC252_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC252_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC252_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC252_IN_SEL_S 0
+
+#define GPIO_FUNC253_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0524)
+#define GPIO_GPIO_SIG253_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG253_IN_SEL_S 7
+#define GPIO_GPIO_FUNC253_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC253_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC253_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC253_IN_SEL_S 0
+
+#define GPIO_FUNC254_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x0528)
+#define GPIO_GPIO_SIG254_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG254_IN_SEL_S 7
+#define GPIO_GPIO_FUNC254_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC254_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC254_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC254_IN_SEL_S 0
+
+#define GPIO_FUNC255_IN_SEL_CFG (DR_REG_GPIO_BASE + 0x052c)
+#define GPIO_GPIO_SIG255_IN_SEL (BIT(7))
+#define GPIO_GPIO_SIG255_IN_SEL_S 7
+#define GPIO_GPIO_FUNC255_IN_INV_SEL (BIT(6))
+#define GPIO_GPIO_FUNC255_IN_INV_SEL_S 6
+#define GPIO_GPIO_FUNC255_IN_SEL 0x0000003F
+#define GPIO_GPIO_FUNC255_IN_SEL_S 0
+
+#define GPIO_FUNC0_OUT_SEL_CFG (DR_REG_GPIO_BASE + 0x0530)
+#define GPIO_GPIO_FUNC0_OEN_INV_SEL (BIT(11))
+#define GPIO_GPIO_FUNC0_OEN_INV_SEL_S 11
+#define GPIO_GPIO_FUNC0_OEN_SEL (BIT(10))
+#define GPIO_GPIO_FUNC0_OEN_SEL_S 10
+#define GPIO_GPIO_FUNC0_OUT_INV_SEL (BIT(9))
+#define GPIO_GPIO_FUNC0_OUT_INV_SEL_S 9
+#define GPIO_GPIO_FUNC0_OUT_SEL 0x000001FF
+#define GPIO_GPIO_FUNC0_OUT_SEL_S 0
+
+#define GPIO_FUNC1_OUT_SEL_CFG (DR_REG_GPIO_BASE + 0x0534)
+#define GPIO_GPIO_FUNC1_OEN_INV_SEL (BIT(11))
+#define GPIO_GPIO_FUNC1_OEN_INV_SEL_S 11
+#define GPIO_GPIO_FUNC1_OEN_SEL (BIT(10))
+#define GPIO_GPIO_FUNC1_OEN_SEL_S 10
+#define GPIO_GPIO_FUNC1_OUT_INV_SEL (BIT(9))
+#define GPIO_GPIO_FUNC1_OUT_INV_SEL_S 9
+#define GPIO_GPIO_FUNC1_OUT_SEL 0x000001FF
+#define GPIO_GPIO_FUNC1_OUT_SEL_S 0
+
+#define GPIO_FUNC2_OUT_SEL_CFG (DR_REG_GPIO_BASE + 0x0538)
+#define GPIO_GPIO_FUNC2_OEN_INV_SEL (BIT(11))
+#define GPIO_GPIO_FUNC2_OEN_INV_SEL_S 11
+#define GPIO_GPIO_FUNC2_OEN_SEL (BIT(10))
+#define GPIO_GPIO_FUNC2_OEN_SEL_S 10
+#define GPIO_GPIO_FUNC2_OUT_INV_SEL (BIT(9))
+#define GPIO_GPIO_FUNC2_OUT_INV_SEL_S 9
+#define GPIO_GPIO_FUNC2_OUT_SEL 0x000001FF
+#define GPIO_GPIO_FUNC2_OUT_SEL_S 0
+
+#define GPIO_FUNC3_OUT_SEL_CFG (DR_REG_GPIO_BASE + 0x053c)
+#define GPIO_GPIO_FUNC3_OEN_INV_SEL (BIT(11))
+#define GPIO_GPIO_FUNC3_OEN_INV_SEL_S 11
+#define GPIO_GPIO_FUNC3_OEN_SEL (BIT(10))
+#define GPIO_GPIO_FUNC3_OEN_SEL_S 10
+#define GPIO_GPIO_FUNC3_OUT_INV_SEL (BIT(9))
+#define GPIO_GPIO_FUNC3_OUT_INV_SEL_S 9
+#define GPIO_GPIO_FUNC3_OUT_SEL 0x000001FF
+#define GPIO_GPIO_FUNC3_OUT_SEL_S 0
+
+#define GPIO_FUNC4_OUT_SEL_CFG (DR_REG_GPIO_BASE + 0x0540)
+#define GPIO_GPIO_FUNC4_OEN_INV_SEL (BIT(11))
+#define GPIO_GPIO_FUNC4_OEN_INV_SEL_S 11
+#define GPIO_GPIO_FUNC4_OEN_SEL (BIT(10))
+#define GPIO_GPIO_FUNC4_OEN_SEL_S 10
+#define GPIO_GPIO_FUNC4_OUT_INV_SEL (BIT(9))
+#define GPIO_GPIO_FUNC4_OUT_INV_SEL_S 9
+#define GPIO_GPIO_FUNC4_OUT_SEL 0x000001FF
+#define GPIO_GPIO_FUNC4_OUT_SEL_S 0
+
+#define GPIO_FUNC5_OUT_SEL_CFG (DR_REG_GPIO_BASE + 0x0544)
+#define GPIO_GPIO_FUNC5_OEN_INV_SEL (BIT(11))
+#define GPIO_GPIO_FUNC5_OEN_INV_SEL_S 11
+#define GPIO_GPIO_FUNC5_OEN_SEL (BIT(10))
+#define GPIO_GPIO_FUNC5_OEN_SEL_S 10
+#define GPIO_GPIO_FUNC5_OUT_INV_SEL (BIT(9))
+#define GPIO_GPIO_FUNC5_OUT_INV_SEL_S 9
+#define GPIO_GPIO_FUNC5_OUT_SEL 0x000001FF
+#define GPIO_GPIO_FUNC5_OUT_SEL_S 0
+
+#define GPIO_FUNC6_OUT_SEL_CFG (DR_REG_GPIO_BASE + 0x0548)
+#define GPIO_GPIO_FUNC6_OEN_INV_SEL (BIT(11))
+#define GPIO_GPIO_FUNC6_OEN_INV_SEL_S 11
+#define GPIO_GPIO_FUNC6_OEN_SEL (BIT(10))
+#define GPIO_GPIO_FUNC6_OEN_SEL_S 10
+#define GPIO_GPIO_FUNC6_OUT_INV_SEL (BIT(9))
+#define GPIO_GPIO_FUNC6_OUT_INV_SEL_S 9
+#define GPIO_GPIO_FUNC6_OUT_SEL 0x000001FF
+#define GPIO_GPIO_FUNC6_OUT_SEL_S 0
+
+#define GPIO_FUNC7_OUT_SEL_CFG (DR_REG_GPIO_BASE + 0x054c)
+#define GPIO_GPIO_FUNC7_OEN_INV_SEL (BIT(11))
+#define GPIO_GPIO_FUNC7_OEN_INV_SEL_S 11
+#define GPIO_GPIO_FUNC7_OEN_SEL (BIT(10))
+#define GPIO_GPIO_FUNC7_OEN_SEL_S 10
+#define GPIO_GPIO_FUNC7_OUT_INV_SEL (BIT(9))
+#define GPIO_GPIO_FUNC7_OUT_INV_SEL_S 9
+#define GPIO_GPIO_FUNC7_OUT_SEL 0x000001FF
+#define GPIO_GPIO_FUNC7_OUT_SEL_S 0
+
+#define GPIO_FUNC8_OUT_SEL_CFG (DR_REG_GPIO_BASE + 0x0550)
+#define GPIO_GPIO_FUNC8_OEN_INV_SEL (BIT(11))
+#define GPIO_GPIO_FUNC8_OEN_INV_SEL_S 11
+#define GPIO_GPIO_FUNC8_OEN_SEL (BIT(10))
+#define GPIO_GPIO_FUNC8_OEN_SEL_S 10
+#define GPIO_GPIO_FUNC8_OUT_INV_SEL (BIT(9))
+#define GPIO_GPIO_FUNC8_OUT_INV_SEL_S 9
+#define GPIO_GPIO_FUNC8_OUT_SEL 0x000001FF
+#define GPIO_GPIO_FUNC8_OUT_SEL_S 0
+
+#define GPIO_FUNC9_OUT_SEL_CFG (DR_REG_GPIO_BASE + 0x0554)
+#define GPIO_GPIO_FUNC9_OEN_INV_SEL (BIT(11))
+#define GPIO_GPIO_FUNC9_OEN_INV_SEL_S 11
+#define GPIO_GPIO_FUNC9_OEN_SEL (BIT(10))
+#define GPIO_GPIO_FUNC9_OEN_SEL_S 10
+#define GPIO_GPIO_FUNC9_OUT_INV_SEL (BIT(9))
+#define GPIO_GPIO_FUNC9_OUT_INV_SEL_S 9
+#define GPIO_GPIO_FUNC9_OUT_SEL 0x000001FF
+#define GPIO_GPIO_FUNC9_OUT_SEL_S 0
+
+#define GPIO_FUNC10_OUT_SEL_CFG (DR_REG_GPIO_BASE + 0x0558)
+#define GPIO_GPIO_FUNC10_OEN_INV_SEL (BIT(11))
+#define GPIO_GPIO_FUNC10_OEN_INV_SEL_S 11
+#define GPIO_GPIO_FUNC10_OEN_SEL (BIT(10))
+#define GPIO_GPIO_FUNC10_OEN_SEL_S 10
+#define GPIO_GPIO_FUNC10_OUT_INV_SEL (BIT(9))
+#define GPIO_GPIO_FUNC10_OUT_INV_SEL_S 9
+#define GPIO_GPIO_FUNC10_OUT_SEL 0x000001FF
+#define GPIO_GPIO_FUNC10_OUT_SEL_S 0
+
+#define GPIO_FUNC11_OUT_SEL_CFG (DR_REG_GPIO_BASE + 0x055c)
+#define GPIO_GPIO_FUNC11_OEN_INV_SEL (BIT(11))
+#define GPIO_GPIO_FUNC11_OEN_INV_SEL_S 11
+#define GPIO_GPIO_FUNC11_OEN_SEL (BIT(10))
+#define GPIO_GPIO_FUNC11_OEN_SEL_S 10
+#define GPIO_GPIO_FUNC11_OUT_INV_SEL (BIT(9))
+#define GPIO_GPIO_FUNC11_OUT_INV_SEL_S 9
+#define GPIO_GPIO_FUNC11_OUT_SEL 0x000001FF
+#define GPIO_GPIO_FUNC11_OUT_SEL_S 0
+
+#define GPIO_FUNC12_OUT_SEL_CFG (DR_REG_GPIO_BASE + 0x0560)
+#define GPIO_GPIO_FUNC12_OEN_INV_SEL (BIT(11))
+#define GPIO_GPIO_FUNC12_OEN_INV_SEL_S 11
+#define GPIO_GPIO_FUNC12_OEN_SEL (BIT(10))
+#define GPIO_GPIO_FUNC12_OEN_SEL_S 10
+#define GPIO_GPIO_FUNC12_OUT_INV_SEL (BIT(9))
+#define GPIO_GPIO_FUNC12_OUT_INV_SEL_S 9
+#define GPIO_GPIO_FUNC12_OUT_SEL 0x000001FF
+#define GPIO_GPIO_FUNC12_OUT_SEL_S 0
+
+#define GPIO_FUNC13_OUT_SEL_CFG (DR_REG_GPIO_BASE + 0x0564)
+#define GPIO_GPIO_FUNC13_OEN_INV_SEL (BIT(11))
+#define GPIO_GPIO_FUNC13_OEN_INV_SEL_S 11
+#define GPIO_GPIO_FUNC13_OEN_SEL (BIT(10))
+#define GPIO_GPIO_FUNC13_OEN_SEL_S 10
+#define GPIO_GPIO_FUNC13_OUT_INV_SEL (BIT(9))
+#define GPIO_GPIO_FUNC13_OUT_INV_SEL_S 9
+#define GPIO_GPIO_FUNC13_OUT_SEL 0x000001FF
+#define GPIO_GPIO_FUNC13_OUT_SEL_S 0
+
+#define GPIO_FUNC14_OUT_SEL_CFG (DR_REG_GPIO_BASE + 0x0568)
+#define GPIO_GPIO_FUNC14_OEN_INV_SEL (BIT(11))
+#define GPIO_GPIO_FUNC14_OEN_INV_SEL_S 11
+#define GPIO_GPIO_FUNC14_OEN_SEL (BIT(10))
+#define GPIO_GPIO_FUNC14_OEN_SEL_S 10
+#define GPIO_GPIO_FUNC14_OUT_INV_SEL (BIT(9))
+#define GPIO_GPIO_FUNC14_OUT_INV_SEL_S 9
+#define GPIO_GPIO_FUNC14_OUT_SEL 0x000001FF
+#define GPIO_GPIO_FUNC14_OUT_SEL_S 0
+
+#define GPIO_FUNC15_OUT_SEL_CFG (DR_REG_GPIO_BASE + 0x056c)
+#define GPIO_GPIO_FUNC15_OEN_INV_SEL (BIT(11))
+#define GPIO_GPIO_FUNC15_OEN_INV_SEL_S 11
+#define GPIO_GPIO_FUNC15_OEN_SEL (BIT(10))
+#define GPIO_GPIO_FUNC15_OEN_SEL_S 10
+#define GPIO_GPIO_FUNC15_OUT_INV_SEL (BIT(9))
+#define GPIO_GPIO_FUNC15_OUT_INV_SEL_S 9
+#define GPIO_GPIO_FUNC15_OUT_SEL 0x000001FF
+#define GPIO_GPIO_FUNC15_OUT_SEL_S 0
+
+#define GPIO_FUNC16_OUT_SEL_CFG (DR_REG_GPIO_BASE + 0x0570)
+#define GPIO_GPIO_FUNC16_OEN_INV_SEL (BIT(11))
+#define GPIO_GPIO_FUNC16_OEN_INV_SEL_S 11
+#define GPIO_GPIO_FUNC16_OEN_SEL (BIT(10))
+#define GPIO_GPIO_FUNC16_OEN_SEL_S 10
+#define GPIO_GPIO_FUNC16_OUT_INV_SEL (BIT(9))
+#define GPIO_GPIO_FUNC16_OUT_INV_SEL_S 9
+#define GPIO_GPIO_FUNC16_OUT_SEL 0x000001FF
+#define GPIO_GPIO_FUNC16_OUT_SEL_S 0
+
+#define GPIO_FUNC17_OUT_SEL_CFG (DR_REG_GPIO_BASE + 0x0574)
+#define GPIO_GPIO_FUNC17_OEN_INV_SEL (BIT(11))
+#define GPIO_GPIO_FUNC17_OEN_INV_SEL_S 11
+#define GPIO_GPIO_FUNC17_OEN_SEL (BIT(10))
+#define GPIO_GPIO_FUNC17_OEN_SEL_S 10
+#define GPIO_GPIO_FUNC17_OUT_INV_SEL (BIT(9))
+#define GPIO_GPIO_FUNC17_OUT_INV_SEL_S 9
+#define GPIO_GPIO_FUNC17_OUT_SEL 0x000001FF
+#define GPIO_GPIO_FUNC17_OUT_SEL_S 0
+
+#define GPIO_FUNC18_OUT_SEL_CFG (DR_REG_GPIO_BASE + 0x0578)
+#define GPIO_GPIO_FUNC18_OEN_INV_SEL (BIT(11))
+#define GPIO_GPIO_FUNC18_OEN_INV_SEL_S 11
+#define GPIO_GPIO_FUNC18_OEN_SEL (BIT(10))
+#define GPIO_GPIO_FUNC18_OEN_SEL_S 10
+#define GPIO_GPIO_FUNC18_OUT_INV_SEL (BIT(9))
+#define GPIO_GPIO_FUNC18_OUT_INV_SEL_S 9
+#define GPIO_GPIO_FUNC18_OUT_SEL 0x000001FF
+#define GPIO_GPIO_FUNC18_OUT_SEL_S 0
+
+#define GPIO_FUNC19_OUT_SEL_CFG (DR_REG_GPIO_BASE + 0x057c)
+#define GPIO_GPIO_FUNC19_OEN_INV_SEL (BIT(11))
+#define GPIO_GPIO_FUNC19_OEN_INV_SEL_S 11
+#define GPIO_GPIO_FUNC19_OEN_SEL (BIT(10))
+#define GPIO_GPIO_FUNC19_OEN_SEL_S 10
+#define GPIO_GPIO_FUNC19_OUT_INV_SEL (BIT(9))
+#define GPIO_GPIO_FUNC19_OUT_INV_SEL_S 9
+#define GPIO_GPIO_FUNC19_OUT_SEL 0x000001FF
+#define GPIO_GPIO_FUNC19_OUT_SEL_S 0
+
+#define GPIO_FUNC20_OUT_SEL_CFG (DR_REG_GPIO_BASE + 0x0580)
+#define GPIO_GPIO_FUNC20_OEN_INV_SEL (BIT(11))
+#define GPIO_GPIO_FUNC20_OEN_INV_SEL_S 11
+#define GPIO_GPIO_FUNC20_OEN_SEL (BIT(10))
+#define GPIO_GPIO_FUNC20_OEN_SEL_S 10
+#define GPIO_GPIO_FUNC20_OUT_INV_SEL (BIT(9))
+#define GPIO_GPIO_FUNC20_OUT_INV_SEL_S 9
+#define GPIO_GPIO_FUNC20_OUT_SEL 0x000001FF
+#define GPIO_GPIO_FUNC20_OUT_SEL_S 0
+
+#define GPIO_FUNC21_OUT_SEL_CFG (DR_REG_GPIO_BASE + 0x0584)
+#define GPIO_GPIO_FUNC21_OEN_INV_SEL (BIT(11))
+#define GPIO_GPIO_FUNC21_OEN_INV_SEL_S 11
+#define GPIO_GPIO_FUNC21_OEN_SEL (BIT(10))
+#define GPIO_GPIO_FUNC21_OEN_SEL_S 10
+#define GPIO_GPIO_FUNC21_OUT_INV_SEL (BIT(9))
+#define GPIO_GPIO_FUNC21_OUT_INV_SEL_S 9
+#define GPIO_GPIO_FUNC21_OUT_SEL 0x000001FF
+#define GPIO_GPIO_FUNC21_OUT_SEL_S 0
+
+#define GPIO_FUNC22_OUT_SEL_CFG (DR_REG_GPIO_BASE + 0x0588)
+#define GPIO_GPIO_FUNC22_OEN_INV_SEL (BIT(11))
+#define GPIO_GPIO_FUNC22_OEN_INV_SEL_S 11
+#define GPIO_GPIO_FUNC22_OEN_SEL (BIT(10))
+#define GPIO_GPIO_FUNC22_OEN_SEL_S 10
+#define GPIO_GPIO_FUNC22_OUT_INV_SEL (BIT(9))
+#define GPIO_GPIO_FUNC22_OUT_INV_SEL_S 9
+#define GPIO_GPIO_FUNC22_OUT_SEL 0x000001FF
+#define GPIO_GPIO_FUNC22_OUT_SEL_S 0
+
+#define GPIO_FUNC23_OUT_SEL_CFG (DR_REG_GPIO_BASE + 0x058c)
+#define GPIO_GPIO_FUNC23_OEN_INV_SEL (BIT(11))
+#define GPIO_GPIO_FUNC23_OEN_INV_SEL_S 11
+#define GPIO_GPIO_FUNC23_OEN_SEL (BIT(10))
+#define GPIO_GPIO_FUNC23_OEN_SEL_S 10
+#define GPIO_GPIO_FUNC23_OUT_INV_SEL (BIT(9))
+#define GPIO_GPIO_FUNC23_OUT_INV_SEL_S 9
+#define GPIO_GPIO_FUNC23_OUT_SEL 0x000001FF
+#define GPIO_GPIO_FUNC23_OUT_SEL_S 0
+
+#define GPIO_FUNC24_OUT_SEL_CFG (DR_REG_GPIO_BASE + 0x0590)
+#define GPIO_GPIO_FUNC24_OEN_INV_SEL (BIT(11))
+#define GPIO_GPIO_FUNC24_OEN_INV_SEL_S 11
+#define GPIO_GPIO_FUNC24_OEN_SEL (BIT(10))
+#define GPIO_GPIO_FUNC24_OEN_SEL_S 10
+#define GPIO_GPIO_FUNC24_OUT_INV_SEL (BIT(9))
+#define GPIO_GPIO_FUNC24_OUT_INV_SEL_S 9
+#define GPIO_GPIO_FUNC24_OUT_SEL 0x000001FF
+#define GPIO_GPIO_FUNC24_OUT_SEL_S 0
+
+#define GPIO_FUNC25_OUT_SEL_CFG (DR_REG_GPIO_BASE + 0x0594)
+#define GPIO_GPIO_FUNC25_OEN_INV_SEL (BIT(11))
+#define GPIO_GPIO_FUNC25_OEN_INV_SEL_S 11
+#define GPIO_GPIO_FUNC25_OEN_SEL (BIT(10))
+#define GPIO_GPIO_FUNC25_OEN_SEL_S 10
+#define GPIO_GPIO_FUNC25_OUT_INV_SEL (BIT(9))
+#define GPIO_GPIO_FUNC25_OUT_INV_SEL_S 9
+#define GPIO_GPIO_FUNC25_OUT_SEL 0x000001FF
+#define GPIO_GPIO_FUNC25_OUT_SEL_S 0
+
+#define GPIO_FUNC26_OUT_SEL_CFG (DR_REG_GPIO_BASE + 0x0598)
+#define GPIO_GPIO_FUNC26_OEN_INV_SEL (BIT(11))
+#define GPIO_GPIO_FUNC26_OEN_INV_SEL_S 11
+#define GPIO_GPIO_FUNC26_OEN_SEL (BIT(10))
+#define GPIO_GPIO_FUNC26_OEN_SEL_S 10
+#define GPIO_GPIO_FUNC26_OUT_INV_SEL (BIT(9))
+#define GPIO_GPIO_FUNC26_OUT_INV_SEL_S 9
+#define GPIO_GPIO_FUNC26_OUT_SEL 0x000001FF
+#define GPIO_GPIO_FUNC26_OUT_SEL_S 0
+
+#define GPIO_FUNC27_OUT_SEL_CFG (DR_REG_GPIO_BASE + 0x059c)
+#define GPIO_GPIO_FUNC27_OEN_INV_SEL (BIT(11))
+#define GPIO_GPIO_FUNC27_OEN_INV_SEL_S 11
+#define GPIO_GPIO_FUNC27_OEN_SEL (BIT(10))
+#define GPIO_GPIO_FUNC27_OEN_SEL_S 10
+#define GPIO_GPIO_FUNC27_OUT_INV_SEL (BIT(9))
+#define GPIO_GPIO_FUNC27_OUT_INV_SEL_S 9
+#define GPIO_GPIO_FUNC27_OUT_SEL 0x000001FF
+#define GPIO_GPIO_FUNC27_OUT_SEL_S 0
+
+#define GPIO_FUNC28_OUT_SEL_CFG (DR_REG_GPIO_BASE + 0x05a0)
+#define GPIO_GPIO_FUNC28_OEN_INV_SEL (BIT(11))
+#define GPIO_GPIO_FUNC28_OEN_INV_SEL_S 11
+#define GPIO_GPIO_FUNC28_OEN_SEL (BIT(10))
+#define GPIO_GPIO_FUNC28_OEN_SEL_S 10
+#define GPIO_GPIO_FUNC28_OUT_INV_SEL (BIT(9))
+#define GPIO_GPIO_FUNC28_OUT_INV_SEL_S 9
+#define GPIO_GPIO_FUNC28_OUT_SEL 0x000001FF
+#define GPIO_GPIO_FUNC28_OUT_SEL_S 0
+
+#define GPIO_FUNC29_OUT_SEL_CFG (DR_REG_GPIO_BASE + 0x05a4)
+#define GPIO_GPIO_FUNC29_OEN_INV_SEL (BIT(11))
+#define GPIO_GPIO_FUNC29_OEN_INV_SEL_S 11
+#define GPIO_GPIO_FUNC29_OEN_SEL (BIT(10))
+#define GPIO_GPIO_FUNC29_OEN_SEL_S 10
+#define GPIO_GPIO_FUNC29_OUT_INV_SEL (BIT(9))
+#define GPIO_GPIO_FUNC29_OUT_INV_SEL_S 9
+#define GPIO_GPIO_FUNC29_OUT_SEL 0x000001FF
+#define GPIO_GPIO_FUNC29_OUT_SEL_S 0
+
+#define GPIO_FUNC30_OUT_SEL_CFG (DR_REG_GPIO_BASE + 0x05a8)
+#define GPIO_GPIO_FUNC30_OEN_INV_SEL (BIT(11))
+#define GPIO_GPIO_FUNC30_OEN_INV_SEL_S 11
+#define GPIO_GPIO_FUNC30_OEN_SEL (BIT(10))
+#define GPIO_GPIO_FUNC30_OEN_SEL_S 10
+#define GPIO_GPIO_FUNC30_OUT_INV_SEL (BIT(9))
+#define GPIO_GPIO_FUNC30_OUT_INV_SEL_S 9
+#define GPIO_GPIO_FUNC30_OUT_SEL 0x000001FF
+#define GPIO_GPIO_FUNC30_OUT_SEL_S 0
+
+#define GPIO_FUNC31_OUT_SEL_CFG (DR_REG_GPIO_BASE + 0x05ac)
+#define GPIO_GPIO_FUNC31_OEN_INV_SEL (BIT(11))
+#define GPIO_GPIO_FUNC31_OEN_INV_SEL_S 11
+#define GPIO_GPIO_FUNC31_OEN_SEL (BIT(10))
+#define GPIO_GPIO_FUNC31_OEN_SEL_S 10
+#define GPIO_GPIO_FUNC31_OUT_INV_SEL (BIT(9))
+#define GPIO_GPIO_FUNC31_OUT_INV_SEL_S 9
+#define GPIO_GPIO_FUNC31_OUT_SEL 0x000001FF
+#define GPIO_GPIO_FUNC31_OUT_SEL_S 0
+
+#define GPIO_FUNC32_OUT_SEL_CFG (DR_REG_GPIO_BASE + 0x05b0)
+#define GPIO_GPIO_FUNC32_OEN_INV_SEL (BIT(11))
+#define GPIO_GPIO_FUNC32_OEN_INV_SEL_S 11
+#define GPIO_GPIO_FUNC32_OEN_SEL (BIT(10))
+#define GPIO_GPIO_FUNC32_OEN_SEL_S 10
+#define GPIO_GPIO_FUNC32_OUT_INV_SEL (BIT(9))
+#define GPIO_GPIO_FUNC32_OUT_INV_SEL_S 9
+#define GPIO_GPIO_FUNC32_OUT_SEL 0x000001FF
+#define GPIO_GPIO_FUNC32_OUT_SEL_S 0
+
+#define GPIO_FUNC33_OUT_SEL_CFG (DR_REG_GPIO_BASE + 0x05b4)
+#define GPIO_GPIO_FUNC33_OEN_INV_SEL (BIT(11))
+#define GPIO_GPIO_FUNC33_OEN_INV_SEL_S 11
+#define GPIO_GPIO_FUNC33_OEN_SEL (BIT(10))
+#define GPIO_GPIO_FUNC33_OEN_SEL_S 10
+#define GPIO_GPIO_FUNC33_OUT_INV_SEL (BIT(9))
+#define GPIO_GPIO_FUNC33_OUT_INV_SEL_S 9
+#define GPIO_GPIO_FUNC33_OUT_SEL 0x000001FF
+#define GPIO_GPIO_FUNC33_OUT_SEL_S 0
+
+#define GPIO_FUNC34_OUT_SEL_CFG (DR_REG_GPIO_BASE + 0x05b8)
+#define GPIO_GPIO_FUNC34_OEN_INV_SEL (BIT(11))
+#define GPIO_GPIO_FUNC34_OEN_INV_SEL_S 11
+#define GPIO_GPIO_FUNC34_OEN_SEL (BIT(10))
+#define GPIO_GPIO_FUNC34_OEN_SEL_S 10
+#define GPIO_GPIO_FUNC34_OUT_INV_SEL (BIT(9))
+#define GPIO_GPIO_FUNC34_OUT_INV_SEL_S 9
+#define GPIO_GPIO_FUNC34_OUT_SEL 0x000001FF
+#define GPIO_GPIO_FUNC34_OUT_SEL_S 0
+
+#define GPIO_FUNC35_OUT_SEL_CFG (DR_REG_GPIO_BASE + 0x05bc)
+#define GPIO_GPIO_FUNC35_OEN_INV_SEL (BIT(11))
+#define GPIO_GPIO_FUNC35_OEN_INV_SEL_S 11
+#define GPIO_GPIO_FUNC35_OEN_SEL (BIT(10))
+#define GPIO_GPIO_FUNC35_OEN_SEL_S 10
+#define GPIO_GPIO_FUNC35_OUT_INV_SEL (BIT(9))
+#define GPIO_GPIO_FUNC35_OUT_INV_SEL_S 9
+#define GPIO_GPIO_FUNC35_OUT_SEL 0x000001FF
+#define GPIO_GPIO_FUNC35_OUT_SEL_S 0
+
+#define GPIO_FUNC36_OUT_SEL_CFG (DR_REG_GPIO_BASE + 0x05c0)
+#define GPIO_GPIO_FUNC36_OEN_INV_SEL (BIT(11))
+#define GPIO_GPIO_FUNC36_OEN_INV_SEL_S 11
+#define GPIO_GPIO_FUNC36_OEN_SEL (BIT(10))
+#define GPIO_GPIO_FUNC36_OEN_SEL_S 10
+#define GPIO_GPIO_FUNC36_OUT_INV_SEL (BIT(9))
+#define GPIO_GPIO_FUNC36_OUT_INV_SEL_S 9
+#define GPIO_GPIO_FUNC36_OUT_SEL 0x000001FF
+#define GPIO_GPIO_FUNC36_OUT_SEL_S 0
+
+#define GPIO_FUNC37_OUT_SEL_CFG (DR_REG_GPIO_BASE + 0x05c4)
+#define GPIO_GPIO_FUNC37_OEN_INV_SEL (BIT(11))
+#define GPIO_GPIO_FUNC37_OEN_INV_SEL_S 11
+#define GPIO_GPIO_FUNC37_OEN_SEL (BIT(10))
+#define GPIO_GPIO_FUNC37_OEN_SEL_S 10
+#define GPIO_GPIO_FUNC37_OUT_INV_SEL (BIT(9))
+#define GPIO_GPIO_FUNC37_OUT_INV_SEL_S 9
+#define GPIO_GPIO_FUNC37_OUT_SEL 0x000001FF
+#define GPIO_GPIO_FUNC37_OUT_SEL_S 0
+
+#define GPIO_FUNC38_OUT_SEL_CFG (DR_REG_GPIO_BASE + 0x05c8)
+#define GPIO_GPIO_FUNC38_OEN_INV_SEL (BIT(11))
+#define GPIO_GPIO_FUNC38_OEN_INV_SEL_S 11
+#define GPIO_GPIO_FUNC38_OEN_SEL (BIT(10))
+#define GPIO_GPIO_FUNC38_OEN_SEL_S 10
+#define GPIO_GPIO_FUNC38_OUT_INV_SEL (BIT(9))
+#define GPIO_GPIO_FUNC38_OUT_INV_SEL_S 9
+#define GPIO_GPIO_FUNC38_OUT_SEL 0x000001FF
+#define GPIO_GPIO_FUNC38_OUT_SEL_S 0
+
+#define GPIO_FUNC39_OUT_SEL_CFG (DR_REG_GPIO_BASE + 0x05cc)
+#define GPIO_GPIO_FUNC39_OEN_INV_SEL (BIT(11))
+#define GPIO_GPIO_FUNC39_OEN_INV_SEL_S 11
+#define GPIO_GPIO_FUNC39_OEN_SEL (BIT(10))
+#define GPIO_GPIO_FUNC39_OEN_SEL_S 10
+#define GPIO_GPIO_FUNC39_OUT_INV_SEL (BIT(9))
+#define GPIO_GPIO_FUNC39_OUT_INV_SEL_S 9
+#define GPIO_GPIO_FUNC39_OUT_SEL 0x000001FF
+#define GPIO_GPIO_FUNC39_OUT_SEL_S 0
+
+#endif /* _SOC_GPIO_REG_H_ */

components/esp32/include/soc/gpio_sd_reg.h

@@ -0,0 +1,80 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_GPIO_SD_REG_H_
+#define _SOC_GPIO_SD_REG_H_
+
+#include "soc.h"
+
+#define SIGMADELTA0 (DR_REG_GPIO_SD_BASE + 0x0000)
+#define SIGMADELTA_SD0_PRESCALE 0x000000FF
+#define SIGMADELTA_SD0_PRESCALE_S 8
+#define SIGMADELTA_SD0_IN 0x000000FF
+#define SIGMADELTA_SD0_IN_S 0
+
+#define SIGMADELTA1 (DR_REG_GPIO_SD_BASE + 0x0004)
+#define SIGMADELTA_SD1_PRESCALE 0x000000FF
+#define SIGMADELTA_SD1_PRESCALE_S 8
+#define SIGMADELTA_SD1_IN 0x000000FF
+#define SIGMADELTA_SD1_IN_S 0
+
+#define SIGMADELTA2 (DR_REG_GPIO_SD_BASE + 0x0008)
+#define SIGMADELTA_SD2_PRESCALE 0x000000FF
+#define SIGMADELTA_SD2_PRESCALE_S 8
+#define SIGMADELTA_SD2_IN 0x000000FF
+#define SIGMADELTA_SD2_IN_S 0
+
+#define SIGMADELTA3 (DR_REG_GPIO_SD_BASE + 0x000c)
+#define SIGMADELTA_SD3_PRESCALE 0x000000FF
+#define SIGMADELTA_SD3_PRESCALE_S 8
+#define SIGMADELTA_SD3_IN 0x000000FF
+#define SIGMADELTA_SD3_IN_S 0
+
+#define SIGMADELTA4 (DR_REG_GPIO_SD_BASE + 0x0010)
+#define SIGMADELTA_SD4_PRESCALE 0x000000FF
+#define SIGMADELTA_SD4_PRESCALE_S 8
+#define SIGMADELTA_SD4_IN 0x000000FF
+#define SIGMADELTA_SD4_IN_S 0
+
+#define SIGMADELTA5 (DR_REG_GPIO_SD_BASE + 0x0014)
+#define SIGMADELTA_SD5_PRESCALE 0x000000FF
+#define SIGMADELTA_SD5_PRESCALE_S 8
+#define SIGMADELTA_SD5_IN 0x000000FF
+#define SIGMADELTA_SD5_IN_S 0
+
+#define SIGMADELTA6 (DR_REG_GPIO_SD_BASE + 0x0018)
+#define SIGMADELTA_SD6_PRESCALE 0x000000FF
+#define SIGMADELTA_SD6_PRESCALE_S 8
+#define SIGMADELTA_SD6_IN 0x000000FF
+#define SIGMADELTA_SD6_IN_S 0
+
+#define SIGMADELTA7 (DR_REG_GPIO_SD_BASE + 0x001c)
+#define SIGMADELTA_SD7_PRESCALE 0x000000FF
+#define SIGMADELTA_SD7_PRESCALE_S 8
+#define SIGMADELTA_SD7_IN 0x000000FF
+#define SIGMADELTA_SD7_IN_S 0
+
+#define SIGMADELTA_CG (DR_REG_GPIO_SD_BASE + 0x0020)
+#define SIGMADELTA_GPIO_SD_CLK_EN (BIT(31))
+#define SIGMADELTA_GPIO_SD_CLK_EN_S 31
+
+#define SIGMADELTA_MISC (DR_REG_GPIO_SD_BASE + 0x0024)
+#define SIGMADELTA_SPI_SWAP (BIT(31))
+#define SIGMADELTA_SPI_SWAP_S 31
+
+#define SIGMADELTA_VERSION (DR_REG_GPIO_SD_BASE + 0x0028)
+#define SIGMADELTA_GPIO_SD_DATE 0x0FFFFFFF
+#define SIGMADELTA_GPIO_SD_DATE_S 0
+#define SIGMADELTA_GPIO_SD_DATE_VERSION 0x1506190
+
+#endif /* _SOC_GPIO_SD_REG_H_ */

components/esp32/include/soc/gpio_sig_map.h

@@ -0,0 +1,422 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_GPIO_SIG_MAP_H_
+#define _SOC_GPIO_SIG_MAP_H_
+
+#define SPICLK_IN_IDX			0
+#define SPICLK_OUT_IDX			0
+#define SPIQ_IN_IDX			1
+#define SPIQ_OUT_IDX			1
+#define SPID_IN_IDX			2
+#define SPID_OUT_IDX			2
+#define SPIHD_IN_IDX			3
+#define SPIHD_OUT_IDX			3
+#define SPIWP_IN_IDX			4
+#define SPIWP_OUT_IDX			4
+#define SPICS0_IN_IDX			5
+#define SPICS0_OUT_IDX			5
+#define SPICS1_IN_IDX			6
+#define SPICS1_OUT_IDX			6
+#define SPICS2_IN_IDX			7
+#define SPICS2_OUT_IDX			7
+#define HSPICLK_IN_IDX			8
+#define HSPICLK_OUT_IDX			8
+#define HSPIQ_IN_IDX			9
+#define HSPIQ_OUT_IDX			9
+#define HSPID_IN_IDX			10
+#define HSPID_OUT_IDX			10
+#define HSPICS0_IN_IDX			11
+#define HSPICS0_OUT_IDX			11
+#define HSPIHD_IN_IDX			12
+#define HSPIHD_OUT_IDX			12
+#define HSPIWP_IN_IDX			13
+#define HSPIWP_OUT_IDX			13
+#define U0RXD_IN_IDX			14
+#define U0TXD_OUT_IDX			14
+#define U0CTS_IN_IDX			15
+#define U0RTS_OUT_IDX			15
+#define U0DSR_IN_IDX			16
+#define U0DTR_OUT_IDX			16
+#define U1RXD_IN_IDX			17
+#define U1TXD_OUT_IDX			17
+#define U1CTS_IN_IDX			18
+#define U1RTS_OUT_IDX			18
+#define I2CM_SCL_O_IDX			19
+#define I2CM_SDA_I_IDX			20
+#define I2CM_SDA_O_IDX			20
+#define EXT_I2C_SCL_O_IDX			21
+#define EXT_I2C_SDA_O_IDX			22
+#define EXT_I2C_SDA_I_IDX			22
+#define I2S0O_BCK_IN_IDX			23
+#define I2S0O_BCK_OUT_IDX			23
+#define I2S1O_BCK_IN_IDX			24
+#define I2S1O_BCK_OUT_IDX			24
+#define I2S0O_WS_IN_IDX			25
+#define I2S0O_WS_OUT_IDX			25
+#define I2S1O_WS_IN_IDX			26
+#define I2S1O_WS_OUT_IDX			26
+#define I2S0I_BCK_IN_IDX			27
+#define I2S0I_BCK_OUT_IDX			27
+#define I2S0I_WS_IN_IDX			28
+#define I2S0I_WS_OUT_IDX			28
+#define I2CEXT0_SCL_IN_IDX			29
+#define I2CEXT0_SCL_OUT_IDX			29
+#define I2CEXT0_SDA_IN_IDX			30
+#define I2CEXT0_SDA_OUT_IDX			30
+#define PWM0_SYNC0_IN_IDX			31
+#define SDIO_TOHOST_INT_OUT_IDX			31
+#define PWM0_SYNC1_IN_IDX			32
+#define PWM0_OUT0A_IDX			32
+#define PWM0_SYNC2_IN_IDX			33
+#define PWM0_OUT0B_IDX			33
+#define PWM0_F0_IN_IDX			34
+#define PWM0_OUT1A_IDX			34
+#define PWM0_F1_IN_IDX			35
+#define PWM0_OUT1B_IDX			35
+#define PWM0_F2_IN_IDX			36
+#define PWM0_OUT2A_IDX			36
+#define GPIO_BT_ACTIVE_IDX			37
+#define PWM0_OUT2B_IDX			37
+#define GPIO_BT_PRIORITY_IDX			38
+#define PCNT_SIG_CH0_IN0_IDX			39
+#define PCNT_SIG_CH1_IN0_IDX			40
+#define GPIO_WLAN_ACTIVE_IDX			40
+#define PCNT_CTRL_CH0_IN0_IDX			41
+#define BB_DIAG0_IDX			41
+#define PCNT_CTRL_CH1_IN0_IDX			42
+#define BB_DIAG1_IDX			42
+#define PCNT_SIG_CH0_IN1_IDX			43
+#define BB_DIAG2_IDX			43
+#define PCNT_SIG_CH1_IN1_IDX			44
+#define BB_DIAG3_IDX			44
+#define PCNT_CTRL_CH0_IN1_IDX			45
+#define BB_DIAG4_IDX			45
+#define PCNT_CTRL_CH1_IN1_IDX			46
+#define BB_DIAG5_IDX			46
+#define PCNT_SIG_CH0_IN2_IDX			47
+#define BB_DIAG6_IDX			47
+#define PCNT_SIG_CH1_IN2_IDX			48
+#define BB_DIAG7_IDX			48
+#define PCNT_CTRL_CH0_IN2_IDX			49
+#define BB_DIAG8_IDX			49
+#define PCNT_CTRL_CH1_IN2_IDX			50
+#define BB_DIAG9_IDX			50
+#define PCNT_SIG_CH0_IN3_IDX			51
+#define BB_DIAG10_IDX			51
+#define PCNT_SIG_CH1_IN3_IDX			52
+#define BB_DIAG11_IDX			52
+#define PCNT_CTRL_CH0_IN3_IDX			53
+#define BB_DIAG12_IDX			53
+#define PCNT_CTRL_CH1_IN3_IDX			54
+#define BB_DIAG13_IDX			54
+#define PCNT_SIG_CH0_IN4_IDX			55
+#define BB_DIAG14_IDX			55
+#define PCNT_SIG_CH1_IN4_IDX			56
+#define BB_DIAG15_IDX			56
+#define PCNT_CTRL_CH0_IN4_IDX			57
+#define BB_DIAG16_IDX			57
+#define PCNT_CTRL_CH1_IN4_IDX			58
+#define BB_DIAG17_IDX			58
+#define BB_DIAG18_IDX			59
+#define BB_DIAG19_IDX			60
+#define HSPICS1_IN_IDX			61
+#define HSPICS1_OUT_IDX			61
+#define HSPICS2_IN_IDX			62
+#define HSPICS2_OUT_IDX			62
+#define VSPICLK_IN_IDX			63
+#define VSPICLK_OUT_MUX_IDX			63
+#define VSPIQ_IN_IDX			64
+#define VSPIQ_OUT_IDX			64
+#define VSPID_IN_IDX			65
+#define VSPID_OUT_IDX			65
+#define VSPIHD_IN_IDX			66
+#define VSPIHD_OUT_IDX			66
+#define VSPIWP_IN_IDX			67
+#define VSPIWP_OUT_IDX			67
+#define VSPICS0_IN_IDX			68
+#define VSPICS0_OUT_IDX			68
+#define VSPICS1_IN_IDX			69
+#define VSPICS1_OUT_IDX			69
+#define VSPICS2_IN_IDX			70
+#define VSPICS2_OUT_IDX			70
+#define PCNT_SIG_CH0_IN5_IDX			71
+#define LEDC_HS_SIG_OUT0_IDX			71
+#define PCNT_SIG_CH1_IN5_IDX			72
+#define LEDC_HS_SIG_OUT1_IDX			72
+#define PCNT_CTRL_CH0_IN5_IDX			73
+#define LEDC_HS_SIG_OUT2_IDX			73
+#define PCNT_CTRL_CH1_IN5_IDX			74
+#define LEDC_HS_SIG_OUT3_IDX			74
+#define PCNT_SIG_CH0_IN6_IDX			75
+#define LEDC_HS_SIG_OUT4_IDX			75
+#define PCNT_SIG_CH1_IN6_IDX			76
+#define LEDC_HS_SIG_OUT5_IDX			76
+#define PCNT_CTRL_CH0_IN6_IDX			77
+#define LEDC_HS_SIG_OUT6_IDX			77
+#define PCNT_CTRL_CH1_IN6_IDX			78
+#define LEDC_HS_SIG_OUT7_IDX			78
+#define PCNT_SIG_CH0_IN7_IDX			79
+#define LEDC_LS_SIG_OUT0_IDX			79
+#define PCNT_SIG_CH1_IN7_IDX			80
+#define LEDC_LS_SIG_OUT1_IDX			80
+#define PCNT_CTRL_CH0_IN7_IDX			81
+#define LEDC_LS_SIG_OUT2_IDX			81
+#define PCNT_CTRL_CH1_IN7_IDX			82
+#define LEDC_LS_SIG_OUT3_IDX			82
+#define RMT_SIG_IN0_IDX			83
+#define LEDC_LS_SIG_OUT4_IDX			83
+#define RMT_SIG_IN1_IDX			84
+#define LEDC_LS_SIG_OUT5_IDX			84
+#define RMT_SIG_IN2_IDX			85
+#define LEDC_LS_SIG_OUT6_IDX			85
+#define RMT_SIG_IN3_IDX			86
+#define LEDC_LS_SIG_OUT7_IDX			86
+#define RMT_SIG_IN4_IDX			87
+#define RMT_SIG_OUT0_IDX			87
+#define RMT_SIG_IN5_IDX			88
+#define RMT_SIG_OUT1_IDX			88
+#define RMT_SIG_IN6_IDX			89
+#define RMT_SIG_OUT2_IDX			89
+#define RMT_SIG_IN7_IDX			90
+#define RMT_SIG_OUT3_IDX			90
+#define RMT_SIG_OUT4_IDX			91
+#define RMT_SIG_OUT5_IDX			92
+#define EXT_ADC_START_IDX			93
+#define RMT_SIG_OUT6_IDX			93
+#define CAN_RX_IDX			94
+#define RMT_SIG_OUT7_IDX			94
+#define I2CEXT1_SCL_IN_IDX			95
+#define I2CEXT1_SCL_OUT_IDX			95
+#define I2CEXT1_SDA_IN_IDX			96
+#define I2CEXT1_SDA_OUT_IDX			96
+#define HOST_CARD_DETECT_N_1_IDX			97
+#define HOST_CCMD_OD_PULLUP_EN_N_IDX			97
+#define HOST_CARD_DETECT_N_2_IDX			98
+#define HOST_RST_N_1_IDX			98
+#define HOST_CARD_WRITE_PRT_1_IDX			99
+#define HOST_RST_N_2_IDX			99
+#define HOST_CARD_WRITE_PRT_2_IDX			100
+#define GPIO_SD0_OUT_IDX			100
+#define HOST_CARD_INT_N_1_IDX			101
+#define GPIO_SD1_OUT_IDX			101
+#define HOST_CARD_INT_N_2_IDX			102
+#define GPIO_SD2_OUT_IDX			102
+#define PWM1_SYNC0_IN_IDX			103
+#define GPIO_SD3_OUT_IDX			103
+#define PWM1_SYNC1_IN_IDX			104
+#define GPIO_SD4_OUT_IDX			104
+#define PWM1_SYNC2_IN_IDX			105
+#define GPIO_SD5_OUT_IDX			105
+#define PWM1_F0_IN_IDX			106
+#define GPIO_SD6_OUT_IDX			106
+#define PWM1_F1_IN_IDX			107
+#define GPIO_SD7_OUT_IDX			107
+#define PWM1_F2_IN_IDX			108
+#define PWM1_OUT0A_IDX			108
+#define PWM0_CAP0_IN_IDX			109
+#define PWM1_OUT0B_IDX			109
+#define PWM0_CAP1_IN_IDX			110
+#define PWM1_OUT1A_IDX			110
+#define PWM0_CAP2_IN_IDX			111
+#define PWM1_OUT1B_IDX			111
+#define PWM1_CAP0_IN_IDX			112
+#define PWM1_OUT2A_IDX			112
+#define PWM1_CAP1_IN_IDX			113
+#define PWM1_OUT2B_IDX			113
+#define PWM1_CAP2_IN_IDX			114
+#define PWM2_OUT1H_IDX			114
+#define PWM2_FLTA_IDX			115
+#define PWM2_OUT1L_IDX			115
+#define PWM2_FLTB_IDX			116
+#define PWM2_OUT2H_IDX			116
+#define PWM2_CAP1_IN_IDX			117
+#define PWM2_OUT2L_IDX			117
+#define PWM2_CAP2_IN_IDX			118
+#define PWM2_OUT3H_IDX			118
+#define PWM2_CAP3_IN_IDX			119
+#define PWM2_OUT3L_IDX			119
+#define PWM3_FLTA_IDX			120
+#define PWM2_OUT4H_IDX			120
+#define PWM3_FLTB_IDX			121
+#define PWM2_OUT4L_IDX			121
+#define PWM3_CAP1_IN_IDX			122
+#define PWM3_CAP2_IN_IDX			123
+#define CAN_TX_IDX			123
+#define PWM3_CAP3_IN_IDX			124
+#define CAN_BUS_OFF_ON_IDX			124
+#define CAN_CLKOUT_IDX			125
+#define SPID4_IN_IDX			128
+#define SPID4_OUT_IDX			128
+#define SPID5_IN_IDX			129
+#define SPID5_OUT_IDX			129
+#define SPID6_IN_IDX			130
+#define SPID6_OUT_IDX			130
+#define SPID7_IN_IDX			131
+#define SPID7_OUT_IDX			131
+#define HSPID4_IN_IDX			132
+#define HSPID4_OUT_IDX			132
+#define HSPID5_IN_IDX			133
+#define HSPID5_OUT_IDX			133
+#define HSPID6_IN_IDX			134
+#define HSPID6_OUT_IDX			134
+#define HSPID7_IN_IDX			135
+#define HSPID7_OUT_IDX			135
+#define VSPID4_IN_IDX			136
+#define VSPID4_OUT_IDX			136
+#define VSPID5_IN_IDX			137
+#define VSPID5_OUT_IDX			137
+#define VSPID6_IN_IDX			138
+#define VSPID6_OUT_IDX			138
+#define VSPID7_IN_IDX			139
+#define VSPID7_OUT_IDX			139
+#define I2S0I_DATA_IN0_IDX			140
+#define I2S0O_DATA_OUT0_IDX			140
+#define I2S0I_DATA_IN1_IDX			141
+#define I2S0O_DATA_OUT1_IDX			141
+#define I2S0I_DATA_IN2_IDX			142
+#define I2S0O_DATA_OUT2_IDX			142
+#define I2S0I_DATA_IN3_IDX			143
+#define I2S0O_DATA_OUT3_IDX			143
+#define I2S0I_DATA_IN4_IDX			144
+#define I2S0O_DATA_OUT4_IDX			144
+#define I2S0I_DATA_IN5_IDX			145
+#define I2S0O_DATA_OUT5_IDX			145
+#define I2S0I_DATA_IN6_IDX			146
+#define I2S0O_DATA_OUT6_IDX			146
+#define I2S0I_DATA_IN7_IDX			147
+#define I2S0O_DATA_OUT7_IDX			147
+#define I2S0I_DATA_IN8_IDX			148
+#define I2S0O_DATA_OUT8_IDX			148
+#define I2S0I_DATA_IN9_IDX			149
+#define I2S0O_DATA_OUT9_IDX			149
+#define I2S0I_DATA_IN10_IDX			150
+#define I2S0O_DATA_OUT10_IDX			150
+#define I2S0I_DATA_IN11_IDX			151
+#define I2S0O_DATA_OUT11_IDX			151
+#define I2S0I_DATA_IN12_IDX			152
+#define I2S0O_DATA_OUT12_IDX			152
+#define I2S0I_DATA_IN13_IDX			153
+#define I2S0O_DATA_OUT13_IDX			153
+#define I2S0I_DATA_IN14_IDX			154
+#define I2S0O_DATA_OUT14_IDX			154
+#define I2S0I_DATA_IN15_IDX			155
+#define I2S0O_DATA_OUT15_IDX			155
+#define I2S0O_DATA_OUT16_IDX			156
+#define I2S0O_DATA_OUT17_IDX			157
+#define I2S0O_DATA_OUT18_IDX			158
+#define I2S0O_DATA_OUT19_IDX			159
+#define I2S0O_DATA_OUT20_IDX			160
+#define I2S0O_DATA_OUT21_IDX			161
+#define I2S0O_DATA_OUT22_IDX			162
+#define I2S0O_DATA_OUT23_IDX			163
+#define I2S1I_BCK_IN_IDX			164
+#define I2S1I_BCK_OUT_IDX			164
+#define I2S1I_WS_IN_IDX			165
+#define I2S1I_WS_OUT_IDX			165
+#define I2S1I_DATA_IN0_IDX			166
+#define I2S1O_DATA_OUT0_IDX			166
+#define I2S1I_DATA_IN1_IDX			167
+#define I2S1O_DATA_OUT1_IDX			167
+#define I2S1I_DATA_IN2_IDX			168
+#define I2S1O_DATA_OUT2_IDX			168
+#define I2S1I_DATA_IN3_IDX			169
+#define I2S1O_DATA_OUT3_IDX			169
+#define I2S1I_DATA_IN4_IDX			170
+#define I2S1O_DATA_OUT4_IDX			170
+#define I2S1I_DATA_IN5_IDX			171
+#define I2S1O_DATA_OUT5_IDX			171
+#define I2S1I_DATA_IN6_IDX			172
+#define I2S1O_DATA_OUT6_IDX			172
+#define I2S1I_DATA_IN7_IDX			173
+#define I2S1O_DATA_OUT7_IDX			173
+#define I2S1I_DATA_IN8_IDX			174
+#define I2S1O_DATA_OUT8_IDX			174
+#define I2S1I_DATA_IN9_IDX			175
+#define I2S1O_DATA_OUT9_IDX			175
+#define I2S1I_DATA_IN10_IDX			176
+#define I2S1O_DATA_OUT10_IDX			176
+#define I2S1I_DATA_IN11_IDX			177
+#define I2S1O_DATA_OUT11_IDX			177
+#define I2S1I_DATA_IN12_IDX			178
+#define I2S1O_DATA_OUT12_IDX			178
+#define I2S1I_DATA_IN13_IDX			179
+#define I2S1O_DATA_OUT13_IDX			179
+#define I2S1I_DATA_IN14_IDX			180
+#define I2S1O_DATA_OUT14_IDX			180
+#define I2S1I_DATA_IN15_IDX			181
+#define I2S1O_DATA_OUT15_IDX			181
+#define I2S1O_DATA_OUT16_IDX			182
+#define I2S1O_DATA_OUT17_IDX			183
+#define I2S1O_DATA_OUT18_IDX			184
+#define I2S1O_DATA_OUT19_IDX			185
+#define I2S1O_DATA_OUT20_IDX			186
+#define I2S1O_DATA_OUT21_IDX			187
+#define I2S1O_DATA_OUT22_IDX			188
+#define I2S1O_DATA_OUT23_IDX			189
+#define I2S0I_H_SYNC_IDX			190
+#define PWM3_OUT1H_IDX			190
+#define I2S0I_V_SYNC_IDX			191
+#define PWM3_OUT1L_IDX			191
+#define I2S0I_H_ENABLE_IDX			192
+#define PWM3_OUT2H_IDX			192
+#define I2S1I_H_SYNC_IDX			193
+#define PWM3_OUT2L_IDX			193
+#define I2S1I_V_SYNC_IDX			194
+#define PWM3_OUT3H_IDX			194
+#define I2S1I_H_ENABLE_IDX			195
+#define PWM3_OUT3L_IDX			195
+#define PWM3_OUT4H_IDX			196
+#define PWM3_OUT4L_IDX			197
+#define U2RXD_IN_IDX			198
+#define U2TXD_OUT_IDX			198
+#define U2CTS_IN_IDX			199
+#define U2RTS_OUT_IDX			199
+#define EMAC_MDC_I_IDX			200
+#define EMAC_MDC_O_IDX			200
+#define EMAC_MDI_I_IDX			201
+#define EMAC_MDO_O_IDX			201
+#define EMAC_CRS_I_IDX			202
+#define EMAC_CRS_O_IDX			202
+#define EMAC_COL_I_IDX			203
+#define EMAC_COL_O_IDX			203
+#define PCMFSYNC_IN_IDX			204
+#define BT_AUDIO0_IRQ_IDX			204
+#define PCMCLK_IN_IDX			205
+#define BT_AUDIO1_IRQ_IDX			205
+#define PCMDIN_IDX			206
+#define BT_AUDIO2_IRQ_IDX			206
+#define BLE_AUDIO0_IRQ_IDX			207
+#define BLE_AUDIO1_IRQ_IDX			208
+#define BLE_AUDIO2_IRQ_IDX			209
+#define PCMFSYNC_OUT_IDX			210
+#define PCMCLK_OUT_IDX			211
+#define PCMDOUT_IDX			212
+#define BLE_AUDIO_SYNC0_P_IDX			213
+#define BLE_AUDIO_SYNC1_P_IDX			214
+#define BLE_AUDIO_SYNC2_P_IDX			215
+#define ANT_SEL0_IDX			216
+#define ANT_SEL1_IDX			217
+#define ANT_SEL2_IDX			218
+#define ANT_SEL3_IDX			219
+#define ANT_SEL4_IDX			220
+#define ANT_SEL5_IDX			221
+#define ANT_SEL6_IDX			222
+#define ANT_SEL7_IDX			223
+#define SIG_IN_FUNC224_IDX			224
+#define SIG_IN_FUNC225_IDX			225
+#define SIG_IN_FUNC226_IDX			226
+#define SIG_IN_FUNC227_IDX			227
+#define SIG_IN_FUNC228_IDX			228
+
+#endif /* _SOC_GPIO_SIG_MAP_H_ */

components/esp32/include/soc/i2s_reg.h

@@ -0,0 +1,579 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_I2S_REG_H_
+#define _SOC_I2S_REG_H_
+
+#include "soc.h"
+
+#define I2SCONF (DR_REG_I2S_BASE + 0x0008)
+#define I2S_I2S_SIG_LOOPBACK (BIT(18))
+#define I2S_I2S_SIG_LOOPBACK_S 18
+#define I2S_RX_MSB_RIGHT (BIT(17))
+#define I2S_RX_MSB_RIGHT_S 17
+#define I2S_TX_MSB_RIGHT (BIT(16))
+#define I2S_TX_MSB_RIGHT_S 16
+#define I2S_I2S_RX_MONO (BIT(15))
+#define I2S_I2S_RX_MONO_S 15
+#define I2S_I2S_TX_MONO (BIT(14))
+#define I2S_I2S_TX_MONO_S 14
+#define I2S_I2S_RX_SHORT_SYNC (BIT(13))
+#define I2S_I2S_RX_SHORT_SYNC_S 13
+#define I2S_I2S_TX_SHORT_SYNC (BIT(12))
+#define I2S_I2S_TX_SHORT_SYNC_S 12
+#define I2S_RX_MSB_SHIFT (BIT(11))
+#define I2S_RX_MSB_SHIFT_S 11
+#define I2S_TX_MSB_SHIFT (BIT(10))
+#define I2S_TX_MSB_SHIFT_S 10
+#define I2S_RX_RIGHT_FIRST (BIT(9))
+#define I2S_RX_RIGHT_FIRST_S 9
+#define I2S_TX_RIGHT_FIRST (BIT(8))
+#define I2S_TX_RIGHT_FIRST_S 8
+#define I2S_RX_SLAVE_MOD (BIT(7))
+#define I2S_RX_SLAVE_MOD_S 7
+#define I2S_TX_SLAVE_MOD (BIT(6))
+#define I2S_TX_SLAVE_MOD_S 6
+#define I2S_I2S_RX_START (BIT(5))
+#define I2S_I2S_RX_START_S 5
+#define I2S_I2S_TX_START (BIT(4))
+#define I2S_I2S_TX_START_S 4
+#define I2S_I2S_RX_FIFO_RESET (BIT(3))
+#define I2S_I2S_RX_FIFO_RESET_S 3
+#define I2S_I2S_TX_FIFO_RESET (BIT(2))
+#define I2S_I2S_TX_FIFO_RESET_S 2
+#define I2S_I2S_RX_RESET (BIT(1))
+#define I2S_I2S_RX_RESET_S 1
+#define I2S_I2S_TX_RESET (BIT(0))
+#define I2S_I2S_TX_RESET_S 0
+
+#define I2SINT_RAW (DR_REG_I2S_BASE + 0x000c)
+#define I2S_I2S_OUT_TOTAL_EOF_INT_RAW (BIT(16))
+#define I2S_I2S_OUT_TOTAL_EOF_INT_RAW_S 16
+#define I2S_I2S_IN_DSCR_EMPTY_INT_RAW (BIT(15))
+#define I2S_I2S_IN_DSCR_EMPTY_INT_RAW_S 15
+#define I2S_I2S_OUT_DSCR_ERR_INT_RAW (BIT(14))
+#define I2S_I2S_OUT_DSCR_ERR_INT_RAW_S 14
+#define I2S_I2S_IN_DSCR_ERR_INT_RAW (BIT(13))
+#define I2S_I2S_IN_DSCR_ERR_INT_RAW_S 13
+#define I2S_I2S_OUT_EOF_INT_RAW (BIT(12))
+#define I2S_I2S_OUT_EOF_INT_RAW_S 12
+#define I2S_I2S_OUT_DONE_INT_RAW (BIT(11))
+#define I2S_I2S_OUT_DONE_INT_RAW_S 11
+#define I2S_I2S_IN_ERR_EOF_INT_RAW (BIT(10))
+#define I2S_I2S_IN_ERR_EOF_INT_RAW_S 10
+#define I2S_I2S_IN_SUC_EOF_INT_RAW (BIT(9))
+#define I2S_I2S_IN_SUC_EOF_INT_RAW_S 9
+#define I2S_I2S_IN_DONE_INT_RAW (BIT(8))
+#define I2S_I2S_IN_DONE_INT_RAW_S 8
+#define I2S_I2S_TX_HUNG_INT_RAW (BIT(7))
+#define I2S_I2S_TX_HUNG_INT_RAW_S 7
+#define I2S_I2S_RX_HUNG_INT_RAW (BIT(6))
+#define I2S_I2S_RX_HUNG_INT_RAW_S 6
+#define I2S_I2S_TX_REMPTY_INT_RAW (BIT(5))
+#define I2S_I2S_TX_REMPTY_INT_RAW_S 5
+#define I2S_I2S_TX_WFULL_INT_RAW (BIT(4))
+#define I2S_I2S_TX_WFULL_INT_RAW_S 4
+#define I2S_I2S_RX_REMPTY_INT_RAW (BIT(3))
+#define I2S_I2S_RX_REMPTY_INT_RAW_S 3
+#define I2S_I2S_RX_WFULL_INT_RAW (BIT(2))
+#define I2S_I2S_RX_WFULL_INT_RAW_S 2
+#define I2S_I2S_TX_PUT_DATA_INT_RAW (BIT(1))
+#define I2S_I2S_TX_PUT_DATA_INT_RAW_S 1
+#define I2S_I2S_RX_TAKE_DATA_INT_RAW (BIT(0))
+#define I2S_I2S_RX_TAKE_DATA_INT_RAW_S 0
+
+#define I2SINT_ST (DR_REG_I2S_BASE + 0x0010)
+#define I2S_I2S_OUT_TOTAL_EOF_INT_ST (BIT(16))
+#define I2S_I2S_OUT_TOTAL_EOF_INT_ST_S 16
+#define I2S_I2S_IN_DSCR_EMPTY_INT_ST (BIT(15))
+#define I2S_I2S_IN_DSCR_EMPTY_INT_ST_S 15
+#define I2S_I2S_OUT_DSCR_ERR_INT_ST (BIT(14))
+#define I2S_I2S_OUT_DSCR_ERR_INT_ST_S 14
+#define I2S_I2S_IN_DSCR_ERR_INT_ST (BIT(13))
+#define I2S_I2S_IN_DSCR_ERR_INT_ST_S 13
+#define I2S_I2S_OUT_EOF_INT_ST (BIT(12))
+#define I2S_I2S_OUT_EOF_INT_ST_S 12
+#define I2S_I2S_OUT_DONE_INT_ST (BIT(11))
+#define I2S_I2S_OUT_DONE_INT_ST_S 11
+#define I2S_I2S_IN_ERR_EOF_INT_ST (BIT(10))
+#define I2S_I2S_IN_ERR_EOF_INT_ST_S 10
+#define I2S_I2S_IN_SUC_EOF_INT_ST (BIT(9))
+#define I2S_I2S_IN_SUC_EOF_INT_ST_S 9
+#define I2S_I2S_IN_DONE_INT_ST (BIT(8))
+#define I2S_I2S_IN_DONE_INT_ST_S 8
+#define I2S_I2S_TX_HUNG_INT_ST (BIT(7))
+#define I2S_I2S_TX_HUNG_INT_ST_S 7
+#define I2S_I2S_RX_HUNG_INT_ST (BIT(6))
+#define I2S_I2S_RX_HUNG_INT_ST_S 6
+#define I2S_I2S_TX_REMPTY_INT_ST (BIT(5))
+#define I2S_I2S_TX_REMPTY_INT_ST_S 5
+#define I2S_I2S_TX_WFULL_INT_ST (BIT(4))
+#define I2S_I2S_TX_WFULL_INT_ST_S 4
+#define I2S_I2S_RX_REMPTY_INT_ST (BIT(3))
+#define I2S_I2S_RX_REMPTY_INT_ST_S 3
+#define I2S_I2S_RX_WFULL_INT_ST (BIT(2))
+#define I2S_I2S_RX_WFULL_INT_ST_S 2
+#define I2S_I2S_TX_PUT_DATA_INT_ST (BIT(1))
+#define I2S_I2S_TX_PUT_DATA_INT_ST_S 1
+#define I2S_I2S_RX_TAKE_DATA_INT_ST (BIT(0))
+#define I2S_I2S_RX_TAKE_DATA_INT_ST_S 0
+
+#define I2SINT_ENA (DR_REG_I2S_BASE + 0x0014)
+#define I2S_I2S_OUT_TOTAL_EOF_INT_ENA (BIT(16))
+#define I2S_I2S_OUT_TOTAL_EOF_INT_ENA_S 16
+#define I2S_I2S_IN_DSCR_EMPTY_INT_ENA (BIT(15))
+#define I2S_I2S_IN_DSCR_EMPTY_INT_ENA_S 15
+#define I2S_I2S_OUT_DSCR_ERR_INT_ENA (BIT(14))
+#define I2S_I2S_OUT_DSCR_ERR_INT_ENA_S 14
+#define I2S_I2S_IN_DSCR_ERR_INT_ENA (BIT(13))
+#define I2S_I2S_IN_DSCR_ERR_INT_ENA_S 13
+#define I2S_I2S_OUT_EOF_INT_ENA (BIT(12))
+#define I2S_I2S_OUT_EOF_INT_ENA_S 12
+#define I2S_I2S_OUT_DONE_INT_ENA (BIT(11))
+#define I2S_I2S_OUT_DONE_INT_ENA_S 11
+#define I2S_I2S_IN_ERR_EOF_INT_ENA (BIT(10))
+#define I2S_I2S_IN_ERR_EOF_INT_ENA_S 10
+#define I2S_I2S_IN_SUC_EOF_INT_ENA (BIT(9))
+#define I2S_I2S_IN_SUC_EOF_INT_ENA_S 9
+#define I2S_I2S_IN_DONE_INT_ENA (BIT(8))
+#define I2S_I2S_IN_DONE_INT_ENA_S 8
+#define I2S_I2S_TX_HUNG_INT_ENA (BIT(7))
+#define I2S_I2S_TX_HUNG_INT_ENA_S 7
+#define I2S_I2S_RX_HUNG_INT_ENA (BIT(6))
+#define I2S_I2S_RX_HUNG_INT_ENA_S 6
+#define I2S_I2S_TX_REMPTY_INT_ENA (BIT(5))
+#define I2S_I2S_TX_REMPTY_INT_ENA_S 5
+#define I2S_I2S_TX_WFULL_INT_ENA (BIT(4))
+#define I2S_I2S_TX_WFULL_INT_ENA_S 4
+#define I2S_I2S_RX_REMPTY_INT_ENA (BIT(3))
+#define I2S_I2S_RX_REMPTY_INT_ENA_S 3
+#define I2S_I2S_RX_WFULL_INT_ENA (BIT(2))
+#define I2S_I2S_RX_WFULL_INT_ENA_S 2
+#define I2S_I2S_TX_PUT_DATA_INT_ENA (BIT(1))
+#define I2S_I2S_TX_PUT_DATA_INT_ENA_S 1
+#define I2S_I2S_RX_TAKE_DATA_INT_ENA (BIT(0))
+#define I2S_I2S_RX_TAKE_DATA_INT_ENA_S 0
+
+#define I2SINT_CLR (DR_REG_I2S_BASE + 0x0018)
+#define I2S_I2S_OUT_TOTAL_EOF_INT_CLR (BIT(16))
+#define I2S_I2S_OUT_TOTAL_EOF_INT_CLR_S 16
+#define I2S_I2S_IN_DSCR_EMPTY_INT_CLR (BIT(15))
+#define I2S_I2S_IN_DSCR_EMPTY_INT_CLR_S 15
+#define I2S_I2S_OUT_DSCR_ERR_INT_CLR (BIT(14))
+#define I2S_I2S_OUT_DSCR_ERR_INT_CLR_S 14
+#define I2S_I2S_IN_DSCR_ERR_INT_CLR (BIT(13))
+#define I2S_I2S_IN_DSCR_ERR_INT_CLR_S 13
+#define I2S_I2S_OUT_EOF_INT_CLR (BIT(12))
+#define I2S_I2S_OUT_EOF_INT_CLR_S 12
+#define I2S_I2S_OUT_DONE_INT_CLR (BIT(11))
+#define I2S_I2S_OUT_DONE_INT_CLR_S 11
+#define I2S_I2S_IN_ERR_EOF_INT_CLR (BIT(10))
+#define I2S_I2S_IN_ERR_EOF_INT_CLR_S 10
+#define I2S_I2S_IN_SUC_EOF_INT_CLR (BIT(9))
+#define I2S_I2S_IN_SUC_EOF_INT_CLR_S 9
+#define I2S_I2S_IN_DONE_INT_CLR (BIT(8))
+#define I2S_I2S_IN_DONE_INT_CLR_S 8
+#define I2S_I2S_TX_HUNG_INT_CLR (BIT(7))
+#define I2S_I2S_TX_HUNG_INT_CLR_S 7
+#define I2S_I2S_RX_HUNG_INT_CLR (BIT(6))
+#define I2S_I2S_RX_HUNG_INT_CLR_S 6
+#define I2S_I2S_TX_REMPTY_INT_CLR (BIT(5))
+#define I2S_I2S_TX_REMPTY_INT_CLR_S 5
+#define I2S_I2S_TX_WFULL_INT_CLR (BIT(4))
+#define I2S_I2S_TX_WFULL_INT_CLR_S 4
+#define I2S_I2S_RX_REMPTY_INT_CLR (BIT(3))
+#define I2S_I2S_RX_REMPTY_INT_CLR_S 3
+#define I2S_I2S_RX_WFULL_INT_CLR (BIT(2))
+#define I2S_I2S_RX_WFULL_INT_CLR_S 2
+#define I2S_I2S_PUT_DATA_INT_CLR (BIT(1))
+#define I2S_I2S_PUT_DATA_INT_CLR_S 1
+#define I2S_I2S_TAKE_DATA_INT_CLR (BIT(0))
+#define I2S_I2S_TAKE_DATA_INT_CLR_S 0
+
+#define I2STIMING (DR_REG_I2S_BASE + 0x001c)
+#define I2S_TX_BCK_IN_INV (BIT(24))
+#define I2S_TX_BCK_IN_INV_S 24
+#define I2S_DATA_ENABLE_DELAY 0x00000003
+#define I2S_DATA_ENABLE_DELAY_S 22
+#define I2S_RX_DSYNC_SW (BIT(21))
+#define I2S_RX_DSYNC_SW_S 21
+#define I2S_TX_DSYNC_SW (BIT(20))
+#define I2S_TX_DSYNC_SW_S 20
+#define I2S_RX_BCK_OUT_DELAY 0x00000003
+#define I2S_RX_BCK_OUT_DELAY_S 18
+#define I2S_RX_WS_OUT_DELAY 0x00000003
+#define I2S_RX_WS_OUT_DELAY_S 16
+#define I2S_TX_SD_OUT_DELAY 0x00000003
+#define I2S_TX_SD_OUT_DELAY_S 14
+#define I2S_TX_WS_OUT_DELAY 0x00000003
+#define I2S_TX_WS_OUT_DELAY_S 12
+#define I2S_TX_BCK_OUT_DELAY 0x00000003
+#define I2S_TX_BCK_OUT_DELAY_S 10
+#define I2S_RX_SD_IN_DELAY 0x00000003
+#define I2S_RX_SD_IN_DELAY_S 8
+#define I2S_RX_WS_IN_DELAY 0x00000003
+#define I2S_RX_WS_IN_DELAY_S 6
+#define I2S_RX_BCK_IN_DELAY 0x00000003
+#define I2S_RX_BCK_IN_DELAY_S 4
+#define I2S_TX_WS_IN_DELAY 0x00000003
+#define I2S_TX_WS_IN_DELAY_S 2
+#define I2S_TX_BCK_IN_DELAY 0x00000003
+#define I2S_TX_BCK_IN_DELAY_S 0
+
+#define I2S_FIFO_CONF (DR_REG_I2S_BASE + 0x0020)
+#define I2S_I2S_RX_FIFO_MOD_FORCE_EN (BIT(20))
+#define I2S_I2S_RX_FIFO_MOD_FORCE_EN_S 20
+#define I2S_I2S_TX_FIFO_MOD_FORCE_EN (BIT(19))
+#define I2S_I2S_TX_FIFO_MOD_FORCE_EN_S 19
+#define I2S_I2S_RX_FIFO_MOD 0x00000007
+#define I2S_I2S_RX_FIFO_MOD_S 16
+#define I2S_I2S_TX_FIFO_MOD 0x00000007
+#define I2S_I2S_TX_FIFO_MOD_S 13
+#define I2S_I2S_DSCR_EN (BIT(12))
+#define I2S_I2S_DSCR_EN_S 12
+#define I2S_I2S_TX_DATA_NUM 0x0000003F
+#define I2S_I2S_TX_DATA_NUM_S 6
+#define I2S_I2S_RX_DATA_NUM 0x0000003F
+#define I2S_I2S_RX_DATA_NUM_S 0
+
+#define I2SRXEOF_NUM (DR_REG_I2S_BASE + 0x0024)
+#define I2S_I2S_RX_EOF_NUM 0xFFFFFFFF
+#define I2S_I2S_RX_EOF_NUM_S 0
+
+#define I2SCONF_SIGLE_DATA (DR_REG_I2S_BASE + 0x0028)
+#define I2S_I2S_SIGLE_DATA 0xFFFFFFFF
+#define I2S_I2S_SIGLE_DATA_S 0
+
+#define I2SCONF_CHAN (DR_REG_I2S_BASE + 0x002c)
+#define I2S_RX_CHAN_MOD 0x00000003
+#define I2S_RX_CHAN_MOD_S 3
+#define I2S_TX_CHAN_MOD 0x00000007
+#define I2S_TX_CHAN_MOD_S 0
+
+#define I2SOUT_LINK (DR_REG_I2S_BASE + 0x0030)
+#define I2S_OUTLINK_PARK (BIT(31))
+#define I2S_OUTLINK_PARK_S 31
+#define I2S_I2S_OUTLINK_RESTART (BIT(30))
+#define I2S_I2S_OUTLINK_RESTART_S 30
+#define I2S_I2S_OUTLINK_START (BIT(29))
+#define I2S_I2S_OUTLINK_START_S 29
+#define I2S_I2S_OUTLINK_STOP (BIT(28))
+#define I2S_I2S_OUTLINK_STOP_S 28
+#define I2S_I2S_OUTLINK_ADDR 0x000FFFFF
+#define I2S_I2S_OUTLINK_ADDR_S 0
+
+#define I2SIN_LINK (DR_REG_I2S_BASE + 0x0034)
+#define I2S_INLINK_PARK (BIT(31))
+#define I2S_INLINK_PARK_S 31
+#define I2S_I2S_INLINK_RESTART (BIT(30))
+#define I2S_I2S_INLINK_RESTART_S 30
+#define I2S_I2S_INLINK_START (BIT(29))
+#define I2S_I2S_INLINK_START_S 29
+#define I2S_I2S_INLINK_STOP (BIT(28))
+#define I2S_I2S_INLINK_STOP_S 28
+#define I2S_I2S_INLINK_ADDR 0x000FFFFF
+#define I2S_I2S_INLINK_ADDR_S 0
+
+#define I2S_OUT_EOF_DES_ADDR (DR_REG_I2S_BASE + 0x0038)
+#define I2S_I2S_OUT_EOF_DES_ADDR 0xFFFFFFFF
+#define I2S_I2S_OUT_EOF_DES_ADDR_S 0
+
+#define I2S_IN_EOF_DES_ADDR (DR_REG_I2S_BASE + 0x003c)
+#define I2S_I2S_IN_SUC_EOF_DES_ADDR 0xFFFFFFFF
+#define I2S_I2S_IN_SUC_EOF_DES_ADDR_S 0
+
+#define I2S_OUT_EOF_BFR_DES_ADDR (DR_REG_I2S_BASE + 0x0040)
+#define I2S_I2S_OUT_EOF_BFR_DES_ADDR 0xFFFFFFFF
+#define I2S_I2S_OUT_EOF_BFR_DES_ADDR_S 0
+
+#define I2S_AHB_TEST (DR_REG_I2S_BASE + 0x0044)
+#define I2S_I2S_AHB_TESTADDR 0x00000003
+#define I2S_I2S_AHB_TESTADDR_S 4
+#define I2S_I2S_AHB_TESTMODE 0x00000007
+#define I2S_I2S_AHB_TESTMODE_S 0
+
+#define I2S_INLINK_DSCR (DR_REG_I2S_BASE + 0x0048)
+#define I2S_I2S_INLINK_DSCR 0xFFFFFFFF
+#define I2S_I2S_INLINK_DSCR_S 0
+
+#define I2S_INLINK_DSCR_BF0 (DR_REG_I2S_BASE + 0x004C)
+#define I2S_I2S_INLINK_DSCR_BF0 0xFFFFFFFF
+#define I2S_I2S_INLINK_DSCR_BF0_S 0
+
+#define I2S_INLINK_DSCR_BF1 (DR_REG_I2S_BASE + 0x0050)
+#define I2S_I2S_INLINK_DSCR_BF1 0xFFFFFFFF
+#define I2S_I2S_INLINK_DSCR_BF1_S 0
+
+#define I2S_OUTLINK_DSCR (DR_REG_I2S_BASE + 0x0054)
+#define I2S_I2S_OUTLINK_DSCR 0xFFFFFFFF
+#define I2S_I2S_OUTLINK_DSCR_S 0
+
+#define I2S_OUTLINK_DSCR_BF0 (DR_REG_I2S_BASE + 0x0058)
+#define I2S_I2S_OUTLINK_DSCR_BF0 0xFFFFFFFF
+#define I2S_I2S_OUTLINK_DSCR_BF0_S 0
+
+#define I2S_OUTLINK_DSCR_BF1 (DR_REG_I2S_BASE + 0x005C)
+#define I2S_I2S_OUTLINK_DSCR_BF1 0xFFFFFFFF
+#define I2S_I2S_OUTLINK_DSCR_BF1_S 0
+
+#define I2S_LC_CONF (DR_REG_I2S_BASE + 0x0060)
+#define I2S_I2S_MEM_TRANS_EN (BIT(13))
+#define I2S_I2S_MEM_TRANS_EN_S 13
+#define I2S_I2S_CHECK_OWNER (BIT(12))
+#define I2S_I2S_CHECK_OWNER_S 12
+#define I2S_I2S_OUT_DATA_BURST_EN (BIT(11))
+#define I2S_I2S_OUT_DATA_BURST_EN_S 11
+#define I2S_I2S_INDSCR_BURST_EN (BIT(10))
+#define I2S_I2S_INDSCR_BURST_EN_S 10
+#define I2S_I2S_OUTDSCR_BURST_EN (BIT(9))
+#define I2S_I2S_OUTDSCR_BURST_EN_S 9
+#define I2S_I2S_OUT_EOF_MODE (BIT(8))
+#define I2S_I2S_OUT_EOF_MODE_S 8
+#define I2S_I2S_OUT_NO_RESTART_CLR (BIT(7))
+#define I2S_I2S_OUT_NO_RESTART_CLR_S 7
+#define I2S_I2S_OUT_AUTO_WRBACK (BIT(6))
+#define I2S_I2S_OUT_AUTO_WRBACK_S 6
+#define I2S_I2S_IN_LOOP_TEST (BIT(5))
+#define I2S_I2S_IN_LOOP_TEST_S 5
+#define I2S_I2S_OUT_LOOP_TEST (BIT(4))
+#define I2S_I2S_OUT_LOOP_TEST_S 4
+#define I2S_I2S_AHBM_RST (BIT(3))
+#define I2S_I2S_AHBM_RST_S 3
+#define I2S_I2S_AHBM_FIFO_RST (BIT(2))
+#define I2S_I2S_AHBM_FIFO_RST_S 2
+#define I2S_I2S_OUT_RST (BIT(1))
+#define I2S_I2S_OUT_RST_S 1
+#define I2S_I2S_IN_RST (BIT(0))
+#define I2S_I2S_IN_RST_S 0
+
+#define I2S_OUTFIFO_PUSH (DR_REG_I2S_BASE + 0x0064)
+#define I2S_I2S_OUTFIFO_PUSH (BIT(16))
+#define I2S_I2S_OUTFIFO_PUSH_S 16
+#define I2S_I2S_OUTFIFO_WDATA 0x000001FF
+#define I2S_I2S_OUTFIFO_WDATA_S 0
+
+#define I2S_INFIFO_POP (DR_REG_I2S_BASE + 0x0068)
+#define I2S_I2S_INFIFO_POP (BIT(16))
+#define I2S_I2S_INFIFO_POP_S 16
+#define I2S_I2S_INFIFO_RDATA 0x00000FFF
+#define I2S_I2S_INFIFO_RDATA_S 0
+
+#define I2S_LC_STATE0 (DR_REG_I2S_BASE + 0x006C)
+#define I2S_I2S_LC_STATE0 0xFFFFFFFF
+#define I2S_I2S_LC_STATE0_S 0
+
+#define I2S_LC_STATE1 (DR_REG_I2S_BASE + 0x0070)
+#define I2S_I2S_LC_STATE1 0xFFFFFFFF
+#define I2S_I2S_LC_STATE1_S 0
+
+#define I2S_LC_HUNG_CONF (DR_REG_I2S_BASE + 0x0074)
+#define I2S_I2S_LC_FIFO_TIMEOUT_ENA (BIT(11))
+#define I2S_I2S_LC_FIFO_TIMEOUT_ENA_S 11
+#define I2S_I2S_LC_FIFO_TIMEOUT_SHIFT 0x00000007
+#define I2S_I2S_LC_FIFO_TIMEOUT_SHIFT_S 8
+#define I2S_I2S_LC_FIFO_TIMEOUT 0x000000FF
+#define I2S_I2S_LC_FIFO_TIMEOUT_S 0
+
+#define I2S_CVSD_CONF0 (DR_REG_I2S_BASE + 0x0080)
+#define I2S_I2S_CVSD_Y_MIN 0x0000FFFF
+#define I2S_I2S_CVSD_Y_MIN_S 16
+#define I2S_I2S_CVSD_Y_MAX 0x0000FFFF
+#define I2S_I2S_CVSD_Y_MAX_S 0
+
+#define I2S_CVSD_CONF1 (DR_REG_I2S_BASE + 0x0084)
+#define I2S_I2S_CVSD_SIGMA_MIN 0x0000FFFF
+#define I2S_I2S_CVSD_SIGMA_MIN_S 16
+#define I2S_I2S_CVSD_SIGMA_MAX 0x0000FFFF
+#define I2S_I2S_CVSD_SIGMA_MAX_S 0
+
+#define I2S_CVSD_CONF2 (DR_REG_I2S_BASE + 0x0088)
+#define I2S_I2S_CVSD_H 0x00000007
+#define I2S_I2S_CVSD_H_S 16
+#define I2S_I2S_CVSD_BETA 0x000003FF
+#define I2S_I2S_CVSD_BETA_S 6
+#define I2S_I2S_CVSD_J 0x00000007
+#define I2S_I2S_CVSD_J_S 3
+#define I2S_I2S_CVSD_K 0x00000007
+#define I2S_I2S_CVSD_K_S 0
+
+#define I2S_PLC_CONF0 (DR_REG_I2S_BASE + 0x008C)
+#define I2S_I2S_N_MIN_ERR 0x00000007
+#define I2S_I2S_N_MIN_ERR_S 25
+#define I2S_I2S_PACK_LEN_8K 0x0000001F
+#define I2S_I2S_PACK_LEN_8K_S 20
+#define I2S_I2S_MAX_SLIDE_SAMPLE 0x000000FF
+#define I2S_I2S_MAX_SLIDE_SAMPLE_S 12
+#define I2S_I2S_SHIFT_RATE 0x00000007
+#define I2S_I2S_SHIFT_RATE_S 9
+#define I2S_I2S_N_ERR_SEG 0x00000007
+#define I2S_I2S_N_ERR_SEG_S 6
+#define I2S_I2S_GOOD_PACK_MAX 0x0000003F
+#define I2S_I2S_GOOD_PACK_MAX_S 0
+
+#define I2S_PLC_CONF1 (DR_REG_I2S_BASE + 0x0090)
+#define I2S_I2S_SLIDE_WIN_LEN 0x000000FF
+#define I2S_I2S_SLIDE_WIN_LEN_S 24
+#define I2S_I2S_BAD_OLA_WIN2_PARA 0x000000FF
+#define I2S_I2S_BAD_OLA_WIN2_PARA_S 16
+#define I2S_I2S_BAD_OLA_WIN2_PARA_SHIFT 0x0000000F
+#define I2S_I2S_BAD_OLA_WIN2_PARA_SHIFT_S 12
+#define I2S_I2S_BAD_CEF_ATTEN_PARA_SHIFT 0x0000000F
+#define I2S_I2S_BAD_CEF_ATTEN_PARA_SHIFT_S 8
+#define I2S_I2S_BAD_CEF_ATTEN_PARA 0x000000FF
+#define I2S_I2S_BAD_CEF_ATTEN_PARA_S 0
+
+#define I2S_PLC_CONF2 (DR_REG_I2S_BASE + 0x0094)
+#define I2S_I2S_MIN_PERIOD 0x0000001F
+#define I2S_I2S_MIN_PERIOD_S 2
+#define I2S_I2S_CVSD_SEG_MOD 0x00000003
+#define I2S_I2S_CVSD_SEG_MOD_S 0
+
+#define I2S_ESCO_CONF0 (DR_REG_I2S_BASE + 0x0098)
+#define I2S_I2S_PLC2DMA_EN (BIT(12))
+#define I2S_I2S_PLC2DMA_EN_S 12
+#define I2S_I2S_PLC_EN (BIT(11))
+#define I2S_I2S_PLC_EN_S 11
+#define I2S_I2S_CVSD_DEC_RESET (BIT(10))
+#define I2S_I2S_CVSD_DEC_RESET_S 10
+#define I2S_I2S_CVSD_DEC_START (BIT(9))
+#define I2S_I2S_CVSD_DEC_START_S 9
+#define I2S_I2S_ESCO_CVSD_INF_EN (BIT(8))
+#define I2S_I2S_ESCO_CVSD_INF_EN_S 8
+#define I2S_I2S_ESCO_CVSD_PACK_LEN_8K 0x0000001F
+#define I2S_I2S_ESCO_CVSD_PACK_LEN_8K_S 3
+#define I2S_I2S_ESCO_CVSD_DEC_PACK_ERR (BIT(2))
+#define I2S_I2S_ESCO_CVSD_DEC_PACK_ERR_S 2
+#define I2S_I2S_ESCO_CHAN_MOD (BIT(1))
+#define I2S_I2S_ESCO_CHAN_MOD_S 1
+#define I2S_I2S_ESCO_EN (BIT(0))
+#define I2S_I2S_ESCO_EN_S 0
+
+#define I2S_SCO_CONF0 (DR_REG_I2S_BASE + 0x009c)
+#define I2S_I2S_CVSD_ENC_RESET (BIT(3))
+#define I2S_I2S_CVSD_ENC_RESET_S 3
+#define I2S_I2S_CVSD_ENC_START (BIT(2))
+#define I2S_I2S_CVSD_ENC_START_S 2
+#define I2S_I2S_SCO_NO_I2S_EN (BIT(1))
+#define I2S_I2S_SCO_NO_I2S_EN_S 1
+#define I2S_I2S_SCO_WITH_I2S_EN (BIT(0))
+#define I2S_I2S_SCO_WITH_I2S_EN_S 0
+
+#define I2SCONF1 (DR_REG_I2S_BASE + 0x00a0)
+#define I2S_I2S_TX_ZEROS_RM_EN (BIT(9))
+#define I2S_I2S_TX_ZEROS_RM_EN_S 9
+#define I2S_I2S_TX_STOP_EN (BIT(8))
+#define I2S_I2S_TX_STOP_EN_S 8
+#define I2S_RX_PCM_BYPASS (BIT(7))
+#define I2S_RX_PCM_BYPASS_S 7
+#define I2S_RX_PCM_CONF 0x00000007
+#define I2S_RX_PCM_CONF_S 4
+#define I2S_TX_PCM_BYPASS (BIT(3))
+#define I2S_TX_PCM_BYPASS_S 3
+#define I2S_TX_PCM_CONF 0x00000007
+#define I2S_TX_PCM_CONF_S 0
+
+#define I2S_PD_CONF (DR_REG_I2S_BASE + 0x00a4)
+#define I2S_PLC_MEM_FORCE_PU (BIT(3))
+#define I2S_PLC_MEM_FORCE_PU_S 3
+#define I2S_PLC_MEM_FORCE_PD (BIT(2))
+#define I2S_PLC_MEM_FORCE_PD_S 2
+#define I2S_I2S_FIFO_FORCE_PU (BIT(1))
+#define I2S_I2S_FIFO_FORCE_PU_S 1
+#define I2S_I2S_FIFO_FORCE_PD (BIT(0))
+#define I2S_I2S_FIFO_FORCE_PD_S 0
+
+#define I2SCONF2 (DR_REG_I2S_BASE + 0x00a8)
+#define I2S_INTER_VALID_EN (BIT(7))
+#define I2S_INTER_VALID_EN_S 7
+#define I2S_EXT_ADC_START_EN (BIT(6))
+#define I2S_EXT_ADC_START_EN_S 6
+#define I2S_LCD_EN (BIT(5))
+#define I2S_LCD_EN_S 5
+#define I2S_DATA_ENABLE (BIT(4))
+#define I2S_DATA_ENABLE_S 4
+#define I2S_DATA_ENABLE_TEST_EN (BIT(3))
+#define I2S_DATA_ENABLE_TEST_EN_S 3
+#define I2S_LCD_TX_SDX2_EN (BIT(2))
+#define I2S_LCD_TX_SDX2_EN_S 2
+#define I2S_LCD_TX_WRX2_EN (BIT(1))
+#define I2S_LCD_TX_WRX2_EN_S 1
+#define I2S_CAMERA_EN (BIT(0))
+#define I2S_CAMERA_EN_S 0
+
+#define I2S_CLKM_CONF (DR_REG_I2S_BASE + 0x00ac)
+#define I2S_CLKA_ENA (BIT(21))
+#define I2S_CLKA_ENA_S 21
+#define I2S_CLK_EN (BIT(20))
+#define I2S_CLK_EN_S 20
+#define I2S_CLKM_DIV_A 0x0000003F
+#define I2S_CLKM_DIV_A_S 14
+#define I2S_CLKM_DIV_B 0x0000003F
+#define I2S_CLKM_DIV_B_S 8
+#define I2S_CLKM_DIV_NUM 0x000000FF
+#define I2S_CLKM_DIV_NUM_S 0
+
+#define I2S_SAMPLE_RATE_CONF (DR_REG_I2S_BASE + 0x00b0)
+#define I2S_RX_BITS_MOD 0x0000003F
+#define I2S_RX_BITS_MOD_S 18
+#define I2S_TX_BITS_MOD 0x0000003F
+#define I2S_TX_BITS_MOD_S 12
+#define I2S_RX_BCK_DIV_NUM 0x0000003F
+#define I2S_RX_BCK_DIV_NUM_S 6
+#define I2S_TX_BCK_DIV_NUM 0x0000003F
+#define I2S_TX_BCK_DIV_NUM_S 0
+
+#define I2S_PDM_CONF (DR_REG_I2S_BASE + 0x00b4)
+#define I2S_TX_PDM_HP_BYPASS (BIT(25))
+#define I2S_TX_PDM_HP_BYPASS_S 25
+#define I2S_RX_PDM_SINC_DSR_16_EN (BIT(24))
+#define I2S_RX_PDM_SINC_DSR_16_EN_S 24
+#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT 0x00000003
+#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_S 22
+#define I2S_TX_PDM_SINC_IN_SHIFT 0x00000003
+#define I2S_TX_PDM_SINC_IN_SHIFT_S 20
+#define I2S_TX_PDM_LP_IN_SHIFT 0x00000003
+#define I2S_TX_PDM_LP_IN_SHIFT_S 18
+#define I2S_TX_PDM_HP_IN_SHIFT 0x00000003
+#define I2S_TX_PDM_HP_IN_SHIFT_S 16
+#define I2S_TX_PDM_PRESCALE 0x000000FF
+#define I2S_TX_PDM_PRESCALE_S 8
+#define I2S_TX_PDM_SINC_OSR2 0x0000000F
+#define I2S_TX_PDM_SINC_OSR2_S 4
+#define I2S_PDM2PCM_CONV_EN (BIT(3))
+#define I2S_PDM2PCM_CONV_EN_S 3
+#define I2S_PCM2PDM_CONV_EN (BIT(2))
+#define I2S_PCM2PDM_CONV_EN_S 2
+#define I2S_RX_PDM_EN (BIT(1))
+#define I2S_RX_PDM_EN_S 1
+#define I2S_TX_PDM_EN (BIT(0))
+#define I2S_TX_PDM_EN_S 0
+
+#define I2S_PDM_FREQ_CONF (DR_REG_I2S_BASE + 0x00b8)
+#define I2S_TX_PDM_FP 0x000003FF
+#define I2S_TX_PDM_FP_S 10
+#define I2S_TX_PDM_FS 0x000003FF
+#define I2S_TX_PDM_FS_S 0
+
+#define I2S_STATE (DR_REG_I2S_BASE + 0x00bc)
+#define I2S_I2S_RX_FIFO_RESET_BACK (BIT(2))
+#define I2S_I2S_RX_FIFO_RESET_BACK_S 2
+#define I2S_I2S_TX_FIFO_RESET_BACK (BIT(1))
+#define I2S_I2S_TX_FIFO_RESET_BACK_S 1
+#define I2S_I2S_TX_IDLE (BIT(0))
+#define I2S_I2S_TX_IDLE_S 0
+
+#define I2S_DATE (DR_REG_I2S_BASE + 0x00fc)
+#define I2S_I2SDATE 0xFFFFFFFF
+#define I2S_I2SDATE_S 0
+
+#endif /* _SOC_I2S_REG_H_ */

components/esp32/include/soc/io_mux_reg.h

@@ -0,0 +1,264 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_IO_MUX_REG_H_
+#define _SOC_IO_MUX_REG_H_
+
+#include "soc.h"
+
+#define SLP_OE (BIT(0))
+#define SLP_SEL (BIT(1))
+#define SLP_PD (BIT(2))
+#define SLP_PU (BIT(3))
+#define SLP_IE (BIT(4))
+#define SLP_DRV 0x3
+#define SLP_DRV_S 5
+#define FUN_PD (BIT(7))
+#define FUN_PU (BIT(8))
+#define FUN_IE (BIT(9))
+#define FUN_DRV 0x3
+#define FUN_DRV_S 10
+#define MCU_SEL 0x7
+#define MCU_SEL_S 12
+
+
+#define PIN_SET_DRV(PIN_NAME, drv)            REG_SET_FIELD(PIN_NAME, FUN_DRV, (drv));
+#define PIN_PULLUP_DIS(PIN_NAME)                 REG_CLR_BIT(PIN_NAME, FUN_PU)
+#define PIN_PULLUP_EN(PIN_NAME)                  REG_SET_BIT(PIN_NAME, FUN_PU)
+#define PIN_PULLDWN_DIS(PIN_NAME)             REG_CLR_BIT(PIN_NAME, FUN_PD)
+#define PIN_PULLDWN_EN(PIN_NAME)              REG_SET_BIT(PIN_NAME, FUN_PD)
+#define PIN_FUNC_SELECT(PIN_NAME, FUNC)      REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC)
+
+#define PIN_CTRL                          (DR_REG_IO_MUX_BASE +0x00)
+#define CLK_OUT3                                    0xf
+#define CLK_OUT3_S                                  8
+#define CLK_OUT2                                    0xf
+#define CLK_OUT2_S                                  4
+#define CLK_OUT1                                    0xf
+#define CLK_OUT1_S                                  0
+
+#define PERIPHS_IO_MUX_GPIO36_U           (DR_REG_IO_MUX_BASE +0x04)
+#define FUNC_GPIO36_GPIO36                          2
+#define FUNC_GPIO36_GPIO36_0                        0
+
+#define PERIPHS_IO_MUX_GPIO37_U           (DR_REG_IO_MUX_BASE +0x08)
+#define FUNC_GPIO37_GPIO37                          2
+#define FUNC_GPIO37_GPIO37_0                        0
+
+#define PERIPHS_IO_MUX_GPIO38_U           (DR_REG_IO_MUX_BASE +0x0c)
+#define FUNC_GPIO38_GPIO38                          2
+#define FUNC_GPIO38_GPIO38_0                        0
+
+#define PERIPHS_IO_MUX_GPIO39_U           (DR_REG_IO_MUX_BASE +0x10)
+#define FUNC_GPIO39_GPIO39                          2
+#define FUNC_GPIO39_GPIO39_0                        0
+
+#define PERIPHS_IO_MUX_GPIO34_U           (DR_REG_IO_MUX_BASE +0x14)
+#define FUNC_GPIO34_GPIO34                          2
+#define FUNC_GPIO34_GPIO34_0                        0
+
+#define PERIPHS_IO_MUX_GPIO35_U           (DR_REG_IO_MUX_BASE +0x18)
+#define FUNC_GPIO35_GPIO35                          2
+#define FUNC_GPIO35_GPIO35_0                        0
+
+#define PERIPHS_IO_MUX_GPIO32_U           (DR_REG_IO_MUX_BASE +0x1c)
+#define FUNC_GPIO32_GPIO32                          2
+#define FUNC_GPIO32_GPIO32_0                        0
+
+#define PERIPHS_IO_MUX_GPIO33_U           (DR_REG_IO_MUX_BASE +0x20)
+#define FUNC_GPIO33_GPIO33                          2
+#define FUNC_GPIO33_GPIO33_0                        0
+
+#define PERIPHS_IO_MUX_GPIO25_U           (DR_REG_IO_MUX_BASE +0x24)
+#define FUNC_GPIO25_GPIO25                          2
+#define FUNC_GPIO25_GPIO25_0                        0
+
+#define PERIPHS_IO_MUX_GPIO26_U           (DR_REG_IO_MUX_BASE +0x28)
+#define FUNC_GPIO26_GPIO26                          2
+#define FUNC_GPIO26_GPIO26_0                        0
+
+#define PERIPHS_IO_MUX_GPIO27_U           (DR_REG_IO_MUX_BASE +0x2c)
+#define FUNC_GPIO27_EMAC_RXD2                       5
+#define FUNC_GPIO27_GPIO27                          2
+#define FUNC_GPIO27_GPIO27_0                        0
+
+#define PERIPHS_IO_MUX_MTMS_U             (DR_REG_IO_MUX_BASE +0x30)
+#define FUNC_MTMS_EMAC_TXD2                         5
+#define FUNC_MTMS_SD_CLK                            4
+#define FUNC_MTMS_GPIO14                            2
+#define FUNC_MTMS_HSPICLK                           1
+#define FUNC_MTMS_MTMS                              0
+
+#define PERIPHS_IO_MUX_MTDI_U             (DR_REG_IO_MUX_BASE +0x34)
+#define FUNC_MTDI_EMAC_TXD3                         5
+#define FUNC_MTDI_SD_DATA2                          4
+#define FUNC_MTDI_GPIO12                            2
+#define FUNC_MTDI_HSPIQ                             1
+#define FUNC_MTDI_MTDI                              0
+
+#define PERIPHS_IO_MUX_MTCK_U             (DR_REG_IO_MUX_BASE +0x38)
+#define FUNC_MTCK_EMAC_RX_ER                        5
+#define FUNC_MTCK_SD_DATA3                          4
+#define FUNC_MTCK_U0CTS                             3
+#define FUNC_MTCK_GPIO13                            2
+#define FUNC_MTCK_HSPID                             1
+#define FUNC_MTCK_MTCK                              0
+
+#define PERIPHS_IO_MUX_MTDO_U             (DR_REG_IO_MUX_BASE +0x3c)
+#define FUNC_MTDO_EMAC_RXD3                         5
+#define FUNC_MTDO_SD_CMD                            4
+#define FUNC_MTDO_U0RTS                             3
+#define FUNC_MTDO_GPIO15                            2
+#define FUNC_MTDO_HSPICS0                           1
+#define FUNC_MTDO_MTDO                              0
+
+#define PERIPHS_IO_MUX_GPIO2_U            (DR_REG_IO_MUX_BASE +0x40)
+#define FUNC_GPIO2_EMAC_RX_DV                       5
+#define FUNC_GPIO2_SD_DATA0                         4
+#define FUNC_GPIO2_GPIO2                            2
+#define FUNC_GPIO2_HSPIWP                           1
+#define FUNC_GPIO2_GPIO2_0                          0
+
+#define PERIPHS_IO_MUX_GPIO0_U            (DR_REG_IO_MUX_BASE +0x44)
+#define FUNC_GPIO0_EMAC_TX_CLK                      5
+#define FUNC_GPIO0_HS2_CMD                          3
+#define FUNC_GPIO0_GPIO0                            2
+#define FUNC_GPIO0_CLK_OUT1                         1
+#define FUNC_GPIO0_GPIO0_0                          0
+
+#define PERIPHS_IO_MUX_GPIO4_U            (DR_REG_IO_MUX_BASE +0x48)
+#define FUNC_GPIO4_EMAC_TX_ER                       5
+#define FUNC_GPIO4_SD_DATA1                         4
+#define FUNC_GPIO4_GPIO4                            2
+#define FUNC_GPIO4_HSPIHD                           1
+#define FUNC_GPIO4_GPIO4_0                          0
+
+#define PERIPHS_IO_MUX_GPIO16_U           (DR_REG_IO_MUX_BASE +0x4c)
+#define FUNC_GPIO16_EMAC_CLK_OUT                    5
+#define FUNC_GPIO16_U2RXD                           4
+#define FUNC_GPIO16_HS1_DATA4                       3
+#define FUNC_GPIO16_GPIO16                          2
+#define FUNC_GPIO16_GPIO16_0                        0
+
+#define PERIPHS_IO_MUX_GPIO17_U           (DR_REG_IO_MUX_BASE +0x50)
+#define FUNC_GPIO17_EMAC_CLK_OUT_180                5
+#define FUNC_GPIO17_U2TXD                           4
+#define FUNC_GPIO17_HS1_DATA5                       3
+#define FUNC_GPIO17_GPIO17                          2
+#define FUNC_GPIO17_GPIO17_0                        0
+
+#define PERIPHS_IO_MUX_SD_DATA2_U         (DR_REG_IO_MUX_BASE +0x54)
+#define FUNC_SD_DATA2_U1RXD                         4
+#define FUNC_SD_DATA2_HS1_DATA2                     3
+#define FUNC_SD_DATA2_GPIO9                         2
+#define FUNC_SD_DATA2_SPIHD                         1
+#define FUNC_SD_DATA2_SD_DATA2                      0
+
+#define PERIPHS_IO_MUX_SD_DATA3_U         (DR_REG_IO_MUX_BASE +0x58)
+#define FUNC_SD_DATA3_U1TXD                         4
+#define FUNC_SD_DATA3_HS1_DATA3                     3
+#define FUNC_SD_DATA3_GPIO10                        2
+#define FUNC_SD_DATA3_SPIWP                         1
+#define FUNC_SD_DATA3_SD_DATA3                      0
+
+#define PERIPHS_IO_MUX_SD_CMD_U           (DR_REG_IO_MUX_BASE +0x5c)
+#define FUNC_SD_CMD_U1RTS                           4
+#define FUNC_SD_CMD_HS1_CMD                         3
+#define FUNC_SD_CMD_GPIO11                          2
+#define FUNC_SD_CMD_SPICS0                          1
+#define FUNC_SD_CMD_SD_CMD                          0
+
+#define PERIPHS_IO_MUX_SD_CLK_U           (DR_REG_IO_MUX_BASE +0x60)
+#define FUNC_SD_CLK_U1CTS                           4
+#define FUNC_SD_CLK_HS1_CLK                         3
+#define FUNC_SD_CLK_GPIO6                           2
+#define FUNC_SD_CLK_SPICLK                          1
+#define FUNC_SD_CLK_SD_CLK                          0
+
+#define PERIPHS_IO_MUX_SD_DATA0_U         (DR_REG_IO_MUX_BASE +0x64)
+#define FUNC_SD_DATA0_U2RTS                         4
+#define FUNC_SD_DATA0_HS1_DATA0                     3
+#define FUNC_SD_DATA0_GPIO7                         2
+#define FUNC_SD_DATA0_SPIQ                          1
+#define FUNC_SD_DATA0_SD_DATA0                      0
+
+#define PERIPHS_IO_MUX_SD_DATA1_U         (DR_REG_IO_MUX_BASE +0x68)
+#define FUNC_SD_DATA1_U2CTS                         4
+#define FUNC_SD_DATA1_HS1_DATA1                     3
+#define FUNC_SD_DATA1_GPIO8                         2
+#define FUNC_SD_DATA1_SPID                          1
+#define FUNC_SD_DATA1_SD_DATA1                      0
+
+#define PERIPHS_IO_MUX_GPIO5_U            (DR_REG_IO_MUX_BASE +0x6c)
+#define FUNC_GPIO5_EMAC_RX_CLK                      5
+#define FUNC_GPIO5_HS1_DATA6                        3
+#define FUNC_GPIO5_GPIO5                            2
+#define FUNC_GPIO5_VSPICS0                          1
+#define FUNC_GPIO5_GPIO5_0                          0
+
+#define PERIPHS_IO_MUX_GPIO18_U           (DR_REG_IO_MUX_BASE +0x70)
+#define FUNC_GPIO18_EMAC_TXD0                       5
+#define FUNC_GPIO18_HS1_DATA7                       3
+#define FUNC_GPIO18_GPIO18                          2
+#define FUNC_GPIO18_VSPICLK                         1
+#define FUNC_GPIO18_GPIO18_0                        0
+
+#define PERIPHS_IO_MUX_GPIO19_U           (DR_REG_IO_MUX_BASE +0x74)
+#define FUNC_GPIO19_EMAC_TXD1                       5
+#define FUNC_GPIO19_HS2_DATA2                       3
+#define FUNC_GPIO19_GPIO19                          2
+#define FUNC_GPIO19_VSPIQ                           1
+#define FUNC_GPIO19_GPIO19_0                        0
+
+#define PERIPHS_IO_MUX_GPIO20_U           (DR_REG_IO_MUX_BASE +0x78)
+#define FUNC_GPIO20_GPIO20                          2
+#define FUNC_GPIO20_GPIO20_0                        0
+
+#define PERIPHS_IO_MUX_GPIO21_U           (DR_REG_IO_MUX_BASE +0x7c)
+#define FUNC_GPIO21_EMAC_RXD0                       5
+#define FUNC_GPIO21_HS2_DATA3                       3
+#define FUNC_GPIO21_GPIO21                          2
+#define FUNC_GPIO21_VSPIHD                          1
+#define FUNC_GPIO21_GPIO21_0                        0
+
+#define PERIPHS_IO_MUX_GPIO22_U           (DR_REG_IO_MUX_BASE +0x80)
+#define FUNC_GPIO22_EMAC_RXD1                       5
+#define FUNC_GPIO22_HS2_CLK                         3
+#define FUNC_GPIO22_GPIO22                          2
+#define FUNC_GPIO22_VSPIWP                          1
+#define FUNC_GPIO22_GPIO22_0                        0
+
+#define PERIPHS_IO_MUX_U0RXD_U            (DR_REG_IO_MUX_BASE +0x84)
+#define FUNC_U0RXD_HS2_DATA0                        3
+#define FUNC_U0RXD_GPIO3                            2
+#define FUNC_U0RXD_CLK_OUT2                         1
+#define FUNC_U0RXD_U0RXD                            0
+
+#define PERIPHS_IO_MUX_U0TXD_U            (DR_REG_IO_MUX_BASE +0x88)
+#define FUNC_U0TXD_HS2_DATA1                        3
+#define FUNC_U0TXD_GPIO1                            2
+#define FUNC_U0TXD_CLK_OUT3                         1
+#define FUNC_U0TXD_U0TXD                            0
+
+#define PERIPHS_IO_MUX_GPIO23_U           (DR_REG_IO_MUX_BASE +0x8c)
+#define FUNC_GPIO23_EMAC_TX_EN                      5
+#define FUNC_GPIO23_HS1_STROBE                      3
+#define FUNC_GPIO23_GPIO23                          2
+#define FUNC_GPIO23_VSPID                           1
+#define FUNC_GPIO23_GPIO23_0                        0
+
+#define PERIPHS_IO_MUX_GPIO24_U           (DR_REG_IO_MUX_BASE +0x90)
+#define FUNC_GPIO24_GPIO24                          2
+#define FUNC_GPIO24_GPIO24_0                        0
+
+#endif /* _SOC_IO_MUX_REG_H_ */

components/esp32/include/soc/pid.h

@@ -0,0 +1,65 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_PID_H_
+#define _SOC_PID_H_
+
+#define PROPID_GEN_BASE 0x3FF1F000
+//Bits 1..7: 1 if interrupt will be triggering PID change
+#define PROPID_CONFIG_INTERRUPT_ENABLE	((PROPID_GEN_BASE)+0x000)
+//Vectors for the various interrupt handlers
+#define PROPID_CONFIG_INTERRUPT_ADDR_1	((PROPID_GEN_BASE)+0x004)
+#define PROPID_CONFIG_INTERRUPT_ADDR_2	((PROPID_GEN_BASE)+0x008)
+#define PROPID_CONFIG_INTERRUPT_ADDR_3	((PROPID_GEN_BASE)+0x00C)
+#define PROPID_CONFIG_INTERRUPT_ADDR_4	((PROPID_GEN_BASE)+0x010)
+#define PROPID_CONFIG_INTERRUPT_ADDR_5	((PROPID_GEN_BASE)+0x014)
+#define PROPID_CONFIG_INTERRUPT_ADDR_6	((PROPID_GEN_BASE)+0x018)
+#define PROPID_CONFIG_INTERRUPT_ADDR_7	((PROPID_GEN_BASE)+0x01C)
+
+//Delay, in CPU cycles, before switching to new PID
+#define PROPID_CONFIG_PID_DELAY			((PROPID_GEN_BASE)+0x020)
+#define PROPID_CONFIG_NMI_DELAY			((PROPID_GEN_BASE)+0x024)
+
+//Last detected interrupt. Set by hw on int.
+#define PROPID_TABLE_LEVEL				((PROPID_GEN_BASE)+0x028)
+//PID/prev int data for each int
+#define PROPID_FROM_1					((PROPID_GEN_BASE)+0x02C)
+#define PROPID_FROM_2					((PROPID_GEN_BASE)+0x030)
+#define PROPID_FROM_3					((PROPID_GEN_BASE)+0x034)
+#define PROPID_FROM_4					((PROPID_GEN_BASE)+0x038)
+#define PROPID_FROM_5					((PROPID_GEN_BASE)+0x03C)
+#define PROPID_FROM_6					((PROPID_GEN_BASE)+0x040)
+#define PROPID_FROM_7					((PROPID_GEN_BASE)+0x044)
+#define PROPID_FROM_PID_MASK	0x7
+#define PROPID_FROM_PID_S		0
+#define PROPID_FROM_INT_MASK	0xF
+#define PROPID_FROM_INT_S		3
+
+//PID to be set after confirm routine
+#define PROPID_PID_NEW					((PROPID_GEN_BASE)+0x048)
+//Write to kick off PID change
+#define PROPID_PID_CONFIRM				((PROPID_GEN_BASE)+0x04c)
+//current PID?
+#define PROPID_PID_REG					((PROPID_GEN_BASE)+0x050)
+
+//Write to mask NMI
+#define PROPID_PID_NMI_MASK_HW_ENABLE	((PROPID_GEN_BASE)+0x054)
+//Write to unmask NMI
+#define PROPID_PID_NMI_MASK_HW_DISABLE	((PROPID_GEN_BASE)+0x058)
+#define PROPID_PID_NMI_MASK_HW_REG		((PROPID_GEN_BASE)+0x05c)
+
+//Debug regs
+#define PROPID_PID						((PROPID_GEN_BASE)+0x060)
+#define PROPID_NMI_MASK_HW				((PROPID_GEN_BASE)+0x064)
+
+#endif /* _SOC_PID_H_ */

components/esp32/include/soc/rtc_cntl_reg.h

@@ -0,0 +1,751 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_RTC_CNTL_REG_H_
+#define _SOC_RTC_CNTL_REG_H_
+
+#include "soc.h"
+
+#define RTC_OPTIONS0 (DR_REG_RTCCNTL_BASE + 0x0)
+#define RTC_CNTL_SW_SYS_RST (BIT(31))
+#define RTC_CNTL_SW_SYS_RST_S 31
+#define RTC_CNTL_DG_WRAP_FORCE_NORST (BIT(30))
+#define RTC_CNTL_DG_WRAP_FORCE_NORST_S 30
+#define RTC_CNTL_DG_WRAP_FORCE_RST (BIT(29))
+#define RTC_CNTL_DG_WRAP_FORCE_RST_S 29
+#define RTC_CNTL_ANALOG_FORCE_NOISO (BIT(28))
+#define RTC_CNTL_ANALOG_FORCE_NOISO_S 28
+#define RTC_CNTL_PLL_FORCE_NOISO (BIT(27))
+#define RTC_CNTL_PLL_FORCE_NOISO_S 27
+#define RTC_CNTL_XTL_FORCE_NOISO (BIT(26))
+#define RTC_CNTL_XTL_FORCE_NOISO_S 26
+#define RTC_CNTL_ANALOG_FORCE_ISO (BIT(25))
+#define RTC_CNTL_ANALOG_FORCE_ISO_S 25
+#define RTC_CNTL_PLL_FORCE_ISO (BIT(24))
+#define RTC_CNTL_PLL_FORCE_ISO_S 24
+#define RTC_CNTL_XTL_FORCE_ISO (BIT(23))
+#define RTC_CNTL_XTL_FORCE_ISO_S 23
+#define RTC_CNTL_BIAS_CORE_FORCE_PU (BIT(22))
+#define RTC_CNTL_BIAS_CORE_FORCE_PU_S 22
+#define RTC_CNTL_BIAS_CORE_FORCE_PD (BIT(21))
+#define RTC_CNTL_BIAS_CORE_FORCE_PD_S 21
+#define RTC_CNTL_BIAS_CORE_FOLW_12M (BIT(20))
+#define RTC_CNTL_BIAS_CORE_FOLW_12M_S 20
+#define RTC_CNTL_BIAS_I2C_FORCE_PU (BIT(19))
+#define RTC_CNTL_BIAS_I2C_FORCE_PU_S 19
+#define RTC_CNTL_BIAS_I2C_FORCE_PD (BIT(18))
+#define RTC_CNTL_BIAS_I2C_FORCE_PD_S 18
+#define RTC_CNTL_BIAS_I2C_FOLW_12M (BIT(17))
+#define RTC_CNTL_BIAS_I2C_FOLW_12M_S 17
+#define RTC_CNTL_BIAS_FORCE_NOSLEEP (BIT(16))
+#define RTC_CNTL_BIAS_FORCE_NOSLEEP_S 16
+#define RTC_CNTL_BIAS_FORCE_SLEEP (BIT(15))
+#define RTC_CNTL_BIAS_FORCE_SLEEP_S 15
+#define RTC_CNTL_BIAS_SLEEP_FOLW_12M (BIT(14))
+#define RTC_CNTL_BIAS_SLEEP_FOLW_12M_S 14
+#define RTC_CNTL_XTL_FORCE_PU (BIT(13))
+#define RTC_CNTL_XTL_FORCE_PU_S 13
+#define RTC_CNTL_XTL_FORCE_PD (BIT(12))
+#define RTC_CNTL_XTL_FORCE_PD_S 12
+#define RTC_CNTL_BBPLL_FORCE_PU (BIT(11))
+#define RTC_CNTL_BBPLL_FORCE_PU_S 11
+#define RTC_CNTL_BBPLL_FORCE_PD (BIT(10))
+#define RTC_CNTL_BBPLL_FORCE_PD_S 10
+#define RTC_CNTL_BBPLL_I2C_FORCE_PU (BIT(9))
+#define RTC_CNTL_BBPLL_I2C_FORCE_PU_S 9
+#define RTC_CNTL_BBPLL_I2C_FORCE_PD (BIT(8))
+#define RTC_CNTL_BBPLL_I2C_FORCE_PD_S 8
+#define RTC_CNTL_BB_I2C_FORCE_PU (BIT(7))
+#define RTC_CNTL_BB_I2C_FORCE_PU_S 7
+#define RTC_CNTL_BB_I2C_FORCE_PD (BIT(6))
+#define RTC_CNTL_BB_I2C_FORCE_PD_S 6
+#define RTC_CNTL_SW_PROCPU_RST (BIT(5))
+#define RTC_CNTL_SW_PROCPU_RST_S 5
+#define RTC_CNTL_SW_APPCPU_RST (BIT(4))
+#define RTC_CNTL_SW_APPCPU_RST_S 4
+#define RTC_CNTL_SW_STALL_PROCPU_C0 0x00000003
+#define RTC_CNTL_SW_STALL_PROCPU_C0_S 2
+#define RTC_CNTL_SW_STALL_APPCPU_C0 0x00000003
+#define RTC_CNTL_SW_STALL_APPCPU_C0_S 0
+
+#define RTC_SLP_TIMER0 (DR_REG_RTCCNTL_BASE + 0x4)
+#define RTC_CNTL_SLP_VAL_LO 0xFFFFFFFF
+#define RTC_CNTL_SLP_VAL_LO_S 0
+
+#define RTC_SLP_TIMER1 (DR_REG_RTCCNTL_BASE + 0x8)
+#define RTC_CNTL_RTC_MAIN_TIMER_ALARM_EN (BIT(16))
+#define RTC_CNTL_RTC_MAIN_TIMER_ALARM_EN_S 16
+#define RTC_CNTL_SLP_VAL_HI 0x0000FFFF
+#define RTC_CNTL_SLP_VAL_HI_S 0
+
+#define RTC_TIME_UPDATE (DR_REG_RTCCNTL_BASE + 0xc)
+#define RTC_CNTL_RTC_TIME_UPDATE (BIT(31))
+#define RTC_CNTL_RTC_TIME_UPDATE_S 31
+#define RTC_CNTL_RTC_TIME_VALID (BIT(30))
+#define RTC_CNTL_RTC_TIME_VALID_S 30
+
+#define RTC_TIME0 (DR_REG_RTCCNTL_BASE + 0x10)
+#define RTC_CNTL_RTC_TIME_LO 0xFFFFFFFF
+#define RTC_CNTL_RTC_TIME_LO_S 0
+
+#define RTC_TIME1 (DR_REG_RTCCNTL_BASE + 0x14)
+#define RTC_CNTL_RTC_TIME_HI 0x0000FFFF
+#define RTC_CNTL_RTC_TIME_HI_S 0
+
+#define RTC_STATE0 (DR_REG_RTCCNTL_BASE + 0x18)
+#define RTC_CNTL_SLEEP_EN (BIT(31))
+#define RTC_CNTL_SLEEP_EN_S 31
+#define RTC_CNTL_SLP_REJECT (BIT(30))
+#define RTC_CNTL_SLP_REJECT_S 30
+#define RTC_CNTL_SLP_WAKEUP (BIT(29))
+#define RTC_CNTL_SLP_WAKEUP_S 29
+#define RTC_CNTL_SDIO_ACTIVE_IND (BIT(28))
+#define RTC_CNTL_SDIO_ACTIVE_IND_S 28
+#define RTC_CNTL_SAR_SLP_TIMER_EN (BIT(24))
+#define RTC_CNTL_SAR_SLP_TIMER_EN_S 24
+#define RTC_CNTL_TOUCH_SLP_TIMER_EN (BIT(23))
+#define RTC_CNTL_TOUCH_SLP_TIMER_EN_S 23
+#define RTC_CNTL_APB2RTC_BRIDGE_SEL (BIT(22))
+#define RTC_CNTL_APB2RTC_BRIDGE_SEL_S 22
+#define RTC_CNTL_SAR_WAKEUP_FORCE_EN (BIT(21))
+#define RTC_CNTL_SAR_WAKEUP_FORCE_EN_S 21
+#define RTC_CNTL_TOUCH_WAKEUP_FORCE_EN (BIT(20))
+#define RTC_CNTL_TOUCH_WAKEUP_FORCE_EN_S 20
+
+#define RTC_TIMER1 (DR_REG_RTCCNTL_BASE + 0x1c)
+#define RTC_CNTL_PLL_BUF_WAIT 0x000000FF
+#define RTC_CNTL_PLL_BUF_WAIT_S 24
+#define RTC_CNTL_XTL_BUF_WAIT 0x000003FF
+#define RTC_CNTL_XTL_BUF_WAIT_S 14
+#define RTC_CNTL_CK12M_WAIT 0x000000FF
+#define RTC_CNTL_CK12M_WAIT_S 6
+#define RTC_CNTL_CPU_STALL_WAIT 0x0000001F
+#define RTC_CNTL_CPU_STALL_WAIT_S 1
+#define RTC_CNTL_CPU_STALL_EN (BIT(0))
+#define RTC_CNTL_CPU_STALL_EN_S 0
+
+#define RTC_TIMER2 (DR_REG_RTCCNTL_BASE + 0x20)
+#define RTC_CNTL_MIN_TIME_CK12M_OFF 0x000000FF
+#define RTC_CNTL_MIN_TIME_CK12M_OFF_S 24
+#define RTC_CNTL_SAR_TOUCH_START_WAIT 0x000001FF
+#define RTC_CNTL_SAR_TOUCH_START_WAIT_S 15
+
+#define RTC_TIMER3 (DR_REG_RTCCNTL_BASE + 0x24)
+#define RTC_CNTL_ROM_RAM_POWERUP_TIMER 0x0000007F
+#define RTC_CNTL_ROM_RAM_POWERUP_TIMER_S 25
+#define RTC_CNTL_ROM_RAM_WAIT_TIMER 0x000001FF
+#define RTC_CNTL_ROM_RAM_WAIT_TIMER_S 16
+#define RTC_CNTL_WIFI_POWERUP_TIMER 0x0000007F
+#define RTC_CNTL_WIFI_POWERUP_TIMER_S 9
+#define RTC_CNTL_WIFI_WAIT_TIMER 0x000001FF
+#define RTC_CNTL_WIFI_WAIT_TIMER_S 0
+
+#define RTC_TIMER4 (DR_REG_RTCCNTL_BASE + 0x28)
+#define RTC_CNTL_DG_WRAP_POWERUP_TIMER 0x0000007F
+#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_S 25
+#define RTC_CNTL_DG_WRAP_WAIT_TIMER 0x000001FF
+#define RTC_CNTL_DG_WRAP_WAIT_TIMER_S 16
+#define RTC_CNTL_RTC_POWERUP_TIMER 0x0000007F
+#define RTC_CNTL_RTC_POWERUP_TIMER_S 9
+#define RTC_CNTL_RTC_WAIT_TIMER 0x000001FF
+#define RTC_CNTL_RTC_WAIT_TIMER_S 0
+
+#define RTC_TIMER5 (DR_REG_RTCCNTL_BASE + 0x2c)
+#define RTC_CNTL_RTCMEM_POWERUP_TIMER 0x0000007F
+#define RTC_CNTL_RTCMEM_POWERUP_TIMER_S 25
+#define RTC_CNTL_RTCMEM_WAIT_TIMER 0x000001FF
+#define RTC_CNTL_RTCMEM_WAIT_TIMER_S 16
+#define RTC_CNTL_MIN_SLP_VAL 0x000000FF
+#define RTC_CNTL_MIN_SLP_VAL_S 8
+#define RTC_CNTL_SAR_SUBTIMER_PREDIV 0x000000FF
+#define RTC_CNTL_SAR_SUBTIMER_PREDIV_S 0
+
+#define RTC_ANA_CONF (DR_REG_RTCCNTL_BASE + 0x30)
+#define RTC_CNTL_PLL_I2C_PU (BIT(31))
+#define RTC_CNTL_PLL_I2C_PU_S 31
+#define RTC_CNTL_CKGEN_I2C_PU (BIT(30))
+#define RTC_CNTL_CKGEN_I2C_PU_S 30
+#define RTC_CNTL_RFRX_PBUS_PU (BIT(28))
+#define RTC_CNTL_RFRX_PBUS_PU_S 28
+#define RTC_CNTL_TXRF_I2C_PU (BIT(27))
+#define RTC_CNTL_TXRF_I2C_PU_S 27
+#define RTC_CNTL_PVTMON_PU (BIT(26))
+#define RTC_CNTL_PVTMON_PU_S 26
+#define RTC_CNTL_BBPLL_CAL_SLP_START (BIT(25))
+#define RTC_CNTL_BBPLL_CAL_SLP_START_S 25
+#define RTC_CNTL_PLLA_FORCE_PU (BIT(24))
+#define RTC_CNTL_PLLA_FORCE_PU_S 24
+#define RTC_CNTL_PLLA_FORCE_PD (BIT(23))
+#define RTC_CNTL_PLLA_FORCE_PD_S 23
+
+#define RTC_RESET_STATE (DR_REG_RTCCNTL_BASE + 0x34)
+#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL (BIT(13))
+#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL_S 13
+#define RTC_CNTL_APPCPU_STAT_VECTOR_SEL (BIT(12))
+#define RTC_CNTL_APPCPU_STAT_VECTOR_SEL_S 12
+#define RTC_CNTL_RESET_CAUSE_APPCPU 0x0000003F
+#define RTC_CNTL_RESET_CAUSE_APPCPU_S 6
+#define RTC_CNTL_RESET_CAUSE_PROCPU 0x0000003F
+#define RTC_CNTL_RESET_CAUSE_PROCPU_S 0
+
+#define RTC_WAKEUP_STATE (DR_REG_RTCCNTL_BASE + 0x38)
+#define RTC_CNTL_GPIO_WAKEUP_FILTER (BIT(22))
+#define RTC_CNTL_GPIO_WAKEUP_FILTER_S 22
+#define RTC_CNTL_RTC_WAKEUP_ENA 0x000007FF
+#define RTC_CNTL_RTC_WAKEUP_ENA_S 11
+#define RTC_CNTL_WAKEUP_CAUSE 0x000007FF
+#define RTC_CNTL_WAKEUP_CAUSE_S 0
+
+#define INT_ENA_RTC (DR_REG_RTCCNTL_BASE + 0x3c)
+#define RTC_CNTL_RTC_MAIN_TIMER_INT_ENA (BIT(8))
+#define RTC_CNTL_RTC_MAIN_TIMER_INT_ENA_S 8
+#define RTC_CNTL_RTC_BROWN_OUT_INT_ENA (BIT(7))
+#define RTC_CNTL_RTC_BROWN_OUT_INT_ENA_S 7
+#define RTC_CNTL_RTC_TOUCH_INT_ENA (BIT(6))
+#define RTC_CNTL_RTC_TOUCH_INT_ENA_S 6
+#define RTC_CNTL_RTC_SAR_INT_ENA (BIT(5))
+#define RTC_CNTL_RTC_SAR_INT_ENA_S 5
+#define RTC_CNTL_RTC_TIME_VALID_INT_ENA (BIT(4))
+#define RTC_CNTL_RTC_TIME_VALID_INT_ENA_S 4
+#define RTC_CNTL_RTC_WDT_INT_ENA (BIT(3))
+#define RTC_CNTL_RTC_WDT_INT_ENA_S 3
+#define RTC_CNTL_SDIO_IDLE_INT_ENA (BIT(2))
+#define RTC_CNTL_SDIO_IDLE_INT_ENA_S 2
+#define RTC_CNTL_SLP_REJECT_INT_ENA (BIT(1))
+#define RTC_CNTL_SLP_REJECT_INT_ENA_S 1
+#define RTC_CNTL_SLP_WAKEUP_INT_ENA (BIT(0))
+#define RTC_CNTL_SLP_WAKEUP_INT_ENA_S 0
+
+#define INT_RAW_RTC (DR_REG_RTCCNTL_BASE + 0x40)
+#define RTC_CNTL_RTC_MAIN_TIMER_INT_RAW (BIT(8))
+#define RTC_CNTL_RTC_MAIN_TIMER_INT_RAW_S 8
+#define RTC_CNTL_RTC_BROWN_OUT_INT_RAW (BIT(7))
+#define RTC_CNTL_RTC_BROWN_OUT_INT_RAW_S 7
+#define RTC_CNTL_RTC_TOUCH_INT_RAW (BIT(6))
+#define RTC_CNTL_RTC_TOUCH_INT_RAW_S 6
+#define RTC_CNTL_RTC_SAR_INT_RAW (BIT(5))
+#define RTC_CNTL_RTC_SAR_INT_RAW_S 5
+#define RTC_CNTL_RTC_TIME_VALID_INT_RAW (BIT(4))
+#define RTC_CNTL_RTC_TIME_VALID_INT_RAW_S 4
+#define RTC_CNTL_RTC_WDT_INT_RAW (BIT(3))
+#define RTC_CNTL_RTC_WDT_INT_RAW_S 3
+#define RTC_CNTL_SDIO_IDLE_INT_RAW (BIT(2))
+#define RTC_CNTL_SDIO_IDLE_INT_RAW_S 2
+#define RTC_CNTL_SLP_REJECT_INT_RAW (BIT(1))
+#define RTC_CNTL_SLP_REJECT_INT_RAW_S 1
+#define RTC_CNTL_SLP_WAKEUP_INT_RAW (BIT(0))
+#define RTC_CNTL_SLP_WAKEUP_INT_RAW_S 0
+
+#define INT_ST_RTC (DR_REG_RTCCNTL_BASE + 0x44)
+#define RTC_CNTL_RTC_MAIN_TIMER_INT_ST (BIT(8))
+#define RTC_CNTL_RTC_MAIN_TIMER_INT_ST_S 8
+#define RTC_CNTL_RTC_BROWN_OUT_INT_ST (BIT(7))
+#define RTC_CNTL_RTC_BROWN_OUT_INT_ST_S 7
+#define RTC_CNTL_RTC_TOUCH_INT_ST (BIT(6))
+#define RTC_CNTL_RTC_TOUCH_INT_ST_S 6
+#define RTC_CNTL_RTC_SAR_INT_ST (BIT(5))
+#define RTC_CNTL_RTC_SAR_INT_ST_S 5
+#define RTC_CNTL_RTC_TIME_VALID_INT_ST (BIT(4))
+#define RTC_CNTL_RTC_TIME_VALID_INT_ST_S 4
+#define RTC_CNTL_RTC_WDT_INT_ST (BIT(3))
+#define RTC_CNTL_RTC_WDT_INT_ST_S 3
+#define RTC_CNTL_SDIO_IDLE_INT_ST (BIT(2))
+#define RTC_CNTL_SDIO_IDLE_INT_ST_S 2
+#define RTC_CNTL_SLP_REJECT_INT_ST (BIT(1))
+#define RTC_CNTL_SLP_REJECT_INT_ST_S 1
+#define RTC_CNTL_SLP_WAKEUP_INT_ST (BIT(0))
+#define RTC_CNTL_SLP_WAKEUP_INT_ST_S 0
+
+#define INT_CLR_RTC (DR_REG_RTCCNTL_BASE + 0x48)
+#define RTC_CNTL_RTC_MAIN_TIMER_INT_CLR (BIT(8))
+#define RTC_CNTL_RTC_MAIN_TIMER_INT_CLR_S 8
+#define RTC_CNTL_RTC_BROWN_OUT_INT_CLR (BIT(7))
+#define RTC_CNTL_RTC_BROWN_OUT_INT_CLR_S 7
+#define RTC_CNTL_RTC_TOUCH_INT_CLR (BIT(6))
+#define RTC_CNTL_RTC_TOUCH_INT_CLR_S 6
+#define RTC_CNTL_RTC_SAR_INT_CLR (BIT(5))
+#define RTC_CNTL_RTC_SAR_INT_CLR_S 5
+#define RTC_CNTL_RTC_TIME_VALID_INT_CLR (BIT(4))
+#define RTC_CNTL_RTC_TIME_VALID_INT_CLR_S 4
+#define RTC_CNTL_RTC_WDT_INT_CLR (BIT(3))
+#define RTC_CNTL_RTC_WDT_INT_CLR_S 3
+#define RTC_CNTL_SDIO_IDLE_INT_CLR (BIT(2))
+#define RTC_CNTL_SDIO_IDLE_INT_CLR_S 2
+#define RTC_CNTL_SLP_REJECT_INT_CLR (BIT(1))
+#define RTC_CNTL_SLP_REJECT_INT_CLR_S 1
+#define RTC_CNTL_SLP_WAKEUP_INT_CLR (BIT(0))
+#define RTC_CNTL_SLP_WAKEUP_INT_CLR_S 0
+
+#define RTC_STORE0 (DR_REG_RTCCNTL_BASE + 0x4c)
+#define RTC_CNTL_RTC_SCRATCH0 0xFFFFFFFF
+#define RTC_CNTL_RTC_SCRATCH0_S 0
+
+#define RTC_STORE1 (DR_REG_RTCCNTL_BASE + 0x50)
+#define RTC_CNTL_RTC_SCRATCH1 0xFFFFFFFF
+#define RTC_CNTL_RTC_SCRATCH1_S 0
+
+#define RTC_STORE2 (DR_REG_RTCCNTL_BASE + 0x54)
+#define RTC_CNTL_RTC_SCRATCH2 0xFFFFFFFF
+#define RTC_CNTL_RTC_SCRATCH2_S 0
+
+#define RTC_STORE3 (DR_REG_RTCCNTL_BASE + 0x58)
+#define RTC_CNTL_RTC_SCRATCH3 0xFFFFFFFF
+#define RTC_CNTL_RTC_SCRATCH3_S 0
+
+#define RTC_EXT_XTL_CONF (DR_REG_RTCCNTL_BASE + 0x5c)
+#define RTC_CNTL_XTL_EXT_CTR_EN (BIT(31))
+#define RTC_CNTL_XTL_EXT_CTR_EN_S 31
+#define RTC_CNTL_XTL_EXT_CTR_LV (BIT(30))
+#define RTC_CNTL_XTL_EXT_CTR_LV_S 30
+
+#define RTC_EXT_WAKEUP_CONF (DR_REG_RTCCNTL_BASE + 0x60)
+#define RTC_CNTL_EXT_WAKEUP1_LV (BIT(31))
+#define RTC_CNTL_EXT_WAKEUP1_LV_S 31
+#define RTC_CNTL_EXT_WAKEUP0_LV (BIT(30))
+#define RTC_CNTL_EXT_WAKEUP0_LV_S 30
+
+#define RTC_SLP_REJECT_CONF (DR_REG_RTCCNTL_BASE + 0x64)
+#define RTC_CNTL_REJECT_CAUSE 0x0000000F
+#define RTC_CNTL_REJECT_CAUSE_S 28
+#define RTC_CNTL_DEEP_SLP_REJECT_EN (BIT(27))
+#define RTC_CNTL_DEEP_SLP_REJECT_EN_S 27
+#define RTC_CNTL_LIGHT_SLP_REJECT_EN (BIT(26))
+#define RTC_CNTL_LIGHT_SLP_REJECT_EN_S 26
+#define RTC_CNTL_SDIO_REJECT_EN (BIT(25))
+#define RTC_CNTL_SDIO_REJECT_EN_S 25
+#define RTC_CNTL_GPIO_REJECT_EN (BIT(24))
+#define RTC_CNTL_GPIO_REJECT_EN_S 24
+
+#define RTC_CPU_PERIOD_CONF (DR_REG_RTCCNTL_BASE + 0x68)
+#define RTC_CNTL_RTC_CPUPERIOD_SEL 0x00000003
+#define RTC_CNTL_RTC_CPUPERIOD_SEL_S 30
+#define RTC_CNTL_RTC_CPUSEL_CONF (BIT(29))
+#define RTC_CNTL_RTC_CPUSEL_CONF_S 29
+
+#define RTC_SDIO_ACT_CONF (DR_REG_RTCCNTL_BASE + 0x6c)
+#define RTC_CNTL_SDIO_ACT_DNUM 0x000003FF
+#define RTC_CNTL_SDIO_ACT_DNUM_S 22
+
+#define RTC_CLK_CONF (DR_REG_RTCCNTL_BASE + 0x70)
+#define RTC_CNTL_ANA_CLK_RTC_SEL 0x00000003
+#define RTC_CNTL_ANA_CLK_RTC_SEL_S 30
+#define RTC_CNTL_FAST_CLK_RTC_SEL (BIT(29))
+#define RTC_CNTL_FAST_CLK_RTC_SEL_S 29
+#define RTC_CNTL_SOC_CLK_SEL 0x00000003
+#define RTC_CNTL_SOC_CLK_SEL_S 27
+#define RTC_CNTL_CK12M_FORCE_PU (BIT(26))
+#define RTC_CNTL_CK12M_FORCE_PU_S 26
+#define RTC_CNTL_CK12M_FORCE_PD (BIT(25))
+#define RTC_CNTL_CK12M_FORCE_PD_S 25
+#define RTC_CNTL_CK12M_DFREQ 0x000000FF
+#define RTC_CNTL_CK12M_DFREQ_S 17
+#define RTC_CNTL_CK12M_FORCE_NOGATING (BIT(16))
+#define RTC_CNTL_CK12M_FORCE_NOGATING_S 16
+#define RTC_CNTL_XTAL_FORCE_NOGATING (BIT(15))
+#define RTC_CNTL_XTAL_FORCE_NOGATING_S 15
+#define RTC_CNTL_CK12M_DIV_SEL 0x00000007
+#define RTC_CNTL_CK12M_DIV_SEL_S 12
+#define RTC_CNTL_CK12M_DFREQ_FORCE (BIT(11))
+#define RTC_CNTL_CK12M_DFREQ_FORCE_S 11
+#define RTC_CNTL_DIG_CLK12M_EN (BIT(10))
+#define RTC_CNTL_DIG_CLK12M_EN_S 10
+#define RTC_CNTL_DIG_CLK12M_D256_EN (BIT(9))
+#define RTC_CNTL_DIG_CLK12M_D256_EN_S 9
+#define RTC_CNTL_DIG_XTAL32K_EN (BIT(8))
+#define RTC_CNTL_DIG_XTAL32K_EN_S 8
+#define RTC_CNTL_ENB_CK12M_DIV (BIT(7))
+#define RTC_CNTL_ENB_CK12M_DIV_S 7
+#define RTC_CNTL_ENB_CK12M (BIT(6))
+#define RTC_CNTL_ENB_CK12M_S 6
+#define RTC_CNTL_CK12M_DIV 0x00000003
+#define RTC_CNTL_CK12M_DIV_S 4
+
+#define RTC_SDIO_CONF (DR_REG_RTCCNTL_BASE + 0x74)
+#define RTC_CNTL_XPD_SDIO_REG (BIT(31))
+#define RTC_CNTL_XPD_SDIO_REG_S 31
+#define RTC_CNTL_DREFH_SDIO 0x00000003
+#define RTC_CNTL_DREFH_SDIO_S 29
+#define RTC_CNTL_DREFM_SDIO 0x00000003
+#define RTC_CNTL_DREFM_SDIO_S 27
+#define RTC_CNTL_DREFL_SDIO 0x00000003
+#define RTC_CNTL_DREFL_SDIO_S 25
+#define RTC_CNTL_REG1P8_READY (BIT(24))
+#define RTC_CNTL_REG1P8_READY_S 24
+#define RTC_CNTL_SDIO_TIEH (BIT(23))
+#define RTC_CNTL_SDIO_TIEH_S 23
+#define RTC_CNTL_SDIO_FORCE (BIT(22))
+#define RTC_CNTL_SDIO_FORCE_S 22
+#define RTC_CNTL_SDIO_REG_PD_EN (BIT(21))
+#define RTC_CNTL_SDIO_REG_PD_EN_S 21
+
+#define RTC_BIAS_CONF (DR_REG_RTCCNTL_BASE + 0x78)
+#define RTC_CNTL_RST_BIAS_I2C (BIT(31))
+#define RTC_CNTL_RST_BIAS_I2C_S 31
+#define RTC_CNTL_DEC_HEARTBEAT_WIDTH (BIT(30))
+#define RTC_CNTL_DEC_HEARTBEAT_WIDTH_S 30
+#define RTC_CNTL_INC_HEARTBEAT_PERIOD (BIT(29))
+#define RTC_CNTL_INC_HEARTBEAT_PERIOD_S 29
+#define RTC_CNTL_DEC_HEARTBEAT_PERIOD (BIT(28))
+#define RTC_CNTL_DEC_HEARTBEAT_PERIOD_S 28
+#define RTC_CNTL_INC_HEARTBEAT_REFRESH (BIT(27))
+#define RTC_CNTL_INC_HEARTBEAT_REFRESH_S 27
+#define RTC_CNTL_ENB_SCK_XTAL (BIT(26))
+#define RTC_CNTL_ENB_SCK_XTAL_S 26
+#define RTC_CNTL_DBG_ATTEN 0x00000003
+#define RTC_CNTL_DBG_ATTEN_S 24
+
+#define RTC_REG (DR_REG_RTCCNTL_BASE + 0x7c)
+#define RTC_CNTL_RTC_REG_FORCE_PU (BIT(31))
+#define RTC_CNTL_RTC_REG_FORCE_PU_S 31
+#define RTC_CNTL_RTC_REG_FORCE_PD (BIT(30))
+#define RTC_CNTL_RTC_REG_FORCE_PD_S 30
+#define RTC_CNTL_RTC_DBOOST_FORCE_PU (BIT(29))
+#define RTC_CNTL_RTC_DBOOST_FORCE_PU_S 29
+#define RTC_CNTL_RTC_DBOOST_FORCE_PD (BIT(28))
+#define RTC_CNTL_RTC_DBOOST_FORCE_PD_S 28
+#define RTC_CNTL_RTC_DBIAS_WAK 0x00000007
+#define RTC_CNTL_RTC_DBIAS_WAK_S 25
+#define RTC_CNTL_RTC_DBIAS_SLP 0x00000007
+#define RTC_CNTL_RTC_DBIAS_SLP_S 22
+#define RTC_CNTL_SCK_DCAP 0x000000FF
+#define RTC_CNTL_SCK_DCAP_S 14
+#define RTC_CNTL_DIG_REG_DBIAS_WAK 0x00000007
+#define RTC_CNTL_DIG_REG_DBIAS_WAK_S 11
+#define RTC_CNTL_DIG_REG_DBIAS_SLP 0x00000007
+#define RTC_CNTL_DIG_REG_DBIAS_SLP_S 8
+#define RTC_CNTL_SCK_DCAP_FORCE (BIT(7))
+#define RTC_CNTL_SCK_DCAP_FORCE_S 7
+
+#define RTC_PWC (DR_REG_RTCCNTL_BASE + 0x80)
+#define RTC_CNTL_RTC_PD_EN (BIT(20))
+#define RTC_CNTL_RTC_PD_EN_S 20
+#define RTC_CNTL_RTC_FORCE_PU (BIT(19))
+#define RTC_CNTL_RTC_FORCE_PU_S 19
+#define RTC_CNTL_RTC_FORCE_PD (BIT(18))
+#define RTC_CNTL_RTC_FORCE_PD_S 18
+#define RTC_CNTL_RTC_SLOWMEM_PD_EN (BIT(17))
+#define RTC_CNTL_RTC_SLOWMEM_PD_EN_S 17
+#define RTC_CNTL_RTC_SLOWMEM_FORCE_PU (BIT(16))
+#define RTC_CNTL_RTC_SLOWMEM_FORCE_PU_S 16
+#define RTC_CNTL_RTC_SLOWMEM_FORCE_PD (BIT(15))
+#define RTC_CNTL_RTC_SLOWMEM_FORCE_PD_S 15
+#define RTC_CNTL_RTC_FASTMEM_PD_EN (BIT(14))
+#define RTC_CNTL_RTC_FASTMEM_PD_EN_S 14
+#define RTC_CNTL_RTC_FASTMEM_FORCE_PU (BIT(13))
+#define RTC_CNTL_RTC_FASTMEM_FORCE_PU_S 13
+#define RTC_CNTL_RTC_FASTMEM_FORCE_PD (BIT(12))
+#define RTC_CNTL_RTC_FASTMEM_FORCE_PD_S 12
+#define RTC_CNTL_RTC_SLOWMEM_FORCE_LPU (BIT(11))
+#define RTC_CNTL_RTC_SLOWMEM_FORCE_LPU_S 11
+#define RTC_CNTL_RTC_SLOWMEM_FORCE_LPD (BIT(10))
+#define RTC_CNTL_RTC_SLOWMEM_FORCE_LPD_S 10
+#define RTC_CNTL_RTC_SLOWMEM_FOLW_CPU (BIT(9))
+#define RTC_CNTL_RTC_SLOWMEM_FOLW_CPU_S 9
+#define RTC_CNTL_RTC_FASTMEM_FORCE_LPU (BIT(8))
+#define RTC_CNTL_RTC_FASTMEM_FORCE_LPU_S 8
+#define RTC_CNTL_RTC_FASTMEM_FORCE_LPD (BIT(7))
+#define RTC_CNTL_RTC_FASTMEM_FORCE_LPD_S 7
+#define RTC_CNTL_RTC_FASTMEM_FOLW_CPU (BIT(6))
+#define RTC_CNTL_RTC_FASTMEM_FOLW_CPU_S 6
+#define RTC_CNTL_RTC_FORCE_NOISO (BIT(5))
+#define RTC_CNTL_RTC_FORCE_NOISO_S 5
+#define RTC_CNTL_RTC_FORCE_ISO (BIT(4))
+#define RTC_CNTL_RTC_FORCE_ISO_S 4
+#define RTC_CNTL_RTC_SLOWMEM_FORCE_ISO (BIT(3))
+#define RTC_CNTL_RTC_SLOWMEM_FORCE_ISO_S 3
+#define RTC_CNTL_RTC_SLOWMEM_FORCE_NOISO (BIT(2))
+#define RTC_CNTL_RTC_SLOWMEM_FORCE_NOISO_S 2
+#define RTC_CNTL_RTC_FASTMEM_FORCE_ISO (BIT(1))
+#define RTC_CNTL_RTC_FASTMEM_FORCE_ISO_S 1
+#define RTC_CNTL_RTC_FASTMEM_FORCE_NOISO (BIT(0))
+#define RTC_CNTL_RTC_FASTMEM_FORCE_NOISO_S 0
+
+#define DIG_PWC (DR_REG_RTCCNTL_BASE + 0x84)
+#define RTC_CNTL_DG_WRAP_PD_EN (BIT(31))
+#define RTC_CNTL_DG_WRAP_PD_EN_S 31
+#define RTC_CNTL_WIFI_PD_EN (BIT(30))
+#define RTC_CNTL_WIFI_PD_EN_S 30
+#define RTC_CNTL_INTER_RAM4_PD_EN (BIT(29))
+#define RTC_CNTL_INTER_RAM4_PD_EN_S 29
+#define RTC_CNTL_INTER_RAM3_PD_EN (BIT(28))
+#define RTC_CNTL_INTER_RAM3_PD_EN_S 28
+#define RTC_CNTL_INTER_RAM2_PD_EN (BIT(27))
+#define RTC_CNTL_INTER_RAM2_PD_EN_S 27
+#define RTC_CNTL_INTER_RAM1_PD_EN (BIT(26))
+#define RTC_CNTL_INTER_RAM1_PD_EN_S 26
+#define RTC_CNTL_INTER_RAM0_PD_EN (BIT(25))
+#define RTC_CNTL_INTER_RAM0_PD_EN_S 25
+#define RTC_CNTL_ROM0_PD_EN (BIT(24))
+#define RTC_CNTL_ROM0_PD_EN_S 24
+#define RTC_CNTL_DG_WRAP_FORCE_PU (BIT(20))
+#define RTC_CNTL_DG_WRAP_FORCE_PU_S 20
+#define RTC_CNTL_DG_WRAP_FORCE_PD (BIT(19))
+#define RTC_CNTL_DG_WRAP_FORCE_PD_S 19
+#define RTC_CNTL_WIFI_FORCE_PU (BIT(18))
+#define RTC_CNTL_WIFI_FORCE_PU_S 18
+#define RTC_CNTL_WIFI_FORCE_PD (BIT(17))
+#define RTC_CNTL_WIFI_FORCE_PD_S 17
+#define RTC_CNTL_INTER_RAM4_FORCE_PU (BIT(16))
+#define RTC_CNTL_INTER_RAM4_FORCE_PU_S 16
+#define RTC_CNTL_INTER_RAM4_FORCE_PD (BIT(15))
+#define RTC_CNTL_INTER_RAM4_FORCE_PD_S 15
+#define RTC_CNTL_INTER_RAM3_FORCE_PU (BIT(14))
+#define RTC_CNTL_INTER_RAM3_FORCE_PU_S 14
+#define RTC_CNTL_INTER_RAM3_FORCE_PD (BIT(13))
+#define RTC_CNTL_INTER_RAM3_FORCE_PD_S 13
+#define RTC_CNTL_INTER_RAM2_FORCE_PU (BIT(12))
+#define RTC_CNTL_INTER_RAM2_FORCE_PU_S 12
+#define RTC_CNTL_INTER_RAM2_FORCE_PD (BIT(11))
+#define RTC_CNTL_INTER_RAM2_FORCE_PD_S 11
+#define RTC_CNTL_INTER_RAM1_FORCE_PU (BIT(10))
+#define RTC_CNTL_INTER_RAM1_FORCE_PU_S 10
+#define RTC_CNTL_INTER_RAM1_FORCE_PD (BIT(9))
+#define RTC_CNTL_INTER_RAM1_FORCE_PD_S 9
+#define RTC_CNTL_INTER_RAM0_FORCE_PU (BIT(8))
+#define RTC_CNTL_INTER_RAM0_FORCE_PU_S 8
+#define RTC_CNTL_INTER_RAM0_FORCE_PD (BIT(7))
+#define RTC_CNTL_INTER_RAM0_FORCE_PD_S 7
+#define RTC_CNTL_ROM0_FORCE_PU (BIT(6))
+#define RTC_CNTL_ROM0_FORCE_PU_S 6
+#define RTC_CNTL_ROM0_FORCE_PD (BIT(5))
+#define RTC_CNTL_ROM0_FORCE_PD_S 5
+#define RTC_CNTL_LSLP_MEM_FORCE_PU (BIT(4))
+#define RTC_CNTL_LSLP_MEM_FORCE_PU_S 4
+#define RTC_CNTL_LSLP_MEM_FORCE_PD (BIT(3))
+#define RTC_CNTL_LSLP_MEM_FORCE_PD_S 3
+
+#define DIG_ISO (DR_REG_RTCCNTL_BASE + 0x88)
+#define RTC_CNTL_DG_WRAP_FORCE_NOISO (BIT(31))
+#define RTC_CNTL_DG_WRAP_FORCE_NOISO_S 31
+#define RTC_CNTL_DG_WRAP_FORCE_ISO (BIT(30))
+#define RTC_CNTL_DG_WRAP_FORCE_ISO_S 30
+#define RTC_CNTL_WIFI_FORCE_NOISO (BIT(29))
+#define RTC_CNTL_WIFI_FORCE_NOISO_S 29
+#define RTC_CNTL_WIFI_FORCE_ISO (BIT(28))
+#define RTC_CNTL_WIFI_FORCE_ISO_S 28
+#define RTC_CNTL_INTER_RAM4_FORCE_NOISO (BIT(27))
+#define RTC_CNTL_INTER_RAM4_FORCE_NOISO_S 27
+#define RTC_CNTL_INTER_RAM4_FORCE_ISO (BIT(26))
+#define RTC_CNTL_INTER_RAM4_FORCE_ISO_S 26
+#define RTC_CNTL_INTER_RAM3_FORCE_NOISO (BIT(25))
+#define RTC_CNTL_INTER_RAM3_FORCE_NOISO_S 25
+#define RTC_CNTL_INTER_RAM3_FORCE_ISO (BIT(24))
+#define RTC_CNTL_INTER_RAM3_FORCE_ISO_S 24
+#define RTC_CNTL_INTER_RAM2_FORCE_NOISO (BIT(23))
+#define RTC_CNTL_INTER_RAM2_FORCE_NOISO_S 23
+#define RTC_CNTL_INTER_RAM2_FORCE_ISO (BIT(22))
+#define RTC_CNTL_INTER_RAM2_FORCE_ISO_S 22
+#define RTC_CNTL_INTER_RAM1_FORCE_NOISO (BIT(21))
+#define RTC_CNTL_INTER_RAM1_FORCE_NOISO_S 21
+#define RTC_CNTL_INTER_RAM1_FORCE_ISO (BIT(20))
+#define RTC_CNTL_INTER_RAM1_FORCE_ISO_S 20
+#define RTC_CNTL_INTER_RAM0_FORCE_NOISO (BIT(19))
+#define RTC_CNTL_INTER_RAM0_FORCE_NOISO_S 19
+#define RTC_CNTL_INTER_RAM0_FORCE_ISO (BIT(18))
+#define RTC_CNTL_INTER_RAM0_FORCE_ISO_S 18
+#define RTC_CNTL_ROM0_FORCE_NOISO (BIT(17))
+#define RTC_CNTL_ROM0_FORCE_NOISO_S 17
+#define RTC_CNTL_ROM0_FORCE_ISO (BIT(16))
+#define RTC_CNTL_ROM0_FORCE_ISO_S 16
+#define RTC_CNTL_DG_PAD_FORCE_HOLD (BIT(15))
+#define RTC_CNTL_DG_PAD_FORCE_HOLD_S 15
+#define RTC_CNTL_DG_PAD_FORCE_UNHOLD (BIT(14))
+#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_S 14
+#define RTC_CNTL_DG_PAD_FORCE_ISO (BIT(13))
+#define RTC_CNTL_DG_PAD_FORCE_ISO_S 13
+#define RTC_CNTL_DG_PAD_FORCE_NOISO (BIT(12))
+#define RTC_CNTL_DG_PAD_FORCE_NOISO_S 12
+#define RTC_CNTL_DG_PAD_AUTOHOLD_EN (BIT(11))
+#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_S 11
+#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD (BIT(10))
+#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_S 10
+#define RTC_CNTL_DG_PAD_AUTOHOLD (BIT(9))
+#define RTC_CNTL_DG_PAD_AUTOHOLD_S 9
+#define RTC_CNTL_DIG_ISO_FORCE_ON (BIT(8))
+#define RTC_CNTL_DIG_ISO_FORCE_ON_S 8
+#define RTC_CNTL_DIG_ISO_FORCE_OFF (BIT(7))
+#define RTC_CNTL_DIG_ISO_FORCE_OFF_S 7
+
+#define RTC_WDTCONFIG0 (DR_REG_RTCCNTL_BASE + 0x8c)
+#define RTC_CNTL_WDT_EN (BIT(31))
+#define RTC_CNTL_WDT_EN_S 31
+#define RTC_CNTL_WDT_STG0 0x00000007
+#define RTC_CNTL_WDT_STG0_S 28
+#define RTC_CNTL_WDT_STG1 0x00000007
+#define RTC_CNTL_WDT_STG1_S 25
+#define RTC_CNTL_WDT_STG2 0x00000007
+#define RTC_CNTL_WDT_STG2_S 22
+#define RTC_CNTL_WDT_STG3 0x00000007
+#define RTC_CNTL_WDT_STG3_S 19
+#define RTC_CNTL_WDT_EDGE_INT_EN (BIT(18))
+#define RTC_CNTL_WDT_EDGE_INT_EN_S 18
+#define RTC_CNTL_WDT_LEVEL_INT_EN (BIT(17))
+#define RTC_CNTL_WDT_LEVEL_INT_EN_S 17
+#define RTC_CNTL_WDT_CPU_RESET_LENGTH 0x00000007
+#define RTC_CNTL_WDT_CPU_RESET_LENGTH_S 14
+#define RTC_CNTL_WDT_SYS_RESET_LENGTH 0x00000007
+#define RTC_CNTL_WDT_SYS_RESET_LENGTH_S 11
+#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN (BIT(10))
+#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_S 10
+#define RTC_CNTL_WDT_PROCPU_RESET_EN (BIT(9))
+#define RTC_CNTL_WDT_PROCPU_RESET_EN_S 9
+#define RTC_CNTL_WDT_APPCPU_RESET_EN (BIT(8))
+#define RTC_CNTL_WDT_APPCPU_RESET_EN_S 8
+#define RTC_CNTL_WDT_PAUSE_IN_SLP (BIT(7))
+#define RTC_CNTL_WDT_PAUSE_IN_SLP_S 7
+
+#define RTC_WDTCONFIG1 (DR_REG_RTCCNTL_BASE + 0x90)
+#define RTC_CNTL_WDT_STG0_HOLD 0xFFFFFFFF
+#define RTC_CNTL_WDT_STG0_HOLD_S 0
+
+#define RTC_WDTCONFIG2 (DR_REG_RTCCNTL_BASE + 0x94)
+#define RTC_CNTL_WDT_STG1_HOLD 0xFFFFFFFF
+#define RTC_CNTL_WDT_STG1_HOLD_S 0
+
+#define RTC_WDTCONFIG3 (DR_REG_RTCCNTL_BASE + 0x98)
+#define RTC_CNTL_WDT_STG2_HOLD 0xFFFFFFFF
+#define RTC_CNTL_WDT_STG2_HOLD_S 0
+
+#define RTC_WDTCONFIG4 (DR_REG_RTCCNTL_BASE + 0x9c)
+#define RTC_CNTL_WDT_STG3_HOLD 0xFFFFFFFF
+#define RTC_CNTL_WDT_STG3_HOLD_S 0
+
+#define RTC_WDTFEED (DR_REG_RTCCNTL_BASE + 0xa0)
+#define RTC_CNTL_RTC_WDT_FEED (BIT(31))
+#define RTC_CNTL_RTC_WDT_FEED_S 31
+
+#define RTC_WDTWPROTECT (DR_REG_RTCCNTL_BASE + 0xa4)
+#define RTC_CNTL_WDT_WKEY 0xFFFFFFFF
+#define RTC_CNTL_WDT_WKEY_S 0
+
+#define RTC_TEST_MUX (DR_REG_RTCCNTL_BASE + 0xa8)
+#define RTC_CNTL_DTEST_RTC 0x00000003
+#define RTC_CNTL_DTEST_RTC_S 30
+#define RTC_CNTL_ENT_RTC (BIT(29))
+#define RTC_CNTL_ENT_RTC_S 29
+
+#define RTC_SW_CPU_STALL (DR_REG_RTCCNTL_BASE + 0xac)
+#define RTC_CNTL_SW_STALL_PROCPU_C1 0x0000003F
+#define RTC_CNTL_SW_STALL_PROCPU_C1_S 26
+#define RTC_CNTL_SW_STALL_APPCPU_C1 0x0000003F
+#define RTC_CNTL_SW_STALL_APPCPU_C1_S 20
+
+#define RTC_STORE4 (DR_REG_RTCCNTL_BASE + 0xb0)
+#define RTC_CNTL_RTC_SCRATCH4 0xFFFFFFFF
+#define RTC_CNTL_RTC_SCRATCH4_S 0
+
+#define RTC_STORE5 (DR_REG_RTCCNTL_BASE + 0xb4)
+#define RTC_CNTL_RTC_SCRATCH5 0xFFFFFFFF
+#define RTC_CNTL_RTC_SCRATCH5_S 0
+
+#define RTC_STORE6 (DR_REG_RTCCNTL_BASE + 0xb8)
+#define RTC_CNTL_RTC_SCRATCH6 0xFFFFFFFF
+#define RTC_CNTL_RTC_SCRATCH6_S 0
+
+#define RTC_STORE7 (DR_REG_RTCCNTL_BASE + 0xbc)
+#define RTC_CNTL_RTC_SCRATCH7 0xFFFFFFFF
+#define RTC_CNTL_RTC_SCRATCH7_S 0
+
+#define RTC_DIAG0 (DR_REG_RTCCNTL_BASE + 0xc0)
+#define RTC_CNTL_RTC_LOW_POWER_DIAG0 0xFFFFFFFF
+#define RTC_CNTL_RTC_LOW_POWER_DIAG0_S 0
+
+#define RTC_DIAG1 (DR_REG_RTCCNTL_BASE + 0xc4)
+#define RTC_CNTL_RTC_LOW_POWER_DIAG1 0xFFFFFFFF
+#define RTC_CNTL_RTC_LOW_POWER_DIAG1_S 0
+
+#define RTC_HOLD_FORCE (DR_REG_RTCCNTL_BASE + 0xc8)
+#define RTC_CNTL_X32N_HOLD_FORCE (BIT(17))
+#define RTC_CNTL_X32N_HOLD_FORCE_S 17
+#define RTC_CNTL_X32P_HOLD_FORCE (BIT(16))
+#define RTC_CNTL_X32P_HOLD_FORCE_S 16
+#define RTC_CNTL_TOUCH_PAD7_HOLD_FORCE (BIT(15))
+#define RTC_CNTL_TOUCH_PAD7_HOLD_FORCE_S 15
+#define RTC_CNTL_TOUCH_PAD6_HOLD_FORCE (BIT(14))
+#define RTC_CNTL_TOUCH_PAD6_HOLD_FORCE_S 14
+#define RTC_CNTL_TOUCH_PAD5_HOLD_FORCE (BIT(13))
+#define RTC_CNTL_TOUCH_PAD5_HOLD_FORCE_S 13
+#define RTC_CNTL_TOUCH_PAD4_HOLD_FORCE (BIT(12))
+#define RTC_CNTL_TOUCH_PAD4_HOLD_FORCE_S 12
+#define RTC_CNTL_TOUCH_PAD3_HOLD_FORCE (BIT(11))
+#define RTC_CNTL_TOUCH_PAD3_HOLD_FORCE_S 11
+#define RTC_CNTL_TOUCH_PAD2_HOLD_FORCE (BIT(10))
+#define RTC_CNTL_TOUCH_PAD2_HOLD_FORCE_S 10
+#define RTC_CNTL_TOUCH_PAD1_HOLD_FORCE (BIT(9))
+#define RTC_CNTL_TOUCH_PAD1_HOLD_FORCE_S 9
+#define RTC_CNTL_TOUCH_PAD0_HOLD_FORCE (BIT(8))
+#define RTC_CNTL_TOUCH_PAD0_HOLD_FORCE_S 8
+#define RTC_CNTL_SENSE4_HOLD_FORCE (BIT(7))
+#define RTC_CNTL_SENSE4_HOLD_FORCE_S 7
+#define RTC_CNTL_SENSE3_HOLD_FORCE (BIT(6))
+#define RTC_CNTL_SENSE3_HOLD_FORCE_S 6
+#define RTC_CNTL_SENSE2_HOLD_FORCE (BIT(5))
+#define RTC_CNTL_SENSE2_HOLD_FORCE_S 5
+#define RTC_CNTL_SENSE1_HOLD_FORCE (BIT(4))
+#define RTC_CNTL_SENSE1_HOLD_FORCE_S 4
+#define RTC_CNTL_PDAC2_HOLD_FORCE (BIT(3))
+#define RTC_CNTL_PDAC2_HOLD_FORCE_S 3
+#define RTC_CNTL_PDAC1_HOLD_FORCE (BIT(2))
+#define RTC_CNTL_PDAC1_HOLD_FORCE_S 2
+#define RTC_CNTL_ADC2_HOLD_FORCE (BIT(1))
+#define RTC_CNTL_ADC2_HOLD_FORCE_S 1
+#define RTC_CNTL_ADC1_HOLD_FORCE (BIT(0))
+#define RTC_CNTL_ADC1_HOLD_FORCE_S 0
+
+#define RTC_EXT_WAKEUP1 (DR_REG_RTCCNTL_BASE + 0xcc)
+#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR (BIT(18))
+#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_S 18
+#define RTC_CNTL_EXT_WAKEUP1_SEL 0x0003FFFF
+#define RTC_CNTL_EXT_WAKEUP1_SEL_S 0
+
+#define RTC_EXT_WAKEUP1_STATUS (DR_REG_RTCCNTL_BASE + 0xd0)
+#define RTC_CNTL_EXT_WAKEUP1_STATUS 0x0003FFFF
+#define RTC_CNTL_EXT_WAKEUP1_STATUS_S 0
+
+#define RTC_BROWN_OUT (DR_REG_RTCCNTL_BASE + 0xd4)
+#define RTC_CNTL_RTC_BROWN_OUT_DET (BIT(31))
+#define RTC_CNTL_RTC_BROWN_OUT_DET_S 31
+#define RTC_CNTL_BROWN_OUT_ENA (BIT(30))
+#define RTC_CNTL_BROWN_OUT_ENA_S 30
+#define RTC_CNTL_DBROWN_OUT_THRES 0x00000007
+#define RTC_CNTL_DBROWN_OUT_THRES_S 27
+#define RTC_CNTL_BROWN_OUT_RST_ENA (BIT(26))
+#define RTC_CNTL_BROWN_OUT_RST_ENA_S 26
+#define RTC_CNTL_BROWN_OUT_RST_WAIT 0x000003FF
+#define RTC_CNTL_BROWN_OUT_RST_WAIT_S 16
+#define RTC_CNTL_BROWN_OUT_PD_RF_ENA (BIT(15))
+#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_S 15
+#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA (BIT(14))
+#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_S 14
+
+#define RTC_MEM_CONF            (DR_REG_RTCCNTL_BASE + 0x40 * 4)
+#define RTC_MEM_CRC_FINISH      (BIT(31))
+#define RTC_MEM_CRC_FINISH_S    (31)
+#define RTC_MEM_CRC_LEN         (0x7ff)
+#define RTC_MEM_CRC_LEN_S       (20)
+#define RTC_MEM_CRC_ADDR        (0x7ff)
+#define RTC_MEM_CRC_ADDR_S      (9)
+#define RTC_MEM_CRC_START       (BIT(8))
+#define RTC_MEM_CRC_START_S     (8)
+#define RTC_MEM_PID_CONF        (0xff)
+#define RTC_MEM_PID_CONF_S      (0)
+
+#define RTC_MEM_CRC_RES         (DR_REG_RTCCNTL_BASE + 0x41 * 4)
+
+
+#define RTC_CNTL_DATE (DR_REG_RTCCNTL_BASE + 0x13c)
+#define RTC_CNTL_RTC_CNTL_DATE 0x0FFFFFFF
+#define RTC_CNTL_RTC_CNTL_DATE_S 0
+#define RTC_CNTL_RTC_CNTL_DATE_VERSION 0x1604280
+
+#endif /* _SOC_RTC_CNTL_REG_H_ */

components/esp32/include/soc/rtc_io_reg.h

@@ -0,0 +1,723 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_RTC_IO_REG_H_
+#define _SOC_RTC_IO_REG_H_
+
+#include "soc.h"
+
+#define RTC_GPIO_OUT (DR_REG_RTCIO_BASE + 0x0)
+#define RTC_IO_RTC_GPIO_OUT_DATA 0x0003FFFF
+#define RTC_IO_RTC_GPIO_OUT_DATA_S 14
+
+#define RTC_GPIO_OUT_W1TS (DR_REG_RTCIO_BASE + 0x4)
+#define RTC_IO_RTC_GPIO_OUT_DATA_W1TS 0x0003FFFF
+#define RTC_IO_RTC_GPIO_OUT_DATA_W1TS_S 14
+
+#define RTC_GPIO_OUT_W1TC (DR_REG_RTCIO_BASE + 0x8)
+#define RTC_IO_RTC_GPIO_OUT_DATA_W1TC 0x0003FFFF
+#define RTC_IO_RTC_GPIO_OUT_DATA_W1TC_S 14
+
+#define RTC_GPIO_ENABLE (DR_REG_RTCIO_BASE + 0xc)
+#define RTC_IO_RTC_GPIO_ENABLE 0x0003FFFF
+#define RTC_IO_RTC_GPIO_ENABLE_S 14
+
+#define RTC_GPIO_ENABLE_W1TS (DR_REG_RTCIO_BASE + 0x10)
+#define RTC_IO_RTC_GPIO_ENABLE_W1TS 0x0003FFFF
+#define RTC_IO_RTC_GPIO_ENABLE_W1TS_S 14
+
+#define RTC_GPIO_ENABLE_W1TC (DR_REG_RTCIO_BASE + 0x14)
+#define RTC_IO_RTC_GPIO_ENABLE_W1TC 0x0003FFFF
+#define RTC_IO_RTC_GPIO_ENABLE_W1TC_S 14
+
+#define RTC_GPIO_STATUS (DR_REG_RTCIO_BASE + 0x18)
+#define RTC_IO_RTC_GPIO_STATUS_INT 0x0003FFFF
+#define RTC_IO_RTC_GPIO_STATUS_INT_S 14
+
+#define RTC_GPIO_STATUS_W1TS (DR_REG_RTCIO_BASE + 0x1c)
+#define RTC_IO_RTC_GPIO_STATUS_INT_W1TS 0x0003FFFF
+#define RTC_IO_RTC_GPIO_STATUS_INT_W1TS_S 14
+
+#define RTC_GPIO_STATUS_W1TC (DR_REG_RTCIO_BASE + 0x20)
+#define RTC_IO_RTC_GPIO_STATUS_INT_W1TC 0x0003FFFF
+#define RTC_IO_RTC_GPIO_STATUS_INT_W1TC_S 14
+
+#define RTC_GPIO_IN (DR_REG_RTCIO_BASE + 0x24)
+#define RTC_IO_RTC_GPIO_IN_NEXT 0x0003FFFF
+#define RTC_IO_RTC_GPIO_IN_NEXT_S 14
+
+#define RTC_GPIO_PIN0 (DR_REG_RTCIO_BASE + 0x28)
+#define RTC_IO_RTC_GPIO_PIN0_WAKEUP_ENABLE (BIT(10))
+#define RTC_IO_RTC_GPIO_PIN0_WAKEUP_ENABLE_S 10
+#define RTC_IO_RTC_GPIO_PIN0_INT_TYPE 0x00000007
+#define RTC_IO_RTC_GPIO_PIN0_INT_TYPE_S 7
+#define RTC_IO_RTC_GPIO_PIN0_PAD_DRIVER (BIT(2))
+#define RTC_IO_RTC_GPIO_PIN0_PAD_DRIVER_S 2
+
+#define RTC_GPIO_PIN1 (DR_REG_RTCIO_BASE + 0x2c)
+#define RTC_IO_RTC_GPIO_PIN1_WAKEUP_ENABLE (BIT(10))
+#define RTC_IO_RTC_GPIO_PIN1_WAKEUP_ENABLE_S 10
+#define RTC_IO_RTC_GPIO_PIN1_INT_TYPE 0x00000007
+#define RTC_IO_RTC_GPIO_PIN1_INT_TYPE_S 7
+#define RTC_IO_RTC_GPIO_PIN1_PAD_DRIVER (BIT(2))
+#define RTC_IO_RTC_GPIO_PIN1_PAD_DRIVER_S 2
+
+#define RTC_GPIO_PIN2 (DR_REG_RTCIO_BASE + 0x30)
+#define RTC_IO_RTC_GPIO_PIN2_WAKEUP_ENABLE (BIT(10))
+#define RTC_IO_RTC_GPIO_PIN2_WAKEUP_ENABLE_S 10
+#define RTC_IO_RTC_GPIO_PIN2_INT_TYPE 0x00000007
+#define RTC_IO_RTC_GPIO_PIN2_INT_TYPE_S 7
+#define RTC_IO_RTC_GPIO_PIN2_PAD_DRIVER (BIT(2))
+#define RTC_IO_RTC_GPIO_PIN2_PAD_DRIVER_S 2
+
+#define RTC_GPIO_PIN3 (DR_REG_RTCIO_BASE + 0x34)
+#define RTC_IO_RTC_GPIO_PIN3_WAKEUP_ENABLE (BIT(10))
+#define RTC_IO_RTC_GPIO_PIN3_WAKEUP_ENABLE_S 10
+#define RTC_IO_RTC_GPIO_PIN3_INT_TYPE 0x00000007
+#define RTC_IO_RTC_GPIO_PIN3_INT_TYPE_S 7
+#define RTC_IO_RTC_GPIO_PIN3_PAD_DRIVER (BIT(2))
+#define RTC_IO_RTC_GPIO_PIN3_PAD_DRIVER_S 2
+
+#define RTC_GPIO_PIN4 (DR_REG_RTCIO_BASE + 0x38)
+#define RTC_IO_RTC_GPIO_PIN4_WAKEUP_ENABLE (BIT(10))
+#define RTC_IO_RTC_GPIO_PIN4_WAKEUP_ENABLE_S 10
+#define RTC_IO_RTC_GPIO_PIN4_INT_TYPE 0x00000007
+#define RTC_IO_RTC_GPIO_PIN4_INT_TYPE_S 7
+#define RTC_IO_RTC_GPIO_PIN4_PAD_DRIVER (BIT(2))
+#define RTC_IO_RTC_GPIO_PIN4_PAD_DRIVER_S 2
+
+#define RTC_GPIO_PIN5 (DR_REG_RTCIO_BASE + 0x3c)
+#define RTC_IO_RTC_GPIO_PIN5_WAKEUP_ENABLE (BIT(10))
+#define RTC_IO_RTC_GPIO_PIN5_WAKEUP_ENABLE_S 10
+#define RTC_IO_RTC_GPIO_PIN5_INT_TYPE 0x00000007
+#define RTC_IO_RTC_GPIO_PIN5_INT_TYPE_S 7
+#define RTC_IO_RTC_GPIO_PIN5_PAD_DRIVER (BIT(2))
+#define RTC_IO_RTC_GPIO_PIN5_PAD_DRIVER_S 2
+
+#define RTC_GPIO_PIN6 (DR_REG_RTCIO_BASE + 0x40)
+#define RTC_IO_RTC_GPIO_PIN6_WAKEUP_ENABLE (BIT(10))
+#define RTC_IO_RTC_GPIO_PIN6_WAKEUP_ENABLE_S 10
+#define RTC_IO_RTC_GPIO_PIN6_INT_TYPE 0x00000007
+#define RTC_IO_RTC_GPIO_PIN6_INT_TYPE_S 7
+#define RTC_IO_RTC_GPIO_PIN6_PAD_DRIVER (BIT(2))
+#define RTC_IO_RTC_GPIO_PIN6_PAD_DRIVER_S 2
+
+#define RTC_GPIO_PIN7 (DR_REG_RTCIO_BASE + 0x44)
+#define RTC_IO_RTC_GPIO_PIN7_WAKEUP_ENABLE (BIT(10))
+#define RTC_IO_RTC_GPIO_PIN7_WAKEUP_ENABLE_S 10
+#define RTC_IO_RTC_GPIO_PIN7_INT_TYPE 0x00000007
+#define RTC_IO_RTC_GPIO_PIN7_INT_TYPE_S 7
+#define RTC_IO_RTC_GPIO_PIN7_PAD_DRIVER (BIT(2))
+#define RTC_IO_RTC_GPIO_PIN7_PAD_DRIVER_S 2
+
+#define RTC_GPIO_PIN8 (DR_REG_RTCIO_BASE + 0x48)
+#define RTC_IO_RTC_GPIO_PIN8_WAKEUP_ENABLE (BIT(10))
+#define RTC_IO_RTC_GPIO_PIN8_WAKEUP_ENABLE_S 10
+#define RTC_IO_RTC_GPIO_PIN8_INT_TYPE 0x00000007
+#define RTC_IO_RTC_GPIO_PIN8_INT_TYPE_S 7
+#define RTC_IO_RTC_GPIO_PIN8_PAD_DRIVER (BIT(2))
+#define RTC_IO_RTC_GPIO_PIN8_PAD_DRIVER_S 2
+
+#define RTC_GPIO_PIN9 (DR_REG_RTCIO_BASE + 0x4c)
+#define RTC_IO_RTC_GPIO_PIN9_WAKEUP_ENABLE (BIT(10))
+#define RTC_IO_RTC_GPIO_PIN9_WAKEUP_ENABLE_S 10
+#define RTC_IO_RTC_GPIO_PIN9_INT_TYPE 0x00000007
+#define RTC_IO_RTC_GPIO_PIN9_INT_TYPE_S 7
+#define RTC_IO_RTC_GPIO_PIN9_PAD_DRIVER (BIT(2))
+#define RTC_IO_RTC_GPIO_PIN9_PAD_DRIVER_S 2
+
+#define RTC_GPIO_PIN10 (DR_REG_RTCIO_BASE + 0x50)
+#define RTC_IO_RTC_GPIO_PIN10_WAKEUP_ENABLE (BIT(10))
+#define RTC_IO_RTC_GPIO_PIN10_WAKEUP_ENABLE_S 10
+#define RTC_IO_RTC_GPIO_PIN10_INT_TYPE 0x00000007
+#define RTC_IO_RTC_GPIO_PIN10_INT_TYPE_S 7
+#define RTC_IO_RTC_GPIO_PIN10_PAD_DRIVER (BIT(2))
+#define RTC_IO_RTC_GPIO_PIN10_PAD_DRIVER_S 2
+
+#define RTC_GPIO_PIN11 (DR_REG_RTCIO_BASE + 0x54)
+#define RTC_IO_RTC_GPIO_PIN11_WAKEUP_ENABLE (BIT(10))
+#define RTC_IO_RTC_GPIO_PIN11_WAKEUP_ENABLE_S 10
+#define RTC_IO_RTC_GPIO_PIN11_INT_TYPE 0x00000007
+#define RTC_IO_RTC_GPIO_PIN11_INT_TYPE_S 7
+#define RTC_IO_RTC_GPIO_PIN11_PAD_DRIVER (BIT(2))
+#define RTC_IO_RTC_GPIO_PIN11_PAD_DRIVER_S 2
+
+#define RTC_GPIO_PIN12 (DR_REG_RTCIO_BASE + 0x58)
+#define RTC_IO_RTC_GPIO_PIN12_WAKEUP_ENABLE (BIT(10))
+#define RTC_IO_RTC_GPIO_PIN12_WAKEUP_ENABLE_S 10
+#define RTC_IO_RTC_GPIO_PIN12_INT_TYPE 0x00000007
+#define RTC_IO_RTC_GPIO_PIN12_INT_TYPE_S 7
+#define RTC_IO_RTC_GPIO_PIN12_PAD_DRIVER (BIT(2))
+#define RTC_IO_RTC_GPIO_PIN12_PAD_DRIVER_S 2
+
+#define RTC_GPIO_PIN13 (DR_REG_RTCIO_BASE + 0x5c)
+#define RTC_IO_RTC_GPIO_PIN13_WAKEUP_ENABLE (BIT(10))
+#define RTC_IO_RTC_GPIO_PIN13_WAKEUP_ENABLE_S 10
+#define RTC_IO_RTC_GPIO_PIN13_INT_TYPE 0x00000007
+#define RTC_IO_RTC_GPIO_PIN13_INT_TYPE_S 7
+#define RTC_IO_RTC_GPIO_PIN13_PAD_DRIVER (BIT(2))
+#define RTC_IO_RTC_GPIO_PIN13_PAD_DRIVER_S 2
+
+#define RTC_GPIO_PIN14 (DR_REG_RTCIO_BASE + 0x60)
+#define RTC_IO_RTC_GPIO_PIN14_WAKEUP_ENABLE (BIT(10))
+#define RTC_IO_RTC_GPIO_PIN14_WAKEUP_ENABLE_S 10
+#define RTC_IO_RTC_GPIO_PIN14_INT_TYPE 0x00000007
+#define RTC_IO_RTC_GPIO_PIN14_INT_TYPE_S 7
+#define RTC_IO_RTC_GPIO_PIN14_PAD_DRIVER (BIT(2))
+#define RTC_IO_RTC_GPIO_PIN14_PAD_DRIVER_S 2
+
+#define RTC_GPIO_PIN15 (DR_REG_RTCIO_BASE + 0x64)
+#define RTC_IO_RTC_GPIO_PIN15_WAKEUP_ENABLE (BIT(10))
+#define RTC_IO_RTC_GPIO_PIN15_WAKEUP_ENABLE_S 10
+#define RTC_IO_RTC_GPIO_PIN15_INT_TYPE 0x00000007
+#define RTC_IO_RTC_GPIO_PIN15_INT_TYPE_S 7
+#define RTC_IO_RTC_GPIO_PIN15_PAD_DRIVER (BIT(2))
+#define RTC_IO_RTC_GPIO_PIN15_PAD_DRIVER_S 2
+
+#define RTC_GPIO_PIN16 (DR_REG_RTCIO_BASE + 0x68)
+#define RTC_IO_RTC_GPIO_PIN16_WAKEUP_ENABLE (BIT(10))
+#define RTC_IO_RTC_GPIO_PIN16_WAKEUP_ENABLE_S 10
+#define RTC_IO_RTC_GPIO_PIN16_INT_TYPE 0x00000007
+#define RTC_IO_RTC_GPIO_PIN16_INT_TYPE_S 7
+#define RTC_IO_RTC_GPIO_PIN16_PAD_DRIVER (BIT(2))
+#define RTC_IO_RTC_GPIO_PIN16_PAD_DRIVER_S 2
+
+#define RTC_GPIO_PIN17 (DR_REG_RTCIO_BASE + 0x6c)
+#define RTC_IO_RTC_GPIO_PIN17_WAKEUP_ENABLE (BIT(10))
+#define RTC_IO_RTC_GPIO_PIN17_WAKEUP_ENABLE_S 10
+#define RTC_IO_RTC_GPIO_PIN17_INT_TYPE 0x00000007
+#define RTC_IO_RTC_GPIO_PIN17_INT_TYPE_S 7
+#define RTC_IO_RTC_GPIO_PIN17_PAD_DRIVER (BIT(2))
+#define RTC_IO_RTC_GPIO_PIN17_PAD_DRIVER_S 2
+
+#define RTC_DEBUG_SEL (DR_REG_RTCIO_BASE + 0x70)
+#define RTC_IO_RTC_DEBUG_12M_NO_GATING (BIT(25))
+#define RTC_IO_RTC_DEBUG_12M_NO_GATING_S 25
+#define RTC_IO_RTC_DEBUG_SEL4 0x0000001F
+#define RTC_IO_RTC_DEBUG_SEL4_S 20
+#define RTC_IO_RTC_DEBUG_SEL3 0x0000001F
+#define RTC_IO_RTC_DEBUG_SEL3_S 15
+#define RTC_IO_RTC_DEBUG_SEL2 0x0000001F
+#define RTC_IO_RTC_DEBUG_SEL2_S 10
+#define RTC_IO_RTC_DEBUG_SEL1 0x0000001F
+#define RTC_IO_RTC_DEBUG_SEL1_S 5
+#define RTC_IO_RTC_DEBUG_SEL0 0x0000001F
+#define RTC_IO_RTC_DEBUG_SEL0_S 0
+
+#define DIG_PAD_HOLD (DR_REG_RTCIO_BASE + 0x74)
+#define RTC_IO_DIG_PAD_HOLD 0xFFFFFFFF
+#define RTC_IO_DIG_PAD_HOLD_S 0
+
+#define HALL_SENS (DR_REG_RTCIO_BASE + 0x78)
+#define RTC_IO_XPD_HALL (BIT(31))
+#define RTC_IO_XPD_HALL_S 31
+#define RTC_IO_HALL_PHASE (BIT(30))
+#define RTC_IO_HALL_PHASE_S 30
+
+#define SENSOR_PADS (DR_REG_RTCIO_BASE + 0x7c)
+#define RTC_IO_SENSE1_HOLD (BIT(31))
+#define RTC_IO_SENSE1_HOLD_S 31
+#define RTC_IO_SENSE2_HOLD (BIT(30))
+#define RTC_IO_SENSE2_HOLD_S 30
+#define RTC_IO_SENSE3_HOLD (BIT(29))
+#define RTC_IO_SENSE3_HOLD_S 29
+#define RTC_IO_SENSE4_HOLD (BIT(28))
+#define RTC_IO_SENSE4_HOLD_S 28
+#define RTC_IO_SENSE1_MUX_SEL (BIT(27))
+#define RTC_IO_SENSE1_MUX_SEL_S 27
+#define RTC_IO_SENSE2_MUX_SEL (BIT(26))
+#define RTC_IO_SENSE2_MUX_SEL_S 26
+#define RTC_IO_SENSE3_MUX_SEL (BIT(25))
+#define RTC_IO_SENSE3_MUX_SEL_S 25
+#define RTC_IO_SENSE4_MUX_SEL (BIT(24))
+#define RTC_IO_SENSE4_MUX_SEL_S 24
+#define RTC_IO_SENSE1_FUN_SEL 0x00000003
+#define RTC_IO_SENSE1_FUN_SEL_S 22
+#define RTC_IO_SENSE1_SLP_SEL (BIT(21))
+#define RTC_IO_SENSE1_SLP_SEL_S 21
+#define RTC_IO_SENSE1_SLP_IE (BIT(20))
+#define RTC_IO_SENSE1_SLP_IE_S 20
+#define RTC_IO_SENSE1_FUN_IE (BIT(19))
+#define RTC_IO_SENSE1_FUN_IE_S 19
+#define RTC_IO_SENSE2_FUN_SEL 0x00000003
+#define RTC_IO_SENSE2_FUN_SEL_S 17
+#define RTC_IO_SENSE2_SLP_SEL (BIT(16))
+#define RTC_IO_SENSE2_SLP_SEL_S 16
+#define RTC_IO_SENSE2_SLP_IE (BIT(15))
+#define RTC_IO_SENSE2_SLP_IE_S 15
+#define RTC_IO_SENSE2_FUN_IE (BIT(14))
+#define RTC_IO_SENSE2_FUN_IE_S 14
+#define RTC_IO_SENSE3_FUN_SEL 0x00000003
+#define RTC_IO_SENSE3_FUN_SEL_S 12
+#define RTC_IO_SENSE3_SLP_SEL (BIT(11))
+#define RTC_IO_SENSE3_SLP_SEL_S 11
+#define RTC_IO_SENSE3_SLP_IE (BIT(10))
+#define RTC_IO_SENSE3_SLP_IE_S 10
+#define RTC_IO_SENSE3_FUN_IE (BIT(9))
+#define RTC_IO_SENSE3_FUN_IE_S 9
+#define RTC_IO_SENSE4_FUN_SEL 0x00000003
+#define RTC_IO_SENSE4_FUN_SEL_S 7
+#define RTC_IO_SENSE4_SLP_SEL (BIT(6))
+#define RTC_IO_SENSE4_SLP_SEL_S 6
+#define RTC_IO_SENSE4_SLP_IE (BIT(5))
+#define RTC_IO_SENSE4_SLP_IE_S 5
+#define RTC_IO_SENSE4_FUN_IE (BIT(4))
+#define RTC_IO_SENSE4_FUN_IE_S 4
+
+#define ADC_PAD (DR_REG_RTCIO_BASE + 0x80)
+#define RTC_IO_ADC1_HOLD (BIT(31))
+#define RTC_IO_ADC1_HOLD_S 31
+#define RTC_IO_ADC2_HOLD (BIT(30))
+#define RTC_IO_ADC2_HOLD_S 30
+#define RTC_IO_ADC1_MUX_SEL (BIT(29))
+#define RTC_IO_ADC1_MUX_SEL_S 29
+#define RTC_IO_ADC2_MUX_SEL (BIT(28))
+#define RTC_IO_ADC2_MUX_SEL_S 28
+#define RTC_IO_ADC1_FUN_SEL 0x00000003
+#define RTC_IO_ADC1_FUN_SEL_S 26
+#define RTC_IO_ADC1_SLP_SEL (BIT(25))
+#define RTC_IO_ADC1_SLP_SEL_S 25
+#define RTC_IO_ADC1_SLP_IE (BIT(24))
+#define RTC_IO_ADC1_SLP_IE_S 24
+#define RTC_IO_ADC1_FUN_IE (BIT(23))
+#define RTC_IO_ADC1_FUN_IE_S 23
+#define RTC_IO_ADC2_FUN_SEL 0x00000003
+#define RTC_IO_ADC2_FUN_SEL_S 21
+#define RTC_IO_ADC2_SLP_SEL (BIT(20))
+#define RTC_IO_ADC2_SLP_SEL_S 20
+#define RTC_IO_ADC2_SLP_IE (BIT(19))
+#define RTC_IO_ADC2_SLP_IE_S 19
+#define RTC_IO_ADC2_FUN_IE (BIT(18))
+#define RTC_IO_ADC2_FUN_IE_S 18
+
+#define PAD_DAC1 (DR_REG_RTCIO_BASE + 0x84)
+#define RTC_IO_PDAC1_DRV 0x00000003
+#define RTC_IO_PDAC1_DRV_S 30
+#define RTC_IO_PDAC1_HOLD (BIT(29))
+#define RTC_IO_PDAC1_HOLD_S 29
+#define RTC_IO_PDAC1_RDE (BIT(28))
+#define RTC_IO_PDAC1_RDE_S 28
+#define RTC_IO_PDAC1_RUE (BIT(27))
+#define RTC_IO_PDAC1_RUE_S 27
+#define RTC_IO_PDAC1_DAC 0x000000FF
+#define RTC_IO_PDAC1_DAC_S 19
+#define RTC_IO_PDAC1_XPD_DAC (BIT(18))
+#define RTC_IO_PDAC1_XPD_DAC_S 18
+#define RTC_IO_PDAC1_MUX_SEL (BIT(17))
+#define RTC_IO_PDAC1_MUX_SEL_S 17
+#define RTC_IO_PDAC1_FUN_SEL 0x00000003
+#define RTC_IO_PDAC1_FUN_SEL_S 15
+#define RTC_IO_PDAC1_SLP_SEL (BIT(14))
+#define RTC_IO_PDAC1_SLP_SEL_S 14
+#define RTC_IO_PDAC1_SLP_IE (BIT(13))
+#define RTC_IO_PDAC1_SLP_IE_S 13
+#define RTC_IO_PDAC1_SLP_OE (BIT(12))
+#define RTC_IO_PDAC1_SLP_OE_S 12
+#define RTC_IO_PDAC1_FUN_IE (BIT(11))
+#define RTC_IO_PDAC1_FUN_IE_S 11
+#define RTC_IO_PDAC1_DAC_XPD_FORCE (BIT(10))
+#define RTC_IO_PDAC1_DAC_XPD_FORCE_S 10
+
+#define PAD_DAC2 (DR_REG_RTCIO_BASE + 0x88)
+#define RTC_IO_PDAC2_DRV 0x00000003
+#define RTC_IO_PDAC2_DRV_S 30
+#define RTC_IO_PDAC2_HOLD (BIT(29))
+#define RTC_IO_PDAC2_HOLD_S 29
+#define RTC_IO_PDAC2_RDE (BIT(28))
+#define RTC_IO_PDAC2_RDE_S 28
+#define RTC_IO_PDAC2_RUE (BIT(27))
+#define RTC_IO_PDAC2_RUE_S 27
+#define RTC_IO_PDAC2_DAC 0x000000FF
+#define RTC_IO_PDAC2_DAC_S 19
+#define RTC_IO_PDAC2_XPD_DAC (BIT(18))
+#define RTC_IO_PDAC2_XPD_DAC_S 18
+#define RTC_IO_PDAC2_MUX_SEL (BIT(17))
+#define RTC_IO_PDAC2_MUX_SEL_S 17
+#define RTC_IO_PDAC2_FUN_SEL 0x00000003
+#define RTC_IO_PDAC2_FUN_SEL_S 15
+#define RTC_IO_PDAC2_SLP_SEL (BIT(14))
+#define RTC_IO_PDAC2_SLP_SEL_S 14
+#define RTC_IO_PDAC2_SLP_IE (BIT(13))
+#define RTC_IO_PDAC2_SLP_IE_S 13
+#define RTC_IO_PDAC2_SLP_OE (BIT(12))
+#define RTC_IO_PDAC2_SLP_OE_S 12
+#define RTC_IO_PDAC2_FUN_IE (BIT(11))
+#define RTC_IO_PDAC2_FUN_IE_S 11
+#define RTC_IO_PDAC2_DAC_XPD_FORCE (BIT(10))
+#define RTC_IO_PDAC2_DAC_XPD_FORCE_S 10
+
+#define XTAL_32K_PAD (DR_REG_RTCIO_BASE + 0x8c)
+#define RTC_IO_X32N_DRV 0x00000003
+#define RTC_IO_X32N_DRV_S 30
+#define RTC_IO_X32N_HOLD (BIT(29))
+#define RTC_IO_X32N_HOLD_S 29
+#define RTC_IO_X32N_RDE (BIT(28))
+#define RTC_IO_X32N_RDE_S 28
+#define RTC_IO_X32N_RUE (BIT(27))
+#define RTC_IO_X32N_RUE_S 27
+#define RTC_IO_X32P_DRV 0x00000003
+#define RTC_IO_X32P_DRV_S 25
+#define RTC_IO_X32P_HOLD (BIT(24))
+#define RTC_IO_X32P_HOLD_S 24
+#define RTC_IO_X32P_RDE (BIT(23))
+#define RTC_IO_X32P_RDE_S 23
+#define RTC_IO_X32P_RUE (BIT(22))
+#define RTC_IO_X32P_RUE_S 22
+#define RTC_IO_DAC_XTAL_32K 0x00000003
+#define RTC_IO_DAC_XTAL_32K_S 20
+#define RTC_IO_XPD_XTAL_32K (BIT(19))
+#define RTC_IO_XPD_XTAL_32K_S 19
+#define RTC_IO_X32N_MUX_SEL (BIT(18))
+#define RTC_IO_X32N_MUX_SEL_S 18
+#define RTC_IO_X32P_MUX_SEL (BIT(17))
+#define RTC_IO_X32P_MUX_SEL_S 17
+#define RTC_IO_X32N_FUN_SEL 0x00000003
+#define RTC_IO_X32N_FUN_SEL_S 15
+#define RTC_IO_X32N_SLP_SEL (BIT(14))
+#define RTC_IO_X32N_SLP_SEL_S 14
+#define RTC_IO_X32N_SLP_IE (BIT(13))
+#define RTC_IO_X32N_SLP_IE_S 13
+#define RTC_IO_X32N_SLP_OE (BIT(12))
+#define RTC_IO_X32N_SLP_OE_S 12
+#define RTC_IO_X32N_FUN_IE (BIT(11))
+#define RTC_IO_X32N_FUN_IE_S 11
+#define RTC_IO_X32P_FUN_SEL 0x00000003
+#define RTC_IO_X32P_FUN_SEL_S 9
+#define RTC_IO_X32P_SLP_SEL (BIT(8))
+#define RTC_IO_X32P_SLP_SEL_S 8
+#define RTC_IO_X32P_SLP_IE (BIT(7))
+#define RTC_IO_X32P_SLP_IE_S 7
+#define RTC_IO_X32P_SLP_OE (BIT(6))
+#define RTC_IO_X32P_SLP_OE_S 6
+#define RTC_IO_X32P_FUN_IE (BIT(5))
+#define RTC_IO_X32P_FUN_IE_S 5
+#define RTC_IO_DRES_XTAL_32K 0x00000003
+#define RTC_IO_DRES_XTAL_32K_S 3
+#define RTC_IO_DBIAS_XTAL_32K 0x00000003
+#define RTC_IO_DBIAS_XTAL_32K_S 1
+
+#define TOUCH_CFG (DR_REG_RTCIO_BASE + 0x90)
+#define RTC_IO_TOUCH_XPD_BIAS (BIT(31))
+#define RTC_IO_TOUCH_XPD_BIAS_S 31
+#define RTC_IO_TOUCH_DREFH 0x00000003
+#define RTC_IO_TOUCH_DREFH_S 29
+#define RTC_IO_TOUCH_DREFL 0x00000003
+#define RTC_IO_TOUCH_DREFL_S 27
+#define RTC_IO_TOUCH_DRANGE 0x00000003
+#define RTC_IO_TOUCH_DRANGE_S 25
+#define RTC_IO_TOUCH_DCUR 0x00000003
+#define RTC_IO_TOUCH_DCUR_S 23
+
+#define TOUCH_PAD0 (DR_REG_RTCIO_BASE + 0x94)
+#define RTC_IO_TOUCH_PAD0_HOLD (BIT(31))
+#define RTC_IO_TOUCH_PAD0_HOLD_S 31
+#define RTC_IO_TOUCH_PAD0_DRV 0x00000003
+#define RTC_IO_TOUCH_PAD0_DRV_S 29
+#define RTC_IO_TOUCH_PAD0_RDE (BIT(28))
+#define RTC_IO_TOUCH_PAD0_RDE_S 28
+#define RTC_IO_TOUCH_PAD0_RUE (BIT(27))
+#define RTC_IO_TOUCH_PAD0_RUE_S 27
+#define RTC_IO_TOUCH_PAD0_DAC 0x00000007
+#define RTC_IO_TOUCH_PAD0_DAC_S 23
+#define RTC_IO_TOUCH_PAD0_START (BIT(22))
+#define RTC_IO_TOUCH_PAD0_START_S 22
+#define RTC_IO_TOUCH_PAD0_TIE_OPT (BIT(21))
+#define RTC_IO_TOUCH_PAD0_TIE_OPT_S 21
+#define RTC_IO_TOUCH_PAD0_XPD (BIT(20))
+#define RTC_IO_TOUCH_PAD0_XPD_S 20
+#define RTC_IO_TOUCH_PAD0_MUX_SEL (BIT(19))
+#define RTC_IO_TOUCH_PAD0_MUX_SEL_S 19
+#define RTC_IO_TOUCH_PAD0_FUN_SEL 0x00000003
+#define RTC_IO_TOUCH_PAD0_FUN_SEL_S 17
+#define RTC_IO_TOUCH_PAD0_SLP_SEL (BIT(16))
+#define RTC_IO_TOUCH_PAD0_SLP_SEL_S 16
+#define RTC_IO_TOUCH_PAD0_SLP_IE (BIT(15))
+#define RTC_IO_TOUCH_PAD0_SLP_IE_S 15
+#define RTC_IO_TOUCH_PAD0_SLP_OE (BIT(14))
+#define RTC_IO_TOUCH_PAD0_SLP_OE_S 14
+#define RTC_IO_TOUCH_PAD0_FUN_IE (BIT(13))
+#define RTC_IO_TOUCH_PAD0_FUN_IE_S 13
+#define RTC_IO_TOUCH_PAD0_TO_GPIO (BIT(12))
+#define RTC_IO_TOUCH_PAD0_TO_GPIO_S 12
+
+#define TOUCH_PAD1 (DR_REG_RTCIO_BASE + 0x98)
+#define RTC_IO_TOUCH_PAD1_HOLD (BIT(31))
+#define RTC_IO_TOUCH_PAD1_HOLD_S 31
+#define RTC_IO_TOUCH_PAD1_DRV 0x00000003
+#define RTC_IO_TOUCH_PAD1_DRV_S 29
+#define RTC_IO_TOUCH_PAD1_RDE (BIT(28))
+#define RTC_IO_TOUCH_PAD1_RDE_S 28
+#define RTC_IO_TOUCH_PAD1_RUE (BIT(27))
+#define RTC_IO_TOUCH_PAD1_RUE_S 27
+#define RTC_IO_TOUCH_PAD1_DAC 0x00000007
+#define RTC_IO_TOUCH_PAD1_DAC_S 23
+#define RTC_IO_TOUCH_PAD1_START (BIT(22))
+#define RTC_IO_TOUCH_PAD1_START_S 22
+#define RTC_IO_TOUCH_PAD1_TIE_OPT (BIT(21))
+#define RTC_IO_TOUCH_PAD1_TIE_OPT_S 21
+#define RTC_IO_TOUCH_PAD1_XPD (BIT(20))
+#define RTC_IO_TOUCH_PAD1_XPD_S 20
+#define RTC_IO_TOUCH_PAD1_MUX_SEL (BIT(19))
+#define RTC_IO_TOUCH_PAD1_MUX_SEL_S 19
+#define RTC_IO_TOUCH_PAD1_FUN_SEL 0x00000003
+#define RTC_IO_TOUCH_PAD1_FUN_SEL_S 17
+#define RTC_IO_TOUCH_PAD1_SLP_SEL (BIT(16))
+#define RTC_IO_TOUCH_PAD1_SLP_SEL_S 16
+#define RTC_IO_TOUCH_PAD1_SLP_IE (BIT(15))
+#define RTC_IO_TOUCH_PAD1_SLP_IE_S 15
+#define RTC_IO_TOUCH_PAD1_SLP_OE (BIT(14))
+#define RTC_IO_TOUCH_PAD1_SLP_OE_S 14
+#define RTC_IO_TOUCH_PAD1_FUN_IE (BIT(13))
+#define RTC_IO_TOUCH_PAD1_FUN_IE_S 13
+#define RTC_IO_TOUCH_PAD1_TO_GPIO (BIT(12))
+#define RTC_IO_TOUCH_PAD1_TO_GPIO_S 12
+
+#define TOUCH_PAD2 (DR_REG_RTCIO_BASE + 0x9c)
+#define RTC_IO_TOUCH_PAD2_HOLD (BIT(31))
+#define RTC_IO_TOUCH_PAD2_HOLD_S 31
+#define RTC_IO_TOUCH_PAD2_DRV 0x00000003
+#define RTC_IO_TOUCH_PAD2_DRV_S 29
+#define RTC_IO_TOUCH_PAD2_RDE (BIT(28))
+#define RTC_IO_TOUCH_PAD2_RDE_S 28
+#define RTC_IO_TOUCH_PAD2_RUE (BIT(27))
+#define RTC_IO_TOUCH_PAD2_RUE_S 27
+#define RTC_IO_TOUCH_PAD2_DAC 0x00000007
+#define RTC_IO_TOUCH_PAD2_DAC_S 23
+#define RTC_IO_TOUCH_PAD2_START (BIT(22))
+#define RTC_IO_TOUCH_PAD2_START_S 22
+#define RTC_IO_TOUCH_PAD2_TIE_OPT (BIT(21))
+#define RTC_IO_TOUCH_PAD2_TIE_OPT_S 21
+#define RTC_IO_TOUCH_PAD2_XPD (BIT(20))
+#define RTC_IO_TOUCH_PAD2_XPD_S 20
+#define RTC_IO_TOUCH_PAD2_MUX_SEL (BIT(19))
+#define RTC_IO_TOUCH_PAD2_MUX_SEL_S 19
+#define RTC_IO_TOUCH_PAD2_FUN_SEL 0x00000003
+#define RTC_IO_TOUCH_PAD2_FUN_SEL_S 17
+#define RTC_IO_TOUCH_PAD2_SLP_SEL (BIT(16))
+#define RTC_IO_TOUCH_PAD2_SLP_SEL_S 16
+#define RTC_IO_TOUCH_PAD2_SLP_IE (BIT(15))
+#define RTC_IO_TOUCH_PAD2_SLP_IE_S 15
+#define RTC_IO_TOUCH_PAD2_SLP_OE (BIT(14))
+#define RTC_IO_TOUCH_PAD2_SLP_OE_S 14
+#define RTC_IO_TOUCH_PAD2_FUN_IE (BIT(13))
+#define RTC_IO_TOUCH_PAD2_FUN_IE_S 13
+#define RTC_IO_TOUCH_PAD2_TO_GPIO (BIT(12))
+#define RTC_IO_TOUCH_PAD2_TO_GPIO_S 12
+
+#define TOUCH_PAD3 (DR_REG_RTCIO_BASE + 0xa0)
+#define RTC_IO_TOUCH_PAD3_HOLD (BIT(31))
+#define RTC_IO_TOUCH_PAD3_HOLD_S 31
+#define RTC_IO_TOUCH_PAD3_DRV 0x00000003
+#define RTC_IO_TOUCH_PAD3_DRV_S 29
+#define RTC_IO_TOUCH_PAD3_RDE (BIT(28))
+#define RTC_IO_TOUCH_PAD3_RDE_S 28
+#define RTC_IO_TOUCH_PAD3_RUE (BIT(27))
+#define RTC_IO_TOUCH_PAD3_RUE_S 27
+#define RTC_IO_TOUCH_PAD3_DAC 0x00000007
+#define RTC_IO_TOUCH_PAD3_DAC_S 23
+#define RTC_IO_TOUCH_PAD3_START (BIT(22))
+#define RTC_IO_TOUCH_PAD3_START_S 22
+#define RTC_IO_TOUCH_PAD3_TIE_OPT (BIT(21))
+#define RTC_IO_TOUCH_PAD3_TIE_OPT_S 21
+#define RTC_IO_TOUCH_PAD3_XPD (BIT(20))
+#define RTC_IO_TOUCH_PAD3_XPD_S 20
+#define RTC_IO_TOUCH_PAD3_MUX_SEL (BIT(19))
+#define RTC_IO_TOUCH_PAD3_MUX_SEL_S 19
+#define RTC_IO_TOUCH_PAD3_FUN_SEL 0x00000003
+#define RTC_IO_TOUCH_PAD3_FUN_SEL_S 17
+#define RTC_IO_TOUCH_PAD3_SLP_SEL (BIT(16))
+#define RTC_IO_TOUCH_PAD3_SLP_SEL_S 16
+#define RTC_IO_TOUCH_PAD3_SLP_IE (BIT(15))
+#define RTC_IO_TOUCH_PAD3_SLP_IE_S 15
+#define RTC_IO_TOUCH_PAD3_SLP_OE (BIT(14))
+#define RTC_IO_TOUCH_PAD3_SLP_OE_S 14
+#define RTC_IO_TOUCH_PAD3_FUN_IE (BIT(13))
+#define RTC_IO_TOUCH_PAD3_FUN_IE_S 13
+#define RTC_IO_TOUCH_PAD3_TO_GPIO (BIT(12))
+#define RTC_IO_TOUCH_PAD3_TO_GPIO_S 12
+
+#define TOUCH_PAD4 (DR_REG_RTCIO_BASE + 0xa4)
+#define RTC_IO_TOUCH_PAD4_HOLD (BIT(31))
+#define RTC_IO_TOUCH_PAD4_HOLD_S 31
+#define RTC_IO_TOUCH_PAD4_DRV 0x00000003
+#define RTC_IO_TOUCH_PAD4_DRV_S 29
+#define RTC_IO_TOUCH_PAD4_RDE (BIT(28))
+#define RTC_IO_TOUCH_PAD4_RDE_S 28
+#define RTC_IO_TOUCH_PAD4_RUE (BIT(27))
+#define RTC_IO_TOUCH_PAD4_RUE_S 27
+#define RTC_IO_TOUCH_PAD4_DAC 0x00000007
+#define RTC_IO_TOUCH_PAD4_DAC_S 23
+#define RTC_IO_TOUCH_PAD4_START (BIT(22))
+#define RTC_IO_TOUCH_PAD4_START_S 22
+#define RTC_IO_TOUCH_PAD4_TIE_OPT (BIT(21))
+#define RTC_IO_TOUCH_PAD4_TIE_OPT_S 21
+#define RTC_IO_TOUCH_PAD4_XPD (BIT(20))
+#define RTC_IO_TOUCH_PAD4_XPD_S 20
+#define RTC_IO_TOUCH_PAD4_MUX_SEL (BIT(19))
+#define RTC_IO_TOUCH_PAD4_MUX_SEL_S 19
+#define RTC_IO_TOUCH_PAD4_FUN_SEL 0x00000003
+#define RTC_IO_TOUCH_PAD4_FUN_SEL_S 17
+#define RTC_IO_TOUCH_PAD4_SLP_SEL (BIT(16))
+#define RTC_IO_TOUCH_PAD4_SLP_SEL_S 16
+#define RTC_IO_TOUCH_PAD4_SLP_IE (BIT(15))
+#define RTC_IO_TOUCH_PAD4_SLP_IE_S 15
+#define RTC_IO_TOUCH_PAD4_SLP_OE (BIT(14))
+#define RTC_IO_TOUCH_PAD4_SLP_OE_S 14
+#define RTC_IO_TOUCH_PAD4_FUN_IE (BIT(13))
+#define RTC_IO_TOUCH_PAD4_FUN_IE_S 13
+#define RTC_IO_TOUCH_PAD4_TO_GPIO (BIT(12))
+#define RTC_IO_TOUCH_PAD4_TO_GPIO_S 12
+
+#define TOUCH_PAD5 (DR_REG_RTCIO_BASE + 0xa8)
+#define RTC_IO_TOUCH_PAD5_HOLD (BIT(31))
+#define RTC_IO_TOUCH_PAD5_HOLD_S 31
+#define RTC_IO_TOUCH_PAD5_DRV 0x00000003
+#define RTC_IO_TOUCH_PAD5_DRV_S 29
+#define RTC_IO_TOUCH_PAD5_RDE (BIT(28))
+#define RTC_IO_TOUCH_PAD5_RDE_S 28
+#define RTC_IO_TOUCH_PAD5_RUE (BIT(27))
+#define RTC_IO_TOUCH_PAD5_RUE_S 27
+#define RTC_IO_TOUCH_PAD5_DAC 0x00000007
+#define RTC_IO_TOUCH_PAD5_DAC_S 23
+#define RTC_IO_TOUCH_PAD5_START (BIT(22))
+#define RTC_IO_TOUCH_PAD5_START_S 22
+#define RTC_IO_TOUCH_PAD5_TIE_OPT (BIT(21))
+#define RTC_IO_TOUCH_PAD5_TIE_OPT_S 21
+#define RTC_IO_TOUCH_PAD5_XPD (BIT(20))
+#define RTC_IO_TOUCH_PAD5_XPD_S 20
+#define RTC_IO_TOUCH_PAD5_MUX_SEL (BIT(19))
+#define RTC_IO_TOUCH_PAD5_MUX_SEL_S 19
+#define RTC_IO_TOUCH_PAD5_FUN_SEL 0x00000003
+#define RTC_IO_TOUCH_PAD5_FUN_SEL_S 17
+#define RTC_IO_TOUCH_PAD5_SLP_SEL (BIT(16))
+#define RTC_IO_TOUCH_PAD5_SLP_SEL_S 16
+#define RTC_IO_TOUCH_PAD5_SLP_IE (BIT(15))
+#define RTC_IO_TOUCH_PAD5_SLP_IE_S 15
+#define RTC_IO_TOUCH_PAD5_SLP_OE (BIT(14))
+#define RTC_IO_TOUCH_PAD5_SLP_OE_S 14
+#define RTC_IO_TOUCH_PAD5_FUN_IE (BIT(13))
+#define RTC_IO_TOUCH_PAD5_FUN_IE_S 13
+#define RTC_IO_TOUCH_PAD5_TO_GPIO (BIT(12))
+#define RTC_IO_TOUCH_PAD5_TO_GPIO_S 12
+
+#define TOUCH_PAD6 (DR_REG_RTCIO_BASE + 0xac)
+#define RTC_IO_TOUCH_PAD6_HOLD (BIT(31))
+#define RTC_IO_TOUCH_PAD6_HOLD_S 31
+#define RTC_IO_TOUCH_PAD6_DRV 0x00000003
+#define RTC_IO_TOUCH_PAD6_DRV_S 29
+#define RTC_IO_TOUCH_PAD6_RDE (BIT(28))
+#define RTC_IO_TOUCH_PAD6_RDE_S 28
+#define RTC_IO_TOUCH_PAD6_RUE (BIT(27))
+#define RTC_IO_TOUCH_PAD6_RUE_S 27
+#define RTC_IO_TOUCH_PAD6_DAC 0x00000007
+#define RTC_IO_TOUCH_PAD6_DAC_S 23
+#define RTC_IO_TOUCH_PAD6_START (BIT(22))
+#define RTC_IO_TOUCH_PAD6_START_S 22
+#define RTC_IO_TOUCH_PAD6_TIE_OPT (BIT(21))
+#define RTC_IO_TOUCH_PAD6_TIE_OPT_S 21
+#define RTC_IO_TOUCH_PAD6_XPD (BIT(20))
+#define RTC_IO_TOUCH_PAD6_XPD_S 20
+#define RTC_IO_TOUCH_PAD6_MUX_SEL (BIT(19))
+#define RTC_IO_TOUCH_PAD6_MUX_SEL_S 19
+#define RTC_IO_TOUCH_PAD6_FUN_SEL 0x00000003
+#define RTC_IO_TOUCH_PAD6_FUN_SEL_S 17
+#define RTC_IO_TOUCH_PAD6_SLP_SEL (BIT(16))
+#define RTC_IO_TOUCH_PAD6_SLP_SEL_S 16
+#define RTC_IO_TOUCH_PAD6_SLP_IE (BIT(15))
+#define RTC_IO_TOUCH_PAD6_SLP_IE_S 15
+#define RTC_IO_TOUCH_PAD6_SLP_OE (BIT(14))
+#define RTC_IO_TOUCH_PAD6_SLP_OE_S 14
+#define RTC_IO_TOUCH_PAD6_FUN_IE (BIT(13))
+#define RTC_IO_TOUCH_PAD6_FUN_IE_S 13
+#define RTC_IO_TOUCH_PAD6_TO_GPIO (BIT(12))
+#define RTC_IO_TOUCH_PAD6_TO_GPIO_S 12
+
+#define TOUCH_PAD7 (DR_REG_RTCIO_BASE + 0xb0)
+#define RTC_IO_TOUCH_PAD7_HOLD (BIT(31))
+#define RTC_IO_TOUCH_PAD7_HOLD_S 31
+#define RTC_IO_TOUCH_PAD7_DRV 0x00000003
+#define RTC_IO_TOUCH_PAD7_DRV_S 29
+#define RTC_IO_TOUCH_PAD7_RDE (BIT(28))
+#define RTC_IO_TOUCH_PAD7_RDE_S 28
+#define RTC_IO_TOUCH_PAD7_RUE (BIT(27))
+#define RTC_IO_TOUCH_PAD7_RUE_S 27
+#define RTC_IO_TOUCH_PAD7_DAC 0x00000007
+#define RTC_IO_TOUCH_PAD7_DAC_S 23
+#define RTC_IO_TOUCH_PAD7_START (BIT(22))
+#define RTC_IO_TOUCH_PAD7_START_S 22
+#define RTC_IO_TOUCH_PAD7_TIE_OPT (BIT(21))
+#define RTC_IO_TOUCH_PAD7_TIE_OPT_S 21
+#define RTC_IO_TOUCH_PAD7_XPD (BIT(20))
+#define RTC_IO_TOUCH_PAD7_XPD_S 20
+#define RTC_IO_TOUCH_PAD7_MUX_SEL (BIT(19))
+#define RTC_IO_TOUCH_PAD7_MUX_SEL_S 19
+#define RTC_IO_TOUCH_PAD7_FUN_SEL 0x00000003
+#define RTC_IO_TOUCH_PAD7_FUN_SEL_S 17
+#define RTC_IO_TOUCH_PAD7_SLP_SEL (BIT(16))
+#define RTC_IO_TOUCH_PAD7_SLP_SEL_S 16
+#define RTC_IO_TOUCH_PAD7_SLP_IE (BIT(15))
+#define RTC_IO_TOUCH_PAD7_SLP_IE_S 15
+#define RTC_IO_TOUCH_PAD7_SLP_OE (BIT(14))
+#define RTC_IO_TOUCH_PAD7_SLP_OE_S 14
+#define RTC_IO_TOUCH_PAD7_FUN_IE (BIT(13))
+#define RTC_IO_TOUCH_PAD7_FUN_IE_S 13
+#define RTC_IO_TOUCH_PAD7_TO_GPIO (BIT(12))
+#define RTC_IO_TOUCH_PAD7_TO_GPIO_S 12
+
+#define TOUCH_PAD8 (DR_REG_RTCIO_BASE + 0xb4)
+#define RTC_IO_TOUCH_PAD8_DAC 0x00000007
+#define RTC_IO_TOUCH_PAD8_DAC_S 23
+#define RTC_IO_TOUCH_PAD8_START (BIT(22))
+#define RTC_IO_TOUCH_PAD8_START_S 22
+#define RTC_IO_TOUCH_PAD8_TIE_OPT (BIT(21))
+#define RTC_IO_TOUCH_PAD8_TIE_OPT_S 21
+#define RTC_IO_TOUCH_PAD8_XPD (BIT(20))
+#define RTC_IO_TOUCH_PAD8_XPD_S 20
+#define RTC_IO_TOUCH_PAD8_TO_GPIO (BIT(19))
+#define RTC_IO_TOUCH_PAD8_TO_GPIO_S 19
+
+#define TOUCH_PAD9 (DR_REG_RTCIO_BASE + 0xb8)
+#define RTC_IO_TOUCH_PAD9_DAC 0x00000007
+#define RTC_IO_TOUCH_PAD9_DAC_S 23
+#define RTC_IO_TOUCH_PAD9_START (BIT(22))
+#define RTC_IO_TOUCH_PAD9_START_S 22
+#define RTC_IO_TOUCH_PAD9_TIE_OPT (BIT(21))
+#define RTC_IO_TOUCH_PAD9_TIE_OPT_S 21
+#define RTC_IO_TOUCH_PAD9_XPD (BIT(20))
+#define RTC_IO_TOUCH_PAD9_XPD_S 20
+#define RTC_IO_TOUCH_PAD9_TO_GPIO (BIT(19))
+#define RTC_IO_TOUCH_PAD9_TO_GPIO_S 19
+
+#define EXT_WAKEUP0 (DR_REG_RTCIO_BASE + 0xbc)
+#define RTC_IO_EXT_WAKEUP0_SEL 0x0000001F
+#define RTC_IO_EXT_WAKEUP0_SEL_S 27
+
+#define XTL_EXT_CTR (DR_REG_RTCIO_BASE + 0xc0)
+#define RTC_IO_XTL_EXT_CTR_SEL 0x0000001F
+#define RTC_IO_XTL_EXT_CTR_SEL_S 27
+
+#define SAR_I2C_IO (DR_REG_RTCIO_BASE + 0xc4)
+#define RTC_IO_SAR_I2C_SDA_SEL 0x00000003
+#define RTC_IO_SAR_I2C_SDA_SEL_S 30
+#define RTC_IO_SAR_I2C_SCL_SEL 0x00000003
+#define RTC_IO_SAR_I2C_SCL_SEL_S 28
+#define RTC_IO_SAR_DEBUG_BIT_SEL 0x0000001F
+#define RTC_IO_SAR_DEBUG_BIT_SEL_S 23
+
+#define RTC_IO_DATE (DR_REG_RTCIO_BASE + 0xc8)
+#define RTC_IO_RTC_IO_DATE 0x0FFFFFFF
+#define RTC_IO_RTC_IO_DATE_S 0
+#define RTC_IO_RTC_IO_DATE_VERSION 0x1703160
+
+#endif /* _SOC_RTC_IO_REG_H_ */
+

components/esp32/include/soc/soc.h

@@ -0,0 +1,270 @@
+// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef _ESP32_SOC_H_
+#define _ESP32_SOC_H_
+
+#include <stdint.h>
+
+//Register Bits{{
+#define BIT31   0x80000000
+#define BIT30   0x40000000
+#define BIT29   0x20000000
+#define BIT28   0x10000000
+#define BIT27   0x08000000
+#define BIT26   0x04000000
+#define BIT25   0x02000000
+#define BIT24   0x01000000
+#define BIT23   0x00800000
+#define BIT22   0x00400000
+#define BIT21   0x00200000
+#define BIT20   0x00100000
+#define BIT19   0x00080000
+#define BIT18   0x00040000
+#define BIT17   0x00020000
+#define BIT16   0x00010000
+#define BIT15   0x00008000
+#define BIT14   0x00004000
+#define BIT13   0x00002000
+#define BIT12   0x00001000
+#define BIT11   0x00000800
+#define BIT10   0x00000400
+#define BIT9     0x00000200
+#define BIT8     0x00000100
+#define BIT7     0x00000080
+#define BIT6     0x00000040
+#define BIT5     0x00000020
+#define BIT4     0x00000010
+#define BIT3     0x00000008
+#define BIT2     0x00000004
+#define BIT1     0x00000002
+#define BIT0     0x00000001
+//}}
+
+//Registers Operation {{
+#define ETS_UNCACHED_ADDR(addr) (addr)
+#define ETS_CACHED_ADDR(addr) (addr) 
+
+#define BIT(nr)                 (1UL << (nr))
+
+#define REG_WRITE(_r, _v)    (*(volatile uint32_t *)(_r)) = (_v)
+#define REG_READ(_r) (*(volatile uint32_t *)(_r))
+
+#define REG_GET_BIT(_r, _b)  (*(volatile uint32_t*)(_r) & (_b))
+#define REG_SET_BIT(_r, _b)  (*(volatile uint32_t*)(_r) |= (_b))
+#define REG_CLR_BIT(_r, _b)  (*(volatile uint32_t*)(_r) &= ~(_b))
+#define REG_SET_BITS(_r, _b, _m) (*(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r) & ~(_m)) | ((_b) & (_m)))
+#define VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f))
+#define VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S))
+#define VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S))))
+#define VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S))))
+#define FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S)
+#define FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f))
+#define REG_GET_FIELD(_r, _f) ((REG_READ(_r) >> (_f##_S)) & (_f))
+#define REG_SET_FIELD(_r, _f, _v) (REG_WRITE((_r),((REG_READ(_r) & ~((_f) << (_f##_S)))|(((_v) & (_f))<<(_f##_S)))))
+
+
+#define READ_PERI_REG(addr) (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) 
+#define WRITE_PERI_REG(addr, val) (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) = (uint32_t)(val)   
+#define CLEAR_PERI_REG_MASK(reg, mask) WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask))))
+#define SET_PERI_REG_MASK(reg, mask)   WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask)))
+#define GET_PERI_REG_MASK(reg, mask)   (READ_PERI_REG(reg) & (mask))
+#define GET_PERI_REG_BITS(reg, hipos,lowpos)      ((READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1)) 
+#define SET_PERI_REG_BITS(reg,bit_map,value,shift) (WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift)) ))
+#define GET_PERI_REG_BITS2(reg, mask,shift)      ((READ_PERI_REG(reg)>>(shift))&(mask))
+//}}
+
+//Periheral Clock {{
+#define  APB_CLK_FREQ_ROM                            13*1000000
+#define  CPU_CLK_FREQ_ROM                            APB_CLK_FREQ_ROM
+#define  CPU_CLK_FREQ                                APB_CLK_FREQ
+#define  APB_CLK_FREQ                                40*1000000       //unit: Hz
+#define  UART_CLK_FREQ                               APB_CLK_FREQ
+//#define  WDT_CLK_FREQ                                APB_CLK_FREQ
+#define  TIMER_CLK_FREQ                              (80000000>>4) //80MHz divided by 16
+#define  SPI_CLK_DIV                                 4
+//#define  RTC_CLK_FREQ                              32768           //unit:Hz
+//#define  RTC_CLK_FREQ                                100000          //unit:Hz
+//#define  CALIB_CLK_MHZ                               40
+#define  TICKS_PER_US                                13              // CPU is 80MHz
+//}}
+
+#if 0
+//Peripheral device base address define{{
+#define DR_REG_DPORT_BASE			0x3ff00000
+#define DR_REG_UART_BASE 0x60000000
+#define DR_REG_SPI1_BASE 0x60002000 //no
+#define DR_REG_SPI0_BASE 0x60003000 //no
+#define DR_REG_GPIO_BASE 0x60004000 //no
+#define DR_REG_FE2_BASE 0x60005000
+#define DR_REG_FE_BASE 0x60006000
+#define DR_REG_TIMER_BASE 0x60007000 //no
+#define DR_REG_RTCCNTL_BASE 0x60008000
+#define DR_REG_RTCIO_BASE 0x60008400
+
+#define DR_REG_RTCMEM0_BASE 0x60021000
+#define DR_REG_RTCMEM1_BASE 0x60022000
+#define DR_REG_RTCMEM2_BASE 0x60023000
+
+#define DR_REG_IO_MUX_BASE 0x60009000 //no
+#define DR_REG_WDG_BASE 0x6000A000 //no
+#define DR_REG_HINF_BASE 0x6000B000 //no
+#define DR_REG_UHCI1_BASE 0x6000C000
+//#define DR_REG_MISC_BASE 0x6000D000 //no use
+#define DR_REG_I2C_BASE 0x6000E000 //no
+#define DR_REG_I2S_BASE 0x6000F000 
+#define DR_REG_UART1_BASE 0x60010000
+#define DR_REG_BT_BASE 0x60011000
+//#define DR_REG_BT_BUFFER_BASE 0x60012000 //no use
+#define DR_REG_I2C_EXT_BASE 0x60013000 //no
+#define DR_REG_UHCI0_BASE 0x60014000
+#define DR_REG_SLCHOST_BASE 0x60015000
+#define DR_REG_RMT_BASE 0x60016000
+#define DR_REG_PCNT_BASE 0x60017000
+#define DR_REG_SLC_BASE 0x60018000
+#define DR_REG_LEDC_BASE 0x60019000
+#define DR_REG_EFUSE_BASE 0x6001A000
+#define DR_REG_SPI_ENCRYPT_BASE 0x6001B000
+#define DR_REG_PWM_BASE 0x6001C000 //no
+#define DR_REG_TIMERGROUP_BASE 0x6001D000 //no
+#define DR_REG_TIMERGROUP1_BASE 0x6001E000 //no
+#define DR_REG_BB_BASE 0x6001F000
+#define DR_REG_GPIO_SD_BASE 0x60004f00
+#else
+#define DR_REG_DPORT_BASE                       0x3ff00000
+#define DR_REG_UART_BASE 0x3ff40000
+#define DR_REG_SPI1_BASE 0x3ff42000 //no
+#define DR_REG_SPI0_BASE 0x3ff43000 //no
+#define DR_REG_GPIO_BASE 0x3ff44000 //no
+#define DR_REG_FE2_BASE 0x3ff45000
+#define DR_REG_FE_BASE 0x3ff46000
+#define DR_REG_TIMER_BASE 0x3ff47000 //no
+#define DR_REG_RTCCNTL_BASE 0x3ff48000
+#define DR_REG_RTCIO_BASE 0x3ff48400
+
+#define DR_REG_RTCMEM0_BASE 0x3ff61000
+#define DR_REG_RTCMEM1_BASE 0x3ff62000
+#define DR_REG_RTCMEM2_BASE 0x3ff63000
+
+#define DR_REG_IO_MUX_BASE 0x3ff49000 //no
+#define DR_REG_WDG_BASE 0x3ff4A000 //no
+#define DR_REG_HINF_BASE 0x3ff4B000 //no
+#define DR_REG_UHCI1_BASE 0x3ff4C000
+//#define DR_REG_MISC_BASE 0x6000D000 //no use
+#define DR_REG_I2C_BASE 0x3ff4E000 //no
+#define DR_REG_I2S_BASE 0x3ff4F000 
+#define DR_REG_I2S1_BASE 0x3ff6D000 
+#define DR_REG_UART1_BASE 0x3ff50000
+#define DR_REG_BT_BASE 0x3ff51000
+//#define DR_REG_BT_BUFFER_BASE 0x60012000 //no use
+#define DR_REG_I2C_EXT_BASE 0x3ff53000 //no
+#define DR_REG_UHCI0_BASE 0x3ff54000
+#define DR_REG_SLCHOST_BASE 0x3ff55000
+#define DR_REG_RMT_BASE 0x3ff56000
+#define DR_REG_PCNT_BASE 0x3ff57000
+#define DR_REG_SLC_BASE 0x3ff58000
+#define DR_REG_LEDC_BASE 0x3ff59000
+#define DR_REG_EFUSE_BASE 0x3ff5A000
+#define DR_REG_SPI_ENCRYPT_BASE 0x3ff5B000
+#define DR_REG_PWM_BASE 0x3ff5C000 //no
+#define DR_REG_TIMERS_BASE 0x3ff5F000 //no
+#define DR_REG_TIMERGROUP1_BASE 0x3ff5E000 //no
+#define DR_REG_BB_BASE 0x3ff5F000
+#define DR_REG_GPIO_SD_BASE 0x3ff44f00
+#endif
+
+//}}
+#define REG_SPI_BASE(i)                     (DR_REG_SPI0_BASE - i*(0x1000))
+#define PERIPHS_TIMER_BASEDDR			DR_REG_TIMER_BASE
+#define PERIPHS_SPI_ENCRYPT_BASEADDR		DR_REG_SPI_ENCRYPT_BASE
+
+#define UART0_UNHOLD_MASK 0x3
+#define UART1_UNHOLD_MASK 0x60
+#define SDIO_UNHOLD_MASK 0xfc
+#define SPI_UNHOLD_MASK 0xfc
+
+// TIMER reg {{
+#define TIMER_REG_READ(addr)                        READ_PERI_REG(addr)
+#define TIMER_REG_WRITE(addr, val)                WRITE_PERI_REG(addr, val)
+#define TIMER_SET_REG_MASK(reg, mask)      WRITE_PERI_REG(reg, (READ_PERI_REG(reg)|(mask)))
+/* Returns the current time according to the timer timer. */
+#define NOW()                                                 TIMER_REG_READ(FRC2_COUNT_ADDRESS)
+//load initial_value to timer1
+#define FRC1_LOAD_ADDRESS                    (PERIPHS_TIMER_BASEDDR +0x00)
+#define FRC1_LOAD_DATA_MSB                 22
+#define FRC1_LOAD_DATA_LSB                  0
+#define FRC1_LOAD_DATA_MASK              0x007fffff
+
+//timer1's counter value(count from initial_value to 0)
+#define FRC1_COUNT_ADDRESS                 (PERIPHS_TIMER_BASEDDR +0x04)
+#define FRC1_COUNT_DATA_MSB              22
+#define FRC1_COUNT_DATA_LSB               0
+#define FRC1_COUNT_DATA_MASK           0x007fffff
+
+#define FRC1_CTRL_ADDRESS                    (PERIPHS_TIMER_BASEDDR +0x08)
+#define FRC1_CTRL_DATA_MSB                 7
+#define FRC1_CTRL_DATA_LSB                  0
+#define FRC1_CTRL_DATA_MASK              0x000000ff
+
+//clear timer1's interrupt when write this address
+#define FRC1_INT_ADDRESS                      (PERIPHS_TIMER_BASEDDR +0x0c)
+#define FRC1_INT_CLR_MSB                      0
+#define FRC1_INT_CLR_LSB                       0
+#define FRC1_INT_CLR_MASK                   0x00000001
+
+//only used for simulation
+#define FRC1_TEST_ADDRESS                   (PERIPHS_TIMER_BASEDDR +0x10)
+#define FRC1_TEST_MODE_MSB                0
+#define FRC1_TEST_MODE_LSB                 0
+#define FRC1_TEST_MODE_MASK             0x00000001
+
+//load initial_value to timer2
+#define FRC2_LOAD_ADDRESS                  (PERIPHS_TIMER_BASEDDR +0x20)
+#define FRC2_LOAD_DATA_MSB               31
+#define FRC2_LOAD_DATA_LSB                0
+#define FRC2_LOAD_DATA_MASK            0xffffffff
+
+//timer2's counter value(count from initial_value to 0)
+#define FRC2_COUNT_ADDRESS                (PERIPHS_TIMER_BASEDDR +0x24)
+#define FRC2_COUNT_DATA_MSB             31
+#define FRC2_COUNT_DATA_LSB              0
+#define FRC2_COUNT_DATA_MASK          0xffffffff
+
+#define FRC2_CTRL_ADDRESS                    (PERIPHS_TIMER_BASEDDR +0x28)
+#define FRC2_CTRL_DATA_MSB                 7
+#define FRC2_CTRL_DATA_LSB                  0
+#define FRC2_CTRL_DATA_MASK              0x000000ff
+                                           
+//clear interrupt when write this address  
+#define FRC2_INT_ADDRESS                      (PERIPHS_TIMER_BASEDDR +0x2c)
+#define FRC2_INT_CLR_MSB                      0
+#define FRC2_INT_CLR_LSB                       0
+#define FRC2_INT_CLR_MASK                   0x00000001
+
+//set Alarm_value for timer2 to generate interrupt
+#define FRC2_ALARM_ADDRESS               (PERIPHS_TIMER_BASEDDR +0x30)
+#define FRC2_ALARM_DATA_MSB            31
+#define FRC2_ALARM_DATA_LSB             0
+#define FRC2_ALARM_DATA_MASK         0xffffffff
+// }}
+
+#define SPI_ENCRYPT_CNTL (PERIPHS_SPI_ENCRYPT_BASEADDR + 0x20)
+#define SPI_ENCRYPT_CNTL_ENA				BIT(0)
+
+#define SPI_ENCRYPT_ADDR (PERIPHS_SPI_ENCRYPT_BASEADDR + 0x24)
+
+#define SPI_ENCRYPT_CHECKDONE (PERIPHS_SPI_ENCRYPT_BASEADDR + 0x28)
+#define SPI_ENCRYPT_CHECKDONE_STATUS                       BIT(0)
+
+#endif /* _ESP32_SOC_H_ */

components/esp32/include/soc/spi_register.h

@@ -0,0 +1,399 @@
+// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef _SOC_SPI_REG_H_
+#define _SOC_SPI_REG_H_
+
+#include "soc.h"
+
+#define SPI_CMD( i )                            (REG_SPI_BASE( i ) + 0x0)
+#define SPI_FLASH_READ (BIT(31))
+#define SPI_FLASH_WREN (BIT(30))
+#define SPI_FLASH_WRDI (BIT(29))
+#define SPI_FLASH_RDID (BIT(28))
+#define SPI_FLASH_RDSR (BIT(27))
+#define SPI_FLASH_WRSR (BIT(26))
+#define SPI_FLASH_PP (BIT(25))
+#define SPI_FLASH_SE (BIT(24))
+#define SPI_FLASH_BE (BIT(23))
+#define SPI_FLASH_CE (BIT(22))
+#define SPI_FLASH_DP (BIT(21))
+#define SPI_FLASH_RES (BIT(20))
+#define SPI_FLASH_HPM (BIT(19))
+#define SPI_USR (BIT(18))
+#define SPI_FLASH_PES (BIT(17))
+#define SPI_FLASH_PER (BIT(16))
+#define SPI_ADDR( i )                           (REG_SPI_BASE( i ) + 0x4)
+#define SPI_CTRL( i )                           (REG_SPI_BASE( i ) + 0x8)
+#define SPI_WR_BIT_ORDER (BIT(26))
+#define SPI_RD_BIT_ORDER (BIT(25))
+#define SPI_FREAD_QIO (BIT(24))
+#define SPI_FREAD_DIO (BIT(23))
+#define SPI_WRSR_2B (BIT(22))
+#define SPI_WP_REG (BIT(21))
+#define SPI_FREAD_QUAD (BIT(20))
+#define SPI_RESANDRES (BIT(15))
+#define SPI_FREAD_DUAL (BIT(14))
+#define SPI_FASTRD_MODE (BIT(13))
+#define SPI_WAIT_FLASH_IDLE_EN (BIT(12))
+#define SPI_TX_CRC_EN (BIT(11))
+#define SPI_FCS_CRC_EN (BIT(10))
+#define SPI_CTRL1( i )                          (REG_SPI_BASE( i ) + 0xC)
+#define SPI_CS_HOLD_DELAY 0x0000000F
+#define SPI_CS_HOLD_DELAY_S 28
+#define SPI_CS_HOLD_DELAY_RES 0x00000FFF
+#define SPI_CS_HOLD_DELAY_RES_S 16
+#define SPI_RD_STATUS( i )                      (REG_SPI_BASE( i ) + 0x10)
+#define SPI_STATUS_EXT 0x000000FF
+#define SPI_STATUS_EXT_S 24
+#define SPI_WB_MODE 0x000000FF
+#define SPI_WB_MODE_S 16
+#define SPI_STATUS 0x0000FFFF
+#define SPI_STATUS_S 0
+
+#define SPI_CTRL2( i )                          (REG_SPI_BASE( i ) + 0x14)
+#define SPI_CS_DELAY_NUM 0x0000000F
+#define SPI_CS_DELAY_NUM_S 28
+#define SPI_CS_DELAY_MODE 0x00000003
+#define SPI_CS_DELAY_MODE_S 26
+#define SPI_MOSI_DELAY_NUM 0x00000007
+#define SPI_MOSI_DELAY_NUM_S 23
+#define SPI_MOSI_DELAY_MODE 0x00000003
+#define SPI_MOSI_DELAY_MODE_S 21
+#define SPI_MISO_DELAY_NUM 0x00000007
+#define SPI_MISO_DELAY_NUM_S 18
+#define SPI_MISO_DELAY_MODE 0x00000003
+#define SPI_MISO_DELAY_MODE_S 16
+#define SPI_CK_OUT_HIGH_MODE 0x0000000F
+#define SPI_CK_OUT_HIGH_MODE_S 12
+#define SPI_CK_OUT_LOW_MODE 0x0000000F
+#define SPI_CK_OUT_LOW_MODE_S 8
+#define SPI_HOLD_TIME 0x0000000F
+#define SPI_HOLD_TIME_S 4
+#define SPI_SETUP_TIME 0x0000000F
+#define SPI_SETUP_TIME_S 0
+
+#define SPI_CLOCK( i )                          (REG_SPI_BASE( i ) + 0x18)
+#define SPI_CLK_EQU_SYSCLK (BIT(31))
+#define SPI_CLKDIV_PRE 0x00001FFF
+#define SPI_CLKDIV_PRE_S 18
+#define SPI_CLKCNT_N 0x0000003F
+#define SPI_CLKCNT_N_S 12
+#define SPI_CLKCNT_H 0x0000003F
+#define SPI_CLKCNT_H_S 6
+#define SPI_CLKCNT_L 0x0000003F
+#define SPI_CLKCNT_L_S 0
+
+#define SPI_USER( i )                           (REG_SPI_BASE( i ) + 0x1C)
+#define SPI_USR_COMMAND (BIT(31))
+#define SPI_USR_ADDR (BIT(30))
+#define SPI_USR_DUMMY (BIT(29))
+#define SPI_USR_MISO (BIT(28))
+#define SPI_USR_MOSI (BIT(27))
+#define SPI_USR_DUMMY_IDLE (BIT(26))
+#define SPI_USR_MOSI_HIGHPART (BIT(25))
+#define SPI_USR_MISO_HIGHPART (BIT(24))
+#define SPI_USR_PREP_HOLD (BIT(23))
+#define SPI_USR_CMD_HOLD (BIT(22))
+#define SPI_USR_ADDR_HOLD (BIT(21))
+#define SPI_USR_DUMMY_HOLD (BIT(20))
+#define SPI_USR_DIN_HOLD (BIT(19))
+#define SPI_USR_DOUT_HOLD (BIT(18))
+#define SPI_USR_HOLD_POL (BIT(17))
+#define SPI_SIO (BIT(16))
+#define SPI_FWRITE_QIO (BIT(15))
+#define SPI_FWRITE_DIO (BIT(14))
+#define SPI_FWRITE_QUAD (BIT(13))
+#define SPI_FWRITE_DUAL (BIT(12))
+#define SPI_WR_BYTE_ORDER (BIT(11))
+#define SPI_RD_BYTE_ORDER (BIT(10))
+#define SPI_CK_OUT_EDGE (BIT(7))
+#define SPI_CK_I_EDGE (BIT(6))
+#define SPI_CS_SETUP (BIT(5))
+#define SPI_CS_HOLD (BIT(4))
+#define SPI_DOUTDIN (BIT(0))
+
+#define SPI_USER1( i )                          (REG_SPI_BASE( i ) + 0x20)
+#define SPI_USR_ADDR_BITLEN 0x0000003F
+#define SPI_USR_ADDR_BITLEN_S 26
+#define SPI_USR_DUMMY_CYCLELEN 0x000000FF
+#define SPI_USR_DUMMY_CYCLELEN_S 0
+
+#define SPI_USER2( i )                          (REG_SPI_BASE( i ) + 0x24)
+#define SPI_USR_COMMAND_BITLEN 0x0000000F
+#define SPI_USR_COMMAND_BITLEN_S 28
+#define SPI_USR_COMMAND_VALUE 0x0000FFFF
+#define SPI_USR_COMMAND_VALUE_S 0
+
+#define SPI_MOSI_DLEN( i )                      (REG_SPI_BASE( i ) + 0x28)
+#define SPI_USR_MOSI_DBITLEN 0x00FFFFFF
+#define SPI_USR_MOSI_DBITLEN_S 0
+
+#define SPI_MISO_DLEN( i )                      (REG_SPI_BASE( i ) + 0x2C)
+#define SPI_USR_MISO_DBITLEN 0x00FFFFFF
+#define SPI_USR_MISO_DBITLEN_S 0
+
+#define SPI_SLV_WR_STATUS( i )                  (REG_SPI_BASE( i ) + 0x30)
+#define SPI_PIN( i )                            (REG_SPI_BASE( i ) + 0x34)
+#define SPI_CS_KEEP_ACTIVE (BIT(30))
+#define SPI_CK_IDLE_EDGE (BIT(29))
+#define SPI_CSCK_SEL (BIT(19))
+#define SPI_MASTER_CK_SEL 0x0000001F
+#define SPI_MASTER_CK_SEL_S 11
+#define SPI_MASTER_CS_POL 0x0000001F
+#define SPI_MASTER_CS_POL_S 6
+#define SPI_CK_DIS (BIT(5))
+#define SPI_CS2_DIS (BIT(2))
+#define SPI_CS1_DIS (BIT(1))
+#define SPI_CS0_DIS (BIT(0))
+
+#define SPI_SLAVE( i )                          (REG_SPI_BASE( i ) + 0x38)
+#define SPI_SYNC_RESET (BIT(31))
+#define SPI_SLAVE_MODE (BIT(30))
+#define SPI_SLV_WR_RD_BUF_EN (BIT(29))
+#define SPI_SLV_WR_RD_STA_EN (BIT(28))
+#define SPI_SLV_CMD_DEFINE (BIT(27))
+#define SPI_TRANS_CNT 0x0000000F
+#define SPI_TRANS_CNT_S 23
+#define SPI_SLV_LAST_STATE 0x00000007
+#define SPI_SLV_LAST_STATE_S 20
+#define SPI_SLV_LAST_COMMAND 0x00000007
+#define SPI_SLV_LAST_COMMAND_S 17
+#define SPI_CS_I_MODE 0x00000003
+#define SPI_CS_I_MODE_S 10
+#define SPI_INT_EN 0x0000001F
+#define SPI_INT_EN_S 5
+#define SPI_TRANS_DONE (BIT(4))
+#define SPI_SLV_WR_STA_DONE (BIT(3))
+#define SPI_SLV_RD_STA_DONE (BIT(2))
+#define SPI_SLV_WR_BUF_DONE (BIT(1))
+#define SPI_SLV_RD_BUF_DONE (BIT(0))
+
+#define SPI_SLAVE1( i )                         (REG_SPI_BASE( i ) + 0x3C)
+#define SPI_SLV_STATUS_BITLEN 0x0000001F
+#define SPI_SLV_STATUS_BITLEN_S 27
+#define SPI_SLV_STATUS_FAST_EN (BIT(26))
+#define SPI_SLV_STATUS_READBACK (BIT(25))
+#define SPI_SLV_RD_ADDR_BITLEN 0x0000003F
+#define SPI_SLV_RD_ADDR_BITLEN_S 10
+#define SPI_SLV_WR_ADDR_BITLEN 0x0000003F
+#define SPI_SLV_WR_ADDR_BITLEN_S 4
+#define SPI_SLV_WRSTA_DUMMY_EN (BIT(3))
+#define SPI_SLV_RDSTA_DUMMY_EN (BIT(2))
+#define SPI_SLV_WRBUF_DUMMY_EN (BIT(1))
+#define SPI_SLV_RDBUF_DUMMY_EN (BIT(0))
+
+#define SPI_SLAVE2( i )                         (REG_SPI_BASE( i ) + 0x40)
+#define SPI_SLV_WRBUF_DUMMY_CYCLELEN 0x000000FF
+#define SPI_SLV_WRBUF_DUMMY_CYCLELEN_S 24
+#define SPI_SLV_RDBUF_DUMMY_CYCLELEN 0x000000FF
+#define SPI_SLV_RDBUF_DUMMY_CYCLELEN_S 16
+#define SPI_SLV_WRSTA_DUMMY_CYCLELEN 0x000000FF
+#define SPI_SLV_WRSTA_DUMMY_CYCLELEN_S 8
+#define SPI_SLV_RDSTA_DUMMY_CYCLELEN 0x000000FF
+#define SPI_SLV_RDSTA_DUMMY_CYCLELEN_S 0
+
+#define SPI_SLAVE3( i )                         (REG_SPI_BASE( i ) + 0x44)
+#define SPI_SLV_WRSTA_CMD_VALUE 0x000000FF
+#define SPI_SLV_WRSTA_CMD_VALUE_S 24
+#define SPI_SLV_RDSTA_CMD_VALUE 0x000000FF
+#define SPI_SLV_RDSTA_CMD_VALUE_S 16
+#define SPI_SLV_WRBUF_CMD_VALUE 0x000000FF
+#define SPI_SLV_WRBUF_CMD_VALUE_S 8
+#define SPI_SLV_RDBUF_CMD_VALUE 0x000000FF
+#define SPI_SLV_RDBUF_CMD_VALUE_S 0
+
+#define SPI_SLV_WRBUF_DLEN( i )                 (REG_SPI_BASE( i ) + 0x48)
+#define SPI_SLV_WRBUF_DBITLEN 0x00FFFFFF
+#define SPI_SLV_WRBUF_DBITLEN_S 0
+
+#define SPI_SLV_RDBUF_DLEN( i )                 (REG_SPI_BASE( i ) + 0x4C)
+#define SPI_SLV_RDBUF_DBITLEN 0x00FFFFFF
+#define SPI_SLV_RDBUF_DBITLEN_S 0
+
+#define SPI_CACHE_FCTRL( i )                    (REG_SPI_BASE( i ) + 0x50)
+#define SPI_CACHE_FLASH_PES_EN (BIT(3))
+#define SPI_CACHE_FLASH_USR_CMD (BIT(2))
+#define SPI_CACHE_USR_CMD_4BYTE (BIT(1))
+#define SPI_CACHE_REQ_EN (BIT(0))
+
+#define SPI_CACHE_SCTRL( i )                    (REG_SPI_BASE( i ) + 0x54)
+#define SPI_CACHE_SRAM_USR_WCMD (BIT(28))
+#define SPI_SRAM_ADDR_BITLEN 0x0000003F
+#define SPI_SRAM_ADDR_BITLEN_S 22
+#define SPI_SRAM_DUMMY_CYCLELEN 0x000000FF
+#define SPI_SRAM_DUMMY_CYCLELEN_S 14
+#define SPI_SRAM_BYTES_LEN 0x000000FF
+#define SPI_SRAM_BYTES_LEN_S 6
+#define SPI_CACHE_SRAM_USR_RCMD (BIT(5))
+#define SPI_USR_RD_SRAM_DUMMY (BIT(4))
+#define SPI_USR_WR_SRAM_DUMMY (BIT(3))
+#define SPI_USR_SRAM_QIO (BIT(2))
+#define SPI_USR_SRAM_DIO (BIT(1))
+#define SPI_SRAM_CMD( i )                       (REG_SPI_BASE( i ) + 0x58)
+#define SPI_SRAM_RSTIO (BIT(4))
+#define SPI_SRAM_QIO (BIT(1))
+#define SPI_SRAM_DIO (BIT(0))
+
+#define SPI_SRAM_DRD_CMD( i )                   (REG_SPI_BASE( i ) + 0x5C)
+#define SPI_CACHE_SRAM_USR_RD_CMD_BITLEN 0x0000000F
+#define SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_S 28
+#define SPI_CACHE_SRAM_USR_RD_CMD_VALUE 0x0000FFFF
+#define SPI_CACHE_SRAM_USR_RD_CMD_VALUE_S 0
+
+#define SPI_SRAM_DWR_CMD( i )                   (REG_SPI_BASE( i ) + 0x60)
+#define SPI_CACHE_SRAM_USR_WR_CMD_BITLEN 0x0000000F
+#define SPI_CACHE_SRAM_USR_WR_CMD_BITLEN_S 28
+#define SPI_CACHE_SRAM_USR_WR_CMD_VALUE 0x0000FFFF
+#define SPI_CACHE_SRAM_USR_WR_CMD_VALUE_S 0
+
+#define SPI_SLV_RD_BIT( i )                     (REG_SPI_BASE( i ) + 0x64)
+#define SPI_SLV_RDATA_BIT 0x00FFFFFF
+#define SPI_SLV_RDATA_BIT_S 0
+
+#define SPI_W0( i )                             (REG_SPI_BASE( i ) + 0x80)
+#define SPI_W1( i )                             (REG_SPI_BASE( i ) + 0x84)
+#define SPI_W2( i )                             (REG_SPI_BASE( i ) + 0x88)
+#define SPI_W3( i )                             (REG_SPI_BASE( i ) + 0x8C)
+#define SPI_W4( i )                             (REG_SPI_BASE( i ) + 0x90)
+#define SPI_W5( i )                             (REG_SPI_BASE( i ) + 0x94)
+#define SPI_W6( i )                             (REG_SPI_BASE( i ) + 0x98)
+#define SPI_W7( i )                             (REG_SPI_BASE( i ) + 0x9C)
+#define SPI_W8( i )                             (REG_SPI_BASE( i ) + 0xA0)
+#define SPI_W9( i )                             (REG_SPI_BASE( i ) + 0xA4)
+#define SPI_W10( i )                            (REG_SPI_BASE( i ) + 0xA8)
+#define SPI_W11( i )                            (REG_SPI_BASE( i ) + 0xAC)
+#define SPI_W12( i )                            (REG_SPI_BASE( i ) + 0xB0)
+#define SPI_W13( i )                            (REG_SPI_BASE( i ) + 0xB4)
+#define SPI_W14( i )                            (REG_SPI_BASE( i ) + 0xB8)
+#define SPI_W15( i )                            (REG_SPI_BASE( i ) + 0xBC)
+#define SPI_TX_CRC( i )                         (REG_SPI_BASE( i ) + 0xC0)
+#define SPI_EXT0( i )                           (REG_SPI_BASE( i ) + 0xF0)
+#define SPI_T_PP_ENA (BIT(31))
+#define SPI_T_PP_SHIFT 0x0000000F
+#define SPI_T_PP_SHIFT_S 16
+#define SPI_T_PP_TIME 0x00000FFF
+#define SPI_T_PP_TIME_S 0
+
+#define SPI_EXT1( i )                           (REG_SPI_BASE( i ) + 0xF4)
+#define SPI_T_ERASE_ENA (BIT(31))
+#define SPI_T_ERASE_SHIFT 0x0000000F
+#define SPI_T_ERASE_SHIFT_S 16
+#define SPI_T_ERASE_TIME 0x00000FFF
+#define SPI_T_ERASE_TIME_S 0
+
+#define SPI_EXT2( i )                           (REG_SPI_BASE( i ) + 0xF8)
+#define SPI_ST 0x00000007
+#define SPI_ST_S 0
+
+#define SPI_EXT3( i )                           (REG_SPI_BASE( i ) + 0xFC)
+#define SPI_INT_HOLD_ENA 0x00000003
+#define SPI_INT_HOLD_ENA_S 0
+
+#define SPI_DMA_CONF( i )                       (REG_SPI_BASE( i ) + 0x100)
+#define SPI_DMA_CONTINUE (BIT(16))
+#define SPI_DMA_TX_STOP (BIT(15))
+#define SPI_DMA_RX_STOP (BIT(14))
+#define SPI_OUT_DATA_BURST_EN (BIT(12))
+#define SPI_INDSCR_BURST_EN (BIT(11))
+#define SPI_OUTDSCR_BURST_EN (BIT(10))
+#define SPI_OUT_EOF_MODE (BIT(9))
+#define SPI_OUT_AUTO_WRBACK (BIT(8))
+#define SPI_OUT_LOOP_TEST (BIT(7))
+#define SPI_IN_LOOP_TEST (BIT(6))
+#define SPI_AHBM_RST (BIT(5))
+#define SPI_AHBM_FIFO_RST (BIT(4))
+#define SPI_OUT_RST (BIT(3))
+#define SPI_IN_RST (BIT(2))
+#define SPI_DMA_OUT_LINK( i )                   (REG_SPI_BASE( i ) + 0x104)
+#define SPI_OUTLINK_RESTART (BIT(30))
+#define SPI_OUTLINK_START (BIT(29))
+#define SPI_OUTLINK_STOP (BIT(28))
+#define SPI_OUTLINK_ADDR 0x000FFFFF
+#define SPI_OUTLINK_ADDR_S 0
+
+#define SPI_DMA_IN_LINK( i )                    (REG_SPI_BASE( i ) + 0x108)
+#define SPI_INLINK_RESTART (BIT(30))
+#define SPI_INLINK_START (BIT(29))
+#define SPI_INLINK_STOP (BIT(28))
+#define SPI_INLINK_AUTO_RET (BIT(20))
+#define SPI_INLINK_ADDR 0x000FFFFF
+#define SPI_INLINK_ADDR_S 0
+
+#define SPI_DMA_STATUS( i )                     (REG_SPI_BASE( i ) + 0x10C)
+#define SPI_DMA_TX_EN (BIT(1))
+#define SPI_DMA_RX_EN (BIT(0))
+
+#define SPI_DMA_INT_ENA( i )                    (REG_SPI_BASE( i ) + 0x110)
+#define SPI_OUT_TOTAL_EOF_INT_ENA (BIT(8))
+#define SPI_OUT_EOF_INT_ENA (BIT(7))
+#define SPI_OUT_DONE_INT_ENA (BIT(6))
+#define SPI_IN_SUC_EOF_INT_ENA (BIT(5))
+#define SPI_IN_ERR_EOF_INT_ENA (BIT(4))
+#define SPI_IN_DONE_INT_ENA (BIT(3))
+#define SPI_INLINK_DSCR_ERROR_INT_ENA (BIT(2))
+#define SPI_OUTLINK_DSCR_ERROR_INT_ENA (BIT(1))
+#define SPI_INLINK_DSCR_EMPTY_INT_ENA (BIT(0))
+
+#define SPI_DMA_INT_RAW( i )                    (REG_SPI_BASE( i ) + 0x114)
+#define SPI_OUT_TOTAL_EOF_INT_RAW (BIT(8))
+#define SPI_OUT_EOF_INT_RAW (BIT(7))
+#define SPI_OUT_DONE_INT_RAW (BIT(6))
+#define SPI_IN_SUC_EOF_INT_RAW (BIT(5))
+#define SPI_IN_ERR_EOF_INT_RAW (BIT(4))
+#define SPI_IN_DONE_INT_RAW (BIT(3))
+#define SPI_INLINK_DSCR_ERROR_INT_RAW (BIT(2))
+#define SPI_OUTLINK_DSCR_ERROR_INT_RAW (BIT(1))
+#define SPI_INLINK_DSCR_EMPTY_INT_RAW (BIT(0))
+
+#define SPI_DMA_INT_ST( i )                     (REG_SPI_BASE( i ) + 0x118)
+#define SPI_OUT_TOTAL_EOF_INT_ST (BIT(8))
+#define SPI_OUT_EOF_INT_ST (BIT(7))
+#define SPI_OUT_DONE_INT_ST (BIT(6))
+#define SPI_IN_SUC_EOF_INT_ST (BIT(5))
+#define SPI_IN_ERR_EOF_INT_ST (BIT(4))
+#define SPI_IN_DONE_INT_ST (BIT(3))
+#define SPI_INLINK_DSCR_ERROR_INT_ST (BIT(2))
+#define SPI_OUTLINK_DSCR_ERROR_INT_ST (BIT(1))
+#define SPI_INLINK_DSCR_EMPTY_INT_ST (BIT(0))
+
+#define SPI_DMA_INT_CLR( i )                    (REG_SPI_BASE( i ) + 0x11C)
+#define SPI_OUT_TOTAL_EOF_INT_CLR (BIT(8))
+#define SPI_OUT_EOF_INT_CLR (BIT(7))
+#define SPI_OUT_DONE_INT_CLR (BIT(6))
+#define SPI_IN_SUC_EOF_INT_CLR (BIT(5))
+#define SPI_IN_ERR_EOF_INT_CLR (BIT(4))
+#define SPI_IN_DONE_INT_CLR (BIT(3))
+#define SPI_INLINK_DSCR_ERROR_INT_CLR (BIT(2))
+#define SPI_OUTLINK_DSCR_ERROR_INT_CLR (BIT(1))
+#define SPI_INLINK_DSCR_EMPTY_INT_CLR (BIT(0))
+
+#define SPI_IN_ERR_EOF_DES_ADDR( i )            (REG_SPI_BASE( i ) + 0x120)
+#define SPI_IN_SUC_EOF_DES_ADDR( i )            (REG_SPI_BASE( i ) + 0x124)
+#define SPI_INLINK_DSCR( i )                    (REG_SPI_BASE( i ) + 0x128)
+#define SPI_INLINK_DSCR_BF0( i )                (REG_SPI_BASE( i ) + 0x12C)
+#define SPI_INLINK_DSCR_BF1( i )                (REG_SPI_BASE( i ) + 0x130)
+#define SPI_OUT_EOF_BFR_DES_ADDR( i )           (REG_SPI_BASE( i ) + 0x134)
+#define SPI_OUT_EOF_DES_ADDR( i )               (REG_SPI_BASE( i ) + 0x138)
+#define SPI_OUTLINK_DSCR( i )                   (REG_SPI_BASE( i ) + 0x13C)
+#define SPI_OUTLINK_DSCR_BF0( i )               (REG_SPI_BASE( i ) + 0x140)
+#define SPI_OUTLINK_DSCR_BF1( i )               (REG_SPI_BASE( i ) + 0x144)
+#define SPI_DMA_RSTATUS( i )                    (REG_SPI_BASE( i ) + 0x148)
+#define SPI_DMA_TSTATUS( i )                    (REG_SPI_BASE( i ) + 0x14C)
+#define SPI_REG_DATE( i )                       (REG_SPI_BASE( i ) + 0x3FC)
+#define SPI_DATE 0x0FFFFFFF
+#define SPI_DATE_S 0
+#define SPI_DATE_VERSION 0x1604290
+ 
+#endif /* _SOC_SPI_REG_H_ */

components/esp32/include/soc/timers_reg.h

@@ -0,0 +1,288 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_TIMERS_REG_H_
+#define _SOC_TIMER_REG_H_
+
+#include "soc.h"
+
+#define T0CONFIG (DR_REG_TIMERS_BASE + 0x0000)
+#define TIMERS_T0_EN (BIT(31))
+#define TIMERS_T0_EN_S 31
+#define TIMERS_T0_INCREASE (BIT(30))
+#define TIMERS_T0_INCREASE_S 30
+#define TIMERS_T0_AUTORELOAD (BIT(29))
+#define TIMERS_T0_AUTORELOAD_S 29
+#define TIMERS_T0_DIVIDER 0x0000FFFF
+#define TIMERS_T0_DIVIDER_S 13
+#define TIMERS_T0_EDGE_INT_EN (BIT(12))
+#define TIMERS_T0_EDGE_INT_EN_S 12
+#define TIMERS_T0_LEVEL_INT_EN (BIT(11))
+#define TIMERS_T0_LEVEL_INT_EN_S 11
+#define TIMERS_T0_ALARM_EN (BIT(10))
+#define TIMERS_T0_ALARM_EN_S 10
+
+#define T0LO (DR_REG_TIMERS_BASE + 0x0004)
+#define TIMERS_T0_LO 0xFFFFFFFF
+#define TIMERS_T0_LO_S 0
+
+#define T0HI (DR_REG_TIMERS_BASE + 0x0008)
+#define TIMERS_T0_HI 0xFFFFFFFF
+#define TIMERS_T0_HI_S 0
+
+#define T0UPDATE (DR_REG_TIMERS_BASE + 0x000c)
+#define TIMERS_T0_UPDATE 0xFFFFFFFF
+#define TIMERS_T0_UPDATE_S 0
+
+#define T0ALARMLO (DR_REG_TIMERS_BASE + 0x0010)
+#define TIMERS_T0_ALARM_LO 0xFFFFFFFF
+#define TIMERS_T0_ALARM_LO_S 0
+
+#define T0ALARMHI (DR_REG_TIMERS_BASE + 0x0014)
+#define TIMERS_T0_ALARM_HI 0xFFFFFFFF
+#define TIMERS_T0_ALARM_HI_S 0
+
+#define T0LOADLO (DR_REG_TIMERS_BASE + 0x0018)
+#define TIMERS_T0_LOAD_LO 0xFFFFFFFF
+#define TIMERS_T0_LOAD_LO_S 0
+
+#define T0LOADHI (DR_REG_TIMERS_BASE + 0x001c)
+#define TIMERS_T0_LOAD_HI 0xFFFFFFFF
+#define TIMERS_T0_LOAD_HI_S 0
+
+#define T0LOAD (DR_REG_TIMERS_BASE + 0x0020)
+#define TIMERS_T0_LOAD 0xFFFFFFFF
+#define TIMERS_T0_LOAD_S 0
+
+#define T1CONFIG (DR_REG_TIMERS_BASE + 0x0024)
+#define TIMERS_T1_EN (BIT(31))
+#define TIMERS_T1_EN_S 31
+#define TIMERS_T1_INCREASE (BIT(30))
+#define TIMERS_T1_INCREASE_S 30
+#define TIMERS_T1_AUTORELOAD (BIT(29))
+#define TIMERS_T1_AUTORELOAD_S 29
+#define TIMERS_T1_DIVIDER 0x0000FFFF
+#define TIMERS_T1_DIVIDER_S 13
+#define TIMERS_T1_EDGE_INT_EN (BIT(12))
+#define TIMERS_T1_EDGE_INT_EN_S 12
+#define TIMERS_T1_LEVEL_INT_EN (BIT(11))
+#define TIMERS_T1_LEVEL_INT_EN_S 11
+#define TIMERS_T1_ALARM_EN (BIT(10))
+#define TIMERS_T1_ALARM_EN_S 10
+
+#define T1LO (DR_REG_TIMERS_BASE + 0x0028)
+#define TIMERS_T1_LO 0xFFFFFFFF
+#define TIMERS_T1_LO_S 0
+
+#define T1HI (DR_REG_TIMERS_BASE + 0x002c)
+#define TIMERS_T1_HI 0xFFFFFFFF
+#define TIMERS_T1_HI_S 0
+
+#define T1UPDATE (DR_REG_TIMERS_BASE + 0x0030)
+#define TIMERS_T1_UPDATE 0xFFFFFFFF
+#define TIMERS_T1_UPDATE_S 0
+
+#define T1ALARMLO (DR_REG_TIMERS_BASE + 0x0034)
+#define TIMERS_T1_ALARM_LO 0xFFFFFFFF
+#define TIMERS_T1_ALARM_LO_S 0
+
+#define T1ALARMHI (DR_REG_TIMERS_BASE + 0x0038)
+#define TIMERS_T1_ALARM_HI 0xFFFFFFFF
+#define TIMERS_T1_ALARM_HI_S 0
+
+#define T1LOADLO (DR_REG_TIMERS_BASE + 0x003c)
+#define TIMERS_T1_LOAD_LO 0xFFFFFFFF
+#define TIMERS_T1_LOAD_LO_S 0
+
+#define T1LOADHI (DR_REG_TIMERS_BASE + 0x0040)
+#define TIMERS_T1_LOAD_HI 0xFFFFFFFF
+#define TIMERS_T1_LOAD_HI_S 0
+
+#define T1LOAD (DR_REG_TIMERS_BASE + 0x0044)
+#define TIMERS_T1_LOAD 0xFFFFFFFF
+#define TIMERS_T1_LOAD_S 0
+
+#define WDTCONFIG0 (DR_REG_TIMERS_BASE + 0x0048)
+#define TIMERS_WDT_EN (BIT(31))
+#define TIMERS_WDT_EN_S 31
+#define TIMERS_WDT_STG0 0x00000003
+#define TIMERS_WDT_STG0_S 29
+#define TIMERS_WDT_STG1 0x00000003
+#define TIMERS_WDT_STG1_S 27
+#define TIMERS_WDT_STG2 0x00000003
+#define TIMERS_WDT_STG2_S 25
+#define TIMERS_WDT_STG3 0x00000003
+#define TIMERS_WDT_STG3_S 23
+#define TIMERS_WDT_EDGE_INT_EN (BIT(22))
+#define TIMERS_WDT_EDGE_INT_EN_S 22
+#define TIMERS_WDT_LEVEL_INT_EN (BIT(21))
+#define TIMERS_WDT_LEVEL_INT_EN_S 21
+#define TIMERS_WDT_CPU_RESET_LENGTH 0x00000007
+#define TIMERS_WDT_CPU_RESET_LENGTH_S 18
+#define TIMERS_WDT_SYS_RESET_LENGTH 0x00000007
+#define TIMERS_WDT_SYS_RESET_LENGTH_S 15
+#define TIMERS_WDT_FLASHBOOT_MOD_EN (BIT(14))
+#define TIMERS_WDT_FLASHBOOT_MOD_EN_S 14
+
+#define WDTCONFIG1 (DR_REG_TIMERS_BASE + 0x004c)
+#define TIMERS_WDT_CLK_PRESCALE 0x0000FFFF
+#define TIMERS_WDT_CLK_PRESCALE_S 16
+
+#define WDTCONFIG2 (DR_REG_TIMERS_BASE + 0x0050)
+#define TIMERS_WDT_STG0_HOLD 0xFFFFFFFF
+#define TIMERS_WDT_STG0_HOLD_S 0
+
+#define WDTCONFIG3 (DR_REG_TIMERS_BASE + 0x0054)
+#define TIMERS_WDT_STG1_HOLD 0xFFFFFFFF
+#define TIMERS_WDT_STG1_HOLD_S 0
+
+#define WDTCONFIG4 (DR_REG_TIMERS_BASE + 0x0058)
+#define TIMERS_WDT_STG2_HOLD 0xFFFFFFFF
+#define TIMERS_WDT_STG2_HOLD_S 0
+
+#define WDTCONFIG5 (DR_REG_TIMERS_BASE + 0x005c)
+#define TIMERS_WDT_STG3_HOLD 0xFFFFFFFF
+#define TIMERS_WDT_STG3_HOLD_S 0
+
+#define WDTFEED (DR_REG_TIMERS_BASE + 0x0060)
+#define TIMERS_WDT_FEED 0xFFFFFFFF
+#define TIMERS_WDT_FEED_S 0
+
+#define WDTWPROTECT (DR_REG_TIMERS_BASE + 0x0064)
+#define TIMERS_WDT_WKEY 0xFFFFFFFF
+#define TIMERS_WDT_WKEY_S 0
+
+#define RTCCALICFG (DR_REG_TIMERS_BASE + 0x0068)
+#define TIMERS_RTC_CALI_START (BIT(31))
+#define TIMERS_RTC_CALI_START_S 31
+#define TIMERS_RTC_CALI_MAX 0x00007FFF
+#define TIMERS_RTC_CALI_MAX_S 16
+#define TIMERS_RTC_CALI_RDY (BIT(15))
+#define TIMERS_RTC_CALI_RDY_S 15
+#define TIMERS_RTC_CALI_CLK_SEL 0x00000003
+#define TIMERS_RTC_CALI_CLK_SEL_S 13
+#define TIMERS_RTC_CALI_START_CYCLING (BIT(12))
+#define TIMERS_RTC_CALI_START_CYCLING_S 12
+
+#define RTCCALICFG1 (DR_REG_TIMERS_BASE + 0x006c)
+#define TIMERS_RTC_CALI_VALUE 0x01FFFFFF
+#define TIMERS_RTC_CALI_VALUE_S 7
+
+#define LACTCONFIG (DR_REG_TIMERS_BASE + 0x0070)
+#define TIMERS_LACT_EN (BIT(31))
+#define TIMERS_LACT_EN_S 31
+#define TIMERS_LACT_INCREASE (BIT(30))
+#define TIMERS_LACT_INCREASE_S 30
+#define TIMERS_LACT_AUTORELOAD (BIT(29))
+#define TIMERS_LACT_AUTORELOAD_S 29
+#define TIMERS_LACT_DIVIDER 0x0000FFFF
+#define TIMERS_LACT_DIVIDER_S 13
+#define TIMERS_LACT_EDGE_INT_EN (BIT(12))
+#define TIMERS_LACT_EDGE_INT_EN_S 12
+#define TIMERS_LACT_LEVEL_INT_EN (BIT(11))
+#define TIMERS_LACT_LEVEL_INT_EN_S 11
+#define TIMERS_LACT_ALARM_EN (BIT(10))
+#define TIMERS_LACT_ALARM_EN_S 10
+#define TIMERS_LACT_LAC_EN (BIT(9))
+#define TIMERS_LACT_LAC_EN_S 9
+#define TIMERS_LACT_CPST_EN (BIT(8))
+#define TIMERS_LACT_CPST_EN_S 8
+#define TIMERS_LACT_RTC_ONLY (BIT(7))
+#define TIMERS_LACT_RTC_ONLY_S 7
+
+#define LACTRTC (DR_REG_TIMERS_BASE + 0x0074)
+#define TIMERS_LACT_RTC_STEP_LEN 0x03FFFFFF
+#define TIMERS_LACT_RTC_STEP_LEN_S 6
+
+#define LACTLO (DR_REG_TIMERS_BASE + 0x0078)
+#define TIMERS_LACT_LO 0xFFFFFFFF
+#define TIMERS_LACT_LO_S 0
+
+#define LACTHI (DR_REG_TIMERS_BASE + 0x007c)
+#define TIMERS_LACT_HI 0xFFFFFFFF
+#define TIMERS_LACT_HI_S 0
+
+#define LACTUPDATE (DR_REG_TIMERS_BASE + 0x0080)
+#define TIMERS_LACT_UPDATE 0xFFFFFFFF
+#define TIMERS_LACT_UPDATE_S 0
+
+#define LACTALARMLO (DR_REG_TIMERS_BASE + 0x0084)
+#define TIMERS_LACT_ALARM_LO 0xFFFFFFFF
+#define TIMERS_LACT_ALARM_LO_S 0
+
+#define LACTALARMHI (DR_REG_TIMERS_BASE + 0x0088)
+#define TIMERS_LACT_ALARM_HI 0xFFFFFFFF
+#define TIMERS_LACT_ALARM_HI_S 0
+
+#define LACTLOADLO (DR_REG_TIMERS_BASE + 0x008c)
+#define TIMERS_LACT_LOAD_LO 0xFFFFFFFF
+#define TIMERS_LACT_LOAD_LO_S 0
+
+#define LACTLOADHI (DR_REG_TIMERS_BASE + 0x0090)
+#define TIMERS_LACT_LOAD_HI 0xFFFFFFFF
+#define TIMERS_LACT_LOAD_HI_S 0
+
+#define LACTLOAD (DR_REG_TIMERS_BASE + 0x0094)
+#define TIMERS_LACT_LOAD 0xFFFFFFFF
+#define TIMERS_LACT_LOAD_S 0
+
+#define INT_ENA_TIMERS (DR_REG_TIMERS_BASE + 0x0098)
+#define TIMERS_LACT_INT_ENA (BIT(3))
+#define TIMERS_LACT_INT_ENA_S 3
+#define TIMERS_WDT_INT_ENA (BIT(2))
+#define TIMERS_WDT_INT_ENA_S 2
+#define TIMERS_T1_INT_ENA (BIT(1))
+#define TIMERS_T1_INT_ENA_S 1
+#define TIMERS_T0_INT_ENA (BIT(0))
+#define TIMERS_T0_INT_ENA_S 0
+
+#define INT_RAW_TIMERS (DR_REG_TIMERS_BASE + 0x009c)
+#define TIMERS_LACT_INT_RAW (BIT(3))
+#define TIMERS_LACT_INT_RAW_S 3
+#define TIMERS_WDT_INT_RAW (BIT(2))
+#define TIMERS_WDT_INT_RAW_S 2
+#define TIMERS_T1_INT_RAW (BIT(1))
+#define TIMERS_T1_INT_RAW_S 1
+#define TIMERS_T0_INT_RAW (BIT(0))
+#define TIMERS_T0_INT_RAW_S 0
+
+#define INT_ST_TIMERS (DR_REG_TIMERS_BASE + 0x00a0)
+#define TIMERS_LACT_INT_ST (BIT(3))
+#define TIMERS_LACT_INT_ST_S 3
+#define TIMERS_WDT_INT_ST (BIT(2))
+#define TIMERS_WDT_INT_ST_S 2
+#define TIMERS_T1_INT_ST (BIT(1))
+#define TIMERS_T1_INT_ST_S 1
+#define TIMERS_T0_INT_ST (BIT(0))
+#define TIMERS_T0_INT_ST_S 0
+
+#define INT_CLR_TIMERS (DR_REG_TIMERS_BASE + 0x00a4)
+#define TIMERS_LACT_INT_CLR (BIT(3))
+#define TIMERS_LACT_INT_CLR_S 3
+#define TIMERS_WDT_INT_CLR (BIT(2))
+#define TIMERS_WDT_INT_CLR_S 2
+#define TIMERS_T1_INT_CLR (BIT(1))
+#define TIMERS_T1_INT_CLR_S 1
+#define TIMERS_T0_INT_CLR (BIT(0))
+#define TIMERS_T0_INT_CLR_S 0
+
+#define NTIMERS_DATE (DR_REG_TIMERS_BASE + 0x00f8)
+#define TIMERS_NTIMERS_DATE 0x0FFFFFFF
+#define TIMERS_NTIMERS_DATE_S 0
+#define TIMERS_NTIMERS_DATE_VERSION 0x1604290
+
+#define REGCLK (DR_REG_TIMERS_BASE + 0x00fc)
+#define TIMERS_CLK_EN (BIT(31))
+#define TIMERS_CLK_EN_S 31
+
+#endif /* _SOC_TIMER_REG_H_ */

components/esp32/include/soc/uart_register.h

@@ -0,0 +1,1399 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_UART_REG_H_
+#define _SOC_UART_REG_H_
+
+#include "soc.h"
+
+//Slow bus
+//#define REG_UART_BASE( i )  (0x60000000+(i)*0x10000)
+//Fast bus
+#define REG_UART_BASE( i )  (0x3ff40000+(i)*0x10000)
+
+#define UART_FIFO_REG(i)          (REG_UART_BASE(i) + 0x0)
+    /* UART_RXFIFO_RD_BYTE : RO ;bitpos:[7:0] ;default: 8'b0 ; */
+    /*description: R/W share the same address*/
+    #define UART_RXFIFO_RD_BYTE  0x000000FF
+    #define UART_RXFIFO_RD_BYTE_M  ((UART_RXFIFO_RD_BYTE_V)<<(UART_RXFIFO_RD_BYTE_S))
+    #define UART_RXFIFO_RD_BYTE_V  0xFF
+    #define UART_RXFIFO_RD_BYTE_S  0
+        #define UART_GET_RXFIFO_RD_BYTE(i)  GET_PERI_REG_BITS2(UART_FIFO_REG(i) , UART_RXFIFO_RD_BYTE_V, UART_RXFIFO_RD_BYTE_S)
+		#define UART_SET_TXFIFO_WR_BYTE(i,val)  SET_PERI_REG_BITS(UART_FIFO_REG(i) , UART_RXFIFO_RD_BYTE_V, val, UART_RXFIFO_RD_BYTE_S)
+
+
+
+#define UART_INT_RAW_REG(i)          (REG_UART_BASE(i) + 0x4)
+    /* UART_AT_CMD_CHAR_DET_INT_RAW : RO ;bitpos:[18] ;default: 1'b0 ; */
+    /*description: The interrupt raw bit for detecting AT_CMD char interrupt*/
+    #define UART_AT_CMD_CHAR_DET_INT_RAW  (BIT(18))
+    #define UART_AT_CMD_CHAR_DET_INT_RAW_M  (BIT(18))
+    #define UART_AT_CMD_CHAR_DET_INT_RAW_V  0x1
+    #define UART_AT_CMD_CHAR_DET_INT_RAW_S  18
+    /* UART_RS485_CLASH_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */
+    /*description: The interrupt raw bit for rs485 tx rx clash interrrupt*/
+    #define UART_RS485_CLASH_INT_RAW  (BIT(17))
+    #define UART_RS485_CLASH_INT_RAW_M  (BIT(17))
+    #define UART_RS485_CLASH_INT_RAW_V  0x1
+    #define UART_RS485_CLASH_INT_RAW_S  17
+    /* UART_RS485_FRM_ERR_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */
+    /*description: The interrupt raw bit for rs485 other rx error*/
+    #define UART_RS485_FRM_ERR_INT_RAW  (BIT(16))
+    #define UART_RS485_FRM_ERR_INT_RAW_M  (BIT(16))
+    #define UART_RS485_FRM_ERR_INT_RAW_V  0x1
+    #define UART_RS485_FRM_ERR_INT_RAW_S  16
+    /* UART_RS485_PARITY_ERR_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */
+    /*description: The interrupt raw bit for rs485 parity error*/
+    #define UART_RS485_PARITY_ERR_INT_RAW  (BIT(15))
+    #define UART_RS485_PARITY_ERR_INT_RAW_M  (BIT(15))
+    #define UART_RS485_PARITY_ERR_INT_RAW_V  0x1
+    #define UART_RS485_PARITY_ERR_INT_RAW_S  15
+    /* UART_TX_DONE_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */
+    /*description: The interrupt raw bit for tx done*/
+    #define UART_TX_DONE_INT_RAW  (BIT(14))
+    #define UART_TX_DONE_INT_RAW_M  (BIT(14))
+    #define UART_TX_DONE_INT_RAW_V  0x1
+    #define UART_TX_DONE_INT_RAW_S  14
+    /* UART_TX_BRK_IDLE_DONE_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */
+    /*description: The interrupt raw bit for tx send idle done(depends on the uart_tx_idle_num)*/
+    #define UART_TX_BRK_IDLE_DONE_INT_RAW  (BIT(13))
+    #define UART_TX_BRK_IDLE_DONE_INT_RAW_M  (BIT(13))
+    #define UART_TX_BRK_IDLE_DONE_INT_RAW_V  0x1
+    #define UART_TX_BRK_IDLE_DONE_INT_RAW_S  13
+    /* UART_TX_BRK_DONE_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */
+    /*description: The interrupt raw bit for send 0 done(depends on uart_tx_brk_num)*/
+    #define UART_TX_BRK_DONE_INT_RAW  (BIT(12))
+    #define UART_TX_BRK_DONE_INT_RAW_M  (BIT(12))
+    #define UART_TX_BRK_DONE_INT_RAW_V  0x1
+    #define UART_TX_BRK_DONE_INT_RAW_S  12
+    /* UART_GLITCH_DET_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */
+    /*description: The interrupt raw bit for detecting rx glitch pulse*/
+    #define UART_GLITCH_DET_INT_RAW  (BIT(11))
+    #define UART_GLITCH_DET_INT_RAW_M  (BIT(11))
+    #define UART_GLITCH_DET_INT_RAW_V  0x1
+    #define UART_GLITCH_DET_INT_RAW_S  11
+    /* UART_SW_XOFF_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */
+    /*description: The interrupt raw bit for rx receive xoff char(depends on the uart_xoff_char )*/
+    #define UART_SW_XOFF_INT_RAW  (BIT(10))
+    #define UART_SW_XOFF_INT_RAW_M  (BIT(10))
+    #define UART_SW_XOFF_INT_RAW_V  0x1
+    #define UART_SW_XOFF_INT_RAW_S  10
+    /* UART_SW_XON_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */
+    /*description: The interrupt raw bit for rx receive xon char(depends on the uart_xon_char )*/
+    #define UART_SW_XON_INT_RAW  (BIT(9))
+    #define UART_SW_XON_INT_RAW_M  (BIT(9))
+    #define UART_SW_XON_INT_RAW_V  0x1
+    #define UART_SW_XON_INT_RAW_S  9
+    /* UART_RXFIFO_TOUT_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */
+    /*description: The interrupt raw bit for Rx time-out interrupt(depands on the UART_RX_TOUT_THRHD)*/
+    #define UART_RXFIFO_TOUT_INT_RAW  (BIT(8))
+    #define UART_RXFIFO_TOUT_INT_RAW_M  (BIT(8))
+    #define UART_RXFIFO_TOUT_INT_RAW_V  0x1
+    #define UART_RXFIFO_TOUT_INT_RAW_S  8
+    /* UART_BRK_DET_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */
+    /*description: The interrupt raw bit for Rx byte start error*/
+    #define UART_BRK_DET_INT_RAW  (BIT(7))
+    #define UART_BRK_DET_INT_RAW_M  (BIT(7))
+    #define UART_BRK_DET_INT_RAW_V  0x1
+    #define UART_BRK_DET_INT_RAW_S  7
+    /* UART_CTS_CHG_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */
+    /*description: The interrupt raw bit for CTS changing level*/
+    #define UART_CTS_CHG_INT_RAW  (BIT(6))
+    #define UART_CTS_CHG_INT_RAW_M  (BIT(6))
+    #define UART_CTS_CHG_INT_RAW_V  0x1
+    #define UART_CTS_CHG_INT_RAW_S  6
+    /* UART_DSR_CHG_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */
+    /*description: The interrupt raw bit for DSR changing level*/
+    #define UART_DSR_CHG_INT_RAW  (BIT(5))
+    #define UART_DSR_CHG_INT_RAW_M  (BIT(5))
+    #define UART_DSR_CHG_INT_RAW_V  0x1
+    #define UART_DSR_CHG_INT_RAW_S  5
+    /* UART_RXFIFO_OVF_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */
+    /*description: The interrupt raw bit for rx fifo overflow*/
+    #define UART_RXFIFO_OVF_INT_RAW  (BIT(4))
+    #define UART_RXFIFO_OVF_INT_RAW_M  (BIT(4))
+    #define UART_RXFIFO_OVF_INT_RAW_V  0x1
+    #define UART_RXFIFO_OVF_INT_RAW_S  4
+    /* UART_FRM_ERR_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
+    /*description: The interrupt raw bit for other rx error*/
+    #define UART_FRM_ERR_INT_RAW  (BIT(3))
+    #define UART_FRM_ERR_INT_RAW_M  (BIT(3))
+    #define UART_FRM_ERR_INT_RAW_V  0x1
+    #define UART_FRM_ERR_INT_RAW_S  3
+    /* UART_PARITY_ERR_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
+    /*description: The interrupt raw bit for parity check error*/
+    #define UART_PARITY_ERR_INT_RAW  (BIT(2))
+    #define UART_PARITY_ERR_INT_RAW_M  (BIT(2))
+    #define UART_PARITY_ERR_INT_RAW_V  0x1
+    #define UART_PARITY_ERR_INT_RAW_S  2
+    /* UART_TXFIFO_EMPTY_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
+    /*description: The interrupt raw bit for tx fifo empty interrupt(depands on UART_TXFIFO_EMPTY_THRHD bits)*/
+    #define UART_TXFIFO_EMPTY_INT_RAW  (BIT(1))
+    #define UART_TXFIFO_EMPTY_INT_RAW_M  (BIT(1))
+    #define UART_TXFIFO_EMPTY_INT_RAW_V  0x1
+    #define UART_TXFIFO_EMPTY_INT_RAW_S  1
+    /* UART_RXFIFO_FULL_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
+    /*description: The interrupt raw bit for rx fifo full interrupt(depands on UART_RXFIFO_FULL_THRHD bits)*/
+    #define UART_RXFIFO_FULL_INT_RAW  (BIT(0))
+    #define UART_RXFIFO_FULL_INT_RAW_M  (BIT(0))
+    #define UART_RXFIFO_FULL_INT_RAW_V  0x1
+    #define UART_RXFIFO_FULL_INT_RAW_S  0
+        #define UART_GET_AT_CMD_CHAR_DET_INT_RAW(i)  GET_PERI_REG_BITS2(UART_INT_RAW_REG(i) , UART_AT_CMD_CHAR_DET_INT_RAW_V, UART_AT_CMD_CHAR_DET_INT_RAW_S)
+        #define UART_GET_RS485_CLASH_INT_RAW(i)  GET_PERI_REG_BITS2(UART_INT_RAW_REG(i) , UART_RS485_CLASH_INT_RAW_V, UART_RS485_CLASH_INT_RAW_S)
+        #define UART_GET_RS485_FRM_ERR_INT_RAW(i)  GET_PERI_REG_BITS2(UART_INT_RAW_REG(i) , UART_RS485_FRM_ERR_INT_RAW_V, UART_RS485_FRM_ERR_INT_RAW_S)
+        #define UART_GET_RS485_PARITY_ERR_INT_RAW(i)  GET_PERI_REG_BITS2(UART_INT_RAW_REG(i) , UART_RS485_PARITY_ERR_INT_RAW_V, UART_RS485_PARITY_ERR_INT_RAW_S)
+        #define UART_GET_TX_DONE_INT_RAW(i)  GET_PERI_REG_BITS2(UART_INT_RAW_REG(i) , UART_TX_DONE_INT_RAW_V, UART_TX_DONE_INT_RAW_S)
+        #define UART_GET_TX_BRK_IDLE_DONE_INT_RAW(i)  GET_PERI_REG_BITS2(UART_INT_RAW_REG(i) , UART_TX_BRK_IDLE_DONE_INT_RAW_V, UART_TX_BRK_IDLE_DONE_INT_RAW_S)
+        #define UART_GET_TX_BRK_DONE_INT_RAW(i)  GET_PERI_REG_BITS2(UART_INT_RAW_REG(i) , UART_TX_BRK_DONE_INT_RAW_V, UART_TX_BRK_DONE_INT_RAW_S)
+        #define UART_GET_GLITCH_DET_INT_RAW(i)  GET_PERI_REG_BITS2(UART_INT_RAW_REG(i) , UART_GLITCH_DET_INT_RAW_V, UART_GLITCH_DET_INT_RAW_S)
+        #define UART_GET_SW_XOFF_INT_RAW(i)  GET_PERI_REG_BITS2(UART_INT_RAW_REG(i) , UART_SW_XOFF_INT_RAW_V, UART_SW_XOFF_INT_RAW_S)
+        #define UART_GET_SW_XON_INT_RAW(i)  GET_PERI_REG_BITS2(UART_INT_RAW_REG(i) , UART_SW_XON_INT_RAW_V, UART_SW_XON_INT_RAW_S)
+        #define UART_GET_RXFIFO_TOUT_INT_RAW(i)  GET_PERI_REG_BITS2(UART_INT_RAW_REG(i) , UART_RXFIFO_TOUT_INT_RAW_V, UART_RXFIFO_TOUT_INT_RAW_S)
+        #define UART_GET_BRK_DET_INT_RAW(i)  GET_PERI_REG_BITS2(UART_INT_RAW_REG(i) , UART_BRK_DET_INT_RAW_V, UART_BRK_DET_INT_RAW_S)
+        #define UART_GET_CTS_CHG_INT_RAW(i)  GET_PERI_REG_BITS2(UART_INT_RAW_REG(i) , UART_CTS_CHG_INT_RAW_V, UART_CTS_CHG_INT_RAW_S)
+        #define UART_GET_DSR_CHG_INT_RAW(i)  GET_PERI_REG_BITS2(UART_INT_RAW_REG(i) , UART_DSR_CHG_INT_RAW_V, UART_DSR_CHG_INT_RAW_S)
+        #define UART_GET_RXFIFO_OVF_INT_RAW(i)  GET_PERI_REG_BITS2(UART_INT_RAW_REG(i) , UART_RXFIFO_OVF_INT_RAW_V, UART_RXFIFO_OVF_INT_RAW_S)
+        #define UART_GET_FRM_ERR_INT_RAW(i)  GET_PERI_REG_BITS2(UART_INT_RAW_REG(i) , UART_FRM_ERR_INT_RAW_V, UART_FRM_ERR_INT_RAW_S)
+        #define UART_GET_PARITY_ERR_INT_RAW(i)  GET_PERI_REG_BITS2(UART_INT_RAW_REG(i) , UART_PARITY_ERR_INT_RAW_V, UART_PARITY_ERR_INT_RAW_S)
+        #define UART_GET_TXFIFO_EMPTY_INT_RAW(i)  GET_PERI_REG_BITS2(UART_INT_RAW_REG(i) , UART_TXFIFO_EMPTY_INT_RAW_V, UART_TXFIFO_EMPTY_INT_RAW_S)
+        #define UART_GET_RXFIFO_FULL_INT_RAW(i)  GET_PERI_REG_BITS2(UART_INT_RAW_REG(i) , UART_RXFIFO_FULL_INT_RAW_V, UART_RXFIFO_FULL_INT_RAW_S)
+
+
+
+#define UART_INT_ST_REG(i)          (REG_UART_BASE(i) + 0x8)
+    /* UART_AT_CMD_CHAR_DET_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */
+    /*description: The interrupt state bit for detecting AT_CMD char interrupt*/
+    #define UART_AT_CMD_CHAR_DET_INT_ST  (BIT(18))
+    #define UART_AT_CMD_CHAR_DET_INT_ST_M  (BIT(18))
+    #define UART_AT_CMD_CHAR_DET_INT_ST_V  0x1
+    #define UART_AT_CMD_CHAR_DET_INT_ST_S  18
+    /* UART_RS485_CLASH_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */
+    /*description: The interrupt state bit for rs485 tx rx clash interrrupt*/
+    #define UART_RS485_CLASH_INT_ST  (BIT(17))
+    #define UART_RS485_CLASH_INT_ST_M  (BIT(17))
+    #define UART_RS485_CLASH_INT_ST_V  0x1
+    #define UART_RS485_CLASH_INT_ST_S  17
+    /* UART_RS485_FRM_ERR_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */
+    /*description: The interrupt state bit for rs485 other rx error*/
+    #define UART_RS485_FRM_ERR_INT_ST  (BIT(16))
+    #define UART_RS485_FRM_ERR_INT_ST_M  (BIT(16))
+    #define UART_RS485_FRM_ERR_INT_ST_V  0x1
+    #define UART_RS485_FRM_ERR_INT_ST_S  16
+    /* UART_RS485_PARITY_ERR_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */
+    /*description: The interrupt state bit for rs485 parity error*/
+    #define UART_RS485_PARITY_ERR_INT_ST  (BIT(15))
+    #define UART_RS485_PARITY_ERR_INT_ST_M  (BIT(15))
+    #define UART_RS485_PARITY_ERR_INT_ST_V  0x1
+    #define UART_RS485_PARITY_ERR_INT_ST_S  15
+    /* UART_TX_DONE_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */
+    /*description: The interrupt state bit for tx done event*/
+    #define UART_TX_DONE_INT_ST  (BIT(14))
+    #define UART_TX_DONE_INT_ST_M  (BIT(14))
+    #define UART_TX_DONE_INT_ST_V  0x1
+    #define UART_TX_DONE_INT_ST_S  14
+    /* UART_TX_BRK_IDLE_DONE_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */
+    /*description: The interrupt state bit for tx send idle done event*/
+    #define UART_TX_BRK_IDLE_DONE_INT_ST  (BIT(13))
+    #define UART_TX_BRK_IDLE_DONE_INT_ST_M  (BIT(13))
+    #define UART_TX_BRK_IDLE_DONE_INT_ST_V  0x1
+    #define UART_TX_BRK_IDLE_DONE_INT_ST_S  13
+    /* UART_TX_BRK_DONE_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */
+    /*description: The interrupt state bit for send 0 done event*/
+    #define UART_TX_BRK_DONE_INT_ST  (BIT(12))
+    #define UART_TX_BRK_DONE_INT_ST_M  (BIT(12))
+    #define UART_TX_BRK_DONE_INT_ST_V  0x1
+    #define UART_TX_BRK_DONE_INT_ST_S  12
+    /* UART_GLITCH_DET_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
+    /*description: The interrupt state bit for detecting rx glitch pulse event*/
+    #define UART_GLITCH_DET_INT_ST  (BIT(11))
+    #define UART_GLITCH_DET_INT_ST_M  (BIT(11))
+    #define UART_GLITCH_DET_INT_ST_V  0x1
+    #define UART_GLITCH_DET_INT_ST_S  11
+    /* UART_SW_XOFF_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
+    /*description: The interrupt state bit for rx receive xoff char event*/
+    #define UART_SW_XOFF_INT_ST  (BIT(10))
+    #define UART_SW_XOFF_INT_ST_M  (BIT(10))
+    #define UART_SW_XOFF_INT_ST_V  0x1
+    #define UART_SW_XOFF_INT_ST_S  10
+    /* UART_SW_XON_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
+    /*description: The interrupt state bit for rx receive xon char event*/
+    #define UART_SW_XON_INT_ST  (BIT(9))
+    #define UART_SW_XON_INT_ST_M  (BIT(9))
+    #define UART_SW_XON_INT_ST_V  0x1
+    #define UART_SW_XON_INT_ST_S  9
+    /* UART_RXFIFO_TOUT_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
+    /*description: The interrupt state bit for Rx time-out event*/
+    #define UART_RXFIFO_TOUT_INT_ST  (BIT(8))
+    #define UART_RXFIFO_TOUT_INT_ST_M  (BIT(8))
+    #define UART_RXFIFO_TOUT_INT_ST_V  0x1
+    #define UART_RXFIFO_TOUT_INT_ST_S  8
+    /* UART_BRK_DET_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
+    /*description: The interrupt state bit for rx byte start error*/
+    #define UART_BRK_DET_INT_ST  (BIT(7))
+    #define UART_BRK_DET_INT_ST_M  (BIT(7))
+    #define UART_BRK_DET_INT_ST_V  0x1
+    #define UART_BRK_DET_INT_ST_S  7
+    /* UART_CTS_CHG_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
+    /*description: The interrupt state bit for CTS changing level*/
+    #define UART_CTS_CHG_INT_ST  (BIT(6))
+    #define UART_CTS_CHG_INT_ST_M  (BIT(6))
+    #define UART_CTS_CHG_INT_ST_V  0x1
+    #define UART_CTS_CHG_INT_ST_S  6
+    /* UART_DSR_CHG_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
+    /*description: The interrupt state bit for DSR changing level*/
+    #define UART_DSR_CHG_INT_ST  (BIT(5))
+    #define UART_DSR_CHG_INT_ST_M  (BIT(5))
+    #define UART_DSR_CHG_INT_ST_V  0x1
+    #define UART_DSR_CHG_INT_ST_S  5
+    /* UART_RXFIFO_OVF_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
+    /*description: The interrupt state bit for RX fifo overflow*/
+    #define UART_RXFIFO_OVF_INT_ST  (BIT(4))
+    #define UART_RXFIFO_OVF_INT_ST_M  (BIT(4))
+    #define UART_RXFIFO_OVF_INT_ST_V  0x1
+    #define UART_RXFIFO_OVF_INT_ST_S  4
+    /* UART_FRM_ERR_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
+    /*description: The interrupt state for other rx error*/
+    #define UART_FRM_ERR_INT_ST  (BIT(3))
+    #define UART_FRM_ERR_INT_ST_M  (BIT(3))
+    #define UART_FRM_ERR_INT_ST_V  0x1
+    #define UART_FRM_ERR_INT_ST_S  3
+    /* UART_PARITY_ERR_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
+    /*description: The interrupt state bit for rx parity error*/
+    #define UART_PARITY_ERR_INT_ST  (BIT(2))
+    #define UART_PARITY_ERR_INT_ST_M  (BIT(2))
+    #define UART_PARITY_ERR_INT_ST_V  0x1
+    #define UART_PARITY_ERR_INT_ST_S  2
+    /* UART_TXFIFO_EMPTY_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
+    /*description: The interrupt state bit for TX fifo empty*/
+    #define UART_TXFIFO_EMPTY_INT_ST  (BIT(1))
+    #define UART_TXFIFO_EMPTY_INT_ST_M  (BIT(1))
+    #define UART_TXFIFO_EMPTY_INT_ST_V  0x1
+    #define UART_TXFIFO_EMPTY_INT_ST_S  1
+    /* UART_RXFIFO_FULL_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+    /*description: The interrupt state bit for RX fifo full event*/
+    #define UART_RXFIFO_FULL_INT_ST  (BIT(0))
+    #define UART_RXFIFO_FULL_INT_ST_M  (BIT(0))
+    #define UART_RXFIFO_FULL_INT_ST_V  0x1
+    #define UART_RXFIFO_FULL_INT_ST_S  0
+        #define UART_GET_AT_CMD_CHAR_DET_INT_ST(i)  GET_PERI_REG_BITS2(UART_INT_ST_REG(i) , UART_AT_CMD_CHAR_DET_INT_ST_V, UART_AT_CMD_CHAR_DET_INT_ST_S)
+        #define UART_GET_RS485_CLASH_INT_ST(i)  GET_PERI_REG_BITS2(UART_INT_ST_REG(i) , UART_RS485_CLASH_INT_ST_V, UART_RS485_CLASH_INT_ST_S)
+        #define UART_GET_RS485_FRM_ERR_INT_ST(i)  GET_PERI_REG_BITS2(UART_INT_ST_REG(i) , UART_RS485_FRM_ERR_INT_ST_V, UART_RS485_FRM_ERR_INT_ST_S)
+        #define UART_GET_RS485_PARITY_ERR_INT_ST(i)  GET_PERI_REG_BITS2(UART_INT_ST_REG(i) , UART_RS485_PARITY_ERR_INT_ST_V, UART_RS485_PARITY_ERR_INT_ST_S)
+        #define UART_GET_TX_DONE_INT_ST(i)  GET_PERI_REG_BITS2(UART_INT_ST_REG(i) , UART_TX_DONE_INT_ST_V, UART_TX_DONE_INT_ST_S)
+        #define UART_GET_TX_BRK_IDLE_DONE_INT_ST(i)  GET_PERI_REG_BITS2(UART_INT_ST_REG(i) , UART_TX_BRK_IDLE_DONE_INT_ST_V, UART_TX_BRK_IDLE_DONE_INT_ST_S)
+        #define UART_GET_TX_BRK_DONE_INT_ST(i)  GET_PERI_REG_BITS2(UART_INT_ST_REG(i) , UART_TX_BRK_DONE_INT_ST_V, UART_TX_BRK_DONE_INT_ST_S)
+        #define UART_GET_GLITCH_DET_INT_ST(i)  GET_PERI_REG_BITS2(UART_INT_ST_REG(i) , UART_GLITCH_DET_INT_ST_V, UART_GLITCH_DET_INT_ST_S)
+        #define UART_GET_SW_XOFF_INT_ST(i)  GET_PERI_REG_BITS2(UART_INT_ST_REG(i) , UART_SW_XOFF_INT_ST_V, UART_SW_XOFF_INT_ST_S)
+        #define UART_GET_SW_XON_INT_ST(i)  GET_PERI_REG_BITS2(UART_INT_ST_REG(i) , UART_SW_XON_INT_ST_V, UART_SW_XON_INT_ST_S)
+        #define UART_GET_RXFIFO_TOUT_INT_ST(i)  GET_PERI_REG_BITS2(UART_INT_ST_REG(i) , UART_RXFIFO_TOUT_INT_ST_V, UART_RXFIFO_TOUT_INT_ST_S)
+        #define UART_GET_BRK_DET_INT_ST(i)  GET_PERI_REG_BITS2(UART_INT_ST_REG(i) , UART_BRK_DET_INT_ST_V, UART_BRK_DET_INT_ST_S)
+        #define UART_GET_CTS_CHG_INT_ST(i)  GET_PERI_REG_BITS2(UART_INT_ST_REG(i) , UART_CTS_CHG_INT_ST_V, UART_CTS_CHG_INT_ST_S)
+        #define UART_GET_DSR_CHG_INT_ST(i)  GET_PERI_REG_BITS2(UART_INT_ST_REG(i) , UART_DSR_CHG_INT_ST_V, UART_DSR_CHG_INT_ST_S)
+        #define UART_GET_RXFIFO_OVF_INT_ST(i)  GET_PERI_REG_BITS2(UART_INT_ST_REG(i) , UART_RXFIFO_OVF_INT_ST_V, UART_RXFIFO_OVF_INT_ST_S)
+        #define UART_GET_FRM_ERR_INT_ST(i)  GET_PERI_REG_BITS2(UART_INT_ST_REG(i) , UART_FRM_ERR_INT_ST_V, UART_FRM_ERR_INT_ST_S)
+        #define UART_GET_PARITY_ERR_INT_ST(i)  GET_PERI_REG_BITS2(UART_INT_ST_REG(i) , UART_PARITY_ERR_INT_ST_V, UART_PARITY_ERR_INT_ST_S)
+        #define UART_GET_TXFIFO_EMPTY_INT_ST(i)  GET_PERI_REG_BITS2(UART_INT_ST_REG(i) , UART_TXFIFO_EMPTY_INT_ST_V, UART_TXFIFO_EMPTY_INT_ST_S)
+        #define UART_GET_RXFIFO_FULL_INT_ST(i)  GET_PERI_REG_BITS2(UART_INT_ST_REG(i) , UART_RXFIFO_FULL_INT_ST_V, UART_RXFIFO_FULL_INT_ST_S)
+
+
+
+#define UART_INT_ENA_REG(i)          (REG_UART_BASE(i) + 0xC)
+    /* UART_AT_CMD_CHAR_DET_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */
+    /*description: The interrupt enable bit for detecting AT_CMD char interrupt*/
+    #define UART_AT_CMD_CHAR_DET_INT_ENA  (BIT(18))
+    #define UART_AT_CMD_CHAR_DET_INT_ENA_M  (BIT(18))
+    #define UART_AT_CMD_CHAR_DET_INT_ENA_V  0x1
+    #define UART_AT_CMD_CHAR_DET_INT_ENA_S  18
+    /* UART_RS485_CLASH_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */
+    /*description: The interrupt enable bit for rs485 tx rx clash interrrupt*/
+    #define UART_RS485_CLASH_INT_ENA  (BIT(17))
+    #define UART_RS485_CLASH_INT_ENA_M  (BIT(17))
+    #define UART_RS485_CLASH_INT_ENA_V  0x1
+    #define UART_RS485_CLASH_INT_ENA_S  17
+    /* UART_RS485_FRM_ERR_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */
+    /*description: The interrupt enable bit for rs485 other rx error*/
+    #define UART_RS485_FRM_ERR_INT_ENA  (BIT(16))
+    #define UART_RS485_FRM_ERR_INT_ENA_M  (BIT(16))
+    #define UART_RS485_FRM_ERR_INT_ENA_V  0x1
+    #define UART_RS485_FRM_ERR_INT_ENA_S  16
+    /* UART_RS485_PARITY_ERR_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */
+    /*description: The interrupt enable bit for rs485 parity error*/
+    #define UART_RS485_PARITY_ERR_INT_ENA  (BIT(15))
+    #define UART_RS485_PARITY_ERR_INT_ENA_M  (BIT(15))
+    #define UART_RS485_PARITY_ERR_INT_ENA_V  0x1
+    #define UART_RS485_PARITY_ERR_INT_ENA_S  15
+    /* UART_TX_DONE_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */
+    /*description: The interrupt enable bit for tx done interrupt*/
+    #define UART_TX_DONE_INT_ENA  (BIT(14))
+    #define UART_TX_DONE_INT_ENA_M  (BIT(14))
+    #define UART_TX_DONE_INT_ENA_V  0x1
+    #define UART_TX_DONE_INT_ENA_S  14
+    /* UART_TX_BRK_IDLE_DONE_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */
+    /*description: The interrupt enable bit for tx send idle done interrupt*/
+    #define UART_TX_BRK_IDLE_DONE_INT_ENA  (BIT(13))
+    #define UART_TX_BRK_IDLE_DONE_INT_ENA_M  (BIT(13))
+    #define UART_TX_BRK_IDLE_DONE_INT_ENA_V  0x1
+    #define UART_TX_BRK_IDLE_DONE_INT_ENA_S  13
+    /* UART_TX_BRK_DONE_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */
+    /*description: The interrupt enable bit for send 0 done interrupt*/
+    #define UART_TX_BRK_DONE_INT_ENA  (BIT(12))
+    #define UART_TX_BRK_DONE_INT_ENA_M  (BIT(12))
+    #define UART_TX_BRK_DONE_INT_ENA_V  0x1
+    #define UART_TX_BRK_DONE_INT_ENA_S  12
+    /* UART_GLITCH_DET_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
+    /*description: The interrupt enable bit for detecting rx glitch pulse interrupt*/
+    #define UART_GLITCH_DET_INT_ENA  (BIT(11))
+    #define UART_GLITCH_DET_INT_ENA_M  (BIT(11))
+    #define UART_GLITCH_DET_INT_ENA_V  0x1
+    #define UART_GLITCH_DET_INT_ENA_S  11
+    /* UART_SW_XOFF_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
+    /*description: The interrupt enable bit for rx receive xoff char interrupt*/
+    #define UART_SW_XOFF_INT_ENA  (BIT(10))
+    #define UART_SW_XOFF_INT_ENA_M  (BIT(10))
+    #define UART_SW_XOFF_INT_ENA_V  0x1
+    #define UART_SW_XOFF_INT_ENA_S  10
+    /* UART_SW_XON_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
+    /*description: The interrupt enable bit for rx receive xon char interrupt*/
+    #define UART_SW_XON_INT_ENA  (BIT(9))
+    #define UART_SW_XON_INT_ENA_M  (BIT(9))
+    #define UART_SW_XON_INT_ENA_V  0x1
+    #define UART_SW_XON_INT_ENA_S  9
+    /* UART_RXFIFO_TOUT_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
+    /*description: The interrupt enable bit for rx time-out interrupt*/
+    #define UART_RXFIFO_TOUT_INT_ENA  (BIT(8))
+    #define UART_RXFIFO_TOUT_INT_ENA_M  (BIT(8))
+    #define UART_RXFIFO_TOUT_INT_ENA_V  0x1
+    #define UART_RXFIFO_TOUT_INT_ENA_S  8
+    /* UART_BRK_DET_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
+    /*description: The interrupt enable bit for rx byte start error*/
+    #define UART_BRK_DET_INT_ENA  (BIT(7))
+    #define UART_BRK_DET_INT_ENA_M  (BIT(7))
+    #define UART_BRK_DET_INT_ENA_V  0x1
+    #define UART_BRK_DET_INT_ENA_S  7
+    /* UART_CTS_CHG_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
+    /*description: The interrupt enable bit for CTS changing level*/
+    #define UART_CTS_CHG_INT_ENA  (BIT(6))
+    #define UART_CTS_CHG_INT_ENA_M  (BIT(6))
+    #define UART_CTS_CHG_INT_ENA_V  0x1
+    #define UART_CTS_CHG_INT_ENA_S  6
+    /* UART_DSR_CHG_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
+    /*description: The interrupt enable bit for DSR changing level*/
+    #define UART_DSR_CHG_INT_ENA  (BIT(5))
+    #define UART_DSR_CHG_INT_ENA_M  (BIT(5))
+    #define UART_DSR_CHG_INT_ENA_V  0x1
+    #define UART_DSR_CHG_INT_ENA_S  5
+    /* UART_RXFIFO_OVF_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+    /*description: The interrupt enable bit for rx fifo overflow*/
+    #define UART_RXFIFO_OVF_INT_ENA  (BIT(4))
+    #define UART_RXFIFO_OVF_INT_ENA_M  (BIT(4))
+    #define UART_RXFIFO_OVF_INT_ENA_V  0x1
+    #define UART_RXFIFO_OVF_INT_ENA_S  4
+    /* UART_FRM_ERR_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
+    /*description: The interrupt enable bit for other rx error*/
+    #define UART_FRM_ERR_INT_ENA  (BIT(3))
+    #define UART_FRM_ERR_INT_ENA_M  (BIT(3))
+    #define UART_FRM_ERR_INT_ENA_V  0x1
+    #define UART_FRM_ERR_INT_ENA_S  3
+    /* UART_PARITY_ERR_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+    /*description: The interrupt enable bit for parity error*/
+    #define UART_PARITY_ERR_INT_ENA  (BIT(2))
+    #define UART_PARITY_ERR_INT_ENA_M  (BIT(2))
+    #define UART_PARITY_ERR_INT_ENA_V  0x1
+    #define UART_PARITY_ERR_INT_ENA_S  2
+    /* UART_TXFIFO_EMPTY_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+    /*description: The interrupt enable bit for tx fifo empty event*/
+    #define UART_TXFIFO_EMPTY_INT_ENA  (BIT(1))
+    #define UART_TXFIFO_EMPTY_INT_ENA_M  (BIT(1))
+    #define UART_TXFIFO_EMPTY_INT_ENA_V  0x1
+    #define UART_TXFIFO_EMPTY_INT_ENA_S  1
+    /* UART_RXFIFO_FULL_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+    /*description: The interrupt enable bit for rx fifo full event*/
+    #define UART_RXFIFO_FULL_INT_ENA  (BIT(0))
+    #define UART_RXFIFO_FULL_INT_ENA_M  (BIT(0))
+    #define UART_RXFIFO_FULL_INT_ENA_V  0x1
+    #define UART_RXFIFO_FULL_INT_ENA_S  0
+        #define UART_GET_AT_CMD_CHAR_DET_INT_ENA(i)  GET_PERI_REG_BITS2(UART_INT_ENA_REG(i) , UART_AT_CMD_CHAR_DET_INT_ENA_V, UART_AT_CMD_CHAR_DET_INT_ENA_S)
+        #define UART_SET_AT_CMD_CHAR_DET_INT_ENA(i,val)  SET_PERI_REG_BITS(UART_INT_ENA_REG(i) ,UART_AT_CMD_CHAR_DET_INT_ENA_V,(val),UART_AT_CMD_CHAR_DET_INT_ENA_S)
+        #define UART_GET_RS485_CLASH_INT_ENA(i)  GET_PERI_REG_BITS2(UART_INT_ENA_REG(i) , UART_RS485_CLASH_INT_ENA_V, UART_RS485_CLASH_INT_ENA_S)
+        #define UART_SET_RS485_CLASH_INT_ENA(i,val)  SET_PERI_REG_BITS(UART_INT_ENA_REG(i) ,UART_RS485_CLASH_INT_ENA_V,(val),UART_RS485_CLASH_INT_ENA_S)
+        #define UART_GET_RS485_FRM_ERR_INT_ENA(i)  GET_PERI_REG_BITS2(UART_INT_ENA_REG(i) , UART_RS485_FRM_ERR_INT_ENA_V, UART_RS485_FRM_ERR_INT_ENA_S)
+        #define UART_SET_RS485_FRM_ERR_INT_ENA(i,val)  SET_PERI_REG_BITS(UART_INT_ENA_REG(i) ,UART_RS485_FRM_ERR_INT_ENA_V,(val),UART_RS485_FRM_ERR_INT_ENA_S)
+        #define UART_GET_RS485_PARITY_ERR_INT_ENA(i)  GET_PERI_REG_BITS2(UART_INT_ENA_REG(i) , UART_RS485_PARITY_ERR_INT_ENA_V, UART_RS485_PARITY_ERR_INT_ENA_S)
+        #define UART_SET_RS485_PARITY_ERR_INT_ENA(i,val)  SET_PERI_REG_BITS(UART_INT_ENA_REG(i) ,UART_RS485_PARITY_ERR_INT_ENA_V,(val),UART_RS485_PARITY_ERR_INT_ENA_S)
+        #define UART_GET_TX_DONE_INT_ENA(i)  GET_PERI_REG_BITS2(UART_INT_ENA_REG(i) , UART_TX_DONE_INT_ENA_V, UART_TX_DONE_INT_ENA_S)
+        #define UART_SET_TX_DONE_INT_ENA(i,val)  SET_PERI_REG_BITS(UART_INT_ENA_REG(i) ,UART_TX_DONE_INT_ENA_V,(val),UART_TX_DONE_INT_ENA_S)
+        #define UART_GET_TX_BRK_IDLE_DONE_INT_ENA(i)  GET_PERI_REG_BITS2(UART_INT_ENA_REG(i) , UART_TX_BRK_IDLE_DONE_INT_ENA_V, UART_TX_BRK_IDLE_DONE_INT_ENA_S)
+        #define UART_SET_TX_BRK_IDLE_DONE_INT_ENA(i,val)  SET_PERI_REG_BITS(UART_INT_ENA_REG(i) ,UART_TX_BRK_IDLE_DONE_INT_ENA_V,(val),UART_TX_BRK_IDLE_DONE_INT_ENA_S)
+        #define UART_GET_TX_BRK_DONE_INT_ENA(i)  GET_PERI_REG_BITS2(UART_INT_ENA_REG(i) , UART_TX_BRK_DONE_INT_ENA_V, UART_TX_BRK_DONE_INT_ENA_S)
+        #define UART_SET_TX_BRK_DONE_INT_ENA(i,val)  SET_PERI_REG_BITS(UART_INT_ENA_REG(i) ,UART_TX_BRK_DONE_INT_ENA_V,(val),UART_TX_BRK_DONE_INT_ENA_S)
+        #define UART_GET_GLITCH_DET_INT_ENA(i)  GET_PERI_REG_BITS2(UART_INT_ENA_REG(i) , UART_GLITCH_DET_INT_ENA_V, UART_GLITCH_DET_INT_ENA_S)
+        #define UART_SET_GLITCH_DET_INT_ENA(i,val)  SET_PERI_REG_BITS(UART_INT_ENA_REG(i) ,UART_GLITCH_DET_INT_ENA_V,(val),UART_GLITCH_DET_INT_ENA_S)
+        #define UART_GET_SW_XOFF_INT_ENA(i)  GET_PERI_REG_BITS2(UART_INT_ENA_REG(i) , UART_SW_XOFF_INT_ENA_V, UART_SW_XOFF_INT_ENA_S)
+        #define UART_SET_SW_XOFF_INT_ENA(i,val)  SET_PERI_REG_BITS(UART_INT_ENA_REG(i) ,UART_SW_XOFF_INT_ENA_V,(val),UART_SW_XOFF_INT_ENA_S)
+        #define UART_GET_SW_XON_INT_ENA(i)  GET_PERI_REG_BITS2(UART_INT_ENA_REG(i) , UART_SW_XON_INT_ENA_V, UART_SW_XON_INT_ENA_S)
+        #define UART_SET_SW_XON_INT_ENA(i,val)  SET_PERI_REG_BITS(UART_INT_ENA_REG(i) ,UART_SW_XON_INT_ENA_V,(val),UART_SW_XON_INT_ENA_S)
+        #define UART_GET_RXFIFO_TOUT_INT_ENA(i)  GET_PERI_REG_BITS2(UART_INT_ENA_REG(i) , UART_RXFIFO_TOUT_INT_ENA_V, UART_RXFIFO_TOUT_INT_ENA_S)
+        #define UART_SET_RXFIFO_TOUT_INT_ENA(i,val)  SET_PERI_REG_BITS(UART_INT_ENA_REG(i) ,UART_RXFIFO_TOUT_INT_ENA_V,(val),UART_RXFIFO_TOUT_INT_ENA_S)
+        #define UART_GET_BRK_DET_INT_ENA(i)  GET_PERI_REG_BITS2(UART_INT_ENA_REG(i) , UART_BRK_DET_INT_ENA_V, UART_BRK_DET_INT_ENA_S)
+        #define UART_SET_BRK_DET_INT_ENA(i,val)  SET_PERI_REG_BITS(UART_INT_ENA_REG(i) ,UART_BRK_DET_INT_ENA_V,(val),UART_BRK_DET_INT_ENA_S)
+        #define UART_GET_CTS_CHG_INT_ENA(i)  GET_PERI_REG_BITS2(UART_INT_ENA_REG(i) , UART_CTS_CHG_INT_ENA_V, UART_CTS_CHG_INT_ENA_S)
+        #define UART_SET_CTS_CHG_INT_ENA(i,val)  SET_PERI_REG_BITS(UART_INT_ENA_REG(i) ,UART_CTS_CHG_INT_ENA_V,(val),UART_CTS_CHG_INT_ENA_S)
+        #define UART_GET_DSR_CHG_INT_ENA(i)  GET_PERI_REG_BITS2(UART_INT_ENA_REG(i) , UART_DSR_CHG_INT_ENA_V, UART_DSR_CHG_INT_ENA_S)
+        #define UART_SET_DSR_CHG_INT_ENA(i,val)  SET_PERI_REG_BITS(UART_INT_ENA_REG(i) ,UART_DSR_CHG_INT_ENA_V,(val),UART_DSR_CHG_INT_ENA_S)
+        #define UART_GET_RXFIFO_OVF_INT_ENA(i)  GET_PERI_REG_BITS2(UART_INT_ENA_REG(i) , UART_RXFIFO_OVF_INT_ENA_V, UART_RXFIFO_OVF_INT_ENA_S)
+        #define UART_SET_RXFIFO_OVF_INT_ENA(i,val)  SET_PERI_REG_BITS(UART_INT_ENA_REG(i) ,UART_RXFIFO_OVF_INT_ENA_V,(val),UART_RXFIFO_OVF_INT_ENA_S)
+        #define UART_GET_FRM_ERR_INT_ENA(i)  GET_PERI_REG_BITS2(UART_INT_ENA_REG(i) , UART_FRM_ERR_INT_ENA_V, UART_FRM_ERR_INT_ENA_S)
+        #define UART_SET_FRM_ERR_INT_ENA(i,val)  SET_PERI_REG_BITS(UART_INT_ENA_REG(i) ,UART_FRM_ERR_INT_ENA_V,(val),UART_FRM_ERR_INT_ENA_S)
+        #define UART_GET_PARITY_ERR_INT_ENA(i)  GET_PERI_REG_BITS2(UART_INT_ENA_REG(i) , UART_PARITY_ERR_INT_ENA_V, UART_PARITY_ERR_INT_ENA_S)
+        #define UART_SET_PARITY_ERR_INT_ENA(i,val)  SET_PERI_REG_BITS(UART_INT_ENA_REG(i) ,UART_PARITY_ERR_INT_ENA_V,(val),UART_PARITY_ERR_INT_ENA_S)
+        #define UART_GET_TXFIFO_EMPTY_INT_ENA(i)  GET_PERI_REG_BITS2(UART_INT_ENA_REG(i) , UART_TXFIFO_EMPTY_INT_ENA_V, UART_TXFIFO_EMPTY_INT_ENA_S)
+        #define UART_SET_TXFIFO_EMPTY_INT_ENA(i,val)  SET_PERI_REG_BITS(UART_INT_ENA_REG(i) ,UART_TXFIFO_EMPTY_INT_ENA_V,(val),UART_TXFIFO_EMPTY_INT_ENA_S)
+        #define UART_GET_RXFIFO_FULL_INT_ENA(i)  GET_PERI_REG_BITS2(UART_INT_ENA_REG(i) , UART_RXFIFO_FULL_INT_ENA_V, UART_RXFIFO_FULL_INT_ENA_S)
+        #define UART_SET_RXFIFO_FULL_INT_ENA(i,val)  SET_PERI_REG_BITS(UART_INT_ENA_REG(i) ,UART_RXFIFO_FULL_INT_ENA_V,(val),UART_RXFIFO_FULL_INT_ENA_S)
+
+
+
+#define UART_INT_CLR_REG(i)          (REG_UART_BASE(i) + 0x10)
+    /* UART_AT_CMD_CHAR_DET_INT_CLR : WO ;bitpos:[18] ;default: 1'b0 ; */
+    /*description: Set this bit for detecting AT_CMD char interrupt*/
+    #define UART_AT_CMD_CHAR_DET_INT_CLR  (BIT(18))
+    #define UART_AT_CMD_CHAR_DET_INT_CLR_M  (BIT(18))
+    #define UART_AT_CMD_CHAR_DET_INT_CLR_V  0x1
+    #define UART_AT_CMD_CHAR_DET_INT_CLR_S  18
+    /* UART_RS485_CLASH_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */
+    /*description: Set this bit for rs485 tx rx clash interrrupt*/
+    #define UART_RS485_CLASH_INT_CLR  (BIT(17))
+    #define UART_RS485_CLASH_INT_CLR_M  (BIT(17))
+    #define UART_RS485_CLASH_INT_CLR_V  0x1
+    #define UART_RS485_CLASH_INT_CLR_S  17
+    /* UART_RS485_FRM_ERR_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */
+    /*description: Set this bit for rs485 other rx error*/
+    #define UART_RS485_FRM_ERR_INT_CLR  (BIT(16))
+    #define UART_RS485_FRM_ERR_INT_CLR_M  (BIT(16))
+    #define UART_RS485_FRM_ERR_INT_CLR_V  0x1
+    #define UART_RS485_FRM_ERR_INT_CLR_S  16
+    /* UART_RS485_PARITY_ERR_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */
+    /*description: Set this bit for rs485 parity error interrupt*/
+    #define UART_RS485_PARITY_ERR_INT_CLR  (BIT(15))
+    #define UART_RS485_PARITY_ERR_INT_CLR_M  (BIT(15))
+    #define UART_RS485_PARITY_ERR_INT_CLR_V  0x1
+    #define UART_RS485_PARITY_ERR_INT_CLR_S  15
+    /* UART_TX_DONE_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */
+    /*description: Set this bit to clear the  tx done interrupt*/
+    #define UART_TX_DONE_INT_CLR  (BIT(14))
+    #define UART_TX_DONE_INT_CLR_M  (BIT(14))
+    #define UART_TX_DONE_INT_CLR_V  0x1
+    #define UART_TX_DONE_INT_CLR_S  14
+    /* UART_TX_BRK_IDLE_DONE_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */
+    /*description: Set this bit to clear the  tx send idle done interrupt*/
+    #define UART_TX_BRK_IDLE_DONE_INT_CLR  (BIT(13))
+    #define UART_TX_BRK_IDLE_DONE_INT_CLR_M  (BIT(13))
+    #define UART_TX_BRK_IDLE_DONE_INT_CLR_V  0x1
+    #define UART_TX_BRK_IDLE_DONE_INT_CLR_S  13
+    /* UART_TX_BRK_DONE_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */
+    /*description: Set this bit to clear the  send 0 done interrupt*/
+    #define UART_TX_BRK_DONE_INT_CLR  (BIT(12))
+    #define UART_TX_BRK_DONE_INT_CLR_M  (BIT(12))
+    #define UART_TX_BRK_DONE_INT_CLR_V  0x1
+    #define UART_TX_BRK_DONE_INT_CLR_S  12
+    /* UART_GLITCH_DET_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */
+    /*description: Set this bit to clear the  detecting rx glitch pulse interrupt*/
+    #define UART_GLITCH_DET_INT_CLR  (BIT(11))
+    #define UART_GLITCH_DET_INT_CLR_M  (BIT(11))
+    #define UART_GLITCH_DET_INT_CLR_V  0x1
+    #define UART_GLITCH_DET_INT_CLR_S  11
+    /* UART_SW_XOFF_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */
+    /*description: Set this bit to clear the  rx receive xoff char interrupt*/
+    #define UART_SW_XOFF_INT_CLR  (BIT(10))
+    #define UART_SW_XOFF_INT_CLR_M  (BIT(10))
+    #define UART_SW_XOFF_INT_CLR_V  0x1
+    #define UART_SW_XOFF_INT_CLR_S  10
+    /* UART_SW_XON_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */
+    /*description: Set this bit to clear the  rx receive xon char interrupt*/
+    #define UART_SW_XON_INT_CLR  (BIT(9))
+    #define UART_SW_XON_INT_CLR_M  (BIT(9))
+    #define UART_SW_XON_INT_CLR_V  0x1
+    #define UART_SW_XON_INT_CLR_S  9
+    /* UART_RXFIFO_TOUT_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */
+    /*description: Set this bit to clear the rx time-out interrupt*/
+    #define UART_RXFIFO_TOUT_INT_CLR  (BIT(8))
+    #define UART_RXFIFO_TOUT_INT_CLR_M  (BIT(8))
+    #define UART_RXFIFO_TOUT_INT_CLR_V  0x1
+    #define UART_RXFIFO_TOUT_INT_CLR_S  8
+    /* UART_BRK_DET_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */
+    /*description: Set this bit to clear the rx byte start interrupt*/
+    #define UART_BRK_DET_INT_CLR  (BIT(7))
+    #define UART_BRK_DET_INT_CLR_M  (BIT(7))
+    #define UART_BRK_DET_INT_CLR_V  0x1
+    #define UART_BRK_DET_INT_CLR_S  7
+    /* UART_CTS_CHG_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */
+    /*description: Set this bit to clear the CTS changing interrupt*/
+    #define UART_CTS_CHG_INT_CLR  (BIT(6))
+    #define UART_CTS_CHG_INT_CLR_M  (BIT(6))
+    #define UART_CTS_CHG_INT_CLR_V  0x1
+    #define UART_CTS_CHG_INT_CLR_S  6
+    /* UART_DSR_CHG_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */
+    /*description: Set this bit to clear the DSR changing interrupt*/
+    #define UART_DSR_CHG_INT_CLR  (BIT(5))
+    #define UART_DSR_CHG_INT_CLR_M  (BIT(5))
+    #define UART_DSR_CHG_INT_CLR_V  0x1
+    #define UART_DSR_CHG_INT_CLR_S  5
+    /* UART_RXFIFO_OVF_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */
+    /*description: Set this bit to clear the rx fifo over-flow interrupt*/
+    #define UART_RXFIFO_OVF_INT_CLR  (BIT(4))
+    #define UART_RXFIFO_OVF_INT_CLR_M  (BIT(4))
+    #define UART_RXFIFO_OVF_INT_CLR_V  0x1
+    #define UART_RXFIFO_OVF_INT_CLR_S  4
+    /* UART_FRM_ERR_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */
+    /*description: Set this bit to clear other rx error interrupt*/
+    #define UART_FRM_ERR_INT_CLR  (BIT(3))
+    #define UART_FRM_ERR_INT_CLR_M  (BIT(3))
+    #define UART_FRM_ERR_INT_CLR_V  0x1
+    #define UART_FRM_ERR_INT_CLR_S  3
+    /* UART_PARITY_ERR_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */
+    /*description: Set this bit to clear the parity error interrupt*/
+    #define UART_PARITY_ERR_INT_CLR  (BIT(2))
+    #define UART_PARITY_ERR_INT_CLR_M  (BIT(2))
+    #define UART_PARITY_ERR_INT_CLR_V  0x1
+    #define UART_PARITY_ERR_INT_CLR_S  2
+    /* UART_TXFIFO_EMPTY_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
+    /*description: Set this bit to clear the tx fifo empty interrupt*/
+    #define UART_TXFIFO_EMPTY_INT_CLR  (BIT(1))
+    #define UART_TXFIFO_EMPTY_INT_CLR_M  (BIT(1))
+    #define UART_TXFIFO_EMPTY_INT_CLR_V  0x1
+    #define UART_TXFIFO_EMPTY_INT_CLR_S  1
+    /* UART_RXFIFO_FULL_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
+    /*description: Set this bit to clear the rx fifo full interrupt*/
+    #define UART_RXFIFO_FULL_INT_CLR  (BIT(0))
+    #define UART_RXFIFO_FULL_INT_CLR_M  (BIT(0))
+    #define UART_RXFIFO_FULL_INT_CLR_V  0x1
+    #define UART_RXFIFO_FULL_INT_CLR_S  0
+        #define UART_SET_AT_CMD_CHAR_DET_INT_CLR(i,val)  SET_PERI_REG_BITS(UART_INT_CLR_REG(i) ,UART_AT_CMD_CHAR_DET_INT_CLR_V,(val),UART_AT_CMD_CHAR_DET_INT_CLR_S)
+        #define UART_SET_RS485_CLASH_INT_CLR(i,val)  SET_PERI_REG_BITS(UART_INT_CLR_REG(i) ,UART_RS485_CLASH_INT_CLR_V,(val),UART_RS485_CLASH_INT_CLR_S)
+        #define UART_SET_RS485_FRM_ERR_INT_CLR(i,val)  SET_PERI_REG_BITS(UART_INT_CLR_REG(i) ,UART_RS485_FRM_ERR_INT_CLR_V,(val),UART_RS485_FRM_ERR_INT_CLR_S)
+        #define UART_SET_RS485_PARITY_ERR_INT_CLR(i,val)  SET_PERI_REG_BITS(UART_INT_CLR_REG(i) ,UART_RS485_PARITY_ERR_INT_CLR_V,(val),UART_RS485_PARITY_ERR_INT_CLR_S)
+        #define UART_SET_TX_DONE_INT_CLR(i,val)  SET_PERI_REG_BITS(UART_INT_CLR_REG(i) ,UART_TX_DONE_INT_CLR_V,(val),UART_TX_DONE_INT_CLR_S)
+        #define UART_SET_TX_BRK_IDLE_DONE_INT_CLR(i,val)  SET_PERI_REG_BITS(UART_INT_CLR_REG(i) ,UART_TX_BRK_IDLE_DONE_INT_CLR_V,(val),UART_TX_BRK_IDLE_DONE_INT_CLR_S)
+        #define UART_SET_TX_BRK_DONE_INT_CLR(i,val)  SET_PERI_REG_BITS(UART_INT_CLR_REG(i) ,UART_TX_BRK_DONE_INT_CLR_V,(val),UART_TX_BRK_DONE_INT_CLR_S)
+        #define UART_SET_GLITCH_DET_INT_CLR(i,val)  SET_PERI_REG_BITS(UART_INT_CLR_REG(i) ,UART_GLITCH_DET_INT_CLR_V,(val),UART_GLITCH_DET_INT_CLR_S)
+        #define UART_SET_SW_XOFF_INT_CLR(i,val)  SET_PERI_REG_BITS(UART_INT_CLR_REG(i) ,UART_SW_XOFF_INT_CLR_V,(val),UART_SW_XOFF_INT_CLR_S)
+        #define UART_SET_SW_XON_INT_CLR(i,val)  SET_PERI_REG_BITS(UART_INT_CLR_REG(i) ,UART_SW_XON_INT_CLR_V,(val),UART_SW_XON_INT_CLR_S)
+        #define UART_SET_RXFIFO_TOUT_INT_CLR(i,val)  SET_PERI_REG_BITS(UART_INT_CLR_REG(i) ,UART_RXFIFO_TOUT_INT_CLR_V,(val),UART_RXFIFO_TOUT_INT_CLR_S)
+        #define UART_SET_BRK_DET_INT_CLR(i,val)  SET_PERI_REG_BITS(UART_INT_CLR_REG(i) ,UART_BRK_DET_INT_CLR_V,(val),UART_BRK_DET_INT_CLR_S)
+        #define UART_SET_CTS_CHG_INT_CLR(i,val)  SET_PERI_REG_BITS(UART_INT_CLR_REG(i) ,UART_CTS_CHG_INT_CLR_V,(val),UART_CTS_CHG_INT_CLR_S)
+        #define UART_SET_DSR_CHG_INT_CLR(i,val)  SET_PERI_REG_BITS(UART_INT_CLR_REG(i) ,UART_DSR_CHG_INT_CLR_V,(val),UART_DSR_CHG_INT_CLR_S)
+        #define UART_SET_RXFIFO_OVF_INT_CLR(i,val)  SET_PERI_REG_BITS(UART_INT_CLR_REG(i) ,UART_RXFIFO_OVF_INT_CLR_V,(val),UART_RXFIFO_OVF_INT_CLR_S)
+        #define UART_SET_FRM_ERR_INT_CLR(i,val)  SET_PERI_REG_BITS(UART_INT_CLR_REG(i) ,UART_FRM_ERR_INT_CLR_V,(val),UART_FRM_ERR_INT_CLR_S)
+        #define UART_SET_PARITY_ERR_INT_CLR(i,val)  SET_PERI_REG_BITS(UART_INT_CLR_REG(i) ,UART_PARITY_ERR_INT_CLR_V,(val),UART_PARITY_ERR_INT_CLR_S)
+        #define UART_SET_TXFIFO_EMPTY_INT_CLR(i,val)  SET_PERI_REG_BITS(UART_INT_CLR_REG(i) ,UART_TXFIFO_EMPTY_INT_CLR_V,(val),UART_TXFIFO_EMPTY_INT_CLR_S)
+        #define UART_SET_RXFIFO_FULL_INT_CLR(i,val)  SET_PERI_REG_BITS(UART_INT_CLR_REG(i) ,UART_RXFIFO_FULL_INT_CLR_V,(val),UART_RXFIFO_FULL_INT_CLR_S)
+
+
+
+#define UART_CLKDIV_REG(i)          (REG_UART_BASE(i) + 0x14)
+    /* UART_CLKDIV_FRAG : R/W ;bitpos:[23:20] ;default: 4'b0 ; */
+    /*description: The decimal part of divider*/
+    #define UART_CLKDIV_FRAG  0x0000000F
+    #define UART_CLKDIV_FRAG_M  ((UART_CLKDIV_FRAG_V)<<(UART_CLKDIV_FRAG_S))
+    #define UART_CLKDIV_FRAG_V  0xF
+    #define UART_CLKDIV_FRAG_S  20
+    /* UART_CLKDIV : R/W ;bitpos:[19:0] ;default: 20'h2B6 ; */
+    /*description: The interger part of divider  BAUDRATE = UART_CLK_FREQ / UART_CLKDIV*/
+    #define UART_CLKDIV  0x000FFFFF
+    #define UART_CLKDIV_M  ((UART_CLKDIV_V)<<(UART_CLKDIV_S))
+    #define UART_CLKDIV_V  0xFFFFF
+    #define UART_CLKDIV_S  0
+        #define UART_GET_CLKDIV_FRAG(i)  GET_PERI_REG_BITS2(UART_CLKDIV_REG(i) , UART_CLKDIV_FRAG_V, UART_CLKDIV_FRAG_S)
+        #define UART_SET_CLKDIV_FRAG(i,val)  SET_PERI_REG_BITS(UART_CLKDIV_REG(i) ,UART_CLKDIV_FRAG_V,(val),UART_CLKDIV_FRAG_S)
+        #define UART_GET_CLKDIV(i)  GET_PERI_REG_BITS2(UART_CLKDIV_REG(i) , UART_CLKDIV_V, UART_CLKDIV_S)
+        #define UART_SET_CLKDIV(i,val)  SET_PERI_REG_BITS(UART_CLKDIV_REG(i) ,UART_CLKDIV_V,(val),UART_CLKDIV_S)
+
+
+
+#define UART_AUTOBAUD_REG(i)          (REG_UART_BASE(i) + 0x18)
+    /* UART_GLITCH_FILT : R/W ;bitpos:[15:8] ;default: 8'h10 ; */
+    /*description: ignore the glitch when pulse cnt is lower then this value*/
+    #define UART_GLITCH_FILT  0x000000FF
+    #define UART_GLITCH_FILT_M  ((UART_GLITCH_FILT_V)<<(UART_GLITCH_FILT_S))
+    #define UART_GLITCH_FILT_V  0xFF
+    #define UART_GLITCH_FILT_S  8
+    /* UART_AUTOBAUD_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
+    /*description: Set this bit to enable baudrate detect*/
+    #define UART_AUTOBAUD_EN  (BIT(0))
+    #define UART_AUTOBAUD_EN_M  (BIT(0))
+    #define UART_AUTOBAUD_EN_V  0x1
+    #define UART_AUTOBAUD_EN_S  0
+        #define UART_GET_GLITCH_FILT(i)  GET_PERI_REG_BITS2(UART_AUTOBAUD_REG(i) , UART_GLITCH_FILT_V, UART_GLITCH_FILT_S)
+        #define UART_SET_GLITCH_FILT(i,val)  SET_PERI_REG_BITS(UART_AUTOBAUD_REG(i) ,UART_GLITCH_FILT_V,(val),UART_GLITCH_FILT_S)
+        #define UART_GET_AUTOBAUD_EN(i)  GET_PERI_REG_BITS2(UART_AUTOBAUD_REG(i) , UART_AUTOBAUD_EN_V, UART_AUTOBAUD_EN_S)
+        #define UART_SET_AUTOBAUD_EN(i,val)  SET_PERI_REG_BITS(UART_AUTOBAUD_REG(i) ,UART_AUTOBAUD_EN_V,(val),UART_AUTOBAUD_EN_S)
+
+
+
+#define UART_STATUS_REG(i)          (REG_UART_BASE(i) + 0x1C)
+    /* UART_TXD : RO ;bitpos:[31] ;default: 8'h0 ; */
+    /*description: The level of the internal uart txd value*/
+    #define UART_TXD  (BIT(31))
+    #define UART_TXD_M  (BIT(31))
+    #define UART_TXD_V  0x1
+    #define UART_TXD_S  31
+    /* UART_RTSN : RO ;bitpos:[30] ;default: 1'b0 ; */
+    /*description: The level of the internal uart rts pin*/
+    #define UART_RTSN  (BIT(30))
+    #define UART_RTSN_M  (BIT(30))
+    #define UART_RTSN_V  0x1
+    #define UART_RTSN_S  30
+    /* UART_DTRN : RO ;bitpos:[29] ;default: 1'b0 ; */
+    /*description: The level of the internaluart dtr pin*/
+    #define UART_DTRN  (BIT(29))
+    #define UART_DTRN_M  (BIT(29))
+    #define UART_DTRN_V  0x1
+    #define UART_DTRN_S  29
+    /* UART_ST_UTX_OUT : RO ;bitpos:[27:24] ;default: 4'b0 ; */
+    /*description: The state for transmitting data. 4'd0:TX_IDLE*/
+    #define UART_ST_UTX_OUT  0x0000000F
+    #define UART_ST_UTX_OUT_M  ((UART_ST_UTX_OUT_V)<<(UART_ST_UTX_OUT_S))
+    #define UART_ST_UTX_OUT_V  0xF
+    #define UART_ST_UTX_OUT_S  24
+    /* UART_TXFIFO_CNT : RO ;bitpos:[23:16] ;default: 8'b0 ; */
+    /*description: Number of data in UART TX fifo*/
+    #define UART_TXFIFO_CNT  0x000000FF
+    #define UART_TXFIFO_CNT_M  ((UART_TXFIFO_CNT_V)<<(UART_TXFIFO_CNT_S))
+    #define UART_TXFIFO_CNT_V  0xFF
+    #define UART_TXFIFO_CNT_S  16
+    /* UART_RXD : RO ;bitpos:[15] ;default: 1'b0 ; */
+    /*description: The level of the internal uart rxd value*/
+    #define UART_RXD  (BIT(15))
+    #define UART_RXD_M  (BIT(15))
+    #define UART_RXD_V  0x1
+    #define UART_RXD_S  15
+    /* UART_CTSN : RO ;bitpos:[14] ;default: 1'b0 ; */
+    /*description: The level of the internal uart cts value*/
+    #define UART_CTSN  (BIT(14))
+    #define UART_CTSN_M  (BIT(14))
+    #define UART_CTSN_V  0x1
+    #define UART_CTSN_S  14
+    /* UART_DSRN : RO ;bitpos:[13] ;default: 1'b0 ; */
+    /*description: The level of the internal uart dsr value*/
+    #define UART_DSRN  (BIT(13))
+    #define UART_DSRN_M  (BIT(13))
+    #define UART_DSRN_V  0x1
+    #define UART_DSRN_S  13
+    /* UART_ST_URX_OUT : RO ;bitpos:[11:8] ;default: 4'b0 ; */
+    /*description: The state for receiving data. 4‘d0: RX_IDLE*/
+    #define UART_ST_URX_OUT  0x0000000F
+    #define UART_ST_URX_OUT_M  ((UART_ST_URX_OUT_V)<<(UART_ST_URX_OUT_S))
+    #define UART_ST_URX_OUT_V  0xF
+    #define UART_ST_URX_OUT_S  8
+    /* UART_RXFIFO_CNT : RO ;bitpos:[7:0] ;default: 8'b0 ; */
+    /*description: Number of data in UART RX fifo*/
+    #define UART_RXFIFO_CNT  0x000000FF
+    #define UART_RXFIFO_CNT_M  ((UART_RXFIFO_CNT_V)<<(UART_RXFIFO_CNT_S))
+    #define UART_RXFIFO_CNT_V  0xFF
+    #define UART_RXFIFO_CNT_S  0
+        #define UART_GET_TXD(i)  GET_PERI_REG_BITS2(UART_STATUS_REG(i) , UART_TXD_V, UART_TXD_S)
+        #define UART_GET_RTSN(i)  GET_PERI_REG_BITS2(UART_STATUS_REG(i) , UART_RTSN_V, UART_RTSN_S)
+        #define UART_GET_DTRN(i)  GET_PERI_REG_BITS2(UART_STATUS_REG(i) , UART_DTRN_V, UART_DTRN_S)
+        #define UART_GET_ST_UTX_OUT(i)  GET_PERI_REG_BITS2(UART_STATUS_REG(i) , UART_ST_UTX_OUT_V, UART_ST_UTX_OUT_S)
+        #define UART_GET_TXFIFO_CNT(i)  GET_PERI_REG_BITS2(UART_STATUS_REG(i) , UART_TXFIFO_CNT_V, UART_TXFIFO_CNT_S)
+        #define UART_GET_RXD(i)  GET_PERI_REG_BITS2(UART_STATUS_REG(i) , UART_RXD_V, UART_RXD_S)
+        #define UART_GET_CTSN(i)  GET_PERI_REG_BITS2(UART_STATUS_REG(i) , UART_CTSN_V, UART_CTSN_S)
+        #define UART_GET_DSRN(i)  GET_PERI_REG_BITS2(UART_STATUS_REG(i) , UART_DSRN_V, UART_DSRN_S)
+        #define UART_GET_ST_URX_OUT(i)  GET_PERI_REG_BITS2(UART_STATUS_REG(i) , UART_ST_URX_OUT_V, UART_ST_URX_OUT_S)
+        #define UART_GET_RXFIFO_CNT(i)  GET_PERI_REG_BITS2(UART_STATUS_REG(i) , UART_RXFIFO_CNT_V, UART_RXFIFO_CNT_S)
+
+
+
+#define UART_CONF0_REG(i)          (REG_UART_BASE(i) + 0x20)
+    /* UART_TICK_REF_ALWAYS_ON : R/W ;bitpos:[27] ;default: 1'b1 ; */
+    /*description: 1：use apb clock：use referrence clock*/
+    #define UART_TICK_REF_ALWAYS_ON  (BIT(27))
+    #define UART_TICK_REF_ALWAYS_ON_M  (BIT(27))
+    #define UART_TICK_REF_ALWAYS_ON_V  0x1
+    #define UART_TICK_REF_ALWAYS_ON_S  27
+    /* UART_ERR_WR_MASK : R/W ;bitpos:[26] ;default: 1'b0 ; */
+    /*description: 1：rx stop storing data int rxfifo when data is error 0：if received data is wrong*/
+    #define UART_ERR_WR_MASK  (BIT(26))
+    #define UART_ERR_WR_MASK_M  (BIT(26))
+    #define UART_ERR_WR_MASK_V  0x1
+    #define UART_ERR_WR_MASK_S  26
+    /* UART_CLK_EN : R/W ;bitpos:[25] ;default: 1'h0 ; */
+    /*description: 1：force clock on for registers：support clock only when write registers*/
+    #define UART_CLK_EN  (BIT(25))
+    #define UART_CLK_EN_M  (BIT(25))
+    #define UART_CLK_EN_V  0x1
+    #define UART_CLK_EN_S  25
+    /* UART_DTR_INV : R/W ;bitpos:[24] ;default: 1'h0 ; */
+    /*description: Set this bit to inverse uart dtr level*/
+    #define UART_DTR_INV  (BIT(24))
+    #define UART_DTR_INV_M  (BIT(24))
+    #define UART_DTR_INV_V  0x1
+    #define UART_DTR_INV_S  24
+    /* UART_RTS_INV : R/W ;bitpos:[23] ;default: 1'h0 ; */
+    /*description: Set this bit to inverse uart rts level*/
+    #define UART_RTS_INV  (BIT(23))
+    #define UART_RTS_INV_M  (BIT(23))
+    #define UART_RTS_INV_V  0x1
+    #define UART_RTS_INV_S  23
+    /* UART_TXD_INV : R/W ;bitpos:[22] ;default: 1'h0 ; */
+    /*description: Set this bit to inverse uart txd level*/
+    #define UART_TXD_INV  (BIT(22))
+    #define UART_TXD_INV_M  (BIT(22))
+    #define UART_TXD_INV_V  0x1
+    #define UART_TXD_INV_S  22
+    /* UART_DSR_INV : R/W ;bitpos:[21] ;default: 1'h0 ; */
+    /*description: Set this bit to inverse uart dsr level*/
+    #define UART_DSR_INV  (BIT(21))
+    #define UART_DSR_INV_M  (BIT(21))
+    #define UART_DSR_INV_V  0x1
+    #define UART_DSR_INV_S  21
+    /* UART_CTS_INV : R/W ;bitpos:[20] ;default: 1'h0 ; */
+    /*description: Set this bit to inverse uart cts level*/
+    #define UART_CTS_INV  (BIT(20))
+    #define UART_CTS_INV_M  (BIT(20))
+    #define UART_CTS_INV_V  0x1
+    #define UART_CTS_INV_S  20
+    /* UART_RXD_INV : R/W ;bitpos:[19] ;default: 1'h0 ; */
+    /*description: Set this bit to inverse uart rxd level*/
+    #define UART_RXD_INV  (BIT(19))
+    #define UART_RXD_INV_M  (BIT(19))
+    #define UART_RXD_INV_V  0x1
+    #define UART_RXD_INV_S  19
+    /* UART_TXFIFO_RST : R/W ;bitpos:[18] ;default: 1'h0 ; */
+    /*description: Set this bit to reset uart tx fifo*/
+    #define UART_TXFIFO_RST  (BIT(18))
+    #define UART_TXFIFO_RST_M  (BIT(18))
+    #define UART_TXFIFO_RST_V  0x1
+    #define UART_TXFIFO_RST_S  18
+    /* UART_RXFIFO_RST : R/W ;bitpos:[17] ;default: 1'h0 ; */
+    /*description: Set this bit to reset uart rx fifo*/
+    #define UART_RXFIFO_RST  (BIT(17))
+    #define UART_RXFIFO_RST_M  (BIT(17))
+    #define UART_RXFIFO_RST_V  0x1
+    #define UART_RXFIFO_RST_S  17
+    /* UART_IRDA_EN : R/W ;bitpos:[16] ;default: 1'h0 ; */
+    /*description: Set this bit to enable irda protocol*/
+    #define UART_IRDA_EN  (BIT(16))
+    #define UART_IRDA_EN_M  (BIT(16))
+    #define UART_IRDA_EN_V  0x1
+    #define UART_IRDA_EN_S  16
+    /* UART_TX_FLOW_EN : R/W ;bitpos:[15] ;default: 1'b0 ; */
+    /*description: Set this bit to enable tx flow control*/
+    #define UART_TX_FLOW_EN  (BIT(15))
+    #define UART_TX_FLOW_EN_M  (BIT(15))
+    #define UART_TX_FLOW_EN_V  0x1
+    #define UART_TX_FLOW_EN_S  15
+    /* UART_LOOPBACK : R/W ;bitpos:[14] ;default: 1'b0 ; */
+    /*description: Set this bit to enable uart loopback test mode*/
+    #define UART_LOOPBACK  (BIT(14))
+    #define UART_LOOPBACK_M  (BIT(14))
+    #define UART_LOOPBACK_V  0x1
+    #define UART_LOOPBACK_S  14
+    /* UART_IRDA_RX_INV : R/W ;bitpos:[13] ;default: 1'b0 ; */
+    /*description: Set this bit to inverse irda rx level*/
+    #define UART_IRDA_RX_INV  (BIT(13))
+    #define UART_IRDA_RX_INV_M  (BIT(13))
+    #define UART_IRDA_RX_INV_V  0x1
+    #define UART_IRDA_RX_INV_S  13
+    /* UART_IRDA_TX_INV : R/W ;bitpos:[12] ;default: 1'b0 ; */
+    /*description: Set this bit to inverse irda tx level*/
+    #define UART_IRDA_TX_INV  (BIT(12))
+    #define UART_IRDA_TX_INV_M  (BIT(12))
+    #define UART_IRDA_TX_INV_V  0x1
+    #define UART_IRDA_TX_INV_S  12
+    /* UART_IRDA_WCTL : R/W ;bitpos:[11] ;default: 1'b0 ; */
+    /*description: 1：the tx 11th bit is the same to the 10th bit 0：set tx 11th bit to 0*/
+    #define UART_IRDA_WCTL  (BIT(11))
+    #define UART_IRDA_WCTL_M  (BIT(11))
+    #define UART_IRDA_WCTL_V  0x1
+    #define UART_IRDA_WCTL_S  11
+    /* UART_IRDA_TX_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
+    /*description: Set this bit to enable irda to send data*/
+    #define UART_IRDA_TX_EN  (BIT(10))
+    #define UART_IRDA_TX_EN_M  (BIT(10))
+    #define UART_IRDA_TX_EN_V  0x1
+    #define UART_IRDA_TX_EN_S  10
+    /* UART_IRDA_DPLX : R/W ;bitpos:[9] ;default: 1'b0 ; */
+    /*description: Set this bit to enable irda duplex mode*/
+    #define UART_IRDA_DPLX  (BIT(9))
+    #define UART_IRDA_DPLX_M  (BIT(9))
+    #define UART_IRDA_DPLX_V  0x1
+    #define UART_IRDA_DPLX_S  9
+    /* UART_TXD_BRK : R/W ;bitpos:[8] ;default: 1'b0 ; */
+    /*description: Set this bit to enbale tx send 0*/
+    #define UART_TXD_BRK  (BIT(8))
+    #define UART_TXD_BRK_M  (BIT(8))
+    #define UART_TXD_BRK_V  0x1
+    #define UART_TXD_BRK_S  8
+    /* UART_SW_DTR : R/W ;bitpos:[7] ;default: 1'b0 ; */
+    /*description: sw dtr*/
+    #define UART_SW_DTR  (BIT(7))
+    #define UART_SW_DTR_M  (BIT(7))
+    #define UART_SW_DTR_V  0x1
+    #define UART_SW_DTR_S  7
+    /* UART_SW_RTS : R/W ;bitpos:[6] ;default: 1'b0 ; */
+    /*description: sw rts*/
+    #define UART_SW_RTS  (BIT(6))
+    #define UART_SW_RTS_M  (BIT(6))
+    #define UART_SW_RTS_V  0x1
+    #define UART_SW_RTS_S  6
+    /* UART_STOP_BIT_NUM : R/W ;bitpos:[5:4] ;default: 2'd1 ; */
+    /*description: Set stop bit: 1:1bit  2:1.5bits  3:2bits*/
+    #define UART_STOP_BIT_NUM  0x00000003
+    #define UART_STOP_BIT_NUM_M  ((UART_STOP_BIT_NUM_V)<<(UART_STOP_BIT_NUM_S))
+    #define UART_STOP_BIT_NUM_V  0x3
+    #define UART_STOP_BIT_NUM_S  4
+    /* UART_BIT_NUM : R/W ;bitpos:[3:2] ;default: 2'd3 ; */
+    /*description: Set bit num:  0:5bits 1:6bits 2:7bits 3:8bits*/
+    #define UART_BIT_NUM  0x00000003
+    #define UART_BIT_NUM_M  ((UART_BIT_NUM_V)<<(UART_BIT_NUM_S))
+    #define UART_BIT_NUM_V  0x3
+    #define UART_BIT_NUM_S  2
+    /* UART_PARITY_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */
+    /*description: Set this bit to enable uart parity check*/
+    #define UART_PARITY_EN  (BIT(1))
+    #define UART_PARITY_EN_M  (BIT(1))
+    #define UART_PARITY_EN_V  0x1
+    #define UART_PARITY_EN_S  1
+    /* UART_PARITY : R/W ;bitpos:[0] ;default: 1'b0 ; */
+    /*description: Set parity check:  0:even 1:odd*/
+    #define UART_PARITY  (BIT(0))
+    #define UART_PARITY_M  (BIT(0))
+    #define UART_PARITY_V  0x1
+    #define UART_PARITY_S  0
+        #define UART_GET_TICK_REF_ALWAYS_ON(i)  GET_PERI_REG_BITS2(UART_CONF0_REG(i) , UART_TICK_REF_ALWAYS_ON_V, UART_TICK_REF_ALWAYS_ON_S)
+        #define UART_SET_TICK_REF_ALWAYS_ON(i,val)  SET_PERI_REG_BITS(UART_CONF0_REG(i) ,UART_TICK_REF_ALWAYS_ON_V,(val),UART_TICK_REF_ALWAYS_ON_S)
+        #define UART_GET_ERR_WR_MASK(i)  GET_PERI_REG_BITS2(UART_CONF0_REG(i) , UART_ERR_WR_MASK_V, UART_ERR_WR_MASK_S)
+        #define UART_SET_ERR_WR_MASK(i,val)  SET_PERI_REG_BITS(UART_CONF0_REG(i) ,UART_ERR_WR_MASK_V,(val),UART_ERR_WR_MASK_S)
+        #define UART_GET_REG_CLK_EN(i)  GET_PERI_REG_BITS2(UART_CONF0_REG(i) , UART_CLK_EN_V, UART_CLK_EN_S)
+        #define UART_SET_REG_CLK_EN(i,val)  SET_PERI_REG_BITS(UART_CONF0_REG(i) ,UART_CLK_EN_V,(val),UART_CLK_EN_S)
+        #define UART_GET_DTR_INV(i)  GET_PERI_REG_BITS2(UART_CONF0_REG(i) , UART_DTR_INV_V, UART_DTR_INV_S)
+        #define UART_SET_DTR_INV(i,val)  SET_PERI_REG_BITS(UART_CONF0_REG(i) ,UART_DTR_INV_V,(val),UART_DTR_INV_S)
+        #define UART_GET_RTS_INV(i)  GET_PERI_REG_BITS2(UART_CONF0_REG(i) , UART_RTS_INV_V, UART_RTS_INV_S)
+        #define UART_SET_RTS_INV(i,val)  SET_PERI_REG_BITS(UART_CONF0_REG(i) ,UART_RTS_INV_V,(val),UART_RTS_INV_S)
+        #define UART_GET_TXD_INV(i)  GET_PERI_REG_BITS2(UART_CONF0_REG(i) , UART_TXD_INV_V, UART_TXD_INV_S)
+        #define UART_SET_TXD_INV(i,val)  SET_PERI_REG_BITS(UART_CONF0_REG(i) ,UART_TXD_INV_V,(val),UART_TXD_INV_S)
+        #define UART_GET_DSR_INV(i)  GET_PERI_REG_BITS2(UART_CONF0_REG(i) , UART_DSR_INV_V, UART_DSR_INV_S)
+        #define UART_SET_DSR_INV(i,val)  SET_PERI_REG_BITS(UART_CONF0_REG(i) ,UART_DSR_INV_V,(val),UART_DSR_INV_S)
+        #define UART_GET_CTS_INV(i)  GET_PERI_REG_BITS2(UART_CONF0_REG(i) , UART_CTS_INV_V, UART_CTS_INV_S)
+        #define UART_SET_CTS_INV(i,val)  SET_PERI_REG_BITS(UART_CONF0_REG(i) ,UART_CTS_INV_V,(val),UART_CTS_INV_S)
+        #define UART_GET_RXD_INV(i)  GET_PERI_REG_BITS2(UART_CONF0_REG(i) , UART_RXD_INV_V, UART_RXD_INV_S)
+        #define UART_SET_RXD_INV(i,val)  SET_PERI_REG_BITS(UART_CONF0_REG(i) ,UART_RXD_INV_V,(val),UART_RXD_INV_S)
+        #define UART_GET_TXFIFO_RST(i)  GET_PERI_REG_BITS2(UART_CONF0_REG(i) , UART_TXFIFO_RST_V, UART_TXFIFO_RST_S)
+        #define UART_SET_TXFIFO_RST(i,val)  SET_PERI_REG_BITS(UART_CONF0_REG(i) ,UART_TXFIFO_RST_V,(val),UART_TXFIFO_RST_S)
+        #define UART_GET_RXFIFO_RST(i)  GET_PERI_REG_BITS2(UART_CONF0_REG(i) , UART_RXFIFO_RST_V, UART_RXFIFO_RST_S)
+        #define UART_SET_RXFIFO_RST(i,val)  SET_PERI_REG_BITS(UART_CONF0_REG(i) ,UART_RXFIFO_RST_V,(val),UART_RXFIFO_RST_S)
+        #define UART_GET_IRDA_EN(i)  GET_PERI_REG_BITS2(UART_CONF0_REG(i) , UART_IRDA_EN_V, UART_IRDA_EN_S)
+        #define UART_SET_IRDA_EN(i,val)  SET_PERI_REG_BITS(UART_CONF0_REG(i) ,UART_IRDA_EN_V,(val),UART_IRDA_EN_S)
+        #define UART_GET_TX_FLOW_EN(i)  GET_PERI_REG_BITS2(UART_CONF0_REG(i) , UART_TX_FLOW_EN_V, UART_TX_FLOW_EN_S)
+        #define UART_SET_TX_FLOW_EN(i,val)  SET_PERI_REG_BITS(UART_CONF0_REG(i) ,UART_TX_FLOW_EN_V,(val),UART_TX_FLOW_EN_S)
+        #define UART_GET_LOOPBACK(i)  GET_PERI_REG_BITS2(UART_CONF0_REG(i) , UART_LOOPBACK_V, UART_LOOPBACK_S)
+        #define UART_SET_LOOPBACK(i,val)  SET_PERI_REG_BITS(UART_CONF0_REG(i) ,UART_LOOPBACK_V,(val),UART_LOOPBACK_S)
+        #define UART_GET_IRDA_RX_INV(i)  GET_PERI_REG_BITS2(UART_CONF0_REG(i) , UART_IRDA_RX_INV_V, UART_IRDA_RX_INV_S)
+        #define UART_SET_IRDA_RX_INV(i,val)  SET_PERI_REG_BITS(UART_CONF0_REG(i) ,UART_IRDA_RX_INV_V,(val),UART_IRDA_RX_INV_S)
+        #define UART_GET_IRDA_TX_INV(i)  GET_PERI_REG_BITS2(UART_CONF0_REG(i) , UART_IRDA_TX_INV_V, UART_IRDA_TX_INV_S)
+        #define UART_SET_IRDA_TX_INV(i,val)  SET_PERI_REG_BITS(UART_CONF0_REG(i) ,UART_IRDA_TX_INV_V,(val),UART_IRDA_TX_INV_S)
+        #define UART_GET_IRDA_WCTL(i)  GET_PERI_REG_BITS2(UART_CONF0_REG(i) , UART_IRDA_WCTL_V, UART_IRDA_WCTL_S)
+        #define UART_SET_IRDA_WCTL(i,val)  SET_PERI_REG_BITS(UART_CONF0_REG(i) ,UART_IRDA_WCTL_V,(val),UART_IRDA_WCTL_S)
+        #define UART_GET_IRDA_TX_EN(i)  GET_PERI_REG_BITS2(UART_CONF0_REG(i) , UART_IRDA_TX_EN_V, UART_IRDA_TX_EN_S)
+        #define UART_SET_IRDA_TX_EN(i,val)  SET_PERI_REG_BITS(UART_CONF0_REG(i) ,UART_IRDA_TX_EN_V,(val),UART_IRDA_TX_EN_S)
+        #define UART_GET_IRDA_DPLX(i)  GET_PERI_REG_BITS2(UART_CONF0_REG(i) , UART_IRDA_DPLX_V, UART_IRDA_DPLX_S)
+        #define UART_SET_IRDA_DPLX(i,val)  SET_PERI_REG_BITS(UART_CONF0_REG(i) ,UART_IRDA_DPLX_V,(val),UART_IRDA_DPLX_S)
+        #define UART_GET_TXD_BRK(i)  GET_PERI_REG_BITS2(UART_CONF0_REG(i) , UART_TXD_BRK_V, UART_TXD_BRK_S)
+        #define UART_SET_TXD_BRK(i,val)  SET_PERI_REG_BITS(UART_CONF0_REG(i) ,UART_TXD_BRK_V,(val),UART_TXD_BRK_S)
+        #define UART_GET_SW_DTR(i)  GET_PERI_REG_BITS2(UART_CONF0_REG(i) , UART_SW_DTR_V, UART_SW_DTR_S)
+        #define UART_SET_SW_DTR(i,val)  SET_PERI_REG_BITS(UART_CONF0_REG(i) ,UART_SW_DTR_V,(val),UART_SW_DTR_S)
+        #define UART_GET_SW_RTS(i)  GET_PERI_REG_BITS2(UART_CONF0_REG(i) , UART_SW_RTS_V, UART_SW_RTS_S)
+        #define UART_SET_SW_RTS(i,val)  SET_PERI_REG_BITS(UART_CONF0_REG(i) ,UART_SW_RTS_V,(val),UART_SW_RTS_S)
+        #define UART_GET_STOP_BIT_NUM(i)  GET_PERI_REG_BITS2(UART_CONF0_REG(i) , UART_STOP_BIT_NUM_V, UART_STOP_BIT_NUM_S)
+        #define UART_SET_STOP_BIT_NUM(i,val)  SET_PERI_REG_BITS(UART_CONF0_REG(i) ,UART_STOP_BIT_NUM_V,(val),UART_STOP_BIT_NUM_S)
+        #define UART_GET_BIT_NUM(i)  GET_PERI_REG_BITS2(UART_CONF0_REG(i) , UART_BIT_NUM_V, UART_BIT_NUM_S)
+        #define UART_SET_BIT_NUM(i,val)  SET_PERI_REG_BITS(UART_CONF0_REG(i) ,UART_BIT_NUM_V,(val),UART_BIT_NUM_S)
+        #define UART_GET_PARITY_EN(i)  GET_PERI_REG_BITS2(UART_CONF0_REG(i) , UART_PARITY_EN_V, UART_PARITY_EN_S)
+        #define UART_SET_PARITY_EN(i,val)  SET_PERI_REG_BITS(UART_CONF0_REG(i) ,UART_PARITY_EN_V,(val),UART_PARITY_EN_S)
+        #define UART_GET_PARITY(i)  GET_PERI_REG_BITS2(UART_CONF0_REG(i) , UART_PARITY_V, UART_PARITY_S)
+        #define UART_SET_PARITY(i,val)  SET_PERI_REG_BITS(UART_CONF0_REG(i) ,UART_PARITY_V,(val),UART_PARITY_S)
+
+
+
+#define UART_CONF1_REG(i)          (REG_UART_BASE(i) + 0x24)
+    /* UART_RX_TOUT_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
+    /*description: Set this bit to enable rx time-out function*/
+    #define UART_RX_TOUT_EN  (BIT(31))
+    #define UART_RX_TOUT_EN_M  (BIT(31))
+    #define UART_RX_TOUT_EN_V  0x1
+    #define UART_RX_TOUT_EN_S  31
+    /* UART_RX_TOUT_THRHD : R/W ;bitpos:[30:24] ;default: 7'b0 ; */
+    /*description: Config bits for rx time-out threshold*/
+    #define UART_RX_TOUT_THRHD  0x0000007F
+    #define UART_RX_TOUT_THRHD_M  ((UART_RX_TOUT_THRHD_V)<<(UART_RX_TOUT_THRHD_S))
+    #define UART_RX_TOUT_THRHD_V  0x7F
+    #define UART_RX_TOUT_THRHD_S  24
+    /* UART_RX_FLOW_EN : R/W ;bitpos:[23] ;default: 1'b0 ; */
+    /*description: Set this bit to enable rx hardware flow control*/
+    #define UART_RX_FLOW_EN  (BIT(23))
+    #define UART_RX_FLOW_EN_M  (BIT(23))
+    #define UART_RX_FLOW_EN_V  0x1
+    #define UART_RX_FLOW_EN_S  23
+    /* UART_RX_FLOW_THRHD : R/W ;bitpos:[22:16] ;default: 7'h0 ; */
+    /*description: The config bits for rx flow control threshold*/
+    #define UART_RX_FLOW_THRHD  0x0000007F
+    #define UART_RX_FLOW_THRHD_M  ((UART_RX_FLOW_THRHD_V)<<(UART_RX_FLOW_THRHD_S))
+    #define UART_RX_FLOW_THRHD_V  0x7F
+    #define UART_RX_FLOW_THRHD_S  16
+    /* UART_TXFIFO_EMPTY_THRHD : R/W ;bitpos:[14:8] ;default: 7'h60 ; */
+    /*description: The config bits for tx fifo empty threshold*/
+    #define UART_TXFIFO_EMPTY_THRHD  0x0000007F
+    #define UART_TXFIFO_EMPTY_THRHD_M  ((UART_TXFIFO_EMPTY_THRHD_V)<<(UART_TXFIFO_EMPTY_THRHD_S))
+    #define UART_TXFIFO_EMPTY_THRHD_V  0x7F
+    #define UART_TXFIFO_EMPTY_THRHD_S  8
+    /* UART_RXFIFO_FULL_THRHD : R/W ;bitpos:[6:0] ;default: 7'h60 ; */
+    /*description: The config bits for rx fifo full threshold*/
+    #define UART_RXFIFO_FULL_THRHD  0x0000007F
+    #define UART_RXFIFO_FULL_THRHD_M  ((UART_RXFIFO_FULL_THRHD_V)<<(UART_RXFIFO_FULL_THRHD_S))
+    #define UART_RXFIFO_FULL_THRHD_V  0x7F
+    #define UART_RXFIFO_FULL_THRHD_S  0
+        #define UART_GET_RX_TOUT_EN(i)  GET_PERI_REG_BITS2(UART_CONF1_REG(i) , UART_RX_TOUT_EN_V, UART_RX_TOUT_EN_S)
+        #define UART_SET_RX_TOUT_EN(i,val)  SET_PERI_REG_BITS(UART_CONF1_REG(i) ,UART_RX_TOUT_EN_V,(val),UART_RX_TOUT_EN_S)
+        #define UART_GET_RX_TOUT_THRHD(i)  GET_PERI_REG_BITS2(UART_CONF1_REG(i) , UART_RX_TOUT_THRHD_V, UART_RX_TOUT_THRHD_S)
+        #define UART_SET_RX_TOUT_THRHD(i,val)  SET_PERI_REG_BITS(UART_CONF1_REG(i) ,UART_RX_TOUT_THRHD_V,(val),UART_RX_TOUT_THRHD_S)
+        #define UART_GET_RX_FLOW_EN(i)  GET_PERI_REG_BITS2(UART_CONF1_REG(i) , UART_RX_FLOW_EN_V, UART_RX_FLOW_EN_S)
+        #define UART_SET_RX_FLOW_EN(i,val)  SET_PERI_REG_BITS(UART_CONF1_REG(i) ,UART_RX_FLOW_EN_V,(val),UART_RX_FLOW_EN_S)
+        #define UART_GET_RX_FLOW_THRHD(i)  GET_PERI_REG_BITS2(UART_CONF1_REG(i) , UART_RX_FLOW_THRHD_V, UART_RX_FLOW_THRHD_S)
+        #define UART_SET_RX_FLOW_THRHD(i,val)  SET_PERI_REG_BITS(UART_CONF1_REG(i) ,UART_RX_FLOW_THRHD_V,(val),UART_RX_FLOW_THRHD_S)
+        #define UART_GET_TXFIFO_EMPTY_THRHD(i)  GET_PERI_REG_BITS2(UART_CONF1_REG(i) , UART_TXFIFO_EMPTY_THRHD_V, UART_TXFIFO_EMPTY_THRHD_S)
+        #define UART_SET_TXFIFO_EMPTY_THRHD(i,val)  SET_PERI_REG_BITS(UART_CONF1_REG(i) ,UART_TXFIFO_EMPTY_THRHD_V,(val),UART_TXFIFO_EMPTY_THRHD_S)
+        #define UART_GET_RXFIFO_FULL_THRHD(i)  GET_PERI_REG_BITS2(UART_CONF1_REG(i) , UART_RXFIFO_FULL_THRHD_V, UART_RXFIFO_FULL_THRHD_S)
+        #define UART_SET_RXFIFO_FULL_THRHD(i,val)  SET_PERI_REG_BITS(UART_CONF1_REG(i) ,UART_RXFIFO_FULL_THRHD_V,(val),UART_RXFIFO_FULL_THRHD_S)
+
+
+
+#define UART_LOWPULSE_REG(i)          (REG_UART_BASE(i) + 0x28)
+    /* UART_LOWPULSE_MIN_CNT : RO ;bitpos:[19:0] ;default: 20'hFFFFF ; */
+    /*description: used in baudrate detect*/
+    #define UART_LOWPULSE_MIN_CNT  0x000FFFFF
+    #define UART_LOWPULSE_MIN_CNT_M  ((UART_LOWPULSE_MIN_CNT_V)<<(UART_LOWPULSE_MIN_CNT_S))
+    #define UART_LOWPULSE_MIN_CNT_V  0xFFFFF
+    #define UART_LOWPULSE_MIN_CNT_S  0
+        #define UART_GET_LOWPULSE_MIN_CNT(i)  GET_PERI_REG_BITS2(UART_LOWPULSE_REG(i) , UART_LOWPULSE_MIN_CNT_V, UART_LOWPULSE_MIN_CNT_S)
+
+
+
+#define UART_HIGHPULSE_REG(i)          (REG_UART_BASE(i) + 0x2C)
+    /* UART_HIGHPULSE_MIN_CNT : RO ;bitpos:[19:0] ;default: 20'hFFFFF ; */
+    /*description: used in baudrate detect*/
+    #define UART_HIGHPULSE_MIN_CNT  0x000FFFFF
+    #define UART_HIGHPULSE_MIN_CNT_M  ((UART_HIGHPULSE_MIN_CNT_V)<<(UART_HIGHPULSE_MIN_CNT_S))
+    #define UART_HIGHPULSE_MIN_CNT_V  0xFFFFF
+    #define UART_HIGHPULSE_MIN_CNT_S  0
+        #define UART_GET_HIGHPULSE_MIN_CNT(i)  GET_PERI_REG_BITS2(UART_HIGHPULSE_REG(i) , UART_HIGHPULSE_MIN_CNT_V, UART_HIGHPULSE_MIN_CNT_S)
+
+
+
+#define UART_RXD_CNT_REG(i)          (REG_UART_BASE(i) + 0x30)
+    /* UART_RXD_EDGE_CNT : RO ;bitpos:[9:0] ;default: 10'h0 ; */
+    /*description: used in baudrate detect*/
+    #define UART_RXD_EDGE_CNT  0x000003FF
+    #define UART_RXD_EDGE_CNT_M  ((UART_RXD_EDGE_CNT_V)<<(UART_RXD_EDGE_CNT_S))
+    #define UART_RXD_EDGE_CNT_V  0x3FF
+    #define UART_RXD_EDGE_CNT_S  0
+        #define UART_GET_RXD_EDGE_CNT(i)  GET_PERI_REG_BITS2(UART_RXD_CNT_REG(i) , UART_RXD_EDGE_CNT_V, UART_RXD_EDGE_CNT_S)
+
+
+
+#define UART_FLOW_CONF_REG(i)          (REG_UART_BASE(i) + 0x34)
+    /* UART_SEND_XOFF : R/W ;bitpos:[5] ;default: 1'b0 ; */
+    /*description: */
+    #define UART_SEND_XOFF  (BIT(5))
+    #define UART_SEND_XOFF_M  (BIT(5))
+    #define UART_SEND_XOFF_V  0x1
+    #define UART_SEND_XOFF_S  5
+    /* UART_SEND_XON : R/W ;bitpos:[4] ;default: 1'b0 ; */
+    /*description: */
+    #define UART_SEND_XON  (BIT(4))
+    #define UART_SEND_XON_M  (BIT(4))
+    #define UART_SEND_XON_V  0x1
+    #define UART_SEND_XON_S  4
+    /* UART_FORCE_XOFF : R/W ;bitpos:[3] ;default: 1'b0 ; */
+    /*description: Set this bit to set ctsn*/
+    #define UART_FORCE_XOFF  (BIT(3))
+    #define UART_FORCE_XOFF_M  (BIT(3))
+    #define UART_FORCE_XOFF_V  0x1
+    #define UART_FORCE_XOFF_S  3
+    /* UART_FORCE_XON : R/W ;bitpos:[2] ;default: 1'b0 ; */
+    /*description: Set this bit to clear ctsn*/
+    #define UART_FORCE_XON  (BIT(2))
+    #define UART_FORCE_XON_M  (BIT(2))
+    #define UART_FORCE_XON_V  0x1
+    #define UART_FORCE_XON_S  2
+    /* UART_XONOFF_DEL : R/W ;bitpos:[1] ;default: 1'b0 ; */
+    /*description: Set this bit to remove flow control char from rx data*/
+    #define UART_XONOFF_DEL  (BIT(1))
+    #define UART_XONOFF_DEL_M  (BIT(1))
+    #define UART_XONOFF_DEL_V  0x1
+    #define UART_XONOFF_DEL_S  1
+    /* UART_SW_FLOW_CON_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
+    /*description: Set this bit to enable sw flow control*/
+    #define UART_SW_FLOW_CON_EN  (BIT(0))
+    #define UART_SW_FLOW_CON_EN_M  (BIT(0))
+    #define UART_SW_FLOW_CON_EN_V  0x1
+    #define UART_SW_FLOW_CON_EN_S  0
+        #define UART_GET_SEND_XOFF(i)  GET_PERI_REG_BITS2(UART_FLOW_CONF_REG(i) , UART_SEND_XOFF_V, UART_SEND_XOFF_S)
+        #define UART_SET_SEND_XOFF(i,val)  SET_PERI_REG_BITS(UART_FLOW_CONF_REG(i) ,UART_SEND_XOFF_V,(val),UART_SEND_XOFF_S)
+        #define UART_GET_SEND_XON(i)  GET_PERI_REG_BITS2(UART_FLOW_CONF_REG(i) , UART_SEND_XON_V, UART_SEND_XON_S)
+        #define UART_SET_SEND_XON(i,val)  SET_PERI_REG_BITS(UART_FLOW_CONF_REG(i) ,UART_SEND_XON_V,(val),UART_SEND_XON_S)
+        #define UART_GET_FORCE_XOFF(i)  GET_PERI_REG_BITS2(UART_FLOW_CONF_REG(i) , UART_FORCE_XOFF_V, UART_FORCE_XOFF_S)
+        #define UART_SET_FORCE_XOFF(i,val)  SET_PERI_REG_BITS(UART_FLOW_CONF_REG(i) ,UART_FORCE_XOFF_V,(val),UART_FORCE_XOFF_S)
+        #define UART_GET_FORCE_XON(i)  GET_PERI_REG_BITS2(UART_FLOW_CONF_REG(i) , UART_FORCE_XON_V, UART_FORCE_XON_S)
+        #define UART_SET_FORCE_XON(i,val)  SET_PERI_REG_BITS(UART_FLOW_CONF_REG(i) ,UART_FORCE_XON_V,(val),UART_FORCE_XON_S)
+        #define UART_GET_XONOFF_DEL(i)  GET_PERI_REG_BITS2(UART_FLOW_CONF_REG(i) , UART_XONOFF_DEL_V, UART_XONOFF_DEL_S)
+        #define UART_SET_XONOFF_DEL(i,val)  SET_PERI_REG_BITS(UART_FLOW_CONF_REG(i) ,UART_XONOFF_DEL_V,(val),UART_XONOFF_DEL_S)
+        #define UART_GET_SW_FLOW_CON_EN(i)  GET_PERI_REG_BITS2(UART_FLOW_CONF_REG(i) , UART_SW_FLOW_CON_EN_V, UART_SW_FLOW_CON_EN_S)
+        #define UART_SET_SW_FLOW_CON_EN(i,val)  SET_PERI_REG_BITS(UART_FLOW_CONF_REG(i) ,UART_SW_FLOW_CON_EN_V,(val),UART_SW_FLOW_CON_EN_S)
+
+
+
+#define UART_SLEEP_CONF_REG(i)          (REG_UART_BASE(i) + 0x38)
+    /* UART_ACTIVE_THRESHOLD : R/W ;bitpos:[9:0] ;default: 10'hf0 ; */
+    /*description: when the num of rx level change is more than this value*/
+    #define UART_ACTIVE_THRESHOLD  0x000003FF
+    #define UART_ACTIVE_THRESHOLD_M  ((UART_ACTIVE_THRESHOLD_V)<<(UART_ACTIVE_THRESHOLD_S))
+    #define UART_ACTIVE_THRESHOLD_V  0x3FF
+    #define UART_ACTIVE_THRESHOLD_S  0
+        #define UART_GET_ACTIVE_THRESHOLD(i)  GET_PERI_REG_BITS2(UART_SLEEP_CONF_REG(i) , UART_ACTIVE_THRESHOLD_V, UART_ACTIVE_THRESHOLD_S)
+        #define UART_SET_ACTIVE_THRESHOLD(i,val)  SET_PERI_REG_BITS(UART_SLEEP_CONF_REG(i) ,UART_ACTIVE_THRESHOLD_V,(val),UART_ACTIVE_THRESHOLD_S)
+
+
+
+#define UART_SWFC_CONF_REG(i)          (REG_UART_BASE(i) + 0x3C)
+    /* UART_XOFF_CHAR : R/W ;bitpos:[31:24] ;default: 8'h13 ; */
+    /*description: xoff char*/
+    #define UART_XOFF_CHAR  0x000000FF
+    #define UART_XOFF_CHAR_M  ((UART_XOFF_CHAR_V)<<(UART_XOFF_CHAR_S))
+    #define UART_XOFF_CHAR_V  0xFF
+    #define UART_XOFF_CHAR_S  24
+    /* UART_XON_CHAR : R/W ;bitpos:[23:16] ;default: 8'h11 ; */
+    /*description: xon char*/
+    #define UART_XON_CHAR  0x000000FF
+    #define UART_XON_CHAR_M  ((UART_XON_CHAR_V)<<(UART_XON_CHAR_S))
+    #define UART_XON_CHAR_V  0xFF
+    #define UART_XON_CHAR_S  16
+    /* UART_XOFF_THRESHOLD : R/W ;bitpos:[15:8] ;default: 8'he0 ; */
+    /*description: rx stop receiving data when rxfifo_cnt is more than this value*/
+    #define UART_XOFF_THRESHOLD  0x000000FF
+    #define UART_XOFF_THRESHOLD_M  ((UART_XOFF_THRESHOLD_V)<<(UART_XOFF_THRESHOLD_S))
+    #define UART_XOFF_THRESHOLD_V  0xFF
+    #define UART_XOFF_THRESHOLD_S  8
+    /* UART_XON_THRESHOLD : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
+    /*description: rx continue receiving data when rxfifo cnt is less then this value*/
+    #define UART_XON_THRESHOLD  0x000000FF
+    #define UART_XON_THRESHOLD_M  ((UART_XON_THRESHOLD_V)<<(UART_XON_THRESHOLD_S))
+    #define UART_XON_THRESHOLD_V  0xFF
+    #define UART_XON_THRESHOLD_S  0
+        #define UART_GET_XOFF_CH(i)  GET_PERI_REG_BITS2(UART_SWFC_CONF_REG(i) , UART_XOFF_CHAR_V, UART_XOFF_CHAR_S)
+        #define UART_SET_XOFF_CH(i,val)  SET_PERI_REG_BITS(UART_SWFC_CONF_REG(i) ,UART_XOFF_CHAR_V,(val),UART_XOFF_CHAR_S)
+        #define UART_GET_XON_CH(i)  GET_PERI_REG_BITS2(UART_SWFC_CONF_REG(i) , UART_XON_CHAR_V, UART_XON_CHAR_S)
+        #define UART_SET_XON_CH(i,val)  SET_PERI_REG_BITS(UART_SWFC_CONF_REG(i) ,UART_XON_CHAR_V,(val),UART_XON_CHAR_S)
+        #define UART_GET_XOFF_THRESHOLD(i)  GET_PERI_REG_BITS2(UART_SWFC_CONF_REG(i) , UART_XOFF_THRESHOLD_V, UART_XOFF_THRESHOLD_S)
+        #define UART_SET_XOFF_THRESHOLD(i,val)  SET_PERI_REG_BITS(UART_SWFC_CONF_REG(i) ,UART_XOFF_THRESHOLD_V,(val),UART_XOFF_THRESHOLD_S)
+        #define UART_GET_XON_THRESHOLD(i)  GET_PERI_REG_BITS2(UART_SWFC_CONF_REG(i) , UART_XON_THRESHOLD_V, UART_XON_THRESHOLD_S)
+        #define UART_SET_XON_THRESHOLD(i,val)  SET_PERI_REG_BITS(UART_SWFC_CONF_REG(i) ,UART_XON_THRESHOLD_V,(val),UART_XON_THRESHOLD_S)
+
+
+
+#define UART_IDLE_CONF_REG(i)          (REG_UART_BASE(i) + 0x40)
+    /* UART_TX_BRK_NUM : R/W ;bitpos:[27:20] ;default: 8'ha ; */
+    /*description: brk number config*/
+    #define UART_TX_BRK_NUM  0x000000FF
+    #define UART_TX_BRK_NUM_M  ((UART_TX_BRK_NUM_V)<<(UART_TX_BRK_NUM_S))
+    #define UART_TX_BRK_NUM_V  0xFF
+    #define UART_TX_BRK_NUM_S  20
+    /* UART_TX_IDLE_NUM : R/W ;bitpos:[19:10] ;default: 10'h100 ; */
+    /*description: idle number config*/
+    #define UART_TX_IDLE_NUM  0x000003FF
+    #define UART_TX_IDLE_NUM_M  ((UART_TX_IDLE_NUM_V)<<(UART_TX_IDLE_NUM_S))
+    #define UART_TX_IDLE_NUM_V  0x3FF
+    #define UART_TX_IDLE_NUM_S  10
+    /* UART_RX_IDLE_THRHD : R/W ;bitpos:[9:0] ;default: 10'h100 ; */
+    /*description: rx idle number config*/
+    #define UART_RX_IDLE_THRHD  0x000003FF
+    #define UART_RX_IDLE_THRHD_M  ((UART_RX_IDLE_THRHD_V)<<(UART_RX_IDLE_THRHD_S))
+    #define UART_RX_IDLE_THRHD_V  0x3FF
+    #define UART_RX_IDLE_THRHD_S  0
+        #define UART_GET_TX_BRK_NUM(i)  GET_PERI_REG_BITS2(UART_IDLE_CONF_REG(i) , UART_TX_BRK_NUM_V, UART_TX_BRK_NUM_S)
+        #define UART_SET_TX_BRK_NUM(i,val)  SET_PERI_REG_BITS(UART_IDLE_CONF_REG(i) ,UART_TX_BRK_NUM_V,(val),UART_TX_BRK_NUM_S)
+        #define UART_GET_TX_IDLE_NUM(i)  GET_PERI_REG_BITS2(UART_IDLE_CONF_REG(i) , UART_TX_IDLE_NUM_V, UART_TX_IDLE_NUM_S)
+        #define UART_SET_TX_IDLE_NUM(i,val)  SET_PERI_REG_BITS(UART_IDLE_CONF_REG(i) ,UART_TX_IDLE_NUM_V,(val),UART_TX_IDLE_NUM_S)
+        #define UART_GET_RX_IDLE_THRHD(i)  GET_PERI_REG_BITS2(UART_IDLE_CONF_REG(i) , UART_RX_IDLE_THRHD_V, UART_RX_IDLE_THRHD_S)
+        #define UART_SET_RX_IDLE_THRHD(i,val)  SET_PERI_REG_BITS(UART_IDLE_CONF_REG(i) ,UART_RX_IDLE_THRHD_V,(val),UART_RX_IDLE_THRHD_S)
+
+
+
+#define UART_RS485_CONF_REG(i)          (REG_UART_BASE(i) + 0x44)
+    /* UART_RS485_TX_DLY_NUM : R/W ;bitpos:[9:6] ;default: 4'b0 ; */
+    /*description: config this reg to delay tx signal*/
+    #define UART_RS485_TX_DLY_NUM  0x0000000F
+    #define UART_RS485_TX_DLY_NUM_M  ((UART_RS485_TX_DLY_NUM_V)<<(UART_RS485_TX_DLY_NUM_S))
+    #define UART_RS485_TX_DLY_NUM_V  0xF
+    #define UART_RS485_TX_DLY_NUM_S  6
+    /* UART_RS485_RX_DLY_NUM : R/W ;bitpos:[5] ;default: 1'b0 ; */
+    /*description: config this reg to delay rx signal*/
+    #define UART_RS485_RX_DLY_NUM  (BIT(5))
+    #define UART_RS485_RX_DLY_NUM_M  (BIT(5))
+    #define UART_RS485_RX_DLY_NUM_V  0x1
+    #define UART_RS485_RX_DLY_NUM_S  5
+    /* UART_RS485RXBY_TX_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */
+    /*description: set this bit to enable tx when rx is busy*/
+    #define UART_RS485RXBY_TX_EN  (BIT(4))
+    #define UART_RS485RXBY_TX_EN_M  (BIT(4))
+    #define UART_RS485RXBY_TX_EN_V  0x1
+    #define UART_RS485RXBY_TX_EN_S  4
+    /* UART_RS485TX_RX_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */
+    /*description: set this bit to enable rx receiving when tx is sending*/
+    #define UART_RS485TX_RX_EN  (BIT(3))
+    #define UART_RS485TX_RX_EN_M  (BIT(3))
+    #define UART_RS485TX_RX_EN_V  0x1
+    #define UART_RS485TX_RX_EN_S  3
+    /* UART_DL1_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */
+    /*description: set this bit to add 1 bit stop bit(after data)*/
+    #define UART_DL1_EN  (BIT(2))
+    #define UART_DL1_EN_M  (BIT(2))
+    #define UART_DL1_EN_V  0x1
+    #define UART_DL1_EN_S  2
+    /* UART_DL0_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */
+    /*description: set this bit to add 1 bit stop bit(before data)*/
+    #define UART_DL0_EN  (BIT(1))
+    #define UART_DL0_EN_M  (BIT(1))
+    #define UART_DL0_EN_V  0x1
+    #define UART_DL0_EN_S  1
+    /* UART_RS485_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
+    /*description: set this bit to enable rs485 protocol*/
+    #define UART_RS485_EN  (BIT(0))
+    #define UART_RS485_EN_M  (BIT(0))
+    #define UART_RS485_EN_V  0x1
+    #define UART_RS485_EN_S  0
+        #define UART_GET_RS485_TX_DLY_NUM(i)  GET_PERI_REG_BITS2(UART_RS485_CONF_REG(i) , UART_RS485_TX_DLY_NUM_V, UART_RS485_TX_DLY_NUM_S)
+        #define UART_SET_RS485_TX_DLY_NUM(i,val)  SET_PERI_REG_BITS(UART_RS485_CONF_REG(i) ,UART_RS485_TX_DLY_NUM_V,(val),UART_RS485_TX_DLY_NUM_S)
+        #define UART_GET_RS485_RX_DLY_NUM(i)  GET_PERI_REG_BITS2(UART_RS485_CONF_REG(i) , UART_RS485_RX_DLY_NUM_V, UART_RS485_RX_DLY_NUM_S)
+        #define UART_SET_RS485_RX_DLY_NUM(i,val)  SET_PERI_REG_BITS(UART_RS485_CONF_REG(i) ,UART_RS485_RX_DLY_NUM_V,(val),UART_RS485_RX_DLY_NUM_S)
+        #define UART_GET_RS485RXBY_TX_EN(i)  GET_PERI_REG_BITS2(UART_RS485_CONF_REG(i) , UART_RS485RXBY_TX_EN_V, UART_RS485RXBY_TX_EN_S)
+        #define UART_SET_RS485RXBY_TX_EN(i,val)  SET_PERI_REG_BITS(UART_RS485_CONF_REG(i) ,UART_RS485RXBY_TX_EN_V,(val),UART_RS485RXBY_TX_EN_S)
+        #define UART_GET_RS485TX_RX_EN(i)  GET_PERI_REG_BITS2(UART_RS485_CONF_REG(i) , UART_RS485TX_RX_EN_V, UART_RS485TX_RX_EN_S)
+        #define UART_SET_RS485TX_RX_EN(i,val)  SET_PERI_REG_BITS(UART_RS485_CONF_REG(i) ,UART_RS485TX_RX_EN_V,(val),UART_RS485TX_RX_EN_S)
+        #define UART_GET_DL1_EN(i)  GET_PERI_REG_BITS2(UART_RS485_CONF_REG(i) , UART_DL1_EN_V, UART_DL1_EN_S)
+        #define UART_SET_DL1_EN(i,val)  SET_PERI_REG_BITS(UART_RS485_CONF_REG(i) ,UART_DL1_EN_V,(val),UART_DL1_EN_S)
+        #define UART_GET_DL0_EN(i)  GET_PERI_REG_BITS2(UART_RS485_CONF_REG(i) , UART_DL0_EN_V, UART_DL0_EN_S)
+        #define UART_SET_DL0_EN(i,val)  SET_PERI_REG_BITS(UART_RS485_CONF_REG(i) ,UART_DL0_EN_V,(val),UART_DL0_EN_S)
+        #define UART_GET_RS485_EN(i)  GET_PERI_REG_BITS2(UART_RS485_CONF_REG(i) , UART_RS485_EN_V, UART_RS485_EN_S)
+        #define UART_SET_RS485_EN(i,val)  SET_PERI_REG_BITS(UART_RS485_CONF_REG(i) ,UART_RS485_EN_V,(val),UART_RS485_EN_S)
+
+
+
+#define UART_AT_CMD_PRECNT_REG(i)          (REG_UART_BASE(i) + 0x48)
+    /* UART_PRE_IDLE_NUM : R/W ;bitpos:[23:0] ;default: 24'h186a00 ; */
+    /*description: config the idle time before receiving AT_CMD*/
+    #define UART_PRE_IDLE_NUM  0x00FFFFFF
+    #define UART_PRE_IDLE_NUM_M  ((UART_PRE_IDLE_NUM_V)<<(UART_PRE_IDLE_NUM_S))
+    #define UART_PRE_IDLE_NUM_V  0xFFFFFF
+    #define UART_PRE_IDLE_NUM_S  0
+        #define UART_GET_PRE_IDLE_NUM(i)  GET_PERI_REG_BITS2(UART_AT_CMD_PRECNT_REG(i) , UART_PRE_IDLE_NUM_V, UART_PRE_IDLE_NUM_S)
+        #define UART_SET_PRE_IDLE_NUM(i,val)  SET_PERI_REG_BITS(UART_AT_CMD_PRECNT_REG(i) ,UART_PRE_IDLE_NUM_V,(val),UART_PRE_IDLE_NUM_S)
+
+
+
+#define UART_AT_CMD_POSTCNT_REG(i)          (REG_UART_BASE(i) + 0x4c)
+    /* UART_POST_IDLE_NUM : R/W ;bitpos:[23:0] ;default: 24'h186a00 ; */
+    /*description: config the idle time after receiving AT_CMD*/
+    #define UART_POST_IDLE_NUM  0x00FFFFFF
+    #define UART_POST_IDLE_NUM_M  ((UART_POST_IDLE_NUM_V)<<(UART_POST_IDLE_NUM_S))
+    #define UART_POST_IDLE_NUM_V  0xFFFFFF
+    #define UART_POST_IDLE_NUM_S  0
+        #define UART_GET_POST_IDLE_NUM(i)  GET_PERI_REG_BITS2(UART_AT_CMD_POSTCNT_REG(i) , UART_POST_IDLE_NUM_V, UART_POST_IDLE_NUM_S)
+        #define UART_SET_POST_IDLE_NUM(i,val)  SET_PERI_REG_BITS(UART_AT_CMD_POSTCNT_REG(i) ,UART_POST_IDLE_NUM_V,(val),UART_POST_IDLE_NUM_S)
+
+
+
+#define UART_AT_CMD_GAPTOUT_REG(i)          (REG_UART_BASE(i) + 0x50)
+    /* UART_RX_GAP_TOUT : R/W ;bitpos:[23:0] ;default: 24'h1e00 ; */
+    /*description: config the time between receiving two AT_CMD*/
+    #define UART_RX_GAP_TOUT  0x00FFFFFF
+    #define UART_RX_GAP_TOUT_M  ((UART_RX_GAP_TOUT_V)<<(UART_RX_GAP_TOUT_S))
+    #define UART_RX_GAP_TOUT_V  0xFFFFFF
+    #define UART_RX_GAP_TOUT_S  0
+        #define UART_GET_RX_GAP_TOUT(i)  GET_PERI_REG_BITS2(UART_AT_CMD_GAPTOUT_REG(i) , UART_RX_GAP_TOUT_V, UART_RX_GAP_TOUT_S)
+        #define UART_SET_RX_GAP_TOUT(i,val)  SET_PERI_REG_BITS(UART_AT_CMD_GAPTOUT_REG(i) ,UART_RX_GAP_TOUT_V,(val),UART_RX_GAP_TOUT_S)
+
+
+
+#define UART_AT_CMD_CHAR_REG(i)          (REG_UART_BASE(i) + 0x54)
+    /* UART_CHAR_NUM : R/W ;bitpos:[15:8] ;default: 8'd3 ; */
+    /*description: config the continous num of AT_CMD*/
+    #define UART_CHAR_NUM  0x000000FF
+    #define UART_CHAR_NUM_M  ((UART_CHAR_NUM_V)<<(UART_CHAR_NUM_S))
+    #define UART_CHAR_NUM_V  0xFF
+    #define UART_CHAR_NUM_S  8
+    /* UART_AT_CMD_CHAR : R/W ;bitpos:[7:0] ;default: 8'h2b ; */
+    /*description: config AT_CMD*/
+    #define UART_AT_CMD_CHAR  0x000000FF
+    #define UART_AT_CMD_CHAR_M  ((UART_AT_CMD_CHAR_V)<<(UART_AT_CMD_CHAR_S))
+    #define UART_AT_CMD_CHAR_V  0xFF
+    #define UART_AT_CMD_CHAR_S  0
+        #define UART_GET_CHAR_NUM(i)  GET_PERI_REG_BITS2(UART_AT_CMD_CHAR_REG(i) , UART_CHAR_NUM_V, UART_CHAR_NUM_S)
+        #define UART_SET_CHAR_NUM(i,val)  SET_PERI_REG_BITS(UART_AT_CMD_CHAR_REG(i) ,UART_CHAR_NUM_V,(val),UART_CHAR_NUM_S)
+        #define UART_GET_AT_CMD_CHAR(i)  GET_PERI_REG_BITS2(UART_AT_CMD_CHAR_REG(i) , UART_AT_CMD_CHAR_V, UART_AT_CMD_CHAR_S)
+        #define UART_SET_AT_CMD_CHAR(i,val)  SET_PERI_REG_BITS(UART_AT_CMD_CHAR_REG(i) ,UART_AT_CMD_CHAR_V,(val),UART_AT_CMD_CHAR_S)
+
+
+
+#define UART_MEM_CONF_REG(i)          (REG_UART_BASE(i) + 0x58)
+    /* UART_TX_MEM_EMPTY_THRHD : R/W ;bitpos:[30:28] ;default: 3'h0 ; */
+    /*description: the most significant bits of tx fifo empty threashold*/
+    #define UART_TX_MEM_EMPTY_THRHD  0x00000007
+    #define UART_TX_MEM_EMPTY_THRHD_M  ((UART_TX_MEM_EMPTY_THRHD_V)<<(UART_TX_MEM_EMPTY_THRHD_S))
+    #define UART_TX_MEM_EMPTY_THRHD_V  0x7
+    #define UART_TX_MEM_EMPTY_THRHD_S  28
+    /* UART_RX_MEM_FULL_THRHD : R/W ;bitpos:[27:25] ;default: 3'h0 ; */
+    /*description: the most significant bits of rx fifo full threashold*/
+    #define UART_RX_MEM_FULL_THRHD  0x00000007
+    #define UART_RX_MEM_FULL_THRHD_M  ((UART_RX_MEM_FULL_THRHD_V)<<(UART_RX_MEM_FULL_THRHD_S))
+    #define UART_RX_MEM_FULL_THRHD_V  0x7
+    #define UART_RX_MEM_FULL_THRHD_S  25
+    /* UART_XOFF_THRESHOLD_H2 : R/W ;bitpos:[24:23] ;default: 2'h0 ; */
+    /*description: the most significant bits of uart xoff flow threashold*/
+    #define UART_XOFF_THRESHOLD_H2  0x00000003
+    #define UART_XOFF_THRESHOLD_H2_M  ((UART_XOFF_THRESHOLD_H2_V)<<(UART_XOFF_THRESHOLD_H2_S))
+    #define UART_XOFF_THRESHOLD_H2_V  0x3
+    #define UART_XOFF_THRESHOLD_H2_S  23
+    /* UART_XON_THRESHOLD_H2 : R/W ;bitpos:[22:21] ;default: 2'h0 ; */
+    /*description: the most significant bits of uart xon flow threshold*/
+    #define UART_XON_THRESHOLD_H2  0x00000003
+    #define UART_XON_THRESHOLD_H2_M  ((UART_XON_THRESHOLD_H2_V)<<(UART_XON_THRESHOLD_H2_S))
+    #define UART_XON_THRESHOLD_H2_V  0x3
+    #define UART_XON_THRESHOLD_H2_S  21
+    /* UART_RX_TOUT_THRHD_H3 : R/W ;bitpos:[20:18] ;default: 3h0 ; */
+    /*description: the most significant bits of rx timeout threshold*/
+    #define UART_RX_TOUT_THRHD_H3  0x00000007
+    #define UART_RX_TOUT_THRHD_H3_M  ((UART_RX_TOUT_THRHD_H3_V)<<(UART_RX_TOUT_THRHD_H3_S))
+    #define UART_RX_TOUT_THRHD_H3_V  0x7
+    #define UART_RX_TOUT_THRHD_H3_S  18
+    /* UART_RX_FLOW_THRHD_H3 : R/W ;bitpos:[17:15] ;default: 3'h0 ; */
+    /*description: the most significant bits of  rx flow control threshold*/
+    #define UART_RX_FLOW_THRHD_H3  0x00000007
+    #define UART_RX_FLOW_THRHD_H3_M  ((UART_RX_FLOW_THRHD_H3_V)<<(UART_RX_FLOW_THRHD_H3_S))
+    #define UART_RX_FLOW_THRHD_H3_V  0x7
+    #define UART_RX_FLOW_THRHD_H3_S  15
+    /* UART_TX_SIZE : R/W ;bitpos:[10:7] ;default: 3'h0 ; */
+    /*description: config tx_mem's size(128*reg_rx_size)*/
+    #define UART_TX_SIZE  0x0000000F
+    #define UART_TX_SIZE_M  ((UART_TX_SIZE_V)<<(UART_TX_SIZE_S))
+    #define UART_TX_SIZE_V  0xF
+    #define UART_TX_SIZE_S  7
+    /* UART_RX_SIZE : R/W ;bitpos:[6:3] ;default: 3'h0 ; */
+    /*description: config rx mem's size(128*reg_rx_size)*/
+    #define UART_RX_SIZE  0x0000000F
+    #define UART_RX_SIZE_M  ((UART_RX_SIZE_V)<<(UART_RX_SIZE_S))
+    #define UART_RX_SIZE_V  0xF
+    #define UART_RX_SIZE_S  3
+    /* UART_MEM_PD : R/W ;bitpos:[0] ;default: 1'b0 ; */
+    /*description: set this bit to pull_down mem's pd signal*/
+    #define UART_MEM_PD  (BIT(0))
+    #define UART_MEM_PD_M  (BIT(0))
+    #define UART_MEM_PD_V  0x1
+    #define UART_MEM_PD_S  0
+        #define UART_GET_TX_MEM_EMPTY_THRHD(i)  GET_PERI_REG_BITS2(UART_MEM_CONF_REG(i) , UART_TX_MEM_EMPTY_THRHD_V, UART_TX_MEM_EMPTY_THRHD_S)
+        #define UART_SET_TX_MEM_EMPTY_THRHD(i,val)  SET_PERI_REG_BITS(UART_MEM_CONF_REG(i) ,UART_TX_MEM_EMPTY_THRHD_V,(val),UART_TX_MEM_EMPTY_THRHD_S)
+        #define UART_GET_RX_MEM_FULL_THRHD(i)  GET_PERI_REG_BITS2(UART_MEM_CONF_REG(i) , UART_RX_MEM_FULL_THRHD_V, UART_RX_MEM_FULL_THRHD_S)
+        #define UART_SET_RX_MEM_FULL_THRHD(i,val)  SET_PERI_REG_BITS(UART_MEM_CONF_REG(i) ,UART_RX_MEM_FULL_THRHD_V,(val),UART_RX_MEM_FULL_THRHD_S)
+        #define UART_GET_XOFF_THRESHOLD_H2(i)  GET_PERI_REG_BITS2(UART_MEM_CONF_REG(i) , UART_XOFF_THRESHOLD_H2_V, UART_XOFF_THRESHOLD_H2_S)
+        #define UART_SET_XOFF_THRESHOLD_H2(i,val)  SET_PERI_REG_BITS(UART_MEM_CONF_REG(i) ,UART_XOFF_THRESHOLD_H2_V,(val),UART_XOFF_THRESHOLD_H2_S)
+        #define UART_GET_XON_THRESHOLD_H2(i)  GET_PERI_REG_BITS2(UART_MEM_CONF_REG(i) , UART_XON_THRESHOLD_H2_V, UART_XON_THRESHOLD_H2_S)
+        #define UART_SET_XON_THRESHOLD_H2(i,val)  SET_PERI_REG_BITS(UART_MEM_CONF_REG(i) ,UART_XON_THRESHOLD_H2_V,(val),UART_XON_THRESHOLD_H2_S)
+        #define UART_GET_RX_TOUT_THRHD_H3(i)  GET_PERI_REG_BITS2(UART_MEM_CONF_REG(i) , UART_RX_TOUT_THRHD_H3_V, UART_RX_TOUT_THRHD_H3_S)
+        #define UART_SET_RX_TOUT_THRHD_H3(i,val)  SET_PERI_REG_BITS(UART_MEM_CONF_REG(i) ,UART_RX_TOUT_THRHD_H3_V,(val),UART_RX_TOUT_THRHD_H3_S)
+        #define UART_GET_RX_FLOW_THRHD_H3(i)  GET_PERI_REG_BITS2(UART_MEM_CONF_REG(i) , UART_RX_FLOW_THRHD_H3_V, UART_RX_FLOW_THRHD_H3_S)
+        #define UART_SET_RX_FLOW_THRHD_H3(i,val)  SET_PERI_REG_BITS(UART_MEM_CONF_REG(i) ,UART_RX_FLOW_THRHD_H3_V,(val),UART_RX_FLOW_THRHD_H3_S)
+        #define UART_GET_REG_TX_SIZE(i)  GET_PERI_REG_BITS2(UART_MEM_CONF_REG(i) , UART_TX_SIZE_V, UART_TX_SIZE_S)
+        #define UART_SET_REG_TX_SIZE(i,val)  SET_PERI_REG_BITS(UART_MEM_CONF_REG(i) ,UART_TX_SIZE_V,(val),UART_TX_SIZE_S)
+        #define UART_GET_REG_RX_SIZE(i)  GET_PERI_REG_BITS2(UART_MEM_CONF_REG(i) , UART_RX_SIZE_V, UART_RX_SIZE_S)
+        #define UART_SET_REG_RX_SIZE(i,val)  SET_PERI_REG_BITS(UART_MEM_CONF_REG(i) ,UART_RX_SIZE_V,(val),UART_RX_SIZE_S)
+        #define UART_GET_REG_MEM_PD(i)  GET_PERI_REG_BITS2(UART_MEM_CONF_REG(i) , UART_MEM_PD_V, UART_MEM_PD_S)
+        #define UART_SET_REG_MEM_PD(i,val)  SET_PERI_REG_BITS(UART_MEM_CONF_REG(i) ,UART_MEM_PD_V,(val),UART_MEM_PD_S)
+
+
+
+#define UART_MEM_TX_STATUS_REG(i)          (REG_UART_BASE(i) + 0x5c)
+    /* UART_TX_RADDR_CHX : RO ;bitpos:[23:13] ;default: 11'b0 ; */
+    /*description: uartx tx mem's read address*/
+    #define UART_TX_RADDR_CHX  0x000007FF
+    #define UART_TX_RADDR_CHX_M  ((UART_TX_RADDR_CHX_V)<<(UART_TX_RADDR_CHX_S))
+    #define UART_TX_RADDR_CHX_V  0x7FF
+    #define UART_TX_RADDR_CHX_S  13
+    /* UART_APB_TX_WADDR_CHX : RO ;bitpos:[12:2] ;default: 11'b0 ; */
+    /*description: uartx tx mem's write address*/
+    #define UART_APB_TX_WADDR_CHX  0x000007FF
+    #define UART_APB_TX_WADDR_CHX_M  ((UART_APB_TX_WADDR_CHX_V)<<(UART_APB_TX_WADDR_CHX_S))
+    #define UART_APB_TX_WADDR_CHX_V  0x7FF
+    #define UART_APB_TX_WADDR_CHX_S  2
+        #define UART_GET_TX_RADDR_CHX(i)  GET_PERI_REG_BITS2(UART_MEM_TX_STATUS_REG(i) , UART_TX_RADDR_CHX_V, UART_TX_RADDR_CHX_S)
+        #define UART_GET_APB_TX_WADDR_CHX(i)  GET_PERI_REG_BITS2(UART_MEM_TX_STATUS_REG(i) , UART_APB_TX_WADDR_CHX_V, UART_APB_TX_WADDR_CHX_S)
+
+
+
+#define UART_MEM_RX_STATUS_REG(i)          (REG_UART_BASE(i) + 0x60)
+    /* UART_RX_WADDR_CHX : RO ;bitpos:[23:13] ;default: 11'b0 ; */
+    /*description: uartx rx mem's write address*/
+    #define UART_RX_WADDR_CHX  0x000007FF
+    #define UART_RX_WADDR_CHX_M  ((UART_RX_WADDR_CHX_V)<<(UART_RX_WADDR_CHX_S))
+    #define UART_RX_WADDR_CHX_V  0x7FF
+    #define UART_RX_WADDR_CHX_S  13
+    /* UART_APB_RX_RADDR_CHX : RO ;bitpos:[12:2] ;default: 11'b0 ; */
+    /*description: uartx rx mem's read address*/
+    #define UART_APB_RX_RADDR_CHX  0x000007FF
+    #define UART_APB_RX_RADDR_CHX_M  ((UART_APB_RX_RADDR_CHX_V)<<(UART_APB_RX_RADDR_CHX_S))
+    #define UART_APB_RX_RADDR_CHX_V  0x7FF
+    #define UART_APB_RX_RADDR_CHX_S  2
+        #define UART_GET_RX_WADDR_CHX(i)  GET_PERI_REG_BITS2(UART_MEM_RX_STATUS_REG(i) , UART_RX_WADDR_CHX_V, UART_RX_WADDR_CHX_S)
+        #define UART_GET_APB_RX_RADDR_CHX(i)  GET_PERI_REG_BITS2(UART_MEM_RX_STATUS_REG(i) , UART_APB_RX_RADDR_CHX_V, UART_APB_RX_RADDR_CHX_S)
+
+
+
+#define UART_DATE_REG(i)          (REG_UART_BASE(i) + 0x78)
+    /* UART_DATE : R/W ;bitpos:[31:0] ;default: 32'h15122500 ; */
+    /*description: */
+    #define UART_DATE  0xFFFFFFFF
+    #define UART_DATE_M  ((UART_DATE_V)<<(UART_DATE_S))
+    #define UART_DATE_V  0xFFFFFFFF
+    #define UART_DATE_S  0
+        #define UART_GET_DATE(i)  GET_PERI_REG_BITS2(UART_DATE_REG(i) , UART_DATE_V, UART_DATE_S)
+        #define UART_SET_DATE(i,val)  SET_PERI_REG_BITS(UART_DATE_REG(i) ,UART_DATE_V,(val),UART_DATE_S)
+
+
+
+#define UART_ID_REG(i)          (REG_UART_BASE(i) + 0x7C)
+    /* UART_ID : R/W ;bitpos:[31:0] ;default: 32'h0500 ; */
+    /*description: */
+    #define UART_ID  0xFFFFFFFF
+    #define UART_ID_M  ((UART_ID_V)<<(UART_ID_S))
+    #define UART_ID_V  0xFFFFFFFF
+    #define UART_ID_S  0
+        #define UART_GET_ID(i)  GET_PERI_REG_BITS2(UART_ID_REG(i) , UART_ID_V, UART_ID_S)
+        #define UART_SET_ID(i,val)  SET_PERI_REG_BITS(UART_ID_REG(i) ,UART_ID_V,(val),UART_ID_S)
+
+
+
+
+
+
+#endif /* _SOC_UART_REG_H_ */
+
+

components/esp32/include/soc/uhci0_reg.h

@@ -0,0 +1,350 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_UHCI0_REG_H_
+#define _SOC_UHCI0_REG_H_
+
+#include "soc.h"
+
+#define UHCI0_CONF0 ( DR_REG_UHCI0_BASE + 0x0)
+#define UHCI0_UART_RX_BRK_EOF_EN (BIT(22))
+#define UHCI0_CLK_EN (BIT(21))
+#define UHCI0_ENCODE_CRC_EN (BIT(20))
+#define UHCI0_LEN_EOF_EN (BIT(19))
+#define UHCI0_UART_IDLE_EOF_EN (BIT(18))
+#define UHCI0_CRC_REC_EN (BIT(17))
+#define UHCI0_HEAD_EN (BIT(16))
+#define UHCI0_SEPER_EN (BIT(15))
+#define UHCI0_MEM_TRANS_EN (BIT(14))
+#define UHCI0_RX_DATA_BURST_EN (BIT(13))
+#define UHCI0_TXDSCR_BURST_EN (BIT(12))
+#define UHCI0_RXDSCR_BURST_EN (BIT(11))
+#define UHCI0_UART1_CE (BIT(10))
+#define UHCI0_UART0_CE (BIT(9))
+#define UHCI0_TO_EOF_MODE (BIT(8))
+#define UHCI0_RX_NO_RESTART_CLR (BIT(7))
+#define UHCI0_RX_AUTO_WRBACK (BIT(6))
+#define UHCI0_RX_LOOP_TEST (BIT(5))
+#define UHCI0_TX_LOOP_TEST (BIT(4))
+#define UHCI0_AHBM_RST (BIT(3))
+#define UHCI0_AHBM_FIFO_RST (BIT(2))
+#define UHCI0_RX_RST (BIT(1))
+#define UHCI0_TX_RST (BIT(0))
+
+#define UHCI0_INT_RAW ( DR_REG_UHCI0_BASE + 0x4)
+#define UHCI0_UHCI_SEND_A_Q_INT_RAW (BIT(15))
+#define UHCI0_UHCI_SEND_S_Q_INT_RAW (BIT(14))
+#define UHCI0_UHCI_TO_TOTAL_EOF_INT_RAW (BIT(13))
+#define UHCI0_UHCI_RXLINK_EOF_ERR_INT_RAW (BIT(12))
+#define UHCI0_UHCI_TX_DSCR_EMPTY_INT_RAW (BIT(11))
+#define UHCI0_UHCI_RX_DSCR_ERR_INT_RAW (BIT(10))
+#define UHCI0_UHCI_TX_DSCR_ERR_INT_RAW (BIT(9))
+#define UHCI0_UHCI_TO_EOF_INT_RAW (BIT(8))
+#define UHCI0_UHCI_RX_DONE_INT_RAW (BIT(7))
+#define UHCI0_UHCI_FROM_ERR_EOF_INT_RAW (BIT(6))
+#define UHCI0_UHCI_FROM_SUC_EOF_INT_RAW (BIT(5))
+#define UHCI0_UHCI_TX_DONE_INT_RAW (BIT(4))
+#define UHCI0_UHCI_TX_HUNG_INT_RAW (BIT(3))
+#define UHCI0_UHCI_RX_HUNG_INT_RAW (BIT(2))
+#define UHCI0_UHCI_TX_START_INT_RAW (BIT(1))
+#define UHCI0_UHCI_RX_START_INT_RAW (BIT(0))
+
+#define UHCI0_INT_ST ( DR_REG_UHCI0_BASE + 0x8)
+#define UHCI0_UHCI_SEND_A_Q_INT_ST (BIT(15))
+#define UHCI0_UHCI_SEND_S_Q_INT_ST (BIT(14))
+#define UHCI0_UHCI_TO_TOTAL_EOF_INT_ST (BIT(13))
+#define UHCI0_UHCI_RXLINK_EOF_ERR_INT_ST (BIT(12))
+#define UHCI0_UHCI_TX_DSCR_EMPTY_INT_ST (BIT(11))
+#define UHCI0_UHCI_RX_DSCR_ERR_INT_ST (BIT(10))
+#define UHCI0_UHCI_TX_DSCR_ERR_INT_ST (BIT(9))
+#define UHCI0_UHCI_TO_EOF_INT_ST (BIT(8))
+#define UHCI0_UHCI_RX_DONE_INT_ST (BIT(7))
+#define UHCI0_UHCI_FROM_ERR_EOF_INT_ST (BIT(6))
+#define UHCI0_UHCI_FROM_SUC_EOF_INT_ST (BIT(5))
+#define UHCI0_UHCI_TX_DONE_INT_ST (BIT(4))
+#define UHCI0_UHCI_TX_HUNG_INT_ST (BIT(3))
+#define UHCI0_UHCI_RX_HUNG_INT_ST (BIT(2))
+#define UHCI0_UHCI_TX_START_INT_ST (BIT(1))
+#define UHCI0_UHCI_RX_START_INT_ST (BIT(0))
+
+#define UHCI0_INT_ENA ( DR_REG_UHCI0_BASE + 0xC)
+#define UHCI0_UHCI_SEND_A_Q_INT_ENA (BIT(15))
+#define UHCI0_UHCI_SEND_S_Q_INT_ENA (BIT(14))
+#define UHCI0_UHCI_TO_TOTAL_EOF_INT_ENA (BIT(13))
+#define UHCI0_UHCI_RXLINK_EOF_ERR_INT_ENA (BIT(12))
+#define UHCI0_UHCI_TX_DSCR_EMPTY_INT_ENA (BIT(11))
+#define UHCI0_UHCI_RX_DSCR_ERR_INT_ENA (BIT(10))
+#define UHCI0_UHCI_TX_DSCR_ERR_INT_ENA (BIT(9))
+#define UHCI0_UHCI_TO_EOF_INT_ENA (BIT(8))
+#define UHCI0_UHCI_RX_DONE_INT_ENA (BIT(7))
+#define UHCI0_UHCI_FROM_ERR_EOF_INT_ENA (BIT(6))
+#define UHCI0_UHCI_FROM_SUC_EOF_INT_ENA (BIT(5))
+#define UHCI0_UHCI_TX_DONE_INT_ENA (BIT(4))
+#define UHCI0_UHCI_TX_HUNG_INT_ENA (BIT(3))
+#define UHCI0_UHCI_RX_HUNG_INT_ENA (BIT(2))
+#define UHCI0_UHCI_TX_START_INT_ENA (BIT(1))
+#define UHCI0_UHCI_RX_START_INT_ENA (BIT(0))
+
+#define UHCI0_INT_CLR ( DR_REG_UHCI0_BASE + 0x10)
+#define UHCI0_SEND_A_REG_Q_INT_CLR (BIT(15))
+#define UHCI0_SEND_S_REG_Q_INT_CLR (BIT(14))
+#define UHCI0_TO_TOTAL_EOF_INT_CLR (BIT(13))
+#define UHCI0_RXLINK_EOF_ERR_INT_CLR (BIT(12))
+#define UHCI0_TX_DSCR_EMPTY_INT_CLR (BIT(11))
+#define UHCI0_RX_DSCR_ERR_INT_CLR (BIT(10))
+#define UHCI0_TX_DSCR_ERR_INT_CLR (BIT(9))
+#define UHCI0_TO_EOF_INT_CLR (BIT(8))
+#define UHCI0_RX_DONE_INT_CLR (BIT(7))
+#define UHCI0_FROM_ERR_EOF_INT_CLR (BIT(6))
+#define UHCI0_FROM_SUC_EOF_INT_CLR (BIT(5))
+#define UHCI0_TX_DONE_INT_CLR (BIT(4))
+#define UHCI0_TX_HUNG_INT_CLR (BIT(3))
+#define UHCI0_RX_HUNG_INT_CLR (BIT(2))
+#define UHCI0_TX_START_INT_CLR (BIT(1))
+#define UHCI0_RX_START_INT_CLR (BIT(0))
+
+#define UHCI0_RX_STATUS ( DR_REG_UHCI0_BASE + 0x14)
+#define UHCI0_RX_EMPTY (BIT(1))
+#define UHCI0_RX_FULL (BIT(0))
+
+#define UHCI0_RXFIFO_PUSH ( DR_REG_UHCI0_BASE + 0x18)
+#define UHCI0_RXFIFO_PUSH_EN (BIT(16))
+#define UHCI0_RXFIFO_WDATA 0x000001FF
+#define UHCI0_RXFIFO_WDATA_S 0
+
+#define UHCI0_TX_STATUS ( DR_REG_UHCI0_BASE + 0x1C)
+#define UHCI0_UHCI_RX_ERR_CAUSE 0x00000007
+#define UHCI0_UHCI_RX_ERR_CAUSE_S 4
+#define UHCI0_TX_EMPTY (BIT(1))
+#define UHCI0_TX_FULL (BIT(0))
+
+#define UHCI0_TX_POP ( DR_REG_UHCI0_BASE + 0x20)
+#define UHCI0_TXFIFO_POP (BIT(16))
+#define UHCI0_TXFIFO_RDATA 0x00000FFF
+#define UHCI0_TXFIFO_RDATA_S 0
+
+#define UHCI0_RX_LINK ( DR_REG_UHCI0_BASE + 0x24)
+#define UHCI0_UHCI_RXLINK_PARK (BIT(31))
+#define UHCI0_RXLINK_RESTART (BIT(30))
+#define UHCI0_RXLINK_START (BIT(29))
+#define UHCI0_RXLINK_STOP (BIT(28))
+#define UHCI0_RXLINK_ADDR 0x000FFFFF
+#define UHCI0_RXLINK_ADDR_S 0
+
+#define UHCI0_TX_LINK ( DR_REG_UHCI0_BASE + 0x28)
+#define UHCI0_UHCI_TXLINK_PARK (BIT(31))
+#define UHCI0_TXLINK_RESTART (BIT(30))
+#define UHCI0_TXLINK_START (BIT(29))
+#define UHCI0_TXLINK_STOP (BIT(28))
+#define UHCI0_TXLINK_AUTO_RET (BIT(20))
+#define UHCI0_TXLINK_ADDR 0x000FFFFF
+#define UHCI0_TXLINK_ADDR_S 0
+
+#define UHCI0_CONF1 ( DR_REG_UHCI0_BASE + 0x2C)
+#define UHCI0_SW_START (BIT(8))
+#define UHCI0_WAIT_SW_START (BIT(7))
+#define UHCI0_CHECK_OWNER (BIT(6))
+#define UHCI0_TX_ACK_NUM_RE (BIT(5))
+#define UHCI0_TX_CHECK_SUM_RE (BIT(4))
+#define UHCI0_SAVE_HEAD (BIT(3))
+#define UHCI0_CRC_DISABLE (BIT(2))
+#define UHCI0_CHECK_SEQ_EN (BIT(1))
+#define UHCI0_CHECK_SUM_EN (BIT(0))
+
+#define UHCI0_STATE0 ( DR_REG_UHCI0_BASE + 0x30)
+#define UHCI0_UHCI_STATE0 0xFFFFFFFF
+#define UHCI0_UHCI_STATE0_S 0
+
+#define UHCI0_STATE1 ( DR_REG_UHCI0_BASE + 0x34)
+#define UHCI0_UHCI_STATE1 0xFFFFFFFF
+#define UHCI0_UHCI_STATE1_S 0
+
+#define UHCI0_RX_EOF_DES_ADDR ( DR_REG_UHCI0_BASE + 0x38)
+#define UHCI0_TO_EOF_DES_ADDR 0xFFFFFFFF
+#define UHCI0_TO_EOF_DES_ADDR_S 0
+
+#define UHCI0_TX_SUC_EOF_DES_ADDR ( DR_REG_UHCI0_BASE + 0x3C)
+#define UHCI0_FROM_SUC_EOF_DES_ADDR 0xFFFFFFFF
+#define UHCI0_FROM_SUC_EOF_DES_ADDR_S 0
+
+#define UHCI0_TX_ERR_EOF_DES_ADDR ( DR_REG_UHCI0_BASE + 0x40)
+#define UHCI0_FROM_ERR_EOF_DES_ADDR 0xFFFFFFFF
+#define UHCI0_FROM_ERR_EOF_DES_ADDR_S 0
+
+#define UHCI0_RX_EOF_BFR_DES_ADDR ( DR_REG_UHCI0_BASE + 0x44)
+#define UHCI0_TO_EOF_BFR_DES_ADDR 0xFFFFFFFF
+#define UHCI0_TO_EOF_BFR_DES_ADDR_S 0
+
+#define UHCI0_AHB_TEST ( DR_REG_UHCI0_BASE + 0x48)
+#define UHCI0_AHB_TESTADDR 0x00000003
+#define UHCI0_AHB_TESTADDR_S 4
+#define UHCI0_AHB_TESTMODE 0x00000007
+#define UHCI0_AHB_TESTMODE_S 0
+
+#define UHCI0_TX_DSCR ( DR_REG_UHCI0_BASE + 0x4C)
+#define UHCI0_TXLINK_DSCR 0xFFFFFFFF
+#define UHCI0_TXLINK_DSCR_S 0
+
+#define UHCI0_TX_DSCR_BF0 ( DR_REG_UHCI0_BASE + 0x50)
+#define UHCI0_TXLINK_DSCR_BF0 0xFFFFFFFF
+#define UHCI0_TXLINK_DSCR_BF0_S 0
+
+#define UHCI0_TX_DSCR_BF1 ( DR_REG_UHCI0_BASE + 0x54)
+#define UHCI0_TXLINK_DSCR_BF1 0xFFFFFFFF
+#define UHCI0_TXLINK_DSCR_BF1_S 0
+
+#define UHCI0_RX_DSCR ( DR_REG_UHCI0_BASE + 0x58)
+#define UHCI0_RXLINK_DSCR 0xFFFFFFFF
+#define UHCI0_RXLINK_DSCR_S 0
+
+#define UHCI0_RX_DSCR_BF0 ( DR_REG_UHCI0_BASE + 0x5C)
+#define UHCI0_RXLINK_DSCR_BF0 0xFFFFFFFF
+#define UHCI0_RXLINK_DSCR_BF0_S 0
+
+#define UHCI0_RX_DSCR_BF1 ( DR_REG_UHCI0_BASE + 0x60)
+#define UHCI0_RXLINK_DSCR_BF1 0xFFFFFFFF
+#define UHCI0_RXLINK_DSCR_BF1_S 0
+
+#define UHCI0_ESCAPE_CONF ( DR_REG_UHCI0_BASE + 0x64)
+#define UHCI0_RX_13_ESC_EN (BIT(7))
+#define UHCI0_RX_11_ESC_EN (BIT(6))
+#define UHCI0_RX_DB_ESC_EN (BIT(5))
+#define UHCI0_RX_C0_ESC_EN (BIT(4))
+#define UHCI0_TX_13_ESC_EN (BIT(3))
+#define UHCI0_TX_11_ESC_EN (BIT(2))
+#define UHCI0_TX_DB_ESC_EN (BIT(1))
+#define UHCI0_TX_C0_ESC_EN (BIT(0))
+
+#define UHCI0_HUNG_CONF ( DR_REG_UHCI0_BASE + 0x68)
+#define UHCI0_RXFIFO_TIMEOUT_ENA (BIT(23))
+#define UHCI0_RXFIFO_TIMEOUT_SHIFT 0x00000007
+#define UHCI0_RXFIFO_TIMEOUT_SHIFT_S 20
+#define UHCI0_RXFIFO_TIMEOUT 0x000000FF
+#define UHCI0_RXFIFO_TIMEOUT_S 12
+#define UHCI0_TXFIFO_TIMEOUT_ENA (BIT(11))
+#define UHCI0_TXFIFO_TIMEOUT_SHIFT 0x00000007
+#define UHCI0_TXFIFO_TIMEOUT_SHIFT_S 8
+#define UHCI0_TXFIFO_TIMEOUT 0x000000FF
+#define UHCI0_TXFIFO_TIMEOUT_S 0
+
+#define UHCI0_ACK_NUM ( DR_REG_UHCI0_BASE + 0x6C)
+
+#define UHCI0_RX_HEAD ( DR_REG_UHCI0_BASE + 0x70)
+#define UHCI0_UHCI_RX_HEAD 0xFFFFFFFF
+#define UHCI0_UHCI_RX_HEAD_S 0
+
+#define UHCI0_QUICK_SENT ( DR_REG_UHCI0_BASE + 0x74)
+#define UHCI0_ALWAYS_SEND_EN (BIT(7))
+#define UHCI0_ALWAYS_SEND_NUM 0x00000007
+#define UHCI0_ALWAYS_SEND_NUM_S 4
+#define UHCI0_SINGLE_SEND_EN (BIT(3))
+#define UHCI0_SINGLE_SEND_NUM 0x00000007
+#define UHCI0_SINGLE_SEND_NUM_S 0
+
+#define UHCI0_REG_Q0_WORD0 ( DR_REG_UHCI0_BASE + 0x78)
+#define UHCI0_SEND_Q0_WORD0 0xFFFFFFFF
+#define UHCI0_SEND_Q0_WORD0_S 0
+
+#define UHCI0_REG_Q0_WORD1 ( DR_REG_UHCI0_BASE + 0x7C)
+#define UHCI0_SEND_Q0_WORD1 0xFFFFFFFF
+#define UHCI0_SEND_Q0_WORD1_S 0
+
+#define UHCI0_REG_Q1_WORD0 ( DR_REG_UHCI0_BASE + 0x80)
+#define UHCI0_SEND_Q1_WORD0 0xFFFFFFFF
+#define UHCI0_SEND_Q1_WORD0_S 0
+
+#define UHCI0_REG_Q1_WORD1 ( DR_REG_UHCI0_BASE + 0x84)
+#define UHCI0_SEND_Q1_WORD1 0xFFFFFFFF
+#define UHCI0_SEND_Q1_WORD1_S 0
+
+#define UHCI0_REG_Q2_WORD0 ( DR_REG_UHCI0_BASE + 0x88)
+#define UHCI0_SEND_Q2_WORD0 0xFFFFFFFF
+#define UHCI0_SEND_Q2_WORD0_S 0
+
+#define UHCI0_REG_Q2_WORD1 ( DR_REG_UHCI0_BASE + 0x8C)
+#define UHCI0_SEND_Q2_WORD1 0xFFFFFFFF
+#define UHCI0_SEND_Q2_WORD1_S 0
+
+#define UHCI0_REG_Q3_WORD0 ( DR_REG_UHCI0_BASE + 0x90)
+#define UHCI0_SEND_Q3_WORD0 0xFFFFFFFF
+#define UHCI0_SEND_Q3_WORD0_S 0
+
+#define UHCI0_REG_Q3_WORD1 ( DR_REG_UHCI0_BASE + 0x94)
+#define UHCI0_SEND_Q3_WORD1 0xFFFFFFFF
+#define UHCI0_SEND_Q3_WORD1_S 0
+
+#define UHCI0_REG_Q4_WORD0 ( DR_REG_UHCI0_BASE + 0x98)
+#define UHCI0_SEND_Q4_WORD0 0xFFFFFFFF
+#define UHCI0_SEND_Q4_WORD0_S 0
+
+#define UHCI0_REG_Q4_WORD1 ( DR_REG_UHCI0_BASE + 0x9C)
+#define UHCI0_SEND_Q4_WORD1 0xFFFFFFFF
+#define UHCI0_SEND_Q4_WORD1_S 0
+
+#define UHCI0_REG_Q5_WORD0 ( DR_REG_UHCI0_BASE + 0xA0)
+#define UHCI0_SEND_Q5_WORD0 0xFFFFFFFF
+#define UHCI0_SEND_Q5_WORD0_S 0
+
+#define UHCI0_REG_Q5_WORD1 ( DR_REG_UHCI0_BASE + 0xA4)
+#define UHCI0_SEND_Q5_WORD1 0xFFFFFFFF
+#define UHCI0_SEND_Q5_WORD1_S 0
+
+#define UHCI0_REG_Q6_WORD0 ( DR_REG_UHCI0_BASE + 0xA8)
+#define UHCI0_SEND_Q6_WORD0 0xFFFFFFFF
+#define UHCI0_SEND_Q6_WORD0_S 0
+
+#define UHCI0_REG_Q6_WORD1 ( DR_REG_UHCI0_BASE + 0xAC)
+#define UHCI0_SEND_Q6_WORD1 0xFFFFFFFF
+#define UHCI0_SEND_Q6_WORD1_S 0
+
+#define UHCI0_ESC_CONF0 ( DR_REG_UHCI0_BASE + 0xB0)
+#define UHCI0_SEPER_ESC_CHAR1 0x000000FF
+#define UHCI0_SEPER_ESC_CHAR1_S 16
+#define UHCI0_SEPER_ESC_CHAR0 0x000000FF
+#define UHCI0_SEPER_ESC_CHAR0_S 8
+#define UHCI0_SEPER_CHAR 0x000000FF
+#define UHCI0_SEPER_CHAR_S 0
+
+#define UHCI0_ESC_CONF1 ( DR_REG_UHCI0_BASE + 0xB4)
+#define UHCI0_ESC_SEQ0_CHAR1 0x000000FF
+#define UHCI0_ESC_SEQ0_CHAR1_S 16
+#define UHCI0_ESC_SEQ0_CHAR0 0x000000FF
+#define UHCI0_ESC_SEQ0_CHAR0_S 8
+#define UHCI0_ESC_SEQ0 0x000000FF
+#define UHCI0_ESC_SEQ0_S 0
+
+#define UHCI0_ESC_CONF2 ( DR_REG_UHCI0_BASE + 0xB8)
+#define UHCI0_ESC_SEQ1_CHAR1 0x000000FF
+#define UHCI0_ESC_SEQ1_CHAR1_S 16
+#define UHCI0_ESC_SEQ1_CHAR0 0x000000FF
+#define UHCI0_ESC_SEQ1_CHAR0_S 8
+#define UHCI0_ESC_SEQ1 0x000000FF
+#define UHCI0_ESC_SEQ1_S 0
+
+#define UHCI0_ESC_CONF3 ( DR_REG_UHCI0_BASE + 0xBC)
+#define UHCI0_ESC_SEQ2_CHAR1 0x000000FF
+#define UHCI0_ESC_SEQ2_CHAR1_S 16
+#define UHCI0_ESC_SEQ2_CHAR0 0x000000FF
+#define UHCI0_ESC_SEQ2_CHAR0_S 8
+#define UHCI0_ESC_SEQ2 0x000000FF
+#define UHCI0_ESC_SEQ2_S 0
+
+#define UHCI0_PKT_THRES ( DR_REG_UHCI0_BASE + 0xC0)
+#define UHCI0_PKT_THRS 0x00001FFF
+#define UHCI0_PKT_THRS_S 0
+
+#define UHCI0_DATA ( DR_REG_UHCI0_BASE + 0xFC)
+#define UHCI0_UHCI_DATA 0xFFFFFFFF
+#define UHCI0_UHCI_DATA_S 0
+
+#endif /* _SOC_UHCI0_REG_H_ */

components/esp32/include/xtensa/board.h

@@ -0,0 +1,28 @@
+/*  This header is supposed to be obtained from <board>/xtensa/board.h
+    using a -I directive passed to the compiler.  */
+
+#error "Unspecified board.  Missing -I directive to select supported Xtensa board, usually -I XTENSA_TOOLS_ROOT/xtensa-elf/include/xtensa/<BOARD> (XTENSA_TOOLS_ROOT is root of Xtensa Tools install, see xt-run --show-config=xttools)"
+
+/*
+ * Copyright (c) 2013 Tensilica Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+

components/esp32/include/xtensa/c6x-compat.h

@@ -0,0 +1,1758 @@
+/*
+ * Copyright (c) 2006-2010 Tensilica Inc. ALL RIGHTS RESERVED.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef __C6X_COMPAT__H
+#define __C6X_COMPAT__H
+
+/* Unimplemented functions _gmpy, _gmpy4, _xormpy, _lssub, _cmpy, _cmpyr,
+   _cmpyr1, _ddotpl2r, _ddotph2r */
+
+
+typedef long long C6X_COMPAT_LONG40;
+
+
+#define _memd8(a) (*((double*)(a)))
+#define _memd8_const(a) (*((const double*)(a)))
+
+#define _amemd8(a) (*((double*)(a)))
+#define _amemd8_const(a) (*((const double*)(a)))
+
+#define _mem8(a) (*((unsigned long long*)(a)))
+#define _mem8_const(a) (*((const unsigned long long*)(a)))
+
+#define _mem4(a) (*((unsigned*)(a)))
+#define _mem4_const(a) (*((const unsigned*)(a)))
+#define _amem4_const(a) (*((const unsigned*)(a)))
+
+/*  NOTE: To emulate a C6X properly you should define global variables
+    for your Xtensa with these names.  Some of the emulation routines
+    will set these values.  */
+
+extern int _carry;
+extern int _overflow;
+
+//   Utility routines
+
+
+#define TESTBIT(x,n) (((x) >> (n)) & 1)
+
+#define NSA_BITS 32
+
+static inline unsigned int norm_shift_amt_U_and_non_U(int is_signed, int inp) {
+int j=0, k=0;
+int x=inp;
+if (is_signed) {
+    /* Invert signed val if negative */
+    x= TESTBIT(x,(NSA_BITS-1))? ~x: x;
+    x= (x&1)|(x<<1);		/* Shift up to return count-1 */
+    if (x ==0) 
+      return NSA_BITS-1;
+  }
+  if (x ==0) 
+    return NSA_BITS;
+  /* Now count leading zeros */
+  for (j=0, k=NSA_BITS-1; k>=0; j++, k--) {
+    if (TESTBIT(x,k)) 
+      return j;
+  }
+  return NSA_BITS;
+}
+
+
+
+static inline long long
+orig_L40_set( long long L40_var1) {
+   long long L40_var_out;
+   
+   L40_var_out =  L40_var1 & 0x000000ffffffffffLL;
+
+   if( L40_var1 & 0x8000000000LL)
+      L40_var_out = L40_var_out | 0xffffff0000000000LL;
+
+   return( L40_var_out);
+}
+
+
+
+static inline signed long long
+util_saturate_n_no_state(signed long long t, int n)
+{
+  signed long long maxv, minv;
+  maxv = (1LL << (n-1)) - 1;
+  minv = (-1LL << (n-1));
+  if (t > maxv) {
+    t = maxv;
+  } else if (t < minv) {
+    t = minv;
+  }
+  return t;
+}
+
+
+static inline signed long long
+util_saturate_n_sgn(signed long long t, int n)
+{
+  signed long long result;
+  signed long long maxv, minv;
+  maxv = (1LL << (n-1)) - 1;
+  minv = (-1LL << (n-1));
+  if (t > 0) {
+    result = maxv;
+    _overflow = 1;
+  } else if (t < 0) {
+    result = minv;
+    _overflow = 1;
+  } else {
+    result = 0;
+  }
+  return result;
+}
+
+
+
+
+/* well-behaved signed shift right (left on negative) with
+   saturation */
+static inline signed long long
+util_shift_right_saturate_n(signed long long t, int shval, int n)
+{
+  /* n should be <= 62 */
+  long long result;
+
+  signed long long mask;
+  int actual_shift = shval;
+  long long shft = actual_shift > 0 ? actual_shift : -actual_shift;
+
+  if (t == 0 || actual_shift == 0)
+    return t;
+
+  if (actual_shift >= n) {
+    return (t < 0) ? -1 : 0;
+  }
+  if (actual_shift <= -n) {
+    return util_saturate_n_sgn(t, n);
+  }
+  if (actual_shift > 0) {
+    return t >> actual_shift;
+  }
+  /* actual_shift < 0. Check for saturation after shift. */
+  mask = (-1LL << (n-shft-1));
+  if (t > 0 && ((mask & t) != 0)) {
+    return util_saturate_n_sgn(t, n);
+  }
+  if (t < 0 && ((mask & t) != mask)) {
+    return util_saturate_n_sgn(t, n);
+  }
+  result = t << shft;
+
+  return result;
+}
+
+
+/* Implemented c6x standard C compatibility functions (alphabetical
+   order) */
+
+
+static inline int _abs(int src1) {
+	if ((unsigned) src1 == (unsigned) 0x80000000) {
+		return 0x7fffffff;
+	}
+	return abs(src1);
+}
+
+
+static inline int _abs2(int src1) {
+	short s1[2],r[2];
+	int result;
+	*((int*)s1) = src1;
+	if ((unsigned short) s1[1] == (unsigned short) 0x8000) r[1] = 0x7fff;
+	   else r[1] = abs(s1[1]);
+	if ((unsigned short) s1[0] == (unsigned short) 0x8000) r[0] = 0x7fff;
+	   else r[0] = abs(s1[0]);
+	result = *(int*)r;
+	return result;
+	}
+
+
+
+
+static inline int _add2(int src1, int src2) {
+	short s1[2], s2[2], r[2];
+	int result;
+	*((int*)s1) = src1;
+	*((int*)s2) = src2;
+	r[0] = s1[0] + s2[0];
+	r[1] = s1[1] + s2[1];
+	result = *(int*)r;
+	return result;
+}
+
+static inline int _add4(int src1, int src2) {
+	char c1[4], c2[4], r[4];
+	int result;
+	*((int*)c1) = src1;
+	*((int*)c2) = src2;
+	r[0] = c1[0] + c2[0];
+	r[1] = c1[1] + c2[1];
+	r[2] = c1[2] + c2[2];
+	r[3] = c1[3] + c2[3];
+	result = *(int*)r;
+	return result;
+}
+
+
+
+static inline long long _addsub(unsigned int src1, unsigned int src2)
+{
+  
+  int res_lo;
+  int res_hi;
+ 
+  res_hi = src1+src2;
+  res_lo = src1-src2;
+  return (((unsigned long long) res_hi) << 32) | ((unsigned int) res_lo) ;
+}
+
+  
+static inline long long _addsub2(unsigned int src1, unsigned int src2)
+{
+  short s1[2], s2[2], ra[2], rs[2];
+  int res_lo;
+  int res_hi;
+
+  *((int*)s1) = src1;
+  *((int*)s2) = src2;
+  ra[0] = s1[0] + s2[0];
+  ra[1] = s1[1] + s2[1];
+  rs[0] = s1[0] - s2[0];
+  rs[1] = s1[1] - s2[1];
+  
+  res_hi = *(int*)ra;
+  res_lo = *(int*)rs;
+  return (((unsigned long long) res_hi) << 32) | ((unsigned int) res_lo) ;
+}
+
+
+static inline int _avg2(int src1, int src2) {
+  int low = (((int)1 +  (short) src1 + (short) src2) >> 1) & 0XFFFF;
+  int high1 = src1 >> 16;
+  int high2 = src2 >> 16;
+  int high = ((high1 + high2 + 1) >> 1)<< 16;
+  return high | low;
+}
+
+
+
+static inline unsigned int _avgu4(unsigned int src1, unsigned int src2) {
+unsigned int res0 = ((src1 & 0xFF) + (src2 & 0xFF) + 1) >> 1;
+  unsigned int res1 = (((src1 & 0xFF00) >> 8) + ((src2 & 0xFF00) >> 8) + 1) >> 1;
+  unsigned int res2 = (((src1 & 0xFF0000) >> 16) + ((src2 & 0xFF0000) >> 16) + 1) >> 1;
+  unsigned int res3 = (((src1 & 0xFF000000) >> 24) + ((src2 & 0xFF000000) >> 24) + 1) >> 1;
+  return (res3 << 24) | (res2 << 16) | (res1 << 8) | res0;
+}
+
+
+static inline int TEN_popc (unsigned char b)
+{
+  int i, result = 0;
+  for (i = 0; i <  8; i++){
+    if (b & 0x1)
+      result++;
+    b >>= 1;
+  }
+  return result;
+}
+
+static inline unsigned int _bitc4(unsigned int src1)
+{
+  unsigned int res0 = TEN_popc(src1 & 0xFF);
+  unsigned int res1 = TEN_popc((src1 & 0xFF00) >> 8);
+  unsigned int res2 = TEN_popc((src1 & 0xFF0000) >> 16);
+  unsigned int res3 = TEN_popc((src1 & 0xFF000000) >> 24);
+  return (res3 << 24) | (res2 << 16) | (res1 << 8) | res0;
+}
+
+static inline unsigned int _bitr(unsigned int src) {
+	int i;
+	unsigned r = 0;
+	for (i = 0; i< 32; ++i) {
+		r = r | (((src >> i) & 1)<<(31-i));
+	}
+	return r;
+}
+
+
+static inline unsigned int _clr(unsigned int src2,  int csta,  int cstb)
+{
+  csta &= 0x1f;
+  cstb &= 0x1f;
+  if (csta > cstb)
+    return src2;
+  else {
+    unsigned int mask =  (((1 <<  (cstb -  csta)) <<  1) -  1) <<  csta;
+    return src2 & (~mask);
+  }
+}
+
+static inline unsigned int _clrr(unsigned int src2, int src1)
+{
+  unsigned int csta = (src1 >> 5) & 0x1f;
+  unsigned int cstb = src1 & 0x1f;
+  if (csta > cstb)
+    return src2;
+  else {
+    unsigned int mask =  (((1 <<  (cstb -  csta)) <<  1) -  1) <<  csta;
+    return src2 & (~mask);
+  }
+}
+
+
+
+
+static inline int _cmpeq2(int src1, int src2) {
+	short s1[2], s2[2];
+	int r0, r1;
+	int result;
+	*((int*)s1) = src1;
+	*((int*)s2) = src2;
+	r0 = s1[0] == s2[0] ? 1 : 0;
+	r1 = s1[1] == s2[1] ? 1 : 0;
+	result = (r1 << 1) | r0;
+	return result;
+}
+
+static inline int _cmpeq4(int src1, int src2) {
+	char s1[4], s2[4];
+	int r0, r1, r2, r3;
+	int result;
+	*((int*)s1) = src1;
+	*((int*)s2) = src2;
+	r0 = s1[0] == s2[0] ? 1 : 0;
+	r1 = s1[1] == s2[1] ? 1 : 0;
+	r2 = s1[2] == s2[2] ? 1 : 0;
+	r3 = s1[3] == s2[3] ? 1 : 0;
+	result = (r3 << 3) | (r2 << 2) | (r1 << 1) | r0;
+	return result;
+}
+
+
+static inline int _cmpgt2(int src1, int src2) {
+	short s1[2], s2[2];
+	int r1, r0;
+	int result;
+	*((int*)s1) = src1;
+	*((int*)s2) = src2;
+	r0 = s1[0] > s2[0] ? 1 : 0;
+	r1 = s1[1] > s2[1] ? 1 : 0;
+	result = (r1<<1) | r0;
+	return result;
+}
+
+
+static inline unsigned int _cmpgtu4(unsigned int src1, unsigned int src2) {
+  unsigned int s1_0 = (src1 & 0xFF);
+  unsigned int s1_1 = (src1 & 0xFF00) >> 8;
+  unsigned int s1_2 = (src1 & 0xFF0000) >> 16;
+  unsigned int s1_3 = (src1 & 0xFF000000) >> 24;
+
+  unsigned int s2_0 = (src2 & 0xFF);
+  unsigned int s2_1 = (src2 & 0xFF00) >> 8;
+  unsigned int s2_2 = (src2 & 0xFF0000) >> 16;
+  unsigned int s2_3 = (src2 & 0xFF000000) >> 24;
+
+  unsigned int result = 0;
+
+  if (s1_0 > s2_0)
+    result |= 0x1;
+
+  if (s1_1 > s2_1)
+    result |= 0x2;
+
+  if (s1_2 > s2_2)
+    result |= 0x4;
+
+  if (s1_3 > s2_3)
+    result |= 0x8;
+
+  return result;
+}
+
+
+
+
+static inline long long _ddotp4(unsigned int src1, unsigned int src2) {
+  unsigned int res0, res1;
+  short s1_0 = (src1 & 0xffff);
+  short s1_1 = (src1 & 0xfff0000) >> 16;
+
+  unsigned short s2_0 = (src2 & 0xff);
+  unsigned short s2_1 = (src2 & 0xff00) >> 8;
+  unsigned short s2_2 = (src2 & 0xff0000) >> 16;
+  unsigned short s2_3 = (src2 & 0xff000000) >> 24;
+
+  res0 = ((int)s1_0) * s2_0 + ((int)s1_1) * s2_1;
+  res1 = ((int)s1_0) * s2_2 + ((int)s1_1) * s2_3;
+
+  return (res1 << 16) | res0;
+}
+
+
+static inline long long _ddotph2(long long src1_o_src1_e, unsigned int src2)
+{
+
+  unsigned int src1_o = src1_o_src1_e >> 32;  
+  unsigned int src1_e = src1_o_src1_e & 0xFFFFFFFF;  
+  short ls1_o = src1_o & 0XFFFF;
+  short hs1_o = src1_o >> 16;
+//  short ls1_e = src1_e & 0XFFFF;
+  short hs1_e = src1_e >> 16;
+  short ls2 = src2 & 0XFFFF;
+  short hs2 = src2 >> 16;
+
+  unsigned long long res_hi = ls2 * ls1_o + hs2 * hs1_o;
+  unsigned int res_lo = ls1_o * hs2 + hs1_e * ls2;
+  return (res_hi << 32) | res_lo;
+}
+
+
+static inline long long _ddotpl2(long long src1_o_src1_e, unsigned int src2)
+{
+  unsigned int src1_o = src1_o_src1_e >> 32;  
+  unsigned int src1_e = src1_o_src1_e & 0xFFFFFFFF;  
+  short ls1_o = src1_o & 0XFFFF;
+//  short hs1_o = src1_o >> 16;
+  short ls1_e = src1_e & 0XFFFF;
+  short hs1_e = src1_e >> 16;
+  short ls2 = src2 & 0XFFFF;
+  short hs2 = src2 >> 16;
+
+  unsigned long long res_hi = ls2 * hs1_e + hs2 * ls1_o;
+  unsigned res_lo = hs1_e * hs2 + ls1_e * ls2;
+  return (res_hi << 32) | res_lo;
+}
+
+
+static inline unsigned int _deal(unsigned int src)
+{
+  int i;
+  unsigned short lo = 0, hi = 0;
+  for (i = 0; i < 32; i+= 2) {
+    lo >>= 1;
+    lo |= (src & 0x1) << 15;
+    src >>= 1;
+    hi >>= 1;
+    hi |= (src & 0x1) << 15;
+    src >>= 1;
+  }
+  return (hi << 16) | lo;
+}
+
+
+static inline long long _dmv(unsigned int src1, unsigned int src2)
+{
+  return (((long long) src1) << 32) | src2;
+}
+
+
+static inline int _dotpn2(int src1, int src2) {
+short int s1_h = src1>>16;
+	short int s1_l = src1;
+	short int s2_h = src2>>16;
+	short int s2_l = src2;
+	return s1_h * s2_h - s1_l * s2_l;
+}
+
+
+static inline int _dotp2(int src1, int src2) {
+	short int s1_h = src1>>16;
+	short int s1_l = src1;
+	short int s2_h = src2>>16;
+	short int s2_l = src2;
+	return s1_h * s2_h + s1_l * s2_l;
+}
+
+
+
+static inline int _dotpnrsu2(int src1, unsigned int src2)
+{
+  short ls1 = src1 & 0XFFFF;
+  unsigned short ls2 = src2 & 0XFFFF;
+  short hs1 = src1 >> 16;
+  unsigned short hs2 = src2 >> 16;
+
+  int result = (((long long) (int)(hs1 * hs2)) - ((long long) (int)(ls1 * ls2)) +  (1 << 15)) >> 16;
+  return result;
+}
+
+
+
+static inline int _dotprsu2(int src1, unsigned int src2) {
+  short ls1 = src1 & 0XFFFF;
+  unsigned short ls2 =  (src2 & 0XFFFF);
+  short hs1 = src1 >> 16;
+  unsigned short hs2 =  (src2 >> 16);
+
+  int result = (((long long) (int) (ls1 * ls2)) + ((long long) (int) (hs1 * hs2)) +  (1LL << 15)) >> 16;
+  return result;
+}
+
+
+
+
+
+
+
+static inline int _dotpsu4(int src1, unsigned int src2) {
+  int result;
+  signed char s1_0 = (src1 & 0xff);
+  signed char s1_1 = (src1 & 0xff00) >> 8;
+  signed char s1_2 = (src1 & 0xff0000) >> 16;
+  signed char s1_3 = (src1 & 0xff000000) >> 24;
+
+  unsigned int s2_0 = (src2 & 0xff);
+  unsigned int s2_1 = (src2 & 0xff00) >> 8;
+  unsigned int s2_2 = (src2 & 0xff0000) >> 16;
+  unsigned int s2_3 = (src2 & 0xff000000) >> 24;
+
+  result = s1_0 * s2_0 + s1_1 * s2_1 + s1_2 * s2_2 + s1_3 * s2_3;
+  return result;
+}
+
+
+static inline unsigned int _dotpu4(unsigned int src1, unsigned int src2) {
+	unsigned char v1_0 = src1 & 0xff;
+	unsigned char v1_1 = (src1>>8) & 0xff;
+	unsigned char v1_2 = (src1>>16) & 0xff;
+	unsigned char v1_3 = (src1>>24) & 0xff;
+
+	unsigned char v2_0 = src2 & 0xff;
+	unsigned char v2_1 = (src2>>8) & 0xff;
+	unsigned char v2_2 = (src2>>16) & 0xff;
+	unsigned char v2_3 = (src2>>24) & 0xff;
+
+	unsigned v = v1_0 * v2_0  + v1_1 * v2_1 + v1_2 * v2_2 + v1_3 * v2_3;
+	return v;
+}
+
+
+static inline long long _dpack2(unsigned int src1, unsigned int src2){
+unsigned short s1[2], s2[2];
+*((int*)s1) = src1;
+*((int*)s2) = src2;
+return ((unsigned long long) s1[1] << 48) | ((unsigned long long) s2[1] << 32) | ((unsigned long long) s1[0] << 16) | ((unsigned long long) s2[0]);
+}
+
+
+static inline long long _dpackx2(unsigned int src1, unsigned int src2){
+unsigned short s1[2], s2[2];
+*((int*)s1) = src1;
+*((int*)s2) = src2;
+return ((unsigned long long) s2[0] << 48) | ((unsigned long long) s1[1] << 32) | ((unsigned long long) s1[0] << 16) | ((unsigned long long) s2[1]);
+}
+
+static inline int _ext(int src2, unsigned int csta, unsigned int cstb)
+{
+  return (src2 << csta) >> cstb;
+}
+
+static inline int _extr(int src2, int src1)
+{
+  unsigned int csta = (src1 >> 5) & 0x1f;
+  unsigned int cstb = src1 & 0x1f;
+  return (src2 << csta) >> cstb;
+}
+
+static inline unsigned int _extu(unsigned int src2, unsigned int csta, unsigned int cstb)
+{
+  return (src2 << csta) >> cstb;
+}
+
+static inline unsigned int _extur(unsigned int src2, int src1)
+{
+  unsigned int csta = (src1 >> 5) & 0x1f;
+  unsigned int cstb = src1 & 0x1f;
+  return (src2 << csta) >> cstb;
+}
+
+
+static inline unsigned long long _hi(double src) {
+	unsigned long long v;
+	*(double*)&v = src;
+	return v>>32;
+}
+
+static inline unsigned int _hill (long long src)
+{
+  return (unsigned int) (src >> 32);
+}
+
+
+
+static inline double _itod(unsigned hi, unsigned lo) {
+	double v;
+	unsigned long long ll = ((((unsigned long long)(hi))<<32) | (unsigned long long)((unsigned)lo)); 
+	*((unsigned long long *)&v) = ll;
+	return v;
+}
+
+
+static inline long long _itoll(unsigned int src2, unsigned int src1)
+{
+  return (((long long) src2) << 32) | src1;
+}
+
+
+static inline C6X_COMPAT_LONG40 _labs(C6X_COMPAT_LONG40 src2)
+{
+  long long maxv = (1LL << (40 -1)) - 1;
+  long long minv = (-1LL << (40 - 1));
+  C6X_COMPAT_LONG40 lres =  orig_L40_set(src2);
+
+  lres = lres < 0 ? -lres : lres;
+  if (lres > maxv) lres = maxv;
+  else if (lres < minv) lres = minv;
+  
+  return lres;
+}
+
+
+static inline C6X_COMPAT_LONG40 _ldotp2(int src1, int src2) {
+return (C6X_COMPAT_LONG40) _dotp2(src1, src2);
+}
+
+
+static inline unsigned int _lmbd(unsigned int src1, unsigned int src2)
+{
+  return norm_shift_amt_U_and_non_U(0,(((int) (src1 << 31)) >> 31) ^ (~src2));
+}
+
+
+static inline unsigned int _lnorm(C6X_COMPAT_LONG40 src2) {
+if (src2 == 0)
+    return 39;
+  else {
+    int hi = (int)(src2 >> 32);
+    int lo = (int)src2;
+    
+
+    long long temp = (unsigned long long)(unsigned)lo | (unsigned long long)hi << 32;
+    temp = orig_L40_set(temp);
+
+    if (temp == 0) return 0;
+    int cnt = 0;
+    while (((temp >> 39) & 1) == ((temp >> 38) & 1)) {
+       temp <<= 1;
+       cnt++;
+       }
+  return cnt;
+  }
+}
+
+
+static inline unsigned long long _lo(double src) {
+	unsigned long long v;
+	*(double*)&v = src;
+	return v;
+}
+
+
+static inline unsigned int _loll (long long src)
+{
+  return (unsigned int) src;
+}
+
+
+static inline C6X_COMPAT_LONG40 _lsadd(int src1, C6X_COMPAT_LONG40 src2)
+{
+  long long maxv = (1LL << (40 -1)) - 1;
+  long long minv = (-1LL << (40 - 1));
+  int hi = (int)(src2 >> 32);
+  int lo = (int)src2;
+  long long src2_int =  (unsigned long long)(unsigned)lo | (unsigned long long)hi << 32;
+
+
+  long long src2_int2 =  orig_L40_set(src2_int);
+  
+  long long res = src1 + src2_int2;
+
+  if (res > maxv) { 
+	res = maxv;
+	_overflow = 1;
+	}
+  else if (res < minv) {
+	res = minv;
+	_overflow = 1;
+	}
+
+  long long res2 = orig_L40_set(res);
+
+  res2 = (signed char)(res2 >> 32);
+  
+  C6X_COMPAT_LONG40 lres = (((C6X_COMPAT_LONG40) res2) << 32) | ((unsigned int)res);
+  return lres;
+}
+
+
+
+static inline int _max2 (int src1, int src2) {
+	short s1[2], s2[2], r[2];
+	int result;
+	*((int*)s1) = src1;
+	*((int*)s2) = src2;
+	r[0] = s1[0] > s2[0] ? s1[0] : s2[0];
+	r[1] = s1[1] > s2[1] ? s1[1] : s2[1];
+	result = *(int*)r;
+	return result;
+}
+
+
+
+
+
+
+static inline unsigned int _maxu4(unsigned int src1, unsigned int src2) {
+  unsigned int res0, res1, res2, res3;
+  unsigned int s1_0 = res0 = (src1 & 0xFF);
+  unsigned int s1_1 = res1 = (src1 & 0xFF00) >> 8;
+  unsigned int s1_2 = res2 = (src1 & 0xFF0000) >> 16;
+  unsigned int s1_3 = res3 = (src1 & 0xFF000000) >> 24;
+
+  unsigned int s2_0 = (src2 & 0xFF);
+  unsigned int s2_1 = (src2 & 0xFF00) >> 8;
+  unsigned int s2_2 = (src2 & 0xFF0000) >> 16;
+  unsigned int s2_3 = (src2 & 0xFF000000) >> 24;
+
+//  unsigned int res = 0;
+
+  if (s1_0 < s2_0)
+    res0 = s2_0;
+
+  if (s1_1 < s2_1)
+    res1 = s2_1;
+
+  if (s1_2 < s2_2)
+    res2 = s2_2;
+
+  if (s1_3 < s2_3)
+    res3 = s2_3;
+
+  return (res3 << 24) | (res2 << 16) | (res1 << 8) | res0;
+
+
+}
+
+static inline int _min2(int src1, int src2) {
+	short s1[2], s2[2], r[2];
+	int result;
+	*((int*)s1) = src1;
+	*((int*)s2) = src2;
+	r[0] = s1[0] < s2[0] ? s1[0] : s2[0];
+	r[1] = s1[1] < s2[1] ? s1[1] : s2[1];
+	result = *(int*)r;
+	return result;
+}
+
+
+static inline unsigned int _minu4(unsigned int src1, unsigned int src2) {
+unsigned int res0, res1, res2, res3;
+  unsigned int s1_0 = res0 = (src1 & 0xFF);
+  unsigned int s1_1 = res1 = (src1 & 0xFF00) >> 8;
+  unsigned int s1_2 = res2 = (src1 & 0xFF0000) >> 16;
+  unsigned int s1_3 = res3 = (src1 & 0xFF000000) >> 24;
+
+  unsigned int s2_0 = (src2 & 0xFF);
+  unsigned int s2_1 = (src2 & 0xFF00) >> 8;
+  unsigned int s2_2 = (src2 & 0xFF0000) >> 16;
+  unsigned int s2_3 = (src2 & 0xFF000000) >> 24;
+
+//  unsigned int res = 0;
+
+  if (s1_0 > s2_0)
+    res0 = s2_0;
+
+  if (s1_1 > s2_1)
+    res1 = s2_1;
+
+  if (s1_2 > s2_2)
+    res2 = s2_2;
+
+  if (s1_3 > s2_3)
+    res3 = s2_3;
+
+  return (res3 << 24) | (res2 << 16) | (res1 << 8) | res0;
+}
+
+
+static inline int _mpy(int src1, int src2) {
+return (short) src1 * (short) src2;
+}
+
+
+static inline int _mpyh(int src1, int src2) {
+return (short) (src1 >> 16) * (short) (src2 >> 16);
+}
+
+
+static inline long long _mpyhill (int src1,  int src2)
+{
+  short s1 = src1 >> 16;
+  return ((long long) src2) * s1;
+}
+
+static inline int _mpyhir(int src1, int src2)
+{
+  short s1 = src1 >> 16;
+  long long result = ((long long) src2) * s1 + (1 << 14);
+  result >>= 15;
+  return result;
+}
+
+
+static inline int _mpyhl(int src1, int src2) {
+return (short) (src1 >> 16) * (short) (src2);
+}
+
+static inline unsigned int _mpyhlu(unsigned int src1, unsigned int src2) {
+return (unsigned short) (src1 >> 16) * (unsigned short) (src2);
+}
+
+static inline int _mpyhslu(int src1, unsigned int src2) {
+return (short) (src1 >> 16) * (unsigned short) src2;
+}
+
+
+static inline int _mpyhsu(int src1, unsigned int src2) {
+return (short) (src1 >>16) * (unsigned short) (src2 >>16);
+}
+
+
+static inline unsigned int _mpyhu(unsigned int src1, unsigned int src2) {
+return (unsigned short) (src1 >>16) * (unsigned short) (src2 >> 16);
+}
+
+
+static inline int _mpyhuls(unsigned int src1, int src2) {
+return (unsigned short) (src1 >>16) * (signed short) (src2);
+}
+
+
+static inline int _mpyhus(unsigned int src1, int src2) {
+return (unsigned short) (src1 >> 16) * (short) (src2 >>16);
+}
+
+
+
+static inline long long _mpyidll (int src1, int src2)
+{
+  return (long long) src1 * src2;
+}
+
+
+static inline int _mpylh(int src1, int src2) {
+return (signed short) (src1 & 0xffff) * (signed short) (src2 >> 16);
+}
+
+static inline unsigned int _mpylhu(unsigned int src1, unsigned int src2) {
+return (unsigned short) src1 * (unsigned short) (src2 >> 16);
+}
+
+
+static inline long long _mpylill (int src1,  int src2)
+{
+  return ((long long) src2) * ((short)src1);
+}
+
+
+
+static inline int _mpylir(int src1, int src2)
+{
+  short s1 = src1;
+  long long result = ((long long) src2) * s1 + (1 << 14);
+  result >>= 15;
+  return result;
+}
+
+
+static inline int _mpylshu(int src1, unsigned int src2) {
+return (short) src1 * (unsigned short) (src2 >> 16);
+}
+
+
+static inline int _mpyluhs(unsigned int src1, int src2) {
+return (unsigned short) src1 * (short) (src2 >> 16);
+}
+
+
+
+static inline int _mpysu(int src1, unsigned int src2) {
+return (short) src1 * (unsigned short) src2;
+}
+
+
+
+static inline long long _mpysu4ll (int src1,  unsigned int src2) {
+  unsigned short res0, res1, res2, res3;
+  signed char s1_0 = (src1 & 0xff);
+  signed char s1_1 = (src1 & 0xff00) >> 8;
+  signed char s1_2 = (src1 & 0xff0000) >> 16;
+  signed char s1_3 = (src1 & 0xff000000) >> 24;
+
+  unsigned short s2_0 = (src2 & 0xff);
+  unsigned short s2_1 = (src2 & 0xff00) >> 8;
+  unsigned short s2_2 = (src2 & 0xff0000) >> 16;
+  unsigned short s2_3 = (src2 & 0xff000000) >> 24;
+
+  res0 = s1_0 * s2_0;
+  res1 = s1_1 * s2_1;
+  res2 = s1_2 * s2_2;
+  res3 = s1_3 * s2_3;
+
+  return (((unsigned long long) res3) << 48)
+    | (((unsigned long long) res2) << 32)
+    | (((unsigned long long) res1) << 16)
+    | res0;
+}
+
+static inline unsigned int _mpyu(unsigned int src1, unsigned int src2) {
+	unsigned v = (unsigned short)src1 * (unsigned short)src2;
+	return v;
+}
+
+static inline int _mpyus(unsigned int src1, int src2) {
+return (unsigned short) src1 * (short) src2;
+}
+
+static inline long long _mpyu4ll (unsigned int src1,  unsigned int src2) {
+  unsigned short res0, res1, res2, res3;
+  unsigned char s1_0 = (src1 & 0xff);
+  unsigned char s1_1 = (src1 & 0xff00) >> 8;
+  unsigned char s1_2 = (src1 & 0xff0000) >> 16;
+  unsigned char s1_3 = (src1 & 0xff000000) >> 24;
+
+  unsigned short s2_0 = (src2 & 0xff);
+  unsigned short s2_1 = (src2 & 0xff00) >> 8;
+  unsigned short s2_2 = (src2 & 0xff0000) >> 16;
+  unsigned short s2_3 = (src2 & 0xff000000) >> 24;
+
+  res0 = s1_0 * s2_0;
+  res1 = s1_1 * s2_1;
+  res2 = s1_2 * s2_2;
+  res3 = s1_3 * s2_3;
+
+  return (((unsigned long long) res3) << 48)
+    | (((unsigned long long) res2) << 32)
+    | (((unsigned long long) res1) << 16)
+    | res0;
+}
+
+
+static inline long long _mpy2ir(unsigned int src1, unsigned int src2)
+{
+  if ((src1 == 0x8000) && (src2 == 0x80000000)) {
+    _overflow = 1;
+    return 0;
+  }
+  else {
+    short ls1 = src1 & 0xffff;
+    short hs1 = src1 >> 16;
+    unsigned long long hi = (((long long) hs1) * (int) src2 + (1 << 14)) >> 15;
+    unsigned long long lo = ((((long long) ls1) * (int) src2 + (1 << 14)) >> 15) & 0xFFFFFFFF;
+    return (hi << 32) | lo;
+  }
+}
+
+
+static inline long long _mpy2ll (int src1,  int src2) {
+  short ls1 = src1 & 0xffff;
+  short hs1 = src1 >> 16;
+  short ls2 = src2 & 0xffff;
+  short hs2 = src2 >> 16;
+
+  unsigned long long hi = hs1 * hs2;
+  unsigned long long lo = (ls1 * ls2) & 0xFFFFFFFF;
+
+  return (hi << 32) | lo;
+  
+}
+
+
+static inline int _mpy32(int src1, int src2)
+{
+  return src1 * src2;
+}
+
+
+static inline long long _mpy32ll(int src1, int src2)
+{
+  return ((long long) src1) * src2;
+}
+
+static inline long long _mpy32su(int src1, unsigned int src2)
+{
+  return ((long long) src1) * ((int) src2);
+}
+
+static inline long long _mpy32u(unsigned int src1, unsigned int src2)
+{
+  return ((long long) ((int) src1)) * ((long long) ((int) src2));
+}
+
+static inline long long _mpy32us(unsigned int src1, int src2)
+{
+  return ((int) src1) * ((long long) src2);
+}
+
+static inline int _mvd (int src2)
+{
+  return src2;
+}
+
+
+static inline unsigned int _norm(int src2)
+{
+  return norm_shift_amt_U_and_non_U(1,src2);
+}
+
+
+static inline unsigned int _pack2 (unsigned int src1, unsigned int src2) {
+	short s1[2], s2[2], r[2];
+	int result;
+	*((int*)s1) = src1;
+	*((int*)s2) = src2;
+	r[0] = s2[0];
+	r[1] = s1[0];
+	result = *(int*)r;
+	return result;
+}
+
+
+static inline int _packh2 (unsigned int src1, unsigned int src2) {
+	unsigned v0 = src1 & 0xffff0000;
+	unsigned v1 = src2 >> 16;
+	unsigned v = v0|v1;
+	return v;
+	
+}
+
+static inline unsigned int _packh4 (unsigned int src1, unsigned int src2) {
+	unsigned v3 = (src1 >> 24) & 0xff;
+	unsigned v2 = (src1 >> 8) & 0xff;
+	unsigned v1 = (src2 >> 24) & 0xff;
+	unsigned v0 = (src2 >> 8) & 0xff;
+	unsigned v = (v3<<24) | (v2<<16) | (v1 << 8) | v0;
+	return v;
+}
+
+static inline unsigned int _packhl2 (unsigned int src1,  unsigned int src2) {
+	unsigned v0 = src1 & 0xffff0000;
+	unsigned v1 = src2 & 0x0000ffff;
+	unsigned v = v0|v1;
+	return v;
+}
+
+static inline unsigned int _packlh2 (unsigned int src1,  unsigned int src2) {
+	unsigned v0 = src1 << 16;
+	unsigned v1 = (src2 >> 16) & 0xffff;
+	unsigned v = v0|v1;
+	return v;
+}
+
+
+
+
+static inline unsigned int _packl4 (unsigned int src1, unsigned int src2) {
+	unsigned v3 = (src1 >> 16) & 0xff;
+	unsigned v2 = (src1) & 0xff;
+	unsigned v1 = (src2 >> 16) & 0xff;
+	unsigned v0 = (src2) & 0xff;
+	unsigned v = (v3<<24) | (v2<<16) | (v1 << 8) | v0;
+	return v;
+}
+
+
+
+
+static inline unsigned int _rpack2 (unsigned int src1, unsigned int src2) {
+int s1 = (int) src1;
+int s2 = (int) src2;
+s1 = util_shift_right_saturate_n (s1, -1, 32);
+s2 = util_shift_right_saturate_n (s2, -1, 32);
+return (unsigned int) (s1 & 0xffff0000) | (unsigned int) ((s2 & 0xffff0000) >>16);
+}
+
+
+static inline unsigned int _rotl (unsigned int src1, unsigned int src2)
+{
+  src2 &= 0x1f;
+  return (src1 << src2) | (src1 >> (32 - src2));
+}
+
+
+static inline int _sadd(int src1, int src2) {
+signed long long res;
+signed long long maxv, minv;
+maxv = (1LL << (32-1)) - 1;
+minv = (-1LL << (32-1));
+res = (long long) src1 + (long long) src2;
+if (res > maxv) {
+	res = maxv;
+	_overflow = 1;
+	}
+else if (res < minv ) {
+	res = minv;
+	_overflow = 1;
+	}
+return (int) res;
+}
+
+static inline long long _saddsub(unsigned int src1, unsigned int src2) {
+int radd;
+signed long long rsub;
+
+signed long long maxv, minv;
+maxv = (1LL << (32-1)) - 1;
+minv = (-1LL << (32-1));
+
+radd = (int) src1 + (int) src2;
+
+//   saturate on subtract, not add
+
+
+rsub = (long long) ((int) src1) - (long long) ((int) src2);
+if (rsub > maxv) {
+	rsub = maxv;
+        /* NOTE:   TI c6x does NOT set the overflow register even if results saturate */
+	/*  _overflow = 1; */
+	}
+else if (rsub < minv ) {
+	rsub = minv;
+        /* NOTE:   TI c6x does NOT set the overflow register even if results saturate */
+	/*  _overflow = 1; */
+	}
+
+return  (((unsigned long long) radd) << 32) |  ( rsub & 0x00000000ffffffff ) ;
+}
+
+
+
+static inline long long _saddsub2(unsigned int src1, unsigned int src2) {
+signed int radd[2];
+signed int rsub[2];
+signed short s1[2], s2[2];
+
+signed int maxv, minv;
+maxv = (1L << (16-1)) - 1;
+minv = (-1L << (16-1));
+
+*((int*)s1) = src1;
+*((int*)s2) = src2;
+
+radd[0] =  (int) s1[0] + (int) s2[0];
+radd[1] =  (int) s1[1] + (int) s2[1];
+
+rsub[0] =  (int) s1[0] - (int) s2[0];
+rsub[1] =  (int) s1[1] - (int) s2[1];
+
+if (radd[0] > maxv) {
+	radd[0] = maxv;
+        /* NOTE:   TI c6x does NOT set the overflow register even if results saturate */
+	/*  _overflow = 1; */
+	}
+else if (radd[0] < minv ) {
+	radd[0] = minv;
+        /* NOTE:   TI c6x does NOT set the overflow register even if results saturate */
+	/*  _overflow = 1; */
+	}
+
+if (radd[1] > maxv) {
+	radd[1] = maxv;
+        /* NOTE:   TI c6x does NOT set the overflow register even if results saturate */
+	/*  _overflow = 1; */
+	}
+else if (radd[1] < minv ) {
+	radd[1] = minv;
+        /* NOTE:   TI c6x does NOT set the overflow register even if results saturate */
+	/*  _overflow = 1; */
+	}
+
+
+if (rsub[0] > maxv) {
+	rsub[0] = maxv;
+        /* NOTE:   TI c6x does NOT set the overflow register even if results saturate */
+	/*  _overflow = 1; */
+	}
+else if (rsub[0] < minv ) {
+	rsub[0] = minv;
+        /* NOTE:   TI c6x does NOT set the overflow register even if results saturate */
+	/*  _overflow = 1; */
+	}
+
+if (rsub[1] > maxv) {
+	rsub[1] = maxv;
+        /* NOTE:   TI c6x does NOT set the overflow register even if results saturate */
+	/*  _overflow = 1; */
+	}
+else if (rsub[1] < minv ) {
+	rsub[1] = minv;
+        /* NOTE:   TI c6x does NOT set the overflow register even if results saturate */
+	/*  _overflow = 1; */
+	}
+
+
+return  ((((unsigned long long) radd[1]) & 0x000000000000ffff) << 48) | 
+        ((((unsigned long long) radd[0]) & 0x000000000000ffff) << 32) | 
+        ((((unsigned long long) rsub[1]) & 0x000000000000ffff) << 16) |
+        ((((unsigned long long) rsub[0]) & 0x000000000000ffff));
+}
+
+
+
+static inline  int _sadd2(int src1, int src2) {
+signed short s1[2], s2[2];
+signed int r[2], maxv, minv;
+
+maxv = (1L << (16-1)) - 1;
+minv = (-1L << (16-1));
+
+
+*((int*)s1) = src1;
+*((int*)s2) = src2;
+
+r[0] =  (int) s1[0] + (int) s2[0];
+r[1] =  (int) s1[1] + (int) s2[1];
+
+if (r[0] > maxv) {
+	r[0] = maxv;
+        /* NOTE:   TI c6x does NOT set the overflow register even if results saturate */
+	/*  _overflow = 1; */
+	}
+else if (r[0] < minv ) {
+	r[0] = minv;
+        /* NOTE:   TI c6x does NOT set the overflow register even if results saturate */
+	/*  _overflow = 1; */
+	}
+if (r[1] > maxv) {
+	r[1] = maxv;
+        /* NOTE:   TI c6x does NOT set the overflow register even if results saturate */
+	/*  _overflow = 1; */
+	}
+else if (r[1] < minv ) {
+	r[1] = minv;
+        /* NOTE:   TI c6x does NOT set the overflow register even if results saturate */
+	/*  _overflow = 1; */
+	}
+
+return ((r[1] & 0xffff) << 16 ) | (r[0] & 0xffff) ;
+}
+
+
+static inline int _saddus2(unsigned int src1, int src2) {
+int res0, res1;
+  unsigned int s1_0 = (src1 & 0xffff);
+  unsigned int s1_1 = (src1 & 0xffff0000) >> 16;
+
+  short s2_0 = (src2 & 0xffff);
+  short s2_1 = (src2 & 0xffff0000) >> 16;
+
+  res0 = s1_0 + s2_0;
+  res1 = s1_1 + s2_1;
+
+  if (res0 >= 0x10000)
+    res0 = 0xffff;
+  else if (res0 < 0)
+    res0 = 0;
+  
+  if (res1 >= 0x10000)
+    res1 = 0xffff;
+  else if (res1 < 0)
+    res1 = 0;
+  
+  return (res1 << 16) | res0;
+}
+
+
+static inline unsigned int _saddu4(unsigned int src1, unsigned int src2) {
+unsigned int res0, res1, res2, res3;
+  unsigned int s1_0 = (src1 & 0xff);
+  unsigned int s1_1 = (src1 & 0xff00) >> 8;
+  unsigned int s1_2 = (src1 & 0xff0000) >> 16;
+  unsigned int s1_3 = (src1 & 0xff000000) >> 24;
+
+  unsigned int s2_0 = (src2 & 0xff);
+  unsigned int s2_1 = (src2 & 0xff00) >> 8;
+  unsigned int s2_2 = (src2 & 0xff0000) >> 16;
+  unsigned int s2_3 = (src2 & 0xff000000) >> 24;
+
+  res0 = s1_0 + s2_0;
+  res1 = s1_1 + s2_1;
+  res2 = s1_2 + s2_2;
+  res3 = s1_3 + s2_3;
+
+  if (res0 >= 0x100)
+    res0 = 0xff;
+  
+  if (res1 >= 0x100)
+    res1 = 0xff;
+  
+  if (res2 >= 0x100)
+    res2 = 0xff;
+  
+  if (res3 >= 0x100)
+    res3 = 0xff;
+
+  return (res3 << 24) | (res2 << 16) | (res1 << 8) | res0;
+
+}
+
+
+
+static inline int _sat(C6X_COMPAT_LONG40 src2)
+{
+  long long maxv = (1LL << (32-1)) - 1;
+  long long minv = (-1LL << (32-1));
+
+  int hi = (int)(src2 >> 32);
+  int lo = (int)src2;
+  long long temp = (unsigned long long)(unsigned)lo | (unsigned long long)hi << 32;
+  temp = orig_L40_set(temp);
+  
+  if (temp > maxv) {
+	temp = maxv;
+	_overflow = 1;
+	}
+  else if (temp < minv) {
+	temp = minv;
+	_overflow = 1;
+	}
+  return (int) temp;
+}
+
+static inline unsigned int _set(unsigned int src2, unsigned int csta, unsigned int cstb)
+{
+  csta &= 0x1f;
+  cstb &= 0x1f;
+  if (csta > cstb)
+    return src2;
+  else {
+    unsigned int mask =  (((1 <<  (cstb -  csta)) <<  1) -  1) <<  csta;
+    return src2 | mask;
+  }
+}
+
+static inline unsigned int _setr(unsigned int src2, int src1)
+{
+  unsigned int csta = (src1 >> 5) & 0x1f;
+  unsigned int cstb = src1 & 0x1f;
+  if (csta > cstb)
+    return src2;
+  else {
+    unsigned int mask =  (((1 <<  (cstb -  csta)) <<  1) -  1) <<  csta;
+    return src2 | mask;
+  }
+}
+
+
+static inline unsigned int _shfl (unsigned int src2)
+{
+  unsigned short lo = src2;
+  unsigned short hi = src2 >> 16;
+  unsigned int result = 0;
+  int i;
+  for (i = 0; i < 32; i+= 2) {
+    result >>= 1;
+    result |= (lo & 0x1) << 31;
+    lo >>= 1;
+    result >>= 1;
+    result |= (hi & 0x1) << 31;
+    hi >>= 1;
+  }
+  return result;
+}
+
+static inline long long _shfl3 (unsigned int src1, unsigned int src2)
+{
+  unsigned short lo = src2;
+  unsigned short hi = src1 >> 16;
+  unsigned short mid = src1;
+  unsigned long long result = 0;
+  int i;
+  for (i = 0; i < 32; i+= 2) {
+    result >>= 1;
+    result |= ((unsigned long long) (lo & 0x1)) << 47;
+    lo >>= 1;
+    result >>= 1;
+    result |= ((unsigned long long) (mid & 0x1)) << 47;
+    mid >>= 1;
+    result >>= 1;
+    result |= ((unsigned long long) (hi & 0x1)) << 47;
+    hi >>= 1;
+  }
+  return result;
+}
+
+
+
+static inline unsigned int _shlmb (unsigned int src1, unsigned int src2)
+{
+  return (src2 << 8) | (src1 >> 24);
+}
+
+static inline unsigned int _shrmb (unsigned int src1, unsigned int src2)
+{
+  return (src2 >> 8) | (src1 << 24);
+}
+
+
+static inline unsigned int _shru2 (unsigned int src1, unsigned int src2) {
+unsigned short hs1 = src1 >> 16;
+  unsigned short ls1 = src1 & 0xFFFF;
+  hs1 >>= src2;
+  ls1 >>= src2;
+  return (hs1 << 16) | ls1;
+}
+
+
+static inline int _shr2 (int src1, unsigned int src2) {
+  short s1[2], result[2];
+  *((int*)s1) = src1;
+  src2 = src2 & 31;
+  result[0] = (int)s1[0] >> src2;
+  result[1] = (int)s1[1] >> src2;
+
+  return *(int*)result;
+}
+
+
+static inline int _smpy (int src1, int src2) {
+unsigned long long result;
+result =  (((short) src1 * (short) src2) << 1);
+
+if ((result & 0xffffffff) == 0x80000000){
+    result = 0x7fffffff;
+    _overflow = 1;
+  }
+return (int) (result);
+}
+
+static inline int _smpyh (int src1, int src2) {
+unsigned long long result;
+result =  ((short) (src1 >> 16) * (short) (src2 >> 16)) << 1;
+if ((result & 0xffffffff) == 0x80000000){
+    result = 0x7fffffff;
+    _overflow = 1;
+  }
+return (int) (result);
+}
+
+static inline int _smpyhl (int src1, int src2) {
+unsigned long long result;
+result = ((short) (src1 >> 16) * (short) (src2)) << 1;
+if ((result & 0xffffffff) == 0x80000000){
+    result = 0x7fffffff;
+    _overflow = 1;
+  }
+return (int) (result);
+}
+
+static inline int _smpylh (int src1, int src2) {
+unsigned long long result;
+result = ((short) (src1) * (short) (src2 >> 16)) << 1;
+if ((result & 0xffffffff) == 0x80000000){
+    result = 0x7fffffff;
+    _overflow = 1;
+  }
+return (int) (result);
+}
+
+static inline long long _smpy2ll (int src1,  int src2) {
+  short ls1 = src1 & 0XFFFF;
+  short hs1 = src1 >> 16;
+  short ls2 = src2 & 0XFFFF;
+  short hs2 = src2 >> 16;
+
+  unsigned long long hi = (hs1 * hs2) << 1;
+  unsigned long long lo = ((ls1 * ls2) << 1) & 0xFFFFFFFF;
+  if ((hi & 0xffffffff) == 0x80000000){
+    hi = 0x7fffffff;
+    _overflow = 1;
+  }
+
+  if ((lo & 0xffffffff) == 0x80000000){
+    lo = 0x7fffffff;
+    _overflow = 1;
+  }
+
+  return (hi << 32) | lo;
+}
+
+
+
+
+static inline int _smpy32(int src1, int src2)
+{
+  long long res = (long long) src1 * src2;
+  res <<= 1;
+  res >>= 32;
+  return res;
+}
+
+static inline unsigned char TEN_satu8 (short src)
+{
+  if (src > 0xff)
+    return 0xff;
+  else if (src < 0)
+    return 0;
+  else
+    return src;
+}
+
+static inline int _spack2 (int src1, int src2) {
+short s1 = (short) util_saturate_n_no_state(src1,16);
+short s2 = (short) util_saturate_n_no_state(src2,16);
+return  ( (unsigned int) s1 << 16) | (((int) s2) & 0xFFFF);
+}
+
+
+static inline unsigned int _spacku4 (int src1, int src2) {
+  short lolo = src2;
+  short lohi = src2 >> 16;
+  short hilo = src1;
+  short hihi = src1 >> 16;
+
+  lolo = TEN_satu8(lolo);
+  lohi = TEN_satu8(lohi);
+  hilo = TEN_satu8(hilo);
+  hihi = TEN_satu8(hihi);
+
+  return (((unsigned int) hihi) <<  24) | (((unsigned int) hilo) << 16) | (lohi << 8) | lolo;
+}
+
+
+
+static inline int _sshl (int src1, unsigned int src2) {
+short local2 = (short)(src2 & 0x7FFF);
+return (int) util_shift_right_saturate_n(src1, -local2, 32);
+}
+
+
+
+
+static inline int _sshvl (int src2, int src1) {
+  short s1;
+  if (src1 > 31)
+    s1 = 31;
+  else if (src1 < -31)
+    s1 = -31;
+  else
+    s1 = src1;
+
+  return (int) util_shift_right_saturate_n(src2, -s1, 32);
+}
+
+
+
+
+
+static inline int _sshvr (int src2, int src1) {
+short s1;
+  if (src1 > 31)
+    s1 = 31;
+  else if (src1 < -31)
+    s1 = -31;
+  else
+    s1 = src1;
+  return (int) util_shift_right_saturate_n(src2, s1, 32);
+}
+
+
+
+
+static inline int _ssub(int src1, int src2) {
+signed long long res;
+signed long long maxv, minv;
+maxv = (1LL << (32-1)) - 1;
+minv = (-1LL << (32-1));
+res = (long long) src1 - (long long) src2;
+if (res > maxv) {
+	res = maxv;
+	_overflow = 1;
+	}
+else if (res < minv ) {
+	res = minv;
+	_overflow = 1;
+	}
+return (int) res;
+}
+
+static inline int _ssub2(int src1, int src2) {
+signed short s1[2], s2[2];
+signed int r[2], maxv, minv;
+
+maxv = (1L << (16-1)) - 1;
+minv = (-1L << (16-1));
+
+
+*((int*)s1) = src1;
+*((int*)s2) = src2;
+
+r[0] =  (int) s1[0] - (int) s2[0];
+r[1] =  (int) s1[1] - (int) s2[1];
+
+if (r[0] > maxv) {
+	r[0] = maxv;
+        /* NOTE:   TI c6x does NOT set the overflow register even if results saturate */
+	/*  _overflow = 1; */
+	}
+else if (r[0] < minv ) {
+	r[0] = minv;
+        /* NOTE:   TI c6x does NOT set the overflow register even if results saturate */
+	/*  _overflow = 1; */
+	}
+if (r[1] > maxv) {
+	r[1] = maxv;
+        /* NOTE:   TI c6x does NOT set the overflow register even if results saturate */
+	/*  _overflow = 1; */
+	}
+else if (r[1] < minv ) {
+	r[1] = minv;
+        /* NOTE:   TI c6x does NOT set the overflow register even if results saturate */
+	/*  _overflow = 1; */
+	}
+
+return ((r[1] & 0xffff) << 16 ) | (r[0] & 0xffff) ;
+}
+
+
+static inline int _subabs4 (int src1, int src2) {
+  int res0, res1, res2, res3;
+  unsigned int s1_0 = (src1 & 0xff);
+  unsigned int s1_1 = (src1 & 0xff00) >> 8;
+  unsigned int s1_2 = (src1 & 0xff0000) >> 16;
+  unsigned int s1_3 = (src1 & 0xff000000) >> 24;
+
+  unsigned int s2_0 = (src2 & 0xff);
+  unsigned int s2_1 = (src2 & 0xff00) >> 8;
+  unsigned int s2_2 = (src2 & 0xff0000) >> 16;
+  unsigned int s2_3 = (src2 & 0xff000000) >> 24;
+
+  res0 = s1_0 - s2_0;
+  res1 = s1_1 - s2_1;
+  res2 = s1_2 - s2_2;
+  res3 = s1_3 - s2_3;
+
+  if (res0 < 0)
+    res0 = -res0;
+  
+  if (res1 < 0)
+    res1 = -res1;
+  
+  if (res2 < 0)
+    res2 = -res2;
+  
+  if (res3 < 0)
+    res3 = -res3;
+
+  return (res3 << 24) | (res2 << 16) | (res1 << 8) | res0;
+}
+
+
+static inline unsigned int _subc (unsigned int src1, unsigned int src2)
+{
+  if ( src1 >=  src2)
+    return ((src1 - src2) <<  1) +  1;
+  else
+    return src1 << 1;
+}
+
+
+
+static inline int _sub2(int src1, int src2) {
+	short s1[2], s2[2], r[2];
+	int result;
+	*((int*)s1) = src1;
+	*((int*)s2) = src2;
+	r[0] = s1[0] - s2[0];
+	r[1] = s1[1] - s2[1];
+	result = *(int*)r;
+	return result;
+}
+
+
+static inline int _sub4(int src1, int src2) {
+	char c1[4], c2[4], r[4];
+	int result;
+	*((int*)c1) = src1;
+	*((int*)c2) = src2;
+	r[0] = c1[0] - c2[0];
+	r[1] = c1[1] - c2[1];
+	r[2] = c1[2] - c2[2];
+	r[3] = c1[3] - c2[3];
+	result = *(int*)r;
+	return result;
+}
+
+
+static inline int _swap4 (unsigned int src1) {
+	unsigned char v0 = src1;
+	unsigned char v1 = src1 >> 8;
+	unsigned char v2 = src1 >> 16;
+	unsigned char v3 = src1 >> 24;
+	unsigned v = v0<<8 | v1 | v2<<24 | v3<<16;
+	return v;
+}
+
+static inline unsigned int _unpkhu4 (unsigned int src1) {
+	unsigned v0 = src1>>24;
+	unsigned v1 = (src1>>16) & 0xff;
+	return (v0<<16) | v1;
+}
+
+static inline unsigned int _unpklu4 (unsigned int src1) {
+	unsigned v1 = (src1>>8) & 0xff;
+	unsigned v0 = (src1) & 0xff;
+	return (v1<<16) | v0;
+}
+
+
+
+
+static inline unsigned int _xpnd2 (unsigned int src1) {
+      int v0 = (src1 & 0x1) ? 0x0000ffff : 0x00000000;
+      int v1 = (src1 & 0x2) ? 0xffff0000 : 0x00000000;
+      return v0|v1;
+}
+
+static inline unsigned int _xpnd4 (unsigned int src1) {
+      int v0 = (src1 & 0x1) ? 0x000000ff : 0x00000000;
+      int v1 = (src1 & 0x2) ? 0x0000ff00 : 0x00000000;
+      int v2 = (src1 & 0x4) ? 0x00ff0000 : 0x00000000;
+      int v3 = (src1 & 0x8) ? 0xff000000 : 0x00000000;
+      int r = v0|v1|v2|v3;
+      return r;
+}
+
+
+
+//     end of Implemented in alphabetical order
+
+
+#endif /* __C6X_COMPAT__H */

components/esp32/include/xtensa/cacheasm.h

@@ -0,0 +1,962 @@
+/*
+ * xtensa/cacheasm.h -- assembler-specific cache related definitions
+ *			that depend on CORE configuration
+ *
+ *  This file is logically part of xtensa/coreasm.h ,
+ *  but is kept separate for modularity / compilation-performance.
+ */
+
+/*
+ * Copyright (c) 2001-2014 Cadence Design Systems, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef XTENSA_CACHEASM_H
+#define XTENSA_CACHEASM_H
+
+#include <xtensa/coreasm.h>
+#include <xtensa/corebits.h>
+#include <xtensa/xtensa-xer.h>
+#include <xtensa/xtensa-versions.h>
+
+/*
+ *  This header file defines assembler macros of the form:
+ *	<x>cache_<func>
+ *  where <x> is 'i' or 'd' for instruction and data caches,
+ *  and <func> indicates the function of the macro.
+ *
+ *  The following functions <func> are defined,
+ *  and apply only to the specified cache (I or D):
+ *
+ *  reset
+ *	Resets the cache.
+ *
+ *  sync
+ *	Makes sure any previous cache instructions have been completed;
+ *	ie. makes sure any previous cache control operations
+ *	have had full effect and been synchronized to memory.
+ *	Eg. any invalidate completed [so as not to generate a hit],
+ *	any writebacks or other pipelined writes written to memory, etc.
+ *
+ *  invalidate_line		(single cache line)
+ *  invalidate_region		(specified memory range)
+ *  invalidate_all		(entire cache)
+ *	Invalidates all cache entries that cache
+ *	data from the specified memory range.
+ *	NOTE: locked entries are not invalidated.
+ *
+ *  writeback_line		(single cache line)
+ *  writeback_region		(specified memory range)
+ *  writeback_all		(entire cache)
+ *	Writes back to memory all dirty cache entries
+ *	that cache data from the specified memory range,
+ *	and marks these entries as clean.
+ *	NOTE: on some future implementations, this might
+ *		also invalidate.
+ *	NOTE: locked entries are written back, but never invalidated.
+ *	NOTE: instruction caches never implement writeback.
+ *
+ *  writeback_inv_line		(single cache line)
+ *  writeback_inv_region	(specified memory range)
+ *  writeback_inv_all		(entire cache)
+ *	Writes back to memory all dirty cache entries
+ *	that cache data from the specified memory range,
+ *	and invalidates these entries (including all clean
+ *	cache entries that cache data from that range).
+ *	NOTE: locked entries are written back but not invalidated.
+ *	NOTE: instruction caches never implement writeback.
+ *
+ *  lock_line			(single cache line)
+ *  lock_region			(specified memory range)
+ *	Prefetch and lock the specified memory range into cache.
+ *	NOTE:  if any part of the specified memory range cannot
+ *	be locked, a Load/Store Error (for dcache) or Instruction
+ *	Fetch Error (for icache) exception occurs.  These macros don't
+ *	do anything special (yet anyway) to handle this situation.
+ *
+ *  unlock_line			(single cache line)
+ *  unlock_region		(specified memory range)
+ *  unlock_all			(entire cache)
+ *	Unlock cache entries that cache the specified memory range.
+ *	Entries not already locked are unaffected.
+ *
+ *  coherence_on
+ *  coherence_off
+ *      Turn off and on cache coherence
+ *
+ */
+
+
+
+/***************************   GENERIC -- ALL CACHES   ***************************/
+
+
+/*
+ *  The following macros assume the following cache size/parameter limits
+ *  in the current Xtensa core implementation:
+ *	cache size:	1024 bytes minimum
+ *	line size:	16 - 64 bytes
+ *	way count:	1 - 4
+ *
+ *  Minimum entries per way (ie. per associativity) = 1024 / 64 / 4 = 4
+ *  Hence the assumption that each loop can execute four cache instructions.
+ *
+ *  Correspondingly, the offset range of instructions is assumed able to cover
+ *  four lines, ie. offsets {0,1,2,3} * line_size are assumed valid for
+ *  both hit and indexed cache instructions.  Ie. these offsets are all
+ *  valid:  0, 16, 32, 48, 64, 96, 128, 192 (for line sizes 16, 32, 64).
+ *  This is true of all original cache instructions
+ *  (dhi, ihi, dhwb, dhwbi, dii, iii) which have offsets
+ *  of 0 to 1020 in multiples of 4 (ie. 8 bits shifted by 2).
+ *  This is also true of subsequent cache instructions
+ *  (dhu, ihu, diu, iiu, diwb, diwbi, dpfl, ipfl) which have offsets
+ *  of 0 to 240 in multiples of 16 (ie. 4 bits shifted by 4).
+ *
+ *  (Maximum cache size, currently 32k, doesn't affect the following macros.
+ *  Cache ways > MMU min page size cause aliasing but that's another matter.)
+ */
+
+
+
+/*
+ *  Macro to apply an 'indexed' cache instruction to the entire cache.
+ *
+ *  Parameters:
+ *	cainst      instruction/ that takes an address register parameter
+ *              and an offset parameter (in range 0 .. 3*linesize).
+ *	size        size of cache in bytes
+ *	linesize    size of cache line in bytes (always power-of-2)
+ *	assoc_or1   number of associativities (ways/sets) in cache
+ *                  if all sets affected by cainst,
+ *                  or 1 if only one set (or not all sets) of the cache
+ *                  is affected by cainst (eg. DIWB or DIWBI [not yet ISA defined]).
+ *	aa, ab      unique address registers (temporaries). 
+ *	awb         set to other than a0 if wb type of instruction
+ *	loopokay    1 allows use of zero-overhead loops, 0 does not
+ *	immrange    range (max value) of cainst's immediate offset parameter, in bytes
+ *              (NOTE: macro assumes immrange allows power-of-2 number of lines)
+ */
+
+	.macro	cache_index_all		cainst, size, linesize, assoc_or1, aa, ab, loopokay, maxofs, awb=a0
+
+	//  Number of indices in cache (lines per way):
+	.set	.Lindices, (\size / (\linesize * \assoc_or1))
+	//  Number of indices processed per loop iteration (max 4):
+	.set	.Lperloop, .Lindices
+	.ifgt	.Lperloop - 4
+	 .set	.Lperloop, 4
+	.endif
+	//  Also limit instructions per loop if cache line size exceeds immediate range:
+	.set	.Lmaxperloop, (\maxofs / \linesize) + 1
+	.ifgt	.Lperloop - .Lmaxperloop
+	 .set	.Lperloop, .Lmaxperloop
+	.endif
+	//  Avoid addi of 128 which takes two instructions (addmi,addi):
+	.ifeq	.Lperloop*\linesize - 128
+	 .ifgt	.Lperloop - 1
+	  .set	.Lperloop, .Lperloop / 2
+	 .endif
+	.endif
+
+	//  \size byte cache, \linesize byte lines, \assoc_or1 way(s) affected by each \cainst.
+	// XCHAL_ERRATUM_497 - don't execute using loop, to reduce the amount of added code
+	.ifne	(\loopokay & XCHAL_HAVE_LOOPS && !XCHAL_ERRATUM_497)
+
+	movi	\aa, .Lindices / .Lperloop		// number of loop iterations
+	// Possible improvement: need only loop if \aa > 1 ;
+	// however \aa == 1 is highly unlikely.
+	movi	\ab, 0		// to iterate over cache
+	loop		\aa, .Lend_cachex\@
+	.set	.Li, 0 ;     .rept .Lperloop
+	  \cainst	\ab, .Li*\linesize
+	.set	.Li, .Li+1 ; .endr
+	addi		\ab, \ab, .Lperloop*\linesize	// move to next line
+.Lend_cachex\@:
+
+	.else
+
+	movi	\aa, (\size / \assoc_or1)
+	// Possible improvement: need only loop if \aa > 1 ;
+	// however \aa == 1 is highly unlikely.
+	movi	\ab, 0		// to iterate over cache
+	.ifne	((\awb !=a0) & XCHAL_ERRATUM_497)		// don't use awb if set to a0
+	movi \awb, 0
+	.endif
+.Lstart_cachex\@:
+	.set	.Li, 0 ;     .rept .Lperloop
+	  \cainst	\ab, .Li*\linesize
+	.set	.Li, .Li+1 ; .endr
+	.ifne	((\awb !=a0) & XCHAL_ERRATUM_497)		// do memw after 8 cainst wb instructions
+	addi \awb, \awb, .Lperloop
+	blti \awb, 8, .Lstart_memw\@
+	memw
+	movi \awb, 0
+.Lstart_memw\@:
+	.endif
+	addi		\ab, \ab, .Lperloop*\linesize	// move to next line
+	bltu		\ab, \aa, .Lstart_cachex\@
+	.endif
+
+	.endm
+
+
+/*
+ *  Macro to apply a 'hit' cache instruction to a memory region,
+ *  ie. to any cache entries that cache a specified portion (region) of memory.
+ *  Takes care of the unaligned cases, ie. may apply to one
+ *  more cache line than $asize / lineSize if $aaddr is not aligned.
+ *
+ *
+ *  Parameters are:
+ *	cainst	instruction/macro that takes an address register parameter
+ *		and an offset parameter (currently always zero)
+ *		and generates a cache instruction (eg. "dhi", "dhwb", "ihi", etc.)
+ *	linesize_log2	log2(size of cache line in bytes)
+ *	addr	register containing start address of region (clobbered)
+ *	asize	register containing size of the region in bytes (clobbered)
+ *	askew	unique register used as temporary
+ *	awb		unique register used as temporary for erratum 497.
+ *
+ *  Note: A possible optimization to this macro is to apply the operation
+ *  to the entire cache if the region exceeds the size of the cache
+ *  by some empirically determined amount or factor.  Some experimentation
+ *  is required to determine the appropriate factors, which also need
+ *  to be tunable if required.
+ */
+
+	.macro	cache_hit_region	cainst, linesize_log2, addr, asize, askew, awb=a0
+
+	//  Make \asize the number of iterations:
+	extui	\askew, \addr, 0, \linesize_log2	// get unalignment amount of \addr
+	add	\asize, \asize, \askew			// ... and add it to \asize
+	addi	\asize, \asize, (1 << \linesize_log2) - 1	// round up!
+	srli	\asize, \asize, \linesize_log2
+
+	//  Iterate over region:
+	.ifne	((\awb !=a0) & XCHAL_ERRATUM_497)		// don't use awb if set to a0
+	movi \awb, 0
+	.endif
+	floopnez	\asize, cacheh\@
+	\cainst		\addr, 0
+	.ifne	((\awb !=a0) & XCHAL_ERRATUM_497)		// do memw after 8 cainst wb instructions
+	addi \awb, \awb, 1
+	blti \awb, 8, .Lstart_memw\@
+	memw
+	movi \awb, 0
+.Lstart_memw\@:
+	.endif
+	addi		\addr, \addr, (1 << \linesize_log2)	// move to next line
+	floopend	\asize, cacheh\@
+	.endm
+
+
+
+
+
+/***************************   INSTRUCTION CACHE   ***************************/
+
+
+/*
+ *  Reset/initialize the instruction cache by simply invalidating it:
+ *  (need to unlock first also, if cache locking implemented):
+ *
+ *  Parameters:
+ *	aa, ab		unique address registers (temporaries)
+ */
+	.macro	icache_reset	aa, ab, loopokay=0
+	icache_unlock_all	\aa, \ab, \loopokay
+	icache_invalidate_all	\aa, \ab, \loopokay
+	.endm
+
+
+/*
+ * Synchronize after an instruction cache operation,
+ * to be sure everything is in sync with memory as to be
+ * expected following any previous instruction cache control operations.
+ *
+ * Even if a config doesn't have caches, an isync is still needed
+ * when instructions in any memory are modified, whether by a loader
+ * or self-modifying code.  Therefore, this macro always produces
+ * an isync, whether or not an icache is present.
+ *
+ * Parameters are:
+ *	ar	an address register (temporary) (currently unused, but may be used in future)
+ */
+	.macro	icache_sync	ar
+	isync
+	.endm
+
+
+
+/*
+ *  Invalidate a single line of the instruction cache.
+ *  Parameters are:
+ *	ar	address register that contains (virtual) address to invalidate
+ *		(may get clobbered in a future implementation, but not currently)
+ *	offset	(optional) offset to add to \ar to compute effective address to invalidate
+ *		(note: some number of lsbits are ignored)
+ */
+	.macro	icache_invalidate_line	ar, offset
+#if XCHAL_ICACHE_SIZE > 0
+	ihi	\ar, \offset		// invalidate icache line
+	icache_sync	\ar
+#endif
+	.endm
+
+
+
+
+/*
+ *  Invalidate instruction  cache entries that cache a specified portion of memory.
+ *  Parameters are:
+ *	astart	start address (register gets clobbered)
+ *	asize	size of the region in bytes (register gets clobbered)
+ *	ac	unique register used as temporary
+ */
+	.macro	icache_invalidate_region	astart, asize, ac
+#if XCHAL_ICACHE_SIZE > 0
+	//  Instruction cache region invalidation:
+	cache_hit_region	ihi, XCHAL_ICACHE_LINEWIDTH, \astart, \asize, \ac
+	icache_sync	\ac
+	//  End of instruction cache region invalidation
+#endif
+	.endm
+
+
+
+/*
+ *  Invalidate entire instruction cache.
+ *
+ *  Parameters:
+ *	aa, ab		unique address registers (temporaries)
+ */
+	.macro	icache_invalidate_all	aa, ab, loopokay=1
+#if XCHAL_ICACHE_SIZE > 0
+	//  Instruction cache invalidation:
+	cache_index_all		iii, XCHAL_ICACHE_SIZE, XCHAL_ICACHE_LINESIZE, XCHAL_ICACHE_WAYS, \aa, \ab, \loopokay, 1020
+	icache_sync	\aa
+	//  End of instruction cache invalidation
+#endif
+	.endm
+
+
+
+/*
+ *  Lock (prefetch & lock) a single line of the instruction cache.
+ *
+ *  Parameters are:
+ *	ar	address register that contains (virtual) address to lock
+ *		(may get clobbered in a future implementation, but not currently)
+ *	offset	offset to add to \ar to compute effective address to lock
+ *		(note: some number of lsbits are ignored)
+ */
+	.macro	icache_lock_line	ar, offset
+#if XCHAL_ICACHE_SIZE > 0 && XCHAL_ICACHE_LINE_LOCKABLE
+	ipfl	\ar, \offset	/* prefetch and lock icache line */
+	icache_sync	\ar
+#endif
+	.endm
+
+
+
+/*
+ *  Lock (prefetch & lock) a specified portion of memory into the instruction cache.
+ *  Parameters are:
+ *	astart	start address (register gets clobbered)
+ *	asize	size of the region in bytes (register gets clobbered)
+ *	ac	unique register used as temporary
+ */
+	.macro	icache_lock_region	astart, asize, ac
+#if XCHAL_ICACHE_SIZE > 0 && XCHAL_ICACHE_LINE_LOCKABLE
+	//  Instruction cache region lock:
+	cache_hit_region	ipfl, XCHAL_ICACHE_LINEWIDTH, \astart, \asize, \ac
+	icache_sync	\ac
+	//  End of instruction cache region lock
+#endif
+	.endm
+
+
+
+/*
+ *  Unlock a single line of the instruction cache.
+ *
+ *  Parameters are:
+ *	ar	address register that contains (virtual) address to unlock
+ *		(may get clobbered in a future implementation, but not currently)
+ *	offset	offset to add to \ar to compute effective address to unlock
+ *		(note: some number of lsbits are ignored)
+ */
+	.macro	icache_unlock_line	ar, offset
+#if XCHAL_ICACHE_SIZE > 0 && XCHAL_ICACHE_LINE_LOCKABLE
+	ihu	\ar, \offset	/* unlock icache line */
+	icache_sync	\ar
+#endif
+	.endm
+
+
+
+/*
+ *  Unlock a specified portion of memory from the instruction cache.
+ *  Parameters are:
+ *	astart	start address (register gets clobbered)
+ *	asize	size of the region in bytes (register gets clobbered)
+ *	ac	unique register used as temporary
+ */
+	.macro	icache_unlock_region	astart, asize, ac
+#if XCHAL_ICACHE_SIZE > 0 && XCHAL_ICACHE_LINE_LOCKABLE
+	//  Instruction cache region unlock:
+	cache_hit_region	ihu, XCHAL_ICACHE_LINEWIDTH, \astart, \asize, \ac
+	icache_sync	\ac
+	//  End of instruction cache region unlock
+#endif
+	.endm
+
+
+
+/*
+ *  Unlock entire instruction cache.
+ *
+ *  Parameters:
+ *	aa, ab		unique address registers (temporaries)
+ */
+	.macro	icache_unlock_all	aa, ab, loopokay=1
+#if XCHAL_ICACHE_SIZE > 0 && XCHAL_ICACHE_LINE_LOCKABLE
+	//  Instruction cache unlock:
+	cache_index_all		iiu, XCHAL_ICACHE_SIZE, XCHAL_ICACHE_LINESIZE, 1, \aa, \ab, \loopokay, 240
+	icache_sync	\aa
+	//  End of instruction cache unlock
+#endif
+	.endm
+
+
+
+
+
+/***************************   DATA CACHE   ***************************/
+
+
+
+/*
+ *  Reset/initialize the data cache by simply invalidating it
+ *  (need to unlock first also, if cache locking implemented):
+ *
+ *  Parameters:
+ *	aa, ab		unique address registers (temporaries)
+ */
+	.macro	dcache_reset	aa, ab, loopokay=0
+	dcache_unlock_all	\aa, \ab, \loopokay
+	dcache_invalidate_all	\aa, \ab, \loopokay
+	.endm
+
+
+
+
+/*
+ * Synchronize after a data cache operation,
+ * to be sure everything is in sync with memory as to be
+ * expected following any previous data cache control operations.
+ *
+ * Parameters are:
+ *	ar	an address register (temporary) (currently unused, but may be used in future)
+ */
+	.macro	dcache_sync	ar, wbtype=0
+#if XCHAL_DCACHE_SIZE > 0
+	//  No synchronization is needed.
+	//  (memw may be desired e.g. after writeback operation to help ensure subsequent
+	//   external accesses are seen to follow that writeback, however that's outside
+	//   the scope of this macro)
+
+	//dsync
+	.ifne	(\wbtype & XCHAL_ERRATUM_497)
+	memw
+	.endif
+#endif
+	.endm
+
+
+
+/*
+ * Turn on cache coherence.
+ *
+ * WARNING:  for RE-201x.x and later hardware, any interrupt that tries
+ * to change MEMCTL will see its changes dropped if the interrupt comes
+ * in the middle of this routine.  If this might be an issue, call this
+ * routine with interrupts disabled.
+ *
+ * Parameters are:
+ *	ar,at	two scratch address registers (both clobbered)
+ */
+	.macro	cache_coherence_on	ar at
+#if XCHAL_DCACHE_IS_COHERENT
+# if XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RE_2012_0
+	/*  Have MEMCTL.  Enable snoop responses.  */
+	rsr.memctl	\ar
+	movi		\at, MEMCTL_SNOOP_EN
+	or		\ar, \ar, \at
+	wsr.memctl	\ar
+# elif XCHAL_HAVE_EXTERN_REGS && XCHAL_HAVE_MX
+	/* Opt into coherence for MX (for backward compatibility / testing).  */
+	movi	\ar, 1
+	movi	\at, XER_CCON
+	wer	\ar, \at
+	extw
+# endif
+#endif
+	.endm
+
+
+
+/*
+ * Turn off cache coherence.
+ *
+ * NOTE:  this is generally preceded by emptying the cache;
+ * see xthal_cache_coherence_optout() in hal/coherence.c for details.
+ *
+ * WARNING:  for RE-201x.x and later hardware, any interrupt that tries
+ * to change MEMCTL will see its changes dropped if the interrupt comes
+ * in the middle of this routine.  If this might be an issue, call this
+ * routine with interrupts disabled.
+ *
+ * Parameters are:
+ *	ar,at	two scratch address registers (both clobbered)
+ */
+	.macro	cache_coherence_off	ar at
+#if XCHAL_DCACHE_IS_COHERENT
+# if XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RE_2012_0
+	/*  Have MEMCTL.  Disable snoop responses.  */
+	rsr.memctl	\ar
+	movi		\at, ~MEMCTL_SNOOP_EN
+	and		\ar, \ar, \at
+	wsr.memctl	\ar
+# elif XCHAL_HAVE_EXTERN_REGS && XCHAL_HAVE_MX
+	/* Opt out of coherence, for MX (for backward compatibility / testing).  */
+	extw
+	movi	\at, 0
+	movi	\ar, XER_CCON
+	wer	\at, \ar
+	extw
+# endif
+#endif
+	.endm
+
+
+
+/*
+ * Synchronize after a data store operation,
+ * to be sure the stored data is completely off the processor
+ * (and assuming there is no buffering outside the processor,
+ *  that the data is in memory).  This may be required to
+ * ensure that the processor's write buffers are emptied.
+ * A MEMW followed by a read guarantees this, by definition.
+ * We also try to make sure the read itself completes.
+ *
+ * Parameters are:
+ *	ar	an address register (temporary)
+ */
+	.macro	write_sync	ar
+	memw			// ensure previous memory accesses are complete prior to subsequent memory accesses
+	l32i	\ar, sp, 0	// completing this read ensures any previous write has completed, because of MEMW
+	//slot
+	add	\ar, \ar, \ar	// use the result of the read to help ensure the read completes (in future architectures)
+	.endm
+
+
+/*
+ *  Invalidate a single line of the data cache.
+ *  Parameters are:
+ *	ar	address register that contains (virtual) address to invalidate
+ *		(may get clobbered in a future implementation, but not currently)
+ *	offset	(optional) offset to add to \ar to compute effective address to invalidate
+ *		(note: some number of lsbits are ignored)
+ */
+	.macro	dcache_invalidate_line	ar, offset
+#if XCHAL_DCACHE_SIZE > 0
+	dhi	\ar, \offset
+	dcache_sync	\ar
+#endif
+	.endm
+
+
+
+
+
+/*
+ *  Invalidate data cache entries that cache a specified portion of memory.
+ *  Parameters are:
+ *	astart	start address (register gets clobbered)
+ *	asize	size of the region in bytes (register gets clobbered)
+ *	ac	unique register used as temporary
+ */
+	.macro	dcache_invalidate_region	astart, asize, ac
+#if XCHAL_DCACHE_SIZE > 0
+	//  Data cache region invalidation:
+	cache_hit_region	dhi, XCHAL_DCACHE_LINEWIDTH, \astart, \asize, \ac
+	dcache_sync	\ac
+	//  End of data cache region invalidation
+#endif
+	.endm
+
+
+
+/*
+ *  Invalidate entire data cache.
+ *
+ *  Parameters:
+ *	aa, ab		unique address registers (temporaries)
+ */
+	.macro	dcache_invalidate_all	aa, ab, loopokay=1
+#if XCHAL_DCACHE_SIZE > 0
+	//  Data cache invalidation:
+	cache_index_all		dii, XCHAL_DCACHE_SIZE, XCHAL_DCACHE_LINESIZE, XCHAL_DCACHE_WAYS, \aa, \ab, \loopokay, 1020
+	dcache_sync	\aa
+	//  End of data cache invalidation
+#endif
+	.endm
+
+
+
+/*
+ *  Writeback a single line of the data cache.
+ *  Parameters are:
+ *	ar	address register that contains (virtual) address to writeback
+ *		(may get clobbered in a future implementation, but not currently)
+ *	offset	offset to add to \ar to compute effective address to writeback
+ *		(note: some number of lsbits are ignored)
+ */
+	.macro	dcache_writeback_line	ar, offset
+#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_IS_WRITEBACK
+	dhwb	\ar, \offset
+	dcache_sync	\ar, wbtype=1
+#endif
+	.endm
+
+
+
+/*
+ *  Writeback dirty data cache entries that cache a specified portion of memory.
+ *  Parameters are:
+ *	astart	start address (register gets clobbered)
+ *	asize	size of the region in bytes (register gets clobbered)
+ *	ac	unique register used as temporary
+ */
+	.macro	dcache_writeback_region		astart, asize, ac, awb
+#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_IS_WRITEBACK
+	//  Data cache region writeback:
+	cache_hit_region	dhwb, XCHAL_DCACHE_LINEWIDTH, \astart, \asize, \ac, \awb
+	dcache_sync	\ac, wbtype=1
+	//  End of data cache region writeback
+#endif
+	.endm
+
+
+
+/*
+ *  Writeback entire data cache.
+ *  Parameters:
+ *	aa, ab		unique address registers (temporaries)
+ */
+	.macro	dcache_writeback_all	aa, ab, awb, loopokay=1
+#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_IS_WRITEBACK
+	//  Data cache writeback:
+	cache_index_all		diwb, XCHAL_DCACHE_SIZE, XCHAL_DCACHE_LINESIZE, 1, \aa, \ab, \loopokay, 240, \awb,
+	dcache_sync	\aa, wbtype=1
+	//  End of data cache writeback
+#endif
+	.endm
+
+
+
+/*
+ *  Writeback and invalidate a single line of the data cache.
+ *  Parameters are:
+ *	ar	address register that contains (virtual) address to writeback and invalidate
+ *		(may get clobbered in a future implementation, but not currently)
+ *	offset	offset to add to \ar to compute effective address to writeback and invalidate
+ *		(note: some number of lsbits are ignored)
+ */
+	.macro	dcache_writeback_inv_line	ar, offset
+#if XCHAL_DCACHE_SIZE > 0
+	dhwbi	\ar, \offset	/* writeback and invalidate dcache line */
+	dcache_sync	\ar, wbtype=1
+#endif
+	.endm
+
+
+
+/*
+ *  Writeback and invalidate data cache entries that cache a specified portion of memory.
+ *  Parameters are:
+ *	astart	start address (register gets clobbered)
+ *	asize	size of the region in bytes (register gets clobbered)
+ *	ac	unique register used as temporary
+ */
+	.macro	dcache_writeback_inv_region	astart, asize, ac, awb
+#if XCHAL_DCACHE_SIZE > 0
+	//  Data cache region writeback and invalidate:
+	cache_hit_region	dhwbi, XCHAL_DCACHE_LINEWIDTH, \astart, \asize, \ac, \awb
+	dcache_sync	\ac, wbtype=1
+	//  End of data cache region writeback and invalidate
+#endif
+	.endm
+
+
+
+/*
+ *  Writeback and invalidate entire data cache.
+ *  Parameters:
+ *	aa, ab		unique address registers (temporaries)
+ */
+	.macro	dcache_writeback_inv_all	aa, ab, awb, loopokay=1
+#if XCHAL_DCACHE_SIZE > 0
+	//  Data cache writeback and invalidate:
+#if XCHAL_DCACHE_IS_WRITEBACK
+	cache_index_all		diwbi, XCHAL_DCACHE_SIZE, XCHAL_DCACHE_LINESIZE, 1, \aa, \ab, \loopokay, 240, \awb
+	dcache_sync	\aa, wbtype=1
+#else /*writeback*/
+	//  Data cache does not support writeback, so just invalidate: */
+	dcache_invalidate_all	\aa, \ab, \loopokay
+#endif /*writeback*/
+	//  End of data cache writeback and invalidate
+#endif
+	.endm
+
+
+
+
+/*
+ *  Lock (prefetch & lock) a single line of the data cache.
+ *
+ *  Parameters are:
+ *	ar	address register that contains (virtual) address to lock
+ *		(may get clobbered in a future implementation, but not currently)
+ *	offset	offset to add to \ar to compute effective address to lock
+ *		(note: some number of lsbits are ignored)
+ */
+	.macro	dcache_lock_line	ar, offset
+#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_LINE_LOCKABLE
+	dpfl	\ar, \offset	/* prefetch and lock dcache line */
+	dcache_sync	\ar
+#endif
+	.endm
+
+
+
+/*
+ *  Lock (prefetch & lock) a specified portion of memory into the data cache.
+ *  Parameters are:
+ *	astart	start address (register gets clobbered)
+ *	asize	size of the region in bytes (register gets clobbered)
+ *	ac	unique register used as temporary
+ */
+	.macro	dcache_lock_region	astart, asize, ac
+#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_LINE_LOCKABLE
+	//  Data cache region lock:
+	cache_hit_region	dpfl, XCHAL_DCACHE_LINEWIDTH, \astart, \asize, \ac
+	dcache_sync	\ac
+	//  End of data cache region lock
+#endif
+	.endm
+
+
+
+/*
+ *  Unlock a single line of the data cache.
+ *
+ *  Parameters are:
+ *	ar	address register that contains (virtual) address to unlock
+ *		(may get clobbered in a future implementation, but not currently)
+ *	offset	offset to add to \ar to compute effective address to unlock
+ *		(note: some number of lsbits are ignored)
+ */
+	.macro	dcache_unlock_line	ar, offset
+#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_LINE_LOCKABLE
+	dhu	\ar, \offset	/* unlock dcache line */
+	dcache_sync	\ar
+#endif
+	.endm
+
+
+
+/*
+ *  Unlock a specified portion of memory from the data cache.
+ *  Parameters are:
+ *	astart	start address (register gets clobbered)
+ *	asize	size of the region in bytes (register gets clobbered)
+ *	ac	unique register used as temporary
+ */
+	.macro	dcache_unlock_region	astart, asize, ac
+#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_LINE_LOCKABLE
+	//  Data cache region unlock:
+	cache_hit_region	dhu, XCHAL_DCACHE_LINEWIDTH, \astart, \asize, \ac
+	dcache_sync	\ac
+	//  End of data cache region unlock
+#endif
+	.endm
+
+
+
+/*
+ *  Unlock entire data cache.
+ *
+ *  Parameters:
+ *	aa, ab		unique address registers (temporaries)
+ */
+	.macro	dcache_unlock_all	aa, ab, loopokay=1
+#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_LINE_LOCKABLE
+	//  Data cache unlock:
+	cache_index_all		diu, XCHAL_DCACHE_SIZE, XCHAL_DCACHE_LINESIZE, 1, \aa, \ab,  \loopokay, 240
+	dcache_sync	\aa
+	//  End of data cache unlock
+#endif
+	.endm
+
+
+
+/*
+ * Get the number of enabled icache ways. Note that this may
+ * be different from the value read from the MEMCTL register.
+ *
+ * Parameters:
+ *	aa	address register where value is returned
+ */
+	.macro	icache_get_ways		aa
+#if XCHAL_ICACHE_SIZE > 0
+#if XCHAL_HAVE_ICACHE_DYN_WAYS
+	// Read from MEMCTL and shift/mask
+	rsr	\aa, MEMCTL
+	extui	\aa, \aa, MEMCTL_ICWU_SHIFT, MEMCTL_ICWU_BITS
+	blti	\aa, XCHAL_ICACHE_WAYS, .Licgw
+	movi	\aa, XCHAL_ICACHE_WAYS
+.Licgw:
+#else
+	// All ways are always enabled
+	movi	\aa, XCHAL_ICACHE_WAYS
+#endif
+#else
+	// No icache
+	movi	\aa, 0
+#endif
+	.endm
+
+
+
+/*
+ * Set the number of enabled icache ways.
+ *
+ * Parameters:
+ *	aa      address register specifying number of ways (trashed)
+ *	ab,ac	address register for scratch use (trashed)
+ */
+	.macro  icache_set_ways		aa, ab, ac
+#if XCHAL_ICACHE_SIZE > 0
+#if XCHAL_HAVE_ICACHE_DYN_WAYS
+	movi	\ac, MEMCTL_ICWU_CLR_MASK	// set up to clear bits 18-22
+	rsr	\ab, MEMCTL
+	and	\ab, \ab, \ac
+	movi	\ac, MEMCTL_INV_EN		// set bit 23
+	slli	\aa, \aa, MEMCTL_ICWU_SHIFT	// move to right spot
+	or	\ab, \ab, \aa
+	or	\ab, \ab, \ac
+	wsr	\ab, MEMCTL
+	isync
+#else
+	// All ways are always enabled
+#endif
+#else
+	// No icache
+#endif
+	.endm
+
+
+
+/*
+ * Get the number of enabled dcache ways. Note that this may
+ * be different from the value read from the MEMCTL register.
+ *
+ * Parameters:
+ *	aa	address register where value is returned
+ */
+	.macro	dcache_get_ways		aa
+#if XCHAL_DCACHE_SIZE > 0
+#if XCHAL_HAVE_DCACHE_DYN_WAYS
+	// Read from MEMCTL and shift/mask
+	rsr	\aa, MEMCTL
+	extui	\aa, \aa, MEMCTL_DCWU_SHIFT, MEMCTL_DCWU_BITS
+	blti	\aa, XCHAL_DCACHE_WAYS, .Ldcgw
+	movi	\aa, XCHAL_DCACHE_WAYS
+.Ldcgw:
+#else
+	// All ways are always enabled  
+	movi	\aa, XCHAL_DCACHE_WAYS
+#endif
+#else
+	// No dcache
+	movi	\aa, 0
+#endif
+	.endm
+
+
+
+/*
+ * Set the number of enabled dcache ways.
+ *
+ * Parameters:
+ *	aa	address register specifying number of ways (trashed)
+ *	ab,ac	address register for scratch use (trashed)
+ */
+	.macro	dcache_set_ways		aa, ab, ac
+#if (XCHAL_DCACHE_SIZE > 0) && XCHAL_HAVE_DCACHE_DYN_WAYS
+	movi	\ac, MEMCTL_DCWA_CLR_MASK	// set up to clear bits 13-17
+	rsr	\ab, MEMCTL
+	and	\ab, \ab, \ac			// clear ways allocatable
+	slli	\ac, \aa, MEMCTL_DCWA_SHIFT
+	or	\ab, \ab, \ac			// set ways allocatable
+	wsr	\ab, MEMCTL
+#if XCHAL_DCACHE_IS_WRITEBACK
+	// Check if the way count is increasing or decreasing
+	extui	\ac, \ab, MEMCTL_DCWU_SHIFT, MEMCTL_DCWU_BITS			// bits 8-12 - ways in use
+	bge	\aa, \ac, .Ldsw3						// equal or increasing
+	slli	\ab, \aa, XCHAL_DCACHE_LINEWIDTH + XCHAL_DCACHE_SETWIDTH	// start way number
+	slli	\ac, \ac, XCHAL_DCACHE_LINEWIDTH + XCHAL_DCACHE_SETWIDTH	// end way number
+.Ldsw1:
+	diwbui.p	\ab		// auto-increments ab
+	bge	\ab, \ac, .Ldsw2
+	beqz	\ab, .Ldsw2
+	j	.Ldsw1
+.Ldsw2:
+	rsr	\ab, MEMCTL
+#endif
+.Ldsw3:
+	// No dirty data to write back, just set the new number of ways
+	movi	\ac, MEMCTL_DCWU_CLR_MASK		// set up to clear bits 8-12
+	and	\ab, \ab, \ac				// clear ways in use
+	movi	\ac, MEMCTL_INV_EN
+	or	\ab, \ab, \ac				// set bit 23
+	slli	\aa, \aa, MEMCTL_DCWU_SHIFT
+	or	\ab, \ab, \aa				// set ways in use
+	wsr	\ab, MEMCTL
+#else
+	// No dcache or no way disable support
+#endif
+	.endm
+
+#endif /*XTENSA_CACHEASM_H*/
+

components/esp32/include/xtensa/cacheattrasm.h

@@ -0,0 +1,436 @@
+/*
+ * xtensa/cacheattrasm.h -- assembler-specific CACHEATTR register related definitions
+ *			that depend on CORE configuration
+ *
+ *  This file is logically part of xtensa/coreasm.h (or perhaps xtensa/cacheasm.h),
+ *  but is kept separate for modularity / compilation-performance.
+ */
+
+/*
+ * Copyright (c) 2001-2009 Tensilica Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef XTENSA_CACHEATTRASM_H
+#define XTENSA_CACHEATTRASM_H
+
+#include <xtensa/coreasm.h>
+
+/*  Determine whether cache attributes are controlled using eight 512MB entries:  */
+#define XCHAL_CA_8X512	(XCHAL_HAVE_CACHEATTR || XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR \
+	|| (XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY))
+
+
+/*
+ *  This header file defines assembler macros of the form:
+ *	<x>cacheattr_<func>
+ *  where:
+ *	<x> is 'i', 'd' or absent for instruction, data
+ *		or both caches; and
+ *	<func> indicates the function of the macro.
+ *
+ *  The following functions are defined:
+ *
+ *  icacheattr_get
+ *	Reads I-cache CACHEATTR into a2 (clobbers a3-a5).
+ *
+ *  dcacheattr_get
+ *	Reads D-cache CACHEATTR into a2 (clobbers a3-a5).
+ *	(Note:  for configs with a real CACHEATTR register, the
+ *	 above two macros are identical.)
+ *
+ *  cacheattr_set
+ *	Writes both I-cache and D-cache CACHEATTRs from a2 (a3-a8 clobbered).
+ *	Works even when changing one's own code's attributes.
+ *
+ *  icacheattr_is_enabled  label
+ *	Branches to \label if I-cache appears to have been enabled
+ *	(eg. if CACHEATTR contains a cache-enabled attribute).
+ *	(clobbers a2-a5,SAR)
+ *
+ *  dcacheattr_is_enabled  label
+ *	Branches to \label if D-cache appears to have been enabled
+ *	(eg. if CACHEATTR contains a cache-enabled attribute).
+ *	(clobbers a2-a5,SAR)
+ *
+ *  cacheattr_is_enabled  label
+ *	Branches to \label if either I-cache or D-cache appears to have been enabled
+ *	(eg. if CACHEATTR contains a cache-enabled attribute).
+ *	(clobbers a2-a5,SAR)
+ *
+ *  The following macros are only defined under certain conditions:
+ *
+ *  icacheattr_set	(if XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR)
+ *	Writes I-cache CACHEATTR from a2 (a3-a8 clobbered).
+ *
+ *  dcacheattr_set	(if XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR)
+ *	Writes D-cache CACHEATTR from a2 (a3-a8 clobbered).
+ */
+
+
+
+/***************************   GENERIC -- ALL CACHES   ***************************/
+
+/*
+ *  _cacheattr_get
+ *
+ *  (Internal macro.)
+ *  Returns value of CACHEATTR register (or closest equivalent) in a2.
+ *  
+ *  Entry:
+ *	(none)
+ *  Exit:
+ *	a2	value read from CACHEATTR
+ *	a3-a5	clobbered (temporaries)
+ */
+	.macro	_cacheattr_get	tlb
+#if XCHAL_HAVE_CACHEATTR
+	rsr	a2, CACHEATTR
+#elif XCHAL_CA_8X512
+	//  We have a config that "mimics" CACHEATTR using a simplified
+	//  "MMU" composed of a single statically-mapped way.
+	//  DTLB and ITLB are independent, so there's no single
+	//  cache attribute that can describe both.  So for now
+	//  just return the DTLB state.
+	movi	a5, 0xE0000000
+	movi	a2, 0
+	movi	a3, XCHAL_SPANNING_WAY
+1:	add	a3, a3, a5	// next segment
+	r&tlb&1	a4, a3		// get PPN+CA of segment at 0xE0000000, 0xC0000000, ..., 0
+	dsync	// interlock???
+	slli	a2, a2, 4
+	extui	a4, a4, 0, 4	// extract CA
+	or	a2, a2, a4
+	bgeui	a3, 16, 1b
+#else
+	//  This macro isn't applicable to arbitrary MMU configurations.
+	//  Just return zero.
+	movi	a2, 0
+#endif
+	.endm
+
+	.macro	icacheattr_get
+	_cacheattr_get	itlb
+	.endm
+
+	.macro	dcacheattr_get
+	_cacheattr_get	dtlb
+	.endm
+
+
+/* Default (powerup/reset) value of CACHEATTR,
+   all BYPASS mode (ie. disabled/bypassed caches): */
+#if XCHAL_HAVE_PTP_MMU
+# define XCHAL_CACHEATTR_ALL_BYPASS	0x33333333
+#else
+# define XCHAL_CACHEATTR_ALL_BYPASS	0x22222222
+#endif
+
+#if XCHAL_CA_8X512
+
+#if XCHAL_HAVE_PTP_MMU
+# define XCHAL_FCA_ENAMASK	0x0AA0	/* bitmap of fetch attributes that require enabled icache */
+# define XCHAL_LCA_ENAMASK	0x0FF0	/* bitmap of load  attributes that require enabled dcache */
+# define XCHAL_SCA_ENAMASK	0x0CC0	/* bitmap of store attributes that require enabled dcache */
+#else
+# define XCHAL_FCA_ENAMASK	0x003A	/* bitmap of fetch attributes that require enabled icache */
+# define XCHAL_LCA_ENAMASK	0x0033	/* bitmap of load  attributes that require enabled dcache */
+# define XCHAL_SCA_ENAMASK	0x0033	/* bitmap of store attributes that require enabled dcache */
+#endif
+#define XCHAL_LSCA_ENAMASK	(XCHAL_LCA_ENAMASK|XCHAL_SCA_ENAMASK)	/* l/s attrs requiring enabled dcache */
+#define XCHAL_ALLCA_ENAMASK	(XCHAL_FCA_ENAMASK|XCHAL_LSCA_ENAMASK)	/* all attrs requiring enabled caches */
+
+/*
+ *  _cacheattr_is_enabled
+ *
+ *  (Internal macro.)
+ *  Branches to \label if CACHEATTR in a2 indicates an enabled
+ *  cache, using mask in a3.
+ *
+ *  Parameters:
+ *	label	where to branch to if cache is enabled
+ *  Entry:
+ *	a2	contains CACHEATTR value used to determine whether
+ *		caches are enabled
+ *	a3	16-bit constant where each bit correspond to
+ *		one of the 16 possible CA values (in a CACHEATTR mask);
+ *		CA values that indicate the cache is enabled
+ *		have their corresponding bit set in this mask
+ *		(eg. use XCHAL_xCA_ENAMASK , above)
+ *  Exit:
+ *	a2,a4,a5	clobbered
+ *	SAR		clobbered
+ */
+	.macro	_cacheattr_is_enabled	label
+	movi	a4, 8		// loop 8 times
+.Lcaife\@:
+	extui	a5, a2, 0, 4	// get CA nibble
+	ssr	a5		// index into mask according to CA...
+	srl	a5, a3		// ...and get CA's mask bit in a5 bit 0
+	bbsi.l	a5, 0, \label	// if CA indicates cache enabled, jump to label
+	srli	a2, a2, 4	// next nibble
+	addi	a4, a4, -1
+	bnez	a4, .Lcaife\@	// loop for each nibble
+	.endm
+
+#else /* XCHAL_CA_8X512 */
+	.macro	_cacheattr_is_enabled	label
+	j	\label		// macro not applicable, assume caches always enabled
+	.endm
+#endif /* XCHAL_CA_8X512 */
+
+
+
+/*
+ *  icacheattr_is_enabled
+ *
+ *  Branches to \label if I-cache is enabled.
+ *
+ *  Parameters:
+ *	label	where to branch to if icache is enabled
+ *  Entry:
+ *	(none)
+ *  Exit:
+ *	a2-a5, SAR	clobbered (temporaries)
+ */
+	.macro	icacheattr_is_enabled	label
+#if XCHAL_CA_8X512
+	icacheattr_get
+	movi	a3, XCHAL_FCA_ENAMASK
+#endif
+	_cacheattr_is_enabled	\label
+	.endm
+
+/*
+ *  dcacheattr_is_enabled
+ *
+ *  Branches to \label if D-cache is enabled.
+ *
+ *  Parameters:
+ *	label	where to branch to if dcache is enabled
+ *  Entry:
+ *	(none)
+ *  Exit:
+ *	a2-a5, SAR	clobbered (temporaries)
+ */
+	.macro	dcacheattr_is_enabled	label
+#if XCHAL_CA_8X512
+	dcacheattr_get
+	movi	a3, XCHAL_LSCA_ENAMASK
+#endif
+	_cacheattr_is_enabled	\label
+	.endm
+
+/*
+ *  cacheattr_is_enabled
+ *
+ *  Branches to \label if either I-cache or D-cache is enabled.
+ *
+ *  Parameters:
+ *	label	where to branch to if a cache is enabled
+ *  Entry:
+ *	(none)
+ *  Exit:
+ *	a2-a5, SAR	clobbered (temporaries)
+ */
+	.macro	cacheattr_is_enabled	label
+#if XCHAL_HAVE_CACHEATTR
+	rsr	a2, CACHEATTR
+	movi	a3, XCHAL_ALLCA_ENAMASK
+#elif XCHAL_CA_8X512
+	icacheattr_get
+	movi	a3, XCHAL_FCA_ENAMASK
+	_cacheattr_is_enabled	\label
+	dcacheattr_get
+	movi	a3, XCHAL_LSCA_ENAMASK
+#endif
+	_cacheattr_is_enabled	\label
+	.endm
+
+
+
+/*
+ *  The ISA does not have a defined way to change the
+ *  instruction cache attributes of the running code,
+ *  ie. of the memory area that encloses the current PC.
+ *  However, each micro-architecture (or class of
+ *  configurations within a micro-architecture)
+ *  provides a way to deal with this issue.
+ *
+ *  Here are a few macros used to implement the relevant
+ *  approach taken.
+ */
+
+#if XCHAL_CA_8X512 && !XCHAL_HAVE_CACHEATTR
+	//  We have a config that "mimics" CACHEATTR using a simplified
+	//  "MMU" composed of a single statically-mapped way.
+
+/*
+ *  icacheattr_set
+ *
+ *  Entry:
+ *	a2		cacheattr value to set
+ *  Exit:
+ *	a2		unchanged
+ *	a3-a8		clobbered (temporaries)
+ */
+	.macro	icacheattr_set
+
+	movi	a5, 0xE0000000	// mask of upper 3 bits
+	movi	a6, 3f		// PC where ITLB is set
+	movi	a3, XCHAL_SPANNING_WAY	// start at region 0 (0 .. 7)
+	mov	a7, a2		// copy a2 so it doesn't get clobbered
+	and	a6, a6, a5	// upper 3 bits of local PC area
+	j	3f
+
+	//  Use micro-architecture specific method.
+	//  The following 4-instruction sequence is aligned such that
+	//  it all fits within a single I-cache line.  Sixteen byte
+	//  alignment is sufficient for this (using XCHAL_ICACHE_LINESIZE
+	//  actually causes problems because that can be greater than
+	//  the alignment of the reset vector, where this macro is often
+	//  invoked, which would cause the linker to align the reset
+	//  vector code away from the reset vector!!).
+	.begin	no-transform
+	.align	16 /*XCHAL_ICACHE_LINESIZE*/
+1:	witlb	a4, a3		// write wired PTE (CA, no PPN) of 512MB segment to ITLB
+	isync
+	.end	no-transform
+	nop
+	nop
+
+	sub	a3, a3, a5	// next segment (add 0x20000000)
+	bltui	a3, 16, 4f	// done?
+
+	//  Note that in the WITLB loop, we don't do any load/stores
+	//  (may not be an issue here, but it is important in the DTLB case).
+2:	srli	a7, a7, 4	// next CA
+3:
+# if XCHAL_HAVE_MIMIC_CACHEATTR
+	extui	a4, a7, 0, 4	// extract CA to set
+# else	/* have translation, preserve it: */
+	ritlb1	a8, a3		// get current PPN+CA of segment
+	//dsync	// interlock???
+	extui	a4, a7, 0, 4	// extract CA to set
+	srli	a8, a8, 4	// clear CA but keep PPN ...
+	slli	a8, a8, 4	// ...
+	add	a4, a4, a8	// combine new CA with PPN to preserve
+# endif
+	beq	a3, a6, 1b	// current PC's region? if so, do it in a safe way
+	witlb	a4, a3		// write wired PTE (CA [+PPN]) of 512MB segment to ITLB
+	sub	a3, a3, a5	// next segment (add 0x20000000)
+	bgeui	a3, 16, 2b
+	isync			// make sure all ifetch changes take effect
+4:
+	.endm	// icacheattr_set
+
+
+/*
+ *  dcacheattr_set
+ *
+ *  Entry:
+ *	a2		cacheattr value to set
+ *  Exit:
+ *	a2		unchanged
+ *	a3-a8		clobbered (temporaries)
+ */
+
+	.macro	dcacheattr_set
+
+	movi	a5, 0xE0000000	// mask of upper 3 bits
+	movi	a3, XCHAL_SPANNING_WAY	// start at region 0 (0 .. 7)
+	mov	a7, a2		// copy a2 so it doesn't get clobbered
+	//  Note that in the WDTLB loop, we don't do any load/stores
+2:	//  (including implicit l32r via movi) because it isn't safe.
+# if XCHAL_HAVE_MIMIC_CACHEATTR
+	extui	a4, a7, 0, 4	// extract CA to set
+# else	/* have translation, preserve it: */
+	rdtlb1	a8, a3		// get current PPN+CA of segment
+	//dsync	// interlock???
+	extui	a4, a7, 0, 4	// extract CA to set
+	srli	a8, a8, 4	// clear CA but keep PPN ...
+	slli	a8, a8, 4	// ...
+	add	a4, a4, a8	// combine new CA with PPN to preserve
+# endif
+	wdtlb	a4, a3		// write wired PTE (CA [+PPN]) of 512MB segment to DTLB
+	sub	a3, a3, a5	// next segment (add 0x20000000)
+	srli	a7, a7, 4	// next CA
+	bgeui	a3, 16, 2b
+	dsync			// make sure all data path changes take effect
+	.endm	// dcacheattr_set
+
+#endif /* XCHAL_CA_8X512 && !XCHAL_HAVE_CACHEATTR */
+
+
+
+/*
+ *  cacheattr_set
+ *
+ *  Macro that sets the current CACHEATTR safely
+ *  (both i and d) according to the current contents of a2.
+ *  It works even when changing the cache attributes of
+ *  the currently running code.
+ *
+ *  Entry:
+ *	a2		cacheattr value to set
+ *  Exit:
+ *	a2		unchanged
+ *	a3-a8		clobbered (temporaries)
+ */
+	.macro	cacheattr_set
+
+#if XCHAL_HAVE_CACHEATTR
+# if XCHAL_ICACHE_LINESIZE < 4
+	//  No i-cache, so can always safely write to CACHEATTR:
+	wsr	a2, CACHEATTR
+# else
+	//  The Athens micro-architecture, when using the old
+	//  exception architecture option (ie. with the CACHEATTR register)
+	//  allows changing the cache attributes of the running code
+	//  using the following exact sequence aligned to be within
+	//  an instruction cache line.  (NOTE: using XCHAL_ICACHE_LINESIZE
+	//  alignment actually causes problems because that can be greater
+	//  than the alignment of the reset vector, where this macro is often
+	//  invoked, which would cause the linker to align the reset
+	//  vector code away from the reset vector!!).
+	j	1f
+	.begin	no-transform
+	.align	16 /*XCHAL_ICACHE_LINESIZE*/	// align to within an I-cache line
+1:	wsr	a2, CACHEATTR
+	isync
+	.end	no-transform
+	nop
+	nop
+# endif
+#elif XCHAL_CA_8X512
+	//  DTLB and ITLB are independent, but to keep semantics
+	//  of this macro we simply write to both.
+	icacheattr_set
+	dcacheattr_set
+#else
+	//  This macro isn't applicable to arbitrary MMU configurations.
+	//  Do nothing in this case.
+#endif
+	.endm
+
+
+#endif /*XTENSA_CACHEATTRASM_H*/
+

components/esp32/include/xtensa/config/core-isa.h

@@ -0,0 +1,655 @@
+/* 
+ * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa
+ *				processor CORE configuration
+ *
+ *  See <xtensa/config/core.h>, which includes this file, for more details.
+ */
+
+/* Xtensa processor core configuration information.
+
+   Customer ID=11657; Build=0x5fe96; Copyright (c) 1999-2016 Tensilica Inc.
+
+   Permission is hereby granted, free of charge, to any person obtaining
+   a copy of this software and associated documentation files (the
+   "Software"), to deal in the Software without restriction, including
+   without limitation the rights to use, copy, modify, merge, publish,
+   distribute, sublicense, and/or sell copies of the Software, and to
+   permit persons to whom the Software is furnished to do so, subject to
+   the following conditions:
+
+   The above copyright notice and this permission notice shall be included
+   in all copies or substantial portions of the Software.
+
+   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
+
+#ifndef _XTENSA_CORE_CONFIGURATION_H
+#define _XTENSA_CORE_CONFIGURATION_H
+
+
+/****************************************************************************
+	    Parameters Useful for Any Code, USER or PRIVILEGED
+ ****************************************************************************/
+
+/*
+ *  Note:  Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is
+ *  configured, and a value of 0 otherwise.  These macros are always defined.
+ */
+
+
+/*----------------------------------------------------------------------
+				ISA
+  ----------------------------------------------------------------------*/
+
+#define XCHAL_HAVE_BE			0	/* big-endian byte ordering */
+#define XCHAL_HAVE_WINDOWED		1	/* windowed registers option */
+#define XCHAL_NUM_AREGS			64	/* num of physical addr regs */
+#define XCHAL_NUM_AREGS_LOG2		6	/* log2(XCHAL_NUM_AREGS) */
+#define XCHAL_MAX_INSTRUCTION_SIZE	3	/* max instr bytes (3..8) */
+#define XCHAL_HAVE_DEBUG		1	/* debug option */
+#define XCHAL_HAVE_DENSITY		1	/* 16-bit instructions */
+#define XCHAL_HAVE_LOOPS		1	/* zero-overhead loops */
+#define XCHAL_LOOP_BUFFER_SIZE		256	/* zero-ov. loop instr buffer size */
+#define XCHAL_HAVE_NSA			1	/* NSA/NSAU instructions */
+#define XCHAL_HAVE_MINMAX		1	/* MIN/MAX instructions */
+#define XCHAL_HAVE_SEXT			1	/* SEXT instruction */
+#define XCHAL_HAVE_DEPBITS		0	/* DEPBITS instruction */
+#define XCHAL_HAVE_CLAMPS		1	/* CLAMPS instruction */
+#define XCHAL_HAVE_MUL16		1	/* MUL16S/MUL16U instructions */
+#define XCHAL_HAVE_MUL32		1	/* MULL instruction */
+#define XCHAL_HAVE_MUL32_HIGH		1	/* MULUH/MULSH instructions */
+#define XCHAL_HAVE_DIV32		1	/* QUOS/QUOU/REMS/REMU instructions */
+#define XCHAL_HAVE_L32R			1	/* L32R instruction */
+#define XCHAL_HAVE_ABSOLUTE_LITERALS	0	/* non-PC-rel (extended) L32R */
+#define XCHAL_HAVE_CONST16		0	/* CONST16 instruction */
+#define XCHAL_HAVE_ADDX			1	/* ADDX#/SUBX# instructions */
+#define XCHAL_HAVE_WIDE_BRANCHES	0	/* B*.W18 or B*.W15 instr's */
+#define XCHAL_HAVE_PREDICTED_BRANCHES	0	/* B[EQ/EQZ/NE/NEZ]T instr's */
+#define XCHAL_HAVE_CALL4AND12		1	/* (obsolete option) */
+#define XCHAL_HAVE_ABS			1	/* ABS instruction */
+/*#define XCHAL_HAVE_POPC		0*/	/* POPC instruction */
+/*#define XCHAL_HAVE_CRC		0*/	/* CRC instruction */
+#define XCHAL_HAVE_RELEASE_SYNC		1	/* L32AI/S32RI instructions */
+#define XCHAL_HAVE_S32C1I		1	/* S32C1I instruction */
+#define XCHAL_HAVE_SPECULATION		0	/* speculation */
+#define XCHAL_HAVE_FULL_RESET		1	/* all regs/state reset */
+#define XCHAL_NUM_CONTEXTS		1	/* */
+#define XCHAL_NUM_MISC_REGS		4	/* num of scratch regs (0..4) */
+#define XCHAL_HAVE_TAP_MASTER		0	/* JTAG TAP control instr's */
+#define XCHAL_HAVE_PRID			1	/* processor ID register */
+#define XCHAL_HAVE_EXTERN_REGS		1	/* WER/RER instructions */
+#define XCHAL_HAVE_MX			0	/* MX core (Tensilica internal) */
+#define XCHAL_HAVE_MP_INTERRUPTS	0	/* interrupt distributor port */
+#define XCHAL_HAVE_MP_RUNSTALL		0	/* core RunStall control port */
+#define XCHAL_HAVE_PSO			0	/* Power Shut-Off */
+#define XCHAL_HAVE_PSO_CDM		0	/* core/debug/mem pwr domains */
+#define XCHAL_HAVE_PSO_FULL_RETENTION	0	/* all regs preserved on PSO */
+#define XCHAL_HAVE_THREADPTR		1	/* THREADPTR register */
+#define XCHAL_HAVE_BOOLEANS		1	/* boolean registers */
+#define XCHAL_HAVE_CP			1	/* CPENABLE reg (coprocessor) */
+#define XCHAL_CP_MAXCFG			8	/* max allowed cp id plus one */
+#define XCHAL_HAVE_MAC16		1	/* MAC16 package */
+
+#define XCHAL_HAVE_FUSION		 0	/* Fusion*/
+#define XCHAL_HAVE_FUSION_FP	 0	        /* Fusion FP option */
+#define XCHAL_HAVE_FUSION_LOW_POWER 0	/* Fusion Low Power option */
+#define XCHAL_HAVE_FUSION_AES	 0	        /* Fusion BLE/Wifi AES-128 CCM option */
+#define XCHAL_HAVE_FUSION_CONVENC	 0       /* Fusion Conv Encode option */
+#define XCHAL_HAVE_FUSION_LFSR_CRC	 0	/* Fusion LFSR-CRC option */
+#define XCHAL_HAVE_FUSION_BITOPS	 0	/* Fusion Bit Operations Support option */
+#define XCHAL_HAVE_FUSION_AVS	 0	/* Fusion AVS option */
+#define XCHAL_HAVE_FUSION_16BIT_BASEBAND	 0	/* Fusion 16-bit Baseband option */
+#define XCHAL_HAVE_FUSION_VITERBI        0     /* Fusion Viterbi option */
+#define XCHAL_HAVE_FUSION_SOFTDEMAP      0   /* Fusion Soft Bit Demap option */
+#define XCHAL_HAVE_HIFIPRO		0	/* HiFiPro Audio Engine pkg */
+#define XCHAL_HAVE_HIFI4		0	/* HiFi4 Audio Engine pkg */
+#define XCHAL_HAVE_HIFI4_VFPU		0	/* HiFi4 Audio Engine VFPU option */
+#define XCHAL_HAVE_HIFI3		0	/* HiFi3 Audio Engine pkg */
+#define XCHAL_HAVE_HIFI3_VFPU		0	/* HiFi3 Audio Engine VFPU option */
+#define XCHAL_HAVE_HIFI2		0	/* HiFi2 Audio Engine pkg */
+#define XCHAL_HAVE_HIFI2EP		0	/* HiFi2EP */
+#define XCHAL_HAVE_HIFI_MINI		0	
+
+
+#define XCHAL_HAVE_VECTORFPU2005	0	/* vector or user floating-point pkg */
+#define XCHAL_HAVE_USER_DPFPU         0       /* user DP floating-point pkg */
+#define XCHAL_HAVE_USER_SPFPU         0       /* user DP floating-point pkg */
+#define XCHAL_HAVE_FP                 1      /* single prec floating point */
+#define XCHAL_HAVE_FP_DIV             1  /* FP with DIV instructions */
+#define XCHAL_HAVE_FP_RECIP           1        /* FP with RECIP instructions */
+#define XCHAL_HAVE_FP_SQRT            1 /* FP with SQRT instructions */
+#define XCHAL_HAVE_FP_RSQRT           1        /* FP with RSQRT instructions */
+#define XCHAL_HAVE_DFP                        0     /* double precision FP pkg */
+#define XCHAL_HAVE_DFP_DIV            0 /* DFP with DIV instructions */
+#define XCHAL_HAVE_DFP_RECIP          0       /* DFP with RECIP instructions*/
+#define XCHAL_HAVE_DFP_SQRT           0        /* DFP with SQRT instructions */
+#define XCHAL_HAVE_DFP_RSQRT          0       /* DFP with RSQRT instructions*/
+#define XCHAL_HAVE_DFP_ACCEL		1	/* double precision FP acceleration pkg */
+#define XCHAL_HAVE_DFP_accel		XCHAL_HAVE_DFP_ACCEL				/* for backward compatibility */
+
+#define XCHAL_HAVE_DFPU_SINGLE_ONLY    1                 	/* DFPU Coprocessor, single precision only */
+#define XCHAL_HAVE_DFPU_SINGLE_DOUBLE  0               	/* DFPU Coprocessor, single and double precision */
+#define XCHAL_HAVE_VECTRA1		0	/* Vectra I  pkg */
+#define XCHAL_HAVE_VECTRALX		0	/* Vectra LX pkg */
+#define XCHAL_HAVE_PDX4		        0	/* PDX4 */
+#define XCHAL_HAVE_CONNXD2		0	/* ConnX D2 pkg */
+#define XCHAL_HAVE_CONNXD2_DUALLSFLIX   0	/* ConnX D2 & Dual LoadStore Flix */
+#define XCHAL_HAVE_BBE16		0	/* ConnX BBE16 pkg */
+#define XCHAL_HAVE_BBE16_RSQRT		0	/* BBE16 & vector recip sqrt */
+#define XCHAL_HAVE_BBE16_VECDIV		0	/* BBE16 & vector divide */
+#define XCHAL_HAVE_BBE16_DESPREAD	0	/* BBE16 & despread */
+#define XCHAL_HAVE_BBENEP		0	/* ConnX BBENEP pkgs */
+#define XCHAL_HAVE_BSP3			0	/* ConnX BSP3 pkg */
+#define XCHAL_HAVE_BSP3_TRANSPOSE	0	/* BSP3 & transpose32x32 */
+#define XCHAL_HAVE_SSP16		0	/* ConnX SSP16 pkg */
+#define XCHAL_HAVE_SSP16_VITERBI	0	/* SSP16 & viterbi */
+#define XCHAL_HAVE_TURBO16		0	/* ConnX Turbo16 pkg */
+#define XCHAL_HAVE_BBP16		0	/* ConnX BBP16 pkg */
+#define XCHAL_HAVE_FLIX3		0	/* basic 3-way FLIX option */
+#define XCHAL_HAVE_GRIVPEP              0   /*  GRIVPEP is General Release of IVPEP */
+#define XCHAL_HAVE_GRIVPEP_HISTOGRAM    0   /* Histogram option on GRIVPEP */
+
+
+/*----------------------------------------------------------------------
+				MISC
+  ----------------------------------------------------------------------*/
+
+#define XCHAL_NUM_LOADSTORE_UNITS	1	/* load/store units */
+#define XCHAL_NUM_WRITEBUFFER_ENTRIES	4	/* size of write buffer */
+#define XCHAL_INST_FETCH_WIDTH		4	/* instr-fetch width in bytes */
+#define XCHAL_DATA_WIDTH		4	/* data width in bytes */
+#define XCHAL_DATA_PIPE_DELAY		2	/* d-side pipeline delay
+						   (1 = 5-stage, 2 = 7-stage) */
+#define XCHAL_CLOCK_GATING_GLOBAL	1	/* global clock gating */
+#define XCHAL_CLOCK_GATING_FUNCUNIT	1	/* funct. unit clock gating */
+/*  In T1050, applies to selected core load and store instructions (see ISA): */
+#define XCHAL_UNALIGNED_LOAD_EXCEPTION	0	/* unaligned loads cause exc. */
+#define XCHAL_UNALIGNED_STORE_EXCEPTION	0	/* unaligned stores cause exc.*/
+#define XCHAL_UNALIGNED_LOAD_HW		1	/* unaligned loads work in hw */
+#define XCHAL_UNALIGNED_STORE_HW	1	/* unaligned stores work in hw*/
+
+#define XCHAL_SW_VERSION		1100003	/* sw version of this header */
+
+#define XCHAL_CORE_ID			"esp32_v3_49_prod"	/* alphanum core name
+						   (CoreID) set in the Xtensa
+						   Processor Generator */
+
+#define XCHAL_BUILD_UNIQUE_ID		0x0005FE96	/* 22-bit sw build ID */
+
+/*
+ *  These definitions describe the hardware targeted by this software.
+ */
+#define XCHAL_HW_CONFIGID0		0xC2BCFFFE	/* ConfigID hi 32 bits*/
+#define XCHAL_HW_CONFIGID1		0x1CC5FE96	/* ConfigID lo 32 bits*/
+#define XCHAL_HW_VERSION_NAME		"LX6.0.3"	/* full version name */
+#define XCHAL_HW_VERSION_MAJOR		2600	/* major ver# of targeted hw */
+#define XCHAL_HW_VERSION_MINOR		3	/* minor ver# of targeted hw */
+#define XCHAL_HW_VERSION		260003	/* major*100+minor */
+#define XCHAL_HW_REL_LX6		1
+#define XCHAL_HW_REL_LX6_0		1
+#define XCHAL_HW_REL_LX6_0_3		1
+#define XCHAL_HW_CONFIGID_RELIABLE	1
+/*  If software targets a *range* of hardware versions, these are the bounds: */
+#define XCHAL_HW_MIN_VERSION_MAJOR	2600	/* major v of earliest tgt hw */
+#define XCHAL_HW_MIN_VERSION_MINOR	3	/* minor v of earliest tgt hw */
+#define XCHAL_HW_MIN_VERSION		260003	/* earliest targeted hw */
+#define XCHAL_HW_MAX_VERSION_MAJOR	2600	/* major v of latest tgt hw */
+#define XCHAL_HW_MAX_VERSION_MINOR	3	/* minor v of latest tgt hw */
+#define XCHAL_HW_MAX_VERSION		260003	/* latest targeted hw */
+
+
+/*----------------------------------------------------------------------
+				CACHE
+  ----------------------------------------------------------------------*/
+
+#define XCHAL_ICACHE_LINESIZE		4	/* I-cache line size in bytes */
+#define XCHAL_DCACHE_LINESIZE		4	/* D-cache line size in bytes */
+#define XCHAL_ICACHE_LINEWIDTH		2	/* log2(I line size in bytes) */
+#define XCHAL_DCACHE_LINEWIDTH		2	/* log2(D line size in bytes) */
+
+#define XCHAL_ICACHE_SIZE		0	/* I-cache size in bytes or 0 */
+#define XCHAL_DCACHE_SIZE		0	/* D-cache size in bytes or 0 */
+
+#define XCHAL_DCACHE_IS_WRITEBACK	0	/* writeback feature */
+#define XCHAL_DCACHE_IS_COHERENT	0	/* MP coherence feature */
+
+#define XCHAL_HAVE_PREFETCH		0	/* PREFCTL register */
+#define XCHAL_HAVE_PREFETCH_L1		0	/* prefetch to L1 dcache */
+#define XCHAL_PREFETCH_CASTOUT_LINES	0	/* dcache pref. castout bufsz */
+#define XCHAL_PREFETCH_ENTRIES		0	/* cache prefetch entries */
+#define XCHAL_PREFETCH_BLOCK_ENTRIES	0	/* prefetch block streams */
+#define XCHAL_HAVE_CACHE_BLOCKOPS	0	/* block prefetch for caches */
+#define XCHAL_HAVE_ICACHE_TEST		0	/* Icache test instructions */
+#define XCHAL_HAVE_DCACHE_TEST		0	/* Dcache test instructions */
+#define XCHAL_HAVE_ICACHE_DYN_WAYS	0	/* Icache dynamic way support */
+#define XCHAL_HAVE_DCACHE_DYN_WAYS	0	/* Dcache dynamic way support */
+
+
+
+
+/****************************************************************************
+    Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
+ ****************************************************************************/
+
+
+#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
+
+/*----------------------------------------------------------------------
+				CACHE
+  ----------------------------------------------------------------------*/
+
+#define XCHAL_HAVE_PIF			1	/* any outbound PIF present */
+#define XCHAL_HAVE_AXI			0	/* AXI bus */
+
+#define XCHAL_HAVE_PIF_WR_RESP			0	/* pif write response */
+#define XCHAL_HAVE_PIF_REQ_ATTR			0	/* pif attribute */
+
+/*  If present, cache size in bytes == (ways * 2^(linewidth + setwidth)).  */
+
+/*  Number of cache sets in log2(lines per way):  */
+#define XCHAL_ICACHE_SETWIDTH		0
+#define XCHAL_DCACHE_SETWIDTH		0
+
+/*  Cache set associativity (number of ways):  */
+#define XCHAL_ICACHE_WAYS		1
+#define XCHAL_DCACHE_WAYS		1
+
+/*  Cache features:  */
+#define XCHAL_ICACHE_LINE_LOCKABLE	0
+#define XCHAL_DCACHE_LINE_LOCKABLE	0
+#define XCHAL_ICACHE_ECC_PARITY		0
+#define XCHAL_DCACHE_ECC_PARITY		0
+
+/*  Cache access size in bytes (affects operation of SICW instruction):  */
+#define XCHAL_ICACHE_ACCESS_SIZE	1
+#define XCHAL_DCACHE_ACCESS_SIZE	1
+
+#define XCHAL_DCACHE_BANKS		0	/* number of banks */
+
+/*  Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits):  */
+#define XCHAL_CA_BITS			4
+
+
+/*----------------------------------------------------------------------
+			INTERNAL I/D RAM/ROMs and XLMI
+  ----------------------------------------------------------------------*/
+
+#define XCHAL_NUM_INSTROM		1	/* number of core instr. ROMs */
+#define XCHAL_NUM_INSTRAM		2	/* number of core instr. RAMs */
+#define XCHAL_NUM_DATAROM		1	/* number of core data ROMs */
+#define XCHAL_NUM_DATARAM		2	/* number of core data RAMs */
+#define XCHAL_NUM_URAM			0	/* number of core unified RAMs*/
+#define XCHAL_NUM_XLMI			1	/* number of core XLMI ports */
+
+/*  Instruction ROM 0:  */
+#define XCHAL_INSTROM0_VADDR		0x40800000	/* virtual address */
+#define XCHAL_INSTROM0_PADDR		0x40800000	/* physical address */
+#define XCHAL_INSTROM0_SIZE		4194304	/* size in bytes */
+#define XCHAL_INSTROM0_ECC_PARITY	0	/* ECC/parity type, 0=none */
+
+/*  Instruction RAM 0:  */
+#define XCHAL_INSTRAM0_VADDR		0x40000000	/* virtual address */
+#define XCHAL_INSTRAM0_PADDR		0x40000000	/* physical address */
+#define XCHAL_INSTRAM0_SIZE		4194304	/* size in bytes */
+#define XCHAL_INSTRAM0_ECC_PARITY	0	/* ECC/parity type, 0=none */
+
+/*  Instruction RAM 1:  */
+#define XCHAL_INSTRAM1_VADDR		0x40400000	/* virtual address */
+#define XCHAL_INSTRAM1_PADDR		0x40400000	/* physical address */
+#define XCHAL_INSTRAM1_SIZE		4194304	/* size in bytes */
+#define XCHAL_INSTRAM1_ECC_PARITY	0	/* ECC/parity type, 0=none */
+
+/*  Data ROM 0:  */
+#define XCHAL_DATAROM0_VADDR		0x3F400000	/* virtual address */
+#define XCHAL_DATAROM0_PADDR		0x3F400000	/* physical address */
+#define XCHAL_DATAROM0_SIZE		4194304	/* size in bytes */
+#define XCHAL_DATAROM0_ECC_PARITY	0	/* ECC/parity type, 0=none */
+#define XCHAL_DATAROM0_BANKS		1	/* number of banks */
+
+/*  Data RAM 0:  */
+#define XCHAL_DATARAM0_VADDR		0x3FF80000	/* virtual address */
+#define XCHAL_DATARAM0_PADDR		0x3FF80000	/* physical address */
+#define XCHAL_DATARAM0_SIZE		524288	/* size in bytes */
+#define XCHAL_DATARAM0_ECC_PARITY	0	/* ECC/parity type, 0=none */
+#define XCHAL_DATARAM0_BANKS		1	/* number of banks */
+
+/*  Data RAM 1:  */
+#define XCHAL_DATARAM1_VADDR		0x3F800000	/* virtual address */
+#define XCHAL_DATARAM1_PADDR		0x3F800000	/* physical address */
+#define XCHAL_DATARAM1_SIZE		4194304	/* size in bytes */
+#define XCHAL_DATARAM1_ECC_PARITY	0	/* ECC/parity type, 0=none */
+#define XCHAL_DATARAM1_BANKS		1	/* number of banks */
+
+/*  XLMI Port 0:  */
+#define XCHAL_XLMI0_VADDR		0x3FF00000	/* virtual address */
+#define XCHAL_XLMI0_PADDR		0x3FF00000	/* physical address */
+#define XCHAL_XLMI0_SIZE		524288	/* size in bytes */
+#define XCHAL_XLMI0_ECC_PARITY	0	/* ECC/parity type, 0=none */
+
+#define XCHAL_HAVE_IMEM_LOADSTORE	1	/* can load/store to IROM/IRAM*/
+
+
+/*----------------------------------------------------------------------
+			INTERRUPTS and TIMERS
+  ----------------------------------------------------------------------*/
+
+#define XCHAL_HAVE_INTERRUPTS		1	/* interrupt option */
+#define XCHAL_HAVE_HIGHPRI_INTERRUPTS	1	/* med/high-pri. interrupts */
+#define XCHAL_HAVE_NMI			1	/* non-maskable interrupt */
+#define XCHAL_HAVE_CCOUNT		1	/* CCOUNT reg. (timer option) */
+#define XCHAL_NUM_TIMERS		3	/* number of CCOMPAREn regs */
+#define XCHAL_NUM_INTERRUPTS		32	/* number of interrupts */
+#define XCHAL_NUM_INTERRUPTS_LOG2	5	/* ceil(log2(NUM_INTERRUPTS)) */
+#define XCHAL_NUM_EXTINTERRUPTS		26	/* num of external interrupts */
+#define XCHAL_NUM_INTLEVELS		6	/* number of interrupt levels
+						   (not including level zero) */
+#define XCHAL_EXCM_LEVEL		3	/* level masked by PS.EXCM */
+	/* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */
+
+/*  Masks of interrupts at each interrupt level:  */
+#define XCHAL_INTLEVEL1_MASK		0x000637FF
+#define XCHAL_INTLEVEL2_MASK		0x00380000
+#define XCHAL_INTLEVEL3_MASK		0x28C08800
+#define XCHAL_INTLEVEL4_MASK		0x53000000
+#define XCHAL_INTLEVEL5_MASK		0x84010000
+#define XCHAL_INTLEVEL6_MASK		0x00000000
+#define XCHAL_INTLEVEL7_MASK		0x00004000
+
+/*  Masks of interrupts at each range 1..n of interrupt levels:  */
+#define XCHAL_INTLEVEL1_ANDBELOW_MASK	0x000637FF
+#define XCHAL_INTLEVEL2_ANDBELOW_MASK	0x003E37FF
+#define XCHAL_INTLEVEL3_ANDBELOW_MASK	0x28FEBFFF
+#define XCHAL_INTLEVEL4_ANDBELOW_MASK	0x7BFEBFFF
+#define XCHAL_INTLEVEL5_ANDBELOW_MASK	0xFFFFBFFF
+#define XCHAL_INTLEVEL6_ANDBELOW_MASK	0xFFFFBFFF
+#define XCHAL_INTLEVEL7_ANDBELOW_MASK	0xFFFFFFFF
+
+/*  Level of each interrupt:  */
+#define XCHAL_INT0_LEVEL		1
+#define XCHAL_INT1_LEVEL		1
+#define XCHAL_INT2_LEVEL		1
+#define XCHAL_INT3_LEVEL		1
+#define XCHAL_INT4_LEVEL		1
+#define XCHAL_INT5_LEVEL		1
+#define XCHAL_INT6_LEVEL		1
+#define XCHAL_INT7_LEVEL		1
+#define XCHAL_INT8_LEVEL		1
+#define XCHAL_INT9_LEVEL		1
+#define XCHAL_INT10_LEVEL		1
+#define XCHAL_INT11_LEVEL		3
+#define XCHAL_INT12_LEVEL		1
+#define XCHAL_INT13_LEVEL		1
+#define XCHAL_INT14_LEVEL		7
+#define XCHAL_INT15_LEVEL		3
+#define XCHAL_INT16_LEVEL		5
+#define XCHAL_INT17_LEVEL		1
+#define XCHAL_INT18_LEVEL		1
+#define XCHAL_INT19_LEVEL		2
+#define XCHAL_INT20_LEVEL		2
+#define XCHAL_INT21_LEVEL		2
+#define XCHAL_INT22_LEVEL		3
+#define XCHAL_INT23_LEVEL		3
+#define XCHAL_INT24_LEVEL		4
+#define XCHAL_INT25_LEVEL		4
+#define XCHAL_INT26_LEVEL		5
+#define XCHAL_INT27_LEVEL		3
+#define XCHAL_INT28_LEVEL		4
+#define XCHAL_INT29_LEVEL		3
+#define XCHAL_INT30_LEVEL		4
+#define XCHAL_INT31_LEVEL		5
+#define XCHAL_DEBUGLEVEL		6	/* debug interrupt level */
+#define XCHAL_HAVE_DEBUG_EXTERN_INT	1	/* OCD external db interrupt */
+#define XCHAL_NMILEVEL			7	/* NMI "level" (for use with
+						   EXCSAVE/EPS/EPC_n, RFI n) */
+
+/*  Type of each interrupt:  */
+#define XCHAL_INT0_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT1_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT2_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT3_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT4_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT5_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT6_TYPE 	XTHAL_INTTYPE_TIMER
+#define XCHAL_INT7_TYPE 	XTHAL_INTTYPE_SOFTWARE
+#define XCHAL_INT8_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT9_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT10_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT11_TYPE 	XTHAL_INTTYPE_PROFILING
+#define XCHAL_INT12_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT13_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT14_TYPE 	XTHAL_INTTYPE_NMI
+#define XCHAL_INT15_TYPE 	XTHAL_INTTYPE_TIMER
+#define XCHAL_INT16_TYPE 	XTHAL_INTTYPE_TIMER
+#define XCHAL_INT17_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT18_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT19_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT20_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT21_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT22_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT23_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT24_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT25_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT26_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT27_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT28_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT29_TYPE 	XTHAL_INTTYPE_SOFTWARE
+#define XCHAL_INT30_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT31_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
+
+/*  Masks of interrupts for each type of interrupt:  */
+#define XCHAL_INTTYPE_MASK_UNCONFIGURED	0x00000000
+#define XCHAL_INTTYPE_MASK_SOFTWARE	0x20000080
+#define XCHAL_INTTYPE_MASK_EXTERN_EDGE	0x50400400
+#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL	0x8FBE333F
+#define XCHAL_INTTYPE_MASK_TIMER	0x00018040
+#define XCHAL_INTTYPE_MASK_NMI		0x00004000
+#define XCHAL_INTTYPE_MASK_WRITE_ERROR	0x00000000
+#define XCHAL_INTTYPE_MASK_PROFILING	0x00000800
+
+/*  Interrupt numbers assigned to specific interrupt sources:  */
+#define XCHAL_TIMER0_INTERRUPT		6	/* CCOMPARE0 */
+#define XCHAL_TIMER1_INTERRUPT		15	/* CCOMPARE1 */
+#define XCHAL_TIMER2_INTERRUPT		16	/* CCOMPARE2 */
+#define XCHAL_TIMER3_INTERRUPT		XTHAL_TIMER_UNCONFIGURED
+#define XCHAL_NMI_INTERRUPT		14	/* non-maskable interrupt */
+#define XCHAL_PROFILING_INTERRUPT	11	/* profiling interrupt */
+
+/*  Interrupt numbers for levels at which only one interrupt is configured:  */
+#define XCHAL_INTLEVEL7_NUM		14
+/*  (There are many interrupts each at level(s) 1, 2, 3, 4, 5.)  */
+
+
+/*
+ *  External interrupt mapping.
+ *  These macros describe how Xtensa processor interrupt numbers
+ *  (as numbered internally, eg. in INTERRUPT and INTENABLE registers)
+ *  map to external BInterrupt<n> pins, for those interrupts
+ *  configured as external (level-triggered, edge-triggered, or NMI).
+ *  See the Xtensa processor databook for more details.
+ */
+
+/*  Core interrupt numbers mapped to each EXTERNAL BInterrupt pin number:  */
+#define XCHAL_EXTINT0_NUM		0	/* (intlevel 1) */
+#define XCHAL_EXTINT1_NUM		1	/* (intlevel 1) */
+#define XCHAL_EXTINT2_NUM		2	/* (intlevel 1) */
+#define XCHAL_EXTINT3_NUM		3	/* (intlevel 1) */
+#define XCHAL_EXTINT4_NUM		4	/* (intlevel 1) */
+#define XCHAL_EXTINT5_NUM		5	/* (intlevel 1) */
+#define XCHAL_EXTINT6_NUM		8	/* (intlevel 1) */
+#define XCHAL_EXTINT7_NUM		9	/* (intlevel 1) */
+#define XCHAL_EXTINT8_NUM		10	/* (intlevel 1) */
+#define XCHAL_EXTINT9_NUM		12	/* (intlevel 1) */
+#define XCHAL_EXTINT10_NUM		13	/* (intlevel 1) */
+#define XCHAL_EXTINT11_NUM		14	/* (intlevel 7) */
+#define XCHAL_EXTINT12_NUM		17	/* (intlevel 1) */
+#define XCHAL_EXTINT13_NUM		18	/* (intlevel 1) */
+#define XCHAL_EXTINT14_NUM		19	/* (intlevel 2) */
+#define XCHAL_EXTINT15_NUM		20	/* (intlevel 2) */
+#define XCHAL_EXTINT16_NUM		21	/* (intlevel 2) */
+#define XCHAL_EXTINT17_NUM		22	/* (intlevel 3) */
+#define XCHAL_EXTINT18_NUM		23	/* (intlevel 3) */
+#define XCHAL_EXTINT19_NUM		24	/* (intlevel 4) */
+#define XCHAL_EXTINT20_NUM		25	/* (intlevel 4) */
+#define XCHAL_EXTINT21_NUM		26	/* (intlevel 5) */
+#define XCHAL_EXTINT22_NUM		27	/* (intlevel 3) */
+#define XCHAL_EXTINT23_NUM		28	/* (intlevel 4) */
+#define XCHAL_EXTINT24_NUM		30	/* (intlevel 4) */
+#define XCHAL_EXTINT25_NUM		31	/* (intlevel 5) */
+/*  EXTERNAL BInterrupt pin numbers mapped to each core interrupt number:  */
+#define XCHAL_INT0_EXTNUM		0	/* (intlevel 1) */
+#define XCHAL_INT1_EXTNUM		1	/* (intlevel 1) */
+#define XCHAL_INT2_EXTNUM		2	/* (intlevel 1) */
+#define XCHAL_INT3_EXTNUM		3	/* (intlevel 1) */
+#define XCHAL_INT4_EXTNUM		4	/* (intlevel 1) */
+#define XCHAL_INT5_EXTNUM		5	/* (intlevel 1) */
+#define XCHAL_INT8_EXTNUM		6	/* (intlevel 1) */
+#define XCHAL_INT9_EXTNUM		7	/* (intlevel 1) */
+#define XCHAL_INT10_EXTNUM		8	/* (intlevel 1) */
+#define XCHAL_INT12_EXTNUM		9	/* (intlevel 1) */
+#define XCHAL_INT13_EXTNUM		10	/* (intlevel 1) */
+#define XCHAL_INT14_EXTNUM		11	/* (intlevel 7) */
+#define XCHAL_INT17_EXTNUM		12	/* (intlevel 1) */
+#define XCHAL_INT18_EXTNUM		13	/* (intlevel 1) */
+#define XCHAL_INT19_EXTNUM		14	/* (intlevel 2) */
+#define XCHAL_INT20_EXTNUM		15	/* (intlevel 2) */
+#define XCHAL_INT21_EXTNUM		16	/* (intlevel 2) */
+#define XCHAL_INT22_EXTNUM		17	/* (intlevel 3) */
+#define XCHAL_INT23_EXTNUM		18	/* (intlevel 3) */
+#define XCHAL_INT24_EXTNUM		19	/* (intlevel 4) */
+#define XCHAL_INT25_EXTNUM		20	/* (intlevel 4) */
+#define XCHAL_INT26_EXTNUM		21	/* (intlevel 5) */
+#define XCHAL_INT27_EXTNUM		22	/* (intlevel 3) */
+#define XCHAL_INT28_EXTNUM		23	/* (intlevel 4) */
+#define XCHAL_INT30_EXTNUM		24	/* (intlevel 4) */
+#define XCHAL_INT31_EXTNUM		25	/* (intlevel 5) */
+
+
+/*----------------------------------------------------------------------
+			EXCEPTIONS and VECTORS
+  ----------------------------------------------------------------------*/
+
+#define XCHAL_XEA_VERSION		2	/* Xtensa Exception Architecture
+						   number: 1 == XEA1 (old)
+							   2 == XEA2 (new)
+							   0 == XEAX (extern) or TX */
+#define XCHAL_HAVE_XEA1			0	/* Exception Architecture 1 */
+#define XCHAL_HAVE_XEA2			1	/* Exception Architecture 2 */
+#define XCHAL_HAVE_XEAX			0	/* External Exception Arch. */
+#define XCHAL_HAVE_EXCEPTIONS		1	/* exception option */
+#define XCHAL_HAVE_HALT			0	/* halt architecture option */
+#define XCHAL_HAVE_BOOTLOADER		0	/* boot loader (for TX) */
+#define XCHAL_HAVE_MEM_ECC_PARITY	0	/* local memory ECC/parity */
+#define XCHAL_HAVE_VECTOR_SELECT	1	/* relocatable vectors */
+#define XCHAL_HAVE_VECBASE		1	/* relocatable vectors */
+#define XCHAL_VECBASE_RESET_VADDR	0x40000000  /* VECBASE reset value */
+#define XCHAL_VECBASE_RESET_PADDR	0x40000000
+#define XCHAL_RESET_VECBASE_OVERLAP	0
+
+#define XCHAL_RESET_VECTOR0_VADDR	0x50000000
+#define XCHAL_RESET_VECTOR0_PADDR	0x50000000
+#define XCHAL_RESET_VECTOR1_VADDR	0x40000400
+#define XCHAL_RESET_VECTOR1_PADDR	0x40000400
+#define XCHAL_RESET_VECTOR_VADDR	0x40000400
+#define XCHAL_RESET_VECTOR_PADDR	0x40000400
+#define XCHAL_USER_VECOFS		0x00000340
+#define XCHAL_USER_VECTOR_VADDR		0x40000340
+#define XCHAL_USER_VECTOR_PADDR		0x40000340
+#define XCHAL_KERNEL_VECOFS		0x00000300
+#define XCHAL_KERNEL_VECTOR_VADDR	0x40000300
+#define XCHAL_KERNEL_VECTOR_PADDR	0x40000300
+#define XCHAL_DOUBLEEXC_VECOFS		0x000003C0
+#define XCHAL_DOUBLEEXC_VECTOR_VADDR	0x400003C0
+#define XCHAL_DOUBLEEXC_VECTOR_PADDR	0x400003C0
+#define XCHAL_WINDOW_OF4_VECOFS		0x00000000
+#define XCHAL_WINDOW_UF4_VECOFS		0x00000040
+#define XCHAL_WINDOW_OF8_VECOFS		0x00000080
+#define XCHAL_WINDOW_UF8_VECOFS		0x000000C0
+#define XCHAL_WINDOW_OF12_VECOFS	0x00000100
+#define XCHAL_WINDOW_UF12_VECOFS	0x00000140
+#define XCHAL_WINDOW_VECTORS_VADDR	0x40000000
+#define XCHAL_WINDOW_VECTORS_PADDR	0x40000000
+#define XCHAL_INTLEVEL2_VECOFS		0x00000180
+#define XCHAL_INTLEVEL2_VECTOR_VADDR	0x40000180
+#define XCHAL_INTLEVEL2_VECTOR_PADDR	0x40000180
+#define XCHAL_INTLEVEL3_VECOFS		0x000001C0
+#define XCHAL_INTLEVEL3_VECTOR_VADDR	0x400001C0
+#define XCHAL_INTLEVEL3_VECTOR_PADDR	0x400001C0
+#define XCHAL_INTLEVEL4_VECOFS		0x00000200
+#define XCHAL_INTLEVEL4_VECTOR_VADDR	0x40000200
+#define XCHAL_INTLEVEL4_VECTOR_PADDR	0x40000200
+#define XCHAL_INTLEVEL5_VECOFS		0x00000240
+#define XCHAL_INTLEVEL5_VECTOR_VADDR	0x40000240
+#define XCHAL_INTLEVEL5_VECTOR_PADDR	0x40000240
+#define XCHAL_INTLEVEL6_VECOFS		0x00000280
+#define XCHAL_INTLEVEL6_VECTOR_VADDR	0x40000280
+#define XCHAL_INTLEVEL6_VECTOR_PADDR	0x40000280
+#define XCHAL_DEBUG_VECOFS		XCHAL_INTLEVEL6_VECOFS
+#define XCHAL_DEBUG_VECTOR_VADDR	XCHAL_INTLEVEL6_VECTOR_VADDR
+#define XCHAL_DEBUG_VECTOR_PADDR	XCHAL_INTLEVEL6_VECTOR_PADDR
+#define XCHAL_NMI_VECOFS		0x000002C0
+#define XCHAL_NMI_VECTOR_VADDR		0x400002C0
+#define XCHAL_NMI_VECTOR_PADDR		0x400002C0
+#define XCHAL_INTLEVEL7_VECOFS		XCHAL_NMI_VECOFS
+#define XCHAL_INTLEVEL7_VECTOR_VADDR	XCHAL_NMI_VECTOR_VADDR
+#define XCHAL_INTLEVEL7_VECTOR_PADDR	XCHAL_NMI_VECTOR_PADDR
+
+
+/*----------------------------------------------------------------------
+				DEBUG MODULE
+  ----------------------------------------------------------------------*/
+
+/*  Misc  */
+#define XCHAL_HAVE_DEBUG_ERI		1	/* ERI to debug module */
+#define XCHAL_HAVE_DEBUG_APB		1	/* APB to debug module */
+#define XCHAL_HAVE_DEBUG_JTAG		1	/* JTAG to debug module */
+
+/*  On-Chip Debug (OCD)  */
+#define XCHAL_HAVE_OCD			1	/* OnChipDebug option */
+#define XCHAL_NUM_IBREAK		2	/* number of IBREAKn regs */
+#define XCHAL_NUM_DBREAK		2	/* number of DBREAKn regs */
+#define XCHAL_HAVE_OCD_DIR_ARRAY	0	/* faster OCD option (to LX4) */
+#define XCHAL_HAVE_OCD_LS32DDR		1	/* L32DDR/S32DDR (faster OCD) */
+
+/*  TRAX (in core)  */
+#define XCHAL_HAVE_TRAX			1	/* TRAX in debug module */
+#define XCHAL_TRAX_MEM_SIZE		16384	/* TRAX memory size in bytes */
+#define XCHAL_TRAX_MEM_SHAREABLE	1	/* start/end regs; ready sig. */
+#define XCHAL_TRAX_ATB_WIDTH		32	/* ATB width (bits), 0=no ATB */
+#define XCHAL_TRAX_TIME_WIDTH		0	/* timestamp bitwidth, 0=none */
+
+/*  Perf counters  */
+#define XCHAL_NUM_PERF_COUNTERS		2	/* performance counters */
+
+
+/*----------------------------------------------------------------------
+				MMU
+  ----------------------------------------------------------------------*/
+
+/*  See core-matmap.h header file for more details.  */
+
+#define XCHAL_HAVE_TLBS			1	/* inverse of HAVE_CACHEATTR */
+#define XCHAL_HAVE_SPANNING_WAY		1	/* one way maps I+D 4GB vaddr */
+#define XCHAL_SPANNING_WAY		0	/* TLB spanning way number */
+#define XCHAL_HAVE_IDENTITY_MAP		1	/* vaddr == paddr always */
+#define XCHAL_HAVE_CACHEATTR		0	/* CACHEATTR register present */
+#define XCHAL_HAVE_MIMIC_CACHEATTR	1	/* region protection */
+#define XCHAL_HAVE_XLT_CACHEATTR	0	/* region prot. w/translation */
+#define XCHAL_HAVE_PTP_MMU		0	/* full MMU (with page table
+						   [autorefill] and protection)
+						   usable for an MMU-based OS */
+/*  If none of the above last 4 are set, it's a custom TLB configuration.  */
+
+#define XCHAL_MMU_ASID_BITS		0	/* number of bits in ASIDs */
+#define XCHAL_MMU_RINGS			1	/* number of rings (1..4) */
+#define XCHAL_MMU_RING_BITS		0	/* num of bits in RING field */
+
+#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
+
+
+#endif /* _XTENSA_CORE_CONFIGURATION_H */
+

components/esp32/include/xtensa/config/core-matmap.h

@@ -0,0 +1,318 @@
+/* 
+ * xtensa/config/core-matmap.h -- Memory access and translation mapping
+ *	parameters (CHAL) of the Xtensa processor core configuration.
+ *
+ *  If you are using Xtensa Tools, see <xtensa/config/core.h> (which includes
+ *  this file) for more details.
+ *
+ *  In the Xtensa processor products released to date, all parameters
+ *  defined in this file are derivable (at least in theory) from
+ *  information contained in the core-isa.h header file.
+ *  In particular, the following core configuration parameters are relevant:
+ *	XCHAL_HAVE_CACHEATTR
+ *	XCHAL_HAVE_MIMIC_CACHEATTR
+ *	XCHAL_HAVE_XLT_CACHEATTR
+ *	XCHAL_HAVE_PTP_MMU
+ *	XCHAL_ITLB_ARF_ENTRIES_LOG2
+ *	XCHAL_DTLB_ARF_ENTRIES_LOG2
+ *	XCHAL_DCACHE_IS_WRITEBACK
+ *	XCHAL_ICACHE_SIZE		(presence of I-cache)
+ *	XCHAL_DCACHE_SIZE		(presence of D-cache)
+ *	XCHAL_HW_VERSION_MAJOR
+ *	XCHAL_HW_VERSION_MINOR
+ */
+
+/* Customer ID=11657; Build=0x5fe96; Copyright (c) 1999-2016 Tensilica Inc.
+
+   Permission is hereby granted, free of charge, to any person obtaining
+   a copy of this software and associated documentation files (the
+   "Software"), to deal in the Software without restriction, including
+   without limitation the rights to use, copy, modify, merge, publish,
+   distribute, sublicense, and/or sell copies of the Software, and to
+   permit persons to whom the Software is furnished to do so, subject to
+   the following conditions:
+
+   The above copyright notice and this permission notice shall be included
+   in all copies or substantial portions of the Software.
+
+   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
+
+
+#ifndef XTENSA_CONFIG_CORE_MATMAP_H
+#define XTENSA_CONFIG_CORE_MATMAP_H
+
+
+/*----------------------------------------------------------------------
+			CACHE (MEMORY ACCESS) ATTRIBUTES
+  ----------------------------------------------------------------------*/
+
+
+/*  Cache Attribute encodings -- lists of access modes for each cache attribute:  */
+#define XCHAL_FCA_LIST		XTHAL_FAM_EXCEPTION	XCHAL_SEP \
+				XTHAL_FAM_BYPASS	XCHAL_SEP \
+				XTHAL_FAM_BYPASS	XCHAL_SEP \
+				XTHAL_FAM_BYPASS	XCHAL_SEP \
+				XTHAL_FAM_BYPASS	XCHAL_SEP \
+				XTHAL_FAM_BYPASS	XCHAL_SEP \
+				XTHAL_FAM_BYPASS	XCHAL_SEP \
+				XTHAL_FAM_EXCEPTION	XCHAL_SEP \
+				XTHAL_FAM_EXCEPTION	XCHAL_SEP \
+				XTHAL_FAM_EXCEPTION	XCHAL_SEP \
+				XTHAL_FAM_EXCEPTION	XCHAL_SEP \
+				XTHAL_FAM_EXCEPTION	XCHAL_SEP \
+				XTHAL_FAM_EXCEPTION	XCHAL_SEP \
+				XTHAL_FAM_EXCEPTION	XCHAL_SEP \
+				XTHAL_FAM_EXCEPTION	XCHAL_SEP \
+				XTHAL_FAM_EXCEPTION
+#define XCHAL_LCA_LIST		XTHAL_LAM_BYPASSG	XCHAL_SEP \
+				XTHAL_LAM_BYPASSG	XCHAL_SEP \
+				XTHAL_LAM_BYPASSG	XCHAL_SEP \
+				XTHAL_LAM_EXCEPTION	XCHAL_SEP \
+				XTHAL_LAM_BYPASSG	XCHAL_SEP \
+				XTHAL_LAM_BYPASSG	XCHAL_SEP \
+				XTHAL_LAM_BYPASSG	XCHAL_SEP \
+				XTHAL_LAM_EXCEPTION	XCHAL_SEP \
+				XTHAL_LAM_EXCEPTION	XCHAL_SEP \
+				XTHAL_LAM_EXCEPTION	XCHAL_SEP \
+				XTHAL_LAM_EXCEPTION	XCHAL_SEP \
+				XTHAL_LAM_EXCEPTION	XCHAL_SEP \
+				XTHAL_LAM_EXCEPTION	XCHAL_SEP \
+				XTHAL_LAM_EXCEPTION	XCHAL_SEP \
+				XTHAL_LAM_BYPASSG	XCHAL_SEP \
+				XTHAL_LAM_EXCEPTION
+#define XCHAL_SCA_LIST		XTHAL_SAM_BYPASS	XCHAL_SEP \
+				XTHAL_SAM_BYPASS	XCHAL_SEP \
+				XTHAL_SAM_BYPASS	XCHAL_SEP \
+				XTHAL_SAM_EXCEPTION	XCHAL_SEP \
+				XTHAL_SAM_BYPASS	XCHAL_SEP \
+				XTHAL_SAM_BYPASS	XCHAL_SEP \
+				XTHAL_SAM_BYPASS	XCHAL_SEP \
+				XTHAL_SAM_EXCEPTION	XCHAL_SEP \
+				XTHAL_SAM_EXCEPTION	XCHAL_SEP \
+				XTHAL_SAM_EXCEPTION	XCHAL_SEP \
+				XTHAL_SAM_EXCEPTION	XCHAL_SEP \
+				XTHAL_SAM_EXCEPTION	XCHAL_SEP \
+				XTHAL_SAM_EXCEPTION	XCHAL_SEP \
+				XTHAL_SAM_EXCEPTION	XCHAL_SEP \
+				XTHAL_SAM_BYPASS	XCHAL_SEP \
+				XTHAL_SAM_EXCEPTION
+
+
+/*
+ *  Specific encoded cache attribute values of general interest.
+ *  If a specific cache mode is not available, the closest available
+ *  one is returned instead (eg. writethru instead of writeback,
+ *  bypass instead of writethru).
+ */
+#define XCHAL_CA_BYPASS  		2	/* cache disabled (bypassed) mode */
+#define XCHAL_CA_BYPASSBUF  		6	/* cache disabled (bypassed) bufferable mode */
+#define XCHAL_CA_WRITETHRU		2	/* cache enabled (write-through) mode */
+#define XCHAL_CA_WRITEBACK		2	/* cache enabled (write-back) mode */
+#define XCHAL_HAVE_CA_WRITEBACK_NOALLOC	0	/* write-back no-allocate availability */
+#define XCHAL_CA_WRITEBACK_NOALLOC	2	/* cache enabled (write-back no-allocate) mode */
+#define XCHAL_CA_BYPASS_RW  		0	/* cache disabled (bypassed) mode (no exec) */
+#define XCHAL_CA_WRITETHRU_RW		0	/* cache enabled (write-through) mode (no exec) */
+#define XCHAL_CA_WRITEBACK_RW		0	/* cache enabled (write-back) mode (no exec) */
+#define XCHAL_CA_WRITEBACK_NOALLOC_RW	0	/* cache enabled (write-back no-allocate) mode (no exec) */
+#define XCHAL_CA_ILLEGAL		15	/* no access allowed (all cause exceptions) mode */
+#define XCHAL_CA_ISOLATE		0	/* cache isolate (accesses go to cache not memory) mode */
+
+
+/*----------------------------------------------------------------------
+				MMU
+  ----------------------------------------------------------------------*/
+
+/*
+ *  General notes on MMU parameters.
+ *
+ *  Terminology:
+ *	ASID = address-space ID (acts as an "extension" of virtual addresses)
+ *	VPN  = virtual page number
+ *	PPN  = physical page number
+ *	CA   = encoded cache attribute (access modes)
+ *	TLB  = translation look-aside buffer (term is stretched somewhat here)
+ *	I    = instruction (fetch accesses)
+ *	D    = data (load and store accesses)
+ *	way  = each TLB (ITLB and DTLB) consists of a number of "ways"
+ *		that simultaneously match the virtual address of an access;
+ *		a TLB successfully translates a virtual address if exactly
+ *		one way matches the vaddr; if none match, it is a miss;
+ *		if multiple match, one gets a "multihit" exception;
+ *		each way can be independently configured in terms of number of
+ *		entries, page sizes, which fields are writable or constant, etc.
+ *	set  = group of contiguous ways with exactly identical parameters
+ *	ARF  = auto-refill; hardware services a 1st-level miss by loading a PTE
+ *		from the page table and storing it in one of the auto-refill ways;
+ *		if this PTE load also misses, a miss exception is posted for s/w.
+ *	min-wired = a "min-wired" way can be used to map a single (minimum-sized)
+ * 		page arbitrarily under program control; it has a single entry,
+ *		is non-auto-refill (some other way(s) must be auto-refill),
+ *		all its fields (VPN, PPN, ASID, CA) are all writable, and it
+ *		supports the XCHAL_MMU_MIN_PTE_PAGE_SIZE page size (a current
+ *		restriction is that this be the only page size it supports).
+ *
+ *  TLB way entries are virtually indexed.
+ *  TLB ways that support multiple page sizes:
+ *	- must have all writable VPN and PPN fields;
+ *	- can only use one page size at any given time (eg. setup at startup),
+ *	  selected by the respective ITLBCFG or DTLBCFG special register,
+ *	  whose bits n*4+3 .. n*4 index the list of page sizes for way n
+ *	  (XCHAL_xTLB_SETm_PAGESZ_LOG2_LIST for set m corresponding to way n);
+ *	  this list may be sparse for auto-refill ways because auto-refill
+ *	  ways have independent lists of supported page sizes sharing a
+ *	  common encoding with PTE entries; the encoding is the index into
+ *	  this list; unsupported sizes for a given way are zero in the list;
+ *	  selecting unsupported sizes results in undefined hardware behaviour;
+ *	- is only possible for ways 0 thru 7 (due to ITLBCFG/DTLBCFG definition).
+ */
+
+#define XCHAL_MMU_ASID_INVALID		0	/* ASID value indicating invalid address space */
+#define XCHAL_MMU_ASID_KERNEL		0	/* ASID value indicating kernel (ring 0) address space */
+#define XCHAL_MMU_SR_BITS		0	/* number of size-restriction bits supported */
+#define XCHAL_MMU_CA_BITS		4	/* number of bits needed to hold cache attribute encoding */
+#define XCHAL_MMU_MAX_PTE_PAGE_SIZE	29	/* max page size in a PTE structure (log2) */
+#define XCHAL_MMU_MIN_PTE_PAGE_SIZE	29	/* min page size in a PTE structure (log2) */
+
+
+/***  Instruction TLB:  ***/
+
+#define XCHAL_ITLB_WAY_BITS		0	/* number of bits holding the ways */
+#define XCHAL_ITLB_WAYS			1	/* number of ways (n-way set-associative TLB) */
+#define XCHAL_ITLB_ARF_WAYS		0	/* number of auto-refill ways */
+#define XCHAL_ITLB_SETS			1	/* number of sets (groups of ways with identical settings) */
+
+/*  Way set to which each way belongs:  */
+#define XCHAL_ITLB_WAY0_SET		0
+
+/*  Ways sets that are used by hardware auto-refill (ARF):  */
+#define XCHAL_ITLB_ARF_SETS		0	/* number of auto-refill sets */
+
+/*  Way sets that are "min-wired" (see terminology comment above):  */
+#define XCHAL_ITLB_MINWIRED_SETS	0	/* number of "min-wired" sets */
+
+
+/*  ITLB way set 0 (group of ways 0 thru 0):  */
+#define XCHAL_ITLB_SET0_WAY			0	/* index of first way in this way set */
+#define XCHAL_ITLB_SET0_WAYS			1	/* number of (contiguous) ways in this way set */
+#define XCHAL_ITLB_SET0_ENTRIES_LOG2		3	/* log2(number of entries in this way) */
+#define XCHAL_ITLB_SET0_ENTRIES			8	/* number of entries in this way (always a power of 2) */
+#define XCHAL_ITLB_SET0_ARF			0	/* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
+#define XCHAL_ITLB_SET0_PAGESIZES		1	/* number of supported page sizes in this way */
+#define XCHAL_ITLB_SET0_PAGESZ_BITS		0	/* number of bits to encode the page size */
+#define XCHAL_ITLB_SET0_PAGESZ_LOG2_MIN		29	/* log2(minimum supported page size) */
+#define XCHAL_ITLB_SET0_PAGESZ_LOG2_MAX		29	/* log2(maximum supported page size) */
+#define XCHAL_ITLB_SET0_PAGESZ_LOG2_LIST	29	/* list of log2(page size)s, separated by XCHAL_SEP;
+							   2^PAGESZ_BITS entries in list, unsupported entries are zero */
+#define XCHAL_ITLB_SET0_ASID_CONSTMASK		0	/* constant ASID bits; 0 if all writable */
+#define XCHAL_ITLB_SET0_VPN_CONSTMASK		0x00000000	/* constant VPN bits, not including entry index bits; 0 if all writable */
+#define XCHAL_ITLB_SET0_PPN_CONSTMASK		0xE0000000	/* constant PPN bits, including entry index bits; 0 if all writable */
+#define XCHAL_ITLB_SET0_CA_CONSTMASK		0	/* constant CA bits; 0 if all writable */
+#define XCHAL_ITLB_SET0_ASID_RESET		0	/* 1 if ASID reset values defined (and all writable); 0 otherwise */
+#define XCHAL_ITLB_SET0_VPN_RESET		0	/* 1 if VPN reset values defined (and all writable); 0 otherwise */
+#define XCHAL_ITLB_SET0_PPN_RESET		0	/* 1 if PPN reset values defined (and all writable); 0 otherwise */
+#define XCHAL_ITLB_SET0_CA_RESET		1	/* 1 if CA reset values defined (and all writable); 0 otherwise */
+/*  Constant VPN values for each entry of ITLB way set 0 (because VPN_CONSTMASK is non-zero):  */
+#define XCHAL_ITLB_SET0_E0_VPN_CONST		0x00000000
+#define XCHAL_ITLB_SET0_E1_VPN_CONST		0x20000000
+#define XCHAL_ITLB_SET0_E2_VPN_CONST		0x40000000
+#define XCHAL_ITLB_SET0_E3_VPN_CONST		0x60000000
+#define XCHAL_ITLB_SET0_E4_VPN_CONST		0x80000000
+#define XCHAL_ITLB_SET0_E5_VPN_CONST		0xA0000000
+#define XCHAL_ITLB_SET0_E6_VPN_CONST		0xC0000000
+#define XCHAL_ITLB_SET0_E7_VPN_CONST		0xE0000000
+/*  Constant PPN values for each entry of ITLB way set 0 (because PPN_CONSTMASK is non-zero):  */
+#define XCHAL_ITLB_SET0_E0_PPN_CONST		0x00000000
+#define XCHAL_ITLB_SET0_E1_PPN_CONST		0x20000000
+#define XCHAL_ITLB_SET0_E2_PPN_CONST		0x40000000
+#define XCHAL_ITLB_SET0_E3_PPN_CONST		0x60000000
+#define XCHAL_ITLB_SET0_E4_PPN_CONST		0x80000000
+#define XCHAL_ITLB_SET0_E5_PPN_CONST		0xA0000000
+#define XCHAL_ITLB_SET0_E6_PPN_CONST		0xC0000000
+#define XCHAL_ITLB_SET0_E7_PPN_CONST		0xE0000000
+/*  Reset CA values for each entry of ITLB way set 0 (because SET0_CA_RESET is non-zero):  */
+#define XCHAL_ITLB_SET0_E0_CA_RESET		0x02
+#define XCHAL_ITLB_SET0_E1_CA_RESET		0x02
+#define XCHAL_ITLB_SET0_E2_CA_RESET		0x02
+#define XCHAL_ITLB_SET0_E3_CA_RESET		0x02
+#define XCHAL_ITLB_SET0_E4_CA_RESET		0x02
+#define XCHAL_ITLB_SET0_E5_CA_RESET		0x02
+#define XCHAL_ITLB_SET0_E6_CA_RESET		0x02
+#define XCHAL_ITLB_SET0_E7_CA_RESET		0x02
+
+
+/***  Data TLB:  ***/
+
+#define XCHAL_DTLB_WAY_BITS		0	/* number of bits holding the ways */
+#define XCHAL_DTLB_WAYS			1	/* number of ways (n-way set-associative TLB) */
+#define XCHAL_DTLB_ARF_WAYS		0	/* number of auto-refill ways */
+#define XCHAL_DTLB_SETS			1	/* number of sets (groups of ways with identical settings) */
+
+/*  Way set to which each way belongs:  */
+#define XCHAL_DTLB_WAY0_SET		0
+
+/*  Ways sets that are used by hardware auto-refill (ARF):  */
+#define XCHAL_DTLB_ARF_SETS		0	/* number of auto-refill sets */
+
+/*  Way sets that are "min-wired" (see terminology comment above):  */
+#define XCHAL_DTLB_MINWIRED_SETS	0	/* number of "min-wired" sets */
+
+
+/*  DTLB way set 0 (group of ways 0 thru 0):  */
+#define XCHAL_DTLB_SET0_WAY			0	/* index of first way in this way set */
+#define XCHAL_DTLB_SET0_WAYS			1	/* number of (contiguous) ways in this way set */
+#define XCHAL_DTLB_SET0_ENTRIES_LOG2		3	/* log2(number of entries in this way) */
+#define XCHAL_DTLB_SET0_ENTRIES			8	/* number of entries in this way (always a power of 2) */
+#define XCHAL_DTLB_SET0_ARF			0	/* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
+#define XCHAL_DTLB_SET0_PAGESIZES		1	/* number of supported page sizes in this way */
+#define XCHAL_DTLB_SET0_PAGESZ_BITS		0	/* number of bits to encode the page size */
+#define XCHAL_DTLB_SET0_PAGESZ_LOG2_MIN		29	/* log2(minimum supported page size) */
+#define XCHAL_DTLB_SET0_PAGESZ_LOG2_MAX		29	/* log2(maximum supported page size) */
+#define XCHAL_DTLB_SET0_PAGESZ_LOG2_LIST	29	/* list of log2(page size)s, separated by XCHAL_SEP;
+							   2^PAGESZ_BITS entries in list, unsupported entries are zero */
+#define XCHAL_DTLB_SET0_ASID_CONSTMASK		0	/* constant ASID bits; 0 if all writable */
+#define XCHAL_DTLB_SET0_VPN_CONSTMASK		0x00000000	/* constant VPN bits, not including entry index bits; 0 if all writable */
+#define XCHAL_DTLB_SET0_PPN_CONSTMASK		0xE0000000	/* constant PPN bits, including entry index bits; 0 if all writable */
+#define XCHAL_DTLB_SET0_CA_CONSTMASK		0	/* constant CA bits; 0 if all writable */
+#define XCHAL_DTLB_SET0_ASID_RESET		0	/* 1 if ASID reset values defined (and all writable); 0 otherwise */
+#define XCHAL_DTLB_SET0_VPN_RESET		0	/* 1 if VPN reset values defined (and all writable); 0 otherwise */
+#define XCHAL_DTLB_SET0_PPN_RESET		0	/* 1 if PPN reset values defined (and all writable); 0 otherwise */
+#define XCHAL_DTLB_SET0_CA_RESET		1	/* 1 if CA reset values defined (and all writable); 0 otherwise */
+/*  Constant VPN values for each entry of DTLB way set 0 (because VPN_CONSTMASK is non-zero):  */
+#define XCHAL_DTLB_SET0_E0_VPN_CONST		0x00000000
+#define XCHAL_DTLB_SET0_E1_VPN_CONST		0x20000000
+#define XCHAL_DTLB_SET0_E2_VPN_CONST		0x40000000
+#define XCHAL_DTLB_SET0_E3_VPN_CONST		0x60000000
+#define XCHAL_DTLB_SET0_E4_VPN_CONST		0x80000000
+#define XCHAL_DTLB_SET0_E5_VPN_CONST		0xA0000000
+#define XCHAL_DTLB_SET0_E6_VPN_CONST		0xC0000000
+#define XCHAL_DTLB_SET0_E7_VPN_CONST		0xE0000000
+/*  Constant PPN values for each entry of DTLB way set 0 (because PPN_CONSTMASK is non-zero):  */
+#define XCHAL_DTLB_SET0_E0_PPN_CONST		0x00000000
+#define XCHAL_DTLB_SET0_E1_PPN_CONST		0x20000000
+#define XCHAL_DTLB_SET0_E2_PPN_CONST		0x40000000
+#define XCHAL_DTLB_SET0_E3_PPN_CONST		0x60000000
+#define XCHAL_DTLB_SET0_E4_PPN_CONST		0x80000000
+#define XCHAL_DTLB_SET0_E5_PPN_CONST		0xA0000000
+#define XCHAL_DTLB_SET0_E6_PPN_CONST		0xC0000000
+#define XCHAL_DTLB_SET0_E7_PPN_CONST		0xE0000000
+/*  Reset CA values for each entry of DTLB way set 0 (because SET0_CA_RESET is non-zero):  */
+#define XCHAL_DTLB_SET0_E0_CA_RESET		0x02
+#define XCHAL_DTLB_SET0_E1_CA_RESET		0x02
+#define XCHAL_DTLB_SET0_E2_CA_RESET		0x02
+#define XCHAL_DTLB_SET0_E3_CA_RESET		0x02
+#define XCHAL_DTLB_SET0_E4_CA_RESET		0x02
+#define XCHAL_DTLB_SET0_E5_CA_RESET		0x02
+#define XCHAL_DTLB_SET0_E6_CA_RESET		0x02
+#define XCHAL_DTLB_SET0_E7_CA_RESET		0x02
+
+
+
+
+#endif /*XTENSA_CONFIG_CORE_MATMAP_H*/
+

components/esp32/include/xtensa/config/core.h

@@ -0,0 +1,1405 @@
+/* 
+ * xtensa/config/core.h -- HAL definitions dependent on CORE configuration
+ *
+ *  This header file is sometimes referred to as the "compile-time HAL" or CHAL.
+ *  It pulls definitions tailored for a specific Xtensa processor configuration.
+ *
+ *  Sources for binaries meant to be configuration-independent generally avoid
+ *  including this file (they may use the configuration-specific HAL library).
+ *  It is normal for the HAL library source itself to include this file.
+ */
+
+/*
+ * Copyright (c) 2005-2014 Cadence Design Systems, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+
+#ifndef XTENSA_CONFIG_CORE_H
+#define XTENSA_CONFIG_CORE_H
+
+/*  CONFIGURATION INDEPENDENT DEFINITIONS:  */
+#ifdef __XTENSA__
+#include <xtensa/hal.h>
+#include <xtensa/xtensa-versions.h>
+#else
+#include "../hal.h"
+#include "../xtensa-versions.h"
+#endif
+
+/*  CONFIGURATION SPECIFIC DEFINITIONS:  */
+#ifdef __XTENSA__
+#include <xtensa/config/core-isa.h>
+#include <xtensa/config/core-matmap.h>
+#include <xtensa/config/tie.h>
+#else
+#include "core-isa.h"
+#include "core-matmap.h"
+#include "tie.h"
+#endif
+
+#if defined (_ASMLANGUAGE) || defined (__ASSEMBLER__)
+#ifdef __XTENSA__
+#include <xtensa/config/tie-asm.h>
+#else
+#include "tie-asm.h"
+#endif
+#endif /*_ASMLANGUAGE or __ASSEMBLER__*/
+
+
+/*----------------------------------------------------------------------
+				GENERAL
+  ----------------------------------------------------------------------*/
+
+/*
+ *  Separators for macros that expand into arrays.
+ *  These can be predefined by files that #include this one,
+ *  when different separators are required.
+ */
+/*  Element separator for macros that expand into 1-dimensional arrays:  */
+#ifndef XCHAL_SEP
+#define XCHAL_SEP			,
+#endif
+/*  Array separator for macros that expand into 2-dimensional arrays:  */
+#ifndef XCHAL_SEP2
+#define XCHAL_SEP2			},{
+#endif
+
+
+
+/*----------------------------------------------------------------------
+				ISA
+  ----------------------------------------------------------------------*/
+
+#if XCHAL_HAVE_BE
+# define XCHAL_HAVE_LE			0
+# define XCHAL_MEMORY_ORDER		XTHAL_BIGENDIAN
+#else
+# define XCHAL_HAVE_LE			1
+# define XCHAL_MEMORY_ORDER		XTHAL_LITTLEENDIAN
+#endif
+
+
+
+/*----------------------------------------------------------------------
+				INTERRUPTS
+  ----------------------------------------------------------------------*/
+
+/*  Indexing macros:  */
+#define _XCHAL_INTLEVEL_MASK(n)		XCHAL_INTLEVEL ## n ## _MASK
+#define XCHAL_INTLEVEL_MASK(n)		_XCHAL_INTLEVEL_MASK(n)		/* n = 0 .. 15 */
+#define _XCHAL_INTLEVEL_ANDBELOWMASK(n)	XCHAL_INTLEVEL ## n ## _ANDBELOW_MASK
+#define XCHAL_INTLEVEL_ANDBELOW_MASK(n)	_XCHAL_INTLEVEL_ANDBELOWMASK(n)	/* n = 0 .. 15 */
+#define _XCHAL_INTLEVEL_NUM(n)		XCHAL_INTLEVEL ## n ## _NUM
+#define XCHAL_INTLEVEL_NUM(n)		_XCHAL_INTLEVEL_NUM(n)		/* n = 0 .. 15 */
+#define _XCHAL_INT_LEVEL(n)		XCHAL_INT ## n ## _LEVEL
+#define XCHAL_INT_LEVEL(n)		_XCHAL_INT_LEVEL(n)		/* n = 0 .. 31 */
+#define _XCHAL_INT_TYPE(n)		XCHAL_INT ## n ## _TYPE
+#define XCHAL_INT_TYPE(n)		_XCHAL_INT_TYPE(n)		/* n = 0 .. 31 */
+#define _XCHAL_TIMER_INTERRUPT(n)	XCHAL_TIMER ## n ## _INTERRUPT
+#define XCHAL_TIMER_INTERRUPT(n)	_XCHAL_TIMER_INTERRUPT(n)	/* n = 0 .. 3 */
+
+
+#define XCHAL_HAVE_HIGHLEVEL_INTERRUPTS	XCHAL_HAVE_HIGHPRI_INTERRUPTS
+#define XCHAL_NUM_LOWPRI_LEVELS		1			/* number of low-priority interrupt levels (always 1) */
+#define XCHAL_FIRST_HIGHPRI_LEVEL	(XCHAL_NUM_LOWPRI_LEVELS+1)	/* level of first high-priority interrupt (always 2) */
+/*  Note:  1 <= LOWPRI_LEVELS <= EXCM_LEVEL < DEBUGLEVEL <= NUM_INTLEVELS < NMILEVEL <= 15  */
+
+/*  These values are constant for existing Xtensa processor implementations:  */
+#define XCHAL_INTLEVEL0_MASK		0x00000000
+#define XCHAL_INTLEVEL8_MASK		0x00000000
+#define XCHAL_INTLEVEL9_MASK		0x00000000
+#define XCHAL_INTLEVEL10_MASK		0x00000000
+#define XCHAL_INTLEVEL11_MASK		0x00000000
+#define XCHAL_INTLEVEL12_MASK		0x00000000
+#define XCHAL_INTLEVEL13_MASK		0x00000000
+#define XCHAL_INTLEVEL14_MASK		0x00000000
+#define XCHAL_INTLEVEL15_MASK		0x00000000
+
+/*  Array of masks of interrupts at each interrupt level:  */
+#define XCHAL_INTLEVEL_MASKS		XCHAL_INTLEVEL0_MASK \
+			XCHAL_SEP	XCHAL_INTLEVEL1_MASK \
+			XCHAL_SEP	XCHAL_INTLEVEL2_MASK \
+			XCHAL_SEP	XCHAL_INTLEVEL3_MASK \
+			XCHAL_SEP	XCHAL_INTLEVEL4_MASK \
+			XCHAL_SEP	XCHAL_INTLEVEL5_MASK \
+			XCHAL_SEP	XCHAL_INTLEVEL6_MASK \
+			XCHAL_SEP	XCHAL_INTLEVEL7_MASK \
+			XCHAL_SEP	XCHAL_INTLEVEL8_MASK \
+			XCHAL_SEP	XCHAL_INTLEVEL9_MASK \
+			XCHAL_SEP	XCHAL_INTLEVEL10_MASK \
+			XCHAL_SEP	XCHAL_INTLEVEL11_MASK \
+			XCHAL_SEP	XCHAL_INTLEVEL12_MASK \
+			XCHAL_SEP	XCHAL_INTLEVEL13_MASK \
+			XCHAL_SEP	XCHAL_INTLEVEL14_MASK \
+			XCHAL_SEP	XCHAL_INTLEVEL15_MASK
+
+/*  These values are constant for existing Xtensa processor implementations:  */
+#define XCHAL_INTLEVEL0_ANDBELOW_MASK	0x00000000
+#define XCHAL_INTLEVEL8_ANDBELOW_MASK	XCHAL_INTLEVEL7_ANDBELOW_MASK
+#define XCHAL_INTLEVEL9_ANDBELOW_MASK	XCHAL_INTLEVEL7_ANDBELOW_MASK
+#define XCHAL_INTLEVEL10_ANDBELOW_MASK	XCHAL_INTLEVEL7_ANDBELOW_MASK
+#define XCHAL_INTLEVEL11_ANDBELOW_MASK	XCHAL_INTLEVEL7_ANDBELOW_MASK
+#define XCHAL_INTLEVEL12_ANDBELOW_MASK	XCHAL_INTLEVEL7_ANDBELOW_MASK
+#define XCHAL_INTLEVEL13_ANDBELOW_MASK	XCHAL_INTLEVEL7_ANDBELOW_MASK
+#define XCHAL_INTLEVEL14_ANDBELOW_MASK	XCHAL_INTLEVEL7_ANDBELOW_MASK
+#define XCHAL_INTLEVEL15_ANDBELOW_MASK	XCHAL_INTLEVEL7_ANDBELOW_MASK
+
+/*  Mask of all low-priority interrupts:  */
+#define XCHAL_LOWPRI_MASK		XCHAL_INTLEVEL1_ANDBELOW_MASK
+
+/*  Mask of all interrupts masked by PS.EXCM (or CEXCM):  */
+#define XCHAL_EXCM_MASK			XCHAL_INTLEVEL_ANDBELOW_MASK(XCHAL_EXCM_LEVEL)
+
+/*  Array of masks of interrupts at each range 1..n of interrupt levels:  */
+#define XCHAL_INTLEVEL_ANDBELOW_MASKS	XCHAL_INTLEVEL0_ANDBELOW_MASK \
+			XCHAL_SEP	XCHAL_INTLEVEL1_ANDBELOW_MASK \
+			XCHAL_SEP	XCHAL_INTLEVEL2_ANDBELOW_MASK \
+			XCHAL_SEP	XCHAL_INTLEVEL3_ANDBELOW_MASK \
+			XCHAL_SEP	XCHAL_INTLEVEL4_ANDBELOW_MASK \
+			XCHAL_SEP	XCHAL_INTLEVEL5_ANDBELOW_MASK \
+			XCHAL_SEP	XCHAL_INTLEVEL6_ANDBELOW_MASK \
+			XCHAL_SEP	XCHAL_INTLEVEL7_ANDBELOW_MASK \
+			XCHAL_SEP	XCHAL_INTLEVEL8_ANDBELOW_MASK \
+			XCHAL_SEP	XCHAL_INTLEVEL9_ANDBELOW_MASK \
+			XCHAL_SEP	XCHAL_INTLEVEL10_ANDBELOW_MASK \
+			XCHAL_SEP	XCHAL_INTLEVEL11_ANDBELOW_MASK \
+			XCHAL_SEP	XCHAL_INTLEVEL12_ANDBELOW_MASK \
+			XCHAL_SEP	XCHAL_INTLEVEL13_ANDBELOW_MASK \
+			XCHAL_SEP	XCHAL_INTLEVEL14_ANDBELOW_MASK \
+			XCHAL_SEP	XCHAL_INTLEVEL15_ANDBELOW_MASK
+
+#if 0 /*XCHAL_HAVE_NMI*/
+/*  NMI "interrupt level" (for use with EXCSAVE_n, EPS_n, EPC_n, RFI n):  */
+# define XCHAL_NMILEVEL		(XCHAL_NUM_INTLEVELS+1)
+#endif
+
+/*  Array of levels of each possible interrupt:  */
+#define XCHAL_INT_LEVELS		XCHAL_INT0_LEVEL \
+			XCHAL_SEP	XCHAL_INT1_LEVEL \
+			XCHAL_SEP	XCHAL_INT2_LEVEL \
+			XCHAL_SEP	XCHAL_INT3_LEVEL \
+			XCHAL_SEP	XCHAL_INT4_LEVEL \
+			XCHAL_SEP	XCHAL_INT5_LEVEL \
+			XCHAL_SEP	XCHAL_INT6_LEVEL \
+			XCHAL_SEP	XCHAL_INT7_LEVEL \
+			XCHAL_SEP	XCHAL_INT8_LEVEL \
+			XCHAL_SEP	XCHAL_INT9_LEVEL \
+			XCHAL_SEP	XCHAL_INT10_LEVEL \
+			XCHAL_SEP	XCHAL_INT11_LEVEL \
+			XCHAL_SEP	XCHAL_INT12_LEVEL \
+			XCHAL_SEP	XCHAL_INT13_LEVEL \
+			XCHAL_SEP	XCHAL_INT14_LEVEL \
+			XCHAL_SEP	XCHAL_INT15_LEVEL \
+			XCHAL_SEP	XCHAL_INT16_LEVEL \
+			XCHAL_SEP	XCHAL_INT17_LEVEL \
+			XCHAL_SEP	XCHAL_INT18_LEVEL \
+			XCHAL_SEP	XCHAL_INT19_LEVEL \
+			XCHAL_SEP	XCHAL_INT20_LEVEL \
+			XCHAL_SEP	XCHAL_INT21_LEVEL \
+			XCHAL_SEP	XCHAL_INT22_LEVEL \
+			XCHAL_SEP	XCHAL_INT23_LEVEL \
+			XCHAL_SEP	XCHAL_INT24_LEVEL \
+			XCHAL_SEP	XCHAL_INT25_LEVEL \
+			XCHAL_SEP	XCHAL_INT26_LEVEL \
+			XCHAL_SEP	XCHAL_INT27_LEVEL \
+			XCHAL_SEP	XCHAL_INT28_LEVEL \
+			XCHAL_SEP	XCHAL_INT29_LEVEL \
+			XCHAL_SEP	XCHAL_INT30_LEVEL \
+			XCHAL_SEP	XCHAL_INT31_LEVEL
+
+/*  Array of types of each possible interrupt:  */
+#define XCHAL_INT_TYPES			XCHAL_INT0_TYPE \
+			XCHAL_SEP	XCHAL_INT1_TYPE \
+			XCHAL_SEP	XCHAL_INT2_TYPE \
+			XCHAL_SEP	XCHAL_INT3_TYPE \
+			XCHAL_SEP	XCHAL_INT4_TYPE \
+			XCHAL_SEP	XCHAL_INT5_TYPE \
+			XCHAL_SEP	XCHAL_INT6_TYPE \
+			XCHAL_SEP	XCHAL_INT7_TYPE \
+			XCHAL_SEP	XCHAL_INT8_TYPE \
+			XCHAL_SEP	XCHAL_INT9_TYPE \
+			XCHAL_SEP	XCHAL_INT10_TYPE \
+			XCHAL_SEP	XCHAL_INT11_TYPE \
+			XCHAL_SEP	XCHAL_INT12_TYPE \
+			XCHAL_SEP	XCHAL_INT13_TYPE \
+			XCHAL_SEP	XCHAL_INT14_TYPE \
+			XCHAL_SEP	XCHAL_INT15_TYPE \
+			XCHAL_SEP	XCHAL_INT16_TYPE \
+			XCHAL_SEP	XCHAL_INT17_TYPE \
+			XCHAL_SEP	XCHAL_INT18_TYPE \
+			XCHAL_SEP	XCHAL_INT19_TYPE \
+			XCHAL_SEP	XCHAL_INT20_TYPE \
+			XCHAL_SEP	XCHAL_INT21_TYPE \
+			XCHAL_SEP	XCHAL_INT22_TYPE \
+			XCHAL_SEP	XCHAL_INT23_TYPE \
+			XCHAL_SEP	XCHAL_INT24_TYPE \
+			XCHAL_SEP	XCHAL_INT25_TYPE \
+			XCHAL_SEP	XCHAL_INT26_TYPE \
+			XCHAL_SEP	XCHAL_INT27_TYPE \
+			XCHAL_SEP	XCHAL_INT28_TYPE \
+			XCHAL_SEP	XCHAL_INT29_TYPE \
+			XCHAL_SEP	XCHAL_INT30_TYPE \
+			XCHAL_SEP	XCHAL_INT31_TYPE
+
+/*  Array of masks of interrupts for each type of interrupt:  */
+#define XCHAL_INTTYPE_MASKS		XCHAL_INTTYPE_MASK_UNCONFIGURED	\
+			XCHAL_SEP	XCHAL_INTTYPE_MASK_SOFTWARE	\
+			XCHAL_SEP	XCHAL_INTTYPE_MASK_EXTERN_EDGE	\
+			XCHAL_SEP	XCHAL_INTTYPE_MASK_EXTERN_LEVEL	\
+			XCHAL_SEP	XCHAL_INTTYPE_MASK_TIMER	\
+			XCHAL_SEP	XCHAL_INTTYPE_MASK_NMI		\
+			XCHAL_SEP	XCHAL_INTTYPE_MASK_WRITE_ERROR
+
+/*  Interrupts that can be cleared using the INTCLEAR special register:  */
+#define XCHAL_INTCLEARABLE_MASK	(XCHAL_INTTYPE_MASK_SOFTWARE+XCHAL_INTTYPE_MASK_EXTERN_EDGE+XCHAL_INTTYPE_MASK_WRITE_ERROR)
+/*  Interrupts that can be triggered using the INTSET special register:  */
+#define XCHAL_INTSETTABLE_MASK	XCHAL_INTTYPE_MASK_SOFTWARE
+
+/*  Array of interrupts assigned to each timer (CCOMPARE0 to CCOMPARE3):  */
+#define XCHAL_TIMER_INTERRUPTS		XCHAL_TIMER0_INTERRUPT \
+			XCHAL_SEP	XCHAL_TIMER1_INTERRUPT \
+			XCHAL_SEP	XCHAL_TIMER2_INTERRUPT \
+			XCHAL_SEP	XCHAL_TIMER3_INTERRUPT
+
+
+
+/*  For backward compatibility and for the array macros, define macros for
+ *  each unconfigured interrupt number (unfortunately, the value of
+ *  XTHAL_INTTYPE_UNCONFIGURED is not zero):  */
+#if XCHAL_NUM_INTERRUPTS == 0
+# define XCHAL_INT0_LEVEL		0
+# define XCHAL_INT0_TYPE		XTHAL_INTTYPE_UNCONFIGURED
+#endif
+#if XCHAL_NUM_INTERRUPTS <= 1
+# define XCHAL_INT1_LEVEL		0
+# define XCHAL_INT1_TYPE		XTHAL_INTTYPE_UNCONFIGURED
+#endif
+#if XCHAL_NUM_INTERRUPTS <= 2
+# define XCHAL_INT2_LEVEL		0
+# define XCHAL_INT2_TYPE		XTHAL_INTTYPE_UNCONFIGURED
+#endif
+#if XCHAL_NUM_INTERRUPTS <= 3
+# define XCHAL_INT3_LEVEL		0
+# define XCHAL_INT3_TYPE		XTHAL_INTTYPE_UNCONFIGURED
+#endif
+#if XCHAL_NUM_INTERRUPTS <= 4
+# define XCHAL_INT4_LEVEL		0
+# define XCHAL_INT4_TYPE		XTHAL_INTTYPE_UNCONFIGURED
+#endif
+#if XCHAL_NUM_INTERRUPTS <= 5
+# define XCHAL_INT5_LEVEL		0
+# define XCHAL_INT5_TYPE		XTHAL_INTTYPE_UNCONFIGURED
+#endif
+#if XCHAL_NUM_INTERRUPTS <= 6
+# define XCHAL_INT6_LEVEL		0
+# define XCHAL_INT6_TYPE		XTHAL_INTTYPE_UNCONFIGURED
+#endif
+#if XCHAL_NUM_INTERRUPTS <= 7
+# define XCHAL_INT7_LEVEL		0
+# define XCHAL_INT7_TYPE		XTHAL_INTTYPE_UNCONFIGURED
+#endif
+#if XCHAL_NUM_INTERRUPTS <= 8
+# define XCHAL_INT8_LEVEL		0
+# define XCHAL_INT8_TYPE		XTHAL_INTTYPE_UNCONFIGURED
+#endif
+#if XCHAL_NUM_INTERRUPTS <= 9
+# define XCHAL_INT9_LEVEL		0
+# define XCHAL_INT9_TYPE		XTHAL_INTTYPE_UNCONFIGURED
+#endif
+#if XCHAL_NUM_INTERRUPTS <= 10
+# define XCHAL_INT10_LEVEL		0
+# define XCHAL_INT10_TYPE		XTHAL_INTTYPE_UNCONFIGURED
+#endif
+#if XCHAL_NUM_INTERRUPTS <= 11
+# define XCHAL_INT11_LEVEL		0
+# define XCHAL_INT11_TYPE		XTHAL_INTTYPE_UNCONFIGURED
+#endif
+#if XCHAL_NUM_INTERRUPTS <= 12
+# define XCHAL_INT12_LEVEL		0
+# define XCHAL_INT12_TYPE		XTHAL_INTTYPE_UNCONFIGURED
+#endif
+#if XCHAL_NUM_INTERRUPTS <= 13
+# define XCHAL_INT13_LEVEL		0
+# define XCHAL_INT13_TYPE		XTHAL_INTTYPE_UNCONFIGURED
+#endif
+#if XCHAL_NUM_INTERRUPTS <= 14
+# define XCHAL_INT14_LEVEL		0
+# define XCHAL_INT14_TYPE		XTHAL_INTTYPE_UNCONFIGURED
+#endif
+#if XCHAL_NUM_INTERRUPTS <= 15
+# define XCHAL_INT15_LEVEL		0
+# define XCHAL_INT15_TYPE		XTHAL_INTTYPE_UNCONFIGURED
+#endif
+#if XCHAL_NUM_INTERRUPTS <= 16
+# define XCHAL_INT16_LEVEL		0
+# define XCHAL_INT16_TYPE		XTHAL_INTTYPE_UNCONFIGURED
+#endif
+#if XCHAL_NUM_INTERRUPTS <= 17
+# define XCHAL_INT17_LEVEL		0
+# define XCHAL_INT17_TYPE		XTHAL_INTTYPE_UNCONFIGURED
+#endif
+#if XCHAL_NUM_INTERRUPTS <= 18
+# define XCHAL_INT18_LEVEL		0
+# define XCHAL_INT18_TYPE		XTHAL_INTTYPE_UNCONFIGURED
+#endif
+#if XCHAL_NUM_INTERRUPTS <= 19
+# define XCHAL_INT19_LEVEL		0
+# define XCHAL_INT19_TYPE		XTHAL_INTTYPE_UNCONFIGURED
+#endif
+#if XCHAL_NUM_INTERRUPTS <= 20
+# define XCHAL_INT20_LEVEL		0
+# define XCHAL_INT20_TYPE		XTHAL_INTTYPE_UNCONFIGURED
+#endif
+#if XCHAL_NUM_INTERRUPTS <= 21
+# define XCHAL_INT21_LEVEL		0
+# define XCHAL_INT21_TYPE		XTHAL_INTTYPE_UNCONFIGURED
+#endif
+#if XCHAL_NUM_INTERRUPTS <= 22
+# define XCHAL_INT22_LEVEL		0
+# define XCHAL_INT22_TYPE		XTHAL_INTTYPE_UNCONFIGURED
+#endif
+#if XCHAL_NUM_INTERRUPTS <= 23
+# define XCHAL_INT23_LEVEL		0
+# define XCHAL_INT23_TYPE		XTHAL_INTTYPE_UNCONFIGURED
+#endif
+#if XCHAL_NUM_INTERRUPTS <= 24
+# define XCHAL_INT24_LEVEL		0
+# define XCHAL_INT24_TYPE		XTHAL_INTTYPE_UNCONFIGURED
+#endif
+#if XCHAL_NUM_INTERRUPTS <= 25
+# define XCHAL_INT25_LEVEL		0
+# define XCHAL_INT25_TYPE		XTHAL_INTTYPE_UNCONFIGURED
+#endif
+#if XCHAL_NUM_INTERRUPTS <= 26
+# define XCHAL_INT26_LEVEL		0
+# define XCHAL_INT26_TYPE		XTHAL_INTTYPE_UNCONFIGURED
+#endif
+#if XCHAL_NUM_INTERRUPTS <= 27
+# define XCHAL_INT27_LEVEL		0
+# define XCHAL_INT27_TYPE		XTHAL_INTTYPE_UNCONFIGURED
+#endif
+#if XCHAL_NUM_INTERRUPTS <= 28
+# define XCHAL_INT28_LEVEL		0
+# define XCHAL_INT28_TYPE		XTHAL_INTTYPE_UNCONFIGURED
+#endif
+#if XCHAL_NUM_INTERRUPTS <= 29
+# define XCHAL_INT29_LEVEL		0
+# define XCHAL_INT29_TYPE		XTHAL_INTTYPE_UNCONFIGURED
+#endif
+#if XCHAL_NUM_INTERRUPTS <= 30
+# define XCHAL_INT30_LEVEL		0
+# define XCHAL_INT30_TYPE		XTHAL_INTTYPE_UNCONFIGURED
+#endif
+#if XCHAL_NUM_INTERRUPTS <= 31
+# define XCHAL_INT31_LEVEL		0
+# define XCHAL_INT31_TYPE		XTHAL_INTTYPE_UNCONFIGURED
+#endif
+
+
+/*
+ *  Masks and levels corresponding to each *external* interrupt.
+ */
+
+#define XCHAL_EXTINT0_MASK		(1 << XCHAL_EXTINT0_NUM)
+#define XCHAL_EXTINT0_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT0_NUM)
+#define XCHAL_EXTINT1_MASK		(1 << XCHAL_EXTINT1_NUM)
+#define XCHAL_EXTINT1_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT1_NUM)
+#define XCHAL_EXTINT2_MASK		(1 << XCHAL_EXTINT2_NUM)
+#define XCHAL_EXTINT2_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT2_NUM)
+#define XCHAL_EXTINT3_MASK		(1 << XCHAL_EXTINT3_NUM)
+#define XCHAL_EXTINT3_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT3_NUM)
+#define XCHAL_EXTINT4_MASK		(1 << XCHAL_EXTINT4_NUM)
+#define XCHAL_EXTINT4_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT4_NUM)
+#define XCHAL_EXTINT5_MASK		(1 << XCHAL_EXTINT5_NUM)
+#define XCHAL_EXTINT5_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT5_NUM)
+#define XCHAL_EXTINT6_MASK		(1 << XCHAL_EXTINT6_NUM)
+#define XCHAL_EXTINT6_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT6_NUM)
+#define XCHAL_EXTINT7_MASK		(1 << XCHAL_EXTINT7_NUM)
+#define XCHAL_EXTINT7_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT7_NUM)
+#define XCHAL_EXTINT8_MASK		(1 << XCHAL_EXTINT8_NUM)
+#define XCHAL_EXTINT8_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT8_NUM)
+#define XCHAL_EXTINT9_MASK		(1 << XCHAL_EXTINT9_NUM)
+#define XCHAL_EXTINT9_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT9_NUM)
+#define XCHAL_EXTINT10_MASK		(1 << XCHAL_EXTINT10_NUM)
+#define XCHAL_EXTINT10_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT10_NUM)
+#define XCHAL_EXTINT11_MASK		(1 << XCHAL_EXTINT11_NUM)
+#define XCHAL_EXTINT11_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT11_NUM)
+#define XCHAL_EXTINT12_MASK		(1 << XCHAL_EXTINT12_NUM)
+#define XCHAL_EXTINT12_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT12_NUM)
+#define XCHAL_EXTINT13_MASK		(1 << XCHAL_EXTINT13_NUM)
+#define XCHAL_EXTINT13_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT13_NUM)
+#define XCHAL_EXTINT14_MASK		(1 << XCHAL_EXTINT14_NUM)
+#define XCHAL_EXTINT14_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT14_NUM)
+#define XCHAL_EXTINT15_MASK		(1 << XCHAL_EXTINT15_NUM)
+#define XCHAL_EXTINT15_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT15_NUM)
+#define XCHAL_EXTINT16_MASK		(1 << XCHAL_EXTINT16_NUM)
+#define XCHAL_EXTINT16_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT16_NUM)
+#define XCHAL_EXTINT17_MASK		(1 << XCHAL_EXTINT17_NUM)
+#define XCHAL_EXTINT17_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT17_NUM)
+#define XCHAL_EXTINT18_MASK		(1 << XCHAL_EXTINT18_NUM)
+#define XCHAL_EXTINT18_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT18_NUM)
+#define XCHAL_EXTINT19_MASK		(1 << XCHAL_EXTINT19_NUM)
+#define XCHAL_EXTINT19_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT19_NUM)
+#define XCHAL_EXTINT20_MASK		(1 << XCHAL_EXTINT20_NUM)
+#define XCHAL_EXTINT20_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT20_NUM)
+#define XCHAL_EXTINT21_MASK		(1 << XCHAL_EXTINT21_NUM)
+#define XCHAL_EXTINT21_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT21_NUM)
+#define XCHAL_EXTINT22_MASK		(1 << XCHAL_EXTINT22_NUM)
+#define XCHAL_EXTINT22_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT22_NUM)
+#define XCHAL_EXTINT23_MASK		(1 << XCHAL_EXTINT23_NUM)
+#define XCHAL_EXTINT23_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT23_NUM)
+#define XCHAL_EXTINT24_MASK		(1 << XCHAL_EXTINT24_NUM)
+#define XCHAL_EXTINT24_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT24_NUM)
+#define XCHAL_EXTINT25_MASK		(1 << XCHAL_EXTINT25_NUM)
+#define XCHAL_EXTINT25_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT25_NUM)
+#define XCHAL_EXTINT26_MASK		(1 << XCHAL_EXTINT26_NUM)
+#define XCHAL_EXTINT26_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT26_NUM)
+#define XCHAL_EXTINT27_MASK		(1 << XCHAL_EXTINT27_NUM)
+#define XCHAL_EXTINT27_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT27_NUM)
+#define XCHAL_EXTINT28_MASK		(1 << XCHAL_EXTINT28_NUM)
+#define XCHAL_EXTINT28_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT28_NUM)
+#define XCHAL_EXTINT29_MASK		(1 << XCHAL_EXTINT29_NUM)
+#define XCHAL_EXTINT29_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT29_NUM)
+#define XCHAL_EXTINT30_MASK		(1 << XCHAL_EXTINT30_NUM)
+#define XCHAL_EXTINT30_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT30_NUM)
+#define XCHAL_EXTINT31_MASK		(1 << XCHAL_EXTINT31_NUM)
+#define XCHAL_EXTINT31_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT31_NUM)
+
+
+/*----------------------------------------------------------------------
+			EXCEPTIONS and VECTORS
+  ----------------------------------------------------------------------*/
+
+/*  For backward compatibility ONLY -- DO NOT USE (will be removed in future release):  */
+#define XCHAL_HAVE_OLD_EXC_ARCH		XCHAL_HAVE_XEA1	/* (DEPRECATED) 1 if old exception architecture (XEA1), 0 otherwise (eg. XEA2) */
+#define XCHAL_HAVE_EXCM			XCHAL_HAVE_XEA2	/* (DEPRECATED) 1 if PS.EXCM bit exists (currently equals XCHAL_HAVE_TLBS) */
+#ifdef XCHAL_USER_VECTOR_VADDR
+#define XCHAL_PROGRAMEXC_VECTOR_VADDR	XCHAL_USER_VECTOR_VADDR
+#define XCHAL_USEREXC_VECTOR_VADDR	XCHAL_USER_VECTOR_VADDR
+#endif
+#ifdef XCHAL_USER_VECTOR_PADDR
+# define XCHAL_PROGRAMEXC_VECTOR_PADDR	XCHAL_USER_VECTOR_PADDR
+# define XCHAL_USEREXC_VECTOR_PADDR	XCHAL_USER_VECTOR_PADDR
+#endif
+#ifdef XCHAL_KERNEL_VECTOR_VADDR
+# define XCHAL_STACKEDEXC_VECTOR_VADDR	XCHAL_KERNEL_VECTOR_VADDR
+# define XCHAL_KERNELEXC_VECTOR_VADDR	XCHAL_KERNEL_VECTOR_VADDR
+#endif
+#ifdef XCHAL_KERNEL_VECTOR_PADDR
+# define XCHAL_STACKEDEXC_VECTOR_PADDR	XCHAL_KERNEL_VECTOR_PADDR
+# define XCHAL_KERNELEXC_VECTOR_PADDR	XCHAL_KERNEL_VECTOR_PADDR
+#endif
+
+#if 0
+#if XCHAL_HAVE_DEBUG
+# define XCHAL_DEBUG_VECTOR_VADDR	XCHAL_INTLEVEL_VECTOR_VADDR(XCHAL_DEBUGLEVEL)
+/*  This one should only get defined if the corresponding intlevel paddr macro exists:  */
+# define XCHAL_DEBUG_VECTOR_PADDR	XCHAL_INTLEVEL_VECTOR_PADDR(XCHAL_DEBUGLEVEL)
+#endif
+#endif
+
+/*  Indexing macros:  */
+#define _XCHAL_INTLEVEL_VECTOR_VADDR(n)		XCHAL_INTLEVEL ## n ## _VECTOR_VADDR
+#define XCHAL_INTLEVEL_VECTOR_VADDR(n)		_XCHAL_INTLEVEL_VECTOR_VADDR(n)		/* n = 0 .. 15 */
+
+/*
+ *  General Exception Causes
+ *  (values of EXCCAUSE special register set by general exceptions,
+ *   which vector to the user, kernel, or double-exception vectors).
+ *
+ *  DEPRECATED.  Please use the equivalent EXCCAUSE_xxx macros
+ *  defined in <xtensa/corebits.h>.  (Note that these have slightly
+ *  different names, they don't just have the XCHAL_ prefix removed.)
+ */
+#define XCHAL_EXCCAUSE_ILLEGAL_INSTRUCTION		0	/* Illegal Instruction */
+#define XCHAL_EXCCAUSE_SYSTEM_CALL			1	/* System Call */
+#define XCHAL_EXCCAUSE_INSTRUCTION_FETCH_ERROR		2	/* Instruction Fetch Error */
+#define XCHAL_EXCCAUSE_LOAD_STORE_ERROR			3	/* Load Store Error */
+#define XCHAL_EXCCAUSE_LEVEL1_INTERRUPT			4	/* Level 1 Interrupt */
+#define XCHAL_EXCCAUSE_ALLOCA				5	/* Stack Extension Assist */
+#define XCHAL_EXCCAUSE_INTEGER_DIVIDE_BY_ZERO		6	/* Integer Divide by Zero */
+#define XCHAL_EXCCAUSE_SPECULATION			7	/* Speculation */
+#define XCHAL_EXCCAUSE_PRIVILEGED			8	/* Privileged Instruction */
+#define XCHAL_EXCCAUSE_UNALIGNED			9	/* Unaligned Load Store */
+/*10..15 reserved*/
+#define XCHAL_EXCCAUSE_ITLB_MISS			16	/* ITlb Miss Exception */
+#define XCHAL_EXCCAUSE_ITLB_MULTIHIT			17	/* ITlb Mutltihit Exception */
+#define XCHAL_EXCCAUSE_ITLB_PRIVILEGE			18	/* ITlb Privilege Exception */
+#define XCHAL_EXCCAUSE_ITLB_SIZE_RESTRICTION		19	/* ITlb Size Restriction Exception */
+#define XCHAL_EXCCAUSE_FETCH_CACHE_ATTRIBUTE		20	/* Fetch Cache Attribute Exception */
+/*21..23 reserved*/
+#define XCHAL_EXCCAUSE_DTLB_MISS			24	/* DTlb Miss Exception */
+#define XCHAL_EXCCAUSE_DTLB_MULTIHIT			25	/* DTlb Multihit Exception */
+#define XCHAL_EXCCAUSE_DTLB_PRIVILEGE			26	/* DTlb Privilege Exception */
+#define XCHAL_EXCCAUSE_DTLB_SIZE_RESTRICTION		27	/* DTlb Size Restriction Exception */
+#define XCHAL_EXCCAUSE_LOAD_CACHE_ATTRIBUTE		28	/* Load Cache Attribute Exception */
+#define XCHAL_EXCCAUSE_STORE_CACHE_ATTRIBUTE		29	/* Store Cache Attribute Exception */
+/*30..31 reserved*/
+#define XCHAL_EXCCAUSE_COPROCESSOR0_DISABLED		32	/* Coprocessor 0 disabled */
+#define XCHAL_EXCCAUSE_COPROCESSOR1_DISABLED		33	/* Coprocessor 1 disabled */
+#define XCHAL_EXCCAUSE_COPROCESSOR2_DISABLED		34	/* Coprocessor 2 disabled */
+#define XCHAL_EXCCAUSE_COPROCESSOR3_DISABLED		35	/* Coprocessor 3 disabled */
+#define XCHAL_EXCCAUSE_COPROCESSOR4_DISABLED		36	/* Coprocessor 4 disabled */
+#define XCHAL_EXCCAUSE_COPROCESSOR5_DISABLED		37	/* Coprocessor 5 disabled */
+#define XCHAL_EXCCAUSE_COPROCESSOR6_DISABLED		38	/* Coprocessor 6 disabled */
+#define XCHAL_EXCCAUSE_COPROCESSOR7_DISABLED		39	/* Coprocessor 7 disabled */
+/*40..63 reserved*/
+
+
+/*
+ *  Miscellaneous special register fields.
+ *
+ *  For each special register, and each field within each register:
+ *	XCHAL_<regname>_VALIDMASK is the set of bits defined in the register.
+ *	XCHAL_<regname>_<field>_BITS is the number of bits in the field.
+ *	XCHAL_<regname>_<field>_NUM is 2^bits, the number of possible values
+ *			of the field.
+ *	XCHAL_<regname>_<field>_SHIFT is the position of the field within
+ *			the register, starting from the least significant bit.
+ *
+ *  DEPRECATED.  Please use the equivalent macros defined in
+ *  <xtensa/corebits.h>.  (Note that these have different names.)
+ */
+
+/*  DBREAKC (special register number 160):  */
+#define XCHAL_DBREAKC_VALIDMASK		0xC000003F
+#define XCHAL_DBREAKC_MASK_BITS 	6
+#define XCHAL_DBREAKC_MASK_NUM  	64
+#define XCHAL_DBREAKC_MASK_SHIFT	0
+#define XCHAL_DBREAKC_MASK_MASK 	0x0000003F
+#define XCHAL_DBREAKC_LOADBREAK_BITS 	1
+#define XCHAL_DBREAKC_LOADBREAK_NUM  	2
+#define XCHAL_DBREAKC_LOADBREAK_SHIFT	30
+#define XCHAL_DBREAKC_LOADBREAK_MASK 	0x40000000
+#define XCHAL_DBREAKC_STOREBREAK_BITS 	1
+#define XCHAL_DBREAKC_STOREBREAK_NUM  	2
+#define XCHAL_DBREAKC_STOREBREAK_SHIFT	31
+#define XCHAL_DBREAKC_STOREBREAK_MASK 	0x80000000
+/*  PS (special register number 230):  */
+#define XCHAL_PS_VALIDMASK		0x00070F3F
+#define XCHAL_PS_INTLEVEL_BITS 		4
+#define XCHAL_PS_INTLEVEL_NUM  		16
+#define XCHAL_PS_INTLEVEL_SHIFT		0
+#define XCHAL_PS_INTLEVEL_MASK 		0x0000000F
+#define XCHAL_PS_EXCM_BITS 		1
+#define XCHAL_PS_EXCM_NUM  		2
+#define XCHAL_PS_EXCM_SHIFT		4
+#define XCHAL_PS_EXCM_MASK 		0x00000010
+#define XCHAL_PS_UM_BITS 		1
+#define XCHAL_PS_UM_NUM  		2
+#define XCHAL_PS_UM_SHIFT		5
+#define XCHAL_PS_UM_MASK 		0x00000020
+#define XCHAL_PS_RING_BITS 		2
+#define XCHAL_PS_RING_NUM  		4
+#define XCHAL_PS_RING_SHIFT		6
+#define XCHAL_PS_RING_MASK 		0x000000C0
+#define XCHAL_PS_OWB_BITS 		4
+#define XCHAL_PS_OWB_NUM  		16
+#define XCHAL_PS_OWB_SHIFT		8
+#define XCHAL_PS_OWB_MASK 		0x00000F00
+#define XCHAL_PS_CALLINC_BITS 		2
+#define XCHAL_PS_CALLINC_NUM  		4
+#define XCHAL_PS_CALLINC_SHIFT		16
+#define XCHAL_PS_CALLINC_MASK 		0x00030000
+#define XCHAL_PS_WOE_BITS 		1
+#define XCHAL_PS_WOE_NUM  		2
+#define XCHAL_PS_WOE_SHIFT		18
+#define XCHAL_PS_WOE_MASK 		0x00040000
+/*  EXCCAUSE (special register number 232):  */
+#define XCHAL_EXCCAUSE_VALIDMASK	0x0000003F
+#define XCHAL_EXCCAUSE_BITS 		6
+#define XCHAL_EXCCAUSE_NUM  		64
+#define XCHAL_EXCCAUSE_SHIFT		0
+#define XCHAL_EXCCAUSE_MASK 		0x0000003F
+/*  DEBUGCAUSE (special register number 233):  */
+#define XCHAL_DEBUGCAUSE_VALIDMASK	0x0000003F
+#define XCHAL_DEBUGCAUSE_ICOUNT_BITS 	1
+#define XCHAL_DEBUGCAUSE_ICOUNT_NUM  	2
+#define XCHAL_DEBUGCAUSE_ICOUNT_SHIFT	0
+#define XCHAL_DEBUGCAUSE_ICOUNT_MASK 	0x00000001
+#define XCHAL_DEBUGCAUSE_IBREAK_BITS 	1
+#define XCHAL_DEBUGCAUSE_IBREAK_NUM  	2
+#define XCHAL_DEBUGCAUSE_IBREAK_SHIFT	1
+#define XCHAL_DEBUGCAUSE_IBREAK_MASK 	0x00000002
+#define XCHAL_DEBUGCAUSE_DBREAK_BITS 	1
+#define XCHAL_DEBUGCAUSE_DBREAK_NUM  	2
+#define XCHAL_DEBUGCAUSE_DBREAK_SHIFT	2
+#define XCHAL_DEBUGCAUSE_DBREAK_MASK 	0x00000004
+#define XCHAL_DEBUGCAUSE_BREAK_BITS 	1
+#define XCHAL_DEBUGCAUSE_BREAK_NUM  	2
+#define XCHAL_DEBUGCAUSE_BREAK_SHIFT	3
+#define XCHAL_DEBUGCAUSE_BREAK_MASK 	0x00000008
+#define XCHAL_DEBUGCAUSE_BREAKN_BITS 	1
+#define XCHAL_DEBUGCAUSE_BREAKN_NUM  	2
+#define XCHAL_DEBUGCAUSE_BREAKN_SHIFT	4
+#define XCHAL_DEBUGCAUSE_BREAKN_MASK 	0x00000010
+#define XCHAL_DEBUGCAUSE_DEBUGINT_BITS 	1
+#define XCHAL_DEBUGCAUSE_DEBUGINT_NUM  	2
+#define XCHAL_DEBUGCAUSE_DEBUGINT_SHIFT	5
+#define XCHAL_DEBUGCAUSE_DEBUGINT_MASK 	0x00000020
+
+
+
+
+/*----------------------------------------------------------------------
+				TIMERS
+  ----------------------------------------------------------------------*/
+
+/*#define XCHAL_HAVE_TIMERS		XCHAL_HAVE_CCOUNT*/
+
+
+
+/*----------------------------------------------------------------------
+			INTERNAL I/D RAM/ROMs and XLMI
+  ----------------------------------------------------------------------*/
+
+#define  XCHAL_NUM_IROM		XCHAL_NUM_INSTROM	/* (DEPRECATED) */
+#define  XCHAL_NUM_IRAM		XCHAL_NUM_INSTRAM	/* (DEPRECATED) */
+#define  XCHAL_NUM_DROM		XCHAL_NUM_DATAROM	/* (DEPRECATED) */
+#define  XCHAL_NUM_DRAM		XCHAL_NUM_DATARAM	/* (DEPRECATED) */
+
+#define XCHAL_IROM0_VADDR	XCHAL_INSTROM0_VADDR	/* (DEPRECATED) */
+#define XCHAL_IROM0_PADDR	XCHAL_INSTROM0_PADDR	/* (DEPRECATED) */
+#define XCHAL_IROM0_SIZE	XCHAL_INSTROM0_SIZE	/* (DEPRECATED) */
+#define XCHAL_IROM1_VADDR	XCHAL_INSTROM1_VADDR	/* (DEPRECATED) */
+#define XCHAL_IROM1_PADDR	XCHAL_INSTROM1_PADDR	/* (DEPRECATED) */
+#define XCHAL_IROM1_SIZE	XCHAL_INSTROM1_SIZE	/* (DEPRECATED) */
+#define XCHAL_IRAM0_VADDR	XCHAL_INSTRAM0_VADDR	/* (DEPRECATED) */
+#define XCHAL_IRAM0_PADDR	XCHAL_INSTRAM0_PADDR	/* (DEPRECATED) */
+#define XCHAL_IRAM0_SIZE	XCHAL_INSTRAM0_SIZE	/* (DEPRECATED) */
+#define XCHAL_IRAM1_VADDR	XCHAL_INSTRAM1_VADDR	/* (DEPRECATED) */
+#define XCHAL_IRAM1_PADDR	XCHAL_INSTRAM1_PADDR	/* (DEPRECATED) */
+#define XCHAL_IRAM1_SIZE	XCHAL_INSTRAM1_SIZE	/* (DEPRECATED) */
+#define XCHAL_DROM0_VADDR	XCHAL_DATAROM0_VADDR	/* (DEPRECATED) */
+#define XCHAL_DROM0_PADDR	XCHAL_DATAROM0_PADDR	/* (DEPRECATED) */
+#define XCHAL_DROM0_SIZE	XCHAL_DATAROM0_SIZE	/* (DEPRECATED) */
+#define XCHAL_DROM1_VADDR	XCHAL_DATAROM1_VADDR	/* (DEPRECATED) */
+#define XCHAL_DROM1_PADDR	XCHAL_DATAROM1_PADDR	/* (DEPRECATED) */
+#define XCHAL_DROM1_SIZE	XCHAL_DATAROM1_SIZE	/* (DEPRECATED) */
+#define XCHAL_DRAM0_VADDR	XCHAL_DATARAM0_VADDR	/* (DEPRECATED) */
+#define XCHAL_DRAM0_PADDR	XCHAL_DATARAM0_PADDR	/* (DEPRECATED) */
+#define XCHAL_DRAM0_SIZE	XCHAL_DATARAM0_SIZE	/* (DEPRECATED) */
+#define XCHAL_DRAM1_VADDR	XCHAL_DATARAM1_VADDR	/* (DEPRECATED) */
+#define XCHAL_DRAM1_PADDR	XCHAL_DATARAM1_PADDR	/* (DEPRECATED) */
+#define XCHAL_DRAM1_SIZE	XCHAL_DATARAM1_SIZE	/* (DEPRECATED) */
+
+
+
+/*----------------------------------------------------------------------
+				CACHE
+  ----------------------------------------------------------------------*/
+
+
+/*  Default PREFCTL value to enable prefetch.  */
+#if XCHAL_HW_MIN_VERSION < XTENSA_HWVERSION_RE_2012_0
+#define XCHAL_CACHE_PREFCTL_DEFAULT	0x00044	/* enabled, not aggressive */
+#elif XCHAL_HW_MIN_VERSION < XTENSA_HWVERSION_RF_2014_0
+#define XCHAL_CACHE_PREFCTL_DEFAULT	0x01044	/* + enable prefetch to L1 */
+#elif XCHAL_PREFETCH_ENTRIES >= 16
+#define XCHAL_CACHE_PREFCTL_DEFAULT	0x81044	/* 12 entries for block ops */
+#elif XCHAL_PREFETCH_ENTRIES >= 8
+#define XCHAL_CACHE_PREFCTL_DEFAULT	0x51044	/* 5 entries for block ops */
+#else
+#define XCHAL_CACHE_PREFCTL_DEFAULT	0x01044	/* 0 entries for block ops */
+#endif
+
+
+/*  Max for both I-cache and D-cache (used for general alignment):  */
+#if XCHAL_ICACHE_LINESIZE > XCHAL_DCACHE_LINESIZE
+# define XCHAL_CACHE_LINEWIDTH_MAX	XCHAL_ICACHE_LINEWIDTH
+# define XCHAL_CACHE_LINESIZE_MAX	XCHAL_ICACHE_LINESIZE
+#else
+# define XCHAL_CACHE_LINEWIDTH_MAX	XCHAL_DCACHE_LINEWIDTH
+# define XCHAL_CACHE_LINESIZE_MAX	XCHAL_DCACHE_LINESIZE
+#endif
+
+#define XCHAL_ICACHE_SETSIZE		(1<<XCHAL_ICACHE_SETWIDTH)
+#define XCHAL_DCACHE_SETSIZE		(1<<XCHAL_DCACHE_SETWIDTH)
+/*  Max for both I and D caches (used for cache-coherency page alignment):  */
+#if XCHAL_ICACHE_SETWIDTH > XCHAL_DCACHE_SETWIDTH
+# define XCHAL_CACHE_SETWIDTH_MAX	XCHAL_ICACHE_SETWIDTH
+# define XCHAL_CACHE_SETSIZE_MAX	XCHAL_ICACHE_SETSIZE
+#else
+# define XCHAL_CACHE_SETWIDTH_MAX	XCHAL_DCACHE_SETWIDTH
+# define XCHAL_CACHE_SETSIZE_MAX	XCHAL_DCACHE_SETSIZE
+#endif
+
+/*  Instruction cache tag bits:  */
+#define XCHAL_ICACHE_TAG_V_SHIFT	0
+#define XCHAL_ICACHE_TAG_V		0x1	/* valid bit */
+#if XCHAL_ICACHE_WAYS > 1
+# define XCHAL_ICACHE_TAG_F_SHIFT	1
+# define XCHAL_ICACHE_TAG_F		0x2	/* fill (LRU) bit */
+#else
+# define XCHAL_ICACHE_TAG_F_SHIFT	0
+# define XCHAL_ICACHE_TAG_F		0	/* no fill (LRU) bit */
+#endif
+#if XCHAL_ICACHE_LINE_LOCKABLE
+# define XCHAL_ICACHE_TAG_L_SHIFT	(XCHAL_ICACHE_TAG_F_SHIFT+1)
+# define XCHAL_ICACHE_TAG_L		(1 << XCHAL_ICACHE_TAG_L_SHIFT)	/* lock bit */
+#else
+# define XCHAL_ICACHE_TAG_L_SHIFT	XCHAL_ICACHE_TAG_F_SHIFT
+# define XCHAL_ICACHE_TAG_L		0	/* no lock bit */
+#endif
+/*  Data cache tag bits:  */
+#define XCHAL_DCACHE_TAG_V_SHIFT	0
+#define XCHAL_DCACHE_TAG_V		0x1	/* valid bit */
+#if XCHAL_DCACHE_WAYS > 1
+# define XCHAL_DCACHE_TAG_F_SHIFT	1
+# define XCHAL_DCACHE_TAG_F		0x2	/* fill (LRU) bit */
+#else
+# define XCHAL_DCACHE_TAG_F_SHIFT	0
+# define XCHAL_DCACHE_TAG_F		0	/* no fill (LRU) bit */
+#endif
+#if XCHAL_DCACHE_IS_WRITEBACK
+# define XCHAL_DCACHE_TAG_D_SHIFT	(XCHAL_DCACHE_TAG_F_SHIFT+1)
+# define XCHAL_DCACHE_TAG_D		(1 << XCHAL_DCACHE_TAG_D_SHIFT)	/* dirty bit */
+#else
+# define XCHAL_DCACHE_TAG_D_SHIFT	XCHAL_DCACHE_TAG_F_SHIFT
+# define XCHAL_DCACHE_TAG_D		0	/* no dirty bit */
+#endif
+#if XCHAL_DCACHE_LINE_LOCKABLE
+# define XCHAL_DCACHE_TAG_L_SHIFT	(XCHAL_DCACHE_TAG_D_SHIFT+1)
+# define XCHAL_DCACHE_TAG_L		(1 << XCHAL_DCACHE_TAG_L_SHIFT)	/* lock bit */
+#else
+# define XCHAL_DCACHE_TAG_L_SHIFT	XCHAL_DCACHE_TAG_D_SHIFT
+# define XCHAL_DCACHE_TAG_L		0	/* no lock bit */
+#endif
+
+/*  Whether MEMCTL register has anything useful  */
+#define XCHAL_USE_MEMCTL		(((XCHAL_LOOP_BUFFER_SIZE > 0)	||      \
+					XCHAL_DCACHE_IS_COHERENT	||      \
+					XCHAL_HAVE_ICACHE_DYN_WAYS	||      \
+					XCHAL_HAVE_DCACHE_DYN_WAYS)	&&      \
+					(XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RE_2012_0))
+
+/*  Default MEMCTL values:  */
+#if XCHAL_HAVE_ICACHE_DYN_WAYS || XCHAL_HAVE_DCACHE_DYN_WAYS
+/* NOTE: constant defined this way to allow movi instead of l32r in reset code. */
+#define XCHAL_CACHE_MEMCTL_DEFAULT	0xFFFFFF00	/* Init all possible ways */
+#else
+#define XCHAL_CACHE_MEMCTL_DEFAULT	0x00000000	/* Nothing to do */
+#endif
+
+#if XCHAL_DCACHE_IS_COHERENT
+#define _MEMCTL_SNOOP_EN		0x02		/* Enable snoop */
+#else
+#define _MEMCTL_SNOOP_EN		0x00		/* Don't enable snoop */
+#endif
+
+#if (XCHAL_LOOP_BUFFER_SIZE == 0) || XCHAL_ERRATUM_453
+#define _MEMCTL_L0IBUF_EN		0x00		/* No loop buffer or don't enable */
+#else
+#define _MEMCTL_L0IBUF_EN		0x01		/* Enable loop buffer */
+#endif
+
+#define XCHAL_SNOOP_LB_MEMCTL_DEFAULT	(_MEMCTL_SNOOP_EN | _MEMCTL_L0IBUF_EN)
+
+
+/*----------------------------------------------------------------------
+				MMU
+  ----------------------------------------------------------------------*/
+
+/*  See <xtensa/config/core-matmap.h> for more details.  */
+
+/*  Has different semantic in open source headers (where it means HAVE_PTP_MMU),
+    so comment out starting with RB-2008.3 release; later, might get
+    get reintroduced as a synonym for XCHAL_HAVE_PTP_MMU instead:  */
+/*#define XCHAL_HAVE_MMU		XCHAL_HAVE_TLBS*/	/* (DEPRECATED; use XCHAL_HAVE_TLBS instead) */
+
+/*  Indexing macros:  */
+#define _XCHAL_ITLB_SET(n,_what)	XCHAL_ITLB_SET ## n ## _what
+#define XCHAL_ITLB_SET(n,what)		_XCHAL_ITLB_SET(n, _ ## what )
+#define _XCHAL_ITLB_SET_E(n,i,_what)	XCHAL_ITLB_SET ## n ## _E ## i ## _what
+#define XCHAL_ITLB_SET_E(n,i,what)	_XCHAL_ITLB_SET_E(n,i, _ ## what )
+#define _XCHAL_DTLB_SET(n,_what)	XCHAL_DTLB_SET ## n ## _what
+#define XCHAL_DTLB_SET(n,what)		_XCHAL_DTLB_SET(n, _ ## what )
+#define _XCHAL_DTLB_SET_E(n,i,_what)	XCHAL_DTLB_SET ## n ## _E ## i ## _what
+#define XCHAL_DTLB_SET_E(n,i,what)	_XCHAL_DTLB_SET_E(n,i, _ ## what )
+/*
+ *  Example use:  XCHAL_ITLB_SET(XCHAL_ITLB_ARF_SET0,ENTRIES)
+ *	to get the value of XCHAL_ITLB_SET<n>_ENTRIES where <n> is the first auto-refill set.
+ */
+
+/*  Number of entries per autorefill way:  */
+#define XCHAL_ITLB_ARF_ENTRIES		(1<<XCHAL_ITLB_ARF_ENTRIES_LOG2)
+#define XCHAL_DTLB_ARF_ENTRIES		(1<<XCHAL_DTLB_ARF_ENTRIES_LOG2)
+
+/*
+ *  Determine whether we have a full MMU (with Page Table and Protection)
+ *  usable for an MMU-based OS:
+ */
+#if 0
+#if XCHAL_HAVE_TLBS && !XCHAL_HAVE_SPANNING_WAY && XCHAL_ITLB_ARF_WAYS > 0 && XCHAL_DTLB_ARF_WAYS > 0 && XCHAL_MMU_RINGS >= 2
+# define XCHAL_HAVE_PTP_MMU		1	/* have full MMU (with page table [autorefill] and protection) */
+#else
+# define XCHAL_HAVE_PTP_MMU		0	/* don't have full MMU */
+#endif
+#endif
+
+/*
+ *  For full MMUs, report kernel RAM segment and kernel I/O segment static page mappings:
+ */
+#if XCHAL_HAVE_PTP_MMU && !XCHAL_HAVE_SPANNING_WAY
+#define XCHAL_KSEG_CACHED_VADDR		0xD0000000	/* virt.addr of kernel RAM cached static map */
+#define XCHAL_KSEG_CACHED_PADDR		0x00000000	/* phys.addr of kseg_cached */
+#define XCHAL_KSEG_CACHED_SIZE		0x08000000	/* size in bytes of kseg_cached (assumed power of 2!!!) */
+#define XCHAL_KSEG_BYPASS_VADDR		0xD8000000	/* virt.addr of kernel RAM bypass (uncached) static map */
+#define XCHAL_KSEG_BYPASS_PADDR		0x00000000	/* phys.addr of kseg_bypass */
+#define XCHAL_KSEG_BYPASS_SIZE		0x08000000	/* size in bytes of kseg_bypass (assumed power of 2!!!) */
+
+#define XCHAL_KIO_CACHED_VADDR		0xE0000000	/* virt.addr of kernel I/O cached static map */
+#define XCHAL_KIO_CACHED_PADDR		0xF0000000	/* phys.addr of kio_cached */
+#define XCHAL_KIO_CACHED_SIZE		0x10000000	/* size in bytes of kio_cached (assumed power of 2!!!) */
+#define XCHAL_KIO_BYPASS_VADDR		0xF0000000	/* virt.addr of kernel I/O bypass (uncached) static map */
+#define XCHAL_KIO_BYPASS_PADDR		0xF0000000	/* phys.addr of kio_bypass */
+#define XCHAL_KIO_BYPASS_SIZE		0x10000000	/* size in bytes of kio_bypass (assumed power of 2!!!) */
+
+#define XCHAL_SEG_MAPPABLE_VADDR	0x00000000	/* start of largest non-static-mapped virtual addr area */
+#define XCHAL_SEG_MAPPABLE_SIZE		0xD0000000	/* size in bytes of  "  */
+/* define XCHAL_SEG_MAPPABLE2_xxx if more areas present, sorted in order of descending size.  */
+#endif
+
+
+/*----------------------------------------------------------------------
+				MISC
+  ----------------------------------------------------------------------*/
+
+/*  Data alignment required if used for instructions:  */
+#if XCHAL_INST_FETCH_WIDTH > XCHAL_DATA_WIDTH
+# define XCHAL_ALIGN_MAX		XCHAL_INST_FETCH_WIDTH
+#else
+# define XCHAL_ALIGN_MAX		XCHAL_DATA_WIDTH
+#endif
+
+/*
+ *  Names kept for backward compatibility.
+ *  (Here "RELEASE" is now a misnomer; these are product *versions*, not the releases
+ *   under which they are released.  In the T10##.# era there was no distinction.)
+ */
+#define XCHAL_HW_RELEASE_MAJOR		XCHAL_HW_VERSION_MAJOR
+#define XCHAL_HW_RELEASE_MINOR		XCHAL_HW_VERSION_MINOR
+#define XCHAL_HW_RELEASE_NAME		XCHAL_HW_VERSION_NAME
+
+
+
+
+/*----------------------------------------------------------------------
+			COPROCESSORS and EXTRA STATE
+  ----------------------------------------------------------------------*/
+
+#define XCHAL_EXTRA_SA_SIZE		XCHAL_NCP_SA_SIZE
+#define XCHAL_EXTRA_SA_ALIGN		XCHAL_NCP_SA_ALIGN
+#define XCHAL_CPEXTRA_SA_SIZE		XCHAL_TOTAL_SA_SIZE
+#define XCHAL_CPEXTRA_SA_ALIGN		XCHAL_TOTAL_SA_ALIGN
+
+#if defined (_ASMLANGUAGE) || defined (__ASSEMBLER__)
+
+	/*  Invoked at start of save area load/store sequence macro to setup macro
+	 *  internal offsets.  Not usually invoked directly.
+	 *	continue	0 for 1st sequence, 1 for subsequent consecutive ones.
+	 *	totofs		offset from original ptr to next load/store location.
+	 */
+	.macro	xchal_sa_start	continue totofs
+	.ifeq \continue
+	 .set	.Lxchal_pofs_, 0	/* offset from original ptr to current \ptr */
+	 .set	.Lxchal_ofs_, 0		/* offset from current \ptr to next load/store location */
+	.endif
+	.if \totofs + 1			/* if totofs specified (not -1) */
+	 .set	.Lxchal_ofs_, \totofs - .Lxchal_pofs_	/* specific offset from original ptr */
+	.endif
+	.endm
+
+	/*  Align portion of save area and bring ptr in range if necessary.
+	 *  Used by save area load/store sequences.  Not usually invoked directly.
+	 *  Allows combining multiple (sub-)sequences arbitrarily.
+	 *	ptr		pointer to save area (may be off, see .Lxchal_pofs_)
+	 *	minofs,maxofs	range of offset from cur ptr to next load/store loc;
+	 *			minofs <= 0 <= maxofs  (0 must always be valid offset)
+	 *			range must be within +/- 30kB or so.
+	 *	ofsalign	alignment granularity of minofs .. maxofs (pow of 2)
+	 *			(restriction on offset from ptr to next load/store loc)
+	 *	totalign	align from orig ptr to next load/store loc (pow of 2)
+	 */
+	.macro	xchal_sa_align	ptr minofs maxofs ofsalign totalign
+	/*  First align where we start accessing the next register
+	 *  per \totalign relative to original ptr (i.e. start of the save area):
+	 */
+	.set	.Lxchal_ofs_, ((.Lxchal_pofs_ + .Lxchal_ofs_ + \totalign - 1) & -\totalign) - .Lxchal_pofs_
+	/*  If necessary, adjust \ptr to bring .Lxchal_ofs_ in acceptable range:  */
+	.if (((\maxofs) - .Lxchal_ofs_) & 0xC0000000) | ((.Lxchal_ofs_ - (\minofs)) & 0xC0000000) | (.Lxchal_ofs_ & (\ofsalign-1))
+	 .set	.Ligmask, 0xFFFFFFFF	/* TODO: optimize to addmi, per aligns and .Lxchal_ofs_ */
+	 addi	\ptr, \ptr, (.Lxchal_ofs_ & .Ligmask)
+	 .set	.Lxchal_pofs_, .Lxchal_pofs_ + (.Lxchal_ofs_ & .Ligmask)
+	 .set	.Lxchal_ofs_, (.Lxchal_ofs_ & ~.Ligmask)
+	.endif
+	.endm
+	/*
+	 *  We could optimize for addi to expand to only addmi instead of
+	 *  "addmi;addi", where possible.  Here's a partial example how:
+	 * .set	.Lmaxmask, -(\ofsalign) & -(\totalign)
+	 * .if (((\maxofs) + ~.Lmaxmask + 1) & 0xFFFFFF00) && ((.Lxchal_ofs_ & ~.Lmaxmask) == 0)
+	 *  .set	.Ligmask, 0xFFFFFF00
+	 * .elif ... ditto for negative ofs range ...
+	 *  .set .Ligmask, 0xFFFFFF00
+	 *  .set ... adjust per offset ...
+	 * .else
+	 *  .set .Ligmask, 0xFFFFFFFF
+	 * .endif
+	 */
+
+	/*  Invoke this after xchal_XXX_{load,store} macros to restore \ptr.  */
+	.macro	xchal_sa_ptr_restore	ptr
+	.if .Lxchal_pofs_
+	 addi	\ptr, \ptr, - .Lxchal_pofs_
+	 .set	.Lxchal_ofs_, .Lxchal_ofs_ + .Lxchal_pofs_
+	 .set	.Lxchal_pofs_, 0
+	.endif
+	.endm
+
+	/*
+	 *  Use as eg:
+	 *	xchal_atmps_store a1, SOMEOFS, XCHAL_SA_NUM_ATMPS, a4, a5
+	 *	xchal_ncp_load a2, a0,a3,a4,a5
+	 *	xchal_atmps_load  a1, SOMEOFS, XCHAL_SA_NUM_ATMPS, a4, a5
+	 *
+	 *  Specify only the ARs you *haven't* saved/restored already, up to 4.
+	 *  They *must* be the *last* ARs (in same order) specified to save area
+	 *  load/store sequences.  In the example above, a0 and a3 were already
+	 *  saved/restored and unused (thus available) but a4 and a5 were not.
+	 */
+#define xchal_atmps_store	xchal_atmps_loadstore s32i,
+#define xchal_atmps_load	xchal_atmps_loadstore l32i,
+	.macro	xchal_atmps_loadstore	inst ptr offset nreq aa=0 ab=0 ac=0 ad=0
+	.set	.Lnsaved_, 0
+	.irp	reg,\aa,\ab,\ac,\ad
+	 .ifeq 0x\reg ; .set .Lnsaved_,.Lnsaved_+1 ; .endif
+	.endr
+	.set	.Laofs_, 0
+	.irp	reg,\aa,\ab,\ac,\ad
+	 .ifgt (\nreq)-.Lnsaved_
+	  \inst	\reg, \ptr, .Laofs_+\offset
+	  .set	.Laofs_,.Laofs_+4
+	  .set	.Lnsaved_,.Lnsaved_+1
+	 .endif
+	.endr
+	.endm
+
+/*#define xchal_ncp_load_a2	xchal_ncp_load	a2,a3,a4,a5,a6*/
+/*#define xchal_ncp_store_a2	xchal_ncp_store	a2,a3,a4,a5,a6*/
+#define xchal_extratie_load		xchal_ncptie_load
+#define xchal_extratie_store		xchal_ncptie_store
+#define xchal_extratie_load_a2		xchal_ncptie_load  a2,a3,a4,a5,a6
+#define xchal_extratie_store_a2		xchal_ncptie_store a2,a3,a4,a5,a6
+#define xchal_extra_load		xchal_ncp_load
+#define xchal_extra_store		xchal_ncp_store
+#define xchal_extra_load_a2		xchal_ncp_load  a2,a3,a4,a5,a6
+#define xchal_extra_store_a2		xchal_ncp_store a2,a3,a4,a5,a6
+#define xchal_extra_load_funcbody	xchal_ncp_load  a2,a3,a4,a5,a6
+#define xchal_extra_store_funcbody	xchal_ncp_store a2,a3,a4,a5,a6
+#define xchal_cp0_store_a2		xchal_cp0_store  a2,a3,a4,a5,a6
+#define xchal_cp0_load_a2		xchal_cp0_load   a2,a3,a4,a5,a6
+#define xchal_cp1_store_a2		xchal_cp1_store  a2,a3,a4,a5,a6
+#define xchal_cp1_load_a2		xchal_cp1_load   a2,a3,a4,a5,a6
+#define xchal_cp2_store_a2		xchal_cp2_store  a2,a3,a4,a5,a6
+#define xchal_cp2_load_a2		xchal_cp2_load   a2,a3,a4,a5,a6
+#define xchal_cp3_store_a2		xchal_cp3_store  a2,a3,a4,a5,a6
+#define xchal_cp3_load_a2		xchal_cp3_load   a2,a3,a4,a5,a6
+#define xchal_cp4_store_a2		xchal_cp4_store  a2,a3,a4,a5,a6
+#define xchal_cp4_load_a2		xchal_cp4_load   a2,a3,a4,a5,a6
+#define xchal_cp5_store_a2		xchal_cp5_store  a2,a3,a4,a5,a6
+#define xchal_cp5_load_a2		xchal_cp5_load   a2,a3,a4,a5,a6
+#define xchal_cp6_store_a2		xchal_cp6_store  a2,a3,a4,a5,a6
+#define xchal_cp6_load_a2		xchal_cp6_load   a2,a3,a4,a5,a6
+#define xchal_cp7_store_a2		xchal_cp7_store  a2,a3,a4,a5,a6
+#define xchal_cp7_load_a2		xchal_cp7_load   a2,a3,a4,a5,a6
+
+/*  Empty placeholder macros for undefined coprocessors:  */
+#if (XCHAL_CP_MASK & ~XCHAL_CP_PORT_MASK) == 0
+# if XCHAL_CP0_SA_SIZE == 0
+	.macro xchal_cp0_store	p a b c d continue=0 ofs=-1 select=-1 ; .endm
+	.macro xchal_cp0_load	p a b c d continue=0 ofs=-1 select=-1 ; .endm
+# endif
+# if XCHAL_CP1_SA_SIZE == 0
+	.macro xchal_cp1_store	p a b c d continue=0 ofs=-1 select=-1 ; .endm
+	.macro xchal_cp1_load	p a b c d continue=0 ofs=-1 select=-1 ; .endm
+# endif
+# if XCHAL_CP2_SA_SIZE == 0
+	.macro xchal_cp2_store	p a b c d continue=0 ofs=-1 select=-1 ; .endm
+	.macro xchal_cp2_load	p a b c d continue=0 ofs=-1 select=-1 ; .endm
+# endif
+# if XCHAL_CP3_SA_SIZE == 0
+	.macro xchal_cp3_store	p a b c d continue=0 ofs=-1 select=-1 ; .endm
+	.macro xchal_cp3_load	p a b c d continue=0 ofs=-1 select=-1 ; .endm
+# endif
+# if XCHAL_CP4_SA_SIZE == 0
+	.macro xchal_cp4_store	p a b c d continue=0 ofs=-1 select=-1 ; .endm
+	.macro xchal_cp4_load	p a b c d continue=0 ofs=-1 select=-1 ; .endm
+# endif
+# if XCHAL_CP5_SA_SIZE == 0
+	.macro xchal_cp5_store	p a b c d continue=0 ofs=-1 select=-1 ; .endm
+	.macro xchal_cp5_load	p a b c d continue=0 ofs=-1 select=-1 ; .endm
+# endif
+# if XCHAL_CP6_SA_SIZE == 0
+	.macro xchal_cp6_store	p a b c d continue=0 ofs=-1 select=-1 ; .endm
+	.macro xchal_cp6_load	p a b c d continue=0 ofs=-1 select=-1 ; .endm
+# endif
+# if XCHAL_CP7_SA_SIZE == 0
+	.macro xchal_cp7_store	p a b c d continue=0 ofs=-1 select=-1 ; .endm
+	.macro xchal_cp7_load	p a b c d continue=0 ofs=-1 select=-1 ; .endm
+# endif
+#endif
+
+	/********************
+	 *  Macros to create functions that save and restore the state of *any* TIE
+	 *  coprocessor (by dynamic index).
+	 */
+
+	/*
+	 *  Macro that expands to the body of a function
+	 *  that stores the selected coprocessor's state (registers etc).
+	 *	Entry:	a2 = ptr to save area in which to save cp state
+	 *		a3 = coprocessor number
+	 *	Exit:	any register a2-a15 (?) may have been clobbered.
+	 */
+	.macro	xchal_cpi_store_funcbody
+#if (XCHAL_CP_MASK & ~XCHAL_CP_PORT_MASK)
+# if XCHAL_CP0_SA_SIZE
+	bnez	a3, 99f
+	xchal_cp0_store_a2
+	j	90f
+99:
+# endif
+# if XCHAL_CP1_SA_SIZE
+	bnei	a3, 1, 99f
+	xchal_cp1_store_a2
+	j	90f
+99:
+# endif
+# if XCHAL_CP2_SA_SIZE
+	bnei	a3, 2, 99f
+	xchal_cp2_store_a2
+	j	90f
+99:
+# endif
+# if XCHAL_CP3_SA_SIZE
+	bnei	a3, 3, 99f
+	xchal_cp3_store_a2
+	j	90f
+99:
+# endif
+# if XCHAL_CP4_SA_SIZE
+	bnei	a3, 4, 99f
+	xchal_cp4_store_a2
+	j	90f
+99:
+# endif
+# if XCHAL_CP5_SA_SIZE
+	bnei	a3, 5, 99f
+	xchal_cp5_store_a2
+	j	90f
+99:
+# endif
+# if XCHAL_CP6_SA_SIZE
+	bnei	a3, 6, 99f
+	xchal_cp6_store_a2
+	j	90f
+99:
+# endif
+# if XCHAL_CP7_SA_SIZE
+	bnei	a3, 7, 99f
+	xchal_cp7_store_a2
+	j	90f
+99:
+# endif
+90:
+#endif
+	.endm
+
+	/*
+	 *  Macro that expands to the body of a function
+	 *  that loads the selected coprocessor's state (registers etc).
+	 *	Entry:	a2 = ptr to save area from which to restore cp state
+	 *		a3 = coprocessor number
+	 *	Exit:	any register a2-a15 (?) may have been clobbered.
+	 */
+	.macro	xchal_cpi_load_funcbody
+#if (XCHAL_CP_MASK & ~XCHAL_CP_PORT_MASK)
+# if XCHAL_CP0_SA_SIZE
+	bnez	a3, 99f
+	xchal_cp0_load_a2
+	j	90f
+99:
+# endif
+# if XCHAL_CP1_SA_SIZE
+	bnei	a3, 1, 99f
+	xchal_cp1_load_a2
+	j	90f
+99:
+# endif
+# if XCHAL_CP2_SA_SIZE
+	bnei	a3, 2, 99f
+	xchal_cp2_load_a2
+	j	90f
+99:
+# endif
+# if XCHAL_CP3_SA_SIZE
+	bnei	a3, 3, 99f
+	xchal_cp3_load_a2
+	j	90f
+99:
+# endif
+# if XCHAL_CP4_SA_SIZE
+	bnei	a3, 4, 99f
+	xchal_cp4_load_a2
+	j	90f
+99:
+# endif
+# if XCHAL_CP5_SA_SIZE
+	bnei	a3, 5, 99f
+	xchal_cp5_load_a2
+	j	90f
+99:
+# endif
+# if XCHAL_CP6_SA_SIZE
+	bnei	a3, 6, 99f
+	xchal_cp6_load_a2
+	j	90f
+99:
+# endif
+# if XCHAL_CP7_SA_SIZE
+	bnei	a3, 7, 99f
+	xchal_cp7_load_a2
+	j	90f
+99:
+# endif
+90:
+#endif
+	.endm
+
+#endif /*_ASMLANGUAGE or __ASSEMBLER__*/
+
+
+/*  Other default macros for undefined coprocessors:  */
+#ifndef XCHAL_CP0_NAME
+# define XCHAL_CP0_NAME				0
+# define XCHAL_CP0_SA_CONTENTS_LIBDB_NUM	0
+# define XCHAL_CP0_SA_CONTENTS_LIBDB		/* empty */
+#endif
+#ifndef XCHAL_CP1_NAME
+# define XCHAL_CP1_NAME				0
+# define XCHAL_CP1_SA_CONTENTS_LIBDB_NUM	0
+# define XCHAL_CP1_SA_CONTENTS_LIBDB		/* empty */
+#endif
+#ifndef XCHAL_CP2_NAME
+# define XCHAL_CP2_NAME				0
+# define XCHAL_CP2_SA_CONTENTS_LIBDB_NUM	0
+# define XCHAL_CP2_SA_CONTENTS_LIBDB		/* empty */
+#endif
+#ifndef XCHAL_CP3_NAME
+# define XCHAL_CP3_NAME				0
+# define XCHAL_CP3_SA_CONTENTS_LIBDB_NUM	0
+# define XCHAL_CP3_SA_CONTENTS_LIBDB		/* empty */
+#endif
+#ifndef XCHAL_CP4_NAME
+# define XCHAL_CP4_NAME				0
+# define XCHAL_CP4_SA_CONTENTS_LIBDB_NUM	0
+# define XCHAL_CP4_SA_CONTENTS_LIBDB		/* empty */
+#endif
+#ifndef XCHAL_CP5_NAME
+# define XCHAL_CP5_NAME				0
+# define XCHAL_CP5_SA_CONTENTS_LIBDB_NUM	0
+# define XCHAL_CP5_SA_CONTENTS_LIBDB		/* empty */
+#endif
+#ifndef XCHAL_CP6_NAME
+# define XCHAL_CP6_NAME				0
+# define XCHAL_CP6_SA_CONTENTS_LIBDB_NUM	0
+# define XCHAL_CP6_SA_CONTENTS_LIBDB		/* empty */
+#endif
+#ifndef XCHAL_CP7_NAME
+# define XCHAL_CP7_NAME				0
+# define XCHAL_CP7_SA_CONTENTS_LIBDB_NUM	0
+# define XCHAL_CP7_SA_CONTENTS_LIBDB		/* empty */
+#endif
+
+#if XCHAL_CP_MASK == 0
+/*  Filler info for unassigned coprocessors, to simplify arrays etc:  */
+#define XCHAL_CP0_SA_SIZE               0
+#define XCHAL_CP0_SA_ALIGN              1
+#define XCHAL_CP1_SA_SIZE               0
+#define XCHAL_CP1_SA_ALIGN              1
+#define XCHAL_CP2_SA_SIZE               0
+#define XCHAL_CP2_SA_ALIGN              1
+#define XCHAL_CP3_SA_SIZE               0
+#define XCHAL_CP3_SA_ALIGN              1
+#define XCHAL_CP4_SA_SIZE               0
+#define XCHAL_CP4_SA_ALIGN              1
+#define XCHAL_CP5_SA_SIZE               0
+#define XCHAL_CP5_SA_ALIGN              1
+#define XCHAL_CP6_SA_SIZE               0
+#define XCHAL_CP6_SA_ALIGN              1
+#define XCHAL_CP7_SA_SIZE               0
+#define XCHAL_CP7_SA_ALIGN              1
+#endif
+
+
+/*  Indexing macros:  */
+#define _XCHAL_CP_SA_SIZE(n)		XCHAL_CP ## n ## _SA_SIZE
+#define XCHAL_CP_SA_SIZE(n)		_XCHAL_CP_SA_SIZE(n)	/* n = 0 .. 7 */
+#define _XCHAL_CP_SA_ALIGN(n)		XCHAL_CP ## n ## _SA_ALIGN
+#define XCHAL_CP_SA_ALIGN(n)		_XCHAL_CP_SA_ALIGN(n)	/* n = 0 .. 7 */
+
+#define XCHAL_CPEXTRA_SA_SIZE_TOR2      XCHAL_CPEXTRA_SA_SIZE	/* Tor2Beta only - do not use */
+
+/*  Link-time HAL global variables that report coprocessor numbers by name
+    (names are case-preserved from the original TIE):  */
+#if !defined(_ASMLANGUAGE) && !defined(_NOCLANGUAGE) && !defined(__ASSEMBLER__)
+# define _XCJOIN(a,b)	a ## b
+# define XCJOIN(a,b)	_XCJOIN(a,b)
+# ifdef XCHAL_CP0_NAME
+extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP0_IDENT);
+extern const unsigned int  XCJOIN(Xthal_cp_mask_,XCHAL_CP0_IDENT);
+# endif
+# ifdef XCHAL_CP1_NAME
+extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP1_IDENT);
+extern const unsigned int  XCJOIN(Xthal_cp_mask_,XCHAL_CP1_IDENT);
+# endif
+# ifdef XCHAL_CP2_NAME
+extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP2_IDENT);
+extern const unsigned int  XCJOIN(Xthal_cp_mask_,XCHAL_CP2_IDENT);
+# endif
+# ifdef XCHAL_CP3_NAME
+extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP3_IDENT);
+extern const unsigned int  XCJOIN(Xthal_cp_mask_,XCHAL_CP3_IDENT);
+# endif
+# ifdef XCHAL_CP4_NAME
+extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP4_IDENT);
+extern const unsigned int  XCJOIN(Xthal_cp_mask_,XCHAL_CP4_IDENT);
+# endif
+# ifdef XCHAL_CP5_NAME
+extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP5_IDENT);
+extern const unsigned int  XCJOIN(Xthal_cp_mask_,XCHAL_CP5_IDENT);
+# endif
+# ifdef XCHAL_CP6_NAME
+extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP6_IDENT);
+extern const unsigned int  XCJOIN(Xthal_cp_mask_,XCHAL_CP6_IDENT);
+# endif
+# ifdef XCHAL_CP7_NAME
+extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP7_IDENT);
+extern const unsigned int  XCJOIN(Xthal_cp_mask_,XCHAL_CP7_IDENT);
+# endif
+#endif
+
+
+
+
+/*----------------------------------------------------------------------
+				DERIVED
+  ----------------------------------------------------------------------*/
+
+#if XCHAL_HAVE_BE
+#define XCHAL_INST_ILLN			0xD60F		/* 2-byte illegal instruction, msb-first */
+#define XCHAL_INST_ILLN_BYTE0		0xD6		/* 2-byte illegal instruction, 1st byte */
+#define XCHAL_INST_ILLN_BYTE1		0x0F		/* 2-byte illegal instruction, 2nd byte */
+#else
+#define XCHAL_INST_ILLN			0xF06D		/* 2-byte illegal instruction, lsb-first */
+#define XCHAL_INST_ILLN_BYTE0		0x6D		/* 2-byte illegal instruction, 1st byte */
+#define XCHAL_INST_ILLN_BYTE1		0xF0		/* 2-byte illegal instruction, 2nd byte */
+#endif
+/*  Belongs in xtensa/hal.h:  */
+#define XTHAL_INST_ILL			0x000000	/* 3-byte illegal instruction */
+
+
+/*
+ *  Because information as to exactly which hardware version is targeted
+ *  by a given software build is not always available, compile-time HAL
+ *  Hardware-Release "_AT" macros are fuzzy (return 0, 1, or XCHAL_MAYBE):
+ *  (Here "RELEASE" is now a misnomer; these are product *versions*, not the releases
+ *   under which they are released.  In the T10##.# era there was no distinction.)
+ */
+#if XCHAL_HW_CONFIGID_RELIABLE
+# define XCHAL_HW_RELEASE_AT_OR_BELOW(major,minor)	(XTHAL_REL_LE( XCHAL_HW_VERSION_MAJOR,XCHAL_HW_VERSION_MINOR, major,minor ) ? 1 : 0)
+# define XCHAL_HW_RELEASE_AT_OR_ABOVE(major,minor)	(XTHAL_REL_GE( XCHAL_HW_VERSION_MAJOR,XCHAL_HW_VERSION_MINOR, major,minor ) ? 1 : 0)
+# define XCHAL_HW_RELEASE_AT(major,minor)		(XTHAL_REL_EQ( XCHAL_HW_VERSION_MAJOR,XCHAL_HW_VERSION_MINOR, major,minor ) ? 1 : 0)
+# define XCHAL_HW_RELEASE_MAJOR_AT(major)		((XCHAL_HW_VERSION_MAJOR == (major)) ? 1 : 0)
+#else
+# define XCHAL_HW_RELEASE_AT_OR_BELOW(major,minor)	( ((major) < 1040 && XCHAL_HAVE_XEA2) ? 0 \
+							: ((major) > 1050 && XCHAL_HAVE_XEA1) ? 1 \
+							: XTHAL_MAYBE )
+# define XCHAL_HW_RELEASE_AT_OR_ABOVE(major,minor)	( ((major) >= 2000 && XCHAL_HAVE_XEA1) ? 0 \
+							: (XTHAL_REL_LE(major,minor, 1040,0) && XCHAL_HAVE_XEA2) ? 1 \
+							: XTHAL_MAYBE )
+# define XCHAL_HW_RELEASE_AT(major,minor)		( (((major) < 1040 && XCHAL_HAVE_XEA2) || \
+							   ((major) >= 2000 && XCHAL_HAVE_XEA1)) ? 0 : XTHAL_MAYBE)
+# define XCHAL_HW_RELEASE_MAJOR_AT(major)		XCHAL_HW_RELEASE_AT(major,0)
+#endif
+
+/*
+ *  Specific errata:
+ */
+
+/*
+ *  Erratum T1020.H13, T1030.H7, T1040.H10, T1050.H4 (fixed in T1040.3 and T1050.1;
+ *  relevant only in XEA1, kernel-vector mode, level-one interrupts and overflows enabled):
+ */
+#define XCHAL_MAYHAVE_ERRATUM_XEA1KWIN	(XCHAL_HAVE_XEA1 && \
+					 (XCHAL_HW_RELEASE_AT_OR_BELOW(1040,2) != 0 \
+					  || XCHAL_HW_RELEASE_AT(1050,0)))
+/*
+ *  Erratum 453 present in RE-2013.2 up to RF-2014.0, fixed in RF-2014.1.
+ *  Applies to specific set of configuration options.
+ *  Part of the workaround is to add ISYNC at certain points in the code.
+ *  The workaround gated by this macro can be disabled if not needed, e.g. if
+ *  zero-overhead loop buffer will be disabled, by defining _NO_ERRATUM_453.
+ */
+#if (	XCHAL_HW_MAX_VERSION >= XTENSA_HWVERSION_RE_2013_2 && \
+	XCHAL_HW_MIN_VERSION <= XTENSA_HWVERSION_RF_2014_0 && \
+	XCHAL_ICACHE_SIZE != 0    && XCHAL_HAVE_PIF /*covers also AXI/AHB*/ && \
+	XCHAL_HAVE_LOOPS          && XCHAL_LOOP_BUFFER_SIZE != 0 && \
+	XCHAL_CLOCK_GATING_GLOBAL && !defined(_NO_ERRATUM_453) )
+#define XCHAL_ERRATUM_453	1
+#else
+#define XCHAL_ERRATUM_453	0
+#endif
+
+/*
+ *  Erratum 497 present in RE-2012.2 up to RG/RF-2015.2
+ *  Applies to specific set of configuration options.
+ *  Workaround is to add MEMWs after at most 8 cache WB instructions
+ */
+#if ( ((XCHAL_HW_MAX_VERSION >= XTENSA_HWVERSION_RE_2012_0 &&    \
+        XCHAL_HW_MIN_VERSION <= XTENSA_HWVERSION_RF_2015_2) ||   \
+       (XCHAL_HW_MAX_VERSION >= XTENSA_HWVERSION_RG_2015_0 &&    \
+        XCHAL_HW_MIN_VERSION <= XTENSA_HWVERSION_RG_2015_2)     \
+      ) && \
+      XCHAL_DCACHE_IS_WRITEBACK && \
+      XCHAL_HAVE_AXI && \
+      XCHAL_HAVE_PIF_WR_RESP && \
+      XCHAL_HAVE_PIF_REQ_ATTR &&  !defined(_NO_ERRATUM_497) \
+    )
+#define XCHAL_ERRATUM_497	1
+#else
+#define XCHAL_ERRATUM_497	0
+#endif
+
+#endif /*XTENSA_CONFIG_CORE_H*/
+

components/esp32/include/xtensa/config/defs.h

@@ -0,0 +1,38 @@
+/* Definitions for Xtensa instructions, types, and protos. */
+
+/* Customer ID=11657; Build=0x5fe96; Copyright (c) 2003-2004 Tensilica Inc.
+
+   Permission is hereby granted, free of charge, to any person obtaining
+   a copy of this software and associated documentation files (the
+   "Software"), to deal in the Software without restriction, including
+   without limitation the rights to use, copy, modify, merge, publish,
+   distribute, sublicense, and/or sell copies of the Software, and to
+   permit persons to whom the Software is furnished to do so, subject to
+   the following conditions:
+
+   The above copyright notice and this permission notice shall be included
+   in all copies or substantial portions of the Software.
+
+   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
+
+/* NOTE: This file exists only for backward compatibility with T1050
+   and earlier Xtensa releases.  It includes only a subset of the
+   available header files.  */
+
+#ifndef _XTENSA_BASE_HEADER
+#define _XTENSA_BASE_HEADER
+
+#ifdef __XTENSA__
+
+#include <xtensa/tie/xt_core.h>
+#include <xtensa/tie/xt_misc.h>
+#include <xtensa/tie/xt_booleans.h>
+
+#endif /* __XTENSA__ */
+#endif /* !_XTENSA_BASE_HEADER */

components/esp32/include/xtensa/config/specreg.h

@@ -0,0 +1,117 @@
+/*
+ * Xtensa Special Register symbolic names
+ */
+
+/* $Id: //depot/rel/Eaglenest/Xtensa/SWConfig/hal/specreg.h.tpp#1 $ */
+
+/* Customer ID=11657; Build=0x5fe96; Copyright (c) 1998-2002 Tensilica Inc.
+
+   Permission is hereby granted, free of charge, to any person obtaining
+   a copy of this software and associated documentation files (the
+   "Software"), to deal in the Software without restriction, including
+   without limitation the rights to use, copy, modify, merge, publish,
+   distribute, sublicense, and/or sell copies of the Software, and to
+   permit persons to whom the Software is furnished to do so, subject to
+   the following conditions:
+
+   The above copyright notice and this permission notice shall be included
+   in all copies or substantial portions of the Software.
+
+   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
+
+#ifndef XTENSA_SPECREG_H
+#define XTENSA_SPECREG_H
+
+/*  Include these special register bitfield definitions, for historical reasons:  */
+#include <xtensa/corebits.h>
+
+
+/*  Special registers:  */
+#define LBEG		0
+#define LEND		1
+#define LCOUNT		2
+#define SAR		3
+#define BR		4
+#define SCOMPARE1	12
+#define ACCLO		16
+#define ACCHI		17
+#define MR_0		32
+#define MR_1		33
+#define MR_2		34
+#define MR_3		35
+#define WINDOWBASE	72
+#define WINDOWSTART	73
+#define IBREAKENABLE	96
+#define MEMCTL		97
+#define ATOMCTL		99
+#define DDR		104
+#define IBREAKA_0	128
+#define IBREAKA_1	129
+#define DBREAKA_0	144
+#define DBREAKA_1	145
+#define DBREAKC_0	160
+#define DBREAKC_1	161
+#define EPC_1		177
+#define EPC_2		178
+#define EPC_3		179
+#define EPC_4		180
+#define EPC_5		181
+#define EPC_6		182
+#define EPC_7		183
+#define DEPC		192
+#define EPS_2		194
+#define EPS_3		195
+#define EPS_4		196
+#define EPS_5		197
+#define EPS_6		198
+#define EPS_7		199
+#define EXCSAVE_1	209
+#define EXCSAVE_2	210
+#define EXCSAVE_3	211
+#define EXCSAVE_4	212
+#define EXCSAVE_5	213
+#define EXCSAVE_6	214
+#define EXCSAVE_7	215
+#define CPENABLE	224
+#define INTERRUPT	226
+#define INTENABLE	228
+#define PS		230
+#define VECBASE		231
+#define EXCCAUSE	232
+#define DEBUGCAUSE	233
+#define CCOUNT		234
+#define PRID		235
+#define ICOUNT		236
+#define ICOUNTLEVEL	237
+#define EXCVADDR	238
+#define CCOMPARE_0	240
+#define CCOMPARE_1	241
+#define CCOMPARE_2	242
+#define MISC_REG_0	244
+#define MISC_REG_1	245
+#define MISC_REG_2	246
+#define MISC_REG_3	247
+
+/*  Special cases (bases of special register series):  */
+#define MR		32
+#define IBREAKA		128
+#define DBREAKA		144
+#define DBREAKC		160
+#define EPC		176
+#define EPS		192
+#define EXCSAVE		208
+#define CCOMPARE	240
+
+/*  Special names for read-only and write-only interrupt registers:  */
+#define INTREAD		226
+#define INTSET		226
+#define INTCLEAR	227
+
+#endif /* XTENSA_SPECREG_H */
+

components/esp32/include/xtensa/config/system.h

@@ -0,0 +1,274 @@
+/* 
+ * xtensa/config/system.h -- HAL definitions that are dependent on SYSTEM configuration
+ *
+ *  NOTE: The location and contents of this file are highly subject to change.
+ *
+ *  Source for configuration-independent binaries (which link in a
+ *  configuration-specific HAL library) must NEVER include this file.
+ *  The HAL itself has historically included this file in some instances,
+ *  but this is not appropriate either, because the HAL is meant to be
+ *  core-specific but system independent.
+ */
+
+/* Customer ID=11657; Build=0x5fe96; Copyright (c) 2000-2010 Tensilica Inc.
+
+   Permission is hereby granted, free of charge, to any person obtaining
+   a copy of this software and associated documentation files (the
+   "Software"), to deal in the Software without restriction, including
+   without limitation the rights to use, copy, modify, merge, publish,
+   distribute, sublicense, and/or sell copies of the Software, and to
+   permit persons to whom the Software is furnished to do so, subject to
+   the following conditions:
+
+   The above copyright notice and this permission notice shall be included
+   in all copies or substantial portions of the Software.
+
+   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
+
+
+#ifndef XTENSA_CONFIG_SYSTEM_H
+#define XTENSA_CONFIG_SYSTEM_H
+
+/*#include <xtensa/hal.h>*/
+
+
+
+/*----------------------------------------------------------------------
+				CONFIGURED SOFTWARE OPTIONS
+  ----------------------------------------------------------------------*/
+
+#define XSHAL_USE_ABSOLUTE_LITERALS	0	/* (sw-only option, whether software uses absolute literals) */
+#define XSHAL_HAVE_TEXT_SECTION_LITERALS 1 /* Set if there is some memory that allows both code and literals.  */
+
+#define XSHAL_ABI			XTHAL_ABI_WINDOWED	/* (sw-only option, selected ABI) */
+/*  The above maps to one of the following constants:  */
+#define XTHAL_ABI_WINDOWED		0
+#define XTHAL_ABI_CALL0			1
+/*  Alternatives:  */
+/*#define XSHAL_WINDOWED_ABI		1*/	/* set if windowed ABI selected */
+/*#define XSHAL_CALL0_ABI		0*/	/* set if call0 ABI selected */
+
+#define XSHAL_CLIB			XTHAL_CLIB_NEWLIB	/* (sw-only option, selected C library) */
+/*  The above maps to one of the following constants:  */
+#define XTHAL_CLIB_NEWLIB		0
+#define XTHAL_CLIB_UCLIBC		1
+#define XTHAL_CLIB_XCLIB		2
+/*  Alternatives:  */
+/*#define XSHAL_NEWLIB			1*/	/* set if newlib C library selected */
+/*#define XSHAL_UCLIBC			0*/	/* set if uCLibC C library selected */
+/*#define XSHAL_XCLIB			0*/	/* set if Xtensa C library selected */
+
+#define XSHAL_USE_FLOATING_POINT	1
+
+#define XSHAL_FLOATING_POINT_ABI	0
+
+/*  SW workarounds enabled for HW errata:  */
+
+/*----------------------------------------------------------------------
+				DEVICE ADDRESSES
+  ----------------------------------------------------------------------*/
+
+/*
+ *  Strange place to find these, but the configuration GUI
+ *  allows moving these around to account for various core
+ *  configurations.  Specific boards (and their BSP software)
+ *  will have specific meanings for these components.
+ */
+
+/*  I/O Block areas:  */
+#define XSHAL_IOBLOCK_CACHED_VADDR	0x70000000
+#define XSHAL_IOBLOCK_CACHED_PADDR	0x70000000
+#define XSHAL_IOBLOCK_CACHED_SIZE	0x0E000000
+
+#define XSHAL_IOBLOCK_BYPASS_VADDR	0x90000000
+#define XSHAL_IOBLOCK_BYPASS_PADDR	0x90000000
+#define XSHAL_IOBLOCK_BYPASS_SIZE	0x0E000000
+
+/*  System ROM:  */
+#define XSHAL_ROM_VADDR		0x50000000
+#define XSHAL_ROM_PADDR		0x50000000
+#define XSHAL_ROM_SIZE		0x01000000
+/*  Largest available area (free of vectors):  */
+#define XSHAL_ROM_AVAIL_VADDR	0x50000000
+#define XSHAL_ROM_AVAIL_VSIZE	0x01000000
+
+/*  System RAM:  */
+#define XSHAL_RAM_VADDR		0x60000000
+#define XSHAL_RAM_PADDR		0x60000000
+#define XSHAL_RAM_VSIZE		0x20000000
+#define XSHAL_RAM_PSIZE		0x20000000
+#define XSHAL_RAM_SIZE		XSHAL_RAM_PSIZE
+/*  Largest available area (free of vectors):  */
+#define XSHAL_RAM_AVAIL_VADDR	0x60000000
+#define XSHAL_RAM_AVAIL_VSIZE	0x20000000
+
+/*
+ *  Shadow system RAM (same device as system RAM, at different address).
+ *  (Emulation boards need this for the SONIC Ethernet driver
+ *   when data caches are configured for writeback mode.)
+ *  NOTE: on full MMU configs, this points to the BYPASS virtual address
+ *  of system RAM, ie. is the same as XSHAL_RAM_* except that virtual
+ *  addresses are viewed through the BYPASS static map rather than
+ *  the CACHED static map.
+ */
+#define XSHAL_RAM_BYPASS_VADDR		0xA0000000
+#define XSHAL_RAM_BYPASS_PADDR		0xA0000000
+#define XSHAL_RAM_BYPASS_PSIZE		0x20000000
+
+/*  Alternate system RAM (different device than system RAM):  */
+/*#define XSHAL_ALTRAM_[VP]ADDR		...not configured...*/
+/*#define XSHAL_ALTRAM_SIZE		...not configured...*/
+
+/*  Some available location in which to place devices in a simulation (eg. XTMP):  */
+#define XSHAL_SIMIO_CACHED_VADDR	0xC0000000
+#define XSHAL_SIMIO_BYPASS_VADDR	0xC0000000
+#define XSHAL_SIMIO_PADDR		0xC0000000
+#define XSHAL_SIMIO_SIZE		0x20000000
+
+
+/*----------------------------------------------------------------------
+ *  For use by reference testbench exit and diagnostic routines.
+ */
+#define XSHAL_MAGIC_EXIT		0x0
+
+/*----------------------------------------------------------------------
+ *			DEVICE-ADDRESS DEPENDENT...
+ *
+ *  Values written to CACHEATTR special register (or its equivalent)
+ *  to enable and disable caches in various modes.
+ *----------------------------------------------------------------------*/
+
+/*----------------------------------------------------------------------
+			BACKWARD COMPATIBILITY ...
+  ----------------------------------------------------------------------*/
+
+/*
+ *  NOTE:  the following two macros are DEPRECATED.  Use the latter
+ *  board-specific macros instead, which are specially tuned for the
+ *  particular target environments' memory maps.
+ */
+#define XSHAL_CACHEATTR_BYPASS		XSHAL_XT2000_CACHEATTR_BYPASS	/* disable caches in bypass mode */
+#define XSHAL_CACHEATTR_DEFAULT		XSHAL_XT2000_CACHEATTR_DEFAULT	/* default setting to enable caches (no writeback!) */
+
+/*----------------------------------------------------------------------
+				GENERIC
+  ----------------------------------------------------------------------*/
+
+/*  For the following, a 512MB region is used if it contains a system (PIF) RAM,
+ *  system (PIF) ROM, local memory, or XLMI.  */
+
+/*  These set any unused 512MB region to cache-BYPASS attribute:  */
+#define XSHAL_ALLVALID_CACHEATTR_WRITEBACK	0x22221112	/* enable caches in write-back mode */
+#define XSHAL_ALLVALID_CACHEATTR_WRITEALLOC	0x22221112	/* enable caches in write-allocate mode */
+#define XSHAL_ALLVALID_CACHEATTR_WRITETHRU	0x22221112	/* enable caches in write-through mode */
+#define XSHAL_ALLVALID_CACHEATTR_BYPASS		0x22222222	/* disable caches in bypass mode */
+#define XSHAL_ALLVALID_CACHEATTR_DEFAULT	XSHAL_ALLVALID_CACHEATTR_WRITEBACK	/* default setting to enable caches */
+
+/*  These set any unused 512MB region to ILLEGAL attribute:  */
+#define XSHAL_STRICT_CACHEATTR_WRITEBACK	0xFFFF111F	/* enable caches in write-back mode */
+#define XSHAL_STRICT_CACHEATTR_WRITEALLOC	0xFFFF111F	/* enable caches in write-allocate mode */
+#define XSHAL_STRICT_CACHEATTR_WRITETHRU	0xFFFF111F	/* enable caches in write-through mode */
+#define XSHAL_STRICT_CACHEATTR_BYPASS		0xFFFF222F	/* disable caches in bypass mode */
+#define XSHAL_STRICT_CACHEATTR_DEFAULT		XSHAL_STRICT_CACHEATTR_WRITEBACK	/* default setting to enable caches */
+
+/*  These set the first 512MB, if unused, to ILLEGAL attribute to help catch
+ *  NULL-pointer dereference bugs; all other unused 512MB regions are set
+ *  to cache-BYPASS attribute:  */
+#define XSHAL_TRAPNULL_CACHEATTR_WRITEBACK	0x2222111F	/* enable caches in write-back mode */
+#define XSHAL_TRAPNULL_CACHEATTR_WRITEALLOC	0x2222111F	/* enable caches in write-allocate mode */
+#define XSHAL_TRAPNULL_CACHEATTR_WRITETHRU	0x2222111F	/* enable caches in write-through mode */
+#define XSHAL_TRAPNULL_CACHEATTR_BYPASS		0x2222222F	/* disable caches in bypass mode */
+#define XSHAL_TRAPNULL_CACHEATTR_DEFAULT	XSHAL_TRAPNULL_CACHEATTR_WRITEBACK	/* default setting to enable caches */
+
+/*----------------------------------------------------------------------
+			ISS (Instruction Set Simulator) SPECIFIC ...
+  ----------------------------------------------------------------------*/
+
+/*  For now, ISS defaults to the TRAPNULL settings:  */
+#define XSHAL_ISS_CACHEATTR_WRITEBACK	XSHAL_TRAPNULL_CACHEATTR_WRITEBACK
+#define XSHAL_ISS_CACHEATTR_WRITEALLOC	XSHAL_TRAPNULL_CACHEATTR_WRITEALLOC
+#define XSHAL_ISS_CACHEATTR_WRITETHRU	XSHAL_TRAPNULL_CACHEATTR_WRITETHRU
+#define XSHAL_ISS_CACHEATTR_BYPASS	XSHAL_TRAPNULL_CACHEATTR_BYPASS
+#define XSHAL_ISS_CACHEATTR_DEFAULT	XSHAL_TRAPNULL_CACHEATTR_WRITEBACK
+
+#define XSHAL_ISS_PIPE_REGIONS	0
+#define XSHAL_ISS_SDRAM_REGIONS	0
+
+
+/*----------------------------------------------------------------------
+			XT2000 BOARD SPECIFIC ...
+  ----------------------------------------------------------------------*/
+
+/*  For the following, a 512MB region is used if it contains any system RAM,
+ *  system ROM, local memory, XLMI, or other XT2000 board device or memory.
+ *  Regions containing devices are forced to cache-BYPASS mode regardless
+ *  of whether the macro is _WRITEBACK vs. _BYPASS etc.  */
+
+/*  These set any 512MB region unused on the XT2000 to ILLEGAL attribute:  */
+#define XSHAL_XT2000_CACHEATTR_WRITEBACK	0xFF22111F	/* enable caches in write-back mode */
+#define XSHAL_XT2000_CACHEATTR_WRITEALLOC	0xFF22111F	/* enable caches in write-allocate mode */
+#define XSHAL_XT2000_CACHEATTR_WRITETHRU	0xFF22111F	/* enable caches in write-through mode */
+#define XSHAL_XT2000_CACHEATTR_BYPASS		0xFF22222F	/* disable caches in bypass mode */
+#define XSHAL_XT2000_CACHEATTR_DEFAULT		XSHAL_XT2000_CACHEATTR_WRITEBACK	/* default setting to enable caches */
+
+#define XSHAL_XT2000_PIPE_REGIONS	0x00000000	/* BusInt pipeline regions */
+#define XSHAL_XT2000_SDRAM_REGIONS	0x00000440	/* BusInt SDRAM regions */
+
+
+/*----------------------------------------------------------------------
+				VECTOR INFO AND SIZES
+  ----------------------------------------------------------------------*/
+
+#define XSHAL_VECTORS_PACKED		0
+#define XSHAL_STATIC_VECTOR_SELECT	1
+#define XSHAL_RESET_VECTOR_VADDR	0x40000400
+#define XSHAL_RESET_VECTOR_PADDR	0x40000400
+
+/*
+ *  Sizes allocated to vectors by the system (memory map) configuration.
+ *  These sizes are constrained by core configuration (eg. one vector's
+ *  code cannot overflow into another vector) but are dependent on the
+ *  system or board (or LSP) memory map configuration.
+ *
+ *  Whether or not each vector happens to be in a system ROM is also
+ *  a system configuration matter, sometimes useful, included here also:
+ */
+#define XSHAL_RESET_VECTOR_SIZE	0x00000300
+#define XSHAL_RESET_VECTOR_ISROM	0
+#define XSHAL_USER_VECTOR_SIZE	0x00000038
+#define XSHAL_USER_VECTOR_ISROM	0
+#define XSHAL_PROGRAMEXC_VECTOR_SIZE	XSHAL_USER_VECTOR_SIZE	/* for backward compatibility */
+#define XSHAL_USEREXC_VECTOR_SIZE	XSHAL_USER_VECTOR_SIZE	/* for backward compatibility */
+#define XSHAL_KERNEL_VECTOR_SIZE	0x00000038
+#define XSHAL_KERNEL_VECTOR_ISROM	0
+#define XSHAL_STACKEDEXC_VECTOR_SIZE	XSHAL_KERNEL_VECTOR_SIZE	/* for backward compatibility */
+#define XSHAL_KERNELEXC_VECTOR_SIZE	XSHAL_KERNEL_VECTOR_SIZE	/* for backward compatibility */
+#define XSHAL_DOUBLEEXC_VECTOR_SIZE	0x00000040
+#define XSHAL_DOUBLEEXC_VECTOR_ISROM	0
+#define XSHAL_WINDOW_VECTORS_SIZE	0x00000178
+#define XSHAL_WINDOW_VECTORS_ISROM	0
+#define XSHAL_INTLEVEL2_VECTOR_SIZE	0x00000038
+#define XSHAL_INTLEVEL2_VECTOR_ISROM	0
+#define XSHAL_INTLEVEL3_VECTOR_SIZE	0x00000038
+#define XSHAL_INTLEVEL3_VECTOR_ISROM	0
+#define XSHAL_INTLEVEL4_VECTOR_SIZE	0x00000038
+#define XSHAL_INTLEVEL4_VECTOR_ISROM	0
+#define XSHAL_INTLEVEL5_VECTOR_SIZE	0x00000038
+#define XSHAL_INTLEVEL5_VECTOR_ISROM	0
+#define XSHAL_INTLEVEL6_VECTOR_SIZE	0x00000038
+#define XSHAL_INTLEVEL6_VECTOR_ISROM	0
+#define XSHAL_DEBUG_VECTOR_SIZE		XSHAL_INTLEVEL6_VECTOR_SIZE
+#define XSHAL_DEBUG_VECTOR_ISROM	XSHAL_INTLEVEL6_VECTOR_ISROM
+#define XSHAL_NMI_VECTOR_SIZE	0x00000038
+#define XSHAL_NMI_VECTOR_ISROM	0
+#define XSHAL_INTLEVEL7_VECTOR_SIZE	XSHAL_NMI_VECTOR_SIZE
+
+
+#endif /*XTENSA_CONFIG_SYSTEM_H*/
+

components/esp32/include/xtensa/config/tie-asm.h

@@ -0,0 +1,323 @@
+/* 
+ * tie-asm.h -- compile-time HAL assembler definitions dependent on CORE & TIE
+ *
+ *  NOTE:  This header file is not meant to be included directly.
+ */
+
+/* This header file contains assembly-language definitions (assembly
+   macros, etc.) for this specific Xtensa processor's TIE extensions
+   and options.  It is customized to this Xtensa processor configuration.
+
+   Customer ID=11657; Build=0x5fe96; Copyright (c) 1999-2016 Cadence Design Systems Inc.
+
+   Permission is hereby granted, free of charge, to any person obtaining
+   a copy of this software and associated documentation files (the
+   "Software"), to deal in the Software without restriction, including
+   without limitation the rights to use, copy, modify, merge, publish,
+   distribute, sublicense, and/or sell copies of the Software, and to
+   permit persons to whom the Software is furnished to do so, subject to
+   the following conditions:
+
+   The above copyright notice and this permission notice shall be included
+   in all copies or substantial portions of the Software.
+
+   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
+
+#ifndef _XTENSA_CORE_TIE_ASM_H
+#define _XTENSA_CORE_TIE_ASM_H
+
+/*  Selection parameter values for save-area save/restore macros:  */
+/*  Option vs. TIE:  */
+#define XTHAL_SAS_TIE	0x0001	/* custom extension or coprocessor */
+#define XTHAL_SAS_OPT	0x0002	/* optional (and not a coprocessor) */
+#define XTHAL_SAS_ANYOT	0x0003	/* both of the above */
+/*  Whether used automatically by compiler:  */
+#define XTHAL_SAS_NOCC	0x0004	/* not used by compiler w/o special opts/code */
+#define XTHAL_SAS_CC	0x0008	/* used by compiler without special opts/code */
+#define XTHAL_SAS_ANYCC	0x000C	/* both of the above */
+/*  ABI handling across function calls:  */
+#define XTHAL_SAS_CALR	0x0010	/* caller-saved */
+#define XTHAL_SAS_CALE	0x0020	/* callee-saved */
+#define XTHAL_SAS_GLOB	0x0040	/* global across function calls (in thread) */
+#define XTHAL_SAS_ANYABI	0x0070	/* all of the above three */
+/*  Misc  */
+#define XTHAL_SAS_ALL	0xFFFF	/* include all default NCP contents */
+#define XTHAL_SAS3(optie,ccuse,abi)	( ((optie) & XTHAL_SAS_ANYOT)  \
+					| ((ccuse) & XTHAL_SAS_ANYCC)  \
+					| ((abi)   & XTHAL_SAS_ANYABI) )
+
+
+    /*
+      *  Macro to store all non-coprocessor (extra) custom TIE and optional state
+      *  (not including zero-overhead loop registers).
+      *  Required parameters:
+      *      ptr         Save area pointer address register (clobbered)
+      *                  (register must contain a 4 byte aligned address).
+      *      at1..at4    Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
+      *                  registers are clobbered, the remaining are unused).
+      *  Optional parameters:
+      *      continue    If macro invoked as part of a larger store sequence, set to 1
+      *                  if this is not the first in the sequence.  Defaults to 0.
+      *      ofs         Offset from start of larger sequence (from value of first ptr
+      *                  in sequence) at which to store.  Defaults to next available space
+      *                  (or 0 if <continue> is 0).
+      *      select      Select what category(ies) of registers to store, as a bitmask
+      *                  (see XTHAL_SAS_xxx constants).  Defaults to all registers.
+      *      alloc       Select what category(ies) of registers to allocate; if any
+      *                  category is selected here that is not in <select>, space for
+      *                  the corresponding registers is skipped without doing any store.
+      */
+    .macro xchal_ncp_store  ptr at1 at2 at3 at4  continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
+	xchal_sa_start	\continue, \ofs
+	// Optional global registers used by default by the compiler:
+	.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select)
+	xchal_sa_align	\ptr, 0, 1016, 4, 4
+	rur.THREADPTR	\at1		// threadptr option
+	s32i	\at1, \ptr, .Lxchal_ofs_+0
+	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 4
+	.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0
+	xchal_sa_align	\ptr, 0, 1016, 4, 4
+	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 4
+	.endif
+	// Optional caller-saved registers used by default by the compiler:
+	.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select)
+	xchal_sa_align	\ptr, 0, 1012, 4, 4
+	rsr.ACCLO	\at1		// MAC16 option
+	s32i	\at1, \ptr, .Lxchal_ofs_+0
+	rsr.ACCHI	\at1		// MAC16 option
+	s32i	\at1, \ptr, .Lxchal_ofs_+4
+	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 8
+	.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
+	xchal_sa_align	\ptr, 0, 1012, 4, 4
+	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 8
+	.endif
+	// Optional caller-saved registers not used by default by the compiler:
+	.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
+	xchal_sa_align	\ptr, 0, 996, 4, 4
+	rsr.BR	\at1		// boolean option
+	s32i	\at1, \ptr, .Lxchal_ofs_+0
+	rsr.SCOMPARE1	\at1		// conditional store option
+	s32i	\at1, \ptr, .Lxchal_ofs_+4
+	rsr.M0	\at1		// MAC16 option
+	s32i	\at1, \ptr, .Lxchal_ofs_+8
+	rsr.M1	\at1		// MAC16 option
+	s32i	\at1, \ptr, .Lxchal_ofs_+12
+	rsr.M2	\at1		// MAC16 option
+	s32i	\at1, \ptr, .Lxchal_ofs_+16
+	rsr.M3	\at1		// MAC16 option
+	s32i	\at1, \ptr, .Lxchal_ofs_+20
+	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 24
+	.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
+	xchal_sa_align	\ptr, 0, 996, 4, 4
+	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 24
+	.endif
+	// Custom caller-saved registers not used by default by the compiler:
+	.ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
+	xchal_sa_align	\ptr, 0, 1008, 4, 4
+	rur.F64R_LO	\at1		// ureg 234
+	s32i	\at1, \ptr, .Lxchal_ofs_+0
+	rur.F64R_HI	\at1		// ureg 235
+	s32i	\at1, \ptr, .Lxchal_ofs_+4
+	rur.F64S	\at1		// ureg 236
+	s32i	\at1, \ptr, .Lxchal_ofs_+8
+	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 12
+	.elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
+	xchal_sa_align	\ptr, 0, 1008, 4, 4
+	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 12
+	.endif
+    .endm	// xchal_ncp_store
+
+    /*
+      *  Macro to load all non-coprocessor (extra) custom TIE and optional state
+      *  (not including zero-overhead loop registers).
+      *  Required parameters:
+      *      ptr         Save area pointer address register (clobbered)
+      *                  (register must contain a 4 byte aligned address).
+      *      at1..at4    Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
+      *                  registers are clobbered, the remaining are unused).
+      *  Optional parameters:
+      *      continue    If macro invoked as part of a larger load sequence, set to 1
+      *                  if this is not the first in the sequence.  Defaults to 0.
+      *      ofs         Offset from start of larger sequence (from value of first ptr
+      *                  in sequence) at which to load.  Defaults to next available space
+      *                  (or 0 if <continue> is 0).
+      *      select      Select what category(ies) of registers to load, as a bitmask
+      *                  (see XTHAL_SAS_xxx constants).  Defaults to all registers.
+      *      alloc       Select what category(ies) of registers to allocate; if any
+      *                  category is selected here that is not in <select>, space for
+      *                  the corresponding registers is skipped without doing any load.
+      */
+    .macro xchal_ncp_load  ptr at1 at2 at3 at4  continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
+	xchal_sa_start	\continue, \ofs
+	// Optional global registers used by default by the compiler:
+	.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select)
+	xchal_sa_align	\ptr, 0, 1016, 4, 4
+	l32i	\at1, \ptr, .Lxchal_ofs_+0
+	wur.THREADPTR	\at1		// threadptr option
+	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 4
+	.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0
+	xchal_sa_align	\ptr, 0, 1016, 4, 4
+	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 4
+	.endif
+	// Optional caller-saved registers used by default by the compiler:
+	.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select)
+	xchal_sa_align	\ptr, 0, 1012, 4, 4
+	l32i	\at1, \ptr, .Lxchal_ofs_+0
+	wsr.ACCLO	\at1		// MAC16 option
+	l32i	\at1, \ptr, .Lxchal_ofs_+4
+	wsr.ACCHI	\at1		// MAC16 option
+	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 8
+	.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
+	xchal_sa_align	\ptr, 0, 1012, 4, 4
+	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 8
+	.endif
+	// Optional caller-saved registers not used by default by the compiler:
+	.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
+	xchal_sa_align	\ptr, 0, 996, 4, 4
+	l32i	\at1, \ptr, .Lxchal_ofs_+0
+	wsr.BR	\at1		// boolean option
+	l32i	\at1, \ptr, .Lxchal_ofs_+4
+	wsr.SCOMPARE1	\at1		// conditional store option
+	l32i	\at1, \ptr, .Lxchal_ofs_+8
+	wsr.M0	\at1		// MAC16 option
+	l32i	\at1, \ptr, .Lxchal_ofs_+12
+	wsr.M1	\at1		// MAC16 option
+	l32i	\at1, \ptr, .Lxchal_ofs_+16
+	wsr.M2	\at1		// MAC16 option
+	l32i	\at1, \ptr, .Lxchal_ofs_+20
+	wsr.M3	\at1		// MAC16 option
+	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 24
+	.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
+	xchal_sa_align	\ptr, 0, 996, 4, 4
+	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 24
+	.endif
+	// Custom caller-saved registers not used by default by the compiler:
+	.ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
+	xchal_sa_align	\ptr, 0, 1008, 4, 4
+	l32i	\at1, \ptr, .Lxchal_ofs_+0
+	wur.F64R_LO	\at1		// ureg 234
+	l32i	\at1, \ptr, .Lxchal_ofs_+4
+	wur.F64R_HI	\at1		// ureg 235
+	l32i	\at1, \ptr, .Lxchal_ofs_+8
+	wur.F64S	\at1		// ureg 236
+	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 12
+	.elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
+	xchal_sa_align	\ptr, 0, 1008, 4, 4
+	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 12
+	.endif
+    .endm	// xchal_ncp_load
+
+
+#define XCHAL_NCP_NUM_ATMPS	1
+
+    /* 
+     *  Macro to store the state of TIE coprocessor FPU.
+     *  Required parameters:
+     *      ptr         Save area pointer address register (clobbered)
+     *                  (register must contain a 4 byte aligned address).
+     *      at1..at4    Four temporary address registers (first XCHAL_CP0_NUM_ATMPS
+     *                  registers are clobbered, the remaining are unused).
+     *  Optional parameters are the same as for xchal_ncp_store.
+     */
+#define xchal_cp_FPU_store	xchal_cp0_store
+    .macro	xchal_cp0_store  ptr at1 at2 at3 at4  continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
+	xchal_sa_start \continue, \ofs
+	// Custom caller-saved registers not used by default by the compiler:
+	.ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
+	xchal_sa_align	\ptr, 0, 948, 4, 4
+	rur.FCR	\at1		// ureg 232
+	s32i	\at1, \ptr, .Lxchal_ofs_+0
+	rur.FSR	\at1		// ureg 233
+	s32i	\at1, \ptr, .Lxchal_ofs_+4
+	ssi	f0, \ptr, .Lxchal_ofs_+8
+	ssi	f1, \ptr, .Lxchal_ofs_+12
+	ssi	f2, \ptr, .Lxchal_ofs_+16
+	ssi	f3, \ptr, .Lxchal_ofs_+20
+	ssi	f4, \ptr, .Lxchal_ofs_+24
+	ssi	f5, \ptr, .Lxchal_ofs_+28
+	ssi	f6, \ptr, .Lxchal_ofs_+32
+	ssi	f7, \ptr, .Lxchal_ofs_+36
+	ssi	f8, \ptr, .Lxchal_ofs_+40
+	ssi	f9, \ptr, .Lxchal_ofs_+44
+	ssi	f10, \ptr, .Lxchal_ofs_+48
+	ssi	f11, \ptr, .Lxchal_ofs_+52
+	ssi	f12, \ptr, .Lxchal_ofs_+56
+	ssi	f13, \ptr, .Lxchal_ofs_+60
+	ssi	f14, \ptr, .Lxchal_ofs_+64
+	ssi	f15, \ptr, .Lxchal_ofs_+68
+	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 72
+	.elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
+	xchal_sa_align	\ptr, 0, 948, 4, 4
+	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 72
+	.endif
+    .endm	// xchal_cp0_store
+
+    /* 
+     *  Macro to load the state of TIE coprocessor FPU.
+     *  Required parameters:
+     *      ptr         Save area pointer address register (clobbered)
+     *                  (register must contain a 4 byte aligned address).
+     *      at1..at4    Four temporary address registers (first XCHAL_CP0_NUM_ATMPS
+     *                  registers are clobbered, the remaining are unused).
+     *  Optional parameters are the same as for xchal_ncp_load.
+     */
+#define xchal_cp_FPU_load	xchal_cp0_load
+    .macro	xchal_cp0_load  ptr at1 at2 at3 at4  continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
+	xchal_sa_start \continue, \ofs
+	// Custom caller-saved registers not used by default by the compiler:
+	.ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
+	xchal_sa_align	\ptr, 0, 948, 4, 4
+	l32i	\at1, \ptr, .Lxchal_ofs_+0
+	wur.FCR	\at1		// ureg 232
+	l32i	\at1, \ptr, .Lxchal_ofs_+4
+	wur.FSR	\at1		// ureg 233
+	lsi	f0, \ptr, .Lxchal_ofs_+8
+	lsi	f1, \ptr, .Lxchal_ofs_+12
+	lsi	f2, \ptr, .Lxchal_ofs_+16
+	lsi	f3, \ptr, .Lxchal_ofs_+20
+	lsi	f4, \ptr, .Lxchal_ofs_+24
+	lsi	f5, \ptr, .Lxchal_ofs_+28
+	lsi	f6, \ptr, .Lxchal_ofs_+32
+	lsi	f7, \ptr, .Lxchal_ofs_+36
+	lsi	f8, \ptr, .Lxchal_ofs_+40
+	lsi	f9, \ptr, .Lxchal_ofs_+44
+	lsi	f10, \ptr, .Lxchal_ofs_+48
+	lsi	f11, \ptr, .Lxchal_ofs_+52
+	lsi	f12, \ptr, .Lxchal_ofs_+56
+	lsi	f13, \ptr, .Lxchal_ofs_+60
+	lsi	f14, \ptr, .Lxchal_ofs_+64
+	lsi	f15, \ptr, .Lxchal_ofs_+68
+	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 72
+	.elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
+	xchal_sa_align	\ptr, 0, 948, 4, 4
+	.set	.Lxchal_ofs_, .Lxchal_ofs_ + 72
+	.endif
+    .endm	// xchal_cp0_load
+
+#define XCHAL_CP0_NUM_ATMPS	1
+#define XCHAL_SA_NUM_ATMPS	1
+
+	/*  Empty macros for unconfigured coprocessors:  */
+	.macro xchal_cp1_store	p a b c d continue=0 ofs=-1 select=-1 ; .endm
+	.macro xchal_cp1_load	p a b c d continue=0 ofs=-1 select=-1 ; .endm
+	.macro xchal_cp2_store	p a b c d continue=0 ofs=-1 select=-1 ; .endm
+	.macro xchal_cp2_load	p a b c d continue=0 ofs=-1 select=-1 ; .endm
+	.macro xchal_cp3_store	p a b c d continue=0 ofs=-1 select=-1 ; .endm
+	.macro xchal_cp3_load	p a b c d continue=0 ofs=-1 select=-1 ; .endm
+	.macro xchal_cp4_store	p a b c d continue=0 ofs=-1 select=-1 ; .endm
+	.macro xchal_cp4_load	p a b c d continue=0 ofs=-1 select=-1 ; .endm
+	.macro xchal_cp5_store	p a b c d continue=0 ofs=-1 select=-1 ; .endm
+	.macro xchal_cp5_load	p a b c d continue=0 ofs=-1 select=-1 ; .endm
+	.macro xchal_cp6_store	p a b c d continue=0 ofs=-1 select=-1 ; .endm
+	.macro xchal_cp6_load	p a b c d continue=0 ofs=-1 select=-1 ; .endm
+	.macro xchal_cp7_store	p a b c d continue=0 ofs=-1 select=-1 ; .endm
+	.macro xchal_cp7_load	p a b c d continue=0 ofs=-1 select=-1 ; .endm
+
+#endif /*_XTENSA_CORE_TIE_ASM_H*/
+

components/esp32/include/xtensa/config/tie.h

@@ -0,0 +1,182 @@
+/* 
+ * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration
+ *
+ *  NOTE:  This header file is not meant to be included directly.
+ */
+
+/* This header file describes this specific Xtensa processor's TIE extensions
+   that extend basic Xtensa core functionality.  It is customized to this
+   Xtensa processor configuration.
+
+   Customer ID=11657; Build=0x5fe96; Copyright (c) 1999-2016 Cadence Design Systems Inc.
+
+   Permission is hereby granted, free of charge, to any person obtaining
+   a copy of this software and associated documentation files (the
+   "Software"), to deal in the Software without restriction, including
+   without limitation the rights to use, copy, modify, merge, publish,
+   distribute, sublicense, and/or sell copies of the Software, and to
+   permit persons to whom the Software is furnished to do so, subject to
+   the following conditions:
+
+   The above copyright notice and this permission notice shall be included
+   in all copies or substantial portions of the Software.
+
+   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
+
+#ifndef _XTENSA_CORE_TIE_H
+#define _XTENSA_CORE_TIE_H
+
+#define XCHAL_CP_NUM			1	/* number of coprocessors */
+#define XCHAL_CP_MAX			1	/* max CP ID + 1 (0 if none) */
+#define XCHAL_CP_MASK			0x01	/* bitmask of all CPs by ID */
+#define XCHAL_CP_PORT_MASK		0x00	/* bitmask of only port CPs */
+
+/*  Basic parameters of each coprocessor:  */
+#define XCHAL_CP0_NAME			"FPU"
+#define XCHAL_CP0_IDENT			FPU
+#define XCHAL_CP0_SA_SIZE		72	/* size of state save area */
+#define XCHAL_CP0_SA_ALIGN		4	/* min alignment of save area */
+#define XCHAL_CP_ID_FPU             	0	/* coprocessor ID (0..7) */
+
+/*  Filler info for unassigned coprocessors, to simplify arrays etc:  */
+#define XCHAL_CP1_SA_SIZE		0
+#define XCHAL_CP1_SA_ALIGN		1
+#define XCHAL_CP2_SA_SIZE		0
+#define XCHAL_CP2_SA_ALIGN		1
+#define XCHAL_CP3_SA_SIZE		0
+#define XCHAL_CP3_SA_ALIGN		1
+#define XCHAL_CP4_SA_SIZE		0
+#define XCHAL_CP4_SA_ALIGN		1
+#define XCHAL_CP5_SA_SIZE		0
+#define XCHAL_CP5_SA_ALIGN		1
+#define XCHAL_CP6_SA_SIZE		0
+#define XCHAL_CP6_SA_ALIGN		1
+#define XCHAL_CP7_SA_SIZE		0
+#define XCHAL_CP7_SA_ALIGN		1
+
+/*  Save area for non-coprocessor optional and custom (TIE) state:  */
+#define XCHAL_NCP_SA_SIZE		48
+#define XCHAL_NCP_SA_ALIGN		4
+
+/*  Total save area for optional and custom state (NCP + CPn):  */
+#define XCHAL_TOTAL_SA_SIZE		128	/* with 16-byte align padding */
+#define XCHAL_TOTAL_SA_ALIGN		4	/* actual minimum alignment */
+
+/*
+ * Detailed contents of save areas.
+ * NOTE:  caller must define the XCHAL_SA_REG macro (not defined here)
+ * before expanding the XCHAL_xxx_SA_LIST() macros.
+ *
+ * XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize,
+ *		dbnum,base,regnum,bitsz,gapsz,reset,x...)
+ *
+ *	s = passed from XCHAL_*_LIST(s), eg. to select how to expand
+ *	ccused = set if used by compiler without special options or code
+ *	abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global)
+ *	kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg)
+ *	opt = 0 (custom TIE extension or coprocessor), or 1 (optional reg)
+ *	name = lowercase reg name (no quotes)
+ *	galign = group byte alignment (power of 2) (galign >= align)
+ *	align = register byte alignment (power of 2)
+ *	asize = allocated size in bytes (asize*8 == bitsz + gapsz + padsz)
+ *	  (not including any pad bytes required to galign this or next reg)
+ *	dbnum = unique target number f/debug (see <xtensa-libdb-macros.h>)
+ *	base = reg shortname w/o index (or sr=special, ur=TIE user reg)
+ *	regnum = reg index in regfile, or special/TIE-user reg number
+ *	bitsz = number of significant bits (regfile width, or ur/sr mask bits)
+ *	gapsz = intervening bits, if bitsz bits not stored contiguously
+ *	(padsz = pad bits at end [TIE regfile] or at msbits [ur,sr] of asize)
+ *	reset = register reset value (or 0 if undefined at reset)
+ *	x = reserved for future use (0 until then)
+ *
+ *  To filter out certain registers, e.g. to expand only the non-global
+ *  registers used by the compiler, you can do something like this:
+ *
+ *  #define XCHAL_SA_REG(s,ccused,p...)	SELCC##ccused(p)
+ *  #define SELCC0(p...)
+ *  #define SELCC1(abikind,p...)	SELAK##abikind(p)
+ *  #define SELAK0(p...)		REG(p)
+ *  #define SELAK1(p...)		REG(p)
+ *  #define SELAK2(p...)
+ *  #define REG(kind,tie,name,galn,aln,asz,csz,dbnum,base,rnum,bsz,rst,x...) \
+ *		...what you want to expand...
+ */
+
+#define XCHAL_NCP_SA_NUM	12
+#define XCHAL_NCP_SA_LIST(s)	\
+ XCHAL_SA_REG(s,1,2,1,1,      threadptr, 4, 4, 4,0x03E7,  ur,231, 32,0,0,0) \
+ XCHAL_SA_REG(s,1,0,0,1,          acclo, 4, 4, 4,0x0210,  sr,16 , 32,0,0,0) \
+ XCHAL_SA_REG(s,1,0,0,1,          acchi, 4, 4, 4,0x0211,  sr,17 ,  8,0,0,0) \
+ XCHAL_SA_REG(s,0,0,0,1,             br, 4, 4, 4,0x0204,  sr,4  , 16,0,0,0) \
+ XCHAL_SA_REG(s,0,0,0,1,      scompare1, 4, 4, 4,0x020C,  sr,12 , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,0,1,             m0, 4, 4, 4,0x0220,  sr,32 , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,0,1,             m1, 4, 4, 4,0x0221,  sr,33 , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,0,1,             m2, 4, 4, 4,0x0222,  sr,34 , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,0,1,             m3, 4, 4, 4,0x0223,  sr,35 , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,1,0,        f64r_lo, 4, 4, 4,0x03EA,  ur,234, 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,1,0,        f64r_hi, 4, 4, 4,0x03EB,  ur,235, 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,1,0,           f64s, 4, 4, 4,0x03EC,  ur,236, 32,0,0,0)
+
+#define XCHAL_CP0_SA_NUM	18
+#define XCHAL_CP0_SA_LIST(s)	\
+ XCHAL_SA_REG(s,0,0,1,0,            fcr, 4, 4, 4,0x03E8,  ur,232, 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,1,0,            fsr, 4, 4, 4,0x03E9,  ur,233, 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,2,0,             f0, 4, 4, 4,0x0030,   f,0  , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,2,0,             f1, 4, 4, 4,0x0031,   f,1  , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,2,0,             f2, 4, 4, 4,0x0032,   f,2  , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,2,0,             f3, 4, 4, 4,0x0033,   f,3  , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,2,0,             f4, 4, 4, 4,0x0034,   f,4  , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,2,0,             f5, 4, 4, 4,0x0035,   f,5  , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,2,0,             f6, 4, 4, 4,0x0036,   f,6  , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,2,0,             f7, 4, 4, 4,0x0037,   f,7  , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,2,0,             f8, 4, 4, 4,0x0038,   f,8  , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,2,0,             f9, 4, 4, 4,0x0039,   f,9  , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,2,0,            f10, 4, 4, 4,0x003A,   f,10 , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,2,0,            f11, 4, 4, 4,0x003B,   f,11 , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,2,0,            f12, 4, 4, 4,0x003C,   f,12 , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,2,0,            f13, 4, 4, 4,0x003D,   f,13 , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,2,0,            f14, 4, 4, 4,0x003E,   f,14 , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,2,0,            f15, 4, 4, 4,0x003F,   f,15 , 32,0,0,0)
+
+#define XCHAL_CP1_SA_NUM	0
+#define XCHAL_CP1_SA_LIST(s)	/* empty */
+
+#define XCHAL_CP2_SA_NUM	0
+#define XCHAL_CP2_SA_LIST(s)	/* empty */
+
+#define XCHAL_CP3_SA_NUM	0
+#define XCHAL_CP3_SA_LIST(s)	/* empty */
+
+#define XCHAL_CP4_SA_NUM	0
+#define XCHAL_CP4_SA_LIST(s)	/* empty */
+
+#define XCHAL_CP5_SA_NUM	0
+#define XCHAL_CP5_SA_LIST(s)	/* empty */
+
+#define XCHAL_CP6_SA_NUM	0
+#define XCHAL_CP6_SA_LIST(s)	/* empty */
+
+#define XCHAL_CP7_SA_NUM	0
+#define XCHAL_CP7_SA_LIST(s)	/* empty */
+
+/* Byte length of instruction from its first nibble (op0 field), per FLIX.  */
+#define XCHAL_OP0_FORMAT_LENGTHS	3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3
+/* Byte length of instruction from its first byte, per FLIX.  */
+#define XCHAL_BYTE0_FORMAT_LENGTHS	\
+	3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
+	3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
+	3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
+	3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
+	3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
+	3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
+	3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
+	3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3
+
+#endif /*_XTENSA_CORE_TIE_H*/
+

components/esp32/include/xtensa/core-macros.h

@@ -0,0 +1,456 @@
+/*
+ * xtensa/core-macros.h -- C specific definitions
+ *                         that depend on CORE configuration
+ */
+
+/*
+ * Copyright (c) 2012 Tensilica Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef XTENSA_CACHE_H
+#define XTENSA_CACHE_H
+
+#include <xtensa/config/core.h>
+
+/*  Only define things for C code.  */
+#if !defined(_ASMLANGUAGE) && !defined(_NOCLANGUAGE) && !defined(__ASSEMBLER__)
+
+
+
+/***************************   CACHE   ***************************/
+
+/* All the macros are in the lower case now and some of them 
+ * share the name with the existing functions from hal.h.
+ * Including this header file will define XTHAL_USE_CACHE_MACROS 
+ * which directs hal.h not to use the functions.
+ *
+
+/*
+ *  Single-cache-line operations in C-callable inline assembly.
+ *  Essentially macro versions (uppercase) of:
+ *
+ *	xthal_icache_line_invalidate(void *addr);
+ *	xthal_icache_line_lock(void *addr);
+ *	xthal_icache_line_unlock(void *addr);
+ *	xthal_icache_sync(void);
+ *
+ *  NOTE:  unlike the above functions, the following macros do NOT
+ *  execute the xthal_icache_sync() as part of each line operation.
+ *  This sync must be called explicitly by the caller.  This is to
+ *  allow better optimization when operating on more than one line.
+ *
+ *	xthal_dcache_line_invalidate(void *addr);
+ *	xthal_dcache_line_writeback(void *addr);
+ *	xthal_dcache_line_writeback_inv(void *addr);
+ *	xthal_dcache_line_lock(void *addr);
+ *	xthal_dcache_line_unlock(void *addr);
+ *	xthal_dcache_sync(void);
+ *	xthal_dcache_line_prefetch_for_write(void *addr);
+ *	xthal_dcache_line_prefetch_for_read(void *addr);
+ *
+ *  All are made memory-barriers, given that's how they're typically used
+ *  (ops operate on a whole line, so clobbers all memory not just *addr).
+ *
+ *  NOTE:  All the block block cache ops and line prefetches are implemented
+ *  using intrinsics so they are better optimized regarding memory barriers etc.
+ *  
+ * All block downgrade functions exist in two forms: with and without
+ * the 'max' parameter: This parameter allows compiler to optimize
+ * the functions whenever the parameter is smaller than the cache size.
+ *
+ *	xthal_dcache_block_invalidate(void *addr, unsigned size);
+ *	xthal_dcache_block_writeback(void *addr, unsigned size);
+ *	xthal_dcache_block_writeback_inv(void *addr, unsigned size);
+ *	xthal_dcache_block_invalidate_max(void *addr, unsigned size, unsigned max);
+ *	xthal_dcache_block_writeback_max(void *addr, unsigned size, unsigned max);
+ *	xthal_dcache_block_writeback_inv_max(void *addr, unsigned size, unsigned max);
+ *
+ *      xthal_dcache_block_prefetch_for_read(void *addr, unsigned size);
+ *      xthal_dcache_block_prefetch_for_write(void *addr, unsigned size);
+ *      xthal_dcache_block_prefetch_modify(void *addr, unsigned size);
+ *      xthal_dcache_block_prefetch_read_write(void *addr, unsigned size);
+ *      xthal_dcache_block_prefetch_for_read_grp(void *addr, unsigned size);
+ *      xthal_dcache_block_prefetch_for_write_grp(void *addr, unsigned size);
+ *      xthal_dcache_block_prefetch_modify_grp(void *addr, unsigned size);
+ *      xthal_dcache_block_prefetch_read_write_grp(void *addr, unsigned size)
+ *
+ *	xthal_dcache_block_wait();
+ *	xthal_dcache_block_required_wait();
+ *	xthal_dcache_block_abort();
+ *	xthal_dcache_block_prefetch_end();
+ *	xthal_dcache_block_newgrp();
+ */
+
+/***   INSTRUCTION CACHE   ***/
+
+#define XTHAL_USE_CACHE_MACROS
+
+#if XCHAL_ICACHE_SIZE > 0
+# define xthal_icache_line_invalidate(addr)	do { void *__a = (void*)(addr); \
+		__asm__ __volatile__("ihi %0, 0" :: "a"(__a) : "memory"); 	\
+		} while(0)
+#else
+# define xthal_icache_line_invalidate(addr)	do {/*nothing*/} while(0)
+#endif
+
+#if XCHAL_ICACHE_SIZE > 0 && XCHAL_ICACHE_LINE_LOCKABLE
+# define xthal_icache_line_lock(addr)	do { void *__a = (void*)(addr);	 	\
+		__asm__ __volatile__("ipfl %0, 0" :: "a"(__a) : "memory"); 	\
+		} while(0)
+# define xthal_icache_line_unlock(addr)	do { void *__a = (void*)(addr); 	\
+		__asm__ __volatile__("ihu %0, 0" :: "a"(__a) : "memory");	\
+		} while(0)
+#else
+# define xthal_icache_line_lock(addr)		do {/*nothing*/} while(0)
+# define xthal_icache_line_unlock(addr)		do {/*nothing*/} while(0)
+#endif
+
+/*
+ * Even if a config doesn't have caches, an isync is still needed
+ * when instructions in any memory are modified, whether by a loader
+ * or self-modifying code.  Therefore, this macro always produces
+ * an isync, whether or not an icache is present.
+ */
+#define xthal_icache_sync()							\
+		__asm__ __volatile__("isync":::"memory")
+
+
+/***   DATA CACHE   ***/
+
+#if XCHAL_DCACHE_SIZE > 0
+
+# include <xtensa/tie/xt_datacache.h>
+
+# define xthal_dcache_line_invalidate(addr)	do { void *__a = (void*)(addr); \
+		__asm__ __volatile__("dhi %0, 0" :: "a"(__a) : "memory"); 	\
+		} while(0)
+# define xthal_dcache_line_writeback(addr)	do { void *__a = (void*)(addr); \
+		__asm__ __volatile__("dhwb %0, 0" :: "a"(__a) : "memory"); 	\
+		} while(0)
+# define xthal_dcache_line_writeback_inv(addr)	do { void *__a = (void*)(addr); \
+		__asm__ __volatile__("dhwbi %0, 0" :: "a"(__a) : "memory"); 	\
+		} while(0)
+# define xthal_dcache_sync()							\
+		__asm__ __volatile__("" /*"dsync"?*/:::"memory")
+# define xthal_dcache_line_prefetch_for_read(addr) do {				\
+		XT_DPFR((const int*)addr, 0);					\
+		} while(0)
+#else
+# define xthal_dcache_line_invalidate(addr)		do {/*nothing*/} while(0)
+# define xthal_dcache_line_writeback(addr)		do {/*nothing*/} while(0)
+# define xthal_dcache_line_writeback_inv(addr)		do {/*nothing*/} while(0)
+# define xthal_dcache_sync()				__asm__ __volatile__("":::"memory")
+# define xthal_dcache_line_prefetch_for_read(addr)	do {/*nothing*/} while(0)
+#endif
+
+#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_LINE_LOCKABLE
+# define xthal_dcache_line_lock(addr)	do { void *__a = (void*)(addr); 	\
+		__asm__ __volatile__("dpfl %0, 0" :: "a"(__a) : "memory"); 	\
+		} while(0)
+# define xthal_dcache_line_unlock(addr)	do { void *__a = (void*)(addr); 	\
+		__asm__ __volatile__("dhu %0, 0" :: "a"(__a) : "memory"); 	\
+		} while(0)
+#else
+# define xthal_dcache_line_lock(addr)		do {/*nothing*/} while(0)
+# define xthal_dcache_line_unlock(addr)		do {/*nothing*/} while(0)
+#endif
+
+#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_IS_WRITEBACK
+
+# define xthal_dcache_line_prefetch_for_write(addr) do {			\
+		XT_DPFW((const int*)addr, 0);					\
+		} while(0)
+#else
+# define xthal_dcache_line_prefetch_for_write(addr)	do {/*nothing*/} while(0)
+#endif
+
+
+/*****   Block Operations   *****/
+
+#if XCHAL_DCACHE_SIZE > 0 && XCHAL_HAVE_CACHE_BLOCKOPS
+
+/* upgrades */
+
+# define _XTHAL_DCACHE_BLOCK_UPGRADE(addr, size, type)		\
+		{						\
+		type((const int*)addr, size);			\
+		}
+
+/*downgrades */
+
+# define _XTHAL_DCACHE_BLOCK_DOWNGRADE(addr, size, type)	\
+	unsigned _s = size;					\
+	unsigned _a = addr;					\
+	do {							\
+		unsigned __s = (_s > XCHAL_DCACHE_SIZE) ? 	\
+				XCHAL_DCACHE_SIZE : _s; 	\
+		type((const int*)_a, __s);			\
+		_s -= __s; 					\
+		_a += __s;					\
+	} while(_s > 0);
+
+# define _XTHAL_DCACHE_BLOCK_DOWNGRADE_MAX(addr, size, type, max)	\
+	if (max <= XCHAL_DCACHE_SIZE) {					\
+		unsigned _s = size;					\
+		unsigned _a = addr;					\
+		type((const int*)_a, _s);				\
+	}								\
+	else {								\
+		_XTHAL_DCACHE_BLOCK_DOWNGRADE(addr, size, type);	\
+	}
+
+# define xthal_dcache_block_invalidate(addr, size)	do { 		\
+		_XTHAL_DCACHE_BLOCK_DOWNGRADE(addr, size, XT_DHI_B);	\
+		} while(0)
+# define xthal_dcache_block_writeback(addr, size)	do {		\
+		_XTHAL_DCACHE_BLOCK_DOWNGRADE(addr, size, XT_DHWB_B);	\
+		} while(0)
+# define xthal_dcache_block_writeback_inv(addr, size)	do {		\
+		_XTHAL_DCACHE_BLOCK_DOWNGRADE(addr, size, XT_DHWBI_B);	\
+		} while(0)
+
+# define xthal_dcache_block_invalidate_max(addr, size, max)	do {		\
+		_XTHAL_DCACHE_BLOCK_DOWNGRADE_MAX(addr, size, XT_DHI_B, max);	\
+		} while(0)
+# define xthal_dcache_block_writeback_max(addr, size, max)	do { 		\
+		_XTHAL_DCACHE_BLOCK_DOWNGRADE_MAX(addr, size, XT_DHWB_B, max);	\
+		} while(0)
+# define xthal_dcache_block_writeback_inv_max(addr, size, max)	do {		\
+		_XTHAL_DCACHE_BLOCK_DOWNGRADE_MAX(addr, size, XT_DHWBI_B, max);	\
+		} while(0)
+
+/* upgrades that are performed even with write-thru caches  */
+
+# define xthal_dcache_block_prefetch_read_write(addr, size) do {	\
+		_XTHAL_DCACHE_BLOCK_UPGRADE(addr, size, XT_DPFW_B);	\
+		} while(0)
+# define xthal_dcache_block_prefetch_read_write_grp(addr, size) do {	\
+		_XTHAL_DCACHE_BLOCK_UPGRADE(addr, size, XT_DPFW_BF);	\
+		} while(0)
+# define xthal_dcache_block_prefetch_for_read(addr, size) do {		\
+		_XTHAL_DCACHE_BLOCK_UPGRADE(addr, size, XT_DPFR_B);	\
+		} while(0)
+# define xthal_dcache_block_prefetch_for_read_grp(addr, size) do {	\
+		_XTHAL_DCACHE_BLOCK_UPGRADE(addr, size, XT_DPFR_BF);	\
+		} while(0)
+
+/* abort all or end optional block cache operations */
+# define xthal_dcache_block_abort()	do { 		\
+		XT_PFEND_A();				\
+		} while(0)
+# define xthal_dcache_block_end()	do { 		\
+		XT_PFEND_O();				\
+		} while(0)
+
+/* wait for all/required block cache operations to finish */
+# define xthal_dcache_block_wait()	do { 		\
+		XT_PFWAIT_A();				\
+		} while(0)
+# define xthal_dcache_block_required_wait()	do { 	\
+		XT_PFWAIT_R();				\
+		} while(0)
+/* Start a new group */
+# define xthal_dcache_block_newgrp()	do { 		\
+		XT_PFNXT_F();				\
+		} while(0)
+#else
+# define xthal_dcache_block_invalidate(addr, size)		do {/*nothing*/} while(0)
+# define xthal_dcache_block_writeback(addr, size)		do {/*nothing*/} while(0)
+# define xthal_dcache_block_writeback_inv(addr, size)		do {/*nothing*/} while(0)
+# define xthal_dcache_block_invalidate_max(addr, size, max)	do {/*nothing*/} while(0)
+# define xthal_dcache_block_writeback_max(addr, size, max)	do {/*nothing*/} while(0)
+# define xthal_dcache_block_writeback_inv_max(addr, size, max) 	do {/*nothing*/} while(0)
+# define xthal_dcache_block_prefetch_read_write(addr, size)	do {/*nothing*/} while(0)
+# define xthal_dcache_block_prefetch_read_write_grp(addr, size)	do {/*nothing*/} while(0)
+# define xthal_dcache_block_prefetch_for_read(addr, size)	do {/*nothing*/} while(0)
+# define xthal_dcache_block_prefetch_for_read_grp(addr, size)	do {/*nothing*/} while(0)
+# define xthal_dcache_block_end()   				do {/*nothing*/} while(0)
+# define xthal_dcache_block_abort()  				do {/*nothing*/} while(0)
+# define xthal_dcache_block_wait()  				do {/*nothing*/} while(0)
+# define xthal_dcache_block_required_wait()   			do {/*nothing*/} while(0)
+# define xthal_dcache_block_newgrp()				do {/*nothing*/} while(0)
+#endif
+
+#if XCHAL_DCACHE_SIZE > 0 && XCHAL_HAVE_CACHE_BLOCKOPS && XCHAL_DCACHE_IS_WRITEBACK
+
+# define xthal_dcache_block_prefetch_for_write(addr, size) do {	\
+		_XTHAL_DCACHE_BLOCK_UPGRADE(addr, size, XT_DPFW_B);	\
+		} while(0)
+# define xthal_dcache_block_prefetch_modify(addr, size) do {		\
+		_XTHAL_DCACHE_BLOCK_UPGRADE(addr, size, XT_DPFM_B);	\
+		} while(0)
+# define xthal_dcache_block_prefetch_for_write_grp(addr, size) do {	\
+		_XTHAL_DCACHE_BLOCK_UPGRADE(addr, size, XT_DPFW_BF);	\
+		} while(0)
+# define xthal_dcache_block_prefetch_modify_grp(addr, size) do {	\
+		_XTHAL_DCACHE_BLOCK_UPGRADE(addr, size, XT_DPFM_BF);	\
+		} while(0)
+#else
+# define xthal_dcache_block_prefetch_for_write(addr, size)	do {/*nothing*/} while(0)
+# define xthal_dcache_block_prefetch_modify(addr, size) 	do {/*nothing*/} while(0)
+# define xthal_dcache_block_prefetch_for_write_grp(addr, size)	do {/*nothing*/} while(0)
+# define xthal_dcache_block_prefetch_modify_grp(addr, size)  	do {/*nothing*/} while(0)
+#endif
+
+/***************************   INTERRUPTS   ***************************/
+
+/*
+ *  Macro versions of:
+ *	unsigned  xthal_get_intenable( void );
+ *	void      xthal_set_intenable( unsigned );
+ *	unsigned  xthal_get_interrupt( void );
+ *	void      xthal_set_intset( unsigned );
+ *	void      xthal_set_intclear( unsigned );
+ *	unsigned  xthal_get_ccount(void);
+ *	void      xthal_set_ccompare(int, unsigned);
+ *	unsigned  xthal_get_ccompare(int);
+ *
+ *  NOTE: for {set,get}_ccompare, the first argument MUST be a decimal constant.
+ */
+
+#if XCHAL_HAVE_INTERRUPTS
+# define XTHAL_GET_INTENABLE()	({ int __intenable; \
+				__asm__("rsr.intenable %0" : "=a"(__intenable)); \
+				__intenable; })
+# define XTHAL_SET_INTENABLE(v)	do { int __intenable = (int)(v); \
+			__asm__ __volatile__("wsr.intenable %0" :: "a"(__intenable):"memory"); \
+				} while(0)
+# define XTHAL_GET_INTERRUPT()	({ int __interrupt; \
+				__asm__("rsr.interrupt %0" : "=a"(__interrupt)); \
+				__interrupt; })
+# define XTHAL_SET_INTSET(v)	do { int __interrupt = (int)(v); \
+			__asm__ __volatile__("wsr.intset %0" :: "a"(__interrupt):"memory"); \
+				} while(0)
+# define XTHAL_SET_INTCLEAR(v)	do { int __interrupt = (int)(v); \
+			__asm__ __volatile__("wsr.intclear %0" :: "a"(__interrupt):"memory"); \
+				} while(0)
+# define XTHAL_GET_CCOUNT()	({ int __ccount; \
+				__asm__("rsr.ccount %0" : "=a"(__ccount)); \
+				__ccount; })
+# define XTHAL_SET_CCOUNT(v)	do { int __ccount = (int)(v); \
+			__asm__ __volatile__("wsr.ccount %0" :: "a"(__ccount):"memory"); \
+				} while(0)
+# define _XTHAL_GET_CCOMPARE(n)	({ int __ccompare; \
+				__asm__("rsr.ccompare" #n " %0" : "=a"(__ccompare)); \
+				__ccompare; })
+# define XTHAL_GET_CCOMPARE(n)	_XTHAL_GET_CCOMPARE(n)
+# define _XTHAL_SET_CCOMPARE(n,v) do { int __ccompare = (int)(v); \
+			__asm__ __volatile__("wsr.ccompare" #n " %0 ; esync" :: "a"(__ccompare):"memory"); \
+				} while(0)
+# define XTHAL_SET_CCOMPARE(n,v) _XTHAL_SET_CCOMPARE(n,v)
+#else
+# define XTHAL_GET_INTENABLE()		0
+# define XTHAL_SET_INTENABLE(v)		do {/*nothing*/} while(0)
+# define XTHAL_GET_INTERRUPT()		0
+# define XTHAL_SET_INTSET(v)		do {/*nothing*/} while(0)
+# define XTHAL_SET_INTCLEAR(v)		do {/*nothing*/} while(0)
+# define XTHAL_GET_CCOUNT()		0
+# define XTHAL_SET_CCOUNT(v)		do {/*nothing*/} while(0)
+# define XTHAL_GET_CCOMPARE(n)		0
+# define XTHAL_SET_CCOMPARE(n,v)	do {/*nothing*/} while(0)
+#endif
+
+
+/***************************   MISC   ***************************/
+
+/*
+ *  Macro or inline versions of:
+ *	void	  xthal_clear_regcached_code( void );
+ *	unsigned  xthal_get_prid( void );
+ *	unsigned  xthal_compare_and_set( int *addr, int testval, int setval );
+ */
+
+#if XCHAL_HAVE_LOOPS
+# define XTHAL_CLEAR_REGCACHED_CODE()		\
+		__asm__ __volatile__("wsr.lcount %0" :: "a"(0) : "memory")
+#else
+# define XTHAL_CLEAR_REGCACHED_CODE()		do {/*nothing*/} while(0)
+#endif
+
+#if XCHAL_HAVE_PRID
+# define XTHAL_GET_PRID()	({ int __prid; \
+				__asm__("rsr.prid %0" : "=a"(__prid)); \
+				__prid; })
+#else
+# define XTHAL_GET_PRID()	0
+#endif
+
+
+static inline unsigned  XTHAL_COMPARE_AND_SET( int *addr, int testval, int setval )
+{
+    int result;
+
+#if XCHAL_HAVE_S32C1I && XCHAL_HW_MIN_VERSION_MAJOR >= 2200
+    __asm__ __volatile__ (
+	"   wsr.scompare1 %2 \n"
+	"   s32c1i %0, %3, 0 \n"
+	    : "=a"(result) : "0" (setval), "a" (testval), "a" (addr)
+	    : "memory");
+#elif XCHAL_HAVE_INTERRUPTS
+    int tmp;
+    __asm__ __volatile__ (
+        "   rsil   %4, 15 \n"		// %4 == saved ps
+        "   l32i   %0, %3, 0 \n"	// %0 == value to test, return val
+        "   bne    %2, %0, 9f \n"	// test
+        "   s32i   %1, %3, 0 \n"	// write the new value
+	"9: wsr.ps %4 ; rsync \n"	// restore the PS
+	: "=a"(result) 
+	: "0" (setval), "a" (testval), "a" (addr), "a" (tmp)
+	: "memory");
+#else
+    __asm__ __volatile__ (
+        "   l32i  %0, %3, 0 \n"		// %0 == value to test, return val
+        "   bne   %2, %0, 9f \n"	// test
+        "   s32i  %1, %3, 0 \n"		// write the new value
+	"9: \n"
+	    : "=a"(result) : "0" (setval), "a" (testval), "a" (addr)
+	    : "memory");
+#endif
+    return result;
+}
+
+#if XCHAL_HAVE_EXTERN_REGS
+
+static inline unsigned XTHAL_RER (unsigned int reg)
+{
+  unsigned result;
+
+  __asm__ __volatile__ (
+	"   rer     %0, %1"
+	: "=a" (result) : "a" (reg) : "memory");
+
+  return result;
+}
+
+static inline void XTHAL_WER (unsigned reg, unsigned value)
+{
+  __asm__ __volatile__ (
+	"   wer     %0, %1"
+	: : "a" (value), "a" (reg) : "memory");
+}
+
+#endif /* XCHAL_HAVE_EXTERN_REGS */
+
+#endif /* C code */
+
+#endif /*XTENSA_CACHE_H*/
+

components/esp32/include/xtensa/coreasm.h

@@ -0,0 +1,939 @@
+/*
+ * xtensa/coreasm.h -- assembler-specific definitions that depend on CORE configuration
+ *
+ *  Source for configuration-independent binaries (which link in a
+ *  configuration-specific HAL library) must NEVER include this file.
+ *  It is perfectly normal, however, for the HAL itself to include this file.
+ *
+ *  This file must NOT include xtensa/config/system.h.  Any assembler
+ *  header file that depends on system information should likely go
+ *  in a new systemasm.h (or sysasm.h) header file.
+ *
+ *  NOTE: macro beqi32 is NOT configuration-dependent, and is placed
+ *        here until we have a proper configuration-independent header file.
+ */
+
+/* $Id: //depot/rel/Eaglenest/Xtensa/OS/include/xtensa/coreasm.h#3 $ */
+
+/*
+ * Copyright (c) 2000-2014 Tensilica Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef XTENSA_COREASM_H
+#define XTENSA_COREASM_H
+
+/*
+ *  Tell header files this is assembly source, so they can avoid non-assembler
+ *  definitions (eg. C types etc):
+ */
+#ifndef _ASMLANGUAGE	/* conditionalize to avoid cpp warnings (3rd parties might use same macro) */
+#define _ASMLANGUAGE
+#endif
+
+#include <xtensa/config/core.h>
+#include <xtensa/config/specreg.h>
+#include <xtensa/config/system.h>
+
+/*
+ *  Assembly-language specific definitions (assembly macros, etc.).
+ */
+
+/*----------------------------------------------------------------------
+ *  find_ms_setbit
+ *
+ *  This macro finds the most significant bit that is set in <as>
+ *  and return its index + <base> in <ad>, or <base> - 1 if <as> is zero.
+ *  The index counts starting at zero for the lsbit, so the return
+ *  value ranges from <base>-1 (no bit set) to <base>+31 (msbit set).
+ *
+ *  Parameters:
+ *	<ad>	destination address register (any register)
+ *	<as>	source address register
+ *	<at>	temporary address register (must be different than <as>)
+ *	<base>	constant value added to result (usually 0 or 1)
+ *  On entry:
+ *	<ad> = undefined if different than <as>
+ *	<as> = value whose most significant set bit is to be found
+ *	<at> = undefined
+ *	no other registers are used by this macro.
+ *  On exit:
+ *	<ad> = <base> + index of msbit set in original <as>,
+ *	     = <base> - 1 if original <as> was zero.
+ *	<as> clobbered (if not <ad>)
+ *	<at> clobbered (if not <ad>)
+ *  Example:
+ *	find_ms_setbit a0, a4, a0, 0		-- return in a0 index of msbit set in a4
+ */
+
+	.macro	find_ms_setbit ad, as, at, base
+#if XCHAL_HAVE_NSA
+	movi	\at, 31+\base
+	nsau	\as, \as	// get index of \as, numbered from msbit (32 if absent)
+	sub	\ad, \at, \as	// get numbering from lsbit (0..31, -1 if absent)
+#else /* XCHAL_HAVE_NSA */
+	movi	\at, \base	// start with result of 0 (point to lsbit of 32)
+
+	beqz	\as, 2f		// special case for zero argument: return -1
+	bltui	\as, 0x10000, 1f	// is it one of the 16 lsbits? (if so, check lower 16 bits)
+	addi	\at, \at, 16	// no, increment result to upper 16 bits (of 32)
+	//srli	\as, \as, 16	// check upper half (shift right 16 bits)
+	extui	\as, \as, 16, 16	// check upper half (shift right 16 bits)
+1:	bltui	\as, 0x100, 1f	// is it one of the 8 lsbits? (if so, check lower 8 bits)
+	addi	\at, \at, 8	// no, increment result to upper 8 bits (of 16)
+	srli	\as, \as, 8	// shift right to check upper 8 bits
+1:	bltui	\as, 0x10, 1f	// is it one of the 4 lsbits? (if so, check lower 4 bits)
+	addi	\at, \at, 4	// no, increment result to upper 4 bits (of 8)
+	srli	\as, \as, 4	// shift right 4 bits to check upper half
+1:	bltui	\as, 0x4, 1f	// is it one of the 2 lsbits? (if so, check lower 2 bits)
+	addi	\at, \at, 2	// no, increment result to upper 2 bits (of 4)
+	srli	\as, \as, 2	// shift right 2 bits to check upper half
+1:	bltui	\as, 0x2, 1f	// is it the lsbit?
+	addi	\at, \at, 2	// no, increment result to upper bit (of 2)
+2:	addi	\at, \at, -1	// (from just above: add 1;  from beqz: return -1)
+	//srli	\as, \as, 1
+1:				// done! \at contains index of msbit set (or -1 if none set)
+	.if	0x\ad - 0x\at	// destination different than \at ? (works because regs are a0-a15)
+	mov	\ad, \at	// then move result to \ad
+	.endif
+#endif /* XCHAL_HAVE_NSA */
+	.endm	// find_ms_setbit
+
+/*----------------------------------------------------------------------
+ *  find_ls_setbit
+ *
+ *  This macro finds the least significant bit that is set in <as>,
+ *  and return its index in <ad>.
+ *  Usage is the same as for the find_ms_setbit macro.
+ *  Example:
+ *	find_ls_setbit a0, a4, a0, 0	-- return in a0 index of lsbit set in a4
+ */
+
+	.macro	find_ls_setbit ad, as, at, base
+	neg	\at, \as	// keep only the least-significant bit that is set...
+	and	\as, \at, \as	// ... in \as
+	find_ms_setbit	\ad, \as, \at, \base
+	.endm	// find_ls_setbit
+
+/*----------------------------------------------------------------------
+ *  find_ls_one
+ *
+ *  Same as find_ls_setbit with base zero.
+ *  Source (as) and destination (ad) registers must be different.
+ *  Provided for backward compatibility.
+ */
+
+	.macro	find_ls_one ad, as
+	find_ls_setbit	\ad, \as, \ad, 0
+	.endm	// find_ls_one
+
+/*----------------------------------------------------------------------
+ *  floop, floopnez, floopgtz, floopend
+ *
+ *  These macros are used for fast inner loops that
+ *  work whether or not the Loops options is configured.
+ *  If the Loops option is configured, they simply use
+ *  the zero-overhead LOOP instructions; otherwise
+ *  they use explicit decrement and branch instructions.
+ *
+ *  They are used in pairs, with floop, floopnez or floopgtz
+ *  at the beginning of the loop, and floopend at the end.
+ *
+ *  Each pair of loop macro calls must be given the loop count
+ *  address register and a unique label for that loop.
+ *
+ *  Example:
+ *
+ *	movi	 a3, 16     // loop 16 times
+ *	floop    a3, myloop1
+ *	:
+ *	bnez     a7, end1	// exit loop if a7 != 0
+ *	:
+ *	floopend a3, myloop1
+ *  end1:
+ *
+ *  Like the LOOP instructions, these macros cannot be
+ *  nested, must include at least one instruction,
+ *  cannot call functions inside the loop, etc.
+ *  The loop can be exited by jumping to the instruction
+ *  following floopend (or elsewhere outside the loop),
+ *  or continued by jumping to a NOP instruction placed
+ *  immediately before floopend.
+ *
+ *  Unlike LOOP instructions, the register passed to floop*
+ *  cannot be used inside the loop, because it is used as
+ *  the loop counter if the Loops option is not configured.
+ *  And its value is undefined after exiting the loop.
+ *  And because the loop counter register is active inside
+ *  the loop, you can't easily use this construct to loop
+ *  across a register file using ROTW as you might with LOOP
+ *  instructions, unless you copy the loop register along.
+ */
+
+	/*  Named label version of the macros:  */
+
+	.macro	floop		ar, endlabel
+	floop_		\ar, .Lfloopstart_\endlabel, .Lfloopend_\endlabel
+	.endm
+
+	.macro	floopnez	ar, endlabel
+	floopnez_	\ar, .Lfloopstart_\endlabel, .Lfloopend_\endlabel
+	.endm
+
+	.macro	floopgtz	ar, endlabel
+	floopgtz_	\ar, .Lfloopstart_\endlabel, .Lfloopend_\endlabel
+	.endm
+
+	.macro	floopend	ar, endlabel
+	floopend_	\ar, .Lfloopstart_\endlabel, .Lfloopend_\endlabel
+	.endm
+
+	/*  Numbered local label version of the macros:  */
+#if 0 /*UNTESTED*/
+	.macro	floop89		ar
+	floop_		\ar, 8, 9f
+	.endm
+
+	.macro	floopnez89	ar
+	floopnez_	\ar, 8, 9f
+	.endm
+
+	.macro	floopgtz89	ar
+	floopgtz_	\ar, 8, 9f
+	.endm
+
+	.macro	floopend89	ar
+	floopend_	\ar, 8b, 9
+	.endm
+#endif /*0*/
+
+	/*  Underlying version of the macros:  */
+
+	.macro	floop_	ar, startlabel, endlabelref
+	.ifdef	_infloop_
+	.if	_infloop_
+	.err	// Error: floop cannot be nested
+	.endif
+	.endif
+	.set	_infloop_, 1
+#if XCHAL_HAVE_LOOPS
+	loop	\ar, \endlabelref
+#else /* XCHAL_HAVE_LOOPS */
+\startlabel:
+	addi	\ar, \ar, -1
+#endif /* XCHAL_HAVE_LOOPS */
+	.endm	// floop_
+
+	.macro	floopnez_	ar, startlabel, endlabelref
+	.ifdef	_infloop_
+	.if	_infloop_
+	.err	// Error: floopnez cannot be nested
+	.endif
+	.endif
+	.set	_infloop_, 1
+#if XCHAL_HAVE_LOOPS
+	loopnez	\ar, \endlabelref
+#else /* XCHAL_HAVE_LOOPS */
+	beqz	\ar, \endlabelref
+\startlabel:
+	addi	\ar, \ar, -1
+#endif /* XCHAL_HAVE_LOOPS */
+	.endm	// floopnez_
+
+	.macro	floopgtz_	ar, startlabel, endlabelref
+	.ifdef	_infloop_
+	.if	_infloop_
+	.err	// Error: floopgtz cannot be nested
+	.endif
+	.endif
+	.set	_infloop_, 1
+#if XCHAL_HAVE_LOOPS
+	loopgtz	\ar, \endlabelref
+#else /* XCHAL_HAVE_LOOPS */
+	bltz	\ar, \endlabelref
+	beqz	\ar, \endlabelref
+\startlabel:
+	addi	\ar, \ar, -1
+#endif /* XCHAL_HAVE_LOOPS */
+	.endm	// floopgtz_
+
+
+	.macro	floopend_	ar, startlabelref, endlabel
+	.ifndef	_infloop_
+	.err	// Error: floopend without matching floopXXX
+	.endif
+	.ifeq	_infloop_
+	.err	// Error: floopend without matching floopXXX
+	.endif
+	.set	_infloop_, 0
+#if ! XCHAL_HAVE_LOOPS
+	bnez	\ar, \startlabelref
+#endif /* XCHAL_HAVE_LOOPS */
+\endlabel:
+	.endm	// floopend_
+
+/*----------------------------------------------------------------------
+ *  crsil  --  conditional RSIL (read/set interrupt level)
+ *
+ *  Executes the RSIL instruction if it exists, else just reads PS.
+ *  The RSIL instruction does not exist in the new exception architecture
+ *  if the interrupt option is not selected.
+ */
+
+	.macro	crsil	ar, newlevel
+#if XCHAL_HAVE_OLD_EXC_ARCH || XCHAL_HAVE_INTERRUPTS
+	rsil	\ar, \newlevel
+#else
+	rsr	\ar, PS
+#endif
+	.endm	// crsil
+
+/*----------------------------------------------------------------------
+ *  safe_movi_a0  --  move constant into a0 when L32R is not safe
+ *
+ *  This macro is typically used by interrupt/exception handlers.
+ *  Loads a 32-bit constant in a0, without using any other register,
+ *  and without corrupting the LITBASE register, even when the
+ *  value of the LITBASE register is unknown (eg. when application
+ *  code and interrupt/exception handling code are built independently,
+ *  and thus with independent values of the LITBASE register;
+ *  debug monitors are one example of this).
+ *
+ *  Worst-case size of resulting code:  17 bytes.
+ */
+
+	.macro	safe_movi_a0	constant
+#if XCHAL_HAVE_ABSOLUTE_LITERALS
+	/*  Contort a PC-relative literal load even though we may be in litbase-relative mode: */
+	j	1f
+	.begin	no-transform			// ensure what follows is assembled exactly as-is
+	.align	4				// ensure constant and call0 target ...
+	.byte	0				// ... are 4-byte aligned (call0 instruction is 3 bytes long)
+1:	call0	2f				// read PC (that follows call0) in a0
+	.long	\constant			// 32-bit constant to load into a0
+2:
+	.end	no-transform
+	l32i	a0, a0, 0			// load constant
+#else
+	movi	a0, \constant			// no LITBASE, can assume PC-relative L32R
+#endif
+	.endm
+
+
+
+
+/*----------------------------------------------------------------------
+ *  window_spill{4,8,12}
+ *
+ *  These macros spill callers' register windows to the stack.
+ *  They work for both privileged and non-privileged tasks.
+ *  Must be called from a windowed ABI context, eg. within
+ *  a windowed ABI function (ie. valid stack frame, window
+ *  exceptions enabled, not in exception mode, etc).
+ *
+ *  This macro requires a single invocation of the window_spill_common
+ *  macro in the same assembly unit and section.
+ *
+ *  Note that using window_spill{4,8,12} macros is more efficient
+ *  than calling a function implemented using window_spill_function,
+ *  because the latter needs extra code to figure out the size of
+ *  the call to the spilling function.
+ *
+ *  Example usage:
+ *	
+ *		.text
+ *		.align	4
+ *		.global	some_function
+ *		.type	some_function,@function
+ *	some_function:
+ *		entry	a1, 16
+ *		:
+ *		:
+ *
+ *		window_spill4	// Spill windows of some_function's callers; preserves a0..a3 only;
+ *				// to use window_spill{8,12} in this example function we'd have
+ *				// to increase space allocated by the entry instruction, because
+ *				// 16 bytes only allows call4; 32 or 48 bytes (+locals) are needed
+ *				// for call8/window_spill8 or call12/window_spill12 respectively.
+ *
+ *		:
+ *
+ *		retw
+ *
+ *		window_spill_common	// instantiates code used by window_spill4
+ *
+ *
+ *  On entry:
+ *	none (if window_spill4)
+ *	stack frame has enough space allocated for call8 (if window_spill8)
+ *	stack frame has enough space allocated for call12 (if window_spill12)
+ *  On exit:
+ *	 a4..a15 clobbered (if window_spill4)
+ *	 a8..a15 clobbered (if window_spill8)
+ *	a12..a15 clobbered (if window_spill12)
+ *	no caller windows are in live registers
+ */
+
+	.macro	window_spill4
+#if XCHAL_HAVE_WINDOWED
+# if XCHAL_NUM_AREGS == 16
+	movi	a15, 0			// for 16-register files, no need to call to reach the end
+# elif XCHAL_NUM_AREGS == 32
+	call4	.L__wdwspill_assist28	// call deep enough to clear out any live callers
+# elif XCHAL_NUM_AREGS == 64
+	call4	.L__wdwspill_assist60	// call deep enough to clear out any live callers
+# endif
+#endif
+	.endm	// window_spill4
+
+	.macro	window_spill8
+#if XCHAL_HAVE_WINDOWED
+# if XCHAL_NUM_AREGS == 16
+	movi	a15, 0			// for 16-register files, no need to call to reach the end
+# elif XCHAL_NUM_AREGS == 32
+	call8	.L__wdwspill_assist24	// call deep enough to clear out any live callers
+# elif XCHAL_NUM_AREGS == 64
+	call8	.L__wdwspill_assist56	// call deep enough to clear out any live callers
+# endif
+#endif
+	.endm	// window_spill8
+
+	.macro	window_spill12
+#if XCHAL_HAVE_WINDOWED
+# if XCHAL_NUM_AREGS == 16
+	movi	a15, 0			// for 16-register files, no need to call to reach the end
+# elif XCHAL_NUM_AREGS == 32
+	call12	.L__wdwspill_assist20	// call deep enough to clear out any live callers
+# elif XCHAL_NUM_AREGS == 64
+	call12	.L__wdwspill_assist52	// call deep enough to clear out any live callers
+# endif
+#endif
+	.endm	// window_spill12
+
+
+/*----------------------------------------------------------------------
+ *  window_spill_function
+ *
+ *  This macro outputs a function that will spill its caller's callers'
+ *  register windows to the stack.  Eg. it could be used to implement
+ *  a version of xthal_window_spill() that works in non-privileged tasks.
+ *  This works for both privileged and non-privileged tasks.
+ *
+ *  Typical usage:
+ *
+ *		.text
+ *		.align	4
+ *		.global	my_spill_function
+ *		.type	my_spill_function,@function
+ *	my_spill_function:
+ *		window_spill_function
+ *
+ *  On entry to resulting function:
+ *	none
+ *  On exit from resulting function:
+ *	none (no caller windows are in live registers)
+ */
+
+	.macro	window_spill_function
+#if XCHAL_HAVE_WINDOWED
+#  if XCHAL_NUM_AREGS == 32
+	entry	sp, 48
+	bbci.l	a0, 31, 1f		// branch if called with call4
+	bbsi.l	a0, 30, 2f		// branch if called with call12
+	call8	.L__wdwspill_assist16	// called with call8, only need another 8
+	retw
+1:	call12	.L__wdwspill_assist16	// called with call4, only need another 12
+	retw
+2:	call4	.L__wdwspill_assist16	// called with call12, only need another 4
+	retw
+#  elif XCHAL_NUM_AREGS == 64
+	entry	sp, 48
+	bbci.l	a0, 31, 1f		// branch if called with call4
+	bbsi.l	a0, 30, 2f		// branch if called with call12
+	call4	.L__wdwspill_assist52	// called with call8, only need a call4
+	retw
+1:	call8	.L__wdwspill_assist52	// called with call4, only need a call8
+	retw
+2:	call12	.L__wdwspill_assist40	// called with call12, can skip a call12
+	retw
+#  elif XCHAL_NUM_AREGS == 16
+	entry	sp, 16
+	bbci.l	a0, 31, 1f	// branch if called with call4
+	bbsi.l	a0, 30, 2f	// branch if called with call12
+	movi	a7, 0		// called with call8
+	retw
+1:	movi	a11, 0		// called with call4
+2:	retw			// if called with call12, everything already spilled
+
+//	movi	a15, 0		// trick to spill all but the direct caller
+//	j	1f
+//	//  The entry instruction is magical in the assembler (gets auto-aligned)
+//	//  so we have to jump to it to avoid falling through the padding.
+//	//  We need entry/retw to know where to return.
+//1:	entry	sp, 16
+//	retw
+#  else
+#   error "unrecognized address register file size"
+#  endif
+
+#endif /* XCHAL_HAVE_WINDOWED */
+	window_spill_common
+	.endm	// window_spill_function
+
+/*----------------------------------------------------------------------
+ *  window_spill_common
+ *
+ *  Common code used by any number of invocations of the window_spill##
+ *  and window_spill_function macros.
+ *
+ *  Must be instantiated exactly once within a given assembly unit,
+ *  within call/j range of and same section as window_spill##
+ *  macro invocations for that assembly unit.
+ *  (Is automatically instantiated by the window_spill_function macro.)
+ */
+
+	.macro	window_spill_common
+#if XCHAL_HAVE_WINDOWED && (XCHAL_NUM_AREGS == 32 || XCHAL_NUM_AREGS == 64)
+	.ifndef	.L__wdwspill_defined
+#  if XCHAL_NUM_AREGS >= 64
+.L__wdwspill_assist60:
+	entry	sp, 32
+	call8	.L__wdwspill_assist52
+	retw
+.L__wdwspill_assist56:
+	entry	sp, 16
+	call4	.L__wdwspill_assist52
+	retw
+.L__wdwspill_assist52:
+	entry	sp, 48
+	call12	.L__wdwspill_assist40
+	retw
+.L__wdwspill_assist40:
+	entry	sp, 48
+	call12	.L__wdwspill_assist28
+	retw
+#  endif
+.L__wdwspill_assist28:
+	entry	sp, 48
+	call12	.L__wdwspill_assist16
+	retw
+.L__wdwspill_assist24:
+	entry	sp, 32
+	call8	.L__wdwspill_assist16
+	retw
+.L__wdwspill_assist20:
+	entry	sp, 16
+	call4	.L__wdwspill_assist16
+	retw
+.L__wdwspill_assist16:
+	entry	sp, 16
+	movi	a15, 0
+	retw
+	.set	.L__wdwspill_defined, 1
+	.endif
+#endif /* XCHAL_HAVE_WINDOWED with 32 or 64 aregs */
+	.endm	// window_spill_common
+
+/*----------------------------------------------------------------------
+ *  beqi32
+ *
+ *  macro implements version of beqi for arbitrary 32-bit immediate value
+ *
+ *     beqi32 ax, ay, imm32, label
+ * 
+ *  Compares value in register ax with imm32 value and jumps to label if
+ *  equal. Clobbers register ay if needed
+ *
+ */
+   .macro beqi32	ax, ay, imm, label
+    .ifeq ((\imm-1) & ~7)	// 1..8 ?
+		beqi	\ax, \imm, \label
+    .else
+      .ifeq (\imm+1)		// -1 ?
+		beqi	\ax, \imm, \label
+      .else
+        .ifeq (\imm)		// 0 ?
+		beqz	\ax, \label
+        .else
+		//  We could also handle immediates 10,12,16,32,64,128,256 
+		//  but it would be a long macro...
+		movi	\ay, \imm
+		beq	\ax, \ay, \label
+        .endif
+      .endif
+    .endif
+   .endm // beqi32
+
+/*----------------------------------------------------------------------
+ *  isync_retw_nop
+ *
+ *  This macro must be invoked immediately after ISYNC if ISYNC
+ *  would otherwise be immediately followed by RETW (or other instruction
+ *  modifying WindowBase or WindowStart), in a context where
+ *  kernel vector mode may be selected, and level-one interrupts
+ *  and window overflows may be enabled, on an XEA1 configuration.
+ *
+ *  On hardware with erratum "XEA1KWIN" (see <xtensa/core.h> for details),
+ *  XEA1 code must have at least one instruction between ISYNC and RETW if
+ *  run in kernel vector mode with interrupts and window overflows enabled.
+ */
+	.macro	isync_retw_nop
+#if XCHAL_MAYHAVE_ERRATUM_XEA1KWIN
+	nop
+#endif
+	.endm
+
+/*----------------------------------------------------------------------
+ *  isync_erratum453
+ *
+ *  This macro must be invoked at certain points in the code,
+ *  such as in exception and interrupt vectors in particular,
+ *  to work around erratum 453.
+ */
+	.macro	isync_erratum453
+#if XCHAL_ERRATUM_453
+	isync
+#endif
+	.endm
+
+
+
+/*----------------------------------------------------------------------
+ *  abs
+ *
+ *  implements abs on machines that do not have it configured
+ */
+	
+#if !XCHAL_HAVE_ABS
+	.macro abs arr, ars
+	.ifc \arr, \ars
+	//src equal dest is less efficient
+	bgez \arr, 1f
+	neg \arr, \arr
+1:	
+	.else
+	neg \arr, \ars
+	movgez \arr, \ars, \ars
+	.endif
+	.endm
+#endif /* !XCHAL_HAVE_ABS */
+
+
+/*----------------------------------------------------------------------
+ *  addx2
+ *  
+ *  implements addx2 on machines that do not have it configured
+ *     
+ */
+
+#if !XCHAL_HAVE_ADDX
+	.macro addx2 arr, ars, art
+	.ifc \arr, \art
+	.ifc \arr, \ars
+	// addx2 a, a, a     (not common)
+	.err
+	.else
+	add \arr, \ars, \art
+	add \arr, \ars, \art
+	.endif
+	.else
+	//addx2 a, b, c
+	//addx2 a, a, b
+	//addx2 a, b, b
+	slli \arr, \ars, 1
+	add  \arr, \arr, \art
+	.endif
+	.endm
+#endif /* !XCHAL_HAVE_ADDX */
+	
+/*----------------------------------------------------------------------
+ *  addx4
+ * 
+ *  implements addx4 on machines that do not have it configured
+ *
+ */
+	
+#if !XCHAL_HAVE_ADDX
+	.macro addx4 arr, ars, art
+	.ifc \arr, \art
+	.ifc \arr, \ars
+	// addx4 a, a, a     (not common)
+	 .err
+	 .else
+	//# addx4 a, b, a
+	add \arr, \ars, \art
+	add \arr, \ars, \art
+	add \arr, \ars, \art
+	add \arr, \ars, \art
+	.endif
+	.else
+	//addx4 a, b, c
+	//addx4 a, a, b
+	//addx4 a, b, b
+	slli \arr, \ars, 2
+	add  \arr, \arr, \art
+	.endif
+	.endm
+#endif /* !XCHAL_HAVE_ADDX */
+
+/*----------------------------------------------------------------------
+ *  addx8
+ * 
+ *  implements addx8 on machines that do not have it configured
+ * 
+ */
+
+#if !XCHAL_HAVE_ADDX
+	.macro addx8 arr, ars, art
+	.ifc \arr, \art
+	.ifc \arr, \ars
+	//addx8 a, a, a     (not common)
+	.err
+	.else
+	//addx8 a, b, a
+	add \arr, \ars, \art
+	add \arr, \ars, \art
+	add \arr, \ars, \art
+	add \arr, \ars, \art
+	add \arr, \ars, \art
+	add \arr, \ars, \art
+	add \arr, \ars, \art
+	add \arr, \ars, \art
+	.endif
+	.else
+	//addx8 a, b, c
+	//addx8 a, a, b
+	//addx8 a, b, b
+	slli \arr, \ars, 3
+	add  \arr, \arr, \art
+	.endif
+	.endm
+#endif /* !XCHAL_HAVE_ADDX */
+
+
+/*----------------------------------------------------------------------
+ *  rfe_rfue
+ * 
+ *  Maps to RFUE on XEA1, and RFE on XEA2.  No mapping on XEAX.
+ */
+
+#if XCHAL_HAVE_XEA1
+	.macro	rfe_rfue
+	rfue
+	.endm
+#elif XCHAL_HAVE_XEA2
+	.macro	rfe_rfue
+	rfe
+	.endm
+#endif
+ 
+
+/*----------------------------------------------------------------------
+ *  abi_entry
+ * 
+ *  Generate proper function entry sequence for the current ABI
+ *  (windowed or call0).  Takes care of allocating stack space (up to 1kB)
+ *  and saving the return PC, if necessary.  The corresponding abi_return
+ *  macro does the corresponding stack deallocation and restoring return PC.
+ *
+ *  Parameters are:
+ *
+ *	locsize		Number of bytes to allocate on the stack
+ *			for local variables (and for args to pass to
+ *			callees, if any calls are made).  Defaults to zero.
+ *			The macro rounds this up to a multiple of 16.
+ *			NOTE:  large values are allowed (e.g. up to 1 GB).
+ *
+ *	callsize	Maximum call size made by this function.
+ *			Leave zero (default) for leaf functions, i.e. if
+ *			this function makes no calls to other functions.
+ *			Otherwise must be set to 4, 8, or 12 according
+ *			to whether the "largest" call made is a call[x]4,
+ *			call[x]8, or call[x]12 (for call0 ABI, it makes
+ *			no difference whether this is set to 4, 8 or 12,
+ *			but it must be set to one of these values).
+ *
+ *  NOTE:  It is up to the caller to align the entry point, declare the
+ *  function symbol, make it global, etc.
+ *
+ *  NOTE:  This macro relies on assembler relaxation for large values
+ *  of locsize.  It might not work with the no-transform directive.
+ *  NOTE:  For the call0 ABI, this macro ensures SP is allocated or
+ *  de-allocated cleanly, i.e. without temporarily allocating too much
+ *  (or allocating negatively!) due to addi relaxation.
+ *
+ *  NOTE:  Generating the proper sequence and register allocation for
+ *  making calls in an ABI independent manner is a separate topic not
+ *  covered by this macro.
+ *
+ *  NOTE:  To access arguments, you can't use a fixed offset from SP.
+ *  The offset depends on the ABI, whether the function is leaf, etc.
+ *  The simplest method is probably to use the .locsz symbol, which
+ *  is set by this macro to the actual number of bytes allocated on
+ *  the stack, in other words, to the offset from SP to the arguments.
+ *  E.g. for a function whose arguments are all 32-bit integers, you
+ *  can get the 7th and 8th arguments (1st and 2nd args stored on stack)
+ *  using:
+ *	l32i	a2, sp, .locsz
+ *	l32i	a3, sp, .locsz+4
+ *  (this example works as long as locsize is under L32I's offset limit
+ *   of 1020 minus up to 48 bytes of ABI-specific stack usage;
+ *   otherwise you might first need to do "addi a?, sp, .locsz"
+ *   or similar sequence).
+ *
+ *  NOTE:  For call0 ABI, this macro (and abi_return) may clobber a9
+ *  (a caller-saved register).
+ *
+ *  Examples:
+ *		abi_entry
+ *		abi_entry  5
+ *		abi_entry  22, 8
+ *		abi_entry  0, 4
+ */
+
+	/*
+	 *  Compute .locsz and .callsz without emitting any instructions.
+	 *  Used by both abi_entry and abi_return.
+	 *  Assumes locsize >= 0.
+	 */
+	.macro	abi_entry_size locsize=0, callsize=0
+#if XCHAL_HAVE_WINDOWED && !__XTENSA_CALL0_ABI__
+	.ifeq	\callsize
+	 .set	.callsz, 16
+	.else
+	 .ifeq	\callsize-4
+	  .set	.callsz, 16
+	 .else
+	  .ifeq	\callsize-8
+	   .set	.callsz, 32
+	  .else
+	   .ifeq \callsize-12
+	    .set .callsz, 48
+	   .else
+	    .error	"abi_entry: invalid call size \callsize"
+	   .endif
+	  .endif
+	 .endif
+	.endif
+	.set	.locsz, .callsz + ((\locsize + 15) & -16)
+#else
+	.set	.callsz, \callsize
+	.if	.callsz		/* if calls, need space for return PC */
+	 .set	.locsz, (\locsize + 4 + 15) & -16
+	.else
+	 .set	.locsz, (\locsize + 15) & -16
+	.endif
+#endif
+	.endm
+
+	.macro abi_entry locsize=0, callsize=0
+	.iflt	\locsize
+	 .error	"abi_entry: invalid negative size of locals (\locsize)"
+	.endif
+	abi_entry_size	\locsize, \callsize
+#if XCHAL_HAVE_WINDOWED && !__XTENSA_CALL0_ABI__
+	.ifgt	.locsz - 32760	/* .locsz > 32760 (ENTRY's max range)? */
+	/*  Funky computation to try to have assembler use addmi efficiently if possible:  */
+	entry	sp, 0x7F00 + (.locsz & 0xF0)
+	addi	a12, sp, - ((.locsz & -0x100) - 0x7F00)
+	movsp	sp, a12
+	.else
+	entry	sp, .locsz
+	.endif
+#else
+	.if	.locsz
+	 .ifle	.locsz - 128	/* if locsz <= 128 */
+	addi	sp, sp, -.locsz
+	  .if	.callsz
+	s32i	a0, sp, .locsz - 4
+	  .endif
+	 .elseif  .callsz	/* locsz > 128, with calls: */
+	movi	a9, .locsz - 16		/* note: a9 is caller-saved */
+	addi	sp, sp, -16
+	s32i	a0, sp, 12
+	sub	sp, sp, a9
+	 .else			/* locsz > 128, no calls: */
+	movi	a9, .locsz
+	sub	sp, sp, a9
+	 .endif			/* end */
+	.endif
+#endif
+	.endm
+
+
+
+/*----------------------------------------------------------------------
+ *  abi_return
+ * 
+ *  Generate proper function exit sequence for the current ABI
+ *  (windowed or call0).  Takes care of freeing stack space and
+ *  restoring the return PC, if necessary.
+ *  NOTE:  This macro MUST be invoked following a corresponding
+ *  abi_entry macro invocation.  For call0 ABI in particular,
+ *  all stack and PC restoration are done according to the last
+ *  abi_entry macro invoked before this macro in the assembly file.
+ *
+ *  Normally this macro takes no arguments.  However to allow
+ *  for placing abi_return *before* abi_entry (as must be done
+ *  for some highly optimized assembly), it optionally takes
+ *  exactly the same arguments as abi_entry.
+ */
+
+	.macro abi_return	locsize=-1, callsize=0
+	.ifge	\locsize
+	abi_entry_size	\locsize, \callsize
+	.endif
+#if XCHAL_HAVE_WINDOWED && !__XTENSA_CALL0_ABI__
+	retw
+#else
+	.if	.locsz
+	 .iflt	.locsz - 128	/* if locsz < 128 */
+	  .if	.callsz
+	l32i	a0, sp, .locsz - 4
+	  .endif
+	addi	sp, sp, .locsz
+	 .elseif  .callsz	/* locsz >= 128, with calls: */
+	addi	a9, sp, .locsz - 16
+	l32i	a0, a9, 12
+	addi	sp, a9, 16
+	 .else			/* locsz >= 128, no calls: */
+	movi	a9, .locsz
+	add	sp, sp, a9
+	 .endif			/* end */
+	.endif
+	ret
+#endif
+	.endm
+
+
+/*
+ * HW erratum fixes.
+ */
+
+	.macro hw_erratum_487_fix
+#if defined XSHAL_ERRATUM_487_FIX
+	isync
+#endif
+	.endm
+
+
+#endif /*XTENSA_COREASM_H*/
+

components/esp32/include/xtensa/corebits.h

@@ -0,0 +1,185 @@
+/*
+ * xtensa/corebits.h - Xtensa Special Register field positions, masks, values.
+ *
+ * (In previous releases, these were defined in specreg.h, a generated file.
+ *  This file is not generated, ie. it is processor configuration independent.)
+ */
+
+/* $Id: //depot/rel/Eaglenest/Xtensa/OS/include/xtensa/corebits.h#2 $ */
+
+/*
+ * Copyright (c) 2005-2011 Tensilica Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef XTENSA_COREBITS_H
+#define XTENSA_COREBITS_H
+
+/*  EXCCAUSE register fields:  */
+#define EXCCAUSE_EXCCAUSE_SHIFT	0
+#define EXCCAUSE_EXCCAUSE_MASK	0x3F
+/*  EXCCAUSE register values:  */
+/*
+ *  General Exception Causes
+ *  (values of EXCCAUSE special register set by general exceptions,
+ *   which vector to the user, kernel, or double-exception vectors).
+ */
+#define EXCCAUSE_ILLEGAL		0	/* Illegal Instruction */
+#define EXCCAUSE_SYSCALL		1	/* System Call (SYSCALL instruction) */
+#define EXCCAUSE_INSTR_ERROR		2	/* Instruction Fetch Error */
+# define EXCCAUSE_IFETCHERROR		2	/* (backward compatibility macro, deprecated, avoid) */
+#define EXCCAUSE_LOAD_STORE_ERROR	3	/* Load Store Error */
+# define EXCCAUSE_LOADSTOREERROR	3	/* (backward compatibility macro, deprecated, avoid) */
+#define EXCCAUSE_LEVEL1_INTERRUPT	4	/* Level 1 Interrupt */
+# define EXCCAUSE_LEVEL1INTERRUPT	4	/* (backward compatibility macro, deprecated, avoid) */
+#define EXCCAUSE_ALLOCA			5	/* Stack Extension Assist (MOVSP instruction) for alloca */
+#define EXCCAUSE_DIVIDE_BY_ZERO		6	/* Integer Divide by Zero */
+#define EXCCAUSE_SPECULATION		7	/* Use of Failed Speculative Access (not implemented) */
+#define EXCCAUSE_PRIVILEGED		8	/* Privileged Instruction */
+#define EXCCAUSE_UNALIGNED		9	/* Unaligned Load or Store */
+/* Reserved				10..11 */
+#define EXCCAUSE_INSTR_DATA_ERROR	12	/* PIF Data Error on Instruction Fetch (RB-200x and later) */
+#define EXCCAUSE_LOAD_STORE_DATA_ERROR	13	/* PIF Data Error on Load or Store (RB-200x and later) */
+#define EXCCAUSE_INSTR_ADDR_ERROR	14	/* PIF Address Error on Instruction Fetch (RB-200x and later) */
+#define EXCCAUSE_LOAD_STORE_ADDR_ERROR	15	/* PIF Address Error on Load or Store (RB-200x and later) */
+#define EXCCAUSE_ITLB_MISS		16	/* ITLB Miss (no ITLB entry matches, hw refill also missed) */
+#define EXCCAUSE_ITLB_MULTIHIT		17	/* ITLB Multihit (multiple ITLB entries match) */
+#define EXCCAUSE_INSTR_RING		18	/* Ring Privilege Violation on Instruction Fetch */
+/* Reserved				19 */	/* Size Restriction on IFetch (not implemented) */
+#define EXCCAUSE_INSTR_PROHIBITED	20	/* Cache Attribute does not allow Instruction Fetch */
+/* Reserved				21..23 */
+#define EXCCAUSE_DTLB_MISS		24	/* DTLB Miss (no DTLB entry matches, hw refill also missed) */
+#define EXCCAUSE_DTLB_MULTIHIT		25	/* DTLB Multihit (multiple DTLB entries match) */
+#define EXCCAUSE_LOAD_STORE_RING	26	/* Ring Privilege Violation on Load or Store */
+/* Reserved				27 */	/* Size Restriction on Load/Store (not implemented) */
+#define EXCCAUSE_LOAD_PROHIBITED	28	/* Cache Attribute does not allow Load */
+#define EXCCAUSE_STORE_PROHIBITED	29	/* Cache Attribute does not allow Store */
+/* Reserved				30..31 */
+#define EXCCAUSE_CP_DISABLED(n)		(32+(n))	/* Access to Coprocessor 'n' when disabled */
+#define EXCCAUSE_CP0_DISABLED		32	/* Access to Coprocessor 0 when disabled */
+#define EXCCAUSE_CP1_DISABLED		33	/* Access to Coprocessor 1 when disabled */
+#define EXCCAUSE_CP2_DISABLED		34	/* Access to Coprocessor 2 when disabled */
+#define EXCCAUSE_CP3_DISABLED		35	/* Access to Coprocessor 3 when disabled */
+#define EXCCAUSE_CP4_DISABLED		36	/* Access to Coprocessor 4 when disabled */
+#define EXCCAUSE_CP5_DISABLED		37	/* Access to Coprocessor 5 when disabled */
+#define EXCCAUSE_CP6_DISABLED		38	/* Access to Coprocessor 6 when disabled */
+#define EXCCAUSE_CP7_DISABLED		39	/* Access to Coprocessor 7 when disabled */
+/* Reserved				40..63 */
+
+/*  PS register fields:  */
+#define PS_WOE_SHIFT		18
+#define PS_WOE_MASK		0x00040000
+#define PS_WOE			PS_WOE_MASK
+#define PS_CALLINC_SHIFT	16
+#define PS_CALLINC_MASK		0x00030000
+#define PS_CALLINC(n)		(((n)&3)<<PS_CALLINC_SHIFT)	/* n = 0..3 */
+#define PS_OWB_SHIFT		8
+#define PS_OWB_MASK		0x00000F00
+#define PS_OWB(n)		(((n)&15)<<PS_OWB_SHIFT)	/* n = 0..15 (or 0..7) */
+#define PS_RING_SHIFT		6
+#define PS_RING_MASK		0x000000C0
+#define PS_RING(n)		(((n)&3)<<PS_RING_SHIFT)	/* n = 0..3 */
+#define PS_UM_SHIFT		5
+#define PS_UM_MASK		0x00000020
+#define PS_UM			PS_UM_MASK
+#define PS_EXCM_SHIFT		4
+#define PS_EXCM_MASK		0x00000010
+#define PS_EXCM			PS_EXCM_MASK
+#define PS_INTLEVEL_SHIFT	0
+#define PS_INTLEVEL_MASK	0x0000000F
+#define PS_INTLEVEL(n)		((n)&PS_INTLEVEL_MASK)		/* n = 0..15 */
+/*  Backward compatibility (deprecated):  */
+#define PS_PROGSTACK_SHIFT	PS_UM_SHIFT
+#define PS_PROGSTACK_MASK	PS_UM_MASK
+#define PS_PROG_SHIFT		PS_UM_SHIFT
+#define PS_PROG_MASK		PS_UM_MASK
+#define PS_PROG			PS_UM
+
+/*  DBREAKCn register fields:  */
+#define DBREAKC_MASK_SHIFT		0
+#define DBREAKC_MASK_MASK		0x0000003F
+#define DBREAKC_LOADBREAK_SHIFT		30
+#define DBREAKC_LOADBREAK_MASK		0x40000000
+#define DBREAKC_STOREBREAK_SHIFT	31
+#define DBREAKC_STOREBREAK_MASK		0x80000000
+
+/*  DEBUGCAUSE register fields:  */
+#define DEBUGCAUSE_DEBUGINT_SHIFT	5
+#define DEBUGCAUSE_DEBUGINT_MASK	0x20	/* debug interrupt */
+#define DEBUGCAUSE_BREAKN_SHIFT		4
+#define DEBUGCAUSE_BREAKN_MASK		0x10	/* BREAK.N instruction */
+#define DEBUGCAUSE_BREAK_SHIFT		3
+#define DEBUGCAUSE_BREAK_MASK		0x08	/* BREAK instruction */
+#define DEBUGCAUSE_DBREAK_SHIFT		2
+#define DEBUGCAUSE_DBREAK_MASK		0x04	/* DBREAK match */
+#define DEBUGCAUSE_IBREAK_SHIFT		1
+#define DEBUGCAUSE_IBREAK_MASK		0x02	/* IBREAK match */
+#define DEBUGCAUSE_ICOUNT_SHIFT		0
+#define DEBUGCAUSE_ICOUNT_MASK		0x01	/* ICOUNT would increment to zero */
+
+/*  MESR register fields:  */
+#define MESR_MEME		0x00000001	/* memory error */
+#define MESR_MEME_SHIFT		0
+#define MESR_DME		0x00000002	/* double memory error */
+#define MESR_DME_SHIFT		1
+#define MESR_RCE		0x00000010	/* recorded memory error */
+#define MESR_RCE_SHIFT		4
+#define MESR_LCE		
+#define MESR_LCE_SHIFT		?
+#define MESR_LCE_L
+#define MESR_ERRENAB		0x00000100
+#define MESR_ERRENAB_SHIFT	8
+#define MESR_ERRTEST		0x00000200
+#define MESR_ERRTEST_SHIFT	9
+#define MESR_DATEXC		0x00000400
+#define MESR_DATEXC_SHIFT	10
+#define MESR_INSEXC		0x00000800
+#define MESR_INSEXC_SHIFT	11
+#define MESR_WAYNUM_SHIFT	16
+#define MESR_ACCTYPE_SHIFT	20
+#define MESR_MEMTYPE_SHIFT	24
+#define MESR_ERRTYPE_SHIFT	30
+
+/*  MEMCTL register fields:  */
+#define MEMCTL_SNOOP_EN_SHIFT	1
+#define MEMCTL_SNOOP_EN		0x02	/* enable snoop responses (default 0) */
+#define MEMCTL_L0IBUF_EN_SHIFT	0
+#define MEMCTL_L0IBUF_EN	0x01	/* enable loop instr. buffer (default 1) */
+#define MEMCTL_INV_EN_SHIFT	23
+#define MEMCTL_INV_EN		0x00800000	/* invalidate cache ways being increased */
+#define MEMCTL_DCWU_SHIFT	8
+#define MEMCTL_DCWU_BITS	5
+#define MEMCTL_DCWA_SHIFT	13
+#define MEMCTL_DCWA_BITS	5
+#define MEMCTL_ICWU_SHIFT	18
+#define MEMCTL_ICWU_BITS	5
+#define MEMCTL_DCWU_MASK	0x00001F00	/* Bits  8-12 dcache ways in use */
+#define MEMCTL_DCWA_MASK	0x0003E000	/* Bits 13-17 dcache ways allocatable */
+#define MEMCTL_ICWU_MASK	0x007C0000	/* Bits 18-22 icache ways in use */
+#define MEMCTL_DCWU_CLR_MASK	~(MEMCTL_DCWU_MASK)
+#define MEMCTL_DCWA_CLR_MASK	~(MEMCTL_DCWA_MASK)
+#define MEMCTL_ICWU_CLR_MASK	~(MEMCTL_ICWU_MASK)
+#define MEMCTL_DCW_CLR_MASK	(MEMCTL_DCWU_CLR_MASK | MEMCTL_DCWA_CLR_MASK)
+#define MEMCTL_IDCW_CLR_MASK	(MEMCTL_DCW_CLR_MASK | MEMCTL_ICWU_CLR_MASK)
+
+
+#endif /*XTENSA_COREBITS_H*/
+

components/esp32/include/xtensa/debugfs.h

@@ -0,0 +1,93 @@
+/*  Xtensa Debug-FileSystem definitions  */
+
+/*
+ * Copyright (c) 2005-2009 by Tensilica Inc.  ALL RIGHTS RESERVED.
+ * These coded instructions, statements, and computer programs are the
+ * copyrighted works and confidential proprietary information of Tensilica Inc.
+ * They may not be modified, copied, reproduced, distributed, or disclosed to
+ * third parties in any manner, medium, or form, in whole or in part, without
+ * the prior written consent of Tensilica Inc.
+ */
+
+#ifndef __DEBUGFS_H__
+#define __DEBUGFS_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <unistd.h>
+#include <fcntl.h>
+#include <stdlib.h>
+
+int xt_dbfs_open(const char *pathname, int flags, mode_t mode);
+int xt_dbfs_ftruncate(int fd, off_t length);
+int xt_dbfs_truncate(const char * filename, off_t length);
+int xt_dbfs_creat(const char *pathname, mode_t mode);
+int xt_dbfs_errno(void);
+int xt_dbfs_lseek(int fd, off_t offset, int whence);
+ssize_t xt_dbfs_write(int fd, const void * buf, size_t bytes);
+  ssize_t xt_dbfs_open_append_close(const char * filename, int align,
+				  const void * buf, size_t bytes);
+ssize_t xt_dbfs_read(int fd, void * buf, size_t bytes);
+int xt_dbfs_close(int fd);
+int xt_dbfs_unlink(const char *pathname);
+
+/* By default, this function is a wrapper around sbrk, and follows 
+   sbrk semantics:
+   
+   On success, it returns increment bytes of memory allocated from 
+   system memory.
+
+   On failure, it returns 0xFFFFFFFF
+
+   
+   If you want to use a method of allocating memory other than sbrk,
+   implement xt_dbfs_sbrk in your own sources, and the linker will 
+   automatically use that copy.
+*/
+void * xt_dbfs_sbrk(int increment);
+
+
+
+#ifdef REPLACE_FS_WITH_DBFS
+#define open xt_dbfs_open
+#define close xt_dbfs_close
+#define creat xt_dbfs_creat
+#define lseek xt_dbfs_lseek
+#define write xt_dbfs_write
+#define read xt_dbfs_read
+#define close xt_dbfs_close
+#define unlink xt_dbfs_unlink
+
+#define rmdir NOT_IMPLEMENTED_IN_DBFS
+#define opendir NOT_IMPLEMENTED_IN_DBFS
+#define closedir NOT_IMPLEMENTED_IN_DBFS
+#define dirfs NOT_IMPLEMENTED_IN_DBFS
+#define readdir NOT_IMPLEMENTED_IN_DBFS
+#define scandir NOT_IMPLEMENTED_IN_DBFS
+#define seekdir NOT_IMPLEMENTED_IN_DBFS
+#define telldir NOT_IMPLEMENTED_IN_DBFS
+
+#define fcntl NOT_IMPLEMENTED_IN_DBFS
+#define dup2 NOT_IMPLEMENTED_IN_DBFS
+#define dup NOT_IMPLEMENTED_IN_DBFS
+#define flock NOT_IMPLEMENTED_IN_DBFS
+#define lockf NOT_IMPLEMENTED_IN_DBFS
+#define link NOT_IMPLEMENTED_IN_DBFS
+#define stat NOT_IMPLEMENTED_IN_DBFS
+#define fstat NOT_IMPLEMENTED_IN_DBFS
+#define lstat NOT_IMPLEMENTED_IN_DBFS
+#define chmod NOT_IMPLEMENTED_IN_DBFS
+#define fchmod NOT_IMPLEMENTED_IN_DBFS
+#define chmown NOT_IMPLEMENTED_IN_DBFS
+#define lchown NOT_IMPLEMENTED_IN_DBFS
+#define fchown NOT_IMPLEMENTED_IN_DBFS
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

components/esp32/include/xtensa/feedback.h

@@ -0,0 +1,45 @@
+
+/*
+ * Copyright (c) 2013 by Tensilica Inc.  ALL RIGHTS RESERVED.
+ * These coded instructions, statements, and computer programs are the
+ * copyrighted works and confidential proprietary information of Tensilica Inc.
+ * They may not be modified, copied, reproduced, distributed, or disclosed to
+ * third parties in any manner, medium, or form, in whole or in part, without
+ * the prior written consent of Tensilica Inc.
+ */
+
+#ifndef __XT_FEEDBACK_INCLUDED__
+#define __XT_FEEDBACK_INCLUDED__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* xt_feedback_save_and_reset
+
+   Save and reset the accumulated feedback data.
+*/
+extern void xt_feedback_save_and_reset(void);
+
+/* xt_feedback_enable
+
+   Turn on feedback accumulation. Ordinarily, feedback accumulation is on
+   by default. If you turn it off using xt_feedback_disable, You can turn 
+   it on again via this function.
+*/
+extern void xt_feedback_enable (void);
+
+/* xt_feedback_disable
+
+   Turn off feedback accumulation. If you don't want to gather feedback for a
+   portion of your code, use this function and then xt_feedback_enable when
+   you want to start again.
+*/
+extern void xt_feedback_disable (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __XT_FEEDBACK_INCLUDED__ */
+

components/esp32/include/xtensa/gdbio.h

@@ -0,0 +1,80 @@
+/*  Xtensa Debug-FileSystem definitions
+ *
+ * Copyright (c) 2006-2009 by Tensilica Inc.  ALL RIGHTS RESERVED.
+ * These coded instructions, statements, and computer programs are the
+ * copyrighted works and confidential proprietary information of Tensilica Inc.
+ * They may not be modified, copied, reproduced, distributed, or disclosed to
+ * third parties in any manner, medium, or form, in whole or in part, without
+ * the prior written consent of Tensilica Inc.
+ */
+
+#ifndef __DEBUGFS_H__
+#define __DEBUGFS_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <unistd.h>
+#include <fcntl.h>
+#include <stdlib.h>
+#include <errno.h>
+
+  int _gdbio_open_r(void * ptr, const char *pathname, int flags, mode_t mode);
+  int _gdbio_creat_r(void * ptr, const char *pathname, mode_t mode);
+  int _gdbio_lseek_r(void * ptr, int fd, off_t offset, int whence);
+  ssize_t _gdbio_write_r(void * ptr, int fd, const void * buf, size_t bytes);
+  ssize_t _gdbio_read_r(void * ptr, int fd, void * buf, size_t bytes);
+  int _gdbio_close_r(void * ptr, int fd);
+  int _gdbio_unlink_r(void * ptr, const char * pathname);
+  
+  static inline
+  int gdbio_open(const char *pathname, int flags, mode_t mode) {
+    return _gdbio_open_r(&errno, pathname, flags, mode);
+  }
+  static inline int 
+  gdbio_creat(const char *pathname, mode_t mode) {
+    return _gdbio_open_r(&errno, pathname, O_CREAT|O_WRONLY|O_TRUNC, mode);
+  }
+  static inline int 
+  gdbio_errno(void) {
+    return errno;
+  }
+  static inline int 
+  gdbio_lseek(int fd, off_t offset, int whence) {
+    return _gdbio_lseek_r(&errno, fd, offset, whence);
+  }
+  static inline 
+  ssize_t gdbio_write(int fd, const void * buf, size_t bytes) {
+    return  _gdbio_write_r(&errno, fd, buf, bytes);
+  }
+  static inline
+  ssize_t gdbio_read(int fd, void * buf, size_t bytes) {
+    return  _gdbio_read_r(&errno, fd, buf, bytes);
+  }
+  static inline int 
+  gdbio_close(int fd) {
+    return _gdbio_close_r(&errno, fd);
+  }
+  static inline int 
+  gdbio_unlink(const char * pathname) {
+    return _gdbio_unlink_r(&errno, pathname);
+  }
+
+#ifdef REPLACE_FS_WITH_GDBIO
+#define open gdbio_open
+#define close gdbio_close
+#define creat gdbio_creat
+#define lseek gdbio_lseek
+#define write gdbio_write
+#define read gdbio_read
+#define close gdbio_close
+#define unlink gdbio_unlink
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

components/esp32/include/xtensa/hal.h

@@ -0,0 +1,1024 @@
+/*
+   xtensa/hal.h -- contains a definition of the Core HAL interface
+
+   All definitions in this header file are independent of any specific
+   Xtensa processor configuration.  Thus software (eg. OS, application,
+   etc) can include this header file and be compiled into configuration-
+   independent objects that can be distributed and eventually linked
+   to the HAL library (libhal.a) to create a configuration-specific
+   final executable.
+
+   Certain definitions, however, are release/version-specific -- such as
+   the XTHAL_RELEASE_xxx macros (or additions made in later versions).
+
+
+   $Id: //depot/rel/Eaglenest/Xtensa/OS/target-os-src/hal.h.tpp#4 $
+
+   Copyright (c) 1999-2014 Cadence Design Systems, Inc.
+
+   Permission is hereby granted, free of charge, to any person obtaining
+   a copy of this software and associated documentation files (the
+   "Software"), to deal in the Software without restriction, including
+   without limitation the rights to use, copy, modify, merge, publish,
+   distribute, sublicense, and/or sell copies of the Software, and to
+   permit persons to whom the Software is furnished to do so, subject to
+   the following conditions:
+
+   The above copyright notice and this permission notice shall be included
+   in all copies or substantial portions of the Software.
+
+   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#ifndef XTENSA_HAL_H
+#define XTENSA_HAL_H
+
+
+/****************************************************************************
+	    Definitions Useful for Any Code, USER or PRIVILEGED
+ ****************************************************************************/
+
+
+/*----------------------------------------------------------------------
+	   Constant Definitions  (shared with assembly)
+  ----------------------------------------------------------------------*/
+
+/*
+ *  Software (Xtensa Tools) version information.  Not configuration-specific!
+ *
+ *  NOTE:  "release" is a misnomer here, these are really product "version"
+ *	numbers.  A "release" is a collection of product versions
+ *	made available at once (together) to customers.
+ *	In the past, release and version names all matched in T####.# form,
+ *	making the distinction irrelevant.  This is no longer the case.
+ */
+#define XTHAL_RELEASE_MAJOR	11000
+#define XTHAL_RELEASE_MINOR	3
+#define XTHAL_RELEASE_NAME	"11.0.3"
+#define XTHAL_REL_11	1
+#define XTHAL_REL_11_0	1
+#define XTHAL_REL_11_0_3	1
+
+/*  HAL version numbers (these names are for backward compatibility):  */
+#define XTHAL_MAJOR_REV		XTHAL_RELEASE_MAJOR
+#define XTHAL_MINOR_REV		XTHAL_RELEASE_MINOR
+/*
+ *  A bit of software release/version history on values of XTHAL_{MAJOR,MINOR}_REV:
+ *
+ *	SW Version	MAJOR	MINOR		Comment
+ *	=======		=====	=====		=======
+ *	T1015.n		n/a	n/a		(HAL not yet available)
+ *	T1020.{0,1,2}	0	1		(HAL beta)
+ *	T1020.{3,4}	0	2		First release.
+ *	T1020.n (n>4)	0	2 or >3		(TBD)
+ *	T1030.0		0	1		(HAL beta)
+ *	T1030.{1,2}	0	3		Equivalent to first release.
+ *	T1030.n (n>=3)	0	>= 3		(TBD)
+ *	T1040.n		1040	n		Full CHAL available from T1040.2
+ *	T1050.n		1050	n		.
+ *	6.0.n		6000	n		Xtensa Tools v6   (RA-200x.n)
+ *	7.0.n		7000	n		Xtensa Tools v7   (RB-200x.n)
+ *	7.1.n		7010	n		Xtensa Tools v7.1 (RB-200x.(n+2))
+ *	8.0.n		8000	n		Xtensa Tools v8   (RC-20xx.n)
+ *	9.0.n		9000	n		Xtensa Tools v9   (RD-201x.n)
+ *	10.0.n		10000	n		Xtensa Tools v10  (RE-201x.n)
+ *
+ *
+ *  Note:  there is a distinction between the software version with
+ *  which something is compiled (accessible using XTHAL_RELEASE_* macros)
+ *  and the software version with which the HAL library was compiled
+ *  (accessible using Xthal_release_* global variables).  This
+ *  distinction is particularly relevant for vendors that distribute
+ *  configuration-independent binaries (eg. an OS), where their customer
+ *  might link it with a HAL of a different Xtensa software version.
+ *  In this case, it may be appropriate for the OS to verify at run-time
+ *  whether XTHAL_RELEASE_* and Xthal_release_* are compatible.
+ *  [Guidelines as to which version is compatible with which are not
+ *  currently provided explicitly, but might be inferred from reading
+ *  OSKit documentation for all releases -- compatibility is also highly
+ *  dependent on which HAL features are used.  Each version is usually
+ *  backward compatible, with very few exceptions if any.]
+ */
+
+/*  Version comparison operators (among major/minor pairs):  */
+#define XTHAL_REL_GE(maja,mina, majb,minb)	((maja) > (majb) || \
+						 ((maja) == (majb) && (mina) >= (minb)))
+#define XTHAL_REL_GT(maja,mina, majb,minb)	((maja) > (majb) || \
+						 ((maja) == (majb) && (mina) > (minb)))
+#define XTHAL_REL_LE(maja,mina, majb,minb)	((maja) < (majb) || \
+						 ((maja) == (majb) && (mina) <= (minb)))
+#define XTHAL_REL_LT(maja,mina, majb,minb)	((maja) < (majb) || \
+						 ((maja) == (majb) && (mina) < (minb)))
+#define XTHAL_REL_EQ(maja,mina, majb,minb)	((maja) == (majb) && (mina) == (minb))
+
+/*  Fuzzy (3-way) logic operators:  */
+#define XTHAL_MAYBE		-1	/* 0=NO, 1=YES, -1=MAYBE */
+#define XTHAL_FUZZY_AND(a,b)	(((a)==0 || (b)==0) ? 0 : ((a)==1 && (b)==1) ? 1 : XTHAL_MAYBE)
+#define XTHAL_FUZZY_OR(a,b)	(((a)==1 || (b)==1) ? 1 : ((a)==0 && (b)==0) ? 0 : XTHAL_MAYBE)
+#define XTHAL_FUZZY_NOT(a)	(((a)==0 || (a)==1) ? (1-(a)) : XTHAL_MAYBE)
+
+
+/*
+ *  Architectural limit, independent of configuration:
+ */
+#define XTHAL_MAX_CPS		8	/* max number of coprocessors (0..7) */
+
+/*  Misc:  */
+#define XTHAL_LITTLEENDIAN		0
+#define XTHAL_BIGENDIAN			1
+
+
+
+#if !defined(_ASMLANGUAGE) && !defined(_NOCLANGUAGE) && !defined(__ASSEMBLER__)
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*----------------------------------------------------------------------
+				HAL
+  ----------------------------------------------------------------------*/
+
+/* Constant to be checked in build = (XTHAL_MAJOR_REV<<16)|XTHAL_MINOR_REV */
+extern const unsigned int Xthal_rev_no;
+
+
+/*----------------------------------------------------------------------
+			Optional/Custom Processor State
+  ----------------------------------------------------------------------*/
+
+/* save & restore the extra processor state */
+extern void xthal_save_extra(void *base);
+extern void xthal_restore_extra(void *base);
+
+extern void xthal_save_cpregs(void *base, int);
+extern void xthal_restore_cpregs(void *base, int);
+/* versions specific to each coprocessor id */
+extern void xthal_save_cp0(void *base);
+extern void xthal_save_cp1(void *base);
+extern void xthal_save_cp2(void *base);
+extern void xthal_save_cp3(void *base);
+extern void xthal_save_cp4(void *base);
+extern void xthal_save_cp5(void *base);
+extern void xthal_save_cp6(void *base);
+extern void xthal_save_cp7(void *base);
+extern void xthal_restore_cp0(void *base);
+extern void xthal_restore_cp1(void *base);
+extern void xthal_restore_cp2(void *base);
+extern void xthal_restore_cp3(void *base);
+extern void xthal_restore_cp4(void *base);
+extern void xthal_restore_cp5(void *base);
+extern void xthal_restore_cp6(void *base);
+extern void xthal_restore_cp7(void *base);
+/* pointers to each of the functions above */
+extern void* Xthal_cpregs_save_fn[XTHAL_MAX_CPS];
+extern void* Xthal_cpregs_restore_fn[XTHAL_MAX_CPS];
+/* similarly for non-windowed ABI (may be same or different) */
+extern void* Xthal_cpregs_save_nw_fn[XTHAL_MAX_CPS];
+extern void* Xthal_cpregs_restore_nw_fn[XTHAL_MAX_CPS];
+
+/*extern void xthal_save_all_extra(void *base);*/
+/*extern void xthal_restore_all_extra(void *base);*/
+
+/* space for processor state */
+extern const unsigned int Xthal_extra_size;
+extern const unsigned int Xthal_extra_align;
+extern const unsigned int Xthal_cpregs_size[XTHAL_MAX_CPS];
+extern const unsigned int Xthal_cpregs_align[XTHAL_MAX_CPS];
+extern const unsigned int Xthal_all_extra_size;
+extern const unsigned int Xthal_all_extra_align;
+/* coprocessor names */
+extern const char * const Xthal_cp_names[XTHAL_MAX_CPS];
+
+/* initialize the extra processor */
+/*extern void xthal_init_extra(void);*/
+/* initialize the TIE coprocessor */
+/*extern void xthal_init_cp(int);*/
+
+/* initialize the extra processor */
+extern void xthal_init_mem_extra(void *);
+/* initialize the TIE coprocessor */
+extern void xthal_init_mem_cp(void *, int);
+
+/* the number of TIE coprocessors contiguous from zero (for Tor2) */
+extern const unsigned int Xthal_num_coprocessors;
+
+/* actual number of coprocessors */
+extern const unsigned char Xthal_cp_num;
+/* index of highest numbered coprocessor, plus one */
+extern const unsigned char Xthal_cp_max;
+/* index of highest allowed coprocessor number, per cfg, plus one */
+/*extern const unsigned char Xthal_cp_maxcfg;*/
+/* bitmask of which coprocessors are present */
+extern const unsigned int  Xthal_cp_mask;
+
+/* read & write extra state register */
+/*extern int xthal_read_extra(void *base, unsigned reg, unsigned *value);*/
+/*extern int xthal_write_extra(void *base, unsigned reg, unsigned value);*/
+
+/* read & write a TIE coprocessor register */
+/*extern int xthal_read_cpreg(void *base, int cp, unsigned reg, unsigned *value);*/
+/*extern int xthal_write_cpreg(void *base, int cp, unsigned reg, unsigned value);*/
+
+/* return coprocessor number based on register */
+/*extern int xthal_which_cp(unsigned reg);*/
+
+
+/*----------------------------------------------------------------------
+   				Register Windows
+  ----------------------------------------------------------------------*/
+
+/* number of registers in register window */
+extern const unsigned int  Xthal_num_aregs;
+extern const unsigned char Xthal_num_aregs_log2;
+
+
+/*----------------------------------------------------------------------
+   				Cache
+  ----------------------------------------------------------------------*/
+
+/* size of the cache lines in log2(bytes) */
+extern const unsigned char Xthal_icache_linewidth;
+extern const unsigned char Xthal_dcache_linewidth;
+/* size of the cache lines in bytes (2^linewidth) */
+extern const unsigned short Xthal_icache_linesize;
+extern const unsigned short Xthal_dcache_linesize;
+
+/* size of the caches in bytes (ways * 2^(linewidth + setwidth)) */
+extern const unsigned int  Xthal_icache_size;
+extern const unsigned int  Xthal_dcache_size;
+/* cache features */
+extern const unsigned char Xthal_dcache_is_writeback;
+
+/* invalidate the caches */
+
+extern void xthal_icache_region_invalidate( void *addr, unsigned size );
+extern void xthal_dcache_region_invalidate( void *addr, unsigned size );
+# ifndef XTHAL_USE_CACHE_MACROS
+extern void xthal_icache_line_invalidate(void *addr);
+extern void xthal_dcache_line_invalidate(void *addr);
+# endif
+/* write dirty data back */
+extern void xthal_dcache_region_writeback( void *addr, unsigned size );
+# ifndef XTHAL_USE_CACHE_MACROS
+extern void xthal_dcache_line_writeback(void *addr);
+# endif
+/* write dirty data back and invalidate */
+extern void xthal_dcache_region_writeback_inv( void *addr, unsigned size );
+# ifndef XTHAL_USE_CACHE_MACROS
+extern void xthal_dcache_line_writeback_inv(void *addr);
+/* sync icache and memory */
+extern void xthal_icache_sync( void );
+/* sync dcache and memory */
+extern void xthal_dcache_sync( void );
+#endif
+
+/* get number of icache ways enabled */
+extern unsigned int xthal_icache_get_ways(void);
+/* set number of icache ways enabled */
+extern void xthal_icache_set_ways(unsigned int ways);
+/* get number of dcache ways enabled */
+extern unsigned int xthal_dcache_get_ways(void);
+/* set number of dcache ways enabled */
+extern void xthal_dcache_set_ways(unsigned int ways);
+
+/* coherency (low-level -- not normally called directly) */
+extern void xthal_cache_coherence_on( void );
+extern void xthal_cache_coherence_off( void );
+/* coherency (high-level) */
+extern void xthal_cache_coherence_optin( void );
+extern void xthal_cache_coherence_optout( void );
+
+/*
+ *  Cache prefetch control.
+ *  The parameter to xthal_set_cache_prefetch() contains both
+ *  a PREFCTL register value and a mask of which bits to actually modify.
+ *  This allows easily combining field macros (below) by ORing,
+ *  leaving unspecified fields unmodified.
+ *
+ *  For backward compatibility with the older version of this routine
+ *  (that took 15-bit value and mask in a 32-bit parameter, for pre-RF
+ *  cores with only the lower 15 bits of PREFCTL defined), the 32-bit
+ *  value and mask are staggered as follows in a 64-bit parameter:
+ *	param[63:48] are PREFCTL[31:16]		if param[31] is set
+ *	param[47:32] are mask[31:16]		if param[31] is set
+ *	param[31]    is set if mask is used, 0 if not
+ *	param[31:16] are mask[15:0]		if param[31] is set
+ *	param[31:16] are PREFCTL[31:16]		if param[31] is clear
+ *	param[15:0]  are PREFCTL[15:0]
+ *
+ *  Limitation:  PREFCTL register bit 31 cannot be set without masking,
+ *  and bit 15 must always be set when using masking, so it is hoped that
+ *  these two bits will remain reserved, read-as-zero in PREFCTL.
+ */
+#define XTHAL_PREFETCH_ENABLE		-1	/* enable inst+data prefetch */
+#define XTHAL_PREFETCH_DISABLE		0xFFFF0000 /* disab inst+data prefetch*/
+#define XTHAL_DCACHE_PREFETCH(n)	(0x800F0000+((n)&0xF))   /* data-side */
+#define XTHAL_DCACHE_PREFETCH_OFF	XTHAL_DCACHE_PREFETCH(0) /* disable */
+#define XTHAL_DCACHE_PREFETCH_LOW	XTHAL_DCACHE_PREFETCH(4) /* less aggr.*/
+#define XTHAL_DCACHE_PREFETCH_MEDIUM	XTHAL_DCACHE_PREFETCH(5) /* mid aggr. */
+#define XTHAL_DCACHE_PREFETCH_HIGH	XTHAL_DCACHE_PREFETCH(8) /* more aggr.*/
+#define XTHAL_DCACHE_PREFETCH_L1_OFF	0x90000000	/* to prefetch buffers*/
+#define XTHAL_DCACHE_PREFETCH_L1	0x90001000	/* direct to L1 dcache*/
+#define XTHAL_ICACHE_PREFETCH(n)	(0x80F00000+(((n)&0xF)<<4)) /* i-side */
+#define XTHAL_ICACHE_PREFETCH_OFF	XTHAL_ICACHE_PREFETCH(0) /* disable */
+#define XTHAL_ICACHE_PREFETCH_LOW	XTHAL_ICACHE_PREFETCH(4) /* less aggr.*/
+#define XTHAL_ICACHE_PREFETCH_MEDIUM	XTHAL_ICACHE_PREFETCH(5) /* mid aggr. */
+#define XTHAL_ICACHE_PREFETCH_HIGH	XTHAL_ICACHE_PREFETCH(8) /* more aggr.*/
+#define XTHAL_ICACHE_PREFETCH_L1_OFF	0xA0000000	/* (not implemented) */
+#define XTHAL_ICACHE_PREFETCH_L1	0xA0002000	/* (not implemented) */
+#define _XTHAL_PREFETCH_BLOCKS(n)	((n)<0?0:(n)<5?(n):(n)<15?((n)>>1)+2:9)
+#define XTHAL_PREFETCH_BLOCKS(n)	(0x0000000F80000000ULL + \
+					(((unsigned long long)_XTHAL_PREFETCH_BLOCKS(n))<<48))
+
+extern int  xthal_get_cache_prefetch( void );
+extern int  xthal_set_cache_prefetch( int );
+extern int  xthal_set_cache_prefetch_long( unsigned long long );
+/*  Only use the new extended function from now on:  */
+#define xthal_set_cache_prefetch	xthal_set_cache_prefetch_long
+#define xthal_set_cache_prefetch_nw	xthal_set_cache_prefetch_long_nw
+
+
+/*----------------------------------------------------------------------
+   				Debug
+  ----------------------------------------------------------------------*/
+
+/*  1 if debug option configured, 0 if not:  */
+extern const int Xthal_debug_configured;
+
+/*  Set (plant) and remove software breakpoint, both synchronizing cache:  */
+extern unsigned int xthal_set_soft_break(void *addr);
+extern void         xthal_remove_soft_break(void *addr, unsigned int);
+
+
+/*----------------------------------------------------------------------
+   				Disassembler
+  ----------------------------------------------------------------------*/
+
+/*  Max expected size of the return buffer for a disassembled instruction (hint only):  */
+#define XTHAL_DISASM_BUFSIZE	80
+
+/*  Disassembly option bits for selecting what to return:  */
+#define XTHAL_DISASM_OPT_ADDR	0x0001	/* display address */
+#define XTHAL_DISASM_OPT_OPHEX	0x0002	/* display opcode bytes in hex */
+#define XTHAL_DISASM_OPT_OPCODE	0x0004	/* display opcode name (mnemonic) */
+#define XTHAL_DISASM_OPT_PARMS	0x0008	/* display parameters */
+#define XTHAL_DISASM_OPT_ALL	0x0FFF	/* display everything */
+
+/* routine to get a string for the disassembled instruction */
+extern int xthal_disassemble( unsigned char *instr_buf, void *tgt_addr,
+		       char *buffer, unsigned buflen, unsigned options );
+
+/* routine to get the size of the next instruction. Returns 0 for
+   illegal instruction */
+extern int xthal_disassemble_size( unsigned char *instr_buf );
+
+
+/*----------------------------------------------------------------------
+			Instruction/Data RAM/ROM Access
+  ----------------------------------------------------------------------*/
+
+extern void* xthal_memcpy(void *dst, const void *src, unsigned len);
+extern void* xthal_bcopy(const void *src, void *dst, unsigned len);
+
+
+/*----------------------------------------------------------------------
+                           MP Synchronization
+  ----------------------------------------------------------------------*/
+
+extern int      xthal_compare_and_set( int *addr, int test_val, int compare_val );
+
+/*extern const char  Xthal_have_s32c1i;*/
+
+
+/*----------------------------------------------------------------------
+                             Miscellaneous
+  ----------------------------------------------------------------------*/
+
+extern const unsigned int  Xthal_release_major;
+extern const unsigned int  Xthal_release_minor;
+extern const char * const  Xthal_release_name;
+extern const char * const  Xthal_release_internal;
+
+extern const unsigned char Xthal_memory_order;
+extern const unsigned char Xthal_have_windowed;
+extern const unsigned char Xthal_have_density;
+extern const unsigned char Xthal_have_booleans;
+extern const unsigned char Xthal_have_loops;
+extern const unsigned char Xthal_have_nsa;
+extern const unsigned char Xthal_have_minmax;
+extern const unsigned char Xthal_have_sext;
+extern const unsigned char Xthal_have_clamps;
+extern const unsigned char Xthal_have_mac16;
+extern const unsigned char Xthal_have_mul16;
+extern const unsigned char Xthal_have_fp;
+extern const unsigned char Xthal_have_speculation;
+extern const unsigned char Xthal_have_threadptr;
+
+extern const unsigned char Xthal_have_pif;
+extern const unsigned short Xthal_num_writebuffer_entries;
+
+extern const unsigned int  Xthal_build_unique_id;
+/*  Version info for hardware targeted by software upgrades:  */
+extern const unsigned int  Xthal_hw_configid0;
+extern const unsigned int  Xthal_hw_configid1;
+extern const unsigned int  Xthal_hw_release_major;
+extern const unsigned int  Xthal_hw_release_minor;
+extern const char * const  Xthal_hw_release_name;
+extern const char * const  Xthal_hw_release_internal;
+
+/*  Clear any remnant code-dependent state (i.e. clear loop count regs).  */
+extern void	xthal_clear_regcached_code( void );
+
+#ifdef __cplusplus
+}
+#endif
+#endif /*!_ASMLANGUAGE && !_NOCLANGUAGE && !__ASSEMBLER__ */
+
+
+
+
+
+/****************************************************************************
+    Definitions Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
+ ****************************************************************************/
+
+
+#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
+
+/*----------------------------------------------------------------------
+	   Constant Definitions  (shared with assembly)
+  ----------------------------------------------------------------------*/
+
+/*
+ *  Architectural limits, independent of configuration.
+ *  Note that these are ISA-defined limits, not micro-architecture implementation
+ *  limits enforced by the Xtensa Processor Generator (which may be stricter than
+ *  these below).
+ */
+#define XTHAL_MAX_INTERRUPTS	32	/* max number of interrupts (0..31) */
+#define XTHAL_MAX_INTLEVELS	16	/* max number of interrupt levels (0..15) */
+					/* (as of T1040, implementation limit is 7: 0..6) */
+#define XTHAL_MAX_TIMERS	4	/* max number of timers (CCOMPARE0..CCOMPARE3) */
+					/* (as of T1040, implementation limit is 3: 0..2) */
+
+/*  Interrupt types:  */
+#define XTHAL_INTTYPE_UNCONFIGURED	0
+#define XTHAL_INTTYPE_SOFTWARE		1
+#define XTHAL_INTTYPE_EXTERN_EDGE	2
+#define XTHAL_INTTYPE_EXTERN_LEVEL	3
+#define XTHAL_INTTYPE_TIMER		4
+#define XTHAL_INTTYPE_NMI		5
+#define XTHAL_INTTYPE_WRITE_ERROR	6
+#define XTHAL_INTTYPE_PROFILING		7
+#define XTHAL_MAX_INTTYPES		8	/* number of interrupt types */
+
+/*  Timer related:  */
+#define XTHAL_TIMER_UNCONFIGURED	-1	/* Xthal_timer_interrupt[] value for non-existent timers */
+#define XTHAL_TIMER_UNASSIGNED	XTHAL_TIMER_UNCONFIGURED	/* (for backwards compatibility only) */
+
+/*  Local Memory ECC/Parity:  */
+#define XTHAL_MEMEP_PARITY	1
+#define XTHAL_MEMEP_ECC		2
+/*  Flags parameter to xthal_memep_inject_error():  */
+#define XTHAL_MEMEP_F_LOCAL		0	/* local memory (default) */
+#define XTHAL_MEMEP_F_DCACHE_DATA	4	/* data cache data */
+#define XTHAL_MEMEP_F_DCACHE_TAG	5	/* data cache tag */
+#define XTHAL_MEMEP_F_ICACHE_DATA	6	/* instruction cache data */
+#define XTHAL_MEMEP_F_ICACHE_TAG	7	/* instruction cache tag */
+#define XTHAL_MEMEP_F_CORRECTABLE	16	/* inject correctable error
+						   (default is non-corr.) */
+
+
+/*  Access Mode bits (tentative):  */	/* bit abbr unit short_name       PPC equ - Description */
+#define XTHAL_AMB_EXCEPTION	0	/* 001 E EX fls: EXception        none
+					   exception on any access (aka "illegal") */
+#define XTHAL_AMB_HITCACHE	1	/* 002 C CH fls: use Cache on Hit ~(I CI)
+					   [or H HC]  way from tag match;
+					   [or U UC] (ISA: same except Isolate case) */
+#define XTHAL_AMB_ALLOCATE	2	/* 004 A AL fl?: ALlocate         none
+					   [or F FI fill] refill cache on miss, way from LRU
+					   (ISA: Read/Write Miss Refill) */
+#define XTHAL_AMB_WRITETHRU	3	/* 008 W WT --s: WriteThrough     W WT
+					   store immediately to memory (ISA: same) */
+#define XTHAL_AMB_ISOLATE	4	/* 010 I IS fls: ISolate          none
+					   use cache regardless of hit-vs-miss,
+					   way from vaddr (ISA: use-cache-on-miss+hit) */
+#define XTHAL_AMB_GUARD		5	/* 020 G GU ?l?: GUard            G *
+					   non-speculative; spec/replay refs not permitted */
+#define XTHAL_AMB_COHERENT	6	/* 040 M MC ?ls: Mem/MP Coherent  M
+					   on read, other CPU/bus-master may need to supply data;
+					   on write, maybe redirect to or flush other CPU dirty line; etc */
+#if 0
+#define XTHAL_AMB_BUFFERABLE	x	/* 000 B BU --s: BUfferable       ?
+					   write response may return earlier than from final destination */
+#define XTHAL_AMB_ORDERED	x	/* 000 O OR fls: ORdered          G *
+					   mem accesses cannot be out of order */
+#define XTHAL_AMB_FUSEWRITES	x	/* 000 F FW --s: FuseWrites       none
+					   allow combining/merging/coalescing multiple writes
+					   (to same datapath data unit) into one
+					   (implied by writeback) */
+#define XTHAL_AMB_TRUSTED	x	/* 000 T TR ?l?: TRusted          none
+					   memory will not bus error (if it does,
+					   handle as fatal imprecise interrupt) */
+#define XTHAL_AMB_PREFETCH	x	/* 000 P PR fl?: PRefetch         none
+					   on refill, read line+1 into prefetch buffers */
+#define XTHAL_AMB_STREAM	x	/* 000 S ST ???: STreaming        none
+					   access one of N stream buffers */
+#endif /*0*/
+
+#define XTHAL_AM_EXCEPTION	(1<<XTHAL_AMB_EXCEPTION)
+#define XTHAL_AM_HITCACHE	(1<<XTHAL_AMB_HITCACHE)
+#define XTHAL_AM_ALLOCATE	(1<<XTHAL_AMB_ALLOCATE)
+#define XTHAL_AM_WRITETHRU	(1<<XTHAL_AMB_WRITETHRU)
+#define XTHAL_AM_ISOLATE	(1<<XTHAL_AMB_ISOLATE)
+#define XTHAL_AM_GUARD		(1<<XTHAL_AMB_GUARD)
+#define XTHAL_AM_COHERENT	(1<<XTHAL_AMB_COHERENT)
+#if 0
+#define XTHAL_AM_BUFFERABLE	(1<<XTHAL_AMB_BUFFERABLE)
+#define XTHAL_AM_ORDERED	(1<<XTHAL_AMB_ORDERED)
+#define XTHAL_AM_FUSEWRITES	(1<<XTHAL_AMB_FUSEWRITES)
+#define XTHAL_AM_TRUSTED	(1<<XTHAL_AMB_TRUSTED)
+#define XTHAL_AM_PREFETCH	(1<<XTHAL_AMB_PREFETCH)
+#define XTHAL_AM_STREAM		(1<<XTHAL_AMB_STREAM)
+#endif /*0*/
+
+/*
+ *  Allowed Access Modes (bit combinations).
+ *
+ *  Columns are:
+ *  "FOGIWACE"
+ *	Access mode bits (see XTHAL_AMB_xxx above).
+ *	<letter> = bit is set
+ *	'-'      = bit is clear
+ *	'.'      = bit is irrelevant / don't care, as follows:
+ *			E=1 makes all others irrelevant
+ *			W,F relevant only for stores
+ *  "2345"
+ *	Indicates which Xtensa releases support the corresponding
+ *	access mode.  Releases for each character column are:
+ *		2 = prior to T1020.2:   T1015 (V1.5), T1020.0, T1020.1
+ *		3 = T1020.2 and later:  T1020.2+, T1030
+ *		4 = T1040
+ *		5 = T1050 (maybe), LX1, LX2, LX2.1
+ *		7 = LX2.2
+ *		8 = LX3, LX4
+ *		9 = LX5
+ *	And the character column contents are:
+ *		<number> = supported by release(s)
+ *		"." = unsupported by release(s)
+ *		"?" = support unknown
+ */
+						/* foMGIWACE 2345789 */
+/*  For instruction fetch:  */
+#define XTHAL_FAM_EXCEPTION		0x001	/* ........E 2345789 exception */
+/*efine XTHAL_FAM_ISOLATE*/	      /*0x012*/	/* .---I.-C- ....... isolate */
+#define XTHAL_FAM_BYPASS		0x000	/* .----.--- 2345789 bypass */
+/*efine XTHAL_FAM_NACACHED*/	      /*0x002*/	/* .----.-C- ....... cached no-allocate (frozen) */
+#define XTHAL_FAM_CACHED		0x006	/* .----.AC- 2345789 cached */
+/*  For data load:  */
+#define XTHAL_LAM_EXCEPTION		0x001	/* ........E 2345789 exception */
+#define XTHAL_LAM_ISOLATE		0x012	/* .---I.-C- 2345789 isolate */
+#define XTHAL_LAM_BYPASS		0x000	/* .O---.--- 2...... bypass speculative */
+#define XTHAL_LAM_BYPASSG		0x020	/* .O-G-.--- .345789 bypass guarded */
+#define XTHAL_LAM_CACHED_NOALLOC	0x002	/* .O---.-C- 2345789 cached no-allocate speculative */
+#define XTHAL_LAM_NACACHED		XTHAL_LAM_CACHED_NOALLOC
+#define XTHAL_LAM_NACACHEDG		0x022	/* .O-G-.-C- .?..... cached no-allocate guarded */
+#define XTHAL_LAM_CACHED		0x006	/* .----.AC- 2345789 cached speculative */
+#define XTHAL_LAM_COHCACHED		0x046	/* .-M--.AC- ....*89 cached speculative MP-coherent */
+/*  For data store:  */
+#define XTHAL_SAM_EXCEPTION		0x001	/* ........E 2345789 exception */
+#define XTHAL_SAM_ISOLATE		0x032	/* .--GI--C- 2345789 isolate */
+#define XTHAL_SAM_BYPASS		0x028	/* -O-G-W--- 2345789 bypass */
+#define XTHAL_SAM_WRITETHRU		0x02A	/* -O-G-W-C- 2345789 writethrough */
+/*efine XTHAL_SAM_WRITETHRU_ALLOC*/   /*0x02E*/	/* -O-G-WAC- ....... writethrough allocate */
+#define XTHAL_SAM_WRITEBACK		0x026	/* F--G--AC- ...5789 writeback */
+#define XTHAL_SAM_WRITEBACK_NOALLOC	0x022	/* ?--G---C- .....89 writeback no-allocate */
+#define XTHAL_SAM_COHWRITEBACK		0x066	/* F-MG--AC- ....*89 writeback MP-coherent */
+/*  For PIF attributes:  */			/* -PIwrWCBUUUU ...9 */
+#define XTHAL_PAM_BYPASS		0x000	/* xxx00000xxxx ...9 bypass non-bufferable */
+#define XTHAL_PAM_BYPASS_BUF		0x010	/* xxx0000bxxxx ...9 bypass */
+#define XTHAL_PAM_CACHED_NOALLOC	0x030	/* xxx0001bxxxx ...9 cached no-allocate */
+#define XTHAL_PAM_WRITETHRU		0x0B0	/* xxx0101bxxxx ...9 writethrough (WT) */
+#define XTHAL_PAM_WRITEBACK_NOALLOC	0x0F0	/* xxx0111bxxxx ...9 writeback no-alloc (WBNA) */
+#define XTHAL_PAM_WRITEBACK		0x1F0	/* xxx1111bxxxx ...9 writeback (WB) */
+/*efine XTHAL_PAM_NORMAL*/	      /*0x050*/	/* xxx0010bxxxx .... (unimplemented) */
+/*efine XTHAL_PAM_WRITETHRU_WA*/      /*0x130*/	/* xxx1001bxxxx .... (unimplemented, less likely) */
+/*efine XTHAL_PAM_WRITETHRU_RWA*/     /*0x1B0*/	/* xxx1101bxxxx .... (unimplemented, less likely) */
+/*efine XTHAL_PAM_WRITEBACK_WA*/      /*0x170*/	/* xxx1011bxxxx .... (unimplemented, less likely) */
+
+
+#if 0
+/*
+    Cache attribute encoding for CACHEATTR (per ISA):
+    (Note:  if this differs from ISA Ref Manual, ISA has precedence)
+
+	Inst-fetches	Loads		Stores
+	-------------	------------	-------------
+0x0	FCA_EXCEPTION	LCA_NACACHED	SCA_WRITETHRU	cached no-allocate (previously misnamed "uncached")
+0x1	FCA_CACHED	LCA_CACHED	SCA_WRITETHRU	cached
+0x2	FCA_BYPASS	LCA_BYPASS_G*	SCA_BYPASS	bypass cache (what most people call uncached)
+0x3	FCA_CACHED	LCA_CACHED	SCA_WRITEALLOCF	write-allocate
+		     or LCA_EXCEPTION	SCA_EXCEPTION	(if unimplemented)
+0x4	FCA_CACHED	LCA_CACHED	SCA_WRITEBACK[M] write-back [MP-coherent]
+		     or LCA_EXCEPTION	SCA_EXCEPTION	(if unimplemented)
+0x5	FCA_CACHED	LCA_CACHED	SCA_WRITEBACK_NOALLOC	write-back no-allocate
+     or	FCA_EXCEPTION	LCA_EXCEPTION	SCA_EXCEPTION	(if unimplemented)
+0x6..D	FCA_EXCEPTION	LCA_EXCEPTION	SCA_EXCEPTION	(reserved)
+0xE	FCA_EXCEPTION	LCA_ISOLATE	SCA_ISOLATE	isolate
+0xF	FCA_EXCEPTION	LCA_EXCEPTION	SCA_EXCEPTION	illegal
+     *  Prior to T1020.2?, guard feature not supported, this defaulted to speculative (no _G)
+*/
+#endif /*0*/
+
+
+#if !defined(_ASMLANGUAGE) && !defined(_NOCLANGUAGE) && !defined(__ASSEMBLER__)
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/*----------------------------------------------------------------------
+   				Register Windows
+  ----------------------------------------------------------------------*/
+
+/*  This spill any live register windows (other than the caller's):
+ *  (NOTE:  current implementation require privileged code, but
+ *   a user-callable implementation is possible.)  */
+extern void      xthal_window_spill( void );
+
+
+/*----------------------------------------------------------------------
+			Optional/Custom Processor State
+  ----------------------------------------------------------------------*/
+
+/* validate & invalidate the TIE register file */
+extern void xthal_validate_cp(int);
+extern void xthal_invalidate_cp(int);
+
+/* read and write cpenable register */
+extern void xthal_set_cpenable(unsigned);
+extern unsigned xthal_get_cpenable(void);
+
+
+/*----------------------------------------------------------------------
+   				Interrupts
+  ----------------------------------------------------------------------*/
+
+/* the number of interrupt levels */
+extern const unsigned char Xthal_num_intlevels;
+/* the number of interrupts */
+extern const unsigned char Xthal_num_interrupts;
+/* the highest level of interrupts masked by PS.EXCM */
+extern const unsigned char Xthal_excm_level;
+
+/* mask for level of interrupts */
+extern const unsigned int Xthal_intlevel_mask[XTHAL_MAX_INTLEVELS];
+/* mask for level 0 to N interrupts */
+extern const unsigned int Xthal_intlevel_andbelow_mask[XTHAL_MAX_INTLEVELS];
+
+/* level of each interrupt */
+extern const unsigned char Xthal_intlevel[XTHAL_MAX_INTERRUPTS];
+
+/* type per interrupt */
+extern const unsigned char Xthal_inttype[XTHAL_MAX_INTERRUPTS];
+
+/* masks of each type of interrupt */
+extern const unsigned int Xthal_inttype_mask[XTHAL_MAX_INTTYPES];
+
+/* interrupt numbers assigned to each timer interrupt */
+extern const int Xthal_timer_interrupt[XTHAL_MAX_TIMERS];
+
+/*  INTENABLE,INTERRUPT,INTSET,INTCLEAR register access functions:  */
+extern unsigned  xthal_get_intenable( void );
+extern void      xthal_set_intenable( unsigned );
+extern unsigned  xthal_get_interrupt( void );
+#define xthal_get_intread	xthal_get_interrupt	/* backward compatibility */
+extern void      xthal_set_intset( unsigned );
+extern void      xthal_set_intclear( unsigned );
+
+
+/*----------------------------------------------------------------------
+   				Debug
+  ----------------------------------------------------------------------*/
+
+/*  Number of instruction and data break registers:  */
+extern const int Xthal_num_ibreak;
+extern const int Xthal_num_dbreak;
+
+
+/*----------------------------------------------------------------------
+   				Core Counter
+  ----------------------------------------------------------------------*/
+
+/* counter info */
+extern const unsigned char Xthal_have_ccount;	/* set if CCOUNT register present */
+extern const unsigned char Xthal_num_ccompare;	/* number of CCOMPAREn registers */
+
+/* get CCOUNT register (if not present return 0) */
+extern unsigned xthal_get_ccount(void);
+
+/* set and get CCOMPAREn registers (if not present, get returns 0) */
+extern void     xthal_set_ccompare(int, unsigned);
+extern unsigned xthal_get_ccompare(int);
+
+
+/*----------------------------------------------------------------------
+                             Miscellaneous
+  ----------------------------------------------------------------------*/
+
+extern const unsigned char Xthal_have_prid;
+extern const unsigned char Xthal_have_exceptions;
+extern const unsigned char Xthal_xea_version;
+extern const unsigned char Xthal_have_interrupts;
+extern const unsigned char Xthal_have_highlevel_interrupts;
+extern const unsigned char Xthal_have_nmi;
+
+extern unsigned xthal_get_prid( void );
+
+
+/*----------------------------------------------------------------------
+		Virtual interrupt prioritization (DEPRECATED)
+  ----------------------------------------------------------------------*/
+
+/*  Convert between interrupt levels (as per PS.INTLEVEL) and virtual interrupt priorities:  */
+extern unsigned	xthal_vpri_to_intlevel(unsigned vpri);
+extern unsigned	xthal_intlevel_to_vpri(unsigned intlevel);
+
+/*  Enables/disables given set (mask) of interrupts; returns previous enabled-mask of all ints:  */
+extern unsigned	xthal_int_enable(unsigned);
+extern unsigned	xthal_int_disable(unsigned);
+
+/*  Set/get virtual priority of an interrupt:  */
+extern int	xthal_set_int_vpri(int intnum, int vpri);
+extern int	xthal_get_int_vpri(int intnum);
+
+/*  Set/get interrupt lockout level for exclusive access to virtual priority data structures:  */
+extern void	xthal_set_vpri_locklevel(unsigned intlevel);
+extern unsigned	xthal_get_vpri_locklevel(void);
+
+/*  Set/get current virtual interrupt priority:  */
+extern unsigned	xthal_set_vpri(unsigned vpri);
+extern unsigned	xthal_get_vpri(void);
+extern unsigned	xthal_set_vpri_intlevel(unsigned intlevel);
+extern unsigned	xthal_set_vpri_lock(void);
+
+
+/*----------------------------------------------------------------------
+	Generic Interrupt Trampolining Support (DEPRECATED)
+  ----------------------------------------------------------------------*/
+
+typedef void (XtHalVoidFunc)(void);
+
+/*  Bitmask of interrupts currently trampolining down:  */
+extern unsigned Xthal_tram_pending;
+
+/*
+ *  Bitmask of which interrupts currently trampolining down synchronously are
+ *  actually enabled; this bitmask is necessary because INTENABLE cannot hold
+ *  that state (sync-trampolining interrupts must be kept disabled while
+ *  trampolining);  in the current implementation, any bit set here is not set
+ *  in INTENABLE, and vice-versa; once a sync-trampoline is handled (at level
+ *  one), its enable bit must be moved from here to INTENABLE:
+ */
+extern unsigned Xthal_tram_enabled;
+
+/*  Bitmask of interrupts configured for sync trampolining:  */
+extern unsigned Xthal_tram_sync;
+
+/*  Trampoline support functions:  */
+extern unsigned  xthal_tram_pending_to_service( void );
+extern void      xthal_tram_done( unsigned serviced_mask );
+extern int       xthal_tram_set_sync( int intnum, int sync );
+extern XtHalVoidFunc* xthal_set_tram_trigger_func( XtHalVoidFunc *trigger_fn );
+
+
+/*----------------------------------------------------------------------
+			Internal Memories
+  ----------------------------------------------------------------------*/
+
+extern const unsigned char Xthal_num_instrom;
+extern const unsigned char Xthal_num_instram;
+extern const unsigned char Xthal_num_datarom;
+extern const unsigned char Xthal_num_dataram;
+extern const unsigned char Xthal_num_xlmi;
+
+/*  Each of the following arrays contains at least one entry,
+ *  or as many entries as needed if more than one:  */
+extern const unsigned int  Xthal_instrom_vaddr[];
+extern const unsigned int  Xthal_instrom_paddr[];
+extern const unsigned int  Xthal_instrom_size [];
+extern const unsigned int  Xthal_instram_vaddr[];
+extern const unsigned int  Xthal_instram_paddr[];
+extern const unsigned int  Xthal_instram_size [];
+extern const unsigned int  Xthal_datarom_vaddr[];
+extern const unsigned int  Xthal_datarom_paddr[];
+extern const unsigned int  Xthal_datarom_size [];
+extern const unsigned int  Xthal_dataram_vaddr[];
+extern const unsigned int  Xthal_dataram_paddr[];
+extern const unsigned int  Xthal_dataram_size [];
+extern const unsigned int  Xthal_xlmi_vaddr[];
+extern const unsigned int  Xthal_xlmi_paddr[];
+extern const unsigned int  Xthal_xlmi_size [];
+
+
+/*----------------------------------------------------------------------
+   				Cache
+  ----------------------------------------------------------------------*/
+
+/* number of cache sets in log2(lines per way) */
+extern const unsigned char Xthal_icache_setwidth;
+extern const unsigned char Xthal_dcache_setwidth;
+/* cache set associativity (number of ways) */
+extern const unsigned int  Xthal_icache_ways;
+extern const unsigned int  Xthal_dcache_ways;
+/* cache features */
+extern const unsigned char Xthal_icache_line_lockable;
+extern const unsigned char Xthal_dcache_line_lockable;
+
+/* cache attribute register control (used by other HAL routines) */
+extern unsigned xthal_get_cacheattr( void );
+extern unsigned xthal_get_icacheattr( void );
+extern unsigned xthal_get_dcacheattr( void );
+extern void     xthal_set_cacheattr( unsigned );
+extern void     xthal_set_icacheattr( unsigned );
+extern void     xthal_set_dcacheattr( unsigned );
+/* set cache attribute (access modes) for a range of memory */
+extern int      xthal_set_region_attribute( void *addr, unsigned size,
+					    unsigned cattr, unsigned flags );
+/*  Bits of flags parameter to xthal_set_region_attribute():  */
+#define XTHAL_CAFLAG_EXPAND		0x000100	/* only expand allowed access to range, don't reduce it */
+#define XTHAL_CAFLAG_EXACT		0x000200	/* return error if can't apply change to exact range specified */
+#define XTHAL_CAFLAG_NO_PARTIAL		0x000400	/* don't apply change to regions partially covered by range */
+#define XTHAL_CAFLAG_NO_AUTO_WB		0x000800	/* don't writeback data after leaving writeback attribute */
+#define XTHAL_CAFLAG_NO_AUTO_INV	0x001000	/* don't invalidate after disabling cache (entering bypass) */
+
+/* enable caches */
+extern void xthal_icache_enable( void );	/* DEPRECATED */
+extern void xthal_dcache_enable( void );	/* DEPRECATED */
+/* disable caches */
+extern void xthal_icache_disable( void );	/* DEPRECATED */
+extern void xthal_dcache_disable( void );	/* DEPRECATED */
+
+/* invalidate the caches */
+extern void xthal_icache_all_invalidate( void );
+extern void xthal_dcache_all_invalidate( void );
+/* write dirty data back */
+extern void xthal_dcache_all_writeback( void );
+/* write dirty data back and invalidate */
+extern void xthal_dcache_all_writeback_inv( void );
+/* prefetch and lock specified memory range into cache */
+extern void xthal_icache_region_lock( void *addr, unsigned size );
+extern void xthal_dcache_region_lock( void *addr, unsigned size );
+# ifndef XTHAL_USE_CACHE_MACROS
+extern void xthal_icache_line_lock(void *addr);
+extern void xthal_dcache_line_lock(void *addr);
+# endif
+/* unlock from cache */
+extern void xthal_icache_all_unlock( void );
+extern void xthal_dcache_all_unlock( void );
+extern void xthal_icache_region_unlock( void *addr, unsigned size );
+extern void xthal_dcache_region_unlock( void *addr, unsigned size );
+# ifndef XTHAL_USE_CACHE_MACROS
+extern void xthal_icache_line_unlock(void *addr);
+extern void xthal_dcache_line_unlock(void *addr);
+# endif
+
+
+
+/*----------------------------------------------------------------------
+                         Local Memory ECC/Parity
+  ----------------------------------------------------------------------*/
+
+/*  Inject memory errors; flags is bit combination of XTHAL_MEMEP_F_xxx:  */
+extern void xthal_memep_inject_error(void *addr, int size, int flags);
+
+
+
+/*----------------------------------------------------------------------
+                         Memory Management Unit
+  ----------------------------------------------------------------------*/
+
+extern const unsigned char Xthal_have_spanning_way;
+extern const unsigned char Xthal_have_identity_map;
+extern const unsigned char Xthal_have_mimic_cacheattr;
+extern const unsigned char Xthal_have_xlt_cacheattr;
+extern const unsigned char Xthal_have_cacheattr;
+extern const unsigned char Xthal_have_tlbs;
+
+extern const unsigned char Xthal_mmu_asid_bits;		/* 0 .. 8 */
+extern const unsigned char Xthal_mmu_asid_kernel;
+extern const unsigned char Xthal_mmu_rings;		/* 1 .. 4 (perhaps 0 if no MMU and/or no protection?) */
+extern const unsigned char Xthal_mmu_ring_bits;
+extern const unsigned char Xthal_mmu_sr_bits;
+extern const unsigned char Xthal_mmu_ca_bits;
+extern const unsigned int  Xthal_mmu_max_pte_page_size;
+extern const unsigned int  Xthal_mmu_min_pte_page_size;
+
+extern const unsigned char Xthal_itlb_way_bits;
+extern const unsigned char Xthal_itlb_ways;
+extern const unsigned char Xthal_itlb_arf_ways;
+extern const unsigned char Xthal_dtlb_way_bits;
+extern const unsigned char Xthal_dtlb_ways;
+extern const unsigned char Xthal_dtlb_arf_ways;
+
+/*  Convert between virtual and physical addresses (through static maps only):  */
+/*** WARNING: these two functions may go away in a future release; don't depend on them! ***/
+extern int  xthal_static_v2p( unsigned vaddr, unsigned *paddrp );
+extern int  xthal_static_p2v( unsigned paddr, unsigned *vaddrp, unsigned cached );
+
+#define XCHAL_SUCCESS 0
+#define XCHAL_ADDRESS_MISALIGNED -1
+#define XCHAL_INEXACT -2
+#define XCHAL_INVALID_ADDRESS -3
+#define XCHAL_UNSUPPORTED_ON_THIS_ARCH -4
+#define XCHAL_NO_PAGES_MAPPED -5
+#define XTHAL_NO_MAPPING -6
+
+#define XCHAL_CA_R   (0xC0 | 0x40000000)
+#define XCHAL_CA_RX  (0xD0 | 0x40000000)
+#define XCHAL_CA_RW  (0xE0 | 0x40000000)
+#define XCHAL_CA_RWX (0xF0 | 0x40000000)
+
+extern int xthal_set_region_translation(void* vaddr, void* paddr, unsigned size, unsigned cache_atr, unsigned flags);
+extern int xthal_v2p(void*, void**, unsigned*, unsigned*);
+extern int xthal_invalidate_region(void* addr);
+extern int xthal_set_region_translation_raw(void *vaddr, void *paddr, unsigned cattr);
+
+#ifdef __cplusplus
+}
+#endif
+#endif /*!_ASMLANGUAGE && !_NOCLANGUAGE && !__ASSEMBLER__ */
+
+#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
+
+
+
+
+/****************************************************************************
+		EXPERIMENTAL and DEPRECATED Definitions
+ ****************************************************************************/
+
+
+#if !defined(_ASMLANGUAGE) && !defined(_NOCLANGUAGE) && !defined(__ASSEMBLER__)
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef INCLUDE_DEPRECATED_HAL_CODE
+extern const unsigned char Xthal_have_old_exc_arch;
+extern const unsigned char Xthal_have_mmu;
+extern const unsigned int  Xthal_num_regs;
+extern const unsigned char Xthal_num_iroms;
+extern const unsigned char Xthal_num_irams;
+extern const unsigned char Xthal_num_droms;
+extern const unsigned char Xthal_num_drams;
+extern const unsigned int  Xthal_configid0;
+extern const unsigned int  Xthal_configid1;
+#endif
+
+#ifdef INCLUDE_DEPRECATED_HAL_DEBUG_CODE
+#define XTHAL_24_BIT_BREAK		0x80000000
+#define XTHAL_16_BIT_BREAK		0x40000000
+extern const unsigned short	Xthal_ill_inst_16[16];
+#define XTHAL_DEST_REG		0xf0000000	/* Mask for destination register */
+#define XTHAL_DEST_REG_INST	0x08000000	/* Branch address is in register */
+#define XTHAL_DEST_REL_INST	0x04000000	/* Branch address is relative */
+#define XTHAL_RFW_INST		0x00000800
+#define XTHAL_RFUE_INST		0x00000400
+#define XTHAL_RFI_INST		0x00000200
+#define XTHAL_RFE_INST		0x00000100
+#define XTHAL_RET_INST		0x00000080
+#define XTHAL_BREAK_INST	0x00000040
+#define XTHAL_SYSCALL_INST	0x00000020
+#define XTHAL_LOOP_END		0x00000010	/* Not set by xthal_inst_type */
+#define XTHAL_JUMP_INST		0x00000008	/* Call or jump instruction */
+#define XTHAL_BRANCH_INST	0x00000004	/* Branch instruction */
+#define XTHAL_24_BIT_INST	0x00000002
+#define XTHAL_16_BIT_INST   0x00000001
+typedef struct xthal_state {
+    unsigned	pc;
+    unsigned	ar[16];
+    unsigned	lbeg;
+    unsigned	lend;
+    unsigned	lcount;
+    unsigned	extra_ptr;
+    unsigned	cpregs_ptr[XTHAL_MAX_CPS];
+} XTHAL_STATE;
+extern unsigned int xthal_inst_type(void *addr);
+extern unsigned int xthal_branch_addr(void *addr);
+extern unsigned int xthal_get_npc(XTHAL_STATE *user_state);
+#endif /* INCLUDE_DEPRECATED_HAL_DEBUG_CODE */
+
+#ifdef __cplusplus
+}
+#endif
+#endif /*!_ASMLANGUAGE && !_NOCLANGUAGE && !__ASSEMBLER__ */
+
+#endif /*XTENSA_HAL_H*/
+

components/esp32/include/xtensa/jtag-xtensa.h

@@ -0,0 +1,99 @@
+/* Copyright (c) 2011-2012 Tensilica Inc.  ALL RIGHTS RESERVED.
+// These coded instructions, statements, and computer programs are the
+// copyrighted works and confidential proprietary information of Tensilica Inc.
+// They may not be modified, copied, reproduced, distributed, or disclosed to
+// third parties in any manner, medium, or form, in whole or in part, without
+// the prior written consent of Tensilica Inc.
+*/
+
+#ifndef _JTAG_XTENSA_H_
+#define _JTAG_XTENSA_H_
+
+
+/* ---------------- JTAG registers ------------------ */
+
+/* -- ER and later JTAG registers */
+typedef enum {
+	regIR,
+	regBypass,
+	regNAR,
+	regNDR,
+	regIdcode,
+	regPWRCTL,
+	regPWRSTAT,
+	regJtagMAX, 
+} xtensaJtagReg;
+
+/* -- pre-ER JTAG registers */
+typedef enum {
+	regOldIR,
+	regOldBypass,
+	regOldDIRW,
+	regOldDIR,
+	regOldDDR,
+	regOldDOSR,
+	regOldESR,
+	regOldDCR,
+	regOldTraxNDR,
+	regOldTraxNAR,
+	regOldMAX
+} xtensaOldJtagReg;
+
+
+/* ---------------- JTAG Instructions ------------------ */
+
+/* -- pre-ER JTAG instructions */
+typedef enum {
+	ji_EnableOCD = 0x11,
+	ji_DebugInt,
+	ji_RetDebugInt,  // TBD: remove
+	ji_DisRetOCD,    // TBD: remove
+	ji_ExecuteDI,
+	ji_LoadDI,
+	ji_ScanDDR,
+	ji_ReadDOSR,
+	ji_ScanDCR,
+	ji_LoadWDI,
+	ji_TRAX   = 0x1c,
+	ji_BYPASS = 0x1f,
+} xtensaJtagInstruction;
+
+typedef enum {
+	OCDNormalMode,
+	OCDRunMode,
+	OCDHaltMode,
+	OCDStepMode
+} xtensaMode;
+
+typedef struct {
+	xtensaMode mode;
+	int DRsel;
+	XTMP_core core;
+	XTMP_tap tap;
+	int core_num;
+	jtagReg_t *jtagRegs;
+	void *dap;             // used for ARM DAP only
+	bool isBig;
+	int dir_array_option;  // used by pre-ER devices only 
+	// for testing, below - FIXME - delete later
+	int ocdReg;
+	unsigned int wr_data;
+	XTMP_event start_OCD_trans;
+	bool data_cycle;
+	bool data_pending;
+} coreSlaveData_t;
+
+
+enum OCD_ACCESS_TYPE{
+   NEXUS_ACCESS,
+   CS_ACCESS,
+};
+
+// pre-ER Xtensa initializiation
+EXTERN XTMP_deviceStatus
+XTMP_jtagCoreSlaveEX(XTMP_component component, XTMP_jtagSlave slave, void* mydata);
+
+extern char *OCDrd;
+extern char *OCDwr;
+
+#endif

components/esp32/include/xtensa/lcd-splc780d-4bitmode-board.h

@@ -0,0 +1,62 @@
+/*******************************************************************************
+Copyright (c) 2009-2013 by Tensilica Inc.  ALL RIGHTS RESERVED.
+These coded instructions, statements, and computer programs are the
+copyrighted works and confidential proprietary information of Tensilica Inc.
+They may not be modified, copied, reproduced, distributed, or disclosed to
+third parties in any manner, medium, or form, in whole or in part, without
+the prior written consent of Tensilica Inc.
+--------------------------------------------------------------------------------
+
+lcd-splc780d-4bitmode-board.h    Board-specific LCD info for these boards:
+	Avnet AV110 (XT-AV110)
+	Xilinx ML605 (XT-ML605)
+	Xilinx KC705 (XT-KC705)
+
+Interface between board-independent driver and board-specific header.
+
+This is used by a board-independent SPLC780D LCD controller (4 bit mode)
+driver to obtain board-specific information about LCD displays on the board, 
+such as the controller register base address and spacing (a function of how 
+the address lines are connected on the board) and length of the visible window 
+of the display (a function of the LCD panel the controller drives). 
+The driver doesnot refer directly to the board-specific header, which therefore is not 
+constrained to use macro names consistent with other boards.
+
+!! Must not contain any board-specific macro names (only controller specific) !!
+
+Included at compile-time via an include path specific to the board.
+
+The listed boards contain a single MYTech MOC-16216B-B display driven by 
+a Sunplus SPLC870D controller.
+
+*******************************************************************************/
+
+#ifndef _LCD_SPLC780D_4BIT_BOARD_H
+#define _LCD_SPLC780D_4BIT_BOARD_H
+
+#include <xtensa/board.h>              /* Board info */
+
+
+/* Base address of the controller's registers. */
+#ifdef SPLC780D_4BIT_VADDR
+#define SPLC780D_4BIT_REGBASE SPLC780D_4BIT_VADDR
+#endif
+
+/* 
+The controller's registers are connected at word addresses on these boards.
+Each byte-wide register appears as the least-significant-byte (LSB) of the 
+word regardless of the endianness of the processor (so if using word accesses 
+then endianness doesn't matter).
+*/
+#define SPLC780D_4BIT_REGSPACING 4
+typedef unsigned splc780d_4bit_reg_t;
+
+/* Include generic information shared by all boards that use this device. */
+#include    <xtensa/lcd-splc780d-4bitmode.h>
+
+
+/* Display limits of the LCD panel. */
+#define DISPLAY_VISIBLE_LEN 16  /* length (chars) of visible window */
+
+#endif /* _LCD_SPLC780D_4BIT_BOARD_H */
+

components/esp32/include/xtensa/lcd-splc780d-4bitmode.h

@@ -0,0 +1,105 @@
+/*******************************************************************************
+
+Copyright (c) 2009-2010 by Tensilica Inc.  ALL RIGHTS RESERVED.
+These coded instructions, statements, and computer programs are the
+copyrighted works and confidential proprietary information of Tensilica Inc.
+They may not be modified, copied, reproduced, distributed, or disclosed to
+third parties in any manner, medium, or form, in whole or in part, without
+the prior written consent of Tensilica Inc.
+--------------------------------------------------------------------------------
+
+lcd-SPLC780D-4bitmode.h  Generic definitions for Sunplus SPLC780D LCD Controller
+operating in 4 bit mode.
+
+This is used by board-support-packages with one or more LCD displays that use
+a SPLC780D controller in 4 bit mode. A BSP provides a base address for each 
+instance of an SPLC780D LCD controller on the board.
+
+Note that LCD display operation is almost totally independent of the LCD 
+display, depending almost entirely on the controller. However the display
+may limit the number of characters of the controller's RAM buffer that are
+actually visible at one time. The length of the display's visible window
+is not specifified in this controller-specific header, but comes to the 
+driver from the board-specific "display.h" header.
+
+*******************************************************************************/
+
+#ifndef _LCD_SPLC780D_4BIT_H_
+#define _LCD_SPLC780D_4BIT_H_
+
+
+/* Offsets to controller registers from base. */
+#define SPLC780D_4BIT_INST   0
+#define SPLC780D_4BIT_DATA   (SPLC780D_4BIT_INST + SPLC780D_4BIT_REGSPACING)
+
+
+#define SPLC780D_4BIT_INST_INIT1             0xFF /* First command in 
+                                                     init sequence */
+#define SPLC780D_4BIT_INST_INIT2             0x30 /* Second command in 
+                                                     init sequence, 
+                                                     issued 3 times */
+#define SPLC780D_4BIT_INST_INIT3             0x20 /* Third and last command 
+                                                     in init sequence */
+#define SPLC780D_4BIT_INST_CLEAR             0x01 /* clear (blank) display) */
+#define SPLC780D_4BIT_INST_SET_MODE          0x28 /* Set LCD mode. Supported
+                                                     setting is 4 bit data 
+                                                     length, 2 lines, 5*8 */
+#define SPLC780D_4BIT_INST_DSPLY_ON          0x0C /* Set Display ON */
+#define SPLC780D_4BIT_INST_CRSR_INC          0x06 /* Set cursor moving direction
+                                                     as increment */
+
+#define SPLC780D_4BIT_LINET_ADDR             0x80 /* clear (blank) display) */
+#define SPLC780D_4BIT_LINEB_ADDR             0xC0 /* clear (blank) display) */
+
+#ifndef __ASSEMBLER__
+
+/* C interface to controller registers. */
+struct splc780d_4bit_s {
+    splc780d_4bit_reg_t  inst;       /* instruction register */
+    splc780d_4bit_reg_t  data;       /* data register */
+};
+
+typedef volatile struct splc780d_4bit_s splc780d_4bit_t;
+
+/*
+Prototypes of high level driver functions.
+*/
+
+/* Write an instruction byte to LCD, result in two back to back writes since the
+ * LCD is hooked up in 4 bit mode*/
+extern void lcd_write_inst_byte(splc780d_4bit_t *lcd, unsigned char inst);
+
+/* Write a data byte to LCD, result in two back to back writes since the
+ * LCD is hooked up in 4 bit mode*/
+extern void lcd_write_data_byte(splc780d_4bit_t *lcd, unsigned char data);
+
+/*
+Initialize the display with default settings. 
+*/
+extern void splc780d_4bit_init_default(splc780d_4bit_t *lcd);
+
+/*
+Write a single character at a given position (chars from left, starting at 0).
+Wait long enough afterward for the controller to be ready for more input.
+Positions beyond the end of the display are ignored.
+*/
+extern void splc780d_4bit_write_char(splc780d_4bit_t *lcd, unsigned pos, const char c);
+
+/*
+Write a string to the display starting at the left (position 0). 
+Blank-pad to or truncate at the end of the display (overwrites any previous 
+string so don't need to blank the display first).
+Wait long enough after each char for the controller to be ready for more input.
+*/
+extern void splc780d_4bit_write_string(splc780d_4bit_t *lcd, const char *s);
+
+/*
+Blank (clear) the entire display.
+Wait long enough afterward for the controller to be ready for more input.
+*/
+extern void splc780d_4bit_blank(splc780d_4bit_t *lcd);
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* _LCD_SPLC780D_4BIT_H_ */
+

components/esp32/include/xtensa/lcd-splc780d.h

@@ -0,0 +1,151 @@
+/*******************************************************************************
+
+Copyright (c) 2006-2007 by Tensilica Inc.  ALL RIGHTS RESERVED.
+These coded instructions, statements, and computer programs are the
+copyrighted works and confidential proprietary information of Tensilica Inc.
+They may not be modified, copied, reproduced, distributed, or disclosed to
+third parties in any manner, medium, or form, in whole or in part, without
+the prior written consent of Tensilica Inc.
+--------------------------------------------------------------------------------
+
+lcd-SPLC780D.h  Generic definitions for Sunplus SPLC780D LCD Controller
+
+This is used by board-support-packages with one or more LCD displays that use
+a SPLC780D controller. A BSP provides a base address for each instance of an 
+SPLC780D LCD controller on the board.
+
+Note that LCD display operation is almost totally independent of the LCD 
+display, depending almost entirely on the controller. However the display
+may limit the number of characters of the controller's RAM buffer that are
+actually visible at one time. The length of the display's visible window
+is not specifified in this controller-specific header, but comes to the 
+driver from the board-specific "display.h" header.
+
+*******************************************************************************/
+
+#ifndef _LCD_SPLC780D_H_
+#define _LCD_SPLC780D_H_
+
+
+/* Offsets to controller registers from base. */
+#define SPLC780D_INST   0
+#define SPLC780D_DATA   (SPLC780D_INST + SPLC780D_REGSPACING)
+
+/*
+Bit fields and their values in the instruction register.
+These fields are NOT orthogonal - they overlap!
+Thus only one field may be written at a time, determined by the 
+most-significant 1 bit in the pattern (the field selector).
+All less significant bits are part of the value of the selected field.
+The fields and their values are grouped together to emphasize this format.
+Field selector macro names end in '_' (implying something more needs
+to be ORed) and the value macros are indented. The pattern written to a
+bitfield is a bitwise OR of a field selector and one or more values, eg.
+  (SPLC780D_INST_ON_ | SPLC780D_INST_ON_DISPLAY | SPLC780D_INST_ON_CURSOR)
+A single bit field (eg. SPCL780D_INST_HOME) need not have a value.
+
+NOTE: Controller requires a software delay after writing to the control
+or data registers. For the data register it is 38us. For the control
+register it is 38us for most bit fields, with the following exceptions:
+    SPLC780D_FUNC_                               100us.
+    SPLC780D_INST_CLEAR, SPLC780D_INST_HOME     1520us.
+For more details and reset timing, see the SUNPLUS SPLC780D data sheet.
+*/
+
+#define SPLC780D_INST_CLEAR_            0x1 /* clear (blank) display) */
+
+#define SPLC780D_INST_HOME_             0x2 /* home cursor and shift pos */
+
+#define SPLC780D_INST_ENTRY_            0x4 /* combine *ENTRY_* flags below */
+#define     SPLC780D_INST_ENTRY_SHIFT   0x1 /* display shift on entry / not */
+#define     SPLC780D_INST_ENTRY_INCR    0x2 /* cursor incr / decr */
+#define     SPLC780D_INST_ENTRY_DECR      0 /* cursor incr / decr */
+
+#define SPLC780D_INST_ON_               0x8     /* combine *ON_* flags below */
+#define     SPLC780D_INST_ON_DISPLAY    0x4 /* display on / off */
+#define     SPLC780D_INST_ON_CURSOR     0x2 /* cursor  on / off */
+#define     SPLC780D_INST_ON_BLINK      0x1 /* blink   on / off */
+
+#define SPLC780D_INST_SHIFT_           0x10 /* combine *SHIFT_* flags below */
+#define     SPLC780D_INST_SHIFT_DISP    0x8 /* shift display / move cursor */
+#define     SPLC780D_INST_SHIFT_CURS      0 /* shift display / move cursor */
+#define     SPLC780D_INST_SHIFT_RIGHT   0x4 /* shift right / left */
+#define     SPLC780D_INST_SHIFT_LEFT      0 /* shift right / left */
+
+#define SPLC780D_INST_FUNC_            0x20 /* combine *FUNC_* flags below */
+#define     SPLC780D_INST_FUNC_8BIT    0x10 /* data length 8 bit / 4 bit */
+#define     SPLC780D_INST_FUNC_4BIT       0 /* data length 8 bit / 4 bit */
+#define     SPLC780D_INST_FUNC_2LINE   0x08 /* display lines 2 / 1 */
+#define     SPLC780D_INST_FUNC_1LINE      0 /* display lines 2 / 1 */
+#define     SPLC780D_INST_FUNC_F5x10   0x04 /* character font 5x10 / 5x8 */
+#define     SPLC780D_INST_FUNC_F5x8       0 /* character font 5x10 / 5x8 */
+                                            /* font must be 5x8 for 2 lines */
+#define SPLC780D_INST_CGEN_            0x40 /* set char generator address */
+#define     SPLC780D_INST_CGEN_ADDR    0x3F /*   to address in this field */
+#define SPLC780D_INST_DRAM_            0x80 /* set display data RAM address */
+#define     SPLC780D_INST_DRAM_ADDR    0x7F /*   to address in this field */
+#define     SPLC780D_INST_DRAM_LINE2   0x40 /* address offset to line 2 */
+/* Controller limits */
+#define SPLC780D_RAMLEN_1LINE          0x50 /* length of line in RAM (1 line) */
+#define SPLC780D_RAMLEN_2LINE          0x28 /* length of line in RAM (2 line) */
+
+
+#ifndef __ASSEMBLER__
+
+/* C interface to controller registers. */
+struct splc780d_s {
+    splc780d_reg_t  inst;       /* instruction register */
+    splc780d_reg_t  data;       /* data register */
+};
+
+typedef volatile struct splc780d_s splc780d_t;
+
+/*
+Prototypes of high level driver functions.
+*/
+
+/*
+Initialize the display with the FUNC_, ENTRY_ and ON_ fields as specified in 
+terms of the values above. The splc780d_init_default() macro is an example.
+*/
+extern void splc780d_init(splc780d_t *lcd,
+                          unsigned func, unsigned entry, unsigned on);
+
+/*
+Initialize the display to default mode: 8-bit interface, 2 line, 5x8 font, 
+increment cursor on entry, display on (cursor and blinking off).
+*/
+#define splc780d_init_default(lcd) \
+    splc780d_init( lcd, \
+            SPLC780D_INST_FUNC_8BIT \
+            | SPLC780D_INST_FUNC_2LINE \
+            | SPLC780D_INST_FUNC_F5x8, \
+            SPLC780D_INST_ENTRY_INCR, \
+            SPLC780D_INST_ON_DISPLAY \
+            )
+
+/*
+Write a single character at a given position (chars from left, starting at 0).
+Wait long enough afterward for the controller to be ready for more input.
+Positions beyond the end of the display are ignored.
+*/
+extern void splc780d_write_char(splc780d_t *lcd, unsigned pos, const char c);
+
+/*
+Write a string to the display starting at the left (position 0). 
+Blank-pad to or truncate at the end of the display (overwrites any previous 
+string so don't need to blank the display first).
+Wait long enough after each char for the controller to be ready for more input.
+*/
+extern void splc780d_write_string(splc780d_t *lcd, const char *s);
+
+/*
+Blank (clear) the entire display.
+Wait long enough afterward for the controller to be ready for more input.
+*/
+extern void splc780d_blank(splc780d_t *lcd);
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* _LCD_SPLC780D_H_ */
+

components/esp32/include/xtensa/overlay.h

@@ -0,0 +1,184 @@
+// overlay.h -- Overlay manager header file
+// $Id$
+
+// Copyright (c) 2013 Tensilica Inc.
+//
+// Permission is hereby granted, free of charge, to any person obtaining
+// a copy of this software and associated documentation files (the
+// "Software"), to deal in the Software without restriction, including
+// without limitation the rights to use, copy, modify, merge, publish,
+// distribute, sublicense, and/or sell copies of the Software, and to
+// permit persons to whom the Software is furnished to do so, subject to
+// the following conditions:
+//
+// The above copyright notice and this permission notice shall be included
+// in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+
+
+#ifndef OVERLAY_H
+#define OVERLAY_H
+
+
+#include <xtensa/xtruntime.h>
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// Define this to turn off overlay support
+#ifdef XT_DISABLE_OVERLAYS
+
+#define OVERLAY(n)
+#define DECLARE_OVERLAY(n)
+
+#define xt_overlay_map(ov_id)
+#define xt_overlay_map_async(ov_id)                 0
+#define xt_overlay_map_in_progress()                0
+#define xt_overlay_get_id()                         0
+#define xt_overlay_get_state(pc)                    0
+#define xt_overlay_check_map(pc,ps,ovstate,sp)      0
+
+#else
+
+// Shorthand for convenience and portability.
+#define OVERLAY(n)  __attribute__((overlay(n)))
+
+// Structure of the overlay table required by gdb and the overlay
+// manager. Should not be accessed by user code unless overriding
+// the load process.
+struct ovly_table {
+    void *        vma;    // The overlay's mapped address.
+    unsigned int  size;   // The size of the overlay, in bytes.
+    void *        lma;    // The overlay's load address.
+    unsigned int  mapped; // Non-zero if overlay is currently mapped; zero otherwise.
+};
+
+// Constructed by the linker. Required for gdb and for the overlay
+// manager. Should not be accessed by user code unless overriding
+// the load process.
+extern struct ovly_table _ovly_table[];
+
+// Functions.
+void xt_overlay_map(int ov_id);
+int  xt_overlay_map_async(int ov_id);
+int  xt_overlay_map_in_progress(void);
+unsigned int xt_overlay_get_state(unsigned int pc);
+unsigned int xt_overlay_check_map(unsigned int * pc, unsigned int * ps,
+                                  unsigned int ovstate, unsigned int sp);
+int  xt_overlay_start_map(void * dst, void * src, unsigned int len, int ov_id);
+int  xt_overlay_is_mapping(int ov_id);
+void xt_overlay_fatal_error(int ov_id);
+
+
+// Returns the current overlay ID. If no overlay is mapped or an overlay
+// is in the middle of being mapped, returns -1. Inlined to avoid calling
+// out of overlay (wastes cycles, can end up reading wrong ID on interrupt
+// activity).
+//
+static inline int xt_overlay_get_id(void)
+{
+#pragma always_inline
+extern short _mapping_id;
+extern short _ovly_id;
+
+    int ret;
+    unsigned int flags = XTOS_SET_INTLEVEL(15);
+
+    if (_mapping_id >= 0) {
+        ret = -1;
+    }
+    else {
+        ret = _ovly_id;
+    }
+
+    XTOS_RESTORE_INTLEVEL(flags);
+    return ret;
+}
+
+
+// The following macros are used to declare numbered overlays and generate
+// the corresponding call stubs. Use as follows:
+//
+//    DECLARE_OVERLAY(n)
+//
+// See documentation for more details.
+
+//#include <xtensa/config/core-isa.h>
+
+// At this time overlays are not supported without windowing.
+#if defined(__XTENSA_WINDOWED_ABI__)
+
+#define xstr(x)   str(x)
+#define str(x)    #x
+
+// At entry, register a8 holds the return address and a9 holds the target
+// function address. This stub saves a8 on the stack at (SP - 20) which
+// is the only location that is safe for us to use. Then it allocates 32
+// bytes on the stack for working storage, loads the overlay number into
+// a8, and jumps to the common handler. The common handler will make sure
+// that the called function is loaded into memory before calling it.
+// NOTE: we are using the stack area normally reserved for nested functions.
+// This means nested functions cannot be used when overlays are in use.
+
+#define CALL_IN(num) \
+    asm(".section .gnu.linkonce.t.overlay.call." xstr(num) ".text, \"ax\"\n" \
+        ".global  _overlay_call_in_" xstr(num)  "_\n" \
+        ".align   4\n" \
+        "_overlay_call_in_" xstr(num) "_:\n" \
+        "s32e    a8, a1, -20\n" \
+        "addi    a8, a1, -32\n" \
+        "movsp   a1, a8\n" \
+        "movi    a8, " xstr(num) "\n" \
+        "j       _overlay_call_in_common\n" \
+        ".size   _overlay_call_in_" xstr(num) "_, . - _overlay_call_in_" xstr(num) "_\n");
+
+// The call-out stub first calls the target function, then loads the overlay
+// number into register a14 and jumps to the common handler. The handler will
+// make sure that the caller function is present in memory before returning.
+// Note that registers a10-a13 may contain return values so must be preserved.
+//
+// Because we came here via a call4, the return address is in a4, and the top
+// 2 bits are set to the window increment. We'll restore the top 2 bits of
+// the return address from the called function's address, assuming that both
+// are in the same 1 GB segment. For now this is always true.
+
+#define CALL_OUT(num) \
+    asm(".section .gnu.linkonce.t.overlay.call." xstr(num) ".text, \"ax\"\n" \
+        ".global  _overlay_call_out_" xstr(num) "_\n" \
+        ".align   4\n" \
+        "_overlay_call_out_" xstr(num) "_:\n" \
+        "slli    a4, a4, 2\n" \
+        "srli    a4, a4, 2\n" \
+        "extui   a8, a9, 30, 2\n" \
+        "slli    a8, a8, 30\n" \
+        "or      a4, a4, a8\n" \
+        "callx8  a9\n" \
+        "movi    a14, " xstr(num) "\n" \
+        "j       _overlay_call_out_common\n" \
+        ".size   _overlay_call_out_" xstr(num) "_, . - _overlay_call_out_" xstr(num) "_\n");
+
+// Generate a call-in and a call-out stub for each overlay.
+
+#define DECLARE_OVERLAY(num) \
+    CALL_IN(num) \
+    CALL_OUT(num)
+
+#endif // defined(__XTENSA_WINDOWED_ABI__)
+
+#endif // XT_DISABLE_OVERLAYS
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // OVERLAY_H
+

components/esp32/include/xtensa/overlay_os_asm.h

@@ -0,0 +1,140 @@
+// overlay_os_asm.h -- Overlay manager assembly macros for OS use.
+// $Id$
+
+// Copyright (c) 2013 Tensilica Inc.
+//
+// Permission is hereby granted, free of charge, to any person obtaining
+// a copy of this software and associated documentation files (the
+// "Software"), to deal in the Software without restriction, including
+// without limitation the rights to use, copy, modify, merge, publish,
+// distribute, sublicense, and/or sell copies of the Software, and to
+// permit persons to whom the Software is furnished to do so, subject to
+// the following conditions:
+//
+// The above copyright notice and this permission notice shall be included
+// in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+
+
+#ifndef OVERLAY_OS_ASM_H
+#define OVERLAY_OS_ASM_H
+
+// The macros in here are intended to be used by RTOS task switch code
+// to check overlay status. Such code is usually in assembly and cannot
+// call C code without penalty. For C code usage, it is best to use the
+// corresponding C functions from the library.
+
+
+// Inline assembly version of xt_overlay_get_state(). The arguments are
+// three AR registers (a0-a15):
+//
+// "pcreg" - should contain the outgoing task's PC, i.e. the point at
+//           which the task got interrupted. The return value is also
+//           returned in this register.
+// "sr1/2" - Scratch registers. These must be distinct from "pcreg".
+//
+// The return value is a 32-bit result that should be saved with the
+// task context and passed as-is to xt_overlay_check_map.
+
+        .macro _xt_overlay_get_state    pcreg  sr1  sr2
+
+        movi    \sr1, _mapping_id
+        movi    \sr2, _ovly_id
+        l16si   \sr1, \sr1, 0
+        l16ui   \sr2, \sr2, 0
+        slli    \sr1, \sr1, 16
+        or      \pcreg, \sr1, \sr2
+
+        .endm
+
+
+// Inline assembly version of xt_overlay_check_map(). It requires 5 AR
+// registers (a0-a15) as arguments.
+//
+// "pcreg" - should contain the interrupted task's PC, i.e. the point
+//           at which the task got interrupted. This will be adjusted
+//           if required.
+// "psreg" - should contain the interrupted task's PS. This will be
+//           adjusted if required.
+// "ovreg" - should contain the overlay state on entry. Contents may
+//           be clobbered.
+// "spreg" - should contain the tasks stack pointer on entry.
+// "sr1"   - Scratch register. Must be distinct from any of the above.
+//
+// The return values are "pcreg" and "psreg" and these must be used
+// to update the task's PC and PS.
+// Note that this macro may store data below the "spreg" pointer. If
+// it does, then it will also disable interrupts via the PS, so that
+// the task resumes with all interrupts disabled (to avoid corrupting
+// this data).
+//
+// (SP - 24)    Overlay ID to restore
+// (SP - 28)    Task PC
+// (SP - 32)    Task PS
+
+        .macro _xt_overlay_check_map    pcreg  psreg ovreg  spreg  sr1
+
+// There are four cases to deal with:
+//
+// _ovly_id = -1, _mapping_id = -1
+// No overlay is mapped or mapping, nothing to do.
+//
+// _ovly_id >= 0, _mapping_id = -1
+// An overlay was mapped, check PC to see if we need a restore.
+//
+// _ovly_id = -1, _mapping_id >= 0
+// An overlay is being mapped. Either it belongs to this task, which
+// implies that the PC is in the mapping function, or it does not 
+// belong to this task. Either way there is nothing to do.
+//
+// _ovly_id >= 0, _mapping_id >= 0
+// Illegal, cannot happen by design. Don't need to handle this.
+//
+// So, the logic is to check _ovly_id first. If this is >= 0, then
+// we check the task PC. If the PC is in the regions of interest then
+// we'll patch the return PC to invoke xt_overlay_restore.
+
+.L1:
+        extui   \sr1, \ovreg, 0, 16             // Extract _ovly_id
+        bbsi.l  \sr1, 15, .Lno                  // If -1 then we're done
+        mov     \ovreg, \sr1                    // Restore this one
+
+// Next check the PC to see if it falls within the ranges of interest.
+
+.L2:
+        movi    \sr1, _overlay_vma              // Is PC < VMA range ?
+        bltu    \pcreg, \sr1, .L3
+        movi    \sr1, _overlay_vma_end          // Is PC > VMA range ?
+        bgeu    \pcreg, \sr1, .L3
+        j       .L4                             // PC is in VMA range
+.L3:
+        movi    \sr1, _overlay_call_stubs_start // Is PC < call stubs range ?
+        bltu    \pcreg, \sr1, .Lno
+        movi    \sr1, _overlay_call_stubs_end   // Is PC > call stubs range ?
+        bgeu    \pcreg, \sr1, .Lno
+
+// If we get here then a restore is needed. Save the overlay ID, PC and PS.
+// Return modified PC and PS so that xt_overlay_restore() will execute in
+// the context of the task when resumed. Note that the OS resumption code
+// may expect PS.EXCM to be set so we leave it as is in the return value.
+
+.L4:
+        s32e    \ovreg, \spreg, -24             // Save overlay ID
+        s32e    \pcreg, \spreg, -28             // Save task PC
+        s32e    \psreg, \spreg, -32             // Save task PS
+        movi    \pcreg, xt_overlay_restore      // Adjust resumption PC
+        movi    \sr1, 15
+        or      \psreg, \psreg, \sr1            // Set intlevel to highest
+.Lno:
+
+        .endm
+
+#endif // OVERLAY_OS_ASM_H
+

components/esp32/include/xtensa/sim.h

@@ -0,0 +1,60 @@
+/* Copyright (c) 2004-2006 by Tensilica Inc.  ALL RIGHTS RESERVED.
+/  These coded instructions, statements, and computer programs are the
+/  copyrighted works and confidential proprietary information of Tensilica Inc.
+/  They may not be modified, copied, reproduced, distributed, or disclosed to
+/  third parties in any manner, medium, or form, in whole or in part, without
+/  the prior written consent of Tensilica Inc.
+*/
+
+/*  sim.h 
+ *
+ *  Definitions and prototypes for specific ISS SIMCALLs
+ *  (ie. outside the standard C library).
+ */
+
+#ifndef _INC_SIM_H_
+#define _INC_SIM_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Shortcuts for enabling/disabling profiling in the Xtensa ISS  */
+extern void xt_iss_profile_enable(void);
+extern void xt_iss_profile_disable(void);
+
+/* Shortcut for setting the trace level in the Xtensa ISS */
+extern void xt_iss_trace_level(unsigned level);
+
+/* Generic interface for passing client commands in the Xtensa ISS:
+ *   returns 0 on success, -1 on failure.
+ */
+extern int xt_iss_client_command(const char *client, const char *command);
+
+/* Interface for switching simulation modes in the Xtensa ISS:
+ *   returns 0 on success, -1 on failure.
+ */
+#define XT_ISS_CYCLE_ACCURATE 0
+#define XT_ISS_FUNCTIONAL     1
+extern int xt_iss_switch_mode(int mode);
+
+
+/* Interface for waiting on a system synchronization event */
+extern void xt_iss_event_wait(unsigned event_id);
+
+/* Interface for firing a system synchronization event */
+extern void xt_iss_event_fire(unsigned event_id);
+
+/* Interface for invoking a user simcall action,
+ * which can be registered in XTMP or XTSC.
+ */
+extern int xt_iss_simcall(int arg1, int arg2, int arg3,
+                          int arg4, int arg5, int arg6);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*_INC_SIM_H_*/
+

components/esp32/include/xtensa/simboard.h

@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2001 Tensilica Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/*  simboard.h  -  Xtensa ISS "Board" specific definitions  */
+
+#ifndef _INC_SIMBOARD_H_
+#define _INC_SIMBOARD_H_
+
+#include <xtensa/config/core.h>
+#include <xtensa/config/system.h>
+
+
+/*
+ *  Device addresses.
+ */
+
+/*  System ROM:  */
+#define XTBOARD_ROM_SIZE		XSHAL_ROM_SIZE
+#ifdef XSHAL_ROM_VADDR
+#define XTBOARD_ROM_VADDR	XSHAL_ROM_VADDR
+#endif
+#ifdef XSHAL_ROM_PADDR
+#define XTBOARD_ROM_PADDR	XSHAL_ROM_PADDR
+#endif
+
+/*  System RAM:  */
+#define XTBOARD_RAM_SIZE		XSHAL_RAM_SIZE
+#ifdef XSHAL_RAM_VADDR
+#define XTBOARD_RAM_VADDR	XSHAL_RAM_VADDR
+#endif
+#ifdef XSHAL_RAM_PADDR
+#define XTBOARD_RAM_PADDR	XSHAL_RAM_PADDR
+#endif
+
+
+/*
+ *  Things that depend on device addresses.
+ */
+
+#define XTBOARD_CACHEATTR_WRITEBACK	XSHAL_ISS_CACHEATTR_WRITEBACK
+#define XTBOARD_CACHEATTR_WRITEALLOC	XSHAL_ISS_CACHEATTR_WRITEALLOC
+#define XTBOARD_CACHEATTR_WRITETHRU	XSHAL_ISS_CACHEATTR_WRITETHRU
+#define XTBOARD_CACHEATTR_BYPASS	XSHAL_ISS_CACHEATTR_BYPASS
+#define XTBOARD_CACHEATTR_DEFAULT	XSHAL_ISS_CACHEATTR_DEFAULT
+
+#define XTBOARD_BUSINT_PIPE_REGIONS	0
+#define XTBOARD_BUSINT_SDRAM_REGIONS	0
+
+
+#endif /*_INC_SIMBOARD_H_*/
+