Merge branch 'change/delete_not_used_mmu_macros' into 'master'

mm: delete not used mmu macros and added soc_ prefix

Closes IDF-7686

See merge request espressif/esp-idf!25663

components/bootloader_support/bootloader_flash/src/bootloader_flash.c

@@ -151,9 +151,9 @@ static const char *TAG = "bootloader_flash";
 #define MMU_BLOCK0_VADDR  SOC_DROM_LOW
 #if CONFIG_IDF_TARGET_ESP32P4
 //TODO: IDF-7918
-#define MMAP_MMU_SIZE     (DRAM_FLASH_ADDRESS_HIGH - DRAM_FLASH_ADDRESS_LOW) // This mmu size means that the mmu size to be mapped
+#define MMAP_MMU_SIZE     (SOC_DRAM_FLASH_ADDRESS_HIGH - SOC_DRAM_FLASH_ADDRESS_LOW) // This mmu size means that the mmu size to be mapped
 #else
-#define MMAP_MMU_SIZE     (DRAM0_CACHE_ADDRESS_HIGH - DRAM0_CACHE_ADDRESS_LOW) // This mmu size means that the mmu size to be mapped
+#define MMAP_MMU_SIZE     (SOC_DRAM0_CACHE_ADDRESS_HIGH - SOC_DRAM0_CACHE_ADDRESS_LOW) // This mmu size means that the mmu size to be mapped
 #endif
 #define MMU_BLOCK63_VADDR (MMU_BLOCK0_VADDR + MMAP_MMU_SIZE - SPI_FLASH_MMU_PAGE_SIZE)
 #define FLASH_READ_VADDR MMU_BLOCK63_VADDR

components/esp_mm/port/esp32/ext_mem_layout.c

@@ -18,7 +18,7 @@ const mmu_mem_region_t g_mmu_mem_regions[SOC_MMU_LINEAR_ADDRESS_REGION_NUM] = {
     [0] = {
         .start = SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW,
         .end = SOC_MMU_IRAM0_LINEAR_ADDRESS_HIGH,
-        .size = BUS_SIZE(SOC_MMU_IRAM0_LINEAR),
+        .size = SOC_BUS_SIZE(SOC_MMU_IRAM0_LINEAR),
         .bus_id = CACHE_BUS_IBUS0,
         .targets = MMU_TARGET_FLASH0,
         .caps = MMU_MEM_CAP_EXEC | MMU_MEM_CAP_32BIT,
@@ -26,7 +26,7 @@ const mmu_mem_region_t g_mmu_mem_regions[SOC_MMU_LINEAR_ADDRESS_REGION_NUM] = {
     [1] = {
         .start = SOC_MMU_DROM0_LINEAR_ADDRESS_LOW,
         .end = SOC_MMU_DROM0_LINEAR_ADDRESS_HIGH,
-        .size = BUS_SIZE(SOC_MMU_DROM0_LINEAR),
+        .size = SOC_BUS_SIZE(SOC_MMU_DROM0_LINEAR),
         .bus_id = CACHE_BUS_DBUS0,
         .targets = MMU_TARGET_FLASH0,
         .caps = MMU_MEM_CAP_READ | MMU_MEM_CAP_32BIT | MMU_MEM_CAP_8BIT,
@@ -34,7 +34,7 @@ const mmu_mem_region_t g_mmu_mem_regions[SOC_MMU_LINEAR_ADDRESS_REGION_NUM] = {
     [2] = {
         .start = SOC_MMU_DRAM1_LINEAR_ADDRESS_LOW,
         .end = SOC_MMU_DRAM1_LINEAR_ADDRESS_HIGH,
-        .size = BUS_SIZE(SOC_MMU_DRAM1_LINEAR),
+        .size = SOC_BUS_SIZE(SOC_MMU_DRAM1_LINEAR),
         .bus_id = CACHE_BUS_DBUS1,
         .targets = MMU_TARGET_PSRAM0,
         .caps = MMU_MEM_CAP_READ | MMU_MEM_CAP_WRITE | MMU_MEM_CAP_32BIT | MMU_MEM_CAP_8BIT,

components/esp_mm/port/esp32c2/ext_mem_layout.c

@@ -17,7 +17,7 @@ const mmu_mem_region_t g_mmu_mem_regions[SOC_MMU_LINEAR_ADDRESS_REGION_NUM] = {
     [0] = {
         .start = SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW,
         .end = SOC_MMU_IRAM0_LINEAR_ADDRESS_HIGH,
-        .size = BUS_SIZE(SOC_MMU_IRAM0_LINEAR),
+        .size = SOC_BUS_SIZE(SOC_MMU_IRAM0_LINEAR),
         .bus_id = CACHE_BUS_IBUS0 | CACHE_BUS_DBUS0,
         .targets = MMU_TARGET_FLASH0,
         .caps = MMU_MEM_CAP_EXEC | MMU_MEM_CAP_READ | MMU_MEM_CAP_32BIT | MMU_MEM_CAP_8BIT,

components/esp_mm/port/esp32c3/ext_mem_layout.c

@@ -17,7 +17,7 @@ const mmu_mem_region_t g_mmu_mem_regions[SOC_MMU_LINEAR_ADDRESS_REGION_NUM] = {
     [0] = {
         .start = SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW,
         .end = SOC_MMU_IRAM0_LINEAR_ADDRESS_HIGH,
-        .size = BUS_SIZE(SOC_MMU_IRAM0_LINEAR),
+        .size = SOC_BUS_SIZE(SOC_MMU_IRAM0_LINEAR),
         .bus_id = CACHE_BUS_IBUS0 | CACHE_BUS_DBUS0,
         .targets = MMU_TARGET_FLASH0,
         .caps = MMU_MEM_CAP_EXEC | MMU_MEM_CAP_READ | MMU_MEM_CAP_32BIT | MMU_MEM_CAP_8BIT,

components/esp_mm/port/esp32c6/ext_mem_layout.c

@@ -18,7 +18,7 @@ const mmu_mem_region_t g_mmu_mem_regions[SOC_MMU_LINEAR_ADDRESS_REGION_NUM] = {
     [0] = {
         .start = SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW,
         .end = SOC_MMU_IRAM0_LINEAR_ADDRESS_HIGH,
-        .size = BUS_SIZE(SOC_MMU_IRAM0_LINEAR),
+        .size = SOC_BUS_SIZE(SOC_MMU_IRAM0_LINEAR),
         .bus_id = CACHE_BUS_IBUS0 | CACHE_BUS_DBUS0,
         .targets = MMU_TARGET_FLASH0,
         .caps = MMU_MEM_CAP_EXEC | MMU_MEM_CAP_READ | MMU_MEM_CAP_32BIT | MMU_MEM_CAP_8BIT,

components/esp_mm/port/esp32h2/ext_mem_layout.c

@@ -18,7 +18,7 @@ const mmu_mem_region_t g_mmu_mem_regions[SOC_MMU_LINEAR_ADDRESS_REGION_NUM] = {
     [0] = {
         .start = SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW,
         .end = SOC_MMU_IRAM0_LINEAR_ADDRESS_HIGH,
-        .size = BUS_SIZE(SOC_MMU_IRAM0_LINEAR),
+        .size = SOC_BUS_SIZE(SOC_MMU_IRAM0_LINEAR),
         .bus_id = CACHE_BUS_IBUS0 | CACHE_BUS_DBUS0,
         .targets = MMU_TARGET_FLASH0,
         .caps = MMU_MEM_CAP_EXEC | MMU_MEM_CAP_READ | MMU_MEM_CAP_32BIT | MMU_MEM_CAP_8BIT,

components/esp_mm/port/esp32p4/ext_mem_layout.c

@@ -18,7 +18,7 @@ const mmu_mem_region_t g_mmu_mem_regions[SOC_MMU_LINEAR_ADDRESS_REGION_NUM] = {
     [0] = {
         .start = SOC_MMU_FLASH_LINEAR_ADDRESS_LOW,
         .end = SOC_MMU_FLASH_LINEAR_ADDRESS_HIGH,
-        .size = BUS_SIZE(SOC_MMU_FLASH_LINEAR),
+        .size = SOC_BUS_SIZE(SOC_MMU_FLASH_LINEAR),
         .bus_id = CACHE_BUS_IBUS0 | CACHE_BUS_DBUS0,
         .targets = MMU_TARGET_FLASH0,
         .caps = MMU_MEM_CAP_EXEC | MMU_MEM_CAP_READ | MMU_MEM_CAP_WRITE | MMU_MEM_CAP_32BIT | MMU_MEM_CAP_8BIT,
@@ -26,7 +26,7 @@ const mmu_mem_region_t g_mmu_mem_regions[SOC_MMU_LINEAR_ADDRESS_REGION_NUM] = {
     [1] = {
         .start = SOC_MMU_PSRAM_LINEAR_ADDRESS_LOW,
         .end = SOC_MMU_PSRAM_LINEAR_ADDRESS_HIGH,
-        .size = BUS_SIZE(SOC_MMU_PSRAM_LINEAR),
+        .size = SOC_BUS_SIZE(SOC_MMU_PSRAM_LINEAR),
         .bus_id = CACHE_BUS_IBUS1 | CACHE_BUS_DBUS1,
         .targets = MMU_TARGET_PSRAM0,
         .caps = MMU_MEM_CAP_EXEC | MMU_MEM_CAP_READ | MMU_MEM_CAP_WRITE | MMU_MEM_CAP_32BIT | MMU_MEM_CAP_8BIT,

components/esp_mm/port/esp32s2/ext_mem_layout.c

@@ -18,7 +18,7 @@ const mmu_mem_region_t g_mmu_mem_regions[SOC_MMU_LINEAR_ADDRESS_REGION_NUM] = {
     [0] = {
         .start = SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW,
         .end = SOC_MMU_IRAM0_LINEAR_ADDRESS_HIGH,
-        .size = BUS_SIZE(SOC_MMU_IRAM0_LINEAR),
+        .size = SOC_BUS_SIZE(SOC_MMU_IRAM0_LINEAR),
         .bus_id = CACHE_BUS_IBUS0,
         .targets = MMU_TARGET_FLASH0 | MMU_TARGET_PSRAM0,
         .caps = MMU_MEM_CAP_EXEC | MMU_MEM_CAP_32BIT,
@@ -26,7 +26,7 @@ const mmu_mem_region_t g_mmu_mem_regions[SOC_MMU_LINEAR_ADDRESS_REGION_NUM] = {
     [1] = {
         .start = SOC_MMU_DROM0_LINEAR_ADDRESS_LOW,
         .end = SOC_MMU_DROM0_LINEAR_ADDRESS_HIGH,
-        .size = BUS_SIZE(SOC_MMU_DROM0_LINEAR),
+        .size = SOC_BUS_SIZE(SOC_MMU_DROM0_LINEAR),
         .bus_id = CACHE_BUS_IBUS2,
         .targets = MMU_TARGET_FLASH0 | MMU_TARGET_PSRAM0,
         .caps = MMU_MEM_CAP_READ | MMU_MEM_CAP_32BIT | MMU_MEM_CAP_8BIT,
@@ -34,7 +34,7 @@ const mmu_mem_region_t g_mmu_mem_regions[SOC_MMU_LINEAR_ADDRESS_REGION_NUM] = {
     [2] = {
         .start = SOC_MMU_DPORT_LINEAR_ADDRESS_LOW,
         .end = SOC_MMU_DPORT_LINEAR_ADDRESS_HIGH,
-        .size = BUS_SIZE(SOC_MMU_DPORT_LINEAR),
+        .size = SOC_BUS_SIZE(SOC_MMU_DPORT_LINEAR),
         .bus_id = CACHE_BUS_DBUS2,
         .targets = MMU_TARGET_FLASH0 | MMU_TARGET_PSRAM0,
         .caps = MMU_MEM_CAP_READ | MMU_MEM_CAP_WRITE | MMU_MEM_CAP_32BIT,
@@ -42,7 +42,7 @@ const mmu_mem_region_t g_mmu_mem_regions[SOC_MMU_LINEAR_ADDRESS_REGION_NUM] = {
     [3] = {
         .start = SOC_MMU_DRAM1_LINEAR_ADDRESS_LOW,
         .end = SOC_MMU_DRAM1_LINEAR_ADDRESS_HIGH,
-        .size = BUS_SIZE(SOC_MMU_DRAM1_LINEAR),
+        .size = SOC_BUS_SIZE(SOC_MMU_DRAM1_LINEAR),
         .bus_id = CACHE_BUS_DBUS1,
         .targets = MMU_TARGET_FLASH0 | MMU_TARGET_PSRAM0,
         .caps = MMU_MEM_CAP_READ | MMU_MEM_CAP_WRITE | MMU_MEM_CAP_32BIT | MMU_MEM_CAP_8BIT,
@@ -50,7 +50,7 @@ const mmu_mem_region_t g_mmu_mem_regions[SOC_MMU_LINEAR_ADDRESS_REGION_NUM] = {
     [4] = {
         .start = SOC_MMU_DRAM0_LINEAR_ADDRESS_LOW,
         .end = SOC_MMU_DRAM0_LINEAR_ADDRESS_HIGH,
-        .size = BUS_SIZE(SOC_MMU_DRAM0_LINEAR),
+        .size = SOC_BUS_SIZE(SOC_MMU_DRAM0_LINEAR),
         .bus_id = CACHE_BUS_DBUS0,
         .targets = MMU_TARGET_FLASH0 | MMU_TARGET_PSRAM0,
         .caps = MMU_MEM_CAP_READ | MMU_MEM_CAP_WRITE | MMU_MEM_CAP_32BIT | MMU_MEM_CAP_8BIT,

components/esp_mm/port/esp32s3/ext_mem_layout.c

@@ -17,7 +17,7 @@ const mmu_mem_region_t g_mmu_mem_regions[SOC_MMU_LINEAR_ADDRESS_REGION_NUM] = {
     [0] = {
         .start = SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW,
         .end = SOC_MMU_IRAM0_LINEAR_ADDRESS_HIGH,
-        .size = BUS_SIZE(SOC_MMU_IRAM0_LINEAR),
+        .size = SOC_BUS_SIZE(SOC_MMU_IRAM0_LINEAR),
         .bus_id = CACHE_BUS_IBUS0 | CACHE_BUS_DBUS0,
         .targets = MMU_TARGET_FLASH0 | MMU_TARGET_PSRAM0,
         .caps = MMU_MEM_CAP_EXEC | MMU_MEM_CAP_READ | MMU_MEM_CAP_WRITE | MMU_MEM_CAP_32BIT | MMU_MEM_CAP_8BIT,

components/esp_psram/mmu_psram_flash.c

@@ -73,10 +73,10 @@ esp_err_t mmu_config_psram_text_segment(uint32_t start_page, uint32_t psram_size
     instruction_flash_page_info_init(page_id);
 
 #if CONFIG_IDF_TARGET_ESP32S2
-    page_id = Cache_Flash_To_SPIRAM_Copy(PRO_CACHE_IBUS0, IRAM0_ADDRESS_LOW, page_id, &page0_page);
-    page_id = Cache_Flash_To_SPIRAM_Copy(PRO_CACHE_IBUS1, IRAM1_ADDRESS_LOW, page_id, &page0_page);
+    page_id = Cache_Flash_To_SPIRAM_Copy(PRO_CACHE_IBUS0, SOC_IRAM0_ADDRESS_LOW, page_id, &page0_page);
+    page_id = Cache_Flash_To_SPIRAM_Copy(PRO_CACHE_IBUS1, SOC_IRAM1_ADDRESS_LOW, page_id, &page0_page);
 #elif CONFIG_IDF_TARGET_ESP32S3
-    page_id = Cache_Flash_To_SPIRAM_Copy(CACHE_IBUS, IRAM0_CACHE_ADDRESS_LOW, page_id, &page0_page);
+    page_id = Cache_Flash_To_SPIRAM_Copy(CACHE_IBUS, SOC_IRAM0_CACHE_ADDRESS_LOW, page_id, &page0_page);
 #endif
     ESP_EARLY_LOGV(TAG, "after copy instruction, page_id is %d", page_id);
     ESP_EARLY_LOGI(TAG, "Instructions copied and mapped to SPIRAM");
@@ -118,12 +118,12 @@ esp_err_t mmu_config_psram_rodata_segment(uint32_t start_page, uint32_t psram_si
     rodata_flash_page_info_init(page_id);
 
 #if CONFIG_IDF_TARGET_ESP32S2
-    page_id = Cache_Flash_To_SPIRAM_Copy(PRO_CACHE_IBUS2, DROM0_ADDRESS_LOW, page_id, &page0_page);
-    page_id = Cache_Flash_To_SPIRAM_Copy(PRO_CACHE_DBUS0, DRAM0_ADDRESS_LOW, page_id, &page0_page);
-    page_id = Cache_Flash_To_SPIRAM_Copy(PRO_CACHE_DBUS1, DRAM1_ADDRESS_LOW, page_id, &page0_page);
-    page_id = Cache_Flash_To_SPIRAM_Copy(PRO_CACHE_DBUS2, DPORT_ADDRESS_LOW, page_id, &page0_page);
+    page_id = Cache_Flash_To_SPIRAM_Copy(PRO_CACHE_IBUS2, SOC_DROM0_ADDRESS_LOW, page_id, &page0_page);
+    page_id = Cache_Flash_To_SPIRAM_Copy(PRO_CACHE_DBUS0, SOC_DRAM0_ADDRESS_LOW, page_id, &page0_page);
+    page_id = Cache_Flash_To_SPIRAM_Copy(PRO_CACHE_DBUS1, SOC_DRAM1_ADDRESS_LOW, page_id, &page0_page);
+    page_id = Cache_Flash_To_SPIRAM_Copy(PRO_CACHE_DBUS2, SOC_DPORT_ADDRESS_LOW, page_id, &page0_page);
 #elif CONFIG_IDF_TARGET_ESP32S3
-    page_id = Cache_Flash_To_SPIRAM_Copy(CACHE_DBUS, DRAM0_CACHE_ADDRESS_LOW, page_id, &page0_page);
+    page_id = Cache_Flash_To_SPIRAM_Copy(CACHE_DBUS, SOC_DRAM0_CACHE_ADDRESS_LOW, page_id, &page0_page);
 #endif
 
     ESP_EARLY_LOGV(TAG, "after copy rodata, page_id is %d", page_id);
@@ -162,13 +162,13 @@ void instruction_flash_page_info_init(uint32_t psram_start_physical_page)
 {
 #if CONFIG_IDF_TARGET_ESP32S2
     uint32_t instr_page_cnt = ((uint32_t)&_instruction_reserved_end - (uint32_t)&_instruction_reserved_start + MMU_PAGE_SIZE - 1) / MMU_PAGE_SIZE;
-    uint32_t instr_mmu_offset = ((uint32_t)&_instruction_reserved_start & MMU_VADDR_MASK) / MMU_PAGE_SIZE;
+    uint32_t instr_mmu_offset = ((uint32_t)&_instruction_reserved_start & SOC_MMU_VADDR_MASK) / MMU_PAGE_SIZE;
     instr_start_page = ((volatile uint32_t *)(DR_REG_MMU_TABLE + PRO_CACHE_IBUS0_MMU_START))[instr_mmu_offset];
 #elif CONFIG_IDF_TARGET_ESP32S3
     uint32_t instr_page_cnt = ((uint32_t)&_instruction_reserved_end - SOC_IROM_LOW + MMU_PAGE_SIZE - 1) / MMU_PAGE_SIZE;
     instr_start_page = *((volatile uint32_t *)(DR_REG_MMU_TABLE + CACHE_IROM_MMU_START));
 #endif
-    instr_start_page &= MMU_VALID_VAL_MASK;
+    instr_start_page &= SOC_MMU_VALID_VAL_MASK;
     instr_end_page = instr_start_page + instr_page_cnt - 1;
     instr_flash2spiram_offs = instr_start_page - psram_start_physical_page;
     instruction_in_spiram = 1;
@@ -215,13 +215,13 @@ void rodata_flash_page_info_init(uint32_t psram_start_physical_page)
 {
 #if CONFIG_IDF_TARGET_ESP32S2
     uint32_t rodata_page_cnt = ((uint32_t)&_rodata_reserved_end - (uint32_t)&_rodata_reserved_start + MMU_PAGE_SIZE - 1) / MMU_PAGE_SIZE;
-    uint32_t rodata_mmu_offset = ((uint32_t)&_rodata_reserved_start & MMU_VADDR_MASK) / MMU_PAGE_SIZE;
+    uint32_t rodata_mmu_offset = ((uint32_t)&_rodata_reserved_start & SOC_MMU_VADDR_MASK) / MMU_PAGE_SIZE;
     rodata_start_page = ((volatile uint32_t *)(DR_REG_MMU_TABLE + PRO_CACHE_IBUS2_MMU_START))[rodata_mmu_offset];
 #elif CONFIG_IDF_TARGET_ESP32S3
     uint32_t rodata_page_cnt = ((uint32_t)&_rodata_reserved_end - ((uint32_t)&_rodata_reserved_start & ~ (MMU_PAGE_SIZE - 1)) + MMU_PAGE_SIZE - 1) / MMU_PAGE_SIZE;
     rodata_start_page = *(volatile uint32_t *)(DR_REG_MMU_TABLE + CACHE_DROM_MMU_START);
 #endif
-    rodata_start_page &= MMU_VALID_VAL_MASK;
+    rodata_start_page &= SOC_MMU_VALID_VAL_MASK;
     rodata_end_page = rodata_start_page + rodata_page_cnt - 1;
     rodata_flash2spiram_offs = rodata_start_page - psram_start_physical_page;
     rodata_in_spiram = 1;

components/esp_rom/include/esp32c6/rom/cache.h

@@ -602,7 +602,7 @@ uint32_t Cache_Get_DROM_MMU_End(void);
 void Cache_Set_IDROM_MMU_Size(uint32_t irom_size, uint32_t drom_size);
 
 #define Cache_Dbus_MMU_Set(ext_ram, vaddr, paddr, psize, num, fixed) \
-    Cache_MSPI_MMU_Set(ets_efuse_cache_encryption_enabled() ? MMU_SENSITIVE : 0, ext_ram, vaddr, paddr, psize, num, fixed)
+    Cache_MSPI_MMU_Set(ets_efuse_cache_encryption_enabled() ? SOC_MMU_SENSITIVE : 0, ext_ram, vaddr, paddr, psize, num, fixed)
 
 #ifdef __cplusplus
 }

components/esp_rom/include/esp32h2/rom/cache.h

@@ -605,7 +605,7 @@ uint32_t Cache_Get_DROM_MMU_End(void);
 void Cache_Set_IDROM_MMU_Size(uint32_t irom_size, uint32_t drom_size);
 
 #define Cache_Dbus_MMU_Set(ext_ram, vaddr, paddr, psize, num, fixed) \
-    Cache_MSPI_MMU_Set(ets_efuse_cache_encryption_enabled() ? MMU_SENSITIVE : 0, ext_ram, vaddr, paddr, psize, num, fixed)
+    Cache_MSPI_MMU_Set(ets_efuse_cache_encryption_enabled() ? SOC_MMU_SENSITIVE : 0, ext_ram, vaddr, paddr, psize, num, fixed)
 
 #ifdef __cplusplus
 }

components/esp_rom/include/esp32s3/rom/cache.h

@@ -224,7 +224,7 @@ void Cache_MMU_Init(void);
   * @brief Set ICache mmu mapping.
   *        Please do not call this function in your SDK application.
   *
-  * @param  uint32_t ext_ram : MMU_ACCESS_FLASH for flash, MMU_ACCESS_SPIRAM for spiram, MMU_INVALID for invalid.
+  * @param  uint32_t ext_ram : SOC_MMU_ACCESS_FLASH for flash, SOC_MMU_ACCESS_SPIRAM for spiram, SOC_MMU_INVALID for invalid.
   *
   * @param  uint32_t vaddr : virtual address in CPU address space.
   *                              Can be Iram0,Iram1,Irom0,Drom0 and AHB buses address.
@@ -251,7 +251,7 @@ int Cache_Ibus_MMU_Set(uint32_t ext_ram, uint32_t vaddr, uint32_t paddr,  uint32
   * @brief Set DCache mmu mapping.
   *        Please do not call this function in your SDK application.
   *
-  * @param  uint32_t ext_ram : MMU_ACCESS_FLASH for flash, MMU_ACCESS_SPIRAM for spiram, MMU_INVALID for invalid.
+  * @param  uint32_t ext_ram : SOC_MMU_ACCESS_FLASH for flash, SOC_MMU_ACCESS_SPIRAM for spiram, SOC_MMU_INVALID for invalid.
   *
   * @param  uint32_t vaddr : virtual address in CPU address space.
   *                              Can be DRam0, DRam1, DRom0, DPort and AHB buses address.

components/esp_system/port/arch/xtensa/panic_arch.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -200,7 +200,7 @@ static inline void print_cache_err_details(const void *f)
             panic_print_str("Icache reject error occurred while accessing the address 0x");
             panic_print_hex(vaddr);
 
-            if (REG_READ(EXTMEM_PRO_CACHE_MMU_FAULT_CONTENT_REG) & MMU_INVALID) {
+            if (REG_READ(EXTMEM_PRO_CACHE_MMU_FAULT_CONTENT_REG) & SOC_MMU_INVALID) {
                 panic_print_str(" (invalid mmu entry)");
             }
             panic_print_str("\r\n");
@@ -235,7 +235,7 @@ static inline void print_cache_err_details(const void *f)
             panic_print_str("Dcache reject error occurred while accessing the address 0x");
             panic_print_hex(vaddr);
 
-            if (REG_READ(EXTMEM_PRO_CACHE_MMU_FAULT_CONTENT_REG) & MMU_INVALID) {
+            if (REG_READ(EXTMEM_PRO_CACHE_MMU_FAULT_CONTENT_REG) & SOC_MMU_INVALID) {
                 panic_print_str(" (invalid mmu entry)");
             }
             panic_print_str("\r\n");
@@ -245,7 +245,7 @@ static inline void print_cache_err_details(const void *f)
             panic_print_str("MMU entry fault error occurred while accessing the address 0x");
             panic_print_hex(vaddr);
 
-            if (REG_READ(EXTMEM_PRO_CACHE_MMU_FAULT_CONTENT_REG) & MMU_INVALID) {
+            if (REG_READ(EXTMEM_PRO_CACHE_MMU_FAULT_CONTENT_REG) & SOC_MMU_INVALID) {
                 panic_print_str(" (invalid mmu entry)");
             }
             panic_print_str("\r\n");
@@ -347,7 +347,7 @@ static inline void print_cache_err_details(const void *f)
             panic_print_str("MMU entry fault error occurred while accessing the address 0x");
             panic_print_hex(vaddr);
 
-            if (REG_READ(EXTMEM_CACHE_MMU_FAULT_CONTENT_REG) & MMU_INVALID) {
+            if (REG_READ(EXTMEM_CACHE_MMU_FAULT_CONTENT_REG) & SOC_MMU_INVALID) {
                 panic_print_str(" (invalid mmu entry)");
             }
             panic_print_str("\r\n");

components/esp_system/port/cpu_start.c

@@ -504,7 +504,7 @@ void IRAM_ATTR call_start_cpu0(void)
         esp_restart();
     }
 
-#if CONFIG_ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE
+#if ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE
 #if CONFIG_APP_BUILD_TYPE_ELF_RAM
     // For RAM loadable ELF case, we don't need to reserve IROM/DROM as instructions and data
     // are all in internal RAM. If the RAM loadable ELF has any requirement to memory map the
@@ -521,7 +521,7 @@ void IRAM_ATTR call_start_cpu0(void)
 
     /* Configure the Cache MMU size for instruction and rodata in flash. */
     Cache_Set_IDROM_MMU_Size(cache_mmu_irom_size, CACHE_DROM_MMU_MAX_END - cache_mmu_irom_size);
-#endif // CONFIG_ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE
+#endif // ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE
 
 #if CONFIG_ESPTOOLPY_OCT_FLASH && !CONFIG_ESPTOOLPY_FLASH_MODE_AUTO_DETECT
     bool efuse_opflash_en = efuse_ll_get_flash_type();

components/hal/esp32/include/hal/cache_ll.h

@@ -98,22 +98,22 @@ static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t v
     cache_bus_mask_t mask = 0;
 
     uint32_t vaddr_end = vaddr_start + len - 1;
-    if (vaddr_start >= IROM0_CACHE_ADDRESS_HIGH) {
+    if (vaddr_start >= SOC_IROM0_CACHE_ADDRESS_HIGH) {
         HAL_ASSERT(false);      //out of range
-    } else if (vaddr_start >= IROM0_CACHE_ADDRESS_LOW) {
+    } else if (vaddr_start >= SOC_IROM0_CACHE_ADDRESS_LOW) {
         mask |= CACHE_BUS_IBUS2;
-    } else if (vaddr_start >= IRAM1_CACHE_ADDRESS_LOW) {
+    } else if (vaddr_start >= SOC_IRAM1_CACHE_ADDRESS_LOW) {
         mask |= CACHE_BUS_IBUS1;
-        mask |= (vaddr_end >= IROM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS2 : 0;
-    } else if (vaddr_start >= IRAM0_CACHE_ADDRESS_LOW) {
+        mask |= (vaddr_end >= SOC_IROM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS2 : 0;
+    } else if (vaddr_start >= SOC_IRAM0_CACHE_ADDRESS_LOW) {
         mask |= CACHE_BUS_IBUS0;
-        mask |= (vaddr_end >= IRAM1_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS1 : 0;
-        mask |= (vaddr_end >= IROM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS2 : 0;
-    } else if (vaddr_start >= DRAM1_CACHE_ADDRESS_LOW) {
-        HAL_ASSERT(vaddr_end < DRAM1_CACHE_ADDRESS_HIGH);  //out of range, vaddr should be consecutive, see `ext_mem_defs.h`
+        mask |= (vaddr_end >= SOC_IRAM1_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS1 : 0;
+        mask |= (vaddr_end >= SOC_IROM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS2 : 0;
+    } else if (vaddr_start >= SOC_DRAM1_CACHE_ADDRESS_LOW) {
+        HAL_ASSERT(vaddr_end < SOC_DRAM1_CACHE_ADDRESS_HIGH);  //out of range, vaddr should be consecutive, see `ext_mem_defs.h`
         mask |= CACHE_BUS_DBUS1;
-    } else if (vaddr_start >= DROM0_CACHE_ADDRESS_LOW) {
-        HAL_ASSERT(vaddr_end < DROM0_CACHE_ADDRESS_HIGH);  //out of range, vaddr should be consecutive, see `ext_mem_defs.h`
+    } else if (vaddr_start >= SOC_DROM0_CACHE_ADDRESS_LOW) {
+        HAL_ASSERT(vaddr_end < SOC_DROM0_CACHE_ADDRESS_HIGH);  //out of range, vaddr should be consecutive, see `ext_mem_defs.h`
         mask |= CACHE_BUS_DBUS0;
     } else {
         HAL_ASSERT(false);

components/hal/esp32/include/hal/mmu_ll.h

@@ -102,14 +102,14 @@ static inline bool mmu_ll_check_valid_ext_vaddr_region(uint32_t mmu_id, uint32_t
     bool valid = false;
 
     if (type & MMU_VADDR_DATA) {
-        valid |= (ADDRESS_IN_DRAM1_CACHE(vaddr_start) && ADDRESS_IN_DRAM1_CACHE(vaddr_end)) ||
-                (ADDRESS_IN_DROM0_CACHE(vaddr_start) && ADDRESS_IN_DROM0_CACHE(vaddr_end));
+        valid |= (SOC_ADDRESS_IN_DRAM1_CACHE(vaddr_start) && SOC_ADDRESS_IN_DRAM1_CACHE(vaddr_end)) ||
+                (SOC_ADDRESS_IN_DROM0_CACHE(vaddr_start) && SOC_ADDRESS_IN_DROM0_CACHE(vaddr_end));
     }
 
     if (type & MMU_VADDR_INSTRUCTION) {
-        valid |= (ADDRESS_IN_IRAM0_CACHE(vaddr_start) && ADDRESS_IN_IRAM0_CACHE(vaddr_end)) ||
-                (ADDRESS_IN_IRAM1_CACHE(vaddr_start) && ADDRESS_IN_IRAM1_CACHE(vaddr_end)) ||
-                (ADDRESS_IN_IROM0_CACHE(vaddr_start) && ADDRESS_IN_IROM0_CACHE(vaddr_end));
+        valid |= (SOC_ADDRESS_IN_IRAM0_CACHE(vaddr_start) && SOC_ADDRESS_IN_IRAM0_CACHE(vaddr_end)) ||
+                (SOC_ADDRESS_IN_IRAM1_CACHE(vaddr_start) && SOC_ADDRESS_IN_IRAM1_CACHE(vaddr_end)) ||
+                (SOC_ADDRESS_IN_IROM0_CACHE(vaddr_start) && SOC_ADDRESS_IN_IROM0_CACHE(vaddr_end));
     }
 
     return valid;
@@ -128,9 +128,9 @@ static inline bool mmu_ll_check_valid_ext_vaddr_region(uint32_t mmu_id, uint32_t
 static inline bool mmu_ll_check_valid_paddr_region(uint32_t mmu_id, uint32_t paddr_start, uint32_t len)
 {
     (void)mmu_id;
-    return (paddr_start < (mmu_ll_get_page_size(mmu_id) * MMU_MAX_PADDR_PAGE_NUM)) &&
-           (len < (mmu_ll_get_page_size(mmu_id) * MMU_MAX_PADDR_PAGE_NUM)) &&
-           ((paddr_start + len - 1) < (mmu_ll_get_page_size(mmu_id) * MMU_MAX_PADDR_PAGE_NUM));
+    return (paddr_start < (mmu_ll_get_page_size(mmu_id) * SOC_MMU_MAX_PADDR_PAGE_NUM)) &&
+           (len < (mmu_ll_get_page_size(mmu_id) * SOC_MMU_MAX_PADDR_PAGE_NUM)) &&
+           ((paddr_start + len - 1) < (mmu_ll_get_page_size(mmu_id) * SOC_MMU_MAX_PADDR_PAGE_NUM));
 }
 
 /**
@@ -151,27 +151,27 @@ static inline uint32_t mmu_ll_get_entry_id(uint32_t mmu_id, uint32_t vaddr)
     uint32_t vaddr_mask = 0;
 
     //On ESP32, we only use PID0 and PID1
-    if (ADDRESS_IN_DROM0_CACHE(vaddr)) {
+    if (SOC_ADDRESS_IN_DROM0_CACHE(vaddr)) {
         offset = 0;
         shift_code = 16;
-        vaddr_mask = MMU_VADDR_MASK;
-    } else if (ADDRESS_IN_IRAM0_CACHE(vaddr)) {
+        vaddr_mask = SOC_MMU_VADDR_MASK;
+    } else if (SOC_ADDRESS_IN_IRAM0_CACHE(vaddr)) {
         offset = 64;
         shift_code = 16;
-        vaddr_mask = MMU_VADDR_MASK;
-    } else if (ADDRESS_IN_IRAM1_CACHE(vaddr)) {
+        vaddr_mask = SOC_MMU_VADDR_MASK;
+    } else if (SOC_ADDRESS_IN_IRAM1_CACHE(vaddr)) {
         offset = 128;
         shift_code = 16;
-        vaddr_mask = MMU_VADDR_MASK;
-    } else if (ADDRESS_IN_IROM0_CACHE(vaddr)) {
+        vaddr_mask = SOC_MMU_VADDR_MASK;
+    } else if (SOC_ADDRESS_IN_IROM0_CACHE(vaddr)) {
         offset = 192;
         shift_code = 16;
-        vaddr_mask = MMU_VADDR_MASK;
-    } else if (ADDRESS_IN_DRAM1_CACHE(vaddr)) {
+        vaddr_mask = SOC_MMU_VADDR_MASK;
+    } else if (SOC_ADDRESS_IN_DRAM1_CACHE(vaddr)) {
         //PSRAM page size 32KB
         offset = MMU_LL_PSRAM_ENTRY_START_ID;
         shift_code = 15;
-        vaddr_mask = MMU_VADDR_MASK >> 1;
+        vaddr_mask = SOC_MMU_VADDR_MASK >> 1;
     } else {
         HAL_ASSERT(false);
     }
@@ -268,14 +268,14 @@ static inline uint32_t mmu_ll_read_entry(uint32_t mmu_id, uint32_t entry_id)
 __attribute__((always_inline))
 static inline void mmu_ll_set_entry_invalid(uint32_t mmu_id, uint32_t entry_id)
 {
-    HAL_ASSERT(entry_id < MMU_ENTRY_NUM);
+    HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM);
     DPORT_INTERRUPT_DISABLE();
     switch (mmu_id) {
         case MMU_TABLE_CORE0:
-            DPORT_WRITE_PERI_REG((uint32_t)&DPORT_PRO_FLASH_MMU_TABLE[entry_id], MMU_INVALID);
+            DPORT_WRITE_PERI_REG((uint32_t)&DPORT_PRO_FLASH_MMU_TABLE[entry_id], SOC_MMU_INVALID);
             break;
         case MMU_TABLE_CORE1:
-            DPORT_WRITE_PERI_REG((uint32_t)&DPORT_APP_FLASH_MMU_TABLE[entry_id], MMU_INVALID);
+            DPORT_WRITE_PERI_REG((uint32_t)&DPORT_APP_FLASH_MMU_TABLE[entry_id], SOC_MMU_INVALID);
             break;
         default:
             HAL_ASSERT(false);
@@ -291,7 +291,7 @@ static inline void mmu_ll_set_entry_invalid(uint32_t mmu_id, uint32_t entry_id)
 __attribute__((always_inline))
 static inline void mmu_ll_unmap_all(uint32_t mmu_id)
 {
-    for (int i = 0; i < MMU_ENTRY_NUM; i++) {
+    for (int i = 0; i < SOC_MMU_ENTRY_NUM; i++) {
         mmu_ll_set_entry_invalid(mmu_id, i);
     }
 }
@@ -307,13 +307,13 @@ static inline void mmu_ll_unmap_all(uint32_t mmu_id)
 static inline bool mmu_ll_check_entry_valid(uint32_t mmu_id, uint32_t entry_id)
 {
     (void)mmu_id;
-    HAL_ASSERT(entry_id < MMU_ENTRY_NUM);
+    HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM);
 
     DPORT_INTERRUPT_DISABLE();
     uint32_t mmu_value = DPORT_SEQUENCE_REG_READ((uint32_t)&DPORT_PRO_FLASH_MMU_TABLE[entry_id]);
     DPORT_INTERRUPT_RESTORE();
 
-    return (mmu_value & MMU_INVALID) ? false : true;
+    return (mmu_value & SOC_MMU_INVALID) ? false : true;
 }
 
 /**
@@ -326,7 +326,7 @@ static inline bool mmu_ll_check_entry_valid(uint32_t mmu_id, uint32_t entry_id)
  */
 static inline mmu_target_t mmu_ll_get_entry_target(uint32_t mmu_id, uint32_t entry_id)
 {
-    HAL_ASSERT(entry_id < MMU_ENTRY_NUM);
+    HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM);
     HAL_ASSERT(mmu_ll_check_entry_valid(mmu_id, entry_id));
 
     return (entry_id >= MMU_LL_PSRAM_ENTRY_START_ID) ? MMU_TARGET_PSRAM0 : MMU_TARGET_FLASH0;
@@ -343,7 +343,7 @@ static inline mmu_target_t mmu_ll_get_entry_target(uint32_t mmu_id, uint32_t ent
 static inline uint32_t mmu_ll_entry_id_to_paddr_base(uint32_t mmu_id, uint32_t entry_id)
 {
     (void)mmu_id;
-    HAL_ASSERT(entry_id < MMU_ENTRY_NUM);
+    HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM);
 
     DPORT_INTERRUPT_DISABLE();
     uint32_t mmu_value = DPORT_SEQUENCE_REG_READ((uint32_t)&DPORT_PRO_FLASH_MMU_TABLE[entry_id]);
@@ -370,9 +370,9 @@ static inline int mmu_ll_find_entry_id_based_on_map_value(uint32_t mmu_id, uint3
 
     DPORT_INTERRUPT_DISABLE();
     if (target == MMU_TARGET_FLASH0) {
-        for (int i = 0; i < MMU_ENTRY_NUM; i++) {
+        for (int i = 0; i < SOC_MMU_ENTRY_NUM; i++) {
             uint32_t mmu_value = DPORT_SEQUENCE_REG_READ((uint32_t)&DPORT_PRO_FLASH_MMU_TABLE[i]);
-            if (!(mmu_value & MMU_INVALID)) {
+            if (!(mmu_value & SOC_MMU_INVALID)) {
                 if (mmu_value == mmu_val) {
                     DPORT_INTERRUPT_RESTORE();
                     return i;
@@ -383,7 +383,7 @@ static inline int mmu_ll_find_entry_id_based_on_map_value(uint32_t mmu_id, uint3
         //For PSRAM, we only use PID 0/1. Its start entry ID is MMU_LL_PSRAM_ENTRY_START_ID (1152), and 128 entries are used for PSRAM
         for (int i = MMU_LL_PSRAM_ENTRY_START_ID; i < 1280; i++) {
             uint32_t mmu_value = DPORT_SEQUENCE_REG_READ((uint32_t)&DPORT_PRO_FLASH_MMU_TABLE[i]);
-            if (!(mmu_value & MMU_INVALID)) {
+            if (!(mmu_value & SOC_MMU_INVALID)) {
                 if (mmu_value == mmu_val) {
                     DPORT_INTERRUPT_RESTORE();
                     return i;

components/hal/esp32c2/include/hal/cache_ll.h

@@ -169,9 +169,9 @@ static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t v
     cache_bus_mask_t mask = 0;
 
     uint32_t vaddr_end = vaddr_start + len - 1;
-    if (vaddr_start >= IRAM0_CACHE_ADDRESS_LOW && vaddr_end < IRAM0_CACHE_ADDRESS_HIGH) {
+    if (vaddr_start >= SOC_IRAM0_CACHE_ADDRESS_LOW && vaddr_end < SOC_IRAM0_CACHE_ADDRESS_HIGH) {
         mask |= CACHE_BUS_IBUS0;
-    } else if (vaddr_start >= DRAM0_CACHE_ADDRESS_LOW && vaddr_end < DRAM0_CACHE_ADDRESS_HIGH) {
+    } else if (vaddr_start >= SOC_DRAM0_CACHE_ADDRESS_LOW && vaddr_end < SOC_DRAM0_CACHE_ADDRESS_HIGH) {
         mask |= CACHE_BUS_DBUS0;
     } else {
         HAL_ASSERT(0);      //Out of region

components/hal/esp32c2/include/hal/mmu_ll.h

@@ -99,11 +99,11 @@ static inline bool mmu_ll_check_valid_ext_vaddr_region(uint32_t mmu_id, uint32_t
     bool valid = false;
 
     if (type & MMU_VADDR_INSTRUCTION) {
-        valid |= (ADDRESS_IN_IRAM0_CACHE(vaddr_start) && ADDRESS_IN_IRAM0_CACHE(vaddr_end));
+        valid |= (SOC_ADDRESS_IN_IRAM0_CACHE(vaddr_start) && SOC_ADDRESS_IN_IRAM0_CACHE(vaddr_end));
     }
 
     if (type & MMU_VADDR_DATA) {
-        valid |= (ADDRESS_IN_DRAM0_CACHE(vaddr_start) && ADDRESS_IN_DRAM0_CACHE(vaddr_end));
+        valid |= (SOC_ADDRESS_IN_DRAM0_CACHE(vaddr_start) && SOC_ADDRESS_IN_DRAM0_CACHE(vaddr_end));
     }
 
     return valid;
@@ -122,9 +122,9 @@ static inline bool mmu_ll_check_valid_ext_vaddr_region(uint32_t mmu_id, uint32_t
 static inline bool mmu_ll_check_valid_paddr_region(uint32_t mmu_id, uint32_t paddr_start, uint32_t len)
 {
     (void)mmu_id;
-    return (paddr_start < (mmu_ll_get_page_size(mmu_id) * MMU_MAX_PADDR_PAGE_NUM)) &&
-           (len < (mmu_ll_get_page_size(mmu_id) * MMU_MAX_PADDR_PAGE_NUM)) &&
-           ((paddr_start + len - 1) < (mmu_ll_get_page_size(mmu_id) * MMU_MAX_PADDR_PAGE_NUM));
+    return (paddr_start < (mmu_ll_get_page_size(mmu_id) * SOC_MMU_MAX_PADDR_PAGE_NUM)) &&
+           (len < (mmu_ll_get_page_size(mmu_id) * SOC_MMU_MAX_PADDR_PAGE_NUM)) &&
+           ((paddr_start + len - 1) < (mmu_ll_get_page_size(mmu_id) * SOC_MMU_MAX_PADDR_PAGE_NUM));
 }
 
 /**
@@ -157,7 +157,7 @@ static inline uint32_t mmu_ll_get_entry_id(uint32_t mmu_id, uint32_t vaddr)
             HAL_ASSERT(shift_code);
     }
 
-    return ((vaddr & MMU_VADDR_MASK) >> shift_code);
+    return ((vaddr & SOC_MMU_VADDR_MASK) >> shift_code);
 }
 
 /**
@@ -208,9 +208,9 @@ static inline void mmu_ll_write_entry(uint32_t mmu_id, uint32_t entry_id, uint32
 {
     (void)mmu_id;
     HAL_ASSERT(target == MMU_TARGET_FLASH0);
-    HAL_ASSERT(entry_id < MMU_ENTRY_NUM);
+    HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM);
 
-    *(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = mmu_val | MMU_ACCESS_FLASH | MMU_VALID;
+    *(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = mmu_val | SOC_MMU_ACCESS_FLASH | SOC_MMU_VALID;
 }
 
 /**
@@ -224,7 +224,7 @@ __attribute__((always_inline))
 static inline uint32_t mmu_ll_read_entry(uint32_t mmu_id, uint32_t entry_id)
 {
     (void)mmu_id;
-    HAL_ASSERT(entry_id < MMU_ENTRY_NUM);
+    HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM);
 
     return *(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4);
 }
@@ -239,9 +239,9 @@ __attribute__((always_inline))
 static inline void mmu_ll_set_entry_invalid(uint32_t mmu_id, uint32_t entry_id)
 {
     (void)mmu_id;
-    HAL_ASSERT(entry_id < MMU_ENTRY_NUM);
+    HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM);
 
-    *(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = MMU_INVALID;
+    *(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = SOC_MMU_INVALID;
 }
 
 /**
@@ -252,7 +252,7 @@ static inline void mmu_ll_set_entry_invalid(uint32_t mmu_id, uint32_t entry_id)
 __attribute__((always_inline))
 static inline void mmu_ll_unmap_all(uint32_t mmu_id)
 {
-    for (int i = 0; i < MMU_ENTRY_NUM; i++) {
+    for (int i = 0; i < SOC_MMU_ENTRY_NUM; i++) {
         mmu_ll_set_entry_invalid(mmu_id, i);
     }
 }
@@ -268,9 +268,9 @@ static inline void mmu_ll_unmap_all(uint32_t mmu_id)
 static inline bool mmu_ll_check_entry_valid(uint32_t mmu_id, uint32_t entry_id)
 {
     (void)mmu_id;
-    HAL_ASSERT(entry_id < MMU_ENTRY_NUM);
+    HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM);
 
-    return (*(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) & MMU_INVALID) ? false : true;
+    return (*(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) & SOC_MMU_INVALID) ? false : true;
 }
 
 /**
@@ -298,7 +298,7 @@ static inline mmu_target_t mmu_ll_get_entry_target(uint32_t mmu_id, uint32_t ent
 static inline uint32_t mmu_ll_entry_id_to_paddr_base(uint32_t mmu_id, uint32_t entry_id)
 {
     (void)mmu_id;
-    HAL_ASSERT(entry_id < MMU_ENTRY_NUM);
+    HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM);
 
     mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id);
     uint32_t shift_code = 0;
@@ -316,7 +316,7 @@ static inline uint32_t mmu_ll_entry_id_to_paddr_base(uint32_t mmu_id, uint32_t e
             HAL_ASSERT(shift_code);
     }
 
-    return ((*(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4)) & MMU_VALID_VAL_MASK) << shift_code;
+    return ((*(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4)) & SOC_MMU_VALID_VAL_MASK) << shift_code;
 }
 
 /**
@@ -333,10 +333,10 @@ static inline uint32_t mmu_ll_entry_id_to_paddr_base(uint32_t mmu_id, uint32_t e
 static inline int mmu_ll_find_entry_id_based_on_map_value(uint32_t mmu_id, uint32_t mmu_val, mmu_target_t target)
 {
     (void)mmu_id;
-    for (int i = 0; i < MMU_ENTRY_NUM; i++) {
+    for (int i = 0; i < SOC_MMU_ENTRY_NUM; i++) {
         if (mmu_ll_check_entry_valid(mmu_id, i)) {
             if (mmu_ll_get_entry_target(mmu_id, i) == target) {
-                if (((*(uint32_t *)(DR_REG_MMU_TABLE + i * 4)) & MMU_VALID_VAL_MASK) == mmu_val) {
+                if (((*(uint32_t *)(DR_REG_MMU_TABLE + i * 4)) & SOC_MMU_VALID_VAL_MASK) == mmu_val) {
                     return i;
                 }
             }

components/hal/esp32c3/include/hal/cache_ll.h

@@ -171,9 +171,9 @@ static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t v
     cache_bus_mask_t mask = 0;
 
     uint32_t vaddr_end = vaddr_start + len - 1;
-    if (vaddr_start >= IRAM0_CACHE_ADDRESS_LOW && vaddr_end < IRAM0_CACHE_ADDRESS_HIGH) {
+    if (vaddr_start >= SOC_IRAM0_CACHE_ADDRESS_LOW && vaddr_end < SOC_IRAM0_CACHE_ADDRESS_HIGH) {
         mask |= CACHE_BUS_IBUS0;
-    } else if (vaddr_start >= DRAM0_CACHE_ADDRESS_LOW && vaddr_end < DRAM0_CACHE_ADDRESS_HIGH) {
+    } else if (vaddr_start >= SOC_DRAM0_CACHE_ADDRESS_LOW && vaddr_end < SOC_DRAM0_CACHE_ADDRESS_HIGH) {
         mask |= CACHE_BUS_DBUS0;
     } else {
         HAL_ASSERT(0);          //Out of region

components/hal/esp32c3/include/hal/mmu_ll.h

@@ -100,11 +100,11 @@ static inline bool mmu_ll_check_valid_ext_vaddr_region(uint32_t mmu_id, uint32_t
     bool valid = false;
 
     if (type & MMU_VADDR_INSTRUCTION) {
-        valid |= (ADDRESS_IN_IRAM0_CACHE(vaddr_start) && ADDRESS_IN_IRAM0_CACHE(vaddr_end));
+        valid |= (SOC_ADDRESS_IN_IRAM0_CACHE(vaddr_start) && SOC_ADDRESS_IN_IRAM0_CACHE(vaddr_end));
     }
 
     if (type & MMU_VADDR_DATA) {
-        valid |= (ADDRESS_IN_DRAM0_CACHE(vaddr_start) && ADDRESS_IN_DRAM0_CACHE(vaddr_end));
+        valid |= (SOC_ADDRESS_IN_DRAM0_CACHE(vaddr_start) && SOC_ADDRESS_IN_DRAM0_CACHE(vaddr_end));
     }
 
     return valid;
@@ -123,9 +123,9 @@ static inline bool mmu_ll_check_valid_ext_vaddr_region(uint32_t mmu_id, uint32_t
 static inline bool mmu_ll_check_valid_paddr_region(uint32_t mmu_id, uint32_t paddr_start, uint32_t len)
 {
     (void)mmu_id;
-    return (paddr_start < (mmu_ll_get_page_size(mmu_id) * MMU_MAX_PADDR_PAGE_NUM)) &&
-           (len < (mmu_ll_get_page_size(mmu_id) * MMU_MAX_PADDR_PAGE_NUM)) &&
-           ((paddr_start + len - 1) < (mmu_ll_get_page_size(mmu_id) * MMU_MAX_PADDR_PAGE_NUM));
+    return (paddr_start < (mmu_ll_get_page_size(mmu_id) * SOC_MMU_MAX_PADDR_PAGE_NUM)) &&
+           (len < (mmu_ll_get_page_size(mmu_id) * SOC_MMU_MAX_PADDR_PAGE_NUM)) &&
+           ((paddr_start + len - 1) < (mmu_ll_get_page_size(mmu_id) * SOC_MMU_MAX_PADDR_PAGE_NUM));
 }
 
 /**
@@ -141,7 +141,7 @@ __attribute__((always_inline))
 static inline uint32_t mmu_ll_get_entry_id(uint32_t mmu_id, uint32_t vaddr)
 {
     (void)mmu_id;
-    return ((vaddr & MMU_VADDR_MASK) >> 16);
+    return ((vaddr & SOC_MMU_VADDR_MASK) >> 16);
 }
 
 /**
@@ -175,9 +175,9 @@ static inline void mmu_ll_write_entry(uint32_t mmu_id, uint32_t entry_id, uint32
 {
     (void)mmu_id;
     HAL_ASSERT(target == MMU_TARGET_FLASH0);
-    HAL_ASSERT(entry_id < MMU_ENTRY_NUM);
+    HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM);
 
-    *(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = mmu_val | MMU_ACCESS_FLASH | MMU_VALID;
+    *(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = mmu_val | SOC_MMU_ACCESS_FLASH | SOC_MMU_VALID;
 }
 
 /**
@@ -191,7 +191,7 @@ __attribute__((always_inline))
 static inline uint32_t mmu_ll_read_entry(uint32_t mmu_id, uint32_t entry_id)
 {
     (void)mmu_id;
-    HAL_ASSERT(entry_id < MMU_ENTRY_NUM);
+    HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM);
 
     return *(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4);
 }
@@ -206,9 +206,9 @@ __attribute__((always_inline))
 static inline void mmu_ll_set_entry_invalid(uint32_t mmu_id, uint32_t entry_id)
 {
     (void)mmu_id;
-    HAL_ASSERT(entry_id < MMU_ENTRY_NUM);
+    HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM);
 
-    *(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = MMU_INVALID;
+    *(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = SOC_MMU_INVALID;
 }
 
 /**
@@ -219,7 +219,7 @@ static inline void mmu_ll_set_entry_invalid(uint32_t mmu_id, uint32_t entry_id)
 __attribute__((always_inline))
 static inline void mmu_ll_unmap_all(uint32_t mmu_id)
 {
-    for (int i = 0; i < MMU_ENTRY_NUM; i++) {
+    for (int i = 0; i < SOC_MMU_ENTRY_NUM; i++) {
         mmu_ll_set_entry_invalid(mmu_id, i);
     }
 }
@@ -235,9 +235,9 @@ static inline void mmu_ll_unmap_all(uint32_t mmu_id)
 static inline bool mmu_ll_check_entry_valid(uint32_t mmu_id, uint32_t entry_id)
 {
     (void)mmu_id;
-    HAL_ASSERT(entry_id < MMU_ENTRY_NUM);
+    HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM);
 
-    return (*(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) & MMU_INVALID) ? false : true;
+    return (*(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) & SOC_MMU_INVALID) ? false : true;
 }
 
 /**
@@ -251,7 +251,7 @@ static inline bool mmu_ll_check_entry_valid(uint32_t mmu_id, uint32_t entry_id)
 static inline mmu_target_t mmu_ll_get_entry_target(uint32_t mmu_id, uint32_t entry_id)
 {
     (void)mmu_id;
-    HAL_ASSERT(entry_id < MMU_ENTRY_NUM);
+    HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM);
 
     return MMU_TARGET_FLASH0;
 }
@@ -267,9 +267,9 @@ static inline mmu_target_t mmu_ll_get_entry_target(uint32_t mmu_id, uint32_t ent
 static inline uint32_t mmu_ll_entry_id_to_paddr_base(uint32_t mmu_id, uint32_t entry_id)
 {
     (void)mmu_id;
-    HAL_ASSERT(entry_id < MMU_ENTRY_NUM);
+    HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM);
 
-    return ((*(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4)) & MMU_VALID_VAL_MASK) << 16;
+    return ((*(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4)) & SOC_MMU_VALID_VAL_MASK) << 16;
 }
 
 /**
@@ -286,10 +286,10 @@ static inline uint32_t mmu_ll_entry_id_to_paddr_base(uint32_t mmu_id, uint32_t e
 static inline int mmu_ll_find_entry_id_based_on_map_value(uint32_t mmu_id, uint32_t mmu_val, mmu_target_t target)
 {
     (void)mmu_id;
-    for (int i = 0; i < MMU_ENTRY_NUM; i++) {
+    for (int i = 0; i < SOC_MMU_ENTRY_NUM; i++) {
         if (mmu_ll_check_entry_valid(mmu_id, i)) {
             if (mmu_ll_get_entry_target(mmu_id, i) == target) {
-                if (((*(uint32_t *)(DR_REG_MMU_TABLE + i * 4)) & MMU_VALID_VAL_MASK) == mmu_val) {
+                if (((*(uint32_t *)(DR_REG_MMU_TABLE + i * 4)) & SOC_MMU_VALID_VAL_MASK) == mmu_val) {
                     return i;
                 }
             }

components/hal/esp32c6/include/hal/cache_ll.h

@@ -168,7 +168,7 @@ static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t v
     cache_bus_mask_t mask = 0;
 
     uint32_t vaddr_end = vaddr_start + len - 1;
-    if (vaddr_start >= IRAM0_CACHE_ADDRESS_LOW && vaddr_end < IRAM0_CACHE_ADDRESS_HIGH) {
+    if (vaddr_start >= SOC_IRAM0_CACHE_ADDRESS_LOW && vaddr_end < SOC_IRAM0_CACHE_ADDRESS_HIGH) {
         //c6 the I/D bus memory are shared, so we always return `CACHE_BUS_IBUS0 | CACHE_BUS_DBUS0`
         mask |= CACHE_BUS_IBUS0 | CACHE_BUS_DBUS0;
     } else {

components/hal/esp32c6/include/hal/mmu_ll.h

@@ -106,7 +106,7 @@ static inline bool mmu_ll_check_valid_ext_vaddr_region(uint32_t mmu_id, uint32_t
     (void)mmu_id;
     (void)type;
     uint32_t vaddr_end = vaddr_start + len - 1;
-    return (ADDRESS_IN_IRAM0_CACHE(vaddr_start) && ADDRESS_IN_IRAM0_CACHE(vaddr_end)) || (ADDRESS_IN_DRAM0_CACHE(vaddr_start) && ADDRESS_IN_DRAM0_CACHE(vaddr_end));
+    return (SOC_ADDRESS_IN_IRAM0_CACHE(vaddr_start) && SOC_ADDRESS_IN_IRAM0_CACHE(vaddr_end)) || (SOC_ADDRESS_IN_DRAM0_CACHE(vaddr_start) && SOC_ADDRESS_IN_DRAM0_CACHE(vaddr_end));
 }
 
 /**
@@ -122,9 +122,9 @@ static inline bool mmu_ll_check_valid_ext_vaddr_region(uint32_t mmu_id, uint32_t
 static inline bool mmu_ll_check_valid_paddr_region(uint32_t mmu_id, uint32_t paddr_start, uint32_t len)
 {
     (void)mmu_id;
-    return (paddr_start < (mmu_ll_get_page_size(mmu_id) * MMU_MAX_PADDR_PAGE_NUM)) &&
-           (len < (mmu_ll_get_page_size(mmu_id) * MMU_MAX_PADDR_PAGE_NUM)) &&
-           ((paddr_start + len - 1) < (mmu_ll_get_page_size(mmu_id) * MMU_MAX_PADDR_PAGE_NUM));
+    return (paddr_start < (mmu_ll_get_page_size(mmu_id) * SOC_MMU_MAX_PADDR_PAGE_NUM)) &&
+           (len < (mmu_ll_get_page_size(mmu_id) * SOC_MMU_MAX_PADDR_PAGE_NUM)) &&
+           ((paddr_start + len - 1) < (mmu_ll_get_page_size(mmu_id) * SOC_MMU_MAX_PADDR_PAGE_NUM));
 }
 
 /**
@@ -158,7 +158,7 @@ static inline uint32_t mmu_ll_get_entry_id(uint32_t mmu_id, uint32_t vaddr)
         default:
             HAL_ASSERT(shift_code);
     }
-    return ((vaddr & MMU_VADDR_MASK) >> shift_code);
+    return ((vaddr & SOC_MMU_VADDR_MASK) >> shift_code);
 }
 
 /**
@@ -211,10 +211,10 @@ __attribute__((always_inline)) static inline void mmu_ll_write_entry(uint32_t mm
     (void)target;
     uint32_t mmu_raw_value;
     if (mmu_ll_cache_encryption_enabled()) {
-        mmu_val |= MMU_SENSITIVE;
+        mmu_val |= SOC_MMU_SENSITIVE;
     }
 
-    mmu_raw_value = mmu_val | MMU_VALID;
+    mmu_raw_value = mmu_val | SOC_MMU_VALID;
     REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id);
     REG_WRITE(SPI_MEM_MMU_ITEM_CONTENT_REG(0), mmu_raw_value);
 }
@@ -234,12 +234,12 @@ __attribute__((always_inline)) static inline uint32_t mmu_ll_read_entry(uint32_t
     REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id);
     mmu_raw_value = REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0));
     if (mmu_ll_cache_encryption_enabled()) {
-        mmu_raw_value &= ~MMU_SENSITIVE;
+        mmu_raw_value &= ~SOC_MMU_SENSITIVE;
     }
-    if (!(mmu_raw_value & MMU_VALID)) {
+    if (!(mmu_raw_value & SOC_MMU_VALID)) {
         return 0;
     }
-    ret = mmu_raw_value & MMU_VALID_VAL_MASK;
+    ret = mmu_raw_value & SOC_MMU_VALID_VAL_MASK;
     return ret;
 }
 
@@ -253,7 +253,7 @@ __attribute__((always_inline)) static inline void mmu_ll_set_entry_invalid(uint3
 {
     (void)mmu_id;
     REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id);
-    REG_WRITE(SPI_MEM_MMU_ITEM_CONTENT_REG(0), MMU_INVALID);
+    REG_WRITE(SPI_MEM_MMU_ITEM_CONTENT_REG(0), SOC_MMU_INVALID);
 }
 
 /**
@@ -264,7 +264,7 @@ __attribute__((always_inline)) static inline void mmu_ll_set_entry_invalid(uint3
 __attribute__((always_inline))
 static inline void mmu_ll_unmap_all(uint32_t mmu_id)
 {
-    for (int i = 0; i < MMU_ENTRY_NUM; i++) {
+    for (int i = 0; i < SOC_MMU_ENTRY_NUM; i++) {
         mmu_ll_set_entry_invalid(mmu_id, i);
     }
 }
@@ -280,10 +280,10 @@ static inline void mmu_ll_unmap_all(uint32_t mmu_id)
 static inline bool mmu_ll_check_entry_valid(uint32_t mmu_id, uint32_t entry_id)
 {
     (void)mmu_id;
-    HAL_ASSERT(entry_id < MMU_ENTRY_NUM);
+    HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM);
 
     REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id);
-    return (REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0)) & MMU_VALID) ? true : false;
+    return (REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0)) & SOC_MMU_VALID) ? true : false;
 }
 
 /**
@@ -311,7 +311,7 @@ static inline mmu_target_t mmu_ll_get_entry_target(uint32_t mmu_id, uint32_t ent
 static inline uint32_t mmu_ll_entry_id_to_paddr_base(uint32_t mmu_id, uint32_t entry_id)
 {
     (void)mmu_id;
-    HAL_ASSERT(entry_id < MMU_ENTRY_NUM);
+    HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM);
 
     mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id);
     uint32_t shift_code = 0;
@@ -333,7 +333,7 @@ static inline uint32_t mmu_ll_entry_id_to_paddr_base(uint32_t mmu_id, uint32_t e
     }
 
     REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id);
-    return (REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0)) & MMU_VALID_VAL_MASK) << shift_code;
+    return (REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0)) & SOC_MMU_VALID_VAL_MASK) << shift_code;
 }
 
 /**
@@ -350,11 +350,11 @@ static inline uint32_t mmu_ll_entry_id_to_paddr_base(uint32_t mmu_id, uint32_t e
 static inline int mmu_ll_find_entry_id_based_on_map_value(uint32_t mmu_id, uint32_t mmu_val, mmu_target_t target)
 {
     (void)mmu_id;
-    for (int i = 0; i < MMU_ENTRY_NUM; i++) {
+    for (int i = 0; i < SOC_MMU_ENTRY_NUM; i++) {
         if (mmu_ll_check_entry_valid(mmu_id, i)) {
             if (mmu_ll_get_entry_target(mmu_id, i) == target) {
                 REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), i);
-                if ((REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0)) & MMU_VALID_VAL_MASK) == mmu_val) {
+                if ((REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0)) & SOC_MMU_VALID_VAL_MASK) == mmu_val) {
                     return i;
                 }
             }

components/hal/esp32h2/include/hal/cache_ll.h

@@ -168,7 +168,7 @@ static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t v
     cache_bus_mask_t mask = 0;
 
     uint32_t vaddr_end = vaddr_start + len - 1;
-    if (vaddr_start >= IRAM0_CACHE_ADDRESS_LOW && vaddr_end < IRAM0_CACHE_ADDRESS_HIGH) {
+    if (vaddr_start >= SOC_IRAM0_CACHE_ADDRESS_LOW && vaddr_end < SOC_IRAM0_CACHE_ADDRESS_HIGH) {
         //h2 the I/D bus memory are shared, so we always return `CACHE_BUS_IBUS0 | CACHE_BUS_DBUS0`
         mask |= CACHE_BUS_IBUS0 | CACHE_BUS_DBUS0;
     } else {

components/hal/esp32h2/include/hal/mmu_ll.h

@@ -109,7 +109,7 @@ static inline bool mmu_ll_check_valid_ext_vaddr_region(uint32_t mmu_id, uint32_t
     (void)mmu_id;
     (void)type;
     uint32_t vaddr_end = vaddr_start + len - 1;
-    return (ADDRESS_IN_IRAM0_CACHE(vaddr_start) && ADDRESS_IN_IRAM0_CACHE(vaddr_end)) || (ADDRESS_IN_DRAM0_CACHE(vaddr_start) && ADDRESS_IN_DRAM0_CACHE(vaddr_end));
+    return (SOC_ADDRESS_IN_IRAM0_CACHE(vaddr_start) && SOC_ADDRESS_IN_IRAM0_CACHE(vaddr_end)) || (SOC_ADDRESS_IN_DRAM0_CACHE(vaddr_start) && SOC_ADDRESS_IN_DRAM0_CACHE(vaddr_end));
 }
 
 /**
@@ -126,9 +126,9 @@ __attribute__((always_inline))
 static inline bool mmu_ll_check_valid_paddr_region(uint32_t mmu_id, uint32_t paddr_start, uint32_t len)
 {
     (void)mmu_id;
-    return (paddr_start < (mmu_ll_get_page_size(mmu_id) * MMU_MAX_PADDR_PAGE_NUM)) &&
-           (len < (mmu_ll_get_page_size(mmu_id) * MMU_MAX_PADDR_PAGE_NUM)) &&
-           ((paddr_start + len - 1) < (mmu_ll_get_page_size(mmu_id) * MMU_MAX_PADDR_PAGE_NUM));
+    return (paddr_start < (mmu_ll_get_page_size(mmu_id) * SOC_MMU_MAX_PADDR_PAGE_NUM)) &&
+           (len < (mmu_ll_get_page_size(mmu_id) * SOC_MMU_MAX_PADDR_PAGE_NUM)) &&
+           ((paddr_start + len - 1) < (mmu_ll_get_page_size(mmu_id) * SOC_MMU_MAX_PADDR_PAGE_NUM));
 }
 
 /**
@@ -164,7 +164,7 @@ static inline uint32_t mmu_ll_get_entry_id(uint32_t mmu_id, uint32_t vaddr)
             HAL_ASSERT(shift_code);
     }
 
-    return ((vaddr & MMU_VADDR_MASK) >> shift_code);
+    return ((vaddr & SOC_MMU_VADDR_MASK) >> shift_code);
 }
 
 /**
@@ -218,10 +218,10 @@ __attribute__((always_inline)) static inline void mmu_ll_write_entry(uint32_t mm
     (void)target;
     uint32_t mmu_raw_value;
     if (mmu_ll_cache_encryption_enabled()) {
-        mmu_val |= MMU_SENSITIVE;
+        mmu_val |= SOC_MMU_SENSITIVE;
     }
     /* Note: for ESP32-H2, invert invalid bit for compatible with upper-layer software */
-    mmu_raw_value = mmu_val ^ MMU_INVALID_MASK;
+    mmu_raw_value = mmu_val ^ SOC_MMU_INVALID_MASK;
     REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id);
     REG_WRITE(SPI_MEM_MMU_ITEM_CONTENT_REG(0), mmu_raw_value);
 }
@@ -242,10 +242,10 @@ __attribute__((always_inline)) static inline uint32_t mmu_ll_read_entry(uint32_t
     REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id);
     mmu_raw_value = REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0));
     if (mmu_ll_cache_encryption_enabled()) {
-        mmu_raw_value &= ~MMU_SENSITIVE;
+        mmu_raw_value &= ~SOC_MMU_SENSITIVE;
     }
     /* Note: for ESP32-H2, invert invalid bit for compatible with upper-layer software */
-    ret = mmu_raw_value ^ MMU_INVALID_MASK;
+    ret = mmu_raw_value ^ SOC_MMU_INVALID_MASK;
     return ret;
 }
 
@@ -260,28 +260,9 @@ __attribute__((always_inline)) static inline void mmu_ll_set_entry_invalid(uint3
     (void)mmu_id;
 
     REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id);
-    REG_WRITE(SPI_MEM_MMU_ITEM_CONTENT_REG(0), MMU_INVALID);
+    REG_WRITE(SPI_MEM_MMU_ITEM_CONTENT_REG(0), SOC_MMU_INVALID);
 }
 
-// /**
-//  * Get MMU table entry is invalid
-//  *
-//  * @param mmu_id   MMU ID
-//  * @param entry_id MMU entry ID
-//  * return ture for MMU entry is invalid, false for valid
-//  */
-// __attribute__((always_inline)) static inline bool mmu_ll_get_entry_is_invalid(uint32_t mmu_id, uint32_t entry_id)
-// {
-//     (void)mmu_id;
-
-//     uint32_t mmu_raw_value;
-//     REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id);
-//     mmu_raw_value = REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0));
-//     /* Note: for ESP32-H2, the invalid-bit of MMU: 0 for invalid, 1 for valid */
-//     return (mmu_raw_value & MMU_INVALID_MASK) ? false : true;
-// }
-
-
 /**
  * Unmap all the items in the MMU table
  *
@@ -290,7 +271,7 @@ __attribute__((always_inline)) static inline void mmu_ll_set_entry_invalid(uint3
 __attribute__((always_inline))
 static inline void mmu_ll_unmap_all(uint32_t mmu_id)
 {
-    for (int i = 0; i < MMU_ENTRY_NUM; i++) {
+    for (int i = 0; i < SOC_MMU_ENTRY_NUM; i++) {
         mmu_ll_set_entry_invalid(mmu_id, i);
     }
 }
@@ -306,10 +287,10 @@ static inline void mmu_ll_unmap_all(uint32_t mmu_id)
 static inline bool mmu_ll_check_entry_valid(uint32_t mmu_id, uint32_t entry_id)
 {
     (void)mmu_id;
-    HAL_ASSERT(entry_id < MMU_ENTRY_NUM);
+    HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM);
 
     REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id);
-    return (REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0)) & MMU_VALID) ? true : false;
+    return (REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0)) & SOC_MMU_VALID) ? true : false;
 }
 
 /**
@@ -337,7 +318,7 @@ static inline mmu_target_t mmu_ll_get_entry_target(uint32_t mmu_id, uint32_t ent
 static inline uint32_t mmu_ll_entry_id_to_paddr_base(uint32_t mmu_id, uint32_t entry_id)
 {
     (void)mmu_id;
-    HAL_ASSERT(entry_id < MMU_ENTRY_NUM);
+    HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM);
 
     mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id);
     uint32_t shift_code = 0;
@@ -359,7 +340,7 @@ static inline uint32_t mmu_ll_entry_id_to_paddr_base(uint32_t mmu_id, uint32_t e
     }
 
     REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id);
-    return (REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0)) & MMU_VALID_VAL_MASK) << shift_code;
+    return (REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0)) & SOC_MMU_VALID_VAL_MASK) << shift_code;
 }
 
 /**
@@ -376,11 +357,11 @@ static inline uint32_t mmu_ll_entry_id_to_paddr_base(uint32_t mmu_id, uint32_t e
 static inline int mmu_ll_find_entry_id_based_on_map_value(uint32_t mmu_id, uint32_t mmu_val, mmu_target_t target)
 {
     (void)mmu_id;
-    for (int i = 0; i < MMU_ENTRY_NUM; i++) {
+    for (int i = 0; i < SOC_MMU_ENTRY_NUM; i++) {
         if (mmu_ll_check_entry_valid(mmu_id, i)) {
             if (mmu_ll_get_entry_target(mmu_id, i) == target) {
                 REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), i);
-                if ((REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0)) & MMU_VALID_VAL_MASK) == mmu_val) {
+                if ((REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0)) & SOC_MMU_VALID_VAL_MASK) == mmu_val) {
                     return i;
                 }
             }

components/hal/esp32p4/include/hal/cache_ll.h

@@ -63,10 +63,10 @@ static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t v
     cache_bus_mask_t mask = 0;
 
     uint32_t vaddr_end = vaddr_start + len - 1;
-    if (vaddr_start >= DRAM_FLASH_ADDRESS_LOW && vaddr_end < DRAM_FLASH_ADDRESS_HIGH) {
+    if (vaddr_start >= SOC_DRAM_FLASH_ADDRESS_LOW && vaddr_end < SOC_DRAM_FLASH_ADDRESS_HIGH) {
         mask |= CACHE_BUS_IBUS0;
         mask |= CACHE_BUS_DBUS0;
-    } else if (vaddr_start >= DRAM_PSRAM_ADDRESS_LOW && vaddr_end < DRAM_PSRAM_ADDRESS_HIGH) {
+    } else if (vaddr_start >= SOC_DRAM_PSRAM_ADDRESS_LOW && vaddr_end < SOC_DRAM_PSRAM_ADDRESS_HIGH) {
         mask |= CACHE_BUS_IBUS1;
         mask |= CACHE_BUS_DBUS1;
     } else {

components/hal/esp32p4/include/hal/mmu_ll.h

@@ -72,9 +72,9 @@ static inline mmu_target_t mmu_ll_vaddr_to_target(uint32_t vaddr)
 {
     mmu_target_t target = MMU_TARGET_FLASH0;
 
-    if (ADDRESS_IN_DRAM_FLASH(vaddr)) {
+    if (SOC_ADDRESS_IN_DRAM_FLASH(vaddr)) {
         target = MMU_TARGET_FLASH0;
-    } else if (ADDRESS_IN_DRAM_PSRAM(vaddr)) {
+    } else if (SOC_ADDRESS_IN_DRAM_PSRAM(vaddr)) {
         target = MMU_TARGET_PSRAM0;
     } else {
         HAL_ASSERT(false);
@@ -133,7 +133,7 @@ static inline bool mmu_ll_check_valid_ext_vaddr_region(uint32_t mmu_id, uint32_t
     (void)mmu_id;
     (void)type;
     uint32_t vaddr_end = vaddr_start + len - 1;
-    return (ADDRESS_IN_DRAM_FLASH(vaddr_start) && ADDRESS_IN_DRAM_FLASH(vaddr_end)) || (ADDRESS_IN_DRAM_PSRAM(vaddr_start) && ADDRESS_IN_DRAM_PSRAM(vaddr_end));
+    return (SOC_ADDRESS_IN_DRAM_FLASH(vaddr_start) && SOC_ADDRESS_IN_DRAM_FLASH(vaddr_end)) || (SOC_ADDRESS_IN_DRAM_PSRAM(vaddr_start) && SOC_ADDRESS_IN_DRAM_PSRAM(vaddr_end));
 }
 
 /**
@@ -150,9 +150,9 @@ static inline bool mmu_ll_check_valid_paddr_region(uint32_t mmu_id, uint32_t pad
 {
     int max_paddr_page_num = 0;
     if (mmu_id == MMU_LL_FLASH_MMU_ID) {
-        max_paddr_page_num = MMU_FLASH_MAX_PADDR_PAGE_NUM;
+        max_paddr_page_num = SOC_MMU_FLASH_MAX_PADDR_PAGE_NUM;
     } else if (mmu_id == MMU_LL_PSRAM_MMU_ID) {
-        max_paddr_page_num = MMU_PSRAM_MAX_PADDR_PAGE_NUM;
+        max_paddr_page_num = SOC_MMU_PSRAM_MAX_PADDR_PAGE_NUM;
     } else {
         HAL_ASSERT(false);
     }
@@ -192,7 +192,7 @@ static inline uint32_t mmu_ll_get_entry_id(uint32_t mmu_id, uint32_t vaddr)
         default:
             HAL_ASSERT(shift_code);
     }
-    return ((vaddr & MMU_VADDR_MASK) >> shift_code);
+    return ((vaddr & SOC_MMU_VADDR_MASK) >> shift_code);
 }
 
 /**
@@ -247,15 +247,15 @@ __attribute__((always_inline)) static inline void mmu_ll_write_entry(uint32_t mm
     if (mmu_id == MMU_LL_FLASH_MMU_ID) {
         index_reg = SPI_MEM_C_MMU_ITEM_INDEX_REG;
         content_reg = SPI_MEM_C_MMU_ITEM_CONTENT_REG;
-        sensitive = MMU_FLASH_SENSITIVE;
-        mmu_val |= MMU_FLASH_VALID;
-        mmu_val |= MMU_ACCESS_FLASH;
+        sensitive = SOC_MMU_FLASH_SENSITIVE;
+        mmu_val |= SOC_MMU_FLASH_VALID;
+        mmu_val |= SOC_MMU_ACCESS_FLASH;
     } else if (mmu_id == MMU_LL_PSRAM_MMU_ID) {
         index_reg = SPI_MEM_S_MMU_ITEM_INDEX_REG;
         content_reg = SPI_MEM_S_MMU_ITEM_CONTENT_REG;
-        sensitive = MMU_PSRAM_SENSITIVE;
-        mmu_val |= MMU_PSRAM_VALID;
-        mmu_val |= MMU_ACCESS_PSRAM;
+        sensitive = SOC_MMU_PSRAM_SENSITIVE;
+        mmu_val |= SOC_MMU_PSRAM_VALID;
+        mmu_val |= SOC_MMU_ACCESS_PSRAM;
     } else {
         HAL_ASSERT(false);
     }
@@ -312,11 +312,11 @@ __attribute__((always_inline)) static inline void mmu_ll_set_entry_invalid(uint3
     if (mmu_id == MMU_LL_FLASH_MMU_ID) {
         index_reg = SPI_MEM_C_MMU_ITEM_INDEX_REG;
         content_reg = SPI_MEM_C_MMU_ITEM_CONTENT_REG;
-        invalid_mask = MMU_FLASH_INVALID;
+        invalid_mask = SOC_MMU_FLASH_INVALID;
     } else if (mmu_id == MMU_LL_PSRAM_MMU_ID) {
         index_reg = SPI_MEM_S_MMU_ITEM_INDEX_REG;
         content_reg = SPI_MEM_S_MMU_ITEM_CONTENT_REG;
-        invalid_mask = MMU_PSRAM_INVALID;
+        invalid_mask = SOC_MMU_PSRAM_INVALID;
     } else {
         HAL_ASSERT(false);
     }
@@ -333,7 +333,7 @@ __attribute__((always_inline)) static inline void mmu_ll_set_entry_invalid(uint3
 __attribute__((always_inline))
 static inline void mmu_ll_unmap_all(uint32_t mmu_id)
 {
-    for (int i = 0; i < MMU_ENTRY_NUM; i++) {
+    for (int i = 0; i < SOC_MMU_ENTRY_NUM; i++) {
         mmu_ll_set_entry_invalid(mmu_id, i);
     }
 }
@@ -356,11 +356,11 @@ static inline bool mmu_ll_check_entry_valid(uint32_t mmu_id, uint32_t entry_id)
     if (mmu_id == MMU_LL_FLASH_MMU_ID) {
         index_reg = SPI_MEM_C_MMU_ITEM_INDEX_REG;
         content_reg = SPI_MEM_C_MMU_ITEM_CONTENT_REG;
-        valid_mask = MMU_FLASH_VALID;
+        valid_mask = SOC_MMU_FLASH_VALID;
     } else if (mmu_id == MMU_LL_PSRAM_MMU_ID) {
         index_reg = SPI_MEM_S_MMU_ITEM_INDEX_REG;
         content_reg = SPI_MEM_S_MMU_ITEM_CONTENT_REG;
-        valid_mask = MMU_PSRAM_VALID;
+        valid_mask = SOC_MMU_PSRAM_VALID;
     } else {
         HAL_ASSERT(false);
     }
@@ -410,7 +410,7 @@ static inline mmu_target_t mmu_ll_get_entry_target(uint32_t mmu_id, uint32_t ent
  */
 static inline uint32_t mmu_ll_entry_id_to_paddr_base(uint32_t mmu_id, uint32_t entry_id)
 {
-    HAL_ASSERT(entry_id < MMU_ENTRY_NUM);
+    HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM);
 
     mmu_page_size_t page_size = mmu_ll_get_page_size(mmu_id);
     uint32_t shift_code = 0;
@@ -432,10 +432,10 @@ static inline uint32_t mmu_ll_entry_id_to_paddr_base(uint32_t mmu_id, uint32_t e
     }
     if (mmu_id == MMU_LL_FLASH_MMU_ID) {
         REG_WRITE(SPI_MEM_C_MMU_ITEM_INDEX_REG, entry_id);
-        return (REG_READ(SPI_MEM_C_MMU_ITEM_CONTENT_REG) & MMU_FLASH_VALID_VAL_MASK) << shift_code;
+        return (REG_READ(SPI_MEM_C_MMU_ITEM_CONTENT_REG) & SOC_MMU_FLASH_VALID_VAL_MASK) << shift_code;
     } else if (mmu_id == MMU_LL_PSRAM_MMU_ID) {
         REG_WRITE(SPI_MEM_S_MMU_ITEM_INDEX_REG, entry_id);
-        return (REG_READ(SPI_MEM_S_MMU_ITEM_CONTENT_REG) & MMU_PSRAM_VALID_VAL_MASK) << shift_code;
+        return (REG_READ(SPI_MEM_S_MMU_ITEM_CONTENT_REG) & SOC_MMU_PSRAM_VALID_VAL_MASK) << shift_code;
     } else {
         HAL_ASSERT(false);
     }
@@ -461,16 +461,16 @@ static inline int mmu_ll_find_entry_id_based_on_map_value(uint32_t mmu_id, uint3
     if (mmu_id == MMU_LL_FLASH_MMU_ID) {
         index_reg = SPI_MEM_C_MMU_ITEM_INDEX_REG;
         content_reg = SPI_MEM_C_MMU_ITEM_CONTENT_REG;
-        valid_val_mask = MMU_FLASH_VALID_VAL_MASK;
+        valid_val_mask = SOC_MMU_FLASH_VALID_VAL_MASK;
     } else if (mmu_id == MMU_LL_PSRAM_MMU_ID) {
         index_reg = SPI_MEM_S_MMU_ITEM_INDEX_REG;
         content_reg = SPI_MEM_S_MMU_ITEM_CONTENT_REG;
-        valid_val_mask = MMU_PSRAM_VALID_VAL_MASK;
+        valid_val_mask = SOC_MMU_PSRAM_VALID_VAL_MASK;
     } else {
         HAL_ASSERT(false);
     }
 
-    for (int i = 0; i < MMU_ENTRY_NUM; i++) {
+    for (int i = 0; i < SOC_MMU_ENTRY_NUM; i++) {
         if (mmu_ll_check_entry_valid(mmu_id, i)) {
             if (mmu_ll_get_entry_target(mmu_id, i) == target) {
                 REG_WRITE(index_reg, i);

components/hal/esp32s2/include/hal/cache_ll.h

@@ -420,33 +420,33 @@ static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t v
 
     cache_bus_mask_t mask = 0;
     uint32_t vaddr_end = vaddr_start + len - 1;
-    if (vaddr_start >= IRAM1_ADDRESS_LOW) {
+    if (vaddr_start >= SOC_IRAM1_ADDRESS_LOW) {
         mask |= CACHE_BUS_IBUS1;
-    } else if (vaddr_start >= IRAM0_CACHE_ADDRESS_LOW) {
+    } else if (vaddr_start >= SOC_IRAM0_CACHE_ADDRESS_LOW) {
         mask |= CACHE_BUS_IBUS0;
-        mask |= (vaddr_end >= IRAM1_ADDRESS_LOW) ? CACHE_BUS_IBUS1 : 0;
-    } else if (vaddr_start >= DRAM0_CACHE_ADDRESS_LOW) {
+        mask |= (vaddr_end >= SOC_IRAM1_ADDRESS_LOW) ? CACHE_BUS_IBUS1 : 0;
+    } else if (vaddr_start >= SOC_DRAM0_CACHE_ADDRESS_LOW) {
         mask |= CACHE_BUS_DBUS0;
-        mask |= (vaddr_end >= IRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS0 : 0;
-        mask |= (vaddr_end >= IRAM1_ADDRESS_LOW) ? CACHE_BUS_IBUS1 : 0;
-    } else if (vaddr_start >= DRAM1_ADDRESS_LOW) {
+        mask |= (vaddr_end >= SOC_IRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS0 : 0;
+        mask |= (vaddr_end >= SOC_IRAM1_ADDRESS_LOW) ? CACHE_BUS_IBUS1 : 0;
+    } else if (vaddr_start >= SOC_DRAM1_ADDRESS_LOW) {
         mask |= CACHE_BUS_DBUS1;
-        mask |= (vaddr_end >= DRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_DBUS0 : 0;
-        mask |= (vaddr_end >= IRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS0 : 0;
-        mask |= (vaddr_end >= IRAM1_ADDRESS_LOW) ? CACHE_BUS_IBUS1 : 0;
-    } else if (vaddr_start >= DPORT_CACHE_ADDRESS_LOW) {
+        mask |= (vaddr_end >= SOC_DRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_DBUS0 : 0;
+        mask |= (vaddr_end >= SOC_IRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS0 : 0;
+        mask |= (vaddr_end >= SOC_IRAM1_ADDRESS_LOW) ? CACHE_BUS_IBUS1 : 0;
+    } else if (vaddr_start >= SOC_DPORT_CACHE_ADDRESS_LOW) {
         mask |= CACHE_BUS_DBUS2;
-        mask |= (vaddr_end >= DRAM1_ADDRESS_LOW) ? CACHE_BUS_DBUS1 : 0;
-        mask |= (vaddr_end >= DRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_DBUS0 : 0;
-        mask |= (vaddr_end >= IRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS0 : 0;
-        mask |= (vaddr_end >= IRAM1_ADDRESS_LOW) ? CACHE_BUS_IBUS1 : 0;
-    } else if (vaddr_start >= DROM0_ADDRESS_LOW) {
+        mask |= (vaddr_end >= SOC_DRAM1_ADDRESS_LOW) ? CACHE_BUS_DBUS1 : 0;
+        mask |= (vaddr_end >= SOC_DRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_DBUS0 : 0;
+        mask |= (vaddr_end >= SOC_IRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS0 : 0;
+        mask |= (vaddr_end >= SOC_IRAM1_ADDRESS_LOW) ? CACHE_BUS_IBUS1 : 0;
+    } else if (vaddr_start >= SOC_DROM0_ADDRESS_LOW) {
         mask |= CACHE_BUS_IBUS2;
-        mask |= (vaddr_end >= DPORT_CACHE_ADDRESS_LOW) ? CACHE_BUS_DBUS2 : 0;
-        mask |= (vaddr_end >= DRAM1_ADDRESS_LOW) ? CACHE_BUS_DBUS1 : 0;
-        mask |= (vaddr_end >= DRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_DBUS0 : 0;
-        mask |= (vaddr_end >= IRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS0 : 0;
-        mask |= (vaddr_end >= IRAM1_ADDRESS_LOW) ? CACHE_BUS_IBUS1 : 0;
+        mask |= (vaddr_end >= SOC_DPORT_CACHE_ADDRESS_LOW) ? CACHE_BUS_DBUS2 : 0;
+        mask |= (vaddr_end >= SOC_DRAM1_ADDRESS_LOW) ? CACHE_BUS_DBUS1 : 0;
+        mask |= (vaddr_end >= SOC_DRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_DBUS0 : 0;
+        mask |= (vaddr_end >= SOC_IRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS0 : 0;
+        mask |= (vaddr_end >= SOC_IRAM1_ADDRESS_LOW) ? CACHE_BUS_IBUS1 : 0;
     } else {
         abort();
     }

components/hal/esp32s2/include/hal/mmu_ll.h

@@ -101,11 +101,11 @@ static inline bool mmu_ll_check_valid_ext_vaddr_region(uint32_t mmu_id, uint32_t
     bool valid = false;
 
     if (type & MMU_VADDR_DATA) {
-        valid |= ((vaddr_start >= DROM0_ADDRESS_LOW) && (vaddr_end < DROM0_ADDRESS_HIGH)) || ((vaddr_start >= DPORT_CACHE_ADDRESS_LOW) && (vaddr_end < DRAM0_CACHE_ADDRESS_HIGH));
+        valid |= ((vaddr_start >= SOC_DROM0_ADDRESS_LOW) && (vaddr_end < SOC_DROM0_ADDRESS_HIGH)) || ((vaddr_start >= SOC_DPORT_CACHE_ADDRESS_LOW) && (vaddr_end < SOC_DRAM0_CACHE_ADDRESS_HIGH));
     }
 
     if (type & MMU_VADDR_INSTRUCTION) {
-        valid |= ((vaddr_start >= IRAM0_CACHE_ADDRESS_LOW) && (vaddr_end < IRAM1_ADDRESS_HIGH));
+        valid |= ((vaddr_start >= SOC_IRAM0_CACHE_ADDRESS_LOW) && (vaddr_end < SOC_IRAM1_ADDRESS_HIGH));
     }
 
     return valid;
@@ -124,9 +124,9 @@ static inline bool mmu_ll_check_valid_ext_vaddr_region(uint32_t mmu_id, uint32_t
 static inline bool mmu_ll_check_valid_paddr_region(uint32_t mmu_id, uint32_t paddr_start, uint32_t len)
 {
     (void)mmu_id;
-    return (paddr_start < (mmu_ll_get_page_size(mmu_id) * MMU_MAX_PADDR_PAGE_NUM)) &&
-           (len < (mmu_ll_get_page_size(mmu_id) * MMU_MAX_PADDR_PAGE_NUM)) &&
-           ((paddr_start + len - 1) < (mmu_ll_get_page_size(mmu_id) * MMU_MAX_PADDR_PAGE_NUM));
+    return (paddr_start < (mmu_ll_get_page_size(mmu_id) * SOC_MMU_MAX_PADDR_PAGE_NUM)) &&
+           (len < (mmu_ll_get_page_size(mmu_id) * SOC_MMU_MAX_PADDR_PAGE_NUM)) &&
+           ((paddr_start + len - 1) < (mmu_ll_get_page_size(mmu_id) * SOC_MMU_MAX_PADDR_PAGE_NUM));
 }
 
 /**
@@ -144,23 +144,23 @@ static inline uint32_t mmu_ll_get_entry_id(uint32_t mmu_id, uint32_t vaddr)
     (void)mmu_id;
     uint32_t offset = 0;
 
-    if (ADDRESS_IN_DROM0(vaddr)) {
+    if (SOC_ADDRESS_IN_DROM0(vaddr)) {
         offset = PRO_CACHE_IBUS2_MMU_START / 4;
-    } else if (ADDRESS_IN_IRAM0_CACHE(vaddr)) {
+    } else if (SOC_ADDRESS_IN_IRAM0_CACHE(vaddr)) {
         offset = PRO_CACHE_IBUS0_MMU_START / 4;
-    } else if (ADDRESS_IN_IRAM1(vaddr)) {
+    } else if (SOC_ADDRESS_IN_IRAM1(vaddr)) {
         offset = PRO_CACHE_IBUS1_MMU_START / 4;
-    } else if (ADDRESS_IN_DPORT_CACHE(vaddr)) {
+    } else if (SOC_ADDRESS_IN_DPORT_CACHE(vaddr)) {
         offset = PRO_CACHE_DBUS2_MMU_START / 4;
-    } else if (ADDRESS_IN_DRAM1(vaddr)) {
+    } else if (SOC_ADDRESS_IN_DRAM1(vaddr)) {
         offset = PRO_CACHE_DBUS1_MMU_START / 4;
-    } else if (ADDRESS_IN_DRAM0_CACHE(vaddr)) {
+    } else if (SOC_ADDRESS_IN_DRAM0_CACHE(vaddr)) {
         offset = PRO_CACHE_DBUS0_MMU_START / 4;
     } else {
         HAL_ASSERT(false);
     }
 
-    return offset + ((vaddr & MMU_VADDR_MASK) >> 16);
+    return offset + ((vaddr & SOC_MMU_VADDR_MASK) >> 16);
 }
 
 /**
@@ -193,10 +193,10 @@ __attribute__((always_inline))
 static inline void mmu_ll_write_entry(uint32_t mmu_id, uint32_t entry_id, uint32_t mmu_val, mmu_target_t target)
 {
     (void)mmu_id;
-    HAL_ASSERT(entry_id < MMU_ENTRY_NUM);
+    HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM);
 
-    uint32_t target_code = (target == MMU_TARGET_FLASH0) ? MMU_ACCESS_FLASH : MMU_ACCESS_SPIRAM;
-    *(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = mmu_val | target_code | MMU_VALID;
+    uint32_t target_code = (target == MMU_TARGET_FLASH0) ? SOC_MMU_ACCESS_FLASH : SOC_MMU_ACCESS_SPIRAM;
+    *(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = mmu_val | target_code | SOC_MMU_VALID;
 }
 
 /**
@@ -210,7 +210,7 @@ __attribute__((always_inline))
 static inline uint32_t mmu_ll_read_entry(uint32_t mmu_id, uint32_t entry_id)
 {
     (void)mmu_id;
-    HAL_ASSERT(entry_id < MMU_ENTRY_NUM);
+    HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM);
 
     return *(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4);
 }
@@ -225,9 +225,9 @@ __attribute__((always_inline))
 static inline void mmu_ll_set_entry_invalid(uint32_t mmu_id, uint32_t entry_id)
 {
     (void)mmu_id;
-    HAL_ASSERT(entry_id < MMU_ENTRY_NUM);
+    HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM);
 
-    *(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = MMU_INVALID;
+    *(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = SOC_MMU_INVALID;
 }
 
 /**
@@ -238,7 +238,7 @@ static inline void mmu_ll_set_entry_invalid(uint32_t mmu_id, uint32_t entry_id)
 __attribute__((always_inline))
 static inline void mmu_ll_unmap_all(uint32_t mmu_id)
 {
-    for (int i = 0; i < MMU_ENTRY_NUM; i++) {
+    for (int i = 0; i < SOC_MMU_ENTRY_NUM; i++) {
         mmu_ll_set_entry_invalid(mmu_id, i);
     }
 }
@@ -254,9 +254,9 @@ static inline void mmu_ll_unmap_all(uint32_t mmu_id)
 static inline bool mmu_ll_check_entry_valid(uint32_t mmu_id, uint32_t entry_id)
 {
     (void)mmu_id;
-    HAL_ASSERT(entry_id < MMU_ENTRY_NUM);
+    HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM);
 
-    return (*(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) & MMU_INVALID) ? false : true;
+    return (*(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) & SOC_MMU_INVALID) ? false : true;
 }
 
 /**
@@ -271,7 +271,7 @@ static inline mmu_target_t mmu_ll_get_entry_target(uint32_t mmu_id, uint32_t ent
 {
     HAL_ASSERT(mmu_ll_check_entry_valid(mmu_id, entry_id));
 
-    if ((*(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4)) & MMU_ACCESS_FLASH) {
+    if ((*(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4)) & SOC_MMU_ACCESS_FLASH) {
         return MMU_TARGET_FLASH0;
     } else {
         return MMU_TARGET_PSRAM0;
@@ -291,7 +291,7 @@ static inline uint32_t mmu_ll_entry_id_to_paddr_base(uint32_t mmu_id, uint32_t e
 {
     (void)mmu_id;
 
-    return ((*(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4)) & MMU_VALID_VAL_MASK) << 16;
+    return ((*(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4)) & SOC_MMU_VALID_VAL_MASK) << 16;
 }
 
 /**
@@ -308,10 +308,10 @@ static inline uint32_t mmu_ll_entry_id_to_paddr_base(uint32_t mmu_id, uint32_t e
 static inline int mmu_ll_find_entry_id_based_on_map_value(uint32_t mmu_id, uint32_t mmu_val, mmu_target_t target)
 {
     (void)mmu_id;
-    for (int i = 0; i < MMU_ENTRY_NUM; i++) {
+    for (int i = 0; i < SOC_MMU_ENTRY_NUM; i++) {
         if (mmu_ll_check_entry_valid(mmu_id, i)) {
             if (mmu_ll_get_entry_target(mmu_id, i) == target) {
-                if (((*(uint32_t *)(DR_REG_MMU_TABLE + i * 4)) & MMU_VALID_VAL_MASK) == mmu_val) {
+                if (((*(uint32_t *)(DR_REG_MMU_TABLE + i * 4)) & SOC_MMU_VALID_VAL_MASK) == mmu_val) {
                     return i;
                 }
             }

components/hal/esp32s3/include/hal/cache_ll.h

@@ -512,9 +512,9 @@ static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t v
 
     cache_bus_mask_t mask = 0;
     uint32_t vaddr_end = vaddr_start + len - 1;
-    if (vaddr_start >= IRAM0_CACHE_ADDRESS_LOW && vaddr_end < IRAM0_CACHE_ADDRESS_HIGH) {
+    if (vaddr_start >= SOC_IRAM0_CACHE_ADDRESS_LOW && vaddr_end < SOC_IRAM0_CACHE_ADDRESS_HIGH) {
         mask |= CACHE_BUS_IBUS0;    //Both cores have their own IBUS0
-    } else if (vaddr_start >= DRAM0_CACHE_ADDRESS_LOW && vaddr_end < DRAM0_CACHE_ADDRESS_HIGH) {
+    } else if (vaddr_start >= SOC_DRAM0_CACHE_ADDRESS_LOW && vaddr_end < SOC_DRAM0_CACHE_ADDRESS_HIGH) {
         mask |= CACHE_BUS_DBUS0;    //Both cores have their own DBUS0
     } else {
         HAL_ASSERT(0);      //Out of region

components/hal/esp32s3/include/hal/mmu_ll.h

@@ -100,11 +100,11 @@ static inline bool mmu_ll_check_valid_ext_vaddr_region(uint32_t mmu_id, uint32_t
     bool valid = false;
 
     if (type & MMU_VADDR_INSTRUCTION) {
-        valid |= (ADDRESS_IN_IRAM0_CACHE(vaddr_start) && ADDRESS_IN_IRAM0_CACHE(vaddr_end));
+        valid |= (SOC_ADDRESS_IN_IRAM0_CACHE(vaddr_start) && SOC_ADDRESS_IN_IRAM0_CACHE(vaddr_end));
     }
 
     if (type & MMU_VADDR_DATA) {
-        valid |= (ADDRESS_IN_DRAM0_CACHE(vaddr_start) && ADDRESS_IN_DRAM0_CACHE(vaddr_end));
+        valid |= (SOC_ADDRESS_IN_DRAM0_CACHE(vaddr_start) && SOC_ADDRESS_IN_DRAM0_CACHE(vaddr_end));
     }
 
     return valid;
@@ -123,9 +123,9 @@ static inline bool mmu_ll_check_valid_ext_vaddr_region(uint32_t mmu_id, uint32_t
 static inline bool mmu_ll_check_valid_paddr_region(uint32_t mmu_id, uint32_t paddr_start, uint32_t len)
 {
     (void)mmu_id;
-    return (paddr_start < (mmu_ll_get_page_size(mmu_id) * MMU_MAX_PADDR_PAGE_NUM)) &&
-           (len < (mmu_ll_get_page_size(mmu_id) * MMU_MAX_PADDR_PAGE_NUM)) &&
-           ((paddr_start + len - 1) < (mmu_ll_get_page_size(mmu_id) * MMU_MAX_PADDR_PAGE_NUM));
+    return (paddr_start < (mmu_ll_get_page_size(mmu_id) * SOC_MMU_MAX_PADDR_PAGE_NUM)) &&
+           (len < (mmu_ll_get_page_size(mmu_id) * SOC_MMU_MAX_PADDR_PAGE_NUM)) &&
+           ((paddr_start + len - 1) < (mmu_ll_get_page_size(mmu_id) * SOC_MMU_MAX_PADDR_PAGE_NUM));
 }
 
 /**
@@ -141,7 +141,7 @@ __attribute__((always_inline))
 static inline uint32_t mmu_ll_get_entry_id(uint32_t mmu_id, uint32_t vaddr)
 {
     (void)mmu_id;
-    return ((vaddr & MMU_VADDR_MASK) >> 16);
+    return ((vaddr & SOC_MMU_VADDR_MASK) >> 16);
 }
 
 /**
@@ -174,10 +174,10 @@ __attribute__((always_inline))
 static inline void mmu_ll_write_entry(uint32_t mmu_id, uint32_t entry_id, uint32_t mmu_val, mmu_target_t target)
 {
     (void)mmu_id;
-    HAL_ASSERT(entry_id < MMU_ENTRY_NUM);
+    HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM);
 
-    uint32_t target_code = (target == MMU_TARGET_FLASH0) ? MMU_ACCESS_FLASH : MMU_ACCESS_SPIRAM;
-    *(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = mmu_val | target_code | MMU_VALID;
+    uint32_t target_code = (target == MMU_TARGET_FLASH0) ? SOC_MMU_ACCESS_FLASH : SOC_MMU_ACCESS_SPIRAM;
+    *(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = mmu_val | target_code | SOC_MMU_VALID;
 }
 
 /**
@@ -191,7 +191,7 @@ __attribute__((always_inline))
 static inline uint32_t mmu_ll_read_entry(uint32_t mmu_id, uint32_t entry_id)
 {
     (void)mmu_id;
-    HAL_ASSERT(entry_id < MMU_ENTRY_NUM);
+    HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM);
 
     return *(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4);
 }
@@ -206,9 +206,9 @@ __attribute__((always_inline))
 static inline void mmu_ll_set_entry_invalid(uint32_t mmu_id, uint32_t entry_id)
 {
     (void)mmu_id;
-    HAL_ASSERT(entry_id < MMU_ENTRY_NUM);
+    HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM);
 
-    *(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = MMU_INVALID;
+    *(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) = SOC_MMU_INVALID;
 }
 
 /**
@@ -219,7 +219,7 @@ static inline void mmu_ll_set_entry_invalid(uint32_t mmu_id, uint32_t entry_id)
 __attribute__((always_inline))
 static inline void mmu_ll_unmap_all(uint32_t mmu_id)
 {
-    for (int i = 0; i < MMU_ENTRY_NUM; i++) {
+    for (int i = 0; i < SOC_MMU_ENTRY_NUM; i++) {
         mmu_ll_set_entry_invalid(mmu_id, i);
     }
 }
@@ -235,9 +235,9 @@ static inline void mmu_ll_unmap_all(uint32_t mmu_id)
 static inline bool mmu_ll_check_entry_valid(uint32_t mmu_id, uint32_t entry_id)
 {
     (void)mmu_id;
-    HAL_ASSERT(entry_id < MMU_ENTRY_NUM);
+    HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM);
 
-    return (*(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) & MMU_INVALID) ? false : true;
+    return (*(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4) & SOC_MMU_INVALID) ? false : true;
 }
 
 /**
@@ -251,10 +251,10 @@ static inline bool mmu_ll_check_entry_valid(uint32_t mmu_id, uint32_t entry_id)
 static inline mmu_target_t mmu_ll_get_entry_target(uint32_t mmu_id, uint32_t entry_id)
 {
     (void)mmu_id;
-    HAL_ASSERT(entry_id < MMU_ENTRY_NUM);
+    HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM);
 
-    bool target_code = (*(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4)) & MMU_TYPE;
-    return (target_code == MMU_ACCESS_FLASH) ? MMU_TARGET_FLASH0 : MMU_TARGET_PSRAM0;
+    bool target_code = (*(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4)) & SOC_MMU_TYPE;
+    return (target_code == SOC_MMU_ACCESS_FLASH) ? MMU_TARGET_FLASH0 : MMU_TARGET_PSRAM0;
 }
 
 /**
@@ -268,9 +268,9 @@ static inline mmu_target_t mmu_ll_get_entry_target(uint32_t mmu_id, uint32_t ent
 static inline uint32_t mmu_ll_entry_id_to_paddr_base(uint32_t mmu_id, uint32_t entry_id)
 {
     (void)mmu_id;
-    HAL_ASSERT(entry_id < MMU_ENTRY_NUM);
+    HAL_ASSERT(entry_id < SOC_MMU_ENTRY_NUM);
 
-    return ((*(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4)) & MMU_VALID_VAL_MASK) << 16;
+    return ((*(uint32_t *)(DR_REG_MMU_TABLE + entry_id * 4)) & SOC_MMU_VALID_VAL_MASK) << 16;
 }
 
 /**
@@ -287,10 +287,10 @@ static inline uint32_t mmu_ll_entry_id_to_paddr_base(uint32_t mmu_id, uint32_t e
 static inline int mmu_ll_find_entry_id_based_on_map_value(uint32_t mmu_id, uint32_t mmu_val, mmu_target_t target)
 {
     (void)mmu_id;
-    for (int i = 0; i < MMU_ENTRY_NUM; i++) {
+    for (int i = 0; i < SOC_MMU_ENTRY_NUM; i++) {
         if (mmu_ll_check_entry_valid(mmu_id, i)) {
             if (mmu_ll_get_entry_target(mmu_id, i) == target) {
-                if (((*(uint32_t *)(DR_REG_MMU_TABLE + i * 4)) & MMU_VALID_VAL_MASK) == mmu_val) {
+                if (((*(uint32_t *)(DR_REG_MMU_TABLE + i * 4)) & SOC_MMU_VALID_VAL_MASK) == mmu_val) {
                     return i;
                 }
             }

components/soc/esp32/include/soc/ext_mem_defs.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -13,45 +13,45 @@
 extern "C" {
 #endif
 
-#define IRAM0_CACHE_ADDRESS_LOW     0x400D0000
-#define IRAM0_CACHE_ADDRESS_HIGH    0x40400000
+#define SOC_IRAM0_CACHE_ADDRESS_LOW     0x400D0000
+#define SOC_IRAM0_CACHE_ADDRESS_HIGH    0x40400000
 
-#define IRAM1_CACHE_ADDRESS_LOW     0x40400000
-#define IRAM1_CACHE_ADDRESS_HIGH    0x40800000
+#define SOC_IRAM1_CACHE_ADDRESS_LOW     0x40400000
+#define SOC_IRAM1_CACHE_ADDRESS_HIGH    0x40800000
 
-#define IROM0_CACHE_ADDRESS_LOW     0x40800000
-#define IROM0_CACHE_ADDRESS_HIGH    0x40C00000
+#define SOC_IROM0_CACHE_ADDRESS_LOW     0x40800000
+#define SOC_IROM0_CACHE_ADDRESS_HIGH    0x40C00000
 
-#define DRAM1_CACHE_ADDRESS_LOW     0x3F800000
-#define DRAM1_CACHE_ADDRESS_HIGH    0x3FC00000
+#define SOC_DRAM1_CACHE_ADDRESS_LOW     0x3F800000
+#define SOC_DRAM1_CACHE_ADDRESS_HIGH    0x3FC00000
 
-#define DROM0_CACHE_ADDRESS_LOW     0x3F400000
-#define DROM0_CACHE_ADDRESS_HIGH    0x3F800000
+#define SOC_DROM0_CACHE_ADDRESS_LOW     0x3F400000
+#define SOC_DROM0_CACHE_ADDRESS_HIGH    0x3F800000
 
 
-#define BUS_SIZE(bus_name)                 (bus_name##_ADDRESS_HIGH - bus_name##_ADDRESS_LOW)
-#define ADDRESS_IN_BUS(bus_name, vaddr)    ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH)
-#define ADDRESS_IN_IRAM0_CACHE(vaddr)      ADDRESS_IN_BUS(IRAM0_CACHE, vaddr)
-#define ADDRESS_IN_IRAM1_CACHE(vaddr)      ADDRESS_IN_BUS(IRAM1_CACHE, vaddr)
-#define ADDRESS_IN_IROM0_CACHE(vaddr)      ADDRESS_IN_BUS(IROM0_CACHE, vaddr)
-#define ADDRESS_IN_DRAM1_CACHE(vaddr)      ADDRESS_IN_BUS(DRAM1_CACHE, vaddr)
-#define ADDRESS_IN_DROM0_CACHE(vaddr)      ADDRESS_IN_BUS(DROM0_CACHE, vaddr)
+#define SOC_BUS_SIZE(bus_name)                     (bus_name##_ADDRESS_HIGH - bus_name##_ADDRESS_LOW)
+#define SOC_ADDRESS_IN_BUS(bus_name, vaddr)        ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH)
+#define SOC_ADDRESS_IN_IRAM0_CACHE(vaddr)          SOC_ADDRESS_IN_BUS(SOC_IRAM0_CACHE, vaddr)
+#define SOC_ADDRESS_IN_IRAM1_CACHE(vaddr)          SOC_ADDRESS_IN_BUS(SOC_IRAM1_CACHE, vaddr)
+#define SOC_ADDRESS_IN_IROM0_CACHE(vaddr)          SOC_ADDRESS_IN_BUS(SOC_IROM0_CACHE, vaddr)
+#define SOC_ADDRESS_IN_DRAM1_CACHE(vaddr)          SOC_ADDRESS_IN_BUS(SOC_DRAM1_CACHE, vaddr)
+#define SOC_ADDRESS_IN_DROM0_CACHE(vaddr)          SOC_ADDRESS_IN_BUS(SOC_DROM0_CACHE, vaddr)
 
-#define MMU_INVALID                           BIT(8)
+#define SOC_MMU_INVALID                       BIT(8)
 
 /**
  * Max MMU available paddr page num.
- * `MMU_MAX_PADDR_PAGE_NUM * SOC_MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.:
+ * `SOC_MMU_MAX_PADDR_PAGE_NUM * SOC_MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.:
  * 256 * 64KB, means MMU can support 16MB paddr at most
  */
-#define MMU_MAX_PADDR_PAGE_NUM    256
+#define SOC_MMU_MAX_PADDR_PAGE_NUM            256
 /**
  * This is the mask used for mapping. e.g.:
- * 0x4008_0000 & MMU_VADDR_MASK
+ * 0x4008_0000 & SOC_MMU_VADDR_MASK
  */
-#define MMU_VADDR_MASK  0x3FFFFF
+#define SOC_MMU_VADDR_MASK                    0x3FFFFF
 //MMU entry num, 384 entries that are used in IDF for Flash
-#define MMU_ENTRY_NUM                         384
+#define SOC_MMU_ENTRY_NUM                     384
 
 
 #define SOC_MMU_DBUS_VADDR_BASE               0x3E000000
@@ -68,20 +68,20 @@ extern "C" {
  */
 #define SOC_MMU_LINEAR_ADDR_MASK              0x1FFFFFF
 
-#define SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW      (IRAM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
-#define SOC_MMU_IRAM0_LINEAR_ADDRESS_HIGH     (IRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
+#define SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW      (SOC_IRAM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
+#define SOC_MMU_IRAM0_LINEAR_ADDRESS_HIGH     (SOC_IRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
 
-#define SOC_MMU_IRAM1_LINEAR_ADDRESS_LOW      (IRAM1_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
-#define SOC_MMU_IRAM1_LINEAR_ADDRESS_HIGH     (IRAM1_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
+#define SOC_MMU_IRAM1_LINEAR_ADDRESS_LOW      (SOC_IRAM1_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
+#define SOC_MMU_IRAM1_LINEAR_ADDRESS_HIGH     (SOC_IRAM1_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
 
-#define SOC_MMU_IROM0_LINEAR_ADDRESS_LOW      (IROM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
-#define SOC_MMU_IROM0_LINEAR_ADDRESS_HIGH     (IROM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
+#define SOC_MMU_IROM0_LINEAR_ADDRESS_LOW      (SOC_IROM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
+#define SOC_MMU_IROM0_LINEAR_ADDRESS_HIGH     (SOC_IROM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
 
-#define SOC_MMU_DROM0_LINEAR_ADDRESS_LOW      (DROM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
-#define SOC_MMU_DROM0_LINEAR_ADDRESS_HIGH     (DROM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
+#define SOC_MMU_DROM0_LINEAR_ADDRESS_LOW      (SOC_DROM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
+#define SOC_MMU_DROM0_LINEAR_ADDRESS_HIGH     (SOC_DROM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
 
-#define SOC_MMU_DRAM1_LINEAR_ADDRESS_LOW      (DRAM1_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
-#define SOC_MMU_DRAM1_LINEAR_ADDRESS_HIGH     (DRAM1_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
+#define SOC_MMU_DRAM1_LINEAR_ADDRESS_LOW      (SOC_DRAM1_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
+#define SOC_MMU_DRAM1_LINEAR_ADDRESS_HIGH     (SOC_DRAM1_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
 
 
 

components/soc/esp32c2/include/soc/ext_mem_defs.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -23,91 +23,50 @@ extern "C" {
 
 
 /*IRAM0 is connected with Cache IBUS0*/
-#define IRAM0_ADDRESS_LOW                      0x4037C000
-#define IRAM0_ADDRESS_HIGH                     0x403C0000
-#define IRAM0_CACHE_ADDRESS_LOW                0x42000000
-#define IRAM0_CACHE_ADDRESS_HIGH               (IRAM0_CACHE_ADDRESS_LOW + ((SOC_MMU_PAGE_SIZE) * MMU_ENTRY_NUM)) // MMU has 64 pages
+#define SOC_IRAM0_ADDRESS_LOW                      0x4037C000
+#define SOC_IRAM0_ADDRESS_HIGH                     0x403C0000
+#define SOC_IRAM0_CACHE_ADDRESS_LOW                0x42000000
+#define SOC_IRAM0_CACHE_ADDRESS_HIGH               (SOC_IRAM0_CACHE_ADDRESS_LOW + ((SOC_MMU_PAGE_SIZE) * SOC_MMU_ENTRY_NUM)) // MMU has 64 pages
 
 /*DRAM0 is connected with Cache DBUS0*/
-#define DRAM0_ADDRESS_LOW                      0x3FCA0000
-#define DRAM0_ADDRESS_HIGH                     0x3FCE0000
-#define DRAM0_CACHE_ADDRESS_LOW                0x3C000000
-#define DRAM0_CACHE_ADDRESS_HIGH               (DRAM0_CACHE_ADDRESS_LOW + ((SOC_MMU_PAGE_SIZE) * MMU_ENTRY_NUM)) // MMU has 64 pages
-#define DRAM0_CACHE_OPERATION_HIGH             DRAM0_CACHE_ADDRESS_HIGH
+#define SOC_DRAM0_ADDRESS_LOW                      0x3FCA0000
+#define SOC_DRAM0_ADDRESS_HIGH                     0x3FCE0000
+#define SOC_DRAM0_CACHE_ADDRESS_LOW                0x3C000000
+#define SOC_DRAM0_CACHE_ADDRESS_HIGH               (SOC_DRAM0_CACHE_ADDRESS_LOW + ((SOC_MMU_PAGE_SIZE) * SOC_MMU_ENTRY_NUM)) // MMU has 64 pages
 
-#define BUS_SIZE(bus_name)                 (bus_name##_ADDRESS_HIGH - bus_name##_ADDRESS_LOW)
-#define ADDRESS_IN_BUS(bus_name, vaddr)    ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH)
+#define SOC_BUS_SIZE(bus_name)                     (bus_name##_ADDRESS_HIGH - bus_name##_ADDRESS_LOW)
+#define SOC_ADDRESS_IN_BUS(bus_name, vaddr)        ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH)
 
-#define ADDRESS_IN_IRAM0(vaddr)            ADDRESS_IN_BUS(IRAM0, vaddr)
-#define ADDRESS_IN_IRAM0_CACHE(vaddr)      ADDRESS_IN_BUS(IRAM0_CACHE, vaddr)
-#define ADDRESS_IN_DRAM0(vaddr)            ADDRESS_IN_BUS(DRAM0, vaddr)
-#define ADDRESS_IN_DRAM0_CACHE(vaddr)      ADDRESS_IN_BUS(DRAM0_CACHE, vaddr)
+#define SOC_ADDRESS_IN_IRAM0(vaddr)                    SOC_ADDRESS_IN_BUS(SOC_IRAM0, vaddr)
+#define SOC_ADDRESS_IN_IRAM0_CACHE(vaddr)              SOC_ADDRESS_IN_BUS(SOC_IRAM0_CACHE, vaddr)
+#define SOC_ADDRESS_IN_DRAM0(vaddr)                    SOC_ADDRESS_IN_BUS(SOC_DRAM0, vaddr)
+#define SOC_ADDRESS_IN_DRAM0_CACHE(vaddr)              SOC_ADDRESS_IN_BUS(SOC_DRAM0_CACHE, vaddr)
 
-#define BUS_IRAM0_CACHE_SIZE              BUS_SIZE(IRAM0_CACHE)
-#define BUS_DRAM0_CACHE_SIZE              BUS_SIZE(DRAM0_CACHE)
-
-#define CACHE_IBUS                      0
-#define CACHE_IBUS_MMU_START            0
-#define CACHE_IBUS_MMU_END              0x100
-
-#define CACHE_DBUS                      1
-#define CACHE_DBUS_MMU_START            0
-#define CACHE_DBUS_MMU_END              0x100
-
-//TODO, remove these cache function dependencies
-#define CACHE_IROM_MMU_START            0
-#define CACHE_IROM_MMU_END              Cache_Get_IROM_MMU_End()
-#define CACHE_IROM_MMU_SIZE             (CACHE_IROM_MMU_END - CACHE_IROM_MMU_START)
-
-#define CACHE_DROM_MMU_START            CACHE_IROM_MMU_END
-#define CACHE_DROM_MMU_END              Cache_Get_DROM_MMU_End()
-#define CACHE_DROM_MMU_SIZE             (CACHE_DROM_MMU_END - CACHE_DROM_MMU_START)
-
-#define CACHE_DROM_MMU_MAX_END          0x100
-
-#define ICACHE_MMU_SIZE                 0x100
-#define DCACHE_MMU_SIZE                 0x100
-
-#define MMU_BUS_START(i)                0
-#define MMU_BUS_SIZE(i)                 0x100
-
-#define MMU_INVALID                     BIT(6)
-#define MMU_VALID                       0
-#define MMU_TYPE                        0
-#define MMU_ACCESS_FLASH                0
-
-#define CACHE_MAX_SYNC_NUM 0x400000
-#define CACHE_MAX_LOCK_NUM 0x8000
+#define SOC_MMU_INVALID                     BIT(6)
+#define SOC_MMU_VALID                       0
+#define SOC_MMU_TYPE                        0
+#define SOC_MMU_ACCESS_FLASH                0
 
 /**
  * MMU entry valid bit mask for mapping value. For an entry:
  * valid bit + value bits
  * valid bit is BIT(6), so value bits are 0x3f
  */
-#define MMU_VALID_VAL_MASK 		        0x3f
+#define SOC_MMU_VALID_VAL_MASK 		        0x3f
 
 /**
  * Max MMU available paddr page num.
- * `MMU_MAX_PADDR_PAGE_NUM * SOC_MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.:
+ * `SOC_MMU_MAX_PADDR_PAGE_NUM * SOC_MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.:
  * 64 * 64KB, means MMU can support 4MB paddr at most
  */
-#define MMU_MAX_PADDR_PAGE_NUM    64
+#define SOC_MMU_MAX_PADDR_PAGE_NUM    64
 /**
  * This is the mask used for mapping. e.g.:
- * 0x4200_0000 & MMU_VADDR_MASK
+ * 0x4200_0000 & SOC_MMU_VADDR_MASK
  */
-#define MMU_VADDR_MASK                 ((SOC_MMU_PAGE_SIZE) * 64 - 1)
+#define SOC_MMU_VADDR_MASK                 ((SOC_MMU_PAGE_SIZE) * 64 - 1)
 //MMU entry num
-#define MMU_ENTRY_NUM  64
-
-#define BUS_PMS_MASK  0xffffff
-
-#define CACHE_ICACHE_LOW_SHIFT         0
-#define CACHE_ICACHE_HIGH_SHIFT        2
-#define CACHE_DCACHE_LOW_SHIFT         4
-#define CACHE_DCACHE_HIGH_SHIFT        6
-
-#define CACHE_MEMORY_IBANK0_ADDR        0x4037C000
+#define SOC_MMU_ENTRY_NUM  64
 
 #define SOC_MMU_DBUS_VADDR_BASE               0x3C000000
 #define SOC_MMU_IBUS_VADDR_BASE               0x42000000
@@ -148,16 +107,16 @@ extern "C" {
  * - If high linear address is 0, this means MMU linear address range is equal or smaller than vaddr range.
  *   Under this condition, we use the max linear space.
  */
-#define SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW      (IRAM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
-#if ((IRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) > 0)
-#define SOC_MMU_IRAM0_LINEAR_ADDRESS_HIGH     (IRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
+#define SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW      (SOC_IRAM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
+#if ((SOC_IRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) > 0)
+#define SOC_MMU_IRAM0_LINEAR_ADDRESS_HIGH     (SOC_IRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
 #else
 #define SOC_MMU_IRAM0_LINEAR_ADDRESS_HIGH     (SOC_MMU_LINEAR_ADDR_MASK + 1)
 #endif
 
-#define SOC_MMU_DRAM0_LINEAR_ADDRESS_LOW      (DRAM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
-#if ((DRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) > 0)
-#define SOC_MMU_DRAM0_LINEAR_ADDRESS_HIGH     (DRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
+#define SOC_MMU_DRAM0_LINEAR_ADDRESS_LOW      (SOC_DRAM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
+#if ((SOC_DRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) > 0)
+#define SOC_MMU_DRAM0_LINEAR_ADDRESS_HIGH     (SOC_DRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
 #else
 #define SOC_MMU_DRAM0_LINEAR_ADDRESS_HIGH     (SOC_MMU_LINEAR_ADDR_MASK + 1)
 #endif
@@ -168,6 +127,36 @@ extern "C" {
 _Static_assert(SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW == SOC_MMU_DRAM0_LINEAR_ADDRESS_LOW, "IRAM0 and DRAM0 linear address should be same");
 
 
+/**
+ * ROM flash mmap driver needs below definitions
+ */
+#define BUS_IRAM0_CACHE_SIZE              SOC_BUS_SIZE(SOC_IRAM0_CACHE)
+#define BUS_DRAM0_CACHE_SIZE              SOC_BUS_SIZE(SOC_DRAM0_CACHE)
+
+#define CACHE_IBUS                      0
+#define CACHE_IBUS_MMU_START            0
+#define CACHE_IBUS_MMU_END              0x100
+
+#define CACHE_DBUS                      1
+#define CACHE_DBUS_MMU_START            0
+#define CACHE_DBUS_MMU_END              0x100
+
+#define CACHE_IROM_MMU_START            0
+#define CACHE_IROM_MMU_END              Cache_Get_IROM_MMU_End()
+#define CACHE_IROM_MMU_SIZE             (CACHE_IROM_MMU_END - CACHE_IROM_MMU_START)
+
+#define CACHE_DROM_MMU_START            CACHE_IROM_MMU_END
+#define CACHE_DROM_MMU_END              Cache_Get_DROM_MMU_End()
+#define CACHE_DROM_MMU_SIZE             (CACHE_DROM_MMU_END - CACHE_DROM_MMU_START)
+
+#define CACHE_DROM_MMU_MAX_END          0x100
+
+#define ICACHE_MMU_SIZE                 0x100
+#define DCACHE_MMU_SIZE                 0x100
+
+#define MMU_BUS_START(i)                0
+#define MMU_BUS_SIZE(i)                 0x100
+
 #ifdef __cplusplus
 }
 #endif

components/soc/esp32c2/include/soc/mmu.h

@@ -20,9 +20,9 @@ extern "C" {
 #define SOC_MMU_IROM0_PAGES_END                 (CACHE_IROM_MMU_END / sizeof(uint32_t))
 #define SOC_MMU_DROM0_PAGES_START               (CACHE_DROM_MMU_START / sizeof(uint32_t))
 #define SOC_MMU_DROM0_PAGES_END                 (CACHE_DROM_MMU_END / sizeof(uint32_t))
-#define SOC_MMU_ADDR_MASK                       MMU_VALID_VAL_MASK
+#define SOC_MMU_ADDR_MASK                       SOC_MMU_VALID_VAL_MASK
 #define SOC_MMU_PAGE_IN_FLASH(page)             (page) //Always in Flash
-#define SOC_MMU_VADDR1_START_ADDR               IRAM0_CACHE_ADDRESS_LOW
+#define SOC_MMU_VADDR1_START_ADDR               SOC_IRAM0_CACHE_ADDRESS_LOW
 #define SOC_MMU_PRO_IRAM0_FIRST_USABLE_PAGE     SOC_MMU_IROM0_PAGES_START
 #define SOC_MMU_VADDR0_START_ADDR               (SOC_DROM_LOW + (SOC_MMU_DROM0_PAGES_START * SPI_FLASH_MMU_PAGE_SIZE))
 #define SOC_MMU_VADDR1_FIRST_USABLE_ADDR        SOC_IROM_LOW

components/soc/esp32c3/include/soc/ext_mem_defs.h

@@ -1,10 +1,9 @@
 /*
- * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
-#ifndef _CACHE_MEMORY_H_
-#define _CACHE_MEMORY_H_
+#pragma once
 
 #include "esp_bit_defs.h"
 
@@ -13,88 +12,49 @@ extern "C" {
 #endif
 
 /*IRAM0 is connected with Cache IBUS0*/
-#define IRAM0_ADDRESS_LOW               0x4037C000
-#define IRAM0_ADDRESS_HIGH              0x403E0000
-#define IRAM0_CACHE_ADDRESS_LOW	        0x42000000
-#define IRAM0_CACHE_ADDRESS_HIGH        0x42800000
+#define SOC_IRAM0_ADDRESS_LOW               0x4037C000
+#define SOC_IRAM0_ADDRESS_HIGH              0x403E0000
+#define SOC_IRAM0_CACHE_ADDRESS_LOW	        0x42000000
+#define SOC_IRAM0_CACHE_ADDRESS_HIGH        0x42800000
 
 /*DRAM0 is connected with Cache DBUS0*/
-#define DRAM0_ADDRESS_LOW               0x3FC80000
-#define DRAM0_ADDRESS_HIGH              0x3FCE0000
-#define DRAM0_CACHE_ADDRESS_LOW         0x3C000000
-#define DRAM0_CACHE_ADDRESS_HIGH        0x3C800000
-#define DRAM0_CACHE_OPERATION_HIGH      DRAM0_CACHE_ADDRESS_HIGH
+#define SOC_DRAM0_ADDRESS_LOW               0x3FC80000
+#define SOC_DRAM0_ADDRESS_HIGH              0x3FCE0000
+#define SOC_DRAM0_CACHE_ADDRESS_LOW         0x3C000000
+#define SOC_DRAM0_CACHE_ADDRESS_HIGH        0x3C800000
 
-#define BUS_SIZE(bus_name)                 (bus_name##_ADDRESS_HIGH - bus_name##_ADDRESS_LOW)
-#define ADDRESS_IN_BUS(bus_name, vaddr)    ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH)
+#define SOC_BUS_SIZE(bus_name)                 (bus_name##_ADDRESS_HIGH - bus_name##_ADDRESS_LOW)
+#define SOC_ADDRESS_IN_BUS(bus_name, vaddr)    ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH)
 
-#define ADDRESS_IN_IRAM0(vaddr)            ADDRESS_IN_BUS(IRAM0, vaddr)
-#define ADDRESS_IN_IRAM0_CACHE(vaddr)      ADDRESS_IN_BUS(IRAM0_CACHE, vaddr)
-#define ADDRESS_IN_DRAM0(vaddr)            ADDRESS_IN_BUS(DRAM0, vaddr)
-#define ADDRESS_IN_DRAM0_CACHE(vaddr)      ADDRESS_IN_BUS(DRAM0_CACHE, vaddr)
+#define SOC_ADDRESS_IN_IRAM0(vaddr)                SOC_ADDRESS_IN_BUS(SOC_IRAM0, vaddr)
+#define SOC_ADDRESS_IN_IRAM0_CACHE(vaddr)          SOC_ADDRESS_IN_BUS(SOC_IRAM0_CACHE, vaddr)
+#define SOC_ADDRESS_IN_DRAM0(vaddr)                SOC_ADDRESS_IN_BUS(SOC_DRAM0, vaddr)
+#define SOC_ADDRESS_IN_DRAM0_CACHE(vaddr)          SOC_ADDRESS_IN_BUS(SOC_DRAM0_CACHE, vaddr)
 
-#define BUS_IRAM0_CACHE_SIZE              BUS_SIZE(IRAM0_CACHE)
-#define BUS_DRAM0_CACHE_SIZE              BUS_SIZE(DRAM0_CACHE)
-
-#define CACHE_IBUS                      0
-#define CACHE_IBUS_MMU_START            0
-#define CACHE_IBUS_MMU_END              0x200
-
-#define CACHE_DBUS                      1
-#define CACHE_DBUS_MMU_START            0
-#define CACHE_DBUS_MMU_END              0x200
-
-//TODO, remove these cache function dependencies
-#define CACHE_IROM_MMU_START            0
-#define CACHE_IROM_MMU_END              Cache_Get_IROM_MMU_End()
-#define CACHE_IROM_MMU_SIZE             (CACHE_IROM_MMU_END - CACHE_IROM_MMU_START)
-
-#define CACHE_DROM_MMU_START            CACHE_IROM_MMU_END
-#define CACHE_DROM_MMU_END              Cache_Get_DROM_MMU_End()
-#define CACHE_DROM_MMU_SIZE             (CACHE_DROM_MMU_END - CACHE_DROM_MMU_START)
-
-#define CACHE_DROM_MMU_MAX_END          0x200
-
-#define ICACHE_MMU_SIZE                 0x200
-#define DCACHE_MMU_SIZE                 0x200
-
-#define MMU_BUS_START(i)                0
-#define MMU_BUS_SIZE(i)                 0x200
-
-#define MMU_INVALID                     BIT(8)
-#define MMU_VALID                       0
-#define MMU_TYPE                        0
-#define MMU_ACCESS_FLASH                0
-
-#define CACHE_MAX_SYNC_NUM 0x400000
-#define CACHE_MAX_LOCK_NUM 0x8000
+#define SOC_MMU_INVALID                     BIT(8)
+#define SOC_MMU_VALID                       0
+#define SOC_MMU_TYPE                        0
+#define SOC_MMU_ACCESS_FLASH                0
 
 /**
  * MMU entry valid bit mask for mapping value. For an entry:
  * valid bit + value bits
  * valid bit is BIT(8), so value bits are 0xff
  */
-#define MMU_VALID_VAL_MASK 0xff
+#define SOC_MMU_VALID_VAL_MASK 0xff
 /**
  * Max MMU available paddr page num.
- * `MMU_MAX_PADDR_PAGE_NUM * SOC_MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.:
+ * `SOC_MMU_MAX_PADDR_PAGE_NUM * SOC_MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.:
  * 256 * 64KB, means MMU can support 16MB paddr at most
  */
-#define MMU_MAX_PADDR_PAGE_NUM    256
+#define SOC_MMU_MAX_PADDR_PAGE_NUM    256
 /**
  * This is the mask used for mapping. e.g.:
- * 0x4200_0000 & MMU_VADDR_MASK
+ * 0x4200_0000 & SOC_MMU_VADDR_MASK
  */
-#define MMU_VADDR_MASK  0x7FFFFF
+#define SOC_MMU_VADDR_MASK  0x7FFFFF
 //MMU entry num
-#define MMU_ENTRY_NUM   128
-
-#define CACHE_ICACHE_LOW_SHIFT         0
-#define CACHE_ICACHE_HIGH_SHIFT        2
-#define CACHE_DCACHE_LOW_SHIFT         4
-#define CACHE_DCACHE_HIGH_SHIFT        6
-
-#define CACHE_MEMORY_IBANK0_ADDR        0x4037c000
+#define SOC_MMU_ENTRY_NUM   128
 
 #define SOC_MMU_DBUS_VADDR_BASE               0x3C000000
 #define SOC_MMU_IBUS_VADDR_BASE               0x42000000
@@ -115,16 +75,16 @@ extern "C" {
  * - If high linear address is 0, this means MMU linear address range is equal or smaller than vaddr range.
  *   Under this condition, we use the max linear space.
  */
-#define SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW      (IRAM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
-#if ((IRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) > 0)
-#define SOC_MMU_IRAM0_LINEAR_ADDRESS_HIGH     (IRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
+#define SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW      (SOC_IRAM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
+#if ((SOC_IRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) > 0)
+#define SOC_MMU_IRAM0_LINEAR_ADDRESS_HIGH     (SOC_IRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
 #else
 #define SOC_MMU_IRAM0_LINEAR_ADDRESS_HIGH     (SOC_MMU_LINEAR_ADDR_MASK + 1)
 #endif
 
-#define SOC_MMU_DRAM0_LINEAR_ADDRESS_LOW      (DRAM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
-#if ((DRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) > 0)
-#define SOC_MMU_DRAM0_LINEAR_ADDRESS_HIGH     (DRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
+#define SOC_MMU_DRAM0_LINEAR_ADDRESS_LOW      (SOC_DRAM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
+#if ((SOC_DRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) > 0)
+#define SOC_MMU_DRAM0_LINEAR_ADDRESS_HIGH     (SOC_DRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
 #else
 #define SOC_MMU_DRAM0_LINEAR_ADDRESS_HIGH     (SOC_MMU_LINEAR_ADDR_MASK + 1)
 #endif
@@ -135,8 +95,36 @@ extern "C" {
 _Static_assert(SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW == SOC_MMU_DRAM0_LINEAR_ADDRESS_LOW, "IRAM0 and DRAM0 linear address should be same");
 
 
+/**
+ * ROM flash mmap driver needs below definitions
+ */
+#define BUS_IRAM0_CACHE_SIZE              SOC_BUS_SIZE(SOC_IRAM0_CACHE)
+#define BUS_DRAM0_CACHE_SIZE              SOC_BUS_SIZE(SOC_DRAM0_CACHE)
+
+#define CACHE_IBUS                      0
+#define CACHE_IBUS_MMU_START            0
+#define CACHE_IBUS_MMU_END              0x200
+
+#define CACHE_DBUS                      1
+#define CACHE_DBUS_MMU_START            0
+#define CACHE_DBUS_MMU_END              0x200
+
+#define CACHE_IROM_MMU_START            0
+#define CACHE_IROM_MMU_END              Cache_Get_IROM_MMU_End()
+#define CACHE_IROM_MMU_SIZE             (CACHE_IROM_MMU_END - CACHE_IROM_MMU_START)
+
+#define CACHE_DROM_MMU_START            CACHE_IROM_MMU_END
+#define CACHE_DROM_MMU_END              Cache_Get_DROM_MMU_End()
+#define CACHE_DROM_MMU_SIZE             (CACHE_DROM_MMU_END - CACHE_DROM_MMU_START)
+
+#define CACHE_DROM_MMU_MAX_END          0x200
+
+#define ICACHE_MMU_SIZE                 0x200
+#define DCACHE_MMU_SIZE                 0x200
+
+#define MMU_BUS_START(i)                0
+#define MMU_BUS_SIZE(i)                 0x200
+
 #ifdef __cplusplus
 }
 #endif
-
-#endif /*_CACHE_MEMORY_H_ */

components/soc/esp32c3/include/soc/mmu.h

@@ -20,9 +20,9 @@ extern "C" {
 #define SOC_MMU_IROM0_PAGES_END                 (CACHE_IROM_MMU_END / sizeof(uint32_t))
 #define SOC_MMU_DROM0_PAGES_START               (CACHE_DROM_MMU_START / sizeof(uint32_t))
 #define SOC_MMU_DROM0_PAGES_END                 (CACHE_DROM_MMU_END / sizeof(uint32_t))
-#define SOC_MMU_ADDR_MASK                       MMU_VALID_VAL_MASK
+#define SOC_MMU_ADDR_MASK                       SOC_MMU_VALID_VAL_MASK
 #define SOC_MMU_PAGE_IN_FLASH(page)             (page) //Always in Flash
-#define SOC_MMU_VADDR1_START_ADDR               IRAM0_CACHE_ADDRESS_LOW
+#define SOC_MMU_VADDR1_START_ADDR               SOC_IRAM0_CACHE_ADDRESS_LOW
 #define SOC_MMU_PRO_IRAM0_FIRST_USABLE_PAGE     SOC_MMU_IROM0_PAGES_START
 #define SOC_MMU_VADDR0_START_ADDR               (SOC_DROM_LOW + (SOC_MMU_DROM0_PAGES_START * SPI_FLASH_MMU_PAGE_SIZE))
 #define SOC_MMU_VADDR1_FIRST_USABLE_ADDR        SOC_IROM_LOW

components/soc/esp32c6/include/soc/ext_mem_defs.h

@@ -20,81 +20,46 @@ extern "C" {
 #endif
 
 
-#define IRAM0_CACHE_ADDRESS_LOW                  0x42000000
-#define IRAM0_CACHE_ADDRESS_HIGH                 (IRAM0_CACHE_ADDRESS_LOW + ((SOC_MMU_PAGE_SIZE) * MMU_ENTRY_NUM))
+#define SOC_IRAM0_CACHE_ADDRESS_LOW                  0x42000000
+#define SOC_IRAM0_CACHE_ADDRESS_HIGH                 (SOC_IRAM0_CACHE_ADDRESS_LOW + ((SOC_MMU_PAGE_SIZE) * SOC_MMU_ENTRY_NUM))
 
-#define DRAM0_CACHE_ADDRESS_LOW                  IRAM0_CACHE_ADDRESS_LOW                //I/D share the same vaddr range
-#define DRAM0_CACHE_ADDRESS_HIGH                 IRAM0_CACHE_ADDRESS_HIGH               //I/D share the same vaddr range
-#define DRAM0_CACHE_OPERATION_HIGH               DRAM0_CACHE_ADDRESS_HIGH
+#define SOC_DRAM0_CACHE_ADDRESS_LOW                  SOC_IRAM0_CACHE_ADDRESS_LOW                //I/D share the same vaddr range
+#define SOC_DRAM0_CACHE_ADDRESS_HIGH                 SOC_IRAM0_CACHE_ADDRESS_HIGH               //I/D share the same vaddr range
 
-#define BUS_SIZE(bus_name)                 (bus_name##_ADDRESS_HIGH - bus_name##_ADDRESS_LOW)
-#define ADDRESS_IN_BUS(bus_name, vaddr)    ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH)
+#define SOC_BUS_SIZE(bus_name)                       (bus_name##_ADDRESS_HIGH - bus_name##_ADDRESS_LOW)
+#define SOC_ADDRESS_IN_BUS(bus_name, vaddr)          ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH)
 
-#define ADDRESS_IN_IRAM0(vaddr)            ADDRESS_IN_BUS(IRAM0, vaddr)
-#define ADDRESS_IN_IRAM0_CACHE(vaddr)      ADDRESS_IN_BUS(IRAM0_CACHE, vaddr)
-#define ADDRESS_IN_DRAM0(vaddr)            ADDRESS_IN_BUS(DRAM0, vaddr)
-#define ADDRESS_IN_DRAM0_CACHE(vaddr)      ADDRESS_IN_BUS(DRAM0_CACHE, vaddr)
+#define SOC_ADDRESS_IN_IRAM0(vaddr)                  SOC_ADDRESS_IN_BUS(SOC_IRAM0, vaddr)
+#define SOC_ADDRESS_IN_IRAM0_CACHE(vaddr)            SOC_ADDRESS_IN_BUS(SOC_IRAM0_CACHE, vaddr)
+#define SOC_ADDRESS_IN_DRAM0(vaddr)                  SOC_ADDRESS_IN_BUS(SOC_DRAM0, vaddr)
+#define SOC_ADDRESS_IN_DRAM0_CACHE(vaddr)            SOC_ADDRESS_IN_BUS(SOC_DRAM0_CACHE, vaddr)
 
-#define BUS_IRAM0_CACHE_SIZE              BUS_SIZE(IRAM0_CACHE)
-#define BUS_DRAM0_CACHE_SIZE              BUS_SIZE(DRAM0_CACHE)
-
-//TODO, remove these cache function dependencies
-#define CACHE_IROM_MMU_START            0
-#define CACHE_IROM_MMU_END              Cache_Get_IROM_MMU_End()
-#define CACHE_IROM_MMU_SIZE             (CACHE_IROM_MMU_END - CACHE_IROM_MMU_START)
-
-#define CACHE_DROM_MMU_START            CACHE_IROM_MMU_END
-#define CACHE_DROM_MMU_END              Cache_Get_DROM_MMU_End()
-#define CACHE_DROM_MMU_SIZE             (CACHE_DROM_MMU_END - CACHE_DROM_MMU_START)
-
-#define CACHE_DROM_MMU_MAX_END          0x400
-
-#define ICACHE_MMU_SIZE                 0x200
-#define DCACHE_MMU_SIZE                 0x200
-
-#define MMU_BUS_START(i)                0
-#define MMU_BUS_SIZE(i)                 0x200
-
-#define MMU_MSPI_ACCESS_FLASH           0
-#define MMU_MSPI_VALID                  BIT(9)
-#define MMU_MSPI_INVALID                0
-#define MMU_MSPI_SENSITIVE              BIT(10)
-
-#define MMU_ACCESS_FLASH                MMU_MSPI_ACCESS_FLASH
-#define MMU_VALID                       MMU_MSPI_VALID
-#define MMU_SENSITIVE                   MMU_MSPI_SENSITIVE
-
-#define MMU_INVALID_MASK                MMU_MSPI_VALID
-#define MMU_INVALID                     MMU_MSPI_INVALID
-
-
-
-#define CACHE_MAX_SYNC_NUM 0x400000
-#define CACHE_MAX_LOCK_NUM 0x8000
+#define SOC_MMU_ACCESS_FLASH            0
+#define SOC_MMU_VALID                   BIT(9)
+#define SOC_MMU_SENSITIVE               BIT(10)
+#define SOC_MMU_INVALID_MASK            BIT(9)
+#define SOC_MMU_INVALID                 0
 
 /**
  * MMU entry valid bit mask for mapping value. For an entry:
  * valid bit + value bits
  * valid bit is BIT(9), so value bits are 0x1ff
  */
-#define MMU_VALID_VAL_MASK 0x1ff
+#define SOC_MMU_VALID_VAL_MASK 0x1ff
 /**
  * Max MMU available paddr page num.
- * `MMU_MAX_PADDR_PAGE_NUM * SOC_MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.:
+ * `SOC_MMU_MAX_PADDR_PAGE_NUM * SOC_MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.:
  * 256 * 64KB, means MMU can support 16MB paddr at most
  */
-#define MMU_MAX_PADDR_PAGE_NUM    256
+#define SOC_MMU_MAX_PADDR_PAGE_NUM    256
 //MMU entry num
-#define MMU_ENTRY_NUM   256
+#define SOC_MMU_ENTRY_NUM   256
 
 /**
  * This is the mask used for mapping. e.g.:
- * 0x4200_0000 & MMU_VADDR_MASK
+ * 0x4200_0000 & SOC_MMU_VADDR_MASK
  */
-#define MMU_VADDR_MASK                  ((SOC_MMU_PAGE_SIZE) * MMU_ENTRY_NUM - 1)
-
-#define CACHE_MEMORY_IBANK0_ADDR        0x40800000
-
+#define SOC_MMU_VADDR_MASK                  ((SOC_MMU_PAGE_SIZE) * SOC_MMU_ENTRY_NUM - 1)
 
 #define SOC_MMU_DBUS_VADDR_BASE               0x42000000
 #define SOC_MMU_IBUS_VADDR_BASE               0x42000000
@@ -135,16 +100,16 @@ extern "C" {
  * - If high linear address is 0, this means MMU linear address range is equal or smaller than vaddr range.
  *   Under this condition, we use the max linear space.
  */
-#define SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW      (IRAM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
-#if ((IRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) > 0)
-#define SOC_MMU_IRAM0_LINEAR_ADDRESS_HIGH     (IRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
+#define SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW      (SOC_IRAM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
+#if ((SOC_IRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) > 0)
+#define SOC_MMU_IRAM0_LINEAR_ADDRESS_HIGH     (SOC_IRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
 #else
 #define SOC_MMU_IRAM0_LINEAR_ADDRESS_HIGH     (SOC_MMU_LINEAR_ADDR_MASK + 1)
 #endif
 
-#define SOC_MMU_DRAM0_LINEAR_ADDRESS_LOW      (DRAM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
-#if ((DRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) > 0)
-#define SOC_MMU_DRAM0_LINEAR_ADDRESS_HIGH     (DRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
+#define SOC_MMU_DRAM0_LINEAR_ADDRESS_LOW      (SOC_DRAM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
+#if ((SOC_DRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) > 0)
+#define SOC_MMU_DRAM0_LINEAR_ADDRESS_HIGH     (SOC_DRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
 #else
 #define SOC_MMU_DRAM0_LINEAR_ADDRESS_HIGH     (SOC_MMU_LINEAR_ADDR_MASK + 1)
 #endif
@@ -155,6 +120,25 @@ extern "C" {
 _Static_assert(SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW == SOC_MMU_DRAM0_LINEAR_ADDRESS_LOW, "IRAM0 and DRAM0 linear address should be same");
 
 
+/**
+ * ROM flash mmap driver needs below definitions
+ */
+#define CACHE_IROM_MMU_START            0
+#define CACHE_IROM_MMU_END              Cache_Get_IROM_MMU_End()
+#define CACHE_IROM_MMU_SIZE             (CACHE_IROM_MMU_END - CACHE_IROM_MMU_START)
+
+#define CACHE_DROM_MMU_START            CACHE_IROM_MMU_END
+#define CACHE_DROM_MMU_END              Cache_Get_DROM_MMU_End()
+#define CACHE_DROM_MMU_SIZE             (CACHE_DROM_MMU_END - CACHE_DROM_MMU_START)
+
+#define CACHE_DROM_MMU_MAX_END          0x400
+
+#define ICACHE_MMU_SIZE                 0x200
+#define DCACHE_MMU_SIZE                 0x200
+
+#define MMU_BUS_START(i)                0
+#define MMU_BUS_SIZE(i)                 0x200
+
 #ifdef __cplusplus
 }
 #endif

components/soc/esp32c6/include/soc/mmu.h

@@ -21,9 +21,9 @@ extern "C" {
 #define SOC_MMU_DROM0_PAGES_START               (CACHE_DROM_MMU_START / sizeof(uint32_t))
 #define SOC_MMU_DROM0_PAGES_END                 (CACHE_DROM_MMU_END / sizeof(uint32_t))
 #define SOC_MMU_INVALID_ENTRY_VAL               MMU_TABLE_INVALID_VAL
-#define SOC_MMU_ADDR_MASK                       (MMU_VALID - 1)
+#define SOC_MMU_ADDR_MASK                       (SOC_MMU_VALID - 1)
 #define SOC_MMU_PAGE_IN_FLASH(page)             (page) //Always in Flash
-#define SOC_MMU_VADDR1_START_ADDR               IRAM0_CACHE_ADDRESS_LOW
+#define SOC_MMU_VADDR1_START_ADDR               SOC_IRAM0_CACHE_ADDRESS_LOW
 #define SOC_MMU_PRO_IRAM0_FIRST_USABLE_PAGE     SOC_MMU_IROM0_PAGES_START
 #define SOC_MMU_VADDR0_START_ADDR               (SOC_IROM_LOW + (SOC_MMU_DROM0_PAGES_START * SPI_FLASH_MMU_PAGE_SIZE))
 #define SOC_MMU_VADDR1_FIRST_USABLE_ADDR        SOC_IROM_LOW

components/soc/esp32h2/include/soc/ext_mem_defs.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -20,81 +20,46 @@ extern "C" {
 #endif
 
 
-#define IRAM0_CACHE_ADDRESS_LOW                  0x42000000
-#define IRAM0_CACHE_ADDRESS_HIGH                 (IRAM0_CACHE_ADDRESS_LOW + ((SOC_MMU_PAGE_SIZE) * MMU_ENTRY_NUM))
+#define SOC_IRAM0_CACHE_ADDRESS_LOW                  0x42000000
+#define SOC_IRAM0_CACHE_ADDRESS_HIGH                 (SOC_IRAM0_CACHE_ADDRESS_LOW + ((SOC_MMU_PAGE_SIZE) * SOC_MMU_ENTRY_NUM))
 
-#define DRAM0_CACHE_ADDRESS_LOW                  IRAM0_CACHE_ADDRESS_LOW                //I/D share the same vaddr range
-#define DRAM0_CACHE_ADDRESS_HIGH                 IRAM0_CACHE_ADDRESS_HIGH               //I/D share the same vaddr range
-#define DRAM0_CACHE_OPERATION_HIGH               DRAM0_CACHE_ADDRESS_HIGH
+#define SOC_DRAM0_CACHE_ADDRESS_LOW                  SOC_IRAM0_CACHE_ADDRESS_LOW                //I/D share the same vaddr range
+#define SOC_DRAM0_CACHE_ADDRESS_HIGH                 SOC_IRAM0_CACHE_ADDRESS_HIGH               //I/D share the same vaddr range
 
-#define BUS_SIZE(bus_name)                 (bus_name##_ADDRESS_HIGH - bus_name##_ADDRESS_LOW)
-#define ADDRESS_IN_BUS(bus_name, vaddr)    ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH)
+#define SOC_BUS_SIZE(bus_name)                       (bus_name##_ADDRESS_HIGH - bus_name##_ADDRESS_LOW)
+#define SOC_ADDRESS_IN_BUS(bus_name, vaddr)          ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH)
 
-#define ADDRESS_IN_IRAM0(vaddr)            ADDRESS_IN_BUS(IRAM0, vaddr)
-#define ADDRESS_IN_IRAM0_CACHE(vaddr)      ADDRESS_IN_BUS(IRAM0_CACHE, vaddr)
-#define ADDRESS_IN_DRAM0(vaddr)            ADDRESS_IN_BUS(DRAM0, vaddr)
-#define ADDRESS_IN_DRAM0_CACHE(vaddr)      ADDRESS_IN_BUS(DRAM0_CACHE, vaddr)
+#define SOC_ADDRESS_IN_IRAM0(vaddr)                  SOC_ADDRESS_IN_BUS(SOC_IRAM0, vaddr)
+#define SOC_ADDRESS_IN_IRAM0_CACHE(vaddr)            SOC_ADDRESS_IN_BUS(SOC_IRAM0_CACHE, vaddr)
+#define SOC_ADDRESS_IN_DRAM0(vaddr)                  SOC_ADDRESS_IN_BUS(SOC_DRAM0, vaddr)
+#define SOC_ADDRESS_IN_DRAM0_CACHE(vaddr)            SOC_ADDRESS_IN_BUS(SOC_DRAM0_CACHE, vaddr)
 
-#define BUS_IRAM0_CACHE_SIZE(page_size)              BUS_SIZE(IRAM0_CACHE)
-#define BUS_DRAM0_CACHE_SIZE(page_size)              BUS_SIZE(DRAM0_CACHE)
-
-//TODO, remove these cache function dependencies
-#define CACHE_IROM_MMU_START            0
-#define CACHE_IROM_MMU_END              Cache_Get_IROM_MMU_End()
-#define CACHE_IROM_MMU_SIZE             (CACHE_IROM_MMU_END - CACHE_IROM_MMU_START)
-
-#define CACHE_DROM_MMU_START            CACHE_IROM_MMU_END
-#define CACHE_DROM_MMU_END              Cache_Get_DROM_MMU_End()
-#define CACHE_DROM_MMU_SIZE             (CACHE_DROM_MMU_END - CACHE_DROM_MMU_START)
-
-#define CACHE_DROM_MMU_MAX_END          0x400
-
-#define ICACHE_MMU_SIZE                 0x200
-#define DCACHE_MMU_SIZE                 0x200
-
-#define MMU_BUS_START(i)                0
-#define MMU_BUS_SIZE(i)                 0x200
-
-#define MMU_MSPI_ACCESS_FLASH           0
-#define MMU_MSPI_VALID                  BIT(9)
-#define MMU_MSPI_INVALID                0
-#define MMU_MSPI_SENSITIVE              BIT(10)
-
-#define MMU_ACCESS_FLASH                MMU_MSPI_ACCESS_FLASH
-#define MMU_VALID                       MMU_MSPI_VALID
-#define MMU_SENSITIVE                   MMU_MSPI_SENSITIVE
-
-#define MMU_INVALID_MASK                MMU_MSPI_VALID
-#define MMU_INVALID                     MMU_MSPI_INVALID
-
-
-
-#define CACHE_MAX_SYNC_NUM 0x400000
-#define CACHE_MAX_LOCK_NUM 0x8000
+#define SOC_MMU_ACCESS_FLASH            0
+#define SOC_MMU_VALID                   BIT(9)
+#define SOC_MMU_SENSITIVE               BIT(10)
+#define SOC_MMU_INVALID_MASK            BIT(9)
+#define SOC_MMU_INVALID                 0
 
 /**
  * MMU entry valid bit mask for mapping value. For an entry:
  * valid bit + value bits
  * valid bit is BIT(9), so value bits are 0x1ff
  */
-#define MMU_VALID_VAL_MASK 0x1ff
+#define SOC_MMU_VALID_VAL_MASK 0x1ff
 /**
  * Max MMU available paddr page num.
- * `MMU_MAX_PADDR_PAGE_NUM * SOC_MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.:
+ * `SOC_MMU_MAX_PADDR_PAGE_NUM * SOC_MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.:
  * 256 * 64KB, means MMU can support 16MB paddr at most
  */
-#define MMU_MAX_PADDR_PAGE_NUM    256
+#define SOC_MMU_MAX_PADDR_PAGE_NUM    256
 //MMU entry num
-#define MMU_ENTRY_NUM   256
+#define SOC_MMU_ENTRY_NUM   256
 
 /**
  * This is the mask used for mapping. e.g.:
- * 0x4200_0000 & MMU_VADDR_MASK
+ * 0x4200_0000 & SOC_MMU_VADDR_MASK
  */
-#define MMU_VADDR_MASK                 ((SOC_MMU_PAGE_SIZE) * MMU_ENTRY_NUM - 1)
-
-#define CACHE_MEMORY_IBANK0_ADDR        0x40800000
-
+#define SOC_MMU_VADDR_MASK                 ((SOC_MMU_PAGE_SIZE) * SOC_MMU_ENTRY_NUM - 1)
 
 #define SOC_MMU_DBUS_VADDR_BASE               0x42000000
 #define SOC_MMU_IBUS_VADDR_BASE               0x42000000
@@ -135,16 +100,16 @@ extern "C" {
  * - If high linear address is 0, this means MMU linear address range is equal or smaller than vaddr range.
  *   Under this condition, we use the max linear space.
  */
-#define SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW      (IRAM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
-#if ((IRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) > 0)
-#define SOC_MMU_IRAM0_LINEAR_ADDRESS_HIGH     (IRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
+#define SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW      (SOC_IRAM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
+#if ((SOC_IRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) > 0)
+#define SOC_MMU_IRAM0_LINEAR_ADDRESS_HIGH     (SOC_IRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
 #else
 #define SOC_MMU_IRAM0_LINEAR_ADDRESS_HIGH     (SOC_MMU_LINEAR_ADDR_MASK + 1)
 #endif
 
-#define SOC_MMU_DRAM0_LINEAR_ADDRESS_LOW      (DRAM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
-#if ((DRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) > 0)
-#define SOC_MMU_DRAM0_LINEAR_ADDRESS_HIGH     (DRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
+#define SOC_MMU_DRAM0_LINEAR_ADDRESS_LOW      (SOC_DRAM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
+#if ((SOC_DRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) > 0)
+#define SOC_MMU_DRAM0_LINEAR_ADDRESS_HIGH     (SOC_DRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
 #else
 #define SOC_MMU_DRAM0_LINEAR_ADDRESS_HIGH     (SOC_MMU_LINEAR_ADDR_MASK + 1)
 #endif
@@ -155,6 +120,28 @@ extern "C" {
 _Static_assert(SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW == SOC_MMU_DRAM0_LINEAR_ADDRESS_LOW, "IRAM0 and DRAM0 linear address should be same");
 
 
+/**
+ * ROM flash mmap driver needs below definitions
+ */
+#define BUS_IRAM0_CACHE_SIZE(page_size)              SOC_BUS_SIZE(SOC_IRAM0_CACHE)
+#define BUS_DRAM0_CACHE_SIZE(page_size)              SOC_BUS_SIZE(SOC_DRAM0_CACHE)
+
+#define CACHE_IROM_MMU_START            0
+#define CACHE_IROM_MMU_END              Cache_Get_IROM_MMU_End()
+#define CACHE_IROM_MMU_SIZE             (CACHE_IROM_MMU_END - CACHE_IROM_MMU_START)
+
+#define CACHE_DROM_MMU_START            CACHE_IROM_MMU_END
+#define CACHE_DROM_MMU_END              Cache_Get_DROM_MMU_End()
+#define CACHE_DROM_MMU_SIZE             (CACHE_DROM_MMU_END - CACHE_DROM_MMU_START)
+
+#define CACHE_DROM_MMU_MAX_END          0x400
+
+#define ICACHE_MMU_SIZE                 0x200
+#define DCACHE_MMU_SIZE                 0x200
+
+#define MMU_BUS_START(i)                0
+#define MMU_BUS_SIZE(i)                 0x200
+
 #ifdef __cplusplus
 }
 #endif

components/soc/esp32h2/include/soc/mmu.h

@@ -21,9 +21,9 @@ extern "C" {
 #define SOC_MMU_DROM0_PAGES_START               (CACHE_DROM_MMU_START / sizeof(uint32_t))
 #define SOC_MMU_DROM0_PAGES_END                 (CACHE_DROM_MMU_END / sizeof(uint32_t))
 #define SOC_MMU_INVALID_ENTRY_VAL               MMU_TABLE_INVALID_VAL
-#define SOC_MMU_ADDR_MASK                       (MMU_VALID - 1)
+#define SOC_MMU_ADDR_MASK                       (SOC_MMU_VALID - 1)
 #define SOC_MMU_PAGE_IN_FLASH(page)             (page) //Always in Flash
-#define SOC_MMU_VADDR1_START_ADDR               IRAM0_CACHE_ADDRESS_LOW
+#define SOC_MMU_VADDR1_START_ADDR               SOC_IRAM0_CACHE_ADDRESS_LOW
 #define SOC_MMU_PRO_IRAM0_FIRST_USABLE_PAGE     SOC_MMU_IROM0_PAGES_START
 #define SOC_MMU_VADDR0_START_ADDR               (SOC_IROM_LOW + (SOC_MMU_DROM0_PAGES_START * SPI_FLASH_MMU_PAGE_SIZE))
 #define SOC_MMU_VADDR1_FIRST_USABLE_ADDR        SOC_IROM_LOW

components/soc/esp32p4/include/soc/ext_mem_defs.h

@@ -20,58 +20,38 @@ extern "C" {
 #endif
 
 
-#define IRAM0_CACHE_ADDRESS_LOW                  0x40000000
-#define IRAM0_CACHE_ADDRESS_HIGH                 0x50000000
+#define SOC_IRAM0_CACHE_ADDRESS_LOW                  0x40000000
+#define SOC_IRAM0_CACHE_ADDRESS_HIGH                 0x50000000
 
-#define DRAM0_CACHE_ADDRESS_LOW                  IRAM0_CACHE_ADDRESS_LOW                //I/D share the same vaddr range
-#define DRAM0_CACHE_ADDRESS_HIGH                 IRAM0_CACHE_ADDRESS_HIGH               //I/D share the same vaddr range
+#define SOC_DRAM0_CACHE_ADDRESS_LOW                  SOC_IRAM0_CACHE_ADDRESS_LOW                //I/D share the same vaddr range
+#define SOC_DRAM0_CACHE_ADDRESS_HIGH                 SOC_IRAM0_CACHE_ADDRESS_HIGH               //I/D share the same vaddr range
 
-#define DRAM_FLASH_ADDRESS_LOW                   DRAM0_CACHE_ADDRESS_LOW
-#define DRAM_FLASH_ADDRESS_HIGH                  0x44000000
+#define SOC_DRAM_FLASH_ADDRESS_LOW                   SOC_DRAM0_CACHE_ADDRESS_LOW
+#define SOC_DRAM_FLASH_ADDRESS_HIGH                  0x44000000
 
-#define DRAM_PSRAM_ADDRESS_LOW                   0x48000000
-#define DRAM_PSRAM_ADDRESS_HIGH                  0x4C000000
+#define SOC_DRAM_PSRAM_ADDRESS_LOW                   0x48000000
+#define SOC_DRAM_PSRAM_ADDRESS_HIGH                  0x4C000000
 
-#define BUS_SIZE(bus_name)                 (bus_name##_ADDRESS_HIGH - bus_name##_ADDRESS_LOW)
-#define ADDRESS_IN_BUS(bus_name, vaddr)    ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH)
+#define SOC_BUS_SIZE(bus_name)                       (bus_name##_ADDRESS_HIGH - bus_name##_ADDRESS_LOW)
+#define SOC_ADDRESS_IN_BUS(bus_name, vaddr)          ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH)
 
-#define ADDRESS_IN_IRAM0_CACHE(vaddr)      ADDRESS_IN_BUS(IRAM0_CACHE, vaddr)
-#define ADDRESS_IN_DRAM0_CACHE(vaddr)      ADDRESS_IN_BUS(DRAM0_CACHE, vaddr)
-#define ADDRESS_IN_DRAM_FLASH(vaddr)       ADDRESS_IN_BUS(DRAM_FLASH, vaddr)
-#define ADDRESS_IN_DRAM_PSRAM(vaddr)       ADDRESS_IN_BUS(DRAM_PSRAM, vaddr)
+#define SOC_ADDRESS_IN_IRAM0_CACHE(vaddr)            SOC_ADDRESS_IN_BUS(SOC_IRAM0_CACHE, vaddr)
+#define SOC_ADDRESS_IN_DRAM0_CACHE(vaddr)            SOC_ADDRESS_IN_BUS(SOC_DRAM0_CACHE, vaddr)
+#define SOC_ADDRESS_IN_DRAM_FLASH(vaddr)             SOC_ADDRESS_IN_BUS(SOC_DRAM_FLASH, vaddr)
+#define SOC_ADDRESS_IN_DRAM_PSRAM(vaddr)             SOC_ADDRESS_IN_BUS(SOC_DRAM_PSRAM, vaddr)
 
-//TODO, remove these cache function dependencies
-#define CACHE_IROM_MMU_START            0
-#define CACHE_IROM_MMU_END              Cache_Get_IROM_MMU_End()
-#define CACHE_IROM_MMU_SIZE             (CACHE_IROM_MMU_END - CACHE_IROM_MMU_START)
 
-#define CACHE_DROM_MMU_START            CACHE_IROM_MMU_END
-#define CACHE_DROM_MMU_END              Cache_Get_DROM_MMU_End()
-#define CACHE_DROM_MMU_SIZE             (CACHE_DROM_MMU_END - CACHE_DROM_MMU_START)
+#define SOC_MMU_FLASH_VALID                 BIT(12)
+#define SOC_MMU_FLASH_INVALID               0
+#define SOC_MMU_PSRAM_VALID                 BIT(11)
+#define SOC_MMU_PSRAM_INVALID               0
 
-#define CACHE_DROM_MMU_MAX_END          0x400
+#define SOC_MMU_ACCESS_FLASH                0
+#define SOC_MMU_ACCESS_PSRAM                BIT(10)
 
-#define ICACHE_MMU_SIZE                 (0x400 * 4)
-#define DCACHE_MMU_SIZE                 (0x400 * 4)
+#define SOC_MMU_FLASH_SENSITIVE             BIT(13)
+#define SOC_MMU_PSRAM_SENSITIVE             BIT(12)
 
-#define MMU_BUS_START(i)                0
-#define MMU_BUS_SIZE(i)                 (0x400 * 4)
-
-
-#define MMU_FLASH_VALID                 BIT(12)
-#define MMU_FLASH_INVALID               0
-#define MMU_PSRAM_VALID                 BIT(11)
-#define MMU_PSRAM_INVALID               0
-
-#define MMU_ACCESS_FLASH                0
-#define MMU_ACCESS_PSRAM                BIT(10)
-
-#define MMU_FLASH_SENSITIVE             BIT(13)
-#define MMU_PSRAM_SENSITIVE             BIT(12)
-
-
-#define CACHE_MAX_SYNC_NUM 0x400000
-#define CACHE_MAX_LOCK_NUM 0x8000
 
 /**
  * MMU entry valid bit mask for mapping value.
@@ -80,26 +60,26 @@ extern "C" {
  * - For a PSRAM MMU entry:
  *   physical page number is BIT(0)~BIT(9), so value bits are 0x3ff
  */
-#define MMU_FLASH_VALID_VAL_MASK 0x7ff
-#define MMU_PSRAM_VALID_VAL_MASK 0x3ff
+#define SOC_MMU_FLASH_VALID_VAL_MASK        0x7ff
+#define SOC_MMU_PSRAM_VALID_VAL_MASK        0x3ff
 /**
  * Max MMU available paddr page num.
- * `MMU_MAX_PADDR_PAGE_NUM * SOC_MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.:
+ * `SOC_MMU_MAX_PADDR_PAGE_NUM * SOC_MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.:
  * 32768 * 64KB, means MMU can support 2GB paddr at most
  */
-#define MMU_FLASH_MAX_PADDR_PAGE_NUM    32768
-#define MMU_PSRAM_MAX_PADDR_PAGE_NUM    16384
+#define SOC_MMU_FLASH_MAX_PADDR_PAGE_NUM    32768
+#define SOC_MMU_PSRAM_MAX_PADDR_PAGE_NUM    16384
 //MMU entry num
-#define MMU_ENTRY_NUM   1024
+#define SOC_MMU_ENTRY_NUM                   1024
 
 /**
  * This is the mask used for mapping. e.g.:
- * 0x4000_0000 & MMU_VADDR_MASK
+ * 0x4000_0000 & SOC_MMU_VADDR_MASK
  */
-#define MMU_VADDR_MASK                  ((SOC_MMU_PAGE_SIZE) * MMU_ENTRY_NUM - 1)
+#define SOC_MMU_VADDR_MASK                  ((SOC_MMU_PAGE_SIZE) * SOC_MMU_ENTRY_NUM - 1)
 
-#define SOC_MMU_FLASH_VADDR_BASE                   0x40000000
-#define SOC_MMU_PSRAM_VADDR_BASE                   0x48000000
+#define SOC_MMU_FLASH_VADDR_BASE            0x40000000
+#define SOC_MMU_PSRAM_VADDR_BASE            0x48000000
 
 /*------------------------------------------------------------------------------
  * MMU Linear Address
@@ -110,23 +90,23 @@ extern "C" {
  *
  * Therefore, 0x3F,FFFF
  */
-#define SOC_MMU_LINEAR_ADDR_MASK              0xFFFFFFF
+#define SOC_MMU_LINEAR_ADDR_MASK            0xFFFFFFF
 
 /**
  * - If high linear address isn't 0, this means MMU can recognize these addresses
  * - If high linear address is 0, this means MMU linear address range is equal or smaller than vaddr range.
  *   Under this condition, we use the max linear space.
  */
-#define SOC_MMU_FLASH_LINEAR_ADDRESS_LOW      (DRAM_FLASH_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
-#if ((DRAM_FLASH_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) > 0)
-#define SOC_MMU_FLASH_LINEAR_ADDRESS_HIGH     (DRAM_FLASH_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
+#define SOC_MMU_FLASH_LINEAR_ADDRESS_LOW      (SOC_DRAM_FLASH_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
+#if ((SOC_DRAM_FLASH_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) > 0)
+#define SOC_MMU_FLASH_LINEAR_ADDRESS_HIGH     (SOC_DRAM_FLASH_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
 #else
 #define SOC_MMU_FLASH_LINEAR_ADDRESS_HIGH     (SOC_MMU_LINEAR_ADDR_MASK + 1)
 #endif
 
-#define SOC_MMU_PSRAM_LINEAR_ADDRESS_LOW      (DRAM_PSRAM_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
-#if ((DRAM_PSRAM_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) > 0)
-#define SOC_MMU_PSRAM_LINEAR_ADDRESS_HIGH     (DRAM_PSRAM_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
+#define SOC_MMU_PSRAM_LINEAR_ADDRESS_LOW      (SOC_DRAM_PSRAM_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
+#if ((SOC_DRAM_PSRAM_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) > 0)
+#define SOC_MMU_PSRAM_LINEAR_ADDRESS_HIGH     (SOC_DRAM_PSRAM_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
 #else
 #define SOC_MMU_PSRAM_LINEAR_ADDRESS_HIGH     (SOC_MMU_LINEAR_ADDR_MASK + 1)
 #endif

components/soc/esp32p4/include/soc/mmu.h

@@ -1,21 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/ext_mem_defs.h"
-#include "soc/soc.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-//To delete this file
-//TODO: IDF-7686
-
-#ifdef __cplusplus
-}
-#endif

components/soc/esp32s2/include/soc/ext_mem_defs.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -13,55 +13,55 @@ extern "C" {
 #endif
 
 /*IRAM0 is connected with Cache IBUS0*/
-#define IRAM0_ADDRESS_LOW		0x40000000
-#define IRAM0_ADDRESS_HIGH		0x40400000
-#define IRAM0_CACHE_ADDRESS_LOW		0x40080000
-#define IRAM0_CACHE_ADDRESS_HIGH	0x40400000
+#define SOC_IRAM0_ADDRESS_LOW		0x40000000
+#define SOC_IRAM0_ADDRESS_HIGH		0x40400000
+#define SOC_IRAM0_CACHE_ADDRESS_LOW		0x40080000
+#define SOC_IRAM0_CACHE_ADDRESS_HIGH	0x40400000
 
 /*IRAM1 is connected with Cache IBUS1*/
-#define IRAM1_ADDRESS_LOW		0x40400000
-#define IRAM1_ADDRESS_HIGH		0x40800000
+#define SOC_IRAM1_ADDRESS_LOW		0x40400000
+#define SOC_IRAM1_ADDRESS_HIGH		0x40800000
 
 /*DROM0 is connected with Cache IBUS2*/
-#define DROM0_ADDRESS_LOW		0x3f000000
-#define DROM0_ADDRESS_HIGH		0x3f400000
+#define SOC_DROM0_ADDRESS_LOW		0x3f000000
+#define SOC_DROM0_ADDRESS_HIGH		0x3f400000
 
 /*DRAM0 is connected with Cache DBUS0*/
-#define DRAM0_ADDRESS_LOW       	0x3fc00000
-#define DRAM0_ADDRESS_HIGH      	0x40000000
-#define DRAM0_CACHE_ADDRESS_LOW       	0x3fc00000
-#define DRAM0_CACHE_ADDRESS_HIGH      	0x3ff80000
+#define SOC_DRAM0_ADDRESS_LOW       	0x3fc00000
+#define SOC_DRAM0_ADDRESS_HIGH      	0x40000000
+#define SOC_DRAM0_CACHE_ADDRESS_LOW       	0x3fc00000
+#define SOC_DRAM0_CACHE_ADDRESS_HIGH      	0x3ff80000
 
 /*DRAM1 is connected with Cache DBUS1*/
-#define DRAM1_ADDRESS_LOW       	0x3f800000
-#define DRAM1_ADDRESS_HIGH      	0x3fc00000
+#define SOC_DRAM1_ADDRESS_LOW       	0x3f800000
+#define SOC_DRAM1_ADDRESS_HIGH      	0x3fc00000
 
 /*DPORT is connected with Cache DBUS2*/
-#define DPORT_ADDRESS_LOW       	0x3f400000
-#define DPORT_ADDRESS_HIGH      	0x3f800000
-#define DPORT_CACHE_ADDRESS_LOW       	0x3f500000
-#define DPORT_CACHE_ADDRESS_HIGH      	0x3f800000
-
-#define BUS_SIZE(bus_name)                 (bus_name##_ADDRESS_HIGH - bus_name##_ADDRESS_LOW)
-#define ADDRESS_IN_BUS(bus_name, vaddr)    ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH)
-
-#define ADDRESS_IN_IRAM0(vaddr)            ADDRESS_IN_BUS(IRAM0, vaddr)
-#define ADDRESS_IN_IRAM0_CACHE(vaddr)      ADDRESS_IN_BUS(IRAM0_CACHE, vaddr)
-#define ADDRESS_IN_IRAM1(vaddr)            ADDRESS_IN_BUS(IRAM1, vaddr)
-#define ADDRESS_IN_DROM0(vaddr)            ADDRESS_IN_BUS(DROM0, vaddr)
-#define ADDRESS_IN_DRAM0(vaddr)            ADDRESS_IN_BUS(DRAM0, vaddr)
-#define ADDRESS_IN_DRAM0_CACHE(vaddr)      ADDRESS_IN_BUS(DRAM0_CACHE, vaddr)
-#define ADDRESS_IN_DRAM1(vaddr)            ADDRESS_IN_BUS(DRAM1, vaddr)
-#define ADDRESS_IN_DPORT(vaddr)            ADDRESS_IN_BUS(DPORT, vaddr)
-#define ADDRESS_IN_DPORT_CACHE(vaddr)      ADDRESS_IN_BUS(DPORT_CACHE, vaddr)
-
-#define BUS_IRAM0_CACHE_SIZE              BUS_SIZE(IRAM0_CACHE)
-#define BUS_IRAM1_CACHE_SIZE              BUS_SIZE(IRAM1)
-#define BUS_IROM0_CACHE_SIZE              BUS_SIZE(IROM0)
-#define BUS_DROM0_CACHE_SIZE              BUS_SIZE(DROM0)
-#define BUS_DRAM0_CACHE_SIZE              BUS_SIZE(DRAM0_CACHE)
-#define BUS_DRAM1_CACHE_SIZE              BUS_SIZE(DRAM1)
-#define BUS_DPORT_CACHE_SIZE              BUS_SIZE(DPORT_CACHE)
+#define SOC_DPORT_ADDRESS_LOW       	0x3f400000
+#define SOC_DPORT_ADDRESS_HIGH      	0x3f800000
+#define SOC_DPORT_CACHE_ADDRESS_LOW       	0x3f500000
+#define SOC_DPORT_CACHE_ADDRESS_HIGH      	0x3f800000
+
+#define SOC_BUS_SIZE(bus_name)                 (bus_name##_ADDRESS_HIGH - bus_name##_ADDRESS_LOW)
+#define SOC_ADDRESS_IN_BUS(bus_name, vaddr)    ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH)
+
+#define SOC_ADDRESS_IN_IRAM0(vaddr)            SOC_ADDRESS_IN_BUS(SOC_IRAM0, vaddr)
+#define SOC_ADDRESS_IN_IRAM0_CACHE(vaddr)      SOC_ADDRESS_IN_BUS(SOC_IRAM0_CACHE, vaddr)
+#define SOC_ADDRESS_IN_IRAM1(vaddr)            SOC_ADDRESS_IN_BUS(SOC_IRAM1, vaddr)
+#define SOC_ADDRESS_IN_DROM0(vaddr)            SOC_ADDRESS_IN_BUS(SOC_DROM0, vaddr)
+#define SOC_ADDRESS_IN_DRAM0(vaddr)            SOC_ADDRESS_IN_BUS(SOC_DRAM0, vaddr)
+#define SOC_ADDRESS_IN_DRAM0_CACHE(vaddr)      SOC_ADDRESS_IN_BUS(SOC_DRAM0_CACHE, vaddr)
+#define SOC_ADDRESS_IN_DRAM1(vaddr)            SOC_ADDRESS_IN_BUS(SOC_DRAM1, vaddr)
+#define SOC_ADDRESS_IN_DPORT(vaddr)            SOC_ADDRESS_IN_BUS(SOC_DPORT, vaddr)
+#define SOC_ADDRESS_IN_DPORT_CACHE(vaddr)      SOC_ADDRESS_IN_BUS(SOC_DPORT_CACHE, vaddr)
+
+#define BUS_IRAM0_CACHE_SIZE              SOC_BUS_SIZE(SOC_IRAM0_CACHE)
+#define BUS_IRAM1_CACHE_SIZE              SOC_BUS_SIZE(SOC_IRAM1)
+#define BUS_IROM0_CACHE_SIZE              SOC_BUS_SIZE(SOC_IROM0)
+#define BUS_DROM0_CACHE_SIZE              SOC_BUS_SIZE(SOC_DROM0)
+#define BUS_DRAM0_CACHE_SIZE              SOC_BUS_SIZE(SOC_DRAM0_CACHE)
+#define BUS_DRAM1_CACHE_SIZE              SOC_BUS_SIZE(SOC_DRAM1)
+#define BUS_DPORT_CACHE_SIZE              SOC_BUS_SIZE(SOC_DPORT_CACHE)
 
 #define PRO_CACHE_IBUS0                 0
 #define PRO_CACHE_IBUS0_MMU_START       0
@@ -93,30 +93,30 @@ extern "C" {
 #define MMU_BUS_START(i)                ((i) * 0x100)
 #define MMU_BUS_SIZE                    0x100
 
-#define MMU_INVALID                     BIT(14)
-#define MMU_VALID                       0
-#define MMU_ACCESS_FLASH                BIT(15)
-#define MMU_ACCESS_SPIRAM               BIT(16)
+#define SOC_MMU_INVALID                     BIT(14)
+#define SOC_MMU_VALID                       0
+#define SOC_MMU_ACCESS_FLASH                BIT(15)
+#define SOC_MMU_ACCESS_SPIRAM               BIT(16)
 
 /**
  * MMU entry valid bit mask for mapping value. For an entry:
  * valid bit + value bits
  * valid bit is BIT(14), so value bits are 0x3fff
  */
-#define MMU_VALID_VAL_MASK 0x3fff
+#define SOC_MMU_VALID_VAL_MASK 0x3fff
 /**
  * Max MMU available paddr page num.
- * `MMU_MAX_PADDR_PAGE_NUM * SOC_MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.:
+ * `SOC_MMU_MAX_PADDR_PAGE_NUM * SOC_MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.:
  * 16384 * 64KB, means MMU can support 1GB paddr at most
  */
-#define MMU_MAX_PADDR_PAGE_NUM    16384
+#define SOC_MMU_MAX_PADDR_PAGE_NUM    16384
 /**
  * This is the mask used for mapping. e.g.:
- * 0x4200_0000 & MMU_VADDR_MASK
+ * 0x4200_0000 & SOC_MMU_VADDR_MASK
  */
-#define MMU_VADDR_MASK  0x3FFFFF
+#define SOC_MMU_VADDR_MASK  0x3FFFFF
 //MMU entry num
-#define MMU_ENTRY_NUM   384
+#define SOC_MMU_ENTRY_NUM   384
 
 #define BUS_NUM_MASK  0x3
 
@@ -149,23 +149,23 @@ extern "C" {
  */
 #define SOC_MMU_LINEAR_ADDR_MASK              0x1FFFFFF
 
-#define SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW      (IRAM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
-#define SOC_MMU_IRAM0_LINEAR_ADDRESS_HIGH     (IRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
+#define SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW      (SOC_IRAM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
+#define SOC_MMU_IRAM0_LINEAR_ADDRESS_HIGH     (SOC_IRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
 
-#define SOC_MMU_IRAM1_LINEAR_ADDRESS_LOW      (IRAM1_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
-#define SOC_MMU_IRAM1_LINEAR_ADDRESS_HIGH     (IRAM1_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
+#define SOC_MMU_IRAM1_LINEAR_ADDRESS_LOW      (SOC_IRAM1_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
+#define SOC_MMU_IRAM1_LINEAR_ADDRESS_HIGH     (SOC_IRAM1_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
 
-#define SOC_MMU_DROM0_LINEAR_ADDRESS_LOW      (DROM0_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
-#define SOC_MMU_DROM0_LINEAR_ADDRESS_HIGH     (DROM0_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
+#define SOC_MMU_DROM0_LINEAR_ADDRESS_LOW      (SOC_DROM0_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
+#define SOC_MMU_DROM0_LINEAR_ADDRESS_HIGH     (SOC_DROM0_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
 
-#define SOC_MMU_DPORT_LINEAR_ADDRESS_LOW      (DPORT_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
-#define SOC_MMU_DPORT_LINEAR_ADDRESS_HIGH     (DPORT_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
+#define SOC_MMU_DPORT_LINEAR_ADDRESS_LOW      (SOC_DPORT_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
+#define SOC_MMU_DPORT_LINEAR_ADDRESS_HIGH     (SOC_DPORT_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
 
-#define SOC_MMU_DRAM1_LINEAR_ADDRESS_LOW      (DRAM1_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
-#define SOC_MMU_DRAM1_LINEAR_ADDRESS_HIGH     (DRAM1_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
+#define SOC_MMU_DRAM1_LINEAR_ADDRESS_LOW      (SOC_DRAM1_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
+#define SOC_MMU_DRAM1_LINEAR_ADDRESS_HIGH     (SOC_DRAM1_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
 
-#define SOC_MMU_DRAM0_LINEAR_ADDRESS_LOW      (DRAM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
-#define SOC_MMU_DRAM0_LINEAR_ADDRESS_HIGH     (DRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
+#define SOC_MMU_DRAM0_LINEAR_ADDRESS_LOW      (SOC_DRAM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
+#define SOC_MMU_DRAM0_LINEAR_ADDRESS_HIGH     (SOC_DRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
 
 #ifdef __cplusplus
 }

components/soc/esp32s2/include/soc/mmu.h

@@ -20,8 +20,8 @@ extern "C" {
 #define SOC_MMU_IROM0_PAGES_END                 (PRO_CACHE_IBUS1_MMU_END / sizeof(uint32_t))
 #define SOC_MMU_DROM0_PAGES_START               (PRO_CACHE_IBUS2_MMU_START / sizeof(uint32_t))
 #define SOC_MMU_DROM0_PAGES_END                 (PRO_CACHE_IBUS2_MMU_END / sizeof(uint32_t))
-#define SOC_MMU_ADDR_MASK                       MMU_VALID_VAL_MASK
-#define SOC_MMU_PAGE_IN_FLASH(page)             ((page) | MMU_ACCESS_FLASH)
+#define SOC_MMU_ADDR_MASK                       SOC_MMU_VALID_VAL_MASK
+#define SOC_MMU_PAGE_IN_FLASH(page)             ((page) | SOC_MMU_ACCESS_FLASH)
 #define SOC_MMU_VADDR1_START_ADDR               SOC_IROM_MASK_LOW
 #define SOC_MMU_PRO_IRAM0_FIRST_USABLE_PAGE     ((SOC_MMU_VADDR1_FIRST_USABLE_ADDR - SOC_MMU_VADDR1_START_ADDR) / SPI_FLASH_MMU_PAGE_SIZE + SOC_MMU_IROM0_PAGES_START)
 #define SOC_MMU_VADDR0_START_ADDR               SOC_DROM_LOW

components/soc/esp32s3/include/soc/ext_mem_defs.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -12,94 +12,50 @@ extern "C" {
 #endif
 
 /*IRAM0 is connected with Cache IBUS0*/
-#define IRAM0_ADDRESS_LOW               0x40370000
-#define IRAM0_ADDRESS_HIGH              0x403E0000
-#define IRAM0_CACHE_ADDRESS_LOW         0x42000000
-#define IRAM0_CACHE_ADDRESS_HIGH        0x44000000
+#define SOC_IRAM0_ADDRESS_LOW               0x40370000
+#define SOC_IRAM0_ADDRESS_HIGH              0x403E0000
+#define SOC_IRAM0_CACHE_ADDRESS_LOW         0x42000000
+#define SOC_IRAM0_CACHE_ADDRESS_HIGH        0x44000000
 
 /*DRAM0 is connected with Cache DBUS0*/
-#define DRAM0_ADDRESS_LOW               0x3FC88000
-#define DRAM0_ADDRESS_HIGH              0x3FD00000
-#define DRAM0_CACHE_ADDRESS_LOW         0x3C000000
-#define DRAM0_CACHE_ADDRESS_HIGH        0x3E000000
-#define DRAM0_CACHE_OPERATION_HIGH      DRAM0_CACHE_ADDRESS_HIGH
+#define SOC_DRAM0_ADDRESS_LOW               0x3FC88000
+#define SOC_DRAM0_ADDRESS_HIGH              0x3FD00000
+#define SOC_DRAM0_CACHE_ADDRESS_LOW         0x3C000000
+#define SOC_DRAM0_CACHE_ADDRESS_HIGH        0x3E000000
 
-#define BUS_SIZE(bus_name)                 (bus_name##_ADDRESS_HIGH - bus_name##_ADDRESS_LOW)
-#define ADDRESS_IN_BUS(bus_name, vaddr)    ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH)
+#define SOC_BUS_SIZE(bus_name)                 (bus_name##_ADDRESS_HIGH - bus_name##_ADDRESS_LOW)
+#define SOC_ADDRESS_IN_BUS(bus_name, vaddr)    ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH)
 
-#define ADDRESS_IN_IRAM0(vaddr)            ADDRESS_IN_BUS(IRAM0, vaddr)
-#define ADDRESS_IN_IRAM0_CACHE(vaddr)      ADDRESS_IN_BUS(IRAM0_CACHE, vaddr)
-#define ADDRESS_IN_DRAM0(vaddr)            ADDRESS_IN_BUS(DRAM0, vaddr)
-#define ADDRESS_IN_DRAM0_CACHE(vaddr)      ADDRESS_IN_BUS(DRAM0_CACHE, vaddr)
+#define SOC_ADDRESS_IN_IRAM0(vaddr)                SOC_ADDRESS_IN_BUS(SOC_IRAM0, vaddr)
+#define SOC_ADDRESS_IN_IRAM0_CACHE(vaddr)          SOC_ADDRESS_IN_BUS(SOC_IRAM0_CACHE, vaddr)
+#define SOC_ADDRESS_IN_DRAM0(vaddr)                SOC_ADDRESS_IN_BUS(SOC_DRAM0, vaddr)
+#define SOC_ADDRESS_IN_DRAM0_CACHE(vaddr)          SOC_ADDRESS_IN_BUS(SOC_DRAM0_CACHE, vaddr)
 
-#define BUS_IRAM0_CACHE_SIZE              BUS_SIZE(IRAM0_CACHE)
-#define BUS_DRAM0_CACHE_SIZE              BUS_SIZE(DRAM0_CACHE)
-
-#define CACHE_IBUS                      0
-#define CACHE_IBUS_MMU_START            0
-#define CACHE_IBUS_MMU_END              0x800
-
-#define CACHE_DBUS                      1
-#define CACHE_DBUS_MMU_START            0
-#define CACHE_DBUS_MMU_END              0x800
-
-//TODO, remove these cache function dependencies
-#define CACHE_IROM_MMU_START            0
-#define CACHE_IROM_MMU_END              Cache_Get_IROM_MMU_End()
-#define CACHE_IROM_MMU_SIZE             (CACHE_IROM_MMU_END - CACHE_IROM_MMU_START)
-
-#define CACHE_DROM_MMU_START            CACHE_IROM_MMU_END
-#define CACHE_DROM_MMU_END              Cache_Get_DROM_MMU_End()
-#define CACHE_DROM_MMU_SIZE             (CACHE_DROM_MMU_END - CACHE_DROM_MMU_START)
-
-#define CACHE_DROM_MMU_MAX_END          0x400
-
-#define ICACHE_MMU_SIZE                 0x800
-#define DCACHE_MMU_SIZE                 0x800
-
-#define MMU_BUS_START(i)                0
-#define MMU_BUS_SIZE(i)                 0x800
-
-#define MMU_INVALID                     BIT(14)
-#define MMU_VALID                       0
-#define MMU_TYPE                        BIT(15)
-#define MMU_ACCESS_FLASH                0
-#define MMU_ACCESS_SPIRAM               BIT(15)
-
-#define CACHE_MAX_SYNC_NUM 0x400000
-#define CACHE_MAX_LOCK_NUM 0x8000
+#define SOC_MMU_INVALID                     BIT(14)
+#define SOC_MMU_VALID                       0
+#define SOC_MMU_TYPE                        BIT(15)
+#define SOC_MMU_ACCESS_FLASH                0
+#define SOC_MMU_ACCESS_SPIRAM               BIT(15)
 
 /**
  * MMU entry valid bit mask for mapping value. For an entry:
  * valid bit + value bits
  * valid bit is BIT(14), so value bits are 0x3fff
  */
-#define MMU_VALID_VAL_MASK 0x3fff
+#define SOC_MMU_VALID_VAL_MASK 0x3fff
 /**
  * Max MMU available paddr page num.
- * `MMU_MAX_PADDR_PAGE_NUM * SOC_MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.:
+ * `SOC_MMU_MAX_PADDR_PAGE_NUM * SOC_MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.:
  * 16384 * 64KB, means MMU can support 1GB paddr at most
  */
-#define MMU_MAX_PADDR_PAGE_NUM    16384
+#define SOC_MMU_MAX_PADDR_PAGE_NUM    16384
 /**
  * This is the mask used for mapping. e.g.:
- * 0x4200_0000 & MMU_VADDR_MASK
+ * 0x4200_0000 & SOC_MMU_VADDR_MASK
  */
-#define MMU_VADDR_MASK  0x1FFFFFF
+#define SOC_MMU_VADDR_MASK  0x1FFFFFF
 //MMU entry num
-#define MMU_ENTRY_NUM   512
-
-#define CACHE_ICACHE_LOW_SHIFT         0
-#define CACHE_ICACHE_HIGH_SHIFT        2
-#define CACHE_DCACHE_LOW_SHIFT         4
-#define CACHE_DCACHE_HIGH_SHIFT        6
-
-#define CACHE_MEMORY_IBANK0_ADDR        0x40370000
-#define CACHE_MEMORY_IBANK1_ADDR        0x40374000
-
-#define CACHE_MEMORY_DBANK0_ADDR        0x3fcf0000
-#define CACHE_MEMORY_DBANK1_ADDR        0x3fcf8000
-
+#define SOC_MMU_ENTRY_NUM   512
 
 #define SOC_MMU_DBUS_VADDR_BASE               0x3C000000
 #define SOC_MMU_IBUS_VADDR_BASE               0x42000000
@@ -120,16 +76,16 @@ extern "C" {
  * - If high linear address is 0, this means MMU linear address range is equal or smaller than vaddr range.
  *   Under this condition, we use the max linear space.
  */
-#define SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW      (IRAM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
-#if ((IRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) > 0)
-#define SOC_MMU_IRAM0_LINEAR_ADDRESS_HIGH     (IRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
+#define SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW      (SOC_IRAM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
+#if ((SOC_IRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) > 0)
+#define SOC_MMU_IRAM0_LINEAR_ADDRESS_HIGH     (SOC_IRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
 #else
 #define SOC_MMU_IRAM0_LINEAR_ADDRESS_HIGH     (SOC_MMU_LINEAR_ADDR_MASK + 1)
 #endif
 
-#define SOC_MMU_DRAM0_LINEAR_ADDRESS_LOW      (DRAM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
-#if ((DRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) > 0)
-#define SOC_MMU_DRAM0_LINEAR_ADDRESS_HIGH     (DRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
+#define SOC_MMU_DRAM0_LINEAR_ADDRESS_LOW      (SOC_DRAM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
+#if ((SOC_DRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) > 0)
+#define SOC_MMU_DRAM0_LINEAR_ADDRESS_HIGH     (SOC_DRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
 #else
 #define SOC_MMU_DRAM0_LINEAR_ADDRESS_HIGH     (SOC_MMU_LINEAR_ADDR_MASK + 1)
 #endif
@@ -141,6 +97,37 @@ extern "C" {
 _Static_assert(SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW == SOC_MMU_DRAM0_LINEAR_ADDRESS_LOW, "IRAM0 and DRAM0 linear address should be same");
 #endif
 
+
+/**
+ * ROM flash mmap driver needs below definitions
+ */
+#define BUS_IRAM0_CACHE_SIZE              SOC_BUS_SIZE(SOC_IRAM0_CACHE)
+#define BUS_DRAM0_CACHE_SIZE              SOC_BUS_SIZE(SOC_DRAM0_CACHE)
+
+#define CACHE_IBUS                      0
+#define CACHE_IBUS_MMU_START            0
+#define CACHE_IBUS_MMU_END              0x800
+
+#define CACHE_DBUS                      1
+#define CACHE_DBUS_MMU_START            0
+#define CACHE_DBUS_MMU_END              0x800
+
+#define CACHE_IROM_MMU_START            0
+#define CACHE_IROM_MMU_END              Cache_Get_IROM_MMU_End()
+#define CACHE_IROM_MMU_SIZE             (CACHE_IROM_MMU_END - CACHE_IROM_MMU_START)
+
+#define CACHE_DROM_MMU_START            CACHE_IROM_MMU_END
+#define CACHE_DROM_MMU_END              Cache_Get_DROM_MMU_End()
+#define CACHE_DROM_MMU_SIZE             (CACHE_DROM_MMU_END - CACHE_DROM_MMU_START)
+
+#define CACHE_DROM_MMU_MAX_END          0x400
+
+#define ICACHE_MMU_SIZE                 0x800
+#define DCACHE_MMU_SIZE                 0x800
+
+#define MMU_BUS_START(i)                0
+#define MMU_BUS_SIZE(i)                 0x800
+
 #ifdef __cplusplus
 }
 #endif

components/soc/esp32s3/include/soc/mmu.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -20,9 +20,9 @@ extern "C" {
 #define SOC_MMU_IROM0_PAGES_END                 (CACHE_IROM_MMU_END / sizeof(uint32_t))
 #define SOC_MMU_DROM0_PAGES_START               (CACHE_DROM_MMU_START / sizeof(uint32_t))
 #define SOC_MMU_DROM0_PAGES_END                 (CACHE_DROM_MMU_END / sizeof(uint32_t))
-#define SOC_MMU_ADDR_MASK                       MMU_VALID_VAL_MASK
-#define SOC_MMU_PAGE_IN_FLASH(page)             ((page) | MMU_ACCESS_FLASH)
-#define SOC_MMU_VADDR1_START_ADDR               IRAM0_CACHE_ADDRESS_LOW
+#define SOC_MMU_ADDR_MASK                       SOC_MMU_VALID_VAL_MASK
+#define SOC_MMU_PAGE_IN_FLASH(page)             ((page) | SOC_MMU_ACCESS_FLASH)
+#define SOC_MMU_VADDR1_START_ADDR               SOC_IRAM0_CACHE_ADDRESS_LOW
 #define SOC_MMU_PRO_IRAM0_FIRST_USABLE_PAGE     SOC_MMU_IROM0_PAGES_START
 #define SOC_MMU_VADDR0_START_ADDR               (SOC_DROM_LOW + (SOC_MMU_DROM0_PAGES_START * SPI_FLASH_MMU_PAGE_SIZE))
 #define SOC_MMU_VADDR1_FIRST_USABLE_ADDR        SOC_IROM_LOW

components/spi_flash/flash_mmap.c

@@ -12,10 +12,13 @@
 #include "sdkconfig.h"
 #include "esp_attr.h"
 #include "esp_log.h"
+#include "esp_rom_caps.h"
 #include "hal/mmu_ll.h"
 #include "hal/mmu_hal.h"
 #include "hal/cache_hal.h"
+#if ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE
 #include "soc/mmu.h"
+#endif
 
 #include "esp_private/esp_mmu_map_private.h"
 #include "esp_mmu_map.h"

tools/ci/check_public_headers_exceptions.txt

@@ -256,7 +256,6 @@ components/soc/esp32c6/include/soc/mmu.h
 components/soc/esp32h2/include/soc/ext_mem_defs.h
 components/soc/esp32h2/include/soc/mmu.h
 components/soc/esp32p4/include/soc/ext_mem_defs.h
-components/soc/esp32p4/include/soc/mmu.h
 components/spi_flash/include/esp_private/spi_flash_os.h
 
 ### To be fixed: files which don't compile for esp32s2 target: