change(efuse): Update eFuses for esp32p4 chip

components/bootloader_support/src/flash_encrypt.c

@@ -139,7 +139,7 @@ esp_flash_enc_mode_t esp_get_flash_encryption_mode(void)
             if (esp_efuse_read_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT)
 #if CONFIG_IDF_TARGET_ESP32P4
                 //TODO: IDF-7545
-                && esp_efuse_read_field_bit(ESP_EFUSE_DIS_SPI_DOWNLOAD_MSPI)
+                && esp_efuse_read_field_bit(ESP_EFUSE_SPI_DOWNLOAD_MSPI_DIS)
 #else
 #if SOC_EFUSE_DIS_DOWNLOAD_ICACHE
                 && esp_efuse_read_field_bit(ESP_EFUSE_DIS_DOWNLOAD_ICACHE)
@@ -194,7 +194,7 @@ void esp_flash_encryption_set_release_mode(void)
     esp_efuse_write_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT);
 #if CONFIG_IDF_TARGET_ESP32P4
     //TODO: IDF-7545
-    esp_efuse_write_field_bit(ESP_EFUSE_DIS_SPI_DOWNLOAD_MSPI);
+    esp_efuse_write_field_bit(ESP_EFUSE_SPI_DOWNLOAD_MSPI_DIS);
 #else
 #if SOC_EFUSE_DIS_DOWNLOAD_ICACHE
     esp_efuse_write_field_bit(ESP_EFUSE_DIS_DOWNLOAD_ICACHE);
@@ -347,7 +347,7 @@ bool esp_flash_encryption_cfg_verify_release_mode(void)
 
 #if CONFIG_IDF_TARGET_ESP32P4
     //TODO: IDF-7545
-    secure = esp_efuse_read_field_bit(ESP_EFUSE_DIS_SPI_DOWNLOAD_MSPI);
+    secure = esp_efuse_read_field_bit(ESP_EFUSE_SPI_DOWNLOAD_MSPI_DIS);
     result &= secure;
     if (!secure) {
         ESP_LOGW(TAG, "Not disabled UART bootloader download mspi (set DIS_DOWNLOAD_MSPI->1)");

components/efuse/esp32p4/esp_efuse_fields.c

@@ -25,7 +25,6 @@ static __attribute__((unused)) const char *TAG = "efuse";
 uint32_t esp_efuse_get_pkg_ver(void)
 {
     uint32_t pkg_ver = 0;
-    esp_efuse_read_field_blob(ESP_EFUSE_PKG_VERSION, &pkg_ver, ESP_EFUSE_PKG_VERSION[0]->bit_count);
     return pkg_ver;
 }
 

components/efuse/esp32p4/esp_efuse_rtc_calib.c

@@ -10,75 +10,32 @@
 
 int esp_efuse_rtc_calib_get_ver(void)
 {
-    //TODO: IDF-7467
-    uint32_t result = 0;
-    esp_efuse_read_field_blob(ESP_EFUSE_BLK_VERSION_MAJOR, &result, ESP_EFUSE_BLK_VERSION_MAJOR[0]->bit_count);
-    return result;
+    //TODO: IDF-7467, eFuses are not defined yet
+    return 0;
 }
 
 uint32_t esp_efuse_rtc_calib_get_init_code(int version, uint32_t adc_unit, int atten)
 {
-    //TODO: IDF-7467, check below
-    assert(version == 1);
+    //TODO: IDF-7467, check below, eFuses are not defined yet
+    (void) version;
     (void) adc_unit;
-    const esp_efuse_desc_t** init_code_efuse;
-    assert(atten < 4);
-    if (atten == 0) {
-        init_code_efuse = ESP_EFUSE_ADC1_INIT_CODE_ATTEN0;
-    } else if (atten == 1) {
-        init_code_efuse = ESP_EFUSE_ADC1_INIT_CODE_ATTEN1;
-    } else if (atten == 2) {
-        init_code_efuse = ESP_EFUSE_ADC1_INIT_CODE_ATTEN2;
-    } else {
-        init_code_efuse = ESP_EFUSE_ADC1_INIT_CODE_ATTEN3;
-    }
-
-    int init_code_size = esp_efuse_get_field_size(init_code_efuse);
-    assert(init_code_size == 10);
-
-    uint32_t init_code = 0;
-    ESP_ERROR_CHECK(esp_efuse_read_field_blob(init_code_efuse, &init_code, init_code_size));
-    return init_code + 1000;    // version 1 logic
+    (void) atten;
+    return 0;
 }
 
 esp_err_t esp_efuse_rtc_calib_get_cal_voltage(int version, int atten, uint32_t* out_digi, uint32_t* out_vol_mv)
 {
-    //TODO: IDF-7467, check below
-    const esp_efuse_desc_t** cal_vol_efuse;
-    uint32_t calib_vol_expected_mv;
-    if (version != 1) {
-        return ESP_ERR_INVALID_ARG;
-    }
-    if (atten >= 4) {
-        return ESP_ERR_INVALID_ARG;
-    }
-    if (atten == 0) {
-        cal_vol_efuse = ESP_EFUSE_ADC1_CAL_VOL_ATTEN0;
-        calib_vol_expected_mv = 400;
-    } else if (atten == 1) {
-        cal_vol_efuse = ESP_EFUSE_ADC1_CAL_VOL_ATTEN1;
-        calib_vol_expected_mv = 550;
-    } else if (atten == 2) {
-        cal_vol_efuse = ESP_EFUSE_ADC1_CAL_VOL_ATTEN2;
-        calib_vol_expected_mv = 750;
-    } else {
-        cal_vol_efuse = ESP_EFUSE_ADC1_CAL_VOL_ATTEN3;
-        calib_vol_expected_mv = 1370;
-    }
-
-    assert(cal_vol_efuse[0]->bit_count == 10);
-
-    uint32_t cal_vol = 0;
-    ESP_ERROR_CHECK(esp_efuse_read_field_blob(cal_vol_efuse, &cal_vol, cal_vol_efuse[0]->bit_count));
-
-    *out_digi = 2000 + ((cal_vol & BIT(9))? -(cal_vol & ~BIT9): cal_vol);
-    *out_vol_mv = calib_vol_expected_mv;
-    return ESP_OK;
+    //TODO: IDF-7467, check below, eFuses are not defined yet
+    (void) version;
+    (void) atten;
+    (void) out_digi;
+    (void) out_vol_mv;
+    return ESP_ERR_NOT_SUPPORTED;
 }
 
 esp_err_t esp_efuse_rtc_calib_get_tsens_val(float* tsens_cal)
 {
     //TODO: IDF-7482
     *tsens_cal = 0;
-    return ESP_OK;
+    return ESP_ERR_NOT_SUPPORTED;
 }

components/efuse/esp32p4/esp_efuse_table.c

@@ -9,557 +9,440 @@
 #include <assert.h>
 #include "esp_efuse_table.h"
 
-// md5_digest_table 57d7fbd8410e3a4d1e0d19e39b9cb3c0
+// md5_digest_table 78dff63df528392f0f37f4880b83c6db
 // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
 // If you want to change some fields, you need to change esp_efuse_table.csv file
 // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
 // To show efuse_table run the command 'show_efuse_table'.
 
 static const esp_efuse_desc_t WR_DIS[] = {
-    {EFUSE_BLK0, 0, 32}, 	 // Write protection,
+    {EFUSE_BLK0, 0, 32}, 	 // [] Disable programming of individual eFuses,
 };
 
 static const esp_efuse_desc_t WR_DIS_RD_DIS[] = {
-    {EFUSE_BLK0, 0, 1}, 	 // Write protection for RD_DIS_KEY0 RD_DIS_KEY1 RD_DIS_KEY2 RD_DIS_KEY3 RD_DIS_KEY4 RD_DIS_KEY5 RD_DIS_SYS_DATA_PART2,
-};
-
-static const esp_efuse_desc_t WR_DIS_GROUP_1[] = {
-    {EFUSE_BLK0, 1, 1}, 	 // Write protection for KM_RND_SWITCH_CYCLE KM_DEPLOY_ONLY_ONCE FORCE_USE_KEY_MANAGER_KEY FORCE_DISABLE_SW_INIT_KEY,
-};
-
-static const esp_efuse_desc_t WR_DIS_GROUP_2[] = {
-    {EFUSE_BLK0, 2, 1}, 	 // Write protection for DIS_USB_JTAG POWERGLITCH_EN DIS_USB_DERIAL_JTAG DIS_FORCE_DOWNLOAD DIS_TWAI JTAG_SEL_ENABLE DIS_PAD_JTAG DIS_DOWNLOAD_MANUAL_ENCRYPT WDT_DELAY_SEL HYS_EN_PAD _0PXA_TIEH_SEL_0 _0PXA_TIEH_SEL_1 _0PXA_TIEH_SEL_2 _0PXA_TIEH_SEL_3 DIS_WDT DIS_SWD,
-};
-
-static const esp_efuse_desc_t WR_DIS_HP_PWR_SRC_SEL[] = {
-    {EFUSE_BLK0, 3, 1}, 	 // Write protection for HP_PWR_SRC_SEL,
+    {EFUSE_BLK0, 0, 1}, 	 // [] wr_dis of RD_DIS,
 };
 
 static const esp_efuse_desc_t WR_DIS_SPI_BOOT_CRYPT_CNT[] = {
-    {EFUSE_BLK0, 4, 1}, 	 // Write protection for SPI_BOOT_CRYPT_CNT,
+    {EFUSE_BLK0, 4, 1}, 	 // [] wr_dis of SPI_BOOT_CRYPT_CNT,
 };
 
 static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_KEY_REVOKE0[] = {
-    {EFUSE_BLK0, 5, 1}, 	 // Write protection for SECURE_BOOT_KEY_REVOKE0,
+    {EFUSE_BLK0, 5, 1}, 	 // [] wr_dis of SECURE_BOOT_KEY_REVOKE0,
 };
 
 static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_KEY_REVOKE1[] = {
-    {EFUSE_BLK0, 6, 1}, 	 // Write protection for SECURE_BOOT_KEY_REVOKE1,
+    {EFUSE_BLK0, 6, 1}, 	 // [] wr_dis of SECURE_BOOT_KEY_REVOKE1,
 };
 
 static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_KEY_REVOKE2[] = {
-    {EFUSE_BLK0, 7, 1}, 	 // Write protection for SECURE_BOOT_KEY_REVOKE2,
+    {EFUSE_BLK0, 7, 1}, 	 // [] wr_dis of SECURE_BOOT_KEY_REVOKE2,
 };
 
-static const esp_efuse_desc_t WR_DIS_KEY0_PURPOSE[] = {
-    {EFUSE_BLK0, 8, 1}, 	 // Write protection for key_purpose. KEY0,
+static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_0[] = {
+    {EFUSE_BLK0, 8, 1}, 	 // [WR_DIS.KEY0_PURPOSE] wr_dis of KEY_PURPOSE_0,
 };
 
-static const esp_efuse_desc_t WR_DIS_KEY1_PURPOSE[] = {
-    {EFUSE_BLK0, 9, 1}, 	 // Write protection for key_purpose. KEY1,
+static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_1[] = {
+    {EFUSE_BLK0, 9, 1}, 	 // [WR_DIS.KEY1_PURPOSE] wr_dis of KEY_PURPOSE_1,
 };
 
-static const esp_efuse_desc_t WR_DIS_KEY2_PURPOSE[] = {
-    {EFUSE_BLK0, 10, 1}, 	 // Write protection for key_purpose. KEY2,
+static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_2[] = {
+    {EFUSE_BLK0, 10, 1}, 	 // [WR_DIS.KEY2_PURPOSE] wr_dis of KEY_PURPOSE_2,
 };
 
-static const esp_efuse_desc_t WR_DIS_KEY3_PURPOSE[] = {
-    {EFUSE_BLK0, 11, 1}, 	 // Write protection for key_purpose. KEY3,
+static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_3[] = {
+    {EFUSE_BLK0, 11, 1}, 	 // [WR_DIS.KEY3_PURPOSE] wr_dis of KEY_PURPOSE_3,
 };
 
-static const esp_efuse_desc_t WR_DIS_KEY4_PURPOSE[] = {
-    {EFUSE_BLK0, 12, 1}, 	 // Write protection for key_purpose. KEY4,
+static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_4[] = {
+    {EFUSE_BLK0, 12, 1}, 	 // [WR_DIS.KEY4_PURPOSE] wr_dis of KEY_PURPOSE_4,
 };
 
-static const esp_efuse_desc_t WR_DIS_KEY5_PURPOSE[] = {
-    {EFUSE_BLK0, 13, 1}, 	 // Write protection for key_purpose. KEY5,
-};
-
-static const esp_efuse_desc_t WR_DIS_GROUP_3[] = {
-    {EFUSE_BLK0, 14, 1}, 	 // Write protection for SEC_DPA_LEVEL CRYPT_DPA_ENABLE,
+static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_5[] = {
+    {EFUSE_BLK0, 13, 1}, 	 // [WR_DIS.KEY5_PURPOSE] wr_dis of KEY_PURPOSE_5,
 };
 
 static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_EN[] = {
-    {EFUSE_BLK0, 15, 1}, 	 // Write protection for SECURE_BOOT_EN,
-};
-
-static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[] = {
-    {EFUSE_BLK0, 16, 1}, 	 // Write protection for SECURE_BOOT_AGGRESSIVE_REVOKE,
-};
-
-static const esp_efuse_desc_t WR_DIS_ECDSA_FORCE_USE_HARDWARE_K[] = {
-    {EFUSE_BLK0, 17, 1}, 	 // Write protection for ECDSA_FORCE_USE_HARDWARE_K,
-};
-
-static const esp_efuse_desc_t WR_DIS_GROUP_4[] = {
-    {EFUSE_BLK0, 18, 1}, 	 // Write protection for FLASH_TYPE FLASH_PAGE_SIZE FLASH_ECC_EN DIS_USB_OTG_DOWNLOAD_MODE FLASH_TPUW DIS_DOWNLOAD_MODE DIS_DIRECT_BOOT DIS_USB_SERIAL_JTAG_ROM_PRINT DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE ENABLE_SECURITY_DOWNLOAD UART_PRINT_CONTROL FORCE_SEND_RESUME SECURE_VERSION SECURE_BOOT_DISABLE_FAST_WAKE,
-};
-
-static const esp_efuse_desc_t WR_DIS_HUK_GEN_STATE[] = {
-    {EFUSE_BLK0, 19, 1}, 	 // Write protection for HUK_GEN_STATE,
+    {EFUSE_BLK0, 15, 1}, 	 // [] wr_dis of SECURE_BOOT_EN,
 };
 
 static const esp_efuse_desc_t WR_DIS_BLK1[] = {
-    {EFUSE_BLK0, 20, 1}, 	 // Write protection for EFUSE_BLK1.  MAC_SPI_8M_SYS,
+    {EFUSE_BLK0, 20, 1}, 	 // [] wr_dis of BLOCK1,
 };
 
-static const esp_efuse_desc_t WR_DIS_SYS_DATA_PART1[] = {
-    {EFUSE_BLK0, 21, 1}, 	 // Write protection for EFUSE_BLK2.  SYS_DATA_PART1,
+static const esp_efuse_desc_t WR_DIS_MAC[] = {
+    {EFUSE_BLK0, 20, 1}, 	 // [WR_DIS.MAC_FACTORY] wr_dis of MAC,
 };
 
-static const esp_efuse_desc_t WR_DIS_USER_DATA[] = {
-    {EFUSE_BLK0, 22, 1}, 	 // Write protection for EFUSE_BLK3.  USER_DATA,
+static const esp_efuse_desc_t WR_DIS_MAC_EXT[] = {
+    {EFUSE_BLK0, 20, 1}, 	 // [] wr_dis of MAC_EXT,
 };
 
-static const esp_efuse_desc_t WR_DIS_KEY0[] = {
-    {EFUSE_BLK0, 23, 1}, 	 // Write protection for EFUSE_BLK4.  KEY0,
+static const esp_efuse_desc_t WR_DIS_BLOCK_SYS_DATA1[] = {
+    {EFUSE_BLK0, 21, 1}, 	 // [WR_DIS.SYS_DATA_PART1] wr_dis of BLOCK_SYS_DATA1,
 };
 
-static const esp_efuse_desc_t WR_DIS_KEY1[] = {
-    {EFUSE_BLK0, 24, 1}, 	 // Write protection for EFUSE_BLK5.  KEY1,
+static const esp_efuse_desc_t WR_DIS_BLOCK_USR_DATA[] = {
+    {EFUSE_BLK0, 22, 1}, 	 // [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA,
 };
 
-static const esp_efuse_desc_t WR_DIS_KEY2[] = {
-    {EFUSE_BLK0, 25, 1}, 	 // Write protection for EFUSE_BLK6.  KEY2,
+static const esp_efuse_desc_t WR_DIS_BLOCK_KEY0[] = {
+    {EFUSE_BLK0, 23, 1}, 	 // [WR_DIS.KEY0] wr_dis of BLOCK_KEY0,
 };
 
-static const esp_efuse_desc_t WR_DIS_KEY3[] = {
-    {EFUSE_BLK0, 26, 1}, 	 // Write protection for EFUSE_BLK7.  KEY3,
+static const esp_efuse_desc_t WR_DIS_BLOCK_KEY1[] = {
+    {EFUSE_BLK0, 24, 1}, 	 // [WR_DIS.KEY1] wr_dis of BLOCK_KEY1,
 };
 
-static const esp_efuse_desc_t WR_DIS_KEY4[] = {
-    {EFUSE_BLK0, 27, 1}, 	 // Write protection for EFUSE_BLK8.  KEY4,
+static const esp_efuse_desc_t WR_DIS_BLOCK_KEY2[] = {
+    {EFUSE_BLK0, 25, 1}, 	 // [WR_DIS.KEY2] wr_dis of BLOCK_KEY2,
 };
 
-static const esp_efuse_desc_t WR_DIS_KEY5[] = {
-    {EFUSE_BLK0, 28, 1}, 	 // Write protection for EFUSE_BLK9.  KEY5,
+static const esp_efuse_desc_t WR_DIS_BLOCK_KEY3[] = {
+    {EFUSE_BLK0, 26, 1}, 	 // [WR_DIS.KEY3] wr_dis of BLOCK_KEY3,
 };
 
-static const esp_efuse_desc_t WR_DIS_SYS_DATA_PART2[] = {
-    {EFUSE_BLK0, 29, 1}, 	 // Write protection for EFUSE_BLK10. SYS_DATA_PART2,
+static const esp_efuse_desc_t WR_DIS_BLOCK_KEY4[] = {
+    {EFUSE_BLK0, 27, 1}, 	 // [WR_DIS.KEY4] wr_dis of BLOCK_KEY4,
 };
 
-static const esp_efuse_desc_t WR_DIS_GROUP_5[] = {
-    {EFUSE_BLK0, 30, 1}, 	 // Write protection for USB_DEVICE_EXCHG_PINS USB_OTG11_EXCHG_PINS USB_DEVICE_DREFH USB_OTG11_DREFH USB_PHY_SEL USB_DEVICE_DREFL USB_OTG11_DREFL,
+static const esp_efuse_desc_t WR_DIS_BLOCK_KEY5[] = {
+    {EFUSE_BLK0, 28, 1}, 	 // [WR_DIS.KEY5] wr_dis of BLOCK_KEY5,
 };
 
-static const esp_efuse_desc_t WR_DIS_SOFT_DIS_JTAG[] = {
-    {EFUSE_BLK0, 31, 1}, 	 // Write protection for SOFT_DIS_JTAG,
+static const esp_efuse_desc_t WR_DIS_BLOCK_SYS_DATA2[] = {
+    {EFUSE_BLK0, 29, 1}, 	 // [WR_DIS.SYS_DATA_PART2] wr_dis of BLOCK_SYS_DATA2,
 };
 
 static const esp_efuse_desc_t RD_DIS[] = {
-    {EFUSE_BLK0, 32, 7}, 	 // Read protection,
+    {EFUSE_BLK0, 32, 7}, 	 // [] Disable reading from BlOCK4-10,
 };
 
-static const esp_efuse_desc_t RD_DIS_KEY0[] = {
-    {EFUSE_BLK0, 32, 1}, 	 // Read protection for EFUSE_BLK4.  KEY0,
+static const esp_efuse_desc_t RD_DIS_BLOCK_KEY0[] = {
+    {EFUSE_BLK0, 32, 1}, 	 // [RD_DIS.KEY0] rd_dis of BLOCK_KEY0,
 };
 
-static const esp_efuse_desc_t RD_DIS_KEY1[] = {
-    {EFUSE_BLK0, 33, 1}, 	 // Read protection for EFUSE_BLK5.  KEY1,
+static const esp_efuse_desc_t RD_DIS_BLOCK_KEY1[] = {
+    {EFUSE_BLK0, 33, 1}, 	 // [RD_DIS.KEY1] rd_dis of BLOCK_KEY1,
 };
 
-static const esp_efuse_desc_t RD_DIS_KEY2[] = {
-    {EFUSE_BLK0, 34, 1}, 	 // Read protection for EFUSE_BLK6.  KEY2,
+static const esp_efuse_desc_t RD_DIS_BLOCK_KEY2[] = {
+    {EFUSE_BLK0, 34, 1}, 	 // [RD_DIS.KEY2] rd_dis of BLOCK_KEY2,
 };
 
-static const esp_efuse_desc_t RD_DIS_KEY3[] = {
-    {EFUSE_BLK0, 35, 1}, 	 // Read protection for EFUSE_BLK7.  KEY3,
+static const esp_efuse_desc_t RD_DIS_BLOCK_KEY3[] = {
+    {EFUSE_BLK0, 35, 1}, 	 // [RD_DIS.KEY3] rd_dis of BLOCK_KEY3,
 };
 
-static const esp_efuse_desc_t RD_DIS_KEY4[] = {
-    {EFUSE_BLK0, 36, 1}, 	 // Read protection for EFUSE_BLK8.  KEY4,
+static const esp_efuse_desc_t RD_DIS_BLOCK_KEY4[] = {
+    {EFUSE_BLK0, 36, 1}, 	 // [RD_DIS.KEY4] rd_dis of BLOCK_KEY4,
 };
 
-static const esp_efuse_desc_t RD_DIS_KEY5[] = {
-    {EFUSE_BLK0, 37, 1}, 	 // Read protection for EFUSE_BLK9.  KEY5,
+static const esp_efuse_desc_t RD_DIS_BLOCK_KEY5[] = {
+    {EFUSE_BLK0, 37, 1}, 	 // [RD_DIS.KEY5] rd_dis of BLOCK_KEY5,
 };
 
-static const esp_efuse_desc_t RD_DIS_SYS_DATA_PART2[] = {
-    {EFUSE_BLK0, 38, 1}, 	 // Read protection for EFUSE_BLK10. SYS_DATA_PART2,
+static const esp_efuse_desc_t RD_DIS_BLOCK_SYS_DATA2[] = {
+    {EFUSE_BLK0, 38, 1}, 	 // [RD_DIS.SYS_DATA_PART2] rd_dis of BLOCK_SYS_DATA2,
 };
 
 static const esp_efuse_desc_t USB_DEVICE_EXCHG_PINS[] = {
-    {EFUSE_BLK0, 39, 1}, 	 // USB-device exchange pins,
+    {EFUSE_BLK0, 39, 1}, 	 // [] Enable usb device exchange pins of D+ and D-,
 };
 
 static const esp_efuse_desc_t USB_OTG11_EXCHG_PINS[] = {
-    {EFUSE_BLK0, 40, 1}, 	 // USB-otg11 change pins,
+    {EFUSE_BLK0, 40, 1}, 	 // [] Enable usb otg11 exchange pins of D+ and D-,
 };
 
 static const esp_efuse_desc_t DIS_USB_JTAG[] = {
-    {EFUSE_BLK0, 41, 1}, 	 // Disable USB JTAG,
+    {EFUSE_BLK0, 41, 1}, 	 // [] Represents whether the function of usb switch to jtag is disabled or enabled. 1: disabled. 0: enabled,
 };
 
 static const esp_efuse_desc_t POWERGLITCH_EN[] = {
-    {EFUSE_BLK0, 42, 1}, 	 // Power glitch enable,
-};
-
-static const esp_efuse_desc_t DIS_USB_SERIAL_JTAG[] = {
-    {EFUSE_BLK0, 43, 1}, 	 // Disable USB_SERIAL_JTAG,
+    {EFUSE_BLK0, 42, 1}, 	 // [] Represents whether power glitch function is enabled. 1: enabled. 0: disabled,
 };
 
 static const esp_efuse_desc_t DIS_FORCE_DOWNLOAD[] = {
-    {EFUSE_BLK0, 44, 1}, 	 // Disable force chip go to download mode function,
+    {EFUSE_BLK0, 44, 1}, 	 // [] Represents whether the function that forces chip into download mode is disabled or enabled. 1: disabled. 0: enabled,
 };
 
-static const esp_efuse_desc_t DIS_SPI_DOWNLOAD_MSPI[] = {
-    {EFUSE_BLK0, 45, 1}, 	 // Represents whether the SPI0 controller is disabled in boot_mode_download,
+static const esp_efuse_desc_t SPI_DOWNLOAD_MSPI_DIS[] = {
+    {EFUSE_BLK0, 45, 1}, 	 // [] Set this bit to disable accessing MSPI flash/MSPI ram by SYS AXI matrix during boot_mode_download,
 };
 
 static const esp_efuse_desc_t DIS_TWAI[] = {
-    {EFUSE_BLK0, 46, 1}, 	 // Disable TWAI function,
+    {EFUSE_BLK0, 46, 1}, 	 // [] Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled,
 };
 
 static const esp_efuse_desc_t JTAG_SEL_ENABLE[] = {
-    {EFUSE_BLK0, 47, 1}, 	 // Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0.,
+    {EFUSE_BLK0, 47, 1}, 	 // [] Represents whether the selection between usb_to_jtag and pad_to_jtag through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled. 1: enabled. 0: disabled,
 };
 
 static const esp_efuse_desc_t SOFT_DIS_JTAG[] = {
-    {EFUSE_BLK0, 48, 3}, 	 // Set these bits to soft disable JTAG (odd number 1 means disable). JTAG can be enabled in HMAC module.,
+    {EFUSE_BLK0, 48, 3}, 	 // [] Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number: enabled,
 };
 
 static const esp_efuse_desc_t DIS_PAD_JTAG[] = {
-    {EFUSE_BLK0, 51, 1}, 	 // Hard disable JTAG. JTAG is disabled permanently.,
+    {EFUSE_BLK0, 51, 1}, 	 // [] Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: enabled,
 };
 
 static const esp_efuse_desc_t DIS_DOWNLOAD_MANUAL_ENCRYPT[] = {
-    {EFUSE_BLK0, 52, 1}, 	 // Disable flash encryption when in download boot modes.,
-};
-
-static const esp_efuse_desc_t USB_DEVICE_DREFH[] = {
-    {EFUSE_BLK0, 53, 2}, 	 // USB-device drefh,
+    {EFUSE_BLK0, 52, 1}, 	 // [] Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode). 1: disabled. 0: enabled,
 };
 
-static const esp_efuse_desc_t USB_OTG11_DREFH[] = {
-    {EFUSE_BLK0, 55, 2}, 	 // USB-otg11 drefh,
+static const esp_efuse_desc_t USB_PHY_SEL[] = {
+    {EFUSE_BLK0, 57, 1}, 	 // [] TBD,
 };
 
-static const esp_efuse_desc_t USB_PHY_SEL[] = {
-    {EFUSE_BLK0, 57, 1}, 	 // Select usb phy,
+static const esp_efuse_desc_t KM_HUK_GEN_STATE_LOW[] = {
+    {EFUSE_BLK0, 58, 6}, 	 // [] Set this bit to control validation of HUK generate mode. Odd of 1 is invalid; even of 1 is valid,
 };
 
-static const esp_efuse_desc_t HUK_GEN_STATE[] = {
-    {EFUSE_BLK0, 58, 9}, 	 // HUK generator state,
+static const esp_efuse_desc_t KM_HUK_GEN_STATE_HIGH[] = {
+    {EFUSE_BLK0, 64, 3}, 	 // [] Set this bit to control validation of HUK generate mode. Odd of 1 is invalid; even of 1 is valid,
 };
 
 static const esp_efuse_desc_t KM_RND_SWITCH_CYCLE[] = {
-    {EFUSE_BLK0, 67, 2}, 	 // km random switch cycle,
+    {EFUSE_BLK0, 67, 2}, 	 // [] Set bits to control key manager random number switch cycle. 0: control by register. 1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles,
 };
 
 static const esp_efuse_desc_t KM_DEPLOY_ONLY_ONCE[] = {
-    {EFUSE_BLK0, 69, 4}, 	 // km deploy only once,
+    {EFUSE_BLK0, 69, 4}, 	 // [] Set each bit to control whether corresponding key can only be deployed once. 1 is true; 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds,
 };
 
 static const esp_efuse_desc_t FORCE_USE_KEY_MANAGER_KEY[] = {
-    {EFUSE_BLK0, 73, 4}, 	 // force use key manager key,
+    {EFUSE_BLK0, 73, 4}, 	 // [] Set each bit to control whether corresponding key must come from key manager.. 1 is true; 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds,
 };
 
 static const esp_efuse_desc_t FORCE_DISABLE_SW_INIT_KEY[] = {
-    {EFUSE_BLK0, 77, 1}, 	 // force disable software init key,
+    {EFUSE_BLK0, 77, 1}, 	 // [] Set this bit to disable software written init key; and force use efuse_init_key,
+};
+
+static const esp_efuse_desc_t XTS_KEY_LENGTH_256[] = {
+    {EFUSE_BLK0, 78, 1}, 	 // [] Set this bit to configure flash encryption use xts-128 key; else use xts-256 key,
 };
 
 static const esp_efuse_desc_t WDT_DELAY_SEL[] = {
-    {EFUSE_BLK0, 80, 2}, 	 // watchdog delay selection,
+    {EFUSE_BLK0, 80, 2}, 	 // [] Represents whether RTC watchdog timeout threshold is selected at startup. 1: selected. 0: not selected,
 };
 
 static const esp_efuse_desc_t SPI_BOOT_CRYPT_CNT[] = {
-    {EFUSE_BLK0, 82, 3}, 	 // spi boot encryption counter,
+    {EFUSE_BLK0, 82, 3}, 	 // [] Enables flash encryption when 1 or 3 bits are set and disables otherwise {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"},
 };
 
 static const esp_efuse_desc_t SECURE_BOOT_KEY_REVOKE0[] = {
-    {EFUSE_BLK0, 85, 1}, 	 // Enable revoke first secure boot key,
+    {EFUSE_BLK0, 85, 1}, 	 // [] Revoke 1st secure boot key,
 };
 
 static const esp_efuse_desc_t SECURE_BOOT_KEY_REVOKE1[] = {
-    {EFUSE_BLK0, 86, 1}, 	 // Enable revoke second secure boot key,
+    {EFUSE_BLK0, 86, 1}, 	 // [] Revoke 2nd secure boot key,
 };
 
 static const esp_efuse_desc_t SECURE_BOOT_KEY_REVOKE2[] = {
-    {EFUSE_BLK0, 87, 1}, 	 // Enable revoke third secure boot key,
+    {EFUSE_BLK0, 87, 1}, 	 // [] Revoke 3rd secure boot key,
 };
 
 static const esp_efuse_desc_t KEY_PURPOSE_0[] = {
-    {EFUSE_BLK0, 88, 4}, 	 // Key0 purpose,
+    {EFUSE_BLK0, 88, 4}, 	 // [KEY0_PURPOSE] Represents the purpose of Key0,
 };
 
 static const esp_efuse_desc_t KEY_PURPOSE_1[] = {
-    {EFUSE_BLK0, 92, 4}, 	 // Key1 purpose,
+    {EFUSE_BLK0, 92, 4}, 	 // [KEY1_PURPOSE] Represents the purpose of Key1,
 };
 
 static const esp_efuse_desc_t KEY_PURPOSE_2[] = {
-    {EFUSE_BLK0, 96, 4}, 	 // Key2 purpose,
+    {EFUSE_BLK0, 96, 4}, 	 // [KEY2_PURPOSE] Represents the purpose of Key2,
 };
 
 static const esp_efuse_desc_t KEY_PURPOSE_3[] = {
-    {EFUSE_BLK0, 100, 4}, 	 // Key3 purpose,
+    {EFUSE_BLK0, 100, 4}, 	 // [KEY3_PURPOSE] Represents the purpose of Key3,
 };
 
 static const esp_efuse_desc_t KEY_PURPOSE_4[] = {
-    {EFUSE_BLK0, 104, 4}, 	 // Key4 purpose,
+    {EFUSE_BLK0, 104, 4}, 	 // [KEY4_PURPOSE] Represents the purpose of Key4,
 };
 
 static const esp_efuse_desc_t KEY_PURPOSE_5[] = {
-    {EFUSE_BLK0, 108, 4}, 	 // Key5 purpose,
+    {EFUSE_BLK0, 108, 4}, 	 // [KEY5_PURPOSE] Represents the purpose of Key5,
 };
 
 static const esp_efuse_desc_t SEC_DPA_LEVEL[] = {
-    {EFUSE_BLK0, 112, 2}, 	 // Configures the clock random divide mode to determine the DPA security level,
+    {EFUSE_BLK0, 112, 2}, 	 // [] Represents the spa secure level by configuring the clock random divide mode,
 };
 
-static const esp_efuse_desc_t ECDSA_FORCE_USE_HARDWARE_K[] = {
-    {EFUSE_BLK0, 114, 1}, 	 // ecdsa force use hardware key,
+static const esp_efuse_desc_t ECDSA_ENABLE_SOFT_K[] = {
+    {EFUSE_BLK0, 114, 1}, 	 // [] Represents whether hardware random number k is forced used in ESDCA. 1: force used. 0: not force used,
 };
 
 static const esp_efuse_desc_t CRYPT_DPA_ENABLE[] = {
-    {EFUSE_BLK0, 115, 1}, 	 // Represents whether defense against DPA attack is enabled,
+    {EFUSE_BLK0, 115, 1}, 	 // [] Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled,
 };
 
 static const esp_efuse_desc_t SECURE_BOOT_EN[] = {
-    {EFUSE_BLK0, 116, 1}, 	 // Secure boot enable,
+    {EFUSE_BLK0, 116, 1}, 	 // [] Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled,
 };
 
 static const esp_efuse_desc_t SECURE_BOOT_AGGRESSIVE_REVOKE[] = {
-    {EFUSE_BLK0, 117, 1}, 	 // Enable aggressive secure boot revoke,
+    {EFUSE_BLK0, 117, 1}, 	 // [] Represents whether revoking aggressive secure boot is enabled or disabled. 1: enabled. 0: disabled,
 };
 
 static const esp_efuse_desc_t FLASH_TYPE[] = {
-    {EFUSE_BLK0, 119, 1}, 	 // flash type,
+    {EFUSE_BLK0, 119, 1}, 	 // [] The type of interfaced flash. 0: four data lines; 1: eight data lines,
 };
 
 static const esp_efuse_desc_t FLASH_PAGE_SIZE[] = {
-    {EFUSE_BLK0, 120, 2}, 	 // flash page size,
+    {EFUSE_BLK0, 120, 2}, 	 // [] Set flash page size,
 };
 
 static const esp_efuse_desc_t FLASH_ECC_EN[] = {
-    {EFUSE_BLK0, 122, 1}, 	 // flash ecc enable,
+    {EFUSE_BLK0, 122, 1}, 	 // [] Set this bit to enable ecc for flash boot,
 };
 
 static const esp_efuse_desc_t DIS_USB_OTG_DOWNLOAD_MODE[] = {
-    {EFUSE_BLK0, 123, 1}, 	 // disable use otg download mode,
+    {EFUSE_BLK0, 123, 1}, 	 // [] Set this bit to disable download via USB-OTG,
 };
 
 static const esp_efuse_desc_t FLASH_TPUW[] = {
-    {EFUSE_BLK0, 124, 4}, 	 // flash tpuw,
+    {EFUSE_BLK0, 124, 4}, 	 // [] Represents the flash waiting time after power-up; in unit of ms. When the value less than 15; the waiting time is the programmed value. Otherwise; the waiting time is 2 times the programmed value,
 };
 
 static const esp_efuse_desc_t DIS_DOWNLOAD_MODE[] = {
-    {EFUSE_BLK0, 128, 1}, 	 // Disble download mode,
+    {EFUSE_BLK0, 128, 1}, 	 // [] Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled,
 };
 
 static const esp_efuse_desc_t DIS_DIRECT_BOOT[] = {
-    {EFUSE_BLK0, 129, 1}, 	 // Disable direct boot mode,
+    {EFUSE_BLK0, 129, 1}, 	 // [] Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled,
 };
 
 static const esp_efuse_desc_t DIS_USB_SERIAL_JTAG_ROM_PRINT[] = {
-    {EFUSE_BLK0, 130, 1}, 	 // Represents whether print from USB-Serial-JTAG during ROM boot is disabled,
+    {EFUSE_BLK0, 130, 1}, 	 // [] Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled,
+};
+
+static const esp_efuse_desc_t LOCK_KM_KEY[] = {
+    {EFUSE_BLK0, 131, 1}, 	 // [] TBD,
 };
 
 static const esp_efuse_desc_t DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[] = {
-    {EFUSE_BLK0, 132, 1}, 	 // Represents whether the USB-Serial-JTAG download func- tion is disabled,
+    {EFUSE_BLK0, 132, 1}, 	 // [] Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: disabled. 0: enabled,
 };
 
 static const esp_efuse_desc_t ENABLE_SECURITY_DOWNLOAD[] = {
-    {EFUSE_BLK0, 133, 1}, 	 // Enable secure download mode,
+    {EFUSE_BLK0, 133, 1}, 	 // [] Represents whether security download is enabled or disabled. 1: enabled. 0: disabled,
 };
 
 static const esp_efuse_desc_t UART_PRINT_CONTROL[] = {
-    {EFUSE_BLK0, 134, 2}, 	 // b00:force print. b01:control by GPIO8 - low level print. b10:control by GPIO8 - high level print. b11:force disable print.,
+    {EFUSE_BLK0, 134, 2}, 	 // [] Represents the type of UART printing. 00: force enable printing. 01: enable printing when GPIO8 is reset at low level. 10: enable printing when GPIO8 is reset at high level. 11: force disable printing,
 };
 
 static const esp_efuse_desc_t FORCE_SEND_RESUME[] = {
-    {EFUSE_BLK0, 136, 1}, 	 // Force ROM code to send a resume command during SPI boot,
+    {EFUSE_BLK0, 136, 1}, 	 // [] Represents whether ROM code is forced to send a resume command during SPI boot. 1: forced. 0:not forced,
 };
 
 static const esp_efuse_desc_t SECURE_VERSION[] = {
-    {EFUSE_BLK0, 137, 16}, 	 // Secure version for anti-rollback,
+    {EFUSE_BLK0, 137, 16}, 	 // [] Represents the version used by ESP-IDF anti-rollback feature,
 };
 
 static const esp_efuse_desc_t SECURE_BOOT_DISABLE_FAST_WAKE[] = {
-    {EFUSE_BLK0, 153, 1}, 	 // Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled,
+    {EFUSE_BLK0, 153, 1}, 	 // [] Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled. 1: disabled. 0: enabled,
 };
 
 static const esp_efuse_desc_t HYS_EN_PAD[] = {
-    {EFUSE_BLK0, 154, 1}, 	 // Hys en pad,
+    {EFUSE_BLK0, 154, 1}, 	 // [] Represents whether the hysteresis function of corresponding PAD is enabled. 1: enabled. 0:disabled,
 };
 
 static const esp_efuse_desc_t DCDC_VSET[] = {
-    {EFUSE_BLK0, 155, 5}, 	 // dcdc vset,
-};
-
-static const esp_efuse_desc_t _0PXA_TIEH_SEL_0[] = {
-    {EFUSE_BLK0, 160, 2}, 	 // 0pxa tieh sel0,
+    {EFUSE_BLK0, 155, 5}, 	 // [] Set the dcdc voltage default,
 };
 
-static const esp_efuse_desc_t _0PXA_TIEH_SEL_1[] = {
-    {EFUSE_BLK0, 162, 2}, 	 // 0pxa tieh sel1,
+static const esp_efuse_desc_t PXA0_TIEH_SEL_0[] = {
+    {EFUSE_BLK0, 160, 2}, 	 // [] TBD,
 };
 
-static const esp_efuse_desc_t _0PXA_TIEH_SEL_2[] = {
-    {EFUSE_BLK0, 164, 2}, 	 // 0pxa tieh sel2,
+static const esp_efuse_desc_t PXA0_TIEH_SEL_1[] = {
+    {EFUSE_BLK0, 162, 2}, 	 // [] TBD,
 };
 
-static const esp_efuse_desc_t _0PXA_TIEH_SEL_3[] = {
-    {EFUSE_BLK0, 166, 2}, 	 // 0pxa tieh sel3,
+static const esp_efuse_desc_t PXA0_TIEH_SEL_2[] = {
+    {EFUSE_BLK0, 164, 2}, 	 // [] TBD,
 };
 
-static const esp_efuse_desc_t USB_DEVICE_DREFL[] = {
-    {EFUSE_BLK0, 172, 2}, 	 // usb device drefl,
+static const esp_efuse_desc_t PXA0_TIEH_SEL_3[] = {
+    {EFUSE_BLK0, 166, 2}, 	 // [] TBD,
 };
 
-static const esp_efuse_desc_t USB_OTG11_DREFL[] = {
-    {EFUSE_BLK0, 174, 2}, 	 // usb otg1.1 drefl,
+static const esp_efuse_desc_t KM_DISABLE_DEPLOY_MODE[] = {
+    {EFUSE_BLK0, 168, 4}, 	 // [] TBD,
 };
 
 static const esp_efuse_desc_t HP_PWR_SRC_SEL[] = {
-    {EFUSE_BLK0, 178, 1}, 	 // hp power source selection,
+    {EFUSE_BLK0, 178, 1}, 	 // [] HP system power source select. 0:LDO. 1: DCDC,
 };
 
 static const esp_efuse_desc_t DCDC_VSET_EN[] = {
-    {EFUSE_BLK0, 179, 1}, 	 // dcdc vset enable,
+    {EFUSE_BLK0, 179, 1}, 	 // [] Select dcdc vset use efuse_dcdc_vset,
 };
 
 static const esp_efuse_desc_t DIS_WDT[] = {
-    {EFUSE_BLK0, 180, 1}, 	 // disable watchdog,
+    {EFUSE_BLK0, 180, 1}, 	 // [] Set this bit to disable watch dog,
 };
 
 static const esp_efuse_desc_t DIS_SWD[] = {
-    {EFUSE_BLK0, 181, 1}, 	 // disable super watchdog,
+    {EFUSE_BLK0, 181, 1}, 	 // [] Set this bit to disable super-watchdog,
 };
 
-static const esp_efuse_desc_t MAC_FACTORY[] = {
-    {EFUSE_BLK1, 40, 8}, 	 // Factory MAC addr [0],
-    {EFUSE_BLK1, 32, 8}, 	 // Factory MAC addr [1],
-    {EFUSE_BLK1, 24, 8}, 	 // Factory MAC addr [2],
-    {EFUSE_BLK1, 16, 8}, 	 // Factory MAC addr [3],
-    {EFUSE_BLK1, 8, 8}, 	 // Factory MAC addr [4],
-    {EFUSE_BLK1, 0, 8}, 	 // Factory MAC addr [5],
+static const esp_efuse_desc_t MAC[] = {
+    {EFUSE_BLK1, 40, 8}, 	 // [MAC_FACTORY] MAC address,
+    {EFUSE_BLK1, 32, 8}, 	 // [MAC_FACTORY] MAC address,
+    {EFUSE_BLK1, 24, 8}, 	 // [MAC_FACTORY] MAC address,
+    {EFUSE_BLK1, 16, 8}, 	 // [MAC_FACTORY] MAC address,
+    {EFUSE_BLK1, 8, 8}, 	 // [MAC_FACTORY] MAC address,
+    {EFUSE_BLK1, 0, 8}, 	 // [MAC_FACTORY] MAC address,
 };
 
 static const esp_efuse_desc_t MAC_EXT[] = {
-    {EFUSE_BLK1, 48, 8}, 	 // Extend  MAC addr [0],
-    {EFUSE_BLK1, 56, 8}, 	 // Extend  MAC addr [1],
+    {EFUSE_BLK1, 48, 8}, 	 // [] Stores the extended bits of MAC address [0],
+    {EFUSE_BLK1, 56, 8}, 	 // [] Stores the extended bits of MAC address [1],
 };
 
-static const esp_efuse_desc_t WAFER_VERSION_MINOR[] = {
-    {EFUSE_BLK1, 114, 3}, 	 // WAFER_VERSION_MINOR least significant bits,
-    {EFUSE_BLK1, 183, 1}, 	 // WAFER_VERSION_MINOR most significant bit,
-};
-
-static const esp_efuse_desc_t PKG_VERSION[] = {
-    {EFUSE_BLK1, 117, 3}, 	 // Package version 0:ESP32C3,
-};
-
-static const esp_efuse_desc_t BLK_VERSION_MINOR[] = {
-    {EFUSE_BLK1, 120, 3}, 	 // BLK_VERSION_MINOR,
-};
-
-static const esp_efuse_desc_t OPTIONAL_UNIQUE_ID[] = {
-    {EFUSE_BLK2, 0, 128}, 	 // Optional unique 128-bit ID,
-};
-
-static const esp_efuse_desc_t BLK_VERSION_MAJOR[] = {
-    {EFUSE_BLK2, 128, 2}, 	 // BLK_VERSION_MAJOR of BLOCK2,
-};
-
-static const esp_efuse_desc_t TEMP_CALIB[] = {
-    {EFUSE_BLK2, 131, 9}, 	 // Temperature calibration data,
-};
-
-static const esp_efuse_desc_t OCODE[] = {
-    {EFUSE_BLK2, 140, 8}, 	 // ADC OCode,
-};
-
-static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN0[] = {
-    {EFUSE_BLK2, 148, 10}, 	 // ADC1 init code at atten0,
-};
-
-static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN1[] = {
-    {EFUSE_BLK2, 158, 10}, 	 // ADC1 init code at atten1,
-};
-
-static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN2[] = {
-    {EFUSE_BLK2, 168, 10}, 	 // ADC1 init code at atten2,
-};
-
-static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN3[] = {
-    {EFUSE_BLK2, 178, 10}, 	 // ADC1 init code at atten3,
-};
-
-static const esp_efuse_desc_t ADC1_CAL_VOL_ATTEN0[] = {
-    {EFUSE_BLK2, 188, 10}, 	 // ADC1 calibration voltage at atten0,
-};
-
-static const esp_efuse_desc_t ADC1_CAL_VOL_ATTEN1[] = {
-    {EFUSE_BLK2, 198, 10}, 	 // ADC1 calibration voltage at atten1,
-};
-
-static const esp_efuse_desc_t ADC1_CAL_VOL_ATTEN2[] = {
-    {EFUSE_BLK2, 208, 10}, 	 // ADC1 calibration voltage at atten2,
-};
-
-static const esp_efuse_desc_t ADC1_CAL_VOL_ATTEN3[] = {
-    {EFUSE_BLK2, 218, 10}, 	 // ADC1 calibration voltage at atten3,
+static const esp_efuse_desc_t BLOCK_SYS_DATA1[] = {
+    {EFUSE_BLK2, 0, 256}, 	 // [SYS_DATA_PART1] System data part 1,
 };
 
 static const esp_efuse_desc_t USER_DATA[] = {
-    {EFUSE_BLK3, 0, 256}, 	 // User data,
+    {EFUSE_BLK3, 0, 256}, 	 // [BLOCK_USR_DATA] User data,
 };
 
 static const esp_efuse_desc_t USER_DATA_MAC_CUSTOM[] = {
-    {EFUSE_BLK3, 200, 48}, 	 // Custom MAC,
+    {EFUSE_BLK3, 200, 48}, 	 // [MAC_CUSTOM CUSTOM_MAC] Custom MAC (TODO,
 };
 
 static const esp_efuse_desc_t KEY0[] = {
-    {EFUSE_BLK4, 0, 256}, 	 // Key0 or user data,
+    {EFUSE_BLK4, 0, 256}, 	 // [BLOCK_KEY0] Key0 or user data,
 };
 
 static const esp_efuse_desc_t KEY1[] = {
-    {EFUSE_BLK5, 0, 256}, 	 // Key1 or user data,
+    {EFUSE_BLK5, 0, 256}, 	 // [BLOCK_KEY1] Key1 or user data,
 };
 
 static const esp_efuse_desc_t KEY2[] = {
-    {EFUSE_BLK6, 0, 256}, 	 // Key2 or user data,
+    {EFUSE_BLK6, 0, 256}, 	 // [BLOCK_KEY2] Key2 or user data,
 };
 
 static const esp_efuse_desc_t KEY3[] = {
-    {EFUSE_BLK7, 0, 256}, 	 // Key3 or user data,
+    {EFUSE_BLK7, 0, 256}, 	 // [BLOCK_KEY3] Key3 or user data,
 };
 
 static const esp_efuse_desc_t KEY4[] = {
-    {EFUSE_BLK8, 0, 256}, 	 // Key4 or user data,
+    {EFUSE_BLK8, 0, 256}, 	 // [BLOCK_KEY4] Key4 or user data,
 };
 
 static const esp_efuse_desc_t KEY5[] = {
-    {EFUSE_BLK9, 0, 256}, 	 // Key5 or user data,
+    {EFUSE_BLK9, 0, 256}, 	 // [BLOCK_KEY5] Key5 or user data,
 };
 
 static const esp_efuse_desc_t SYS_DATA_PART2[] = {
-    {EFUSE_BLK10, 0, 256}, 	 // System configuration,
-};
-
-static const esp_efuse_desc_t K_RTC_LDO[] = {
-    {EFUSE_BLK1, 135, 7}, 	 // BLOCK1 K_RTC_LDO,
-};
-
-static const esp_efuse_desc_t K_DIG_LDO[] = {
-    {EFUSE_BLK1, 142, 7}, 	 // BLOCK1 K_DIG_LDO,
-};
-
-static const esp_efuse_desc_t V_RTC_DBIAS20[] = {
-    {EFUSE_BLK1, 149, 8}, 	 // BLOCK1 voltage of rtc dbias20,
-};
-
-static const esp_efuse_desc_t V_DIG_DBIAS20[] = {
-    {EFUSE_BLK1, 157, 8}, 	 // BLOCK1 voltage of digital dbias20,
-};
-
-static const esp_efuse_desc_t DIG_DBIAS_HVT[] = {
-    {EFUSE_BLK1, 165, 5}, 	 // BLOCK1 digital dbias when hvt,
-};
-
-static const esp_efuse_desc_t THRES_HVT[] = {
-    {EFUSE_BLK1, 170, 10}, 	 // BLOCK1 pvt threshold when hvt,
+    {EFUSE_BLK10, 0, 256}, 	 // [BLOCK_SYS_DATA2] System data part 2 (reserved),
 };
 
 
@@ -567,683 +450,537 @@ static const esp_efuse_desc_t THRES_HVT[] = {
 
 
 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS[] = {
-    &WR_DIS[0],    		// Write protection
+    &WR_DIS[0],    		// [] Disable programming of individual eFuses
     NULL
 };
 
 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[] = {
-    &WR_DIS_RD_DIS[0],    		// Write protection for RD_DIS_KEY0 RD_DIS_KEY1 RD_DIS_KEY2 RD_DIS_KEY3 RD_DIS_KEY4 RD_DIS_KEY5 RD_DIS_SYS_DATA_PART2
-    NULL
-};
-
-const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_1[] = {
-    &WR_DIS_GROUP_1[0],    		// Write protection for KM_RND_SWITCH_CYCLE KM_DEPLOY_ONLY_ONCE FORCE_USE_KEY_MANAGER_KEY FORCE_DISABLE_SW_INIT_KEY
-    NULL
-};
-
-const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_2[] = {
-    &WR_DIS_GROUP_2[0],    		// Write protection for DIS_USB_JTAG POWERGLITCH_EN DIS_USB_DERIAL_JTAG DIS_FORCE_DOWNLOAD DIS_TWAI JTAG_SEL_ENABLE DIS_PAD_JTAG DIS_DOWNLOAD_MANUAL_ENCRYPT WDT_DELAY_SEL HYS_EN_PAD _0PXA_TIEH_SEL_0 _0PXA_TIEH_SEL_1 _0PXA_TIEH_SEL_2 _0PXA_TIEH_SEL_3 DIS_WDT DIS_SWD
-    NULL
-};
-
-const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_HP_PWR_SRC_SEL[] = {
-    &WR_DIS_HP_PWR_SRC_SEL[0],    		// Write protection for HP_PWR_SRC_SEL
+    &WR_DIS_RD_DIS[0],    		// [] wr_dis of RD_DIS
     NULL
 };
 
 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT[] = {
-    &WR_DIS_SPI_BOOT_CRYPT_CNT[0],    		// Write protection for SPI_BOOT_CRYPT_CNT
+    &WR_DIS_SPI_BOOT_CRYPT_CNT[0],    		// [] wr_dis of SPI_BOOT_CRYPT_CNT
     NULL
 };
 
 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE0[] = {
-    &WR_DIS_SECURE_BOOT_KEY_REVOKE0[0],    		// Write protection for SECURE_BOOT_KEY_REVOKE0
+    &WR_DIS_SECURE_BOOT_KEY_REVOKE0[0],    		// [] wr_dis of SECURE_BOOT_KEY_REVOKE0
     NULL
 };
 
 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE1[] = {
-    &WR_DIS_SECURE_BOOT_KEY_REVOKE1[0],    		// Write protection for SECURE_BOOT_KEY_REVOKE1
+    &WR_DIS_SECURE_BOOT_KEY_REVOKE1[0],    		// [] wr_dis of SECURE_BOOT_KEY_REVOKE1
     NULL
 };
 
 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE2[] = {
-    &WR_DIS_SECURE_BOOT_KEY_REVOKE2[0],    		// Write protection for SECURE_BOOT_KEY_REVOKE2
-    NULL
-};
-
-const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY0_PURPOSE[] = {
-    &WR_DIS_KEY0_PURPOSE[0],    		// Write protection for key_purpose. KEY0
+    &WR_DIS_SECURE_BOOT_KEY_REVOKE2[0],    		// [] wr_dis of SECURE_BOOT_KEY_REVOKE2
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY1_PURPOSE[] = {
-    &WR_DIS_KEY1_PURPOSE[0],    		// Write protection for key_purpose. KEY1
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_0[] = {
+    &WR_DIS_KEY_PURPOSE_0[0],    		// [WR_DIS.KEY0_PURPOSE] wr_dis of KEY_PURPOSE_0
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY2_PURPOSE[] = {
-    &WR_DIS_KEY2_PURPOSE[0],    		// Write protection for key_purpose. KEY2
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_1[] = {
+    &WR_DIS_KEY_PURPOSE_1[0],    		// [WR_DIS.KEY1_PURPOSE] wr_dis of KEY_PURPOSE_1
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY3_PURPOSE[] = {
-    &WR_DIS_KEY3_PURPOSE[0],    		// Write protection for key_purpose. KEY3
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_2[] = {
+    &WR_DIS_KEY_PURPOSE_2[0],    		// [WR_DIS.KEY2_PURPOSE] wr_dis of KEY_PURPOSE_2
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY4_PURPOSE[] = {
-    &WR_DIS_KEY4_PURPOSE[0],    		// Write protection for key_purpose. KEY4
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_3[] = {
+    &WR_DIS_KEY_PURPOSE_3[0],    		// [WR_DIS.KEY3_PURPOSE] wr_dis of KEY_PURPOSE_3
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY5_PURPOSE[] = {
-    &WR_DIS_KEY5_PURPOSE[0],    		// Write protection for key_purpose. KEY5
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_4[] = {
+    &WR_DIS_KEY_PURPOSE_4[0],    		// [WR_DIS.KEY4_PURPOSE] wr_dis of KEY_PURPOSE_4
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_3[] = {
-    &WR_DIS_GROUP_3[0],    		// Write protection for SEC_DPA_LEVEL CRYPT_DPA_ENABLE
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_5[] = {
+    &WR_DIS_KEY_PURPOSE_5[0],    		// [WR_DIS.KEY5_PURPOSE] wr_dis of KEY_PURPOSE_5
     NULL
 };
 
 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_EN[] = {
-    &WR_DIS_SECURE_BOOT_EN[0],    		// Write protection for SECURE_BOOT_EN
-    NULL
-};
-
-const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[] = {
-    &WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[0],    		// Write protection for SECURE_BOOT_AGGRESSIVE_REVOKE
-    NULL
-};
-
-const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ECDSA_FORCE_USE_HARDWARE_K[] = {
-    &WR_DIS_ECDSA_FORCE_USE_HARDWARE_K[0],    		// Write protection for ECDSA_FORCE_USE_HARDWARE_K
-    NULL
-};
-
-const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_4[] = {
-    &WR_DIS_GROUP_4[0],    		// Write protection for FLASH_TYPE FLASH_PAGE_SIZE FLASH_ECC_EN DIS_USB_OTG_DOWNLOAD_MODE FLASH_TPUW DIS_DOWNLOAD_MODE DIS_DIRECT_BOOT DIS_USB_SERIAL_JTAG_ROM_PRINT DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE ENABLE_SECURITY_DOWNLOAD UART_PRINT_CONTROL FORCE_SEND_RESUME SECURE_VERSION SECURE_BOOT_DISABLE_FAST_WAKE
-    NULL
-};
-
-const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_HUK_GEN_STATE[] = {
-    &WR_DIS_HUK_GEN_STATE[0],    		// Write protection for HUK_GEN_STATE
+    &WR_DIS_SECURE_BOOT_EN[0],    		// [] wr_dis of SECURE_BOOT_EN
     NULL
 };
 
 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK1[] = {
-    &WR_DIS_BLK1[0],    		// Write protection for EFUSE_BLK1.  MAC_SPI_8M_SYS
+    &WR_DIS_BLK1[0],    		// [] wr_dis of BLOCK1
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[] = {
-    &WR_DIS_SYS_DATA_PART1[0],    		// Write protection for EFUSE_BLK2.  SYS_DATA_PART1
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC[] = {
+    &WR_DIS_MAC[0],    		// [WR_DIS.MAC_FACTORY] wr_dis of MAC
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USER_DATA[] = {
-    &WR_DIS_USER_DATA[0],    		// Write protection for EFUSE_BLK3.  USER_DATA
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC_EXT[] = {
+    &WR_DIS_MAC_EXT[0],    		// [] wr_dis of MAC_EXT
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY0[] = {
-    &WR_DIS_KEY0[0],    		// Write protection for EFUSE_BLK4.  KEY0
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA1[] = {
+    &WR_DIS_BLOCK_SYS_DATA1[0],    		// [WR_DIS.SYS_DATA_PART1] wr_dis of BLOCK_SYS_DATA1
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY1[] = {
-    &WR_DIS_KEY1[0],    		// Write protection for EFUSE_BLK5.  KEY1
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_USR_DATA[] = {
+    &WR_DIS_BLOCK_USR_DATA[0],    		// [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY2[] = {
-    &WR_DIS_KEY2[0],    		// Write protection for EFUSE_BLK6.  KEY2
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY0[] = {
+    &WR_DIS_BLOCK_KEY0[0],    		// [WR_DIS.KEY0] wr_dis of BLOCK_KEY0
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY3[] = {
-    &WR_DIS_KEY3[0],    		// Write protection for EFUSE_BLK7.  KEY3
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY1[] = {
+    &WR_DIS_BLOCK_KEY1[0],    		// [WR_DIS.KEY1] wr_dis of BLOCK_KEY1
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY4[] = {
-    &WR_DIS_KEY4[0],    		// Write protection for EFUSE_BLK8.  KEY4
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY2[] = {
+    &WR_DIS_BLOCK_KEY2[0],    		// [WR_DIS.KEY2] wr_dis of BLOCK_KEY2
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY5[] = {
-    &WR_DIS_KEY5[0],    		// Write protection for EFUSE_BLK9.  KEY5
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY3[] = {
+    &WR_DIS_BLOCK_KEY3[0],    		// [WR_DIS.KEY3] wr_dis of BLOCK_KEY3
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART2[] = {
-    &WR_DIS_SYS_DATA_PART2[0],    		// Write protection for EFUSE_BLK10. SYS_DATA_PART2
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY4[] = {
+    &WR_DIS_BLOCK_KEY4[0],    		// [WR_DIS.KEY4] wr_dis of BLOCK_KEY4
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_5[] = {
-    &WR_DIS_GROUP_5[0],    		// Write protection for USB_DEVICE_EXCHG_PINS USB_OTG11_EXCHG_PINS USB_DEVICE_DREFH USB_OTG11_DREFH USB_PHY_SEL USB_DEVICE_DREFL USB_OTG11_DREFL
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY5[] = {
+    &WR_DIS_BLOCK_KEY5[0],    		// [WR_DIS.KEY5] wr_dis of BLOCK_KEY5
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SOFT_DIS_JTAG[] = {
-    &WR_DIS_SOFT_DIS_JTAG[0],    		// Write protection for SOFT_DIS_JTAG
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2[] = {
+    &WR_DIS_BLOCK_SYS_DATA2[0],    		// [WR_DIS.SYS_DATA_PART2] wr_dis of BLOCK_SYS_DATA2
     NULL
 };
 
 const esp_efuse_desc_t* ESP_EFUSE_RD_DIS[] = {
-    &RD_DIS[0],    		// Read protection
+    &RD_DIS[0],    		// [] Disable reading from BlOCK4-10
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY0[] = {
-    &RD_DIS_KEY0[0],    		// Read protection for EFUSE_BLK4.  KEY0
+const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY0[] = {
+    &RD_DIS_BLOCK_KEY0[0],    		// [RD_DIS.KEY0] rd_dis of BLOCK_KEY0
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY1[] = {
-    &RD_DIS_KEY1[0],    		// Read protection for EFUSE_BLK5.  KEY1
+const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY1[] = {
+    &RD_DIS_BLOCK_KEY1[0],    		// [RD_DIS.KEY1] rd_dis of BLOCK_KEY1
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY2[] = {
-    &RD_DIS_KEY2[0],    		// Read protection for EFUSE_BLK6.  KEY2
+const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY2[] = {
+    &RD_DIS_BLOCK_KEY2[0],    		// [RD_DIS.KEY2] rd_dis of BLOCK_KEY2
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY3[] = {
-    &RD_DIS_KEY3[0],    		// Read protection for EFUSE_BLK7.  KEY3
+const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY3[] = {
+    &RD_DIS_BLOCK_KEY3[0],    		// [RD_DIS.KEY3] rd_dis of BLOCK_KEY3
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY4[] = {
-    &RD_DIS_KEY4[0],    		// Read protection for EFUSE_BLK8.  KEY4
+const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY4[] = {
+    &RD_DIS_BLOCK_KEY4[0],    		// [RD_DIS.KEY4] rd_dis of BLOCK_KEY4
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY5[] = {
-    &RD_DIS_KEY5[0],    		// Read protection for EFUSE_BLK9.  KEY5
+const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY5[] = {
+    &RD_DIS_BLOCK_KEY5[0],    		// [RD_DIS.KEY5] rd_dis of BLOCK_KEY5
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_SYS_DATA_PART2[] = {
-    &RD_DIS_SYS_DATA_PART2[0],    		// Read protection for EFUSE_BLK10. SYS_DATA_PART2
+const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2[] = {
+    &RD_DIS_BLOCK_SYS_DATA2[0],    		// [RD_DIS.SYS_DATA_PART2] rd_dis of BLOCK_SYS_DATA2
     NULL
 };
 
 const esp_efuse_desc_t* ESP_EFUSE_USB_DEVICE_EXCHG_PINS[] = {
-    &USB_DEVICE_EXCHG_PINS[0],    		// USB-device exchange pins
+    &USB_DEVICE_EXCHG_PINS[0],    		// [] Enable usb device exchange pins of D+ and D-
     NULL
 };
 
 const esp_efuse_desc_t* ESP_EFUSE_USB_OTG11_EXCHG_PINS[] = {
-    &USB_OTG11_EXCHG_PINS[0],    		// USB-otg11 change pins
+    &USB_OTG11_EXCHG_PINS[0],    		// [] Enable usb otg11 exchange pins of D+ and D-
     NULL
 };
 
 const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_JTAG[] = {
-    &DIS_USB_JTAG[0],    		// Disable USB JTAG
+    &DIS_USB_JTAG[0],    		// [] Represents whether the function of usb switch to jtag is disabled or enabled. 1: disabled. 0: enabled
     NULL
 };
 
 const esp_efuse_desc_t* ESP_EFUSE_POWERGLITCH_EN[] = {
-    &POWERGLITCH_EN[0],    		// Power glitch enable
-    NULL
-};
-
-const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG[] = {
-    &DIS_USB_SERIAL_JTAG[0],    		// Disable USB_SERIAL_JTAG
+    &POWERGLITCH_EN[0],    		// [] Represents whether power glitch function is enabled. 1: enabled. 0: disabled
     NULL
 };
 
 const esp_efuse_desc_t* ESP_EFUSE_DIS_FORCE_DOWNLOAD[] = {
-    &DIS_FORCE_DOWNLOAD[0],    		// Disable force chip go to download mode function
+    &DIS_FORCE_DOWNLOAD[0],    		// [] Represents whether the function that forces chip into download mode is disabled or enabled. 1: disabled. 0: enabled
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_DIS_SPI_DOWNLOAD_MSPI[] = {
-    &DIS_SPI_DOWNLOAD_MSPI[0],    		// Represents whether the SPI0 controller is disabled in boot_mode_download
+const esp_efuse_desc_t* ESP_EFUSE_SPI_DOWNLOAD_MSPI_DIS[] = {
+    &SPI_DOWNLOAD_MSPI_DIS[0],    		// [] Set this bit to disable accessing MSPI flash/MSPI ram by SYS AXI matrix during boot_mode_download
     NULL
 };
 
 const esp_efuse_desc_t* ESP_EFUSE_DIS_TWAI[] = {
-    &DIS_TWAI[0],    		// Disable TWAI function
+    &DIS_TWAI[0],    		// [] Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled
     NULL
 };
 
 const esp_efuse_desc_t* ESP_EFUSE_JTAG_SEL_ENABLE[] = {
-    &JTAG_SEL_ENABLE[0],    		// Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0.
+    &JTAG_SEL_ENABLE[0],    		// [] Represents whether the selection between usb_to_jtag and pad_to_jtag through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled. 1: enabled. 0: disabled
     NULL
 };
 
 const esp_efuse_desc_t* ESP_EFUSE_SOFT_DIS_JTAG[] = {
-    &SOFT_DIS_JTAG[0],    		// Set these bits to soft disable JTAG (odd number 1 means disable). JTAG can be enabled in HMAC module.
+    &SOFT_DIS_JTAG[0],    		// [] Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number: enabled
     NULL
 };
 
 const esp_efuse_desc_t* ESP_EFUSE_DIS_PAD_JTAG[] = {
-    &DIS_PAD_JTAG[0],    		// Hard disable JTAG. JTAG is disabled permanently.
+    &DIS_PAD_JTAG[0],    		// [] Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: enabled
     NULL
 };
 
 const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT[] = {
-    &DIS_DOWNLOAD_MANUAL_ENCRYPT[0],    		// Disable flash encryption when in download boot modes.
+    &DIS_DOWNLOAD_MANUAL_ENCRYPT[0],    		// [] Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode). 1: disabled. 0: enabled
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_USB_DEVICE_DREFH[] = {
-    &USB_DEVICE_DREFH[0],    		// USB-device drefh
-    NULL
-};
-
-const esp_efuse_desc_t* ESP_EFUSE_USB_OTG11_DREFH[] = {
-    &USB_OTG11_DREFH[0],    		// USB-otg11 drefh
+const esp_efuse_desc_t* ESP_EFUSE_USB_PHY_SEL[] = {
+    &USB_PHY_SEL[0],    		// [] TBD
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_USB_PHY_SEL[] = {
-    &USB_PHY_SEL[0],    		// Select usb phy
+const esp_efuse_desc_t* ESP_EFUSE_KM_HUK_GEN_STATE_LOW[] = {
+    &KM_HUK_GEN_STATE_LOW[0],    		// [] Set this bit to control validation of HUK generate mode. Odd of 1 is invalid; even of 1 is valid
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_HUK_GEN_STATE[] = {
-    &HUK_GEN_STATE[0],    		// HUK generator state
+const esp_efuse_desc_t* ESP_EFUSE_KM_HUK_GEN_STATE_HIGH[] = {
+    &KM_HUK_GEN_STATE_HIGH[0],    		// [] Set this bit to control validation of HUK generate mode. Odd of 1 is invalid; even of 1 is valid
     NULL
 };
 
 const esp_efuse_desc_t* ESP_EFUSE_KM_RND_SWITCH_CYCLE[] = {
-    &KM_RND_SWITCH_CYCLE[0],    		// km random switch cycle
+    &KM_RND_SWITCH_CYCLE[0],    		// [] Set bits to control key manager random number switch cycle. 0: control by register. 1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles
     NULL
 };
 
 const esp_efuse_desc_t* ESP_EFUSE_KM_DEPLOY_ONLY_ONCE[] = {
-    &KM_DEPLOY_ONLY_ONCE[0],    		// km deploy only once
+    &KM_DEPLOY_ONLY_ONCE[0],    		// [] Set each bit to control whether corresponding key can only be deployed once. 1 is true; 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds
     NULL
 };
 
 const esp_efuse_desc_t* ESP_EFUSE_FORCE_USE_KEY_MANAGER_KEY[] = {
-    &FORCE_USE_KEY_MANAGER_KEY[0],    		// force use key manager key
+    &FORCE_USE_KEY_MANAGER_KEY[0],    		// [] Set each bit to control whether corresponding key must come from key manager.. 1 is true; 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds
     NULL
 };
 
 const esp_efuse_desc_t* ESP_EFUSE_FORCE_DISABLE_SW_INIT_KEY[] = {
-    &FORCE_DISABLE_SW_INIT_KEY[0],    		// force disable software init key
+    &FORCE_DISABLE_SW_INIT_KEY[0],    		// [] Set this bit to disable software written init key; and force use efuse_init_key
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_XTS_KEY_LENGTH_256[] = {
+    &XTS_KEY_LENGTH_256[0],    		// [] Set this bit to configure flash encryption use xts-128 key; else use xts-256 key
     NULL
 };
 
 const esp_efuse_desc_t* ESP_EFUSE_WDT_DELAY_SEL[] = {
-    &WDT_DELAY_SEL[0],    		// watchdog delay selection
+    &WDT_DELAY_SEL[0],    		// [] Represents whether RTC watchdog timeout threshold is selected at startup. 1: selected. 0: not selected
     NULL
 };
 
 const esp_efuse_desc_t* ESP_EFUSE_SPI_BOOT_CRYPT_CNT[] = {
-    &SPI_BOOT_CRYPT_CNT[0],    		// spi boot encryption counter
+    &SPI_BOOT_CRYPT_CNT[0],    		// [] Enables flash encryption when 1 or 3 bits are set and disables otherwise {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"}
     NULL
 };
 
 const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE0[] = {
-    &SECURE_BOOT_KEY_REVOKE0[0],    		// Enable revoke first secure boot key
+    &SECURE_BOOT_KEY_REVOKE0[0],    		// [] Revoke 1st secure boot key
     NULL
 };
 
 const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE1[] = {
-    &SECURE_BOOT_KEY_REVOKE1[0],    		// Enable revoke second secure boot key
+    &SECURE_BOOT_KEY_REVOKE1[0],    		// [] Revoke 2nd secure boot key
     NULL
 };
 
 const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE2[] = {
-    &SECURE_BOOT_KEY_REVOKE2[0],    		// Enable revoke third secure boot key
+    &SECURE_BOOT_KEY_REVOKE2[0],    		// [] Revoke 3rd secure boot key
     NULL
 };
 
 const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_0[] = {
-    &KEY_PURPOSE_0[0],    		// Key0 purpose
+    &KEY_PURPOSE_0[0],    		// [KEY0_PURPOSE] Represents the purpose of Key0
     NULL
 };
 
 const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_1[] = {
-    &KEY_PURPOSE_1[0],    		// Key1 purpose
+    &KEY_PURPOSE_1[0],    		// [KEY1_PURPOSE] Represents the purpose of Key1
     NULL
 };
 
 const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_2[] = {
-    &KEY_PURPOSE_2[0],    		// Key2 purpose
+    &KEY_PURPOSE_2[0],    		// [KEY2_PURPOSE] Represents the purpose of Key2
     NULL
 };
 
 const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_3[] = {
-    &KEY_PURPOSE_3[0],    		// Key3 purpose
+    &KEY_PURPOSE_3[0],    		// [KEY3_PURPOSE] Represents the purpose of Key3
     NULL
 };
 
 const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_4[] = {
-    &KEY_PURPOSE_4[0],    		// Key4 purpose
+    &KEY_PURPOSE_4[0],    		// [KEY4_PURPOSE] Represents the purpose of Key4
     NULL
 };
 
 const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_5[] = {
-    &KEY_PURPOSE_5[0],    		// Key5 purpose
+    &KEY_PURPOSE_5[0],    		// [KEY5_PURPOSE] Represents the purpose of Key5
     NULL
 };
 
 const esp_efuse_desc_t* ESP_EFUSE_SEC_DPA_LEVEL[] = {
-    &SEC_DPA_LEVEL[0],    		// Configures the clock random divide mode to determine the DPA security level
+    &SEC_DPA_LEVEL[0],    		// [] Represents the spa secure level by configuring the clock random divide mode
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_ECDSA_FORCE_USE_HARDWARE_K[] = {
-    &ECDSA_FORCE_USE_HARDWARE_K[0],    		// ecdsa force use hardware key
+const esp_efuse_desc_t* ESP_EFUSE_ECDSA_ENABLE_SOFT_K[] = {
+    &ECDSA_ENABLE_SOFT_K[0],    		// [] Represents whether hardware random number k is forced used in ESDCA. 1: force used. 0: not force used
     NULL
 };
 
 const esp_efuse_desc_t* ESP_EFUSE_CRYPT_DPA_ENABLE[] = {
-    &CRYPT_DPA_ENABLE[0],    		// Represents whether defense against DPA attack is enabled
+    &CRYPT_DPA_ENABLE[0],    		// [] Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled
     NULL
 };
 
 const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_EN[] = {
-    &SECURE_BOOT_EN[0],    		// Secure boot enable
+    &SECURE_BOOT_EN[0],    		// [] Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled
     NULL
 };
 
 const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE[] = {
-    &SECURE_BOOT_AGGRESSIVE_REVOKE[0],    		// Enable aggressive secure boot revoke
+    &SECURE_BOOT_AGGRESSIVE_REVOKE[0],    		// [] Represents whether revoking aggressive secure boot is enabled or disabled. 1: enabled. 0: disabled
     NULL
 };
 
 const esp_efuse_desc_t* ESP_EFUSE_FLASH_TYPE[] = {
-    &FLASH_TYPE[0],    		// flash type
+    &FLASH_TYPE[0],    		// [] The type of interfaced flash. 0: four data lines; 1: eight data lines
     NULL
 };
 
 const esp_efuse_desc_t* ESP_EFUSE_FLASH_PAGE_SIZE[] = {
-    &FLASH_PAGE_SIZE[0],    		// flash page size
+    &FLASH_PAGE_SIZE[0],    		// [] Set flash page size
     NULL
 };
 
 const esp_efuse_desc_t* ESP_EFUSE_FLASH_ECC_EN[] = {
-    &FLASH_ECC_EN[0],    		// flash ecc enable
+    &FLASH_ECC_EN[0],    		// [] Set this bit to enable ecc for flash boot
     NULL
 };
 
 const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_OTG_DOWNLOAD_MODE[] = {
-    &DIS_USB_OTG_DOWNLOAD_MODE[0],    		// disable use otg download mode
+    &DIS_USB_OTG_DOWNLOAD_MODE[0],    		// [] Set this bit to disable download via USB-OTG
     NULL
 };
 
 const esp_efuse_desc_t* ESP_EFUSE_FLASH_TPUW[] = {
-    &FLASH_TPUW[0],    		// flash tpuw
+    &FLASH_TPUW[0],    		// [] Represents the flash waiting time after power-up; in unit of ms. When the value less than 15; the waiting time is the programmed value. Otherwise; the waiting time is 2 times the programmed value
     NULL
 };
 
 const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MODE[] = {
-    &DIS_DOWNLOAD_MODE[0],    		// Disble download mode
+    &DIS_DOWNLOAD_MODE[0],    		// [] Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled
     NULL
 };
 
 const esp_efuse_desc_t* ESP_EFUSE_DIS_DIRECT_BOOT[] = {
-    &DIS_DIRECT_BOOT[0],    		// Disable direct boot mode
+    &DIS_DIRECT_BOOT[0],    		// [] Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled
     NULL
 };
 
 const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT[] = {
-    &DIS_USB_SERIAL_JTAG_ROM_PRINT[0],    		// Represents whether print from USB-Serial-JTAG during ROM boot is disabled
+    &DIS_USB_SERIAL_JTAG_ROM_PRINT[0],    		// [] Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_LOCK_KM_KEY[] = {
+    &LOCK_KM_KEY[0],    		// [] TBD
     NULL
 };
 
 const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[] = {
-    &DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[0],    		// Represents whether the USB-Serial-JTAG download func- tion is disabled
+    &DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[0],    		// [] Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: disabled. 0: enabled
     NULL
 };
 
 const esp_efuse_desc_t* ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD[] = {
-    &ENABLE_SECURITY_DOWNLOAD[0],    		// Enable secure download mode
+    &ENABLE_SECURITY_DOWNLOAD[0],    		// [] Represents whether security download is enabled or disabled. 1: enabled. 0: disabled
     NULL
 };
 
 const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CONTROL[] = {
-    &UART_PRINT_CONTROL[0],    		// b00:force print. b01:control by GPIO8 - low level print. b10:control by GPIO8 - high level print. b11:force disable print.
+    &UART_PRINT_CONTROL[0],    		// [] Represents the type of UART printing. 00: force enable printing. 01: enable printing when GPIO8 is reset at low level. 10: enable printing when GPIO8 is reset at high level. 11: force disable printing
     NULL
 };
 
 const esp_efuse_desc_t* ESP_EFUSE_FORCE_SEND_RESUME[] = {
-    &FORCE_SEND_RESUME[0],    		// Force ROM code to send a resume command during SPI boot
+    &FORCE_SEND_RESUME[0],    		// [] Represents whether ROM code is forced to send a resume command during SPI boot. 1: forced. 0:not forced
     NULL
 };
 
 const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[] = {
-    &SECURE_VERSION[0],    		// Secure version for anti-rollback
+    &SECURE_VERSION[0],    		// [] Represents the version used by ESP-IDF anti-rollback feature
     NULL
 };
 
 const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE[] = {
-    &SECURE_BOOT_DISABLE_FAST_WAKE[0],    		// Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled
+    &SECURE_BOOT_DISABLE_FAST_WAKE[0],    		// [] Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled. 1: disabled. 0: enabled
     NULL
 };
 
 const esp_efuse_desc_t* ESP_EFUSE_HYS_EN_PAD[] = {
-    &HYS_EN_PAD[0],    		// Hys en pad
+    &HYS_EN_PAD[0],    		// [] Represents whether the hysteresis function of corresponding PAD is enabled. 1: enabled. 0:disabled
     NULL
 };
 
 const esp_efuse_desc_t* ESP_EFUSE_DCDC_VSET[] = {
-    &DCDC_VSET[0],    		// dcdc vset
+    &DCDC_VSET[0],    		// [] Set the dcdc voltage default
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE__0PXA_TIEH_SEL_0[] = {
-    &_0PXA_TIEH_SEL_0[0],    		// 0pxa tieh sel0
+const esp_efuse_desc_t* ESP_EFUSE_PXA0_TIEH_SEL_0[] = {
+    &PXA0_TIEH_SEL_0[0],    		// [] TBD
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE__0PXA_TIEH_SEL_1[] = {
-    &_0PXA_TIEH_SEL_1[0],    		// 0pxa tieh sel1
+const esp_efuse_desc_t* ESP_EFUSE_PXA0_TIEH_SEL_1[] = {
+    &PXA0_TIEH_SEL_1[0],    		// [] TBD
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE__0PXA_TIEH_SEL_2[] = {
-    &_0PXA_TIEH_SEL_2[0],    		// 0pxa tieh sel2
+const esp_efuse_desc_t* ESP_EFUSE_PXA0_TIEH_SEL_2[] = {
+    &PXA0_TIEH_SEL_2[0],    		// [] TBD
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE__0PXA_TIEH_SEL_3[] = {
-    &_0PXA_TIEH_SEL_3[0],    		// 0pxa tieh sel3
+const esp_efuse_desc_t* ESP_EFUSE_PXA0_TIEH_SEL_3[] = {
+    &PXA0_TIEH_SEL_3[0],    		// [] TBD
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_USB_DEVICE_DREFL[] = {
-    &USB_DEVICE_DREFL[0],    		// usb device drefl
-    NULL
-};
-
-const esp_efuse_desc_t* ESP_EFUSE_USB_OTG11_DREFL[] = {
-    &USB_OTG11_DREFL[0],    		// usb otg1.1 drefl
+const esp_efuse_desc_t* ESP_EFUSE_KM_DISABLE_DEPLOY_MODE[] = {
+    &KM_DISABLE_DEPLOY_MODE[0],    		// [] TBD
     NULL
 };
 
 const esp_efuse_desc_t* ESP_EFUSE_HP_PWR_SRC_SEL[] = {
-    &HP_PWR_SRC_SEL[0],    		// hp power source selection
+    &HP_PWR_SRC_SEL[0],    		// [] HP system power source select. 0:LDO. 1: DCDC
     NULL
 };
 
 const esp_efuse_desc_t* ESP_EFUSE_DCDC_VSET_EN[] = {
-    &DCDC_VSET_EN[0],    		// dcdc vset enable
+    &DCDC_VSET_EN[0],    		// [] Select dcdc vset use efuse_dcdc_vset
     NULL
 };
 
 const esp_efuse_desc_t* ESP_EFUSE_DIS_WDT[] = {
-    &DIS_WDT[0],    		// disable watchdog
+    &DIS_WDT[0],    		// [] Set this bit to disable watch dog
     NULL
 };
 
 const esp_efuse_desc_t* ESP_EFUSE_DIS_SWD[] = {
-    &DIS_SWD[0],    		// disable super watchdog
+    &DIS_SWD[0],    		// [] Set this bit to disable super-watchdog
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY[] = {
-    &MAC_FACTORY[0],    		// Factory MAC addr [0]
-    &MAC_FACTORY[1],    		// Factory MAC addr [1]
-    &MAC_FACTORY[2],    		// Factory MAC addr [2]
-    &MAC_FACTORY[3],    		// Factory MAC addr [3]
-    &MAC_FACTORY[4],    		// Factory MAC addr [4]
-    &MAC_FACTORY[5],    		// Factory MAC addr [5]
+const esp_efuse_desc_t* ESP_EFUSE_MAC[] = {
+    &MAC[0],    		// [MAC_FACTORY] MAC address
+    &MAC[1],    		// [MAC_FACTORY] MAC address
+    &MAC[2],    		// [MAC_FACTORY] MAC address
+    &MAC[3],    		// [MAC_FACTORY] MAC address
+    &MAC[4],    		// [MAC_FACTORY] MAC address
+    &MAC[5],    		// [MAC_FACTORY] MAC address
     NULL
 };
 
 const esp_efuse_desc_t* ESP_EFUSE_MAC_EXT[] = {
-    &MAC_EXT[0],    		// Extend  MAC addr [0]
-    &MAC_EXT[1],    		// Extend  MAC addr [1]
-    NULL
-};
-
-const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[] = {
-    &WAFER_VERSION_MINOR[0],    		// WAFER_VERSION_MINOR least significant bits
-    &WAFER_VERSION_MINOR[1],    		// WAFER_VERSION_MINOR most significant bit
-    NULL
-};
-
-const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[] = {
-    &PKG_VERSION[0],    		// Package version 0:ESP32C3
-    NULL
-};
-
-const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[] = {
-    &BLK_VERSION_MINOR[0],    		// BLK_VERSION_MINOR
-    NULL
-};
-
-const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[] = {
-    &OPTIONAL_UNIQUE_ID[0],    		// Optional unique 128-bit ID
-    NULL
-};
-
-const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[] = {
-    &BLK_VERSION_MAJOR[0],    		// BLK_VERSION_MAJOR of BLOCK2
-    NULL
-};
-
-const esp_efuse_desc_t* ESP_EFUSE_TEMP_CALIB[] = {
-    &TEMP_CALIB[0],    		// Temperature calibration data
+    &MAC_EXT[0],    		// [] Stores the extended bits of MAC address [0]
+    &MAC_EXT[1],    		// [] Stores the extended bits of MAC address [1]
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_OCODE[] = {
-    &OCODE[0],    		// ADC OCode
-    NULL
-};
-
-const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0[] = {
-    &ADC1_INIT_CODE_ATTEN0[0],    		// ADC1 init code at atten0
-    NULL
-};
-
-const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN1[] = {
-    &ADC1_INIT_CODE_ATTEN1[0],    		// ADC1 init code at atten1
-    NULL
-};
-
-const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN2[] = {
-    &ADC1_INIT_CODE_ATTEN2[0],    		// ADC1 init code at atten2
-    NULL
-};
-
-const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN3[] = {
-    &ADC1_INIT_CODE_ATTEN3[0],    		// ADC1 init code at atten3
-    NULL
-};
-
-const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN0[] = {
-    &ADC1_CAL_VOL_ATTEN0[0],    		// ADC1 calibration voltage at atten0
-    NULL
-};
-
-const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN1[] = {
-    &ADC1_CAL_VOL_ATTEN1[0],    		// ADC1 calibration voltage at atten1
-    NULL
-};
-
-const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN2[] = {
-    &ADC1_CAL_VOL_ATTEN2[0],    		// ADC1 calibration voltage at atten2
-    NULL
-};
-
-const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN3[] = {
-    &ADC1_CAL_VOL_ATTEN3[0],    		// ADC1 calibration voltage at atten3
+const esp_efuse_desc_t* ESP_EFUSE_BLOCK_SYS_DATA1[] = {
+    &BLOCK_SYS_DATA1[0],    		// [SYS_DATA_PART1] System data part 1
     NULL
 };
 
 const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[] = {
-    &USER_DATA[0],    		// User data
+    &USER_DATA[0],    		// [BLOCK_USR_DATA] User data
     NULL
 };
 
 const esp_efuse_desc_t* ESP_EFUSE_USER_DATA_MAC_CUSTOM[] = {
-    &USER_DATA_MAC_CUSTOM[0],    		// Custom MAC
+    &USER_DATA_MAC_CUSTOM[0],    		// [MAC_CUSTOM CUSTOM_MAC] Custom MAC (TODO
     NULL
 };
 
 const esp_efuse_desc_t* ESP_EFUSE_KEY0[] = {
-    &KEY0[0],    		// Key0 or user data
+    &KEY0[0],    		// [BLOCK_KEY0] Key0 or user data
     NULL
 };
 
 const esp_efuse_desc_t* ESP_EFUSE_KEY1[] = {
-    &KEY1[0],    		// Key1 or user data
+    &KEY1[0],    		// [BLOCK_KEY1] Key1 or user data
     NULL
 };
 
 const esp_efuse_desc_t* ESP_EFUSE_KEY2[] = {
-    &KEY2[0],    		// Key2 or user data
+    &KEY2[0],    		// [BLOCK_KEY2] Key2 or user data
     NULL
 };
 
 const esp_efuse_desc_t* ESP_EFUSE_KEY3[] = {
-    &KEY3[0],    		// Key3 or user data
+    &KEY3[0],    		// [BLOCK_KEY3] Key3 or user data
     NULL
 };
 
 const esp_efuse_desc_t* ESP_EFUSE_KEY4[] = {
-    &KEY4[0],    		// Key4 or user data
+    &KEY4[0],    		// [BLOCK_KEY4] Key4 or user data
     NULL
 };
 
 const esp_efuse_desc_t* ESP_EFUSE_KEY5[] = {
-    &KEY5[0],    		// Key5 or user data
+    &KEY5[0],    		// [BLOCK_KEY5] Key5 or user data
     NULL
 };
 
 const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART2[] = {
-    &SYS_DATA_PART2[0],    		// System configuration
-    NULL
-};
-
-const esp_efuse_desc_t* ESP_EFUSE_K_RTC_LDO[] = {
-    &K_RTC_LDO[0],    		// BLOCK1 K_RTC_LDO
-    NULL
-};
-
-const esp_efuse_desc_t* ESP_EFUSE_K_DIG_LDO[] = {
-    &K_DIG_LDO[0],    		// BLOCK1 K_DIG_LDO
-    NULL
-};
-
-const esp_efuse_desc_t* ESP_EFUSE_V_RTC_DBIAS20[] = {
-    &V_RTC_DBIAS20[0],    		// BLOCK1 voltage of rtc dbias20
-    NULL
-};
-
-const esp_efuse_desc_t* ESP_EFUSE_V_DIG_DBIAS20[] = {
-    &V_DIG_DBIAS20[0],    		// BLOCK1 voltage of digital dbias20
-    NULL
-};
-
-const esp_efuse_desc_t* ESP_EFUSE_DIG_DBIAS_HVT[] = {
-    &DIG_DBIAS_HVT[0],    		// BLOCK1 digital dbias when hvt
-    NULL
-};
-
-const esp_efuse_desc_t* ESP_EFUSE_THRES_HVT[] = {
-    &THRES_HVT[0],    		// BLOCK1 pvt threshold when hvt
+    &SYS_DATA_PART2[0],    		// [BLOCK_SYS_DATA2] System data part 2 (reserved)
     NULL
 };

components/efuse/esp32p4/esp_efuse_table.csv

@@ -1,187 +1,125 @@
+
 # field_name,       |    efuse_block, | bit_start, | bit_count, |comment #
-#                   |    (EFUSE_BLK0  | (0..255)   | (1..-)     |        #
-#                   |     EFUSE_BLK1  |            |MAX_BLK_LEN*|        #
-#                   |        ...      |            |            |        #
-#                   |     EFUSE_BLK10)|            |            |        #
+#                   |    (EFUSE_BLK0  | (0..255)   | (1-256)    |        #
+#                   |     EFUSE_BLK1  |            |            |        #
+#                   |        ...)     |            |            |        #
 ##########################################################################
-# *) The value MAX_BLK_LEN depends on CONFIG_EFUSE_MAX_BLK_LEN, will be replaced with "None" - 256. "3/4" - 192. "REPEAT" - 128.
 # !!!!!!!!!!! #
-# After editing this file, run the command manually "make efuse_common_table" or "idf.py efuse-common-table"
+# After editing this file, run the command manually "idf.py efuse-common-table"
 # this will generate new source files, next rebuild all the sources.
 # !!!!!!!!!!! #
 
-# EFUSE_RD_REPEAT_DATA BLOCK #
-##############################
-    # EFUSE_RD_WR_DIS_REG #
-        WR_DIS,                           EFUSE_BLK0,   0,    32,     Write protection
-            WR_DIS.RD_DIS,                EFUSE_BLK0,   0,    1,      Write protection for RD_DIS_KEY0 RD_DIS_KEY1 RD_DIS_KEY2 RD_DIS_KEY3 RD_DIS_KEY4 RD_DIS_KEY5 RD_DIS_SYS_DATA_PART2
-            WR_DIS.GROUP_1,               EFUSE_BLK0,   1,    1,      Write protection for KM_RND_SWITCH_CYCLE KM_DEPLOY_ONLY_ONCE FORCE_USE_KEY_MANAGER_KEY FORCE_DISABLE_SW_INIT_KEY
-            WR_DIS.GROUP_2,               EFUSE_BLK0,   2,    1,      Write protection for DIS_USB_JTAG POWERGLITCH_EN DIS_USB_DERIAL_JTAG DIS_FORCE_DOWNLOAD DIS_TWAI JTAG_SEL_ENABLE DIS_PAD_JTAG DIS_DOWNLOAD_MANUAL_ENCRYPT WDT_DELAY_SEL HYS_EN_PAD _0PXA_TIEH_SEL_0 _0PXA_TIEH_SEL_1 _0PXA_TIEH_SEL_2 _0PXA_TIEH_SEL_3 DIS_WDT DIS_SWD
-            WR_DIS.HP_PWR_SRC_SEL,        EFUSE_BLK0,   3,    1,      Write protection for HP_PWR_SRC_SEL
-            WR_DIS.SPI_BOOT_CRYPT_CNT,    EFUSE_BLK0,   4,    1,      Write protection for SPI_BOOT_CRYPT_CNT
-            WR_DIS.SECURE_BOOT_KEY_REVOKE0,EFUSE_BLK0,  5,    1,      Write protection for SECURE_BOOT_KEY_REVOKE0
-            WR_DIS.SECURE_BOOT_KEY_REVOKE1,EFUSE_BLK0,  6,    1,      Write protection for SECURE_BOOT_KEY_REVOKE1
-            WR_DIS.SECURE_BOOT_KEY_REVOKE2,EFUSE_BLK0,  7,    1,      Write protection for SECURE_BOOT_KEY_REVOKE2
-            WR_DIS.KEY0_PURPOSE,          EFUSE_BLK0,   8,    1,      Write protection for key_purpose. KEY0
-            WR_DIS.KEY1_PURPOSE,          EFUSE_BLK0,   9,    1,      Write protection for key_purpose. KEY1
-            WR_DIS.KEY2_PURPOSE,          EFUSE_BLK0,  10,    1,      Write protection for key_purpose. KEY2
-            WR_DIS.KEY3_PURPOSE,          EFUSE_BLK0,  11,    1,      Write protection for key_purpose. KEY3
-            WR_DIS.KEY4_PURPOSE,          EFUSE_BLK0,  12,    1,      Write protection for key_purpose. KEY4
-            WR_DIS.KEY5_PURPOSE,          EFUSE_BLK0,  13,    1,      Write protection for key_purpose. KEY5
-            WR_DIS.GROUP_3,               EFUSE_BLK0,  14,    1,      Write protection for SEC_DPA_LEVEL CRYPT_DPA_ENABLE
-            WR_DIS.SECURE_BOOT_EN,        EFUSE_BLK0,  15,    1,      Write protection for SECURE_BOOT_EN
-            WR_DIS.SECURE_BOOT_AGGRESSIVE_REVOKE,EFUSE_BLK0, 16, 1,   Write protection for SECURE_BOOT_AGGRESSIVE_REVOKE
-            WR_DIS.ECDSA_FORCE_USE_HARDWARE_K,EFUSE_BLK0, 17, 1,      Write protection for ECDSA_FORCE_USE_HARDWARE_K
-            WR_DIS.GROUP_4,               EFUSE_BLK0,  18,    1,      Write protection for FLASH_TYPE FLASH_PAGE_SIZE FLASH_ECC_EN DIS_USB_OTG_DOWNLOAD_MODE FLASH_TPUW DIS_DOWNLOAD_MODE DIS_DIRECT_BOOT DIS_USB_SERIAL_JTAG_ROM_PRINT DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE ENABLE_SECURITY_DOWNLOAD UART_PRINT_CONTROL FORCE_SEND_RESUME SECURE_VERSION SECURE_BOOT_DISABLE_FAST_WAKE
-            WR_DIS.HUK_GEN_STATE,         EFUSE_BLK0,  19,    1,      Write protection for HUK_GEN_STATE
-
-            WR_DIS.BLK1,                  EFUSE_BLK0,  20,    1,      Write protection for EFUSE_BLK1.  MAC_SPI_8M_SYS
-            WR_DIS.SYS_DATA_PART1,        EFUSE_BLK0,  21,    1,      Write protection for EFUSE_BLK2.  SYS_DATA_PART1
-            WR_DIS.USER_DATA,             EFUSE_BLK0,  22,    1,      Write protection for EFUSE_BLK3.  USER_DATA
-            WR_DIS.KEY0,                  EFUSE_BLK0,  23,    1,      Write protection for EFUSE_BLK4.  KEY0
-            WR_DIS.KEY1,                  EFUSE_BLK0,  24,    1,      Write protection for EFUSE_BLK5.  KEY1
-            WR_DIS.KEY2,                  EFUSE_BLK0,  25,    1,      Write protection for EFUSE_BLK6.  KEY2
-            WR_DIS.KEY3,                  EFUSE_BLK0,  26,    1,      Write protection for EFUSE_BLK7.  KEY3
-            WR_DIS.KEY4,                  EFUSE_BLK0,  27,    1,      Write protection for EFUSE_BLK8.  KEY4
-            WR_DIS.KEY5,                  EFUSE_BLK0,  28,    1,      Write protection for EFUSE_BLK9.  KEY5
-            WR_DIS.SYS_DATA_PART2,        EFUSE_BLK0,  29,    1,      Write protection for EFUSE_BLK10. SYS_DATA_PART2
-            WR_DIS.GROUP_5,               EFUSE_BLK0,  30,    1,      Write protection for USB_DEVICE_EXCHG_PINS USB_OTG11_EXCHG_PINS USB_DEVICE_DREFH USB_OTG11_DREFH USB_PHY_SEL USB_DEVICE_DREFL USB_OTG11_DREFL
-            WR_DIS.SOFT_DIS_JTAG,         EFUSE_BLK0,  31,    1,      Write protection for SOFT_DIS_JTAG
-
-    # EFUSE_RD_REPEAT_DATA0_REG #
-        RD_DIS,                           EFUSE_BLK0,   32,    7,     Read protection
-            RD_DIS.KEY0,                  EFUSE_BLK0,   32,    1,     Read protection for EFUSE_BLK4.  KEY0
-            RD_DIS.KEY1,                  EFUSE_BLK0,   33,    1,     Read protection for EFUSE_BLK5.  KEY1
-            RD_DIS.KEY2,                  EFUSE_BLK0,   34,    1,     Read protection for EFUSE_BLK6.  KEY2
-            RD_DIS.KEY3,                  EFUSE_BLK0,   35,    1,     Read protection for EFUSE_BLK7.  KEY3
-            RD_DIS.KEY4,                  EFUSE_BLK0,   36,    1,     Read protection for EFUSE_BLK8.  KEY4
-            RD_DIS.KEY5,                  EFUSE_BLK0,   37,    1,     Read protection for EFUSE_BLK9.  KEY5
-            RD_DIS.SYS_DATA_PART2,        EFUSE_BLK0,   38,    1,     Read protection for EFUSE_BLK10. SYS_DATA_PART2
-        USB_DEVICE_EXCHG_PINS,            EFUSE_BLK0,   39,    1,     USB-device exchange pins
-        USB_OTG11_EXCHG_PINS,             EFUSE_BLK0,   40,    1,     USB-otg11 change pins
-        DIS_USB_JTAG,                     EFUSE_BLK0,   41,    1,     Disable USB JTAG
-        POWERGLITCH_EN,                   EFUSE_BLK0,   42,    1,     Power glitch enable
-        DIS_USB_SERIAL_JTAG,              EFUSE_BLK0,   43,    1,     Disable USB_SERIAL_JTAG
-        DIS_FORCE_DOWNLOAD,               EFUSE_BLK0,   44,    1,     Disable force chip go to download mode function
-        DIS_SPI_DOWNLOAD_MSPI,            EFUSE_BLK0,   45,    1,     Represents whether the SPI0 controller is disabled in boot_mode_download
-        DIS_TWAI,                         EFUSE_BLK0,   46,    1,     Disable TWAI function
-        JTAG_SEL_ENABLE,                  EFUSE_BLK0,   47,    1,     Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0.
-        SOFT_DIS_JTAG,                    EFUSE_BLK0,   48,    3,     Set these bits to soft disable JTAG (odd number 1 means disable). JTAG can be enabled in HMAC module.
-        DIS_PAD_JTAG,                     EFUSE_BLK0,   51,    1,     Hard disable JTAG. JTAG is disabled permanently.
-        DIS_DOWNLOAD_MANUAL_ENCRYPT,      EFUSE_BLK0,   52,    1,     Disable flash encryption when in download boot modes.
-        USB_DEVICE_DREFH,                 EFUSE_BLK0,   53,    2,     USB-device drefh
-        USB_OTG11_DREFH,                  EFUSE_BLK0,   55,    2,     USB-otg11 drefh
-
-    # EFUSE_RD_REPEAT_DATA1_REG #
-        USB_PHY_SEL,                      EFUSE_BLK0,   57,    1,     Select usb phy
-        HUK_GEN_STATE,                    EFUSE_BLK0,   58,    9,     HUK generator state
-        KM_RND_SWITCH_CYCLE,              EFUSE_BLK0,   67,    2,     km random switch cycle
-        KM_DEPLOY_ONLY_ONCE,              EFUSE_BLK0,   69,    4,     km deploy only once
-        FORCE_USE_KEY_MANAGER_KEY,        EFUSE_BLK0,   73,    4,     force use key manager key
-        FORCE_DISABLE_SW_INIT_KEY,        EFUSE_BLK0,   77,    1,     force disable software init key
-        WDT_DELAY_SEL,                    EFUSE_BLK0,   80,    2,     watchdog delay selection
-        SPI_BOOT_CRYPT_CNT,               EFUSE_BLK0,   82,    3,     spi boot encryption counter
-        SECURE_BOOT_KEY_REVOKE0,          EFUSE_BLK0,   85,    1,     Enable revoke first secure boot key
-        SECURE_BOOT_KEY_REVOKE1,          EFUSE_BLK0,   86,    1,     Enable revoke second secure boot key
-        SECURE_BOOT_KEY_REVOKE2,          EFUSE_BLK0,   87,    1,     Enable revoke third secure boot key
-        KEY_PURPOSE_0,                    EFUSE_BLK0,   88,    4,     Key0 purpose
-        KEY_PURPOSE_1,                    EFUSE_BLK0,   92,    4,     Key1 purpose
-
-    # EFUSE_RD_REPEAT_DATA2_REG #
-        KEY_PURPOSE_2,                    EFUSE_BLK0,   96,    4,     Key2 purpose
-        KEY_PURPOSE_3,                    EFUSE_BLK0,  100,    4,     Key3 purpose
-        KEY_PURPOSE_4,                    EFUSE_BLK0,  104,    4,     Key4 purpose
-        KEY_PURPOSE_5,                    EFUSE_BLK0,  108,    4,     Key5 purpose
-        SEC_DPA_LEVEL,                    EFUSE_BLK0,  112,    2,     Configures the clock random divide mode to determine the DPA security level
-        ECDSA_FORCE_USE_HARDWARE_K,       EFUSE_BLK0,  114,    1,     ecdsa force use hardware key
-        CRYPT_DPA_ENABLE,                 EFUSE_BLK0,  115,    1,     Represents whether defense against DPA attack is enabled
-        SECURE_BOOT_EN,                   EFUSE_BLK0,  116,    1,     Secure boot enable
-        SECURE_BOOT_AGGRESSIVE_REVOKE,    EFUSE_BLK0,  117,    1,     Enable aggressive secure boot revoke
-        FLASH_TYPE,                       EFUSE_BLK0,  119,    1,     flash type
-
-    # EFUSE_RD_REPEAT_DATA3_REG #
-        FLASH_PAGE_SIZE,                  EFUSE_BLK0,  120,    2,     flash page size
-        FLASH_ECC_EN,                     EFUSE_BLK0,  122,    1,     flash ecc enable
-        DIS_USB_OTG_DOWNLOAD_MODE,        EFUSE_BLK0,  123,    1,     disable use otg download mode
-        FLASH_TPUW,                       EFUSE_BLK0,  124,    4,     flash tpuw
-        DIS_DOWNLOAD_MODE,                EFUSE_BLK0,  128,    1,     Disble download mode
-        DIS_DIRECT_BOOT,                  EFUSE_BLK0,  129,    1,     Disable direct boot mode
-        DIS_USB_SERIAL_JTAG_ROM_PRINT,    EFUSE_BLK0,  130,    1,     Represents whether print from USB-Serial-JTAG during ROM boot is disabled
-        DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE, EFUSE_BLK0, 132,    1,     Represents whether the USB-Serial-JTAG download func- tion is disabled
-        ENABLE_SECURITY_DOWNLOAD,         EFUSE_BLK0,  133,    1,     Enable secure download mode
-        UART_PRINT_CONTROL,               EFUSE_BLK0,  134,    2,     b00:force print. b01:control by GPIO8 - low level print. b10:control by GPIO8 - high level print. b11:force disable print.
-        FORCE_SEND_RESUME,                EFUSE_BLK0,  136,    1,     Force ROM code to send a resume command during SPI boot
-        SECURE_VERSION,                   EFUSE_BLK0,  137,   16,     Secure version for anti-rollback
-
-    # EFUSE_RD_REPEAT_DATA4_REG #
-        SECURE_BOOT_DISABLE_FAST_WAKE,    EFUSE_BLK0,  153,    1,     Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled
-        HYS_EN_PAD,                       EFUSE_BLK0,  154,    1,     Hys en pad
-        DCDC_VSET,                        EFUSE_BLK0,  155,    5,     dcdc vset
-        _0PXA_TIEH_SEL_0,                  EFUSE_BLK0,  160,    2,     0pxa tieh sel0
-        _0PXA_TIEH_SEL_1,                  EFUSE_BLK0,  162,    2,     0pxa tieh sel1
-        _0PXA_TIEH_SEL_2,                  EFUSE_BLK0,  164,    2,     0pxa tieh sel2
-        _0PXA_TIEH_SEL_3,                  EFUSE_BLK0,  166,    2,     0pxa tieh sel3
-        USB_DEVICE_DREFL,                 EFUSE_BLK0,  172,    2,     usb device drefl
-        USB_OTG11_DREFL,                  EFUSE_BLK0,  174,    2,     usb otg1.1 drefl
-        HP_PWR_SRC_SEL,                   EFUSE_BLK0,  178,    1,     hp power source selection
-        DCDC_VSET_EN,                     EFUSE_BLK0,  179,    1,     dcdc vset enable
-        DIS_WDT,                          EFUSE_BLK0,  180,    1,     disable watchdog
-        DIS_SWD,                          EFUSE_BLK0,  181,    1,     disable super watchdog
-
-# MAC_SYS_VERSION BLOCK #
-#######################
-        MAC_FACTORY,                          EFUSE_BLK1,   40,    8,     Factory MAC addr [0]
-        ,                                     EFUSE_BLK1,   32,    8,     Factory MAC addr [1]
-        ,                                     EFUSE_BLK1,   24,    8,     Factory MAC addr [2]
-        ,                                     EFUSE_BLK1,   16,    8,     Factory MAC addr [3]
-        ,                                     EFUSE_BLK1,    8,    8,     Factory MAC addr [4]
-        ,                                     EFUSE_BLK1,    0,    8,     Factory MAC addr [5]
-        MAC_EXT,                              EFUSE_BLK1,   48,    8,     Extend  MAC addr [0]
-        ,                                     EFUSE_BLK1,   56,    8,     Extend  MAC addr [1]
-        WAFER_VERSION_MINOR,                  EFUSE_BLK1,  114,    3,     WAFER_VERSION_MINOR least significant bits
-        ,                                     EFUSE_BLK1,  183,    1,     WAFER_VERSION_MINOR most significant bit
-        # WAFER_VERSION_MINOR most significant bit is from RD_MAC_SPI_SYS_5
-        PKG_VERSION,                          EFUSE_BLK1,  117,    3,     Package version 0:ESP32C3
-        BLK_VERSION_MINOR,                    EFUSE_BLK1,  120,    3,     BLK_VERSION_MINOR
-
-# SYS_DATA_PART1 BLOCK# - System configuration (TODO: IDF-6483) #
-#######################
-    # RD_SYS_PART1_DATA0 - rd_sys_part1_data3
-        OPTIONAL_UNIQUE_ID,                   EFUSE_BLK2,    0,  128,     Optional unique 128-bit ID
-
-    # RD_SYS_PART1_DATA4
-        BLK_VERSION_MAJOR,                    EFUSE_BLK2,  128,    2,     BLK_VERSION_MAJOR of BLOCK2
-        TEMP_CALIB,                           EFUSE_BLK2,  131,    9,     Temperature calibration data
-        OCODE,                                EFUSE_BLK2,  140,    8,     ADC OCode
-        ADC1_INIT_CODE_ATTEN0,                EFUSE_BLK2,  148,   10,     ADC1 init code at atten0
-        ADC1_INIT_CODE_ATTEN1,                EFUSE_BLK2,  158,   10,     ADC1 init code at atten1
-
-    # RD_SYS_PART1_DATA5
-        ADC1_INIT_CODE_ATTEN2,                EFUSE_BLK2,  168,   10,     ADC1 init code at atten2
-        ADC1_INIT_CODE_ATTEN3,                EFUSE_BLK2,  178,   10,     ADC1 init code at atten3
-        ADC1_CAL_VOL_ATTEN0,                  EFUSE_BLK2,  188,   10,     ADC1 calibration voltage at atten0
-        ADC1_CAL_VOL_ATTEN1,                  EFUSE_BLK2,  198,   10,     ADC1 calibration voltage at atten1
-        ADC1_CAL_VOL_ATTEN2,                  EFUSE_BLK2,  208,   10,     ADC1 calibration voltage at atten2
-        ADC1_CAL_VOL_ATTEN3,                  EFUSE_BLK2,  218,   10,     ADC1 calibration voltage at atten3
-
-################
-USER_DATA,                                EFUSE_BLK3,    0,  256,     User data
-USER_DATA.MAC_CUSTOM,                     EFUSE_BLK3,  200,   48,     Custom MAC
-
-################
-KEY0,                                     EFUSE_BLK4,    0,  256,     Key0 or user data
-KEY1,                                     EFUSE_BLK5,    0,  256,     Key1 or user data
-KEY2,                                     EFUSE_BLK6,    0,  256,     Key2 or user data
-KEY3,                                     EFUSE_BLK7,    0,  256,     Key3 or user data
-KEY4,                                     EFUSE_BLK8,    0,  256,     Key4 or user data
-KEY5,                                     EFUSE_BLK9,    0,  256,     Key5 or user data
-SYS_DATA_PART2,                           EFUSE_BLK10,   0,  256,     System configuration
+# This file was generated by regtools.py based on the efuses.yaml file with the version: 552d7a824581925566213ca4f4d488dc
 
-# AUTO CONFIG DIG&RTC DBIAS (TODO: IDF-6483)#
-################
-K_RTC_LDO,                              EFUSE_BLK1,    135,    7,      BLOCK1 K_RTC_LDO
-K_DIG_LDO,                              EFUSE_BLK1,    142,    7,      BLOCK1 K_DIG_LDO
-V_RTC_DBIAS20,                          EFUSE_BLK1,    149,    8,      BLOCK1 voltage of rtc dbias20
-V_DIG_DBIAS20,                          EFUSE_BLK1,    157,    8,      BLOCK1 voltage of digital dbias20
-DIG_DBIAS_HVT,                          EFUSE_BLK1,    165,    5,      BLOCK1 digital dbias when hvt
-THRES_HVT,                              EFUSE_BLK1,    170,    10,     BLOCK1 pvt threshold when hvt
+WR_DIS,                                          EFUSE_BLK0,   0,  32, [] Disable programming of individual eFuses
+WR_DIS.RD_DIS,                                   EFUSE_BLK0,   0,   1, [] wr_dis of RD_DIS
+WR_DIS.SPI_BOOT_CRYPT_CNT,                       EFUSE_BLK0,   4,   1, [] wr_dis of SPI_BOOT_CRYPT_CNT
+WR_DIS.SECURE_BOOT_KEY_REVOKE0,                  EFUSE_BLK0,   5,   1, [] wr_dis of SECURE_BOOT_KEY_REVOKE0
+WR_DIS.SECURE_BOOT_KEY_REVOKE1,                  EFUSE_BLK0,   6,   1, [] wr_dis of SECURE_BOOT_KEY_REVOKE1
+WR_DIS.SECURE_BOOT_KEY_REVOKE2,                  EFUSE_BLK0,   7,   1, [] wr_dis of SECURE_BOOT_KEY_REVOKE2
+WR_DIS.KEY_PURPOSE_0,                            EFUSE_BLK0,   8,   1, [WR_DIS.KEY0_PURPOSE] wr_dis of KEY_PURPOSE_0
+WR_DIS.KEY_PURPOSE_1,                            EFUSE_BLK0,   9,   1, [WR_DIS.KEY1_PURPOSE] wr_dis of KEY_PURPOSE_1
+WR_DIS.KEY_PURPOSE_2,                            EFUSE_BLK0,  10,   1, [WR_DIS.KEY2_PURPOSE] wr_dis of KEY_PURPOSE_2
+WR_DIS.KEY_PURPOSE_3,                            EFUSE_BLK0,  11,   1, [WR_DIS.KEY3_PURPOSE] wr_dis of KEY_PURPOSE_3
+WR_DIS.KEY_PURPOSE_4,                            EFUSE_BLK0,  12,   1, [WR_DIS.KEY4_PURPOSE] wr_dis of KEY_PURPOSE_4
+WR_DIS.KEY_PURPOSE_5,                            EFUSE_BLK0,  13,   1, [WR_DIS.KEY5_PURPOSE] wr_dis of KEY_PURPOSE_5
+WR_DIS.SECURE_BOOT_EN,                           EFUSE_BLK0,  15,   1, [] wr_dis of SECURE_BOOT_EN
+WR_DIS.BLK1,                                     EFUSE_BLK0,  20,   1, [] wr_dis of BLOCK1
+WR_DIS.MAC,                                      EFUSE_BLK0,  20,   1, [WR_DIS.MAC_FACTORY] wr_dis of MAC
+WR_DIS.MAC_EXT,                                  EFUSE_BLK0,  20,   1, [] wr_dis of MAC_EXT
+WR_DIS.BLOCK_SYS_DATA1,                          EFUSE_BLK0,  21,   1, [WR_DIS.SYS_DATA_PART1] wr_dis of BLOCK_SYS_DATA1
+WR_DIS.BLOCK_USR_DATA,                           EFUSE_BLK0,  22,   1, [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA
+WR_DIS.BLOCK_KEY0,                               EFUSE_BLK0,  23,   1, [WR_DIS.KEY0] wr_dis of BLOCK_KEY0
+WR_DIS.BLOCK_KEY1,                               EFUSE_BLK0,  24,   1, [WR_DIS.KEY1] wr_dis of BLOCK_KEY1
+WR_DIS.BLOCK_KEY2,                               EFUSE_BLK0,  25,   1, [WR_DIS.KEY2] wr_dis of BLOCK_KEY2
+WR_DIS.BLOCK_KEY3,                               EFUSE_BLK0,  26,   1, [WR_DIS.KEY3] wr_dis of BLOCK_KEY3
+WR_DIS.BLOCK_KEY4,                               EFUSE_BLK0,  27,   1, [WR_DIS.KEY4] wr_dis of BLOCK_KEY4
+WR_DIS.BLOCK_KEY5,                               EFUSE_BLK0,  28,   1, [WR_DIS.KEY5] wr_dis of BLOCK_KEY5
+WR_DIS.BLOCK_SYS_DATA2,                          EFUSE_BLK0,  29,   1, [WR_DIS.SYS_DATA_PART2] wr_dis of BLOCK_SYS_DATA2
+RD_DIS,                                          EFUSE_BLK0,  32,   7, [] Disable reading from BlOCK4-10
+RD_DIS.BLOCK_KEY0,                               EFUSE_BLK0,  32,   1, [RD_DIS.KEY0] rd_dis of BLOCK_KEY0
+RD_DIS.BLOCK_KEY1,                               EFUSE_BLK0,  33,   1, [RD_DIS.KEY1] rd_dis of BLOCK_KEY1
+RD_DIS.BLOCK_KEY2,                               EFUSE_BLK0,  34,   1, [RD_DIS.KEY2] rd_dis of BLOCK_KEY2
+RD_DIS.BLOCK_KEY3,                               EFUSE_BLK0,  35,   1, [RD_DIS.KEY3] rd_dis of BLOCK_KEY3
+RD_DIS.BLOCK_KEY4,                               EFUSE_BLK0,  36,   1, [RD_DIS.KEY4] rd_dis of BLOCK_KEY4
+RD_DIS.BLOCK_KEY5,                               EFUSE_BLK0,  37,   1, [RD_DIS.KEY5] rd_dis of BLOCK_KEY5
+RD_DIS.BLOCK_SYS_DATA2,                          EFUSE_BLK0,  38,   1, [RD_DIS.SYS_DATA_PART2] rd_dis of BLOCK_SYS_DATA2
+USB_DEVICE_EXCHG_PINS,                           EFUSE_BLK0,  39,   1, [] Enable usb device exchange pins of D+ and D-
+USB_OTG11_EXCHG_PINS,                            EFUSE_BLK0,  40,   1, [] Enable usb otg11 exchange pins of D+ and D-
+DIS_USB_JTAG,                                    EFUSE_BLK0,  41,   1, [] Represents whether the function of usb switch to jtag is disabled or enabled. 1: disabled. 0: enabled
+POWERGLITCH_EN,                                  EFUSE_BLK0,  42,   1, [] Represents whether power glitch function is enabled. 1: enabled. 0: disabled
+DIS_FORCE_DOWNLOAD,                              EFUSE_BLK0,  44,   1, [] Represents whether the function that forces chip into download mode is disabled or enabled. 1: disabled. 0: enabled
+SPI_DOWNLOAD_MSPI_DIS,                           EFUSE_BLK0,  45,   1, [] Set this bit to disable accessing MSPI flash/MSPI ram by SYS AXI matrix during boot_mode_download
+DIS_TWAI,                                        EFUSE_BLK0,  46,   1, [] Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled
+JTAG_SEL_ENABLE,                                 EFUSE_BLK0,  47,   1, [] Represents whether the selection between usb_to_jtag and pad_to_jtag through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled. 1: enabled. 0: disabled
+SOFT_DIS_JTAG,                                   EFUSE_BLK0,  48,   3, [] Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number: enabled
+DIS_PAD_JTAG,                                    EFUSE_BLK0,  51,   1, [] Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: enabled
+DIS_DOWNLOAD_MANUAL_ENCRYPT,                     EFUSE_BLK0,  52,   1, [] Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode). 1: disabled. 0: enabled
+USB_PHY_SEL,                                     EFUSE_BLK0,  57,   1, [] TBD
+KM_HUK_GEN_STATE_LOW,                            EFUSE_BLK0,  58,   6, [] Set this bit to control validation of HUK generate mode. Odd of 1 is invalid; even of 1 is valid
+KM_HUK_GEN_STATE_HIGH,                           EFUSE_BLK0,  64,   3, [] Set this bit to control validation of HUK generate mode. Odd of 1 is invalid; even of 1 is valid
+KM_RND_SWITCH_CYCLE,                             EFUSE_BLK0,  67,   2, [] Set bits to control key manager random number switch cycle. 0: control by register. 1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles
+KM_DEPLOY_ONLY_ONCE,                             EFUSE_BLK0,  69,   4, [] Set each bit to control whether corresponding key can only be deployed once. 1 is true; 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds
+FORCE_USE_KEY_MANAGER_KEY,                       EFUSE_BLK0,  73,   4, [] Set each bit to control whether corresponding key must come from key manager.. 1 is true; 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds
+FORCE_DISABLE_SW_INIT_KEY,                       EFUSE_BLK0,  77,   1, [] Set this bit to disable software written init key; and force use efuse_init_key
+XTS_KEY_LENGTH_256,                              EFUSE_BLK0,  78,   1, [] Set this bit to configure flash encryption use xts-128 key; else use xts-256 key
+WDT_DELAY_SEL,                                   EFUSE_BLK0,  80,   2, [] Represents whether RTC watchdog timeout threshold is selected at startup. 1: selected. 0: not selected
+SPI_BOOT_CRYPT_CNT,                              EFUSE_BLK0,  82,   3, [] Enables flash encryption when 1 or 3 bits are set and disables otherwise {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"}
+SECURE_BOOT_KEY_REVOKE0,                         EFUSE_BLK0,  85,   1, [] Revoke 1st secure boot key
+SECURE_BOOT_KEY_REVOKE1,                         EFUSE_BLK0,  86,   1, [] Revoke 2nd secure boot key
+SECURE_BOOT_KEY_REVOKE2,                         EFUSE_BLK0,  87,   1, [] Revoke 3rd secure boot key
+KEY_PURPOSE_0,                                   EFUSE_BLK0,  88,   4, [KEY0_PURPOSE] Represents the purpose of Key0
+KEY_PURPOSE_1,                                   EFUSE_BLK0,  92,   4, [KEY1_PURPOSE] Represents the purpose of Key1
+KEY_PURPOSE_2,                                   EFUSE_BLK0,  96,   4, [KEY2_PURPOSE] Represents the purpose of Key2
+KEY_PURPOSE_3,                                   EFUSE_BLK0, 100,   4, [KEY3_PURPOSE] Represents the purpose of Key3
+KEY_PURPOSE_4,                                   EFUSE_BLK0, 104,   4, [KEY4_PURPOSE] Represents the purpose of Key4
+KEY_PURPOSE_5,                                   EFUSE_BLK0, 108,   4, [KEY5_PURPOSE] Represents the purpose of Key5
+SEC_DPA_LEVEL,                                   EFUSE_BLK0, 112,   2, [] Represents the spa secure level by configuring the clock random divide mode
+ECDSA_ENABLE_SOFT_K,                             EFUSE_BLK0, 114,   1, [] Represents whether hardware random number k is forced used in ESDCA. 1: force used. 0: not force used
+CRYPT_DPA_ENABLE,                                EFUSE_BLK0, 115,   1, [] Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled
+SECURE_BOOT_EN,                                  EFUSE_BLK0, 116,   1, [] Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled
+SECURE_BOOT_AGGRESSIVE_REVOKE,                   EFUSE_BLK0, 117,   1, [] Represents whether revoking aggressive secure boot is enabled or disabled. 1: enabled. 0: disabled
+FLASH_TYPE,                                      EFUSE_BLK0, 119,   1, [] The type of interfaced flash. 0: four data lines; 1: eight data lines
+FLASH_PAGE_SIZE,                                 EFUSE_BLK0, 120,   2, [] Set flash page size
+FLASH_ECC_EN,                                    EFUSE_BLK0, 122,   1, [] Set this bit to enable ecc for flash boot
+DIS_USB_OTG_DOWNLOAD_MODE,                       EFUSE_BLK0, 123,   1, [] Set this bit to disable download via USB-OTG
+FLASH_TPUW,                                      EFUSE_BLK0, 124,   4, [] Represents the flash waiting time after power-up; in unit of ms. When the value less than 15; the waiting time is the programmed value. Otherwise; the waiting time is 2 times the programmed value
+DIS_DOWNLOAD_MODE,                               EFUSE_BLK0, 128,   1, [] Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled
+DIS_DIRECT_BOOT,                                 EFUSE_BLK0, 129,   1, [] Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled
+DIS_USB_SERIAL_JTAG_ROM_PRINT,                   EFUSE_BLK0, 130,   1, [] Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled
+LOCK_KM_KEY,                                     EFUSE_BLK0, 131,   1, [] TBD
+DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE,               EFUSE_BLK0, 132,   1, [] Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: disabled. 0: enabled
+ENABLE_SECURITY_DOWNLOAD,                        EFUSE_BLK0, 133,   1, [] Represents whether security download is enabled or disabled. 1: enabled. 0: disabled
+UART_PRINT_CONTROL,                              EFUSE_BLK0, 134,   2, [] Represents the type of UART printing. 00: force enable printing. 01: enable printing when GPIO8 is reset at low level. 10: enable printing when GPIO8 is reset at high level. 11: force disable printing
+FORCE_SEND_RESUME,                               EFUSE_BLK0, 136,   1, [] Represents whether ROM code is forced to send a resume command during SPI boot. 1: forced. 0:not forced
+SECURE_VERSION,                                  EFUSE_BLK0, 137,  16, [] Represents the version used by ESP-IDF anti-rollback feature
+SECURE_BOOT_DISABLE_FAST_WAKE,                   EFUSE_BLK0, 153,   1, [] Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled. 1: disabled. 0: enabled
+HYS_EN_PAD,                                      EFUSE_BLK0, 154,   1, [] Represents whether the hysteresis function of corresponding PAD is enabled. 1: enabled. 0:disabled
+DCDC_VSET,                                       EFUSE_BLK0, 155,   5, [] Set the dcdc voltage default
+PXA0_TIEH_SEL_0,                                 EFUSE_BLK0, 160,   2, [] TBD
+PXA0_TIEH_SEL_1,                                 EFUSE_BLK0, 162,   2, [] TBD
+PXA0_TIEH_SEL_2,                                 EFUSE_BLK0, 164,   2, [] TBD
+PXA0_TIEH_SEL_3,                                 EFUSE_BLK0, 166,   2, [] TBD
+KM_DISABLE_DEPLOY_MODE,                          EFUSE_BLK0, 168,   4, [] TBD
+HP_PWR_SRC_SEL,                                  EFUSE_BLK0, 178,   1, [] HP system power source select. 0:LDO. 1: DCDC
+DCDC_VSET_EN,                                    EFUSE_BLK0, 179,   1, [] Select dcdc vset use efuse_dcdc_vset
+DIS_WDT,                                         EFUSE_BLK0, 180,   1, [] Set this bit to disable watch dog
+DIS_SWD,                                         EFUSE_BLK0, 181,   1, [] Set this bit to disable super-watchdog
+MAC,                                             EFUSE_BLK1,  40,   8, [MAC_FACTORY] MAC address
+,                                                EFUSE_BLK1,  32,   8, [MAC_FACTORY] MAC address
+,                                                EFUSE_BLK1,  24,   8, [MAC_FACTORY] MAC address
+,                                                EFUSE_BLK1,  16,   8, [MAC_FACTORY] MAC address
+,                                                EFUSE_BLK1,   8,   8, [MAC_FACTORY] MAC address
+,                                                EFUSE_BLK1,   0,   8, [MAC_FACTORY] MAC address
+MAC_EXT,                                         EFUSE_BLK1,  48,   8, [] Stores the extended bits of MAC address [0]
+,                                                EFUSE_BLK1,  56,   8, [] Stores the extended bits of MAC address [1]
+BLOCK_SYS_DATA1,                                 EFUSE_BLK2,   0, 256, [SYS_DATA_PART1] System data part 1
+USER_DATA,                                       EFUSE_BLK3,   0, 256, [BLOCK_USR_DATA] User data
+USER_DATA.MAC_CUSTOM,                            EFUSE_BLK3, 200,  48, [MAC_CUSTOM CUSTOM_MAC] Custom MAC (TODO, not defined yet)
+KEY0,                                            EFUSE_BLK4,   0, 256, [BLOCK_KEY0] Key0 or user data
+KEY1,                                            EFUSE_BLK5,   0, 256, [BLOCK_KEY1] Key1 or user data
+KEY2,                                            EFUSE_BLK6,   0, 256, [BLOCK_KEY2] Key2 or user data
+KEY3,                                            EFUSE_BLK7,   0, 256, [BLOCK_KEY3] Key3 or user data
+KEY4,                                            EFUSE_BLK8,   0, 256, [BLOCK_KEY4] Key4 or user data
+KEY5,                                            EFUSE_BLK9,   0, 256, [BLOCK_KEY5] Key5 or user data
+SYS_DATA_PART2,                                  EFUSE_BLK10,   0, 256, [BLOCK_SYS_DATA2] System data part 2 (reserved)

components/efuse/esp32p4/include/esp_efuse_table.h

@@ -10,7 +10,7 @@ extern "C" {
 
 #include "esp_efuse.h"
 
-// md5_digest_table 57d7fbd8410e3a4d1e0d19e39b9cb3c0
+// md5_digest_table 78dff63df528392f0f37f4880b83c6db
 // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
 // If you want to change some fields, you need to change esp_efuse_table.csv file
 // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
@@ -19,78 +19,98 @@ extern "C" {
 
 extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS[];
 extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_1[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_2[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_HP_PWR_SRC_SEL[];
 extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT[];
 extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE0[];
 extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE1[];
 extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE2[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY0_PURPOSE[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY1_PURPOSE[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY2_PURPOSE[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY3_PURPOSE[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY4_PURPOSE[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY5_PURPOSE[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_3[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_0[];
+#define ESP_EFUSE_WR_DIS_KEY0_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_0
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_1[];
+#define ESP_EFUSE_WR_DIS_KEY1_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_1
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_2[];
+#define ESP_EFUSE_WR_DIS_KEY2_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_2
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_3[];
+#define ESP_EFUSE_WR_DIS_KEY3_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_3
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_4[];
+#define ESP_EFUSE_WR_DIS_KEY4_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_4
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_5[];
+#define ESP_EFUSE_WR_DIS_KEY5_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_5
 extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_EN[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ECDSA_FORCE_USE_HARDWARE_K[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_4[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_HUK_GEN_STATE[];
 extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK1[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USER_DATA[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY0[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY1[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY2[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY3[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY4[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY5[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART2[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_5[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SOFT_DIS_JTAG[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC[];
+#define ESP_EFUSE_WR_DIS_MAC_FACTORY ESP_EFUSE_WR_DIS_MAC
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC_EXT[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA1[];
+#define ESP_EFUSE_WR_DIS_SYS_DATA_PART1 ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA1
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_USR_DATA[];
+#define ESP_EFUSE_WR_DIS_USER_DATA ESP_EFUSE_WR_DIS_BLOCK_USR_DATA
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY0[];
+#define ESP_EFUSE_WR_DIS_KEY0 ESP_EFUSE_WR_DIS_BLOCK_KEY0
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY1[];
+#define ESP_EFUSE_WR_DIS_KEY1 ESP_EFUSE_WR_DIS_BLOCK_KEY1
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY2[];
+#define ESP_EFUSE_WR_DIS_KEY2 ESP_EFUSE_WR_DIS_BLOCK_KEY2
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY3[];
+#define ESP_EFUSE_WR_DIS_KEY3 ESP_EFUSE_WR_DIS_BLOCK_KEY3
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY4[];
+#define ESP_EFUSE_WR_DIS_KEY4 ESP_EFUSE_WR_DIS_BLOCK_KEY4
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY5[];
+#define ESP_EFUSE_WR_DIS_KEY5 ESP_EFUSE_WR_DIS_BLOCK_KEY5
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2[];
+#define ESP_EFUSE_WR_DIS_SYS_DATA_PART2 ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2
 extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS[];
-extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY0[];
-extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY1[];
-extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY2[];
-extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY3[];
-extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY4[];
-extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY5[];
-extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_SYS_DATA_PART2[];
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY0[];
+#define ESP_EFUSE_RD_DIS_KEY0 ESP_EFUSE_RD_DIS_BLOCK_KEY0
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY1[];
+#define ESP_EFUSE_RD_DIS_KEY1 ESP_EFUSE_RD_DIS_BLOCK_KEY1
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY2[];
+#define ESP_EFUSE_RD_DIS_KEY2 ESP_EFUSE_RD_DIS_BLOCK_KEY2
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY3[];
+#define ESP_EFUSE_RD_DIS_KEY3 ESP_EFUSE_RD_DIS_BLOCK_KEY3
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY4[];
+#define ESP_EFUSE_RD_DIS_KEY4 ESP_EFUSE_RD_DIS_BLOCK_KEY4
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY5[];
+#define ESP_EFUSE_RD_DIS_KEY5 ESP_EFUSE_RD_DIS_BLOCK_KEY5
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2[];
+#define ESP_EFUSE_RD_DIS_SYS_DATA_PART2 ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2
 extern const esp_efuse_desc_t* ESP_EFUSE_USB_DEVICE_EXCHG_PINS[];
 extern const esp_efuse_desc_t* ESP_EFUSE_USB_OTG11_EXCHG_PINS[];
 extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_JTAG[];
 extern const esp_efuse_desc_t* ESP_EFUSE_POWERGLITCH_EN[];
-extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG[];
 extern const esp_efuse_desc_t* ESP_EFUSE_DIS_FORCE_DOWNLOAD[];
-extern const esp_efuse_desc_t* ESP_EFUSE_DIS_SPI_DOWNLOAD_MSPI[];
+extern const esp_efuse_desc_t* ESP_EFUSE_SPI_DOWNLOAD_MSPI_DIS[];
 extern const esp_efuse_desc_t* ESP_EFUSE_DIS_TWAI[];
 extern const esp_efuse_desc_t* ESP_EFUSE_JTAG_SEL_ENABLE[];
 extern const esp_efuse_desc_t* ESP_EFUSE_SOFT_DIS_JTAG[];
 extern const esp_efuse_desc_t* ESP_EFUSE_DIS_PAD_JTAG[];
 extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT[];
-extern const esp_efuse_desc_t* ESP_EFUSE_USB_DEVICE_DREFH[];
-extern const esp_efuse_desc_t* ESP_EFUSE_USB_OTG11_DREFH[];
 extern const esp_efuse_desc_t* ESP_EFUSE_USB_PHY_SEL[];
-extern const esp_efuse_desc_t* ESP_EFUSE_HUK_GEN_STATE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_KM_HUK_GEN_STATE_LOW[];
+extern const esp_efuse_desc_t* ESP_EFUSE_KM_HUK_GEN_STATE_HIGH[];
 extern const esp_efuse_desc_t* ESP_EFUSE_KM_RND_SWITCH_CYCLE[];
 extern const esp_efuse_desc_t* ESP_EFUSE_KM_DEPLOY_ONLY_ONCE[];
 extern const esp_efuse_desc_t* ESP_EFUSE_FORCE_USE_KEY_MANAGER_KEY[];
 extern const esp_efuse_desc_t* ESP_EFUSE_FORCE_DISABLE_SW_INIT_KEY[];
+extern const esp_efuse_desc_t* ESP_EFUSE_XTS_KEY_LENGTH_256[];
 extern const esp_efuse_desc_t* ESP_EFUSE_WDT_DELAY_SEL[];
 extern const esp_efuse_desc_t* ESP_EFUSE_SPI_BOOT_CRYPT_CNT[];
 extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE0[];
 extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE1[];
 extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE2[];
 extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_0[];
+#define ESP_EFUSE_KEY0_PURPOSE ESP_EFUSE_KEY_PURPOSE_0
 extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_1[];
+#define ESP_EFUSE_KEY1_PURPOSE ESP_EFUSE_KEY_PURPOSE_1
 extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_2[];
+#define ESP_EFUSE_KEY2_PURPOSE ESP_EFUSE_KEY_PURPOSE_2
 extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_3[];
+#define ESP_EFUSE_KEY3_PURPOSE ESP_EFUSE_KEY_PURPOSE_3
 extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_4[];
+#define ESP_EFUSE_KEY4_PURPOSE ESP_EFUSE_KEY_PURPOSE_4
 extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_5[];
+#define ESP_EFUSE_KEY5_PURPOSE ESP_EFUSE_KEY_PURPOSE_5
 extern const esp_efuse_desc_t* ESP_EFUSE_SEC_DPA_LEVEL[];
-extern const esp_efuse_desc_t* ESP_EFUSE_ECDSA_FORCE_USE_HARDWARE_K[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ECDSA_ENABLE_SOFT_K[];
 extern const esp_efuse_desc_t* ESP_EFUSE_CRYPT_DPA_ENABLE[];
 extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_EN[];
 extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE[];
@@ -102,6 +122,7 @@ extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_TPUW[];
 extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MODE[];
 extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DIRECT_BOOT[];
 extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT[];
+extern const esp_efuse_desc_t* ESP_EFUSE_LOCK_KM_KEY[];
 extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[];
 extern const esp_efuse_desc_t* ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD[];
 extern const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CONTROL[];
@@ -110,48 +131,39 @@ extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[];
 extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE[];
 extern const esp_efuse_desc_t* ESP_EFUSE_HYS_EN_PAD[];
 extern const esp_efuse_desc_t* ESP_EFUSE_DCDC_VSET[];
-extern const esp_efuse_desc_t* ESP_EFUSE__0PXA_TIEH_SEL_0[];
-extern const esp_efuse_desc_t* ESP_EFUSE__0PXA_TIEH_SEL_1[];
-extern const esp_efuse_desc_t* ESP_EFUSE__0PXA_TIEH_SEL_2[];
-extern const esp_efuse_desc_t* ESP_EFUSE__0PXA_TIEH_SEL_3[];
-extern const esp_efuse_desc_t* ESP_EFUSE_USB_DEVICE_DREFL[];
-extern const esp_efuse_desc_t* ESP_EFUSE_USB_OTG11_DREFL[];
+extern const esp_efuse_desc_t* ESP_EFUSE_PXA0_TIEH_SEL_0[];
+extern const esp_efuse_desc_t* ESP_EFUSE_PXA0_TIEH_SEL_1[];
+extern const esp_efuse_desc_t* ESP_EFUSE_PXA0_TIEH_SEL_2[];
+extern const esp_efuse_desc_t* ESP_EFUSE_PXA0_TIEH_SEL_3[];
+extern const esp_efuse_desc_t* ESP_EFUSE_KM_DISABLE_DEPLOY_MODE[];
 extern const esp_efuse_desc_t* ESP_EFUSE_HP_PWR_SRC_SEL[];
 extern const esp_efuse_desc_t* ESP_EFUSE_DCDC_VSET_EN[];
 extern const esp_efuse_desc_t* ESP_EFUSE_DIS_WDT[];
 extern const esp_efuse_desc_t* ESP_EFUSE_DIS_SWD[];
-extern const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY[];
+extern const esp_efuse_desc_t* ESP_EFUSE_MAC[];
+#define ESP_EFUSE_MAC_FACTORY ESP_EFUSE_MAC
 extern const esp_efuse_desc_t* ESP_EFUSE_MAC_EXT[];
-extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[];
-extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[];
-extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[];
-extern const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[];
-extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[];
-extern const esp_efuse_desc_t* ESP_EFUSE_TEMP_CALIB[];
-extern const esp_efuse_desc_t* ESP_EFUSE_OCODE[];
-extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0[];
-extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN1[];
-extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN2[];
-extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN3[];
-extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN0[];
-extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN1[];
-extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN2[];
-extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN3[];
+extern const esp_efuse_desc_t* ESP_EFUSE_BLOCK_SYS_DATA1[];
+#define ESP_EFUSE_SYS_DATA_PART1 ESP_EFUSE_BLOCK_SYS_DATA1
 extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[];
+#define ESP_EFUSE_BLOCK_USR_DATA ESP_EFUSE_USER_DATA
 extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA_MAC_CUSTOM[];
+#define ESP_EFUSE_MAC_CUSTOM ESP_EFUSE_USER_DATA_MAC_CUSTOM
+#define ESP_EFUSE_CUSTOM_MAC ESP_EFUSE_USER_DATA_MAC_CUSTOM
 extern const esp_efuse_desc_t* ESP_EFUSE_KEY0[];
+#define ESP_EFUSE_BLOCK_KEY0 ESP_EFUSE_KEY0
 extern const esp_efuse_desc_t* ESP_EFUSE_KEY1[];
+#define ESP_EFUSE_BLOCK_KEY1 ESP_EFUSE_KEY1
 extern const esp_efuse_desc_t* ESP_EFUSE_KEY2[];
+#define ESP_EFUSE_BLOCK_KEY2 ESP_EFUSE_KEY2
 extern const esp_efuse_desc_t* ESP_EFUSE_KEY3[];
+#define ESP_EFUSE_BLOCK_KEY3 ESP_EFUSE_KEY3
 extern const esp_efuse_desc_t* ESP_EFUSE_KEY4[];
+#define ESP_EFUSE_BLOCK_KEY4 ESP_EFUSE_KEY4
 extern const esp_efuse_desc_t* ESP_EFUSE_KEY5[];
+#define ESP_EFUSE_BLOCK_KEY5 ESP_EFUSE_KEY5
 extern const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART2[];
-extern const esp_efuse_desc_t* ESP_EFUSE_K_RTC_LDO[];
-extern const esp_efuse_desc_t* ESP_EFUSE_K_DIG_LDO[];
-extern const esp_efuse_desc_t* ESP_EFUSE_V_RTC_DBIAS20[];
-extern const esp_efuse_desc_t* ESP_EFUSE_V_DIG_DBIAS20[];
-extern const esp_efuse_desc_t* ESP_EFUSE_DIG_DBIAS_HVT[];
-extern const esp_efuse_desc_t* ESP_EFUSE_THRES_HVT[];
+#define ESP_EFUSE_BLOCK_SYS_DATA2 ESP_EFUSE_SYS_DATA_PART2
 
 #ifdef __cplusplus
 }

components/soc/esp32p4/include/soc/efuse_defs.h

@@ -0,0 +1,17 @@
+/**
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define EFUSE_WRITE_OP_CODE 0x5a5a
+#define EFUSE_READ_OP_CODE 0x5aa5
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32p4/include/soc/efuse_reg.h

@@ -7,13 +7,11 @@
 
 #include <stdint.h>
 #include "soc/soc.h"
+#include "efuse_defs.h"
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-#define EFUSE_READ_OP_CODE 0x5aa5
-#define EFUSE_WRITE_OP_CODE 0x5a5a
-
 /** EFUSE_PGM_DATA0_REG register
  *  Register 0 that stores data to be programmed.
  */
@@ -200,6 +198,13 @@ extern "C" {
 #define EFUSE_POWERGLITCH_EN_M  (EFUSE_POWERGLITCH_EN_V << EFUSE_POWERGLITCH_EN_S)
 #define EFUSE_POWERGLITCH_EN_V  0x00000001U
 #define EFUSE_POWERGLITCH_EN_S  10
+/** EFUSE_DIS_USB_SERIAL_JTAG : RO; bitpos: [11]; default: 0;
+ *  Represents whether USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled.
+ */
+#define EFUSE_DIS_USB_SERIAL_JTAG    (BIT(11))
+#define EFUSE_DIS_USB_SERIAL_JTAG_M  (EFUSE_DIS_USB_SERIAL_JTAG_V << EFUSE_DIS_USB_SERIAL_JTAG_S)
+#define EFUSE_DIS_USB_SERIAL_JTAG_V  0x00000001U
+#define EFUSE_DIS_USB_SERIAL_JTAG_S  11
 /** EFUSE_DIS_FORCE_DOWNLOAD : RO; bitpos: [12]; default: 0;
  *  Represents whether the function that forces chip into download mode is disabled or
  *  enabled. 1: disabled. 0: enabled.
@@ -256,6 +261,20 @@ extern "C" {
 #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_M  (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S)
 #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V  0x00000001U
 #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S  20
+/** EFUSE_USB_DEVICE_DREFH : RO; bitpos: [22:21]; default: 0;
+ *  USB intphy of usb device signle-end input high threshold, 1.76V to 2V. Step by 80mV
+ */
+#define EFUSE_USB_DEVICE_DREFH    0x00000003U
+#define EFUSE_USB_DEVICE_DREFH_M  (EFUSE_USB_DEVICE_DREFH_V << EFUSE_USB_DEVICE_DREFH_S)
+#define EFUSE_USB_DEVICE_DREFH_V  0x00000003U
+#define EFUSE_USB_DEVICE_DREFH_S  21
+/** EFUSE_USB_OTG11_DREFH : RO; bitpos: [24:23]; default: 0;
+ *  USB intphy of usb otg11 signle-end input high threshold, 1.76V to 2V. Step by 80mV
+ */
+#define EFUSE_USB_OTG11_DREFH    0x00000003U
+#define EFUSE_USB_OTG11_DREFH_M  (EFUSE_USB_OTG11_DREFH_V << EFUSE_USB_OTG11_DREFH_S)
+#define EFUSE_USB_OTG11_DREFH_V  0x00000003U
+#define EFUSE_USB_OTG11_DREFH_S  23
 /** EFUSE_USB_PHY_SEL : RO; bitpos: [25]; default: 0;
  *  TBD
  */
@@ -322,6 +341,13 @@ extern "C" {
 #define EFUSE_XTS_KEY_LENGTH_256_M  (EFUSE_XTS_KEY_LENGTH_256_V << EFUSE_XTS_KEY_LENGTH_256_S)
 #define EFUSE_XTS_KEY_LENGTH_256_V  0x00000001U
 #define EFUSE_XTS_KEY_LENGTH_256_S  14
+/** EFUSE_RD_RESERVE_0_79 : RW; bitpos: [15]; default: 0;
+ *  Reserved, it was created by set_missed_fields_in_regs func
+ */
+#define EFUSE_RD_RESERVE_0_79    (BIT(15))
+#define EFUSE_RD_RESERVE_0_79_M  (EFUSE_RD_RESERVE_0_79_V << EFUSE_RD_RESERVE_0_79_S)
+#define EFUSE_RD_RESERVE_0_79_V  0x00000001U
+#define EFUSE_RD_RESERVE_0_79_S  15
 /** EFUSE_WDT_DELAY_SEL : RO; bitpos: [17:16]; default: 0;
  *  Represents whether RTC watchdog timeout threshold is selected at startup. 1:
  *  selected. 0: not selected.
@@ -446,6 +472,13 @@ extern "C" {
 #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_M  (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S)
 #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V  0x00000001U
 #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S  21
+/** EFUSE_RD_RESERVE_0_118 : RW; bitpos: [22]; default: 0;
+ *  Reserved, it was created by set_missed_fields_in_regs func
+ */
+#define EFUSE_RD_RESERVE_0_118    (BIT(22))
+#define EFUSE_RD_RESERVE_0_118_M  (EFUSE_RD_RESERVE_0_118_V << EFUSE_RD_RESERVE_0_118_S)
+#define EFUSE_RD_RESERVE_0_118_V  0x00000001U
+#define EFUSE_RD_RESERVE_0_118_S  22
 /** EFUSE_FLASH_TYPE : RO; bitpos: [23]; default: 0;
  *  The type of interfaced flash. 0: four data lines, 1: eight data lines.
  */
@@ -585,34 +618,34 @@ extern "C" {
  *  BLOCK0 data register 5.
  */
 #define EFUSE_RD_REPEAT_DATA4_REG (DR_REG_EFUSE_BASE + 0x40)
-/** EFUSE_0PXA_TIEH_SEL_0 : RO; bitpos: [1:0]; default: 0;
+/** EFUSE_PXA0_TIEH_SEL_0 : RO; bitpos: [1:0]; default: 0;
  *  TBD
  */
-#define EFUSE_0PXA_TIEH_SEL_0    0x00000003U
-#define EFUSE_0PXA_TIEH_SEL_0_M  (EFUSE_0PXA_TIEH_SEL_0_V << EFUSE_0PXA_TIEH_SEL_0_S)
-#define EFUSE_0PXA_TIEH_SEL_0_V  0x00000003U
-#define EFUSE_0PXA_TIEH_SEL_0_S  0
-/** EFUSE_0PXA_TIEH_SEL_1 : RO; bitpos: [3:2]; default: 0;
+#define EFUSE_PXA0_TIEH_SEL_0    0x00000003U
+#define EFUSE_PXA0_TIEH_SEL_0_M  (EFUSE_PXA0_TIEH_SEL_0_V << EFUSE_PXA0_TIEH_SEL_0_S)
+#define EFUSE_PXA0_TIEH_SEL_0_V  0x00000003U
+#define EFUSE_PXA0_TIEH_SEL_0_S  0
+/** EFUSE_PXA0_TIEH_SEL_1 : RO; bitpos: [3:2]; default: 0;
  *  TBD.
  */
-#define EFUSE_0PXA_TIEH_SEL_1    0x00000003U
-#define EFUSE_0PXA_TIEH_SEL_1_M  (EFUSE_0PXA_TIEH_SEL_1_V << EFUSE_0PXA_TIEH_SEL_1_S)
-#define EFUSE_0PXA_TIEH_SEL_1_V  0x00000003U
-#define EFUSE_0PXA_TIEH_SEL_1_S  2
-/** EFUSE_0PXA_TIEH_SEL_2 : RO; bitpos: [5:4]; default: 0;
+#define EFUSE_PXA0_TIEH_SEL_1    0x00000003U
+#define EFUSE_PXA0_TIEH_SEL_1_M  (EFUSE_PXA0_TIEH_SEL_1_V << EFUSE_PXA0_TIEH_SEL_1_S)
+#define EFUSE_PXA0_TIEH_SEL_1_V  0x00000003U
+#define EFUSE_PXA0_TIEH_SEL_1_S  2
+/** EFUSE_PXA0_TIEH_SEL_2 : RO; bitpos: [5:4]; default: 0;
  *  TBD.
  */
-#define EFUSE_0PXA_TIEH_SEL_2    0x00000003U
-#define EFUSE_0PXA_TIEH_SEL_2_M  (EFUSE_0PXA_TIEH_SEL_2_V << EFUSE_0PXA_TIEH_SEL_2_S)
-#define EFUSE_0PXA_TIEH_SEL_2_V  0x00000003U
-#define EFUSE_0PXA_TIEH_SEL_2_S  4
-/** EFUSE_0PXA_TIEH_SEL_3 : RO; bitpos: [7:6]; default: 0;
+#define EFUSE_PXA0_TIEH_SEL_2    0x00000003U
+#define EFUSE_PXA0_TIEH_SEL_2_M  (EFUSE_PXA0_TIEH_SEL_2_V << EFUSE_PXA0_TIEH_SEL_2_S)
+#define EFUSE_PXA0_TIEH_SEL_2_V  0x00000003U
+#define EFUSE_PXA0_TIEH_SEL_2_S  4
+/** EFUSE_PXA0_TIEH_SEL_3 : RO; bitpos: [7:6]; default: 0;
  *  TBD.
  */
-#define EFUSE_0PXA_TIEH_SEL_3    0x00000003U
-#define EFUSE_0PXA_TIEH_SEL_3_M  (EFUSE_0PXA_TIEH_SEL_3_V << EFUSE_0PXA_TIEH_SEL_3_S)
-#define EFUSE_0PXA_TIEH_SEL_3_V  0x00000003U
-#define EFUSE_0PXA_TIEH_SEL_3_S  6
+#define EFUSE_PXA0_TIEH_SEL_3    0x00000003U
+#define EFUSE_PXA0_TIEH_SEL_3_M  (EFUSE_PXA0_TIEH_SEL_3_V << EFUSE_PXA0_TIEH_SEL_3_S)
+#define EFUSE_PXA0_TIEH_SEL_3_V  0x00000003U
+#define EFUSE_PXA0_TIEH_SEL_3_S  6
 /** EFUSE_KM_DISABLE_DEPLOY_MODE : RO; bitpos: [11:8]; default: 0;
  *  TBD.
  */
@@ -620,6 +653,29 @@ extern "C" {
 #define EFUSE_KM_DISABLE_DEPLOY_MODE_M  (EFUSE_KM_DISABLE_DEPLOY_MODE_V << EFUSE_KM_DISABLE_DEPLOY_MODE_S)
 #define EFUSE_KM_DISABLE_DEPLOY_MODE_V  0x0000000FU
 #define EFUSE_KM_DISABLE_DEPLOY_MODE_S  8
+/** EFUSE_USB_DEVICE_DREFL : RO; bitpos: [13:12]; default: 0;
+ *  Represents the usb device single-end input low threhold, 0.8 V to 1.04 V with step
+ *  of 80 mV.
+ */
+#define EFUSE_USB_DEVICE_DREFL    0x00000003U
+#define EFUSE_USB_DEVICE_DREFL_M  (EFUSE_USB_DEVICE_DREFL_V << EFUSE_USB_DEVICE_DREFL_S)
+#define EFUSE_USB_DEVICE_DREFL_V  0x00000003U
+#define EFUSE_USB_DEVICE_DREFL_S  12
+/** EFUSE_USB_OTG11_DREFL : RO; bitpos: [15:14]; default: 0;
+ *  Represents the usb otg11 single-end input low threhold, 0.8 V to 1.04 V with step
+ *  of 80 mV.
+ */
+#define EFUSE_USB_OTG11_DREFL    0x00000003U
+#define EFUSE_USB_OTG11_DREFL_M  (EFUSE_USB_OTG11_DREFL_V << EFUSE_USB_OTG11_DREFL_S)
+#define EFUSE_USB_OTG11_DREFL_V  0x00000003U
+#define EFUSE_USB_OTG11_DREFL_S  14
+/** EFUSE_RD_RESERVE_0_176 : RW; bitpos: [17:16]; default: 0;
+ *  Reserved, it was created by set_missed_fields_in_regs func
+ */
+#define EFUSE_RD_RESERVE_0_176    0x00000003U
+#define EFUSE_RD_RESERVE_0_176_M  (EFUSE_RD_RESERVE_0_176_V << EFUSE_RD_RESERVE_0_176_S)
+#define EFUSE_RD_RESERVE_0_176_V  0x00000003U
+#define EFUSE_RD_RESERVE_0_176_S  16
 /** EFUSE_HP_PWR_SRC_SEL : RO; bitpos: [18]; default: 0;
  *  HP system power source select. 0:LDO. 1: DCDC.
  */
@@ -648,6 +704,13 @@ extern "C" {
 #define EFUSE_DIS_SWD_M  (EFUSE_DIS_SWD_V << EFUSE_DIS_SWD_S)
 #define EFUSE_DIS_SWD_V  0x00000001U
 #define EFUSE_DIS_SWD_S  21
+/** EFUSE_RD_RESERVE_0_182 : RW; bitpos: [31:22]; default: 0;
+ *  Reserved, it was created by set_missed_fields_in_regs func
+ */
+#define EFUSE_RD_RESERVE_0_182    0x000003FFU
+#define EFUSE_RD_RESERVE_0_182_M  (EFUSE_RD_RESERVE_0_182_V << EFUSE_RD_RESERVE_0_182_S)
+#define EFUSE_RD_RESERVE_0_182_V  0x000003FFU
+#define EFUSE_RD_RESERVE_0_182_S  22
 
 /** EFUSE_RD_MAC_SYS_0_REG register
  *  BLOCK1 data register $n.
@@ -1645,6 +1708,13 @@ extern "C" {
 #define EFUSE_POWERGLITCH_EN_ERR_M  (EFUSE_POWERGLITCH_EN_ERR_V << EFUSE_POWERGLITCH_EN_ERR_S)
 #define EFUSE_POWERGLITCH_EN_ERR_V  0x00000001U
 #define EFUSE_POWERGLITCH_EN_ERR_S  10
+/** EFUSE_DIS_USB_SERIAL_JTAG_ERR : RO; bitpos: [11]; default: 0;
+ *  Indicates a programming error of DIS_USB_SERIAL_JTAG.
+ */
+#define EFUSE_DIS_USB_SERIAL_JTAG_ERR    (BIT(11))
+#define EFUSE_DIS_USB_SERIAL_JTAG_ERR_M  (EFUSE_DIS_USB_SERIAL_JTAG_ERR_V << EFUSE_DIS_USB_SERIAL_JTAG_ERR_S)
+#define EFUSE_DIS_USB_SERIAL_JTAG_ERR_V  0x00000001U
+#define EFUSE_DIS_USB_SERIAL_JTAG_ERR_S  11
 /** EFUSE_DIS_FORCE_DOWNLOAD_ERR : RO; bitpos: [12]; default: 0;
  *  Indicates a programming error of DIS_FORCE_DOWNLOAD.
  */
@@ -1694,6 +1764,20 @@ extern "C" {
 #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_M  (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S)
 #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V  0x00000001U
 #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S  20
+/** EFUSE_USB_DEVICE_DREFH_ERR : RO; bitpos: [22:21]; default: 0;
+ *  Indicates a programming error of USB_DEVICE_DREFH.
+ */
+#define EFUSE_USB_DEVICE_DREFH_ERR    0x00000003U
+#define EFUSE_USB_DEVICE_DREFH_ERR_M  (EFUSE_USB_DEVICE_DREFH_ERR_V << EFUSE_USB_DEVICE_DREFH_ERR_S)
+#define EFUSE_USB_DEVICE_DREFH_ERR_V  0x00000003U
+#define EFUSE_USB_DEVICE_DREFH_ERR_S  21
+/** EFUSE_USB_OTG11_DREFH_ERR : RO; bitpos: [24:23]; default: 0;
+ *  Indicates a programming error of USB_OTG11_DREFH.
+ */
+#define EFUSE_USB_OTG11_DREFH_ERR    0x00000003U
+#define EFUSE_USB_OTG11_DREFH_ERR_M  (EFUSE_USB_OTG11_DREFH_ERR_V << EFUSE_USB_OTG11_DREFH_ERR_S)
+#define EFUSE_USB_OTG11_DREFH_ERR_V  0x00000003U
+#define EFUSE_USB_OTG11_DREFH_ERR_S  23
 /** EFUSE_USB_PHY_SEL_ERR : RO; bitpos: [25]; default: 0;
  *  Indicates a programming error of USB_PHY_SEL.
  */
@@ -2001,34 +2085,34 @@ extern "C" {
  *  Programming error record register 4 of BLOCK0.
  */
 #define EFUSE_RD_REPEAT_ERR4_REG (DR_REG_EFUSE_BASE + 0x18c)
-/** EFUSE_0PXA_TIEH_SEL_0_ERR : RO; bitpos: [1:0]; default: 0;
+/** EFUSE_PXA0_TIEH_SEL_0_ERR : RO; bitpos: [1:0]; default: 0;
  *  Indicates a programming error of 0PXA_TIEH_SEL_0.
  */
-#define EFUSE_0PXA_TIEH_SEL_0_ERR    0x00000003U
-#define EFUSE_0PXA_TIEH_SEL_0_ERR_M  (EFUSE_0PXA_TIEH_SEL_0_ERR_V << EFUSE_0PXA_TIEH_SEL_0_ERR_S)
-#define EFUSE_0PXA_TIEH_SEL_0_ERR_V  0x00000003U
-#define EFUSE_0PXA_TIEH_SEL_0_ERR_S  0
-/** EFUSE_0PXA_TIEH_SEL_1_ERR : RO; bitpos: [3:2]; default: 0;
+#define EFUSE_PXA0_TIEH_SEL_0_ERR    0x00000003U
+#define EFUSE_PXA0_TIEH_SEL_0_ERR_M  (EFUSE_PXA0_TIEH_SEL_0_ERR_V << EFUSE_PXA0_TIEH_SEL_0_ERR_S)
+#define EFUSE_PXA0_TIEH_SEL_0_ERR_V  0x00000003U
+#define EFUSE_PXA0_TIEH_SEL_0_ERR_S  0
+/** EFUSE_PXA0_TIEH_SEL_1_ERR : RO; bitpos: [3:2]; default: 0;
  *  Indicates a programming error of 0PXA_TIEH_SEL_1.
  */
-#define EFUSE_0PXA_TIEH_SEL_1_ERR    0x00000003U
-#define EFUSE_0PXA_TIEH_SEL_1_ERR_M  (EFUSE_0PXA_TIEH_SEL_1_ERR_V << EFUSE_0PXA_TIEH_SEL_1_ERR_S)
-#define EFUSE_0PXA_TIEH_SEL_1_ERR_V  0x00000003U
-#define EFUSE_0PXA_TIEH_SEL_1_ERR_S  2
-/** EFUSE_0PXA_TIEH_SEL_2_ERR : RO; bitpos: [5:4]; default: 0;
+#define EFUSE_PXA0_TIEH_SEL_1_ERR    0x00000003U
+#define EFUSE_PXA0_TIEH_SEL_1_ERR_M  (EFUSE_PXA0_TIEH_SEL_1_ERR_V << EFUSE_PXA0_TIEH_SEL_1_ERR_S)
+#define EFUSE_PXA0_TIEH_SEL_1_ERR_V  0x00000003U
+#define EFUSE_PXA0_TIEH_SEL_1_ERR_S  2
+/** EFUSE_PXA0_TIEH_SEL_2_ERR : RO; bitpos: [5:4]; default: 0;
  *  Indicates a programming error of 0PXA_TIEH_SEL_2.
  */
-#define EFUSE_0PXA_TIEH_SEL_2_ERR    0x00000003U
-#define EFUSE_0PXA_TIEH_SEL_2_ERR_M  (EFUSE_0PXA_TIEH_SEL_2_ERR_V << EFUSE_0PXA_TIEH_SEL_2_ERR_S)
-#define EFUSE_0PXA_TIEH_SEL_2_ERR_V  0x00000003U
-#define EFUSE_0PXA_TIEH_SEL_2_ERR_S  4
-/** EFUSE_0PXA_TIEH_SEL_3_ERR : RO; bitpos: [7:6]; default: 0;
+#define EFUSE_PXA0_TIEH_SEL_2_ERR    0x00000003U
+#define EFUSE_PXA0_TIEH_SEL_2_ERR_M  (EFUSE_PXA0_TIEH_SEL_2_ERR_V << EFUSE_PXA0_TIEH_SEL_2_ERR_S)
+#define EFUSE_PXA0_TIEH_SEL_2_ERR_V  0x00000003U
+#define EFUSE_PXA0_TIEH_SEL_2_ERR_S  4
+/** EFUSE_PXA0_TIEH_SEL_3_ERR : RO; bitpos: [7:6]; default: 0;
  *  Indicates a programming error of 0PXA_TIEH_SEL_3.
  */
-#define EFUSE_0PXA_TIEH_SEL_3_ERR    0x00000003U
-#define EFUSE_0PXA_TIEH_SEL_3_ERR_M  (EFUSE_0PXA_TIEH_SEL_3_ERR_V << EFUSE_0PXA_TIEH_SEL_3_ERR_S)
-#define EFUSE_0PXA_TIEH_SEL_3_ERR_V  0x00000003U
-#define EFUSE_0PXA_TIEH_SEL_3_ERR_S  6
+#define EFUSE_PXA0_TIEH_SEL_3_ERR    0x00000003U
+#define EFUSE_PXA0_TIEH_SEL_3_ERR_M  (EFUSE_PXA0_TIEH_SEL_3_ERR_V << EFUSE_PXA0_TIEH_SEL_3_ERR_S)
+#define EFUSE_PXA0_TIEH_SEL_3_ERR_V  0x00000003U
+#define EFUSE_PXA0_TIEH_SEL_3_ERR_S  6
 /** EFUSE_KM_DISABLE_DEPLOY_MODE_ERR : RO; bitpos: [11:8]; default: 0;
  *  TBD.
  */
@@ -2302,6 +2386,48 @@ extern "C" {
 #define EFUSE_STATE_M  (EFUSE_STATE_V << EFUSE_STATE_S)
 #define EFUSE_STATE_V  0x0000000FU
 #define EFUSE_STATE_S  0
+/** EFUSE_OTP_LOAD_SW : RO; bitpos: [4]; default: 0;
+ *  The value of OTP_LOAD_SW.
+ */
+#define EFUSE_OTP_LOAD_SW    (BIT(4))
+#define EFUSE_OTP_LOAD_SW_M  (EFUSE_OTP_LOAD_SW_V << EFUSE_OTP_LOAD_SW_S)
+#define EFUSE_OTP_LOAD_SW_V  0x00000001U
+#define EFUSE_OTP_LOAD_SW_S  4
+/** EFUSE_OTP_VDDQ_C_SYNC2 : RO; bitpos: [5]; default: 0;
+ *  The value of OTP_VDDQ_C_SYNC2.
+ */
+#define EFUSE_OTP_VDDQ_C_SYNC2    (BIT(5))
+#define EFUSE_OTP_VDDQ_C_SYNC2_M  (EFUSE_OTP_VDDQ_C_SYNC2_V << EFUSE_OTP_VDDQ_C_SYNC2_S)
+#define EFUSE_OTP_VDDQ_C_SYNC2_V  0x00000001U
+#define EFUSE_OTP_VDDQ_C_SYNC2_S  5
+/** EFUSE_OTP_STROBE_SW : RO; bitpos: [6]; default: 0;
+ *  The value of OTP_STROBE_SW.
+ */
+#define EFUSE_OTP_STROBE_SW    (BIT(6))
+#define EFUSE_OTP_STROBE_SW_M  (EFUSE_OTP_STROBE_SW_V << EFUSE_OTP_STROBE_SW_S)
+#define EFUSE_OTP_STROBE_SW_V  0x00000001U
+#define EFUSE_OTP_STROBE_SW_S  6
+/** EFUSE_OTP_CSB_SW : RO; bitpos: [7]; default: 0;
+ *  The value of OTP_CSB_SW.
+ */
+#define EFUSE_OTP_CSB_SW    (BIT(7))
+#define EFUSE_OTP_CSB_SW_M  (EFUSE_OTP_CSB_SW_V << EFUSE_OTP_CSB_SW_S)
+#define EFUSE_OTP_CSB_SW_V  0x00000001U
+#define EFUSE_OTP_CSB_SW_S  7
+/** EFUSE_OTP_PGENB_SW : RO; bitpos: [8]; default: 0;
+ *  The value of OTP_PGENB_SW.
+ */
+#define EFUSE_OTP_PGENB_SW    (BIT(8))
+#define EFUSE_OTP_PGENB_SW_M  (EFUSE_OTP_PGENB_SW_V << EFUSE_OTP_PGENB_SW_S)
+#define EFUSE_OTP_PGENB_SW_V  0x00000001U
+#define EFUSE_OTP_PGENB_SW_S  8
+/** EFUSE_OTP_VDDQ_IS_SW : RO; bitpos: [9]; default: 0;
+ *  The value of OTP_VDDQ_IS_SW.
+ */
+#define EFUSE_OTP_VDDQ_IS_SW    (BIT(9))
+#define EFUSE_OTP_VDDQ_IS_SW_M  (EFUSE_OTP_VDDQ_IS_SW_V << EFUSE_OTP_VDDQ_IS_SW_S)
+#define EFUSE_OTP_VDDQ_IS_SW_V  0x00000001U
+#define EFUSE_OTP_VDDQ_IS_SW_S  9
 /** EFUSE_BLK0_VALID_BIT_CNT : RO; bitpos: [19:10]; default: 0;
  *  Indicates the number of block valid bit.
  */

components/soc/esp32p4/include/soc/efuse_struct.h

@@ -197,7 +197,10 @@ typedef union {
          *  Represents whether power glitch function is enabled. 1: enabled. 0: disabled.
          */
         uint32_t powerglitch_en:1;
-        uint32_t reserved_11:1;
+        /** dis_usb_serial_jtag : RO; bitpos: [11]; default: 0;
+         *  Represents whether USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled.
+         */
+        uint32_t dis_usb_serial_jtag:1;
         /** dis_force_download : RO; bitpos: [12]; default: 0;
          *  Represents whether the function that forces chip into download mode is disabled or
          *  enabled. 1: disabled. 0: enabled.
@@ -233,7 +236,14 @@ typedef union {
          *  mode). 1: disabled. 0: enabled.
          */
         uint32_t dis_download_manual_encrypt:1;
-        uint32_t reserved_21:4;
+        /** usb_device_drefh : RO; bitpos: [22:21]; default: 0;
+         *  USB intphy of usb device signle-end input high threshold, 1.76V to 2V. Step by 80mV
+         */
+        uint32_t usb_device_drefh:2;
+        /** usb_otg11_drefh : RO; bitpos: [24:23]; default: 0;
+         *  USB intphy of usb otg11 signle-end input high threshold, 1.76V to 2V. Step by 80mV
+         */
+        uint32_t usb_otg11_drefh:2;
         /** usb_phy_sel : RO; bitpos: [25]; default: 0;
          *  TBD
          */
@@ -280,7 +290,10 @@ typedef union {
          *  Set this bit to configure flash encryption use xts-128 key, else use xts-256 key.
          */
         uint32_t xts_key_length_256:1;
-        uint32_t reserved_15:1;
+        /** rd_reserve_0_79 : RW; bitpos: [15]; default: 0;
+         *  Reserved, it was created by set_missed_fields_in_regs func
+         */
+        uint32_t rd_reserve_0_79:1;
         /** wdt_delay_sel : RO; bitpos: [17:16]; default: 0;
          *  Represents whether RTC watchdog timeout threshold is selected at startup. 1:
          *  selected. 0: not selected.
@@ -361,7 +374,10 @@ typedef union {
          *  enabled. 0: disabled.
          */
         uint32_t secure_boot_aggressive_revoke:1;
-        uint32_t reserved_22:1;
+        /** rd_reserve_0_118 : RW; bitpos: [22]; default: 0;
+         *  Reserved, it was created by set_missed_fields_in_regs func
+         */
+        uint32_t rd_reserve_0_118:1;
         /** flash_type : RO; bitpos: [23]; default: 0;
          *  The type of interfaced flash. 0: four data lines, 1: eight data lines.
          */
@@ -458,27 +474,40 @@ typedef union {
  */
 typedef union {
     struct {
-        /** 0pxa_tieh_sel_0 : RO; bitpos: [1:0]; default: 0;
+        /** pxa0_tieh_sel_0 : RO; bitpos: [1:0]; default: 0;
          *  TBD
          */
-        uint32_t rd_0pxa_tieh_sel_0:2;
-        /** 0pxa_tieh_sel_1 : RO; bitpos: [3:2]; default: 0;
+        uint32_t pxa0_tieh_sel_0:2;
+        /** pxa0_tieh_sel_1 : RO; bitpos: [3:2]; default: 0;
          *  TBD.
          */
-        uint32_t rd_0pxa_tieh_sel_1:2;
-        /** 0pxa_tieh_sel_2 : RO; bitpos: [5:4]; default: 0;
+        uint32_t pxa0_tieh_sel_1:2;
+        /** pxa0_tieh_sel_2 : RO; bitpos: [5:4]; default: 0;
          *  TBD.
          */
-        uint32_t rd_0pxa_tieh_sel_2:2;
-        /** 0pxa_tieh_sel_3 : RO; bitpos: [7:6]; default: 0;
+        uint32_t pxa0_tieh_sel_2:2;
+        /** pxa0_tieh_sel_3 : RO; bitpos: [7:6]; default: 0;
          *  TBD.
          */
-        uint32_t rd_0pxa_tieh_sel_3:2;
+        uint32_t pxa0_tieh_sel_3:2;
         /** km_disable_deploy_mode : RO; bitpos: [11:8]; default: 0;
          *  TBD.
          */
         uint32_t km_disable_deploy_mode:4;
-        uint32_t reserved_12:6;
+        /** usb_device_drefl : RO; bitpos: [13:12]; default: 0;
+         *  Represents the usb device single-end input low threhold, 0.8 V to 1.04 V with step
+         *  of 80 mV.
+         */
+        uint32_t usb_device_drefl:2;
+        /** usb_otg11_drefl : RO; bitpos: [15:14]; default: 0;
+         *  Represents the usb otg11 single-end input low threhold, 0.8 V to 1.04 V with step
+         *  of 80 mV.
+         */
+        uint32_t usb_otg11_drefl:2;
+        /** rd_reserve_0_176 : RW; bitpos: [17:16]; default: 0;
+         *  Reserved, it was created by set_missed_fields_in_regs func
+         */
+        uint32_t rd_reserve_0_176:2;
         /** hp_pwr_src_sel : RO; bitpos: [18]; default: 0;
          *  HP system power source select. 0:LDO. 1: DCDC.
          */
@@ -495,7 +524,10 @@ typedef union {
          *  Set this bit to disable super-watchdog.
          */
         uint32_t dis_swd:1;
-        uint32_t reserved_22:10;
+        /** rd_reserve_0_182 : RW; bitpos: [31:22]; default: 0;
+         *  Reserved, it was created by set_missed_fields_in_regs func
+         */
+        uint32_t rd_reserve_0_182:10;
     };
     uint32_t val;
 } efuse_rd_repeat_data4_reg_t;
@@ -1551,7 +1583,10 @@ typedef union {
          *  Indicates a programming error of POWERGLITCH_EN.
          */
         uint32_t powerglitch_en_err:1;
-        uint32_t reserved_11:1;
+        /** dis_usb_serial_jtag_err : RO; bitpos: [11]; default: 0;
+         *  Indicates a programming error of DIS_USB_SERIAL_JTAG.
+         */
+        uint32_t dis_usb_serial_jtag_err:1;
         /** dis_force_download_err : RO; bitpos: [12]; default: 0;
          *  Indicates a programming error of DIS_FORCE_DOWNLOAD.
          */
@@ -1580,7 +1615,14 @@ typedef union {
          *  Indicates a programming error of DIS_DOWNLOAD_MANUAL_ENCRYPT.
          */
         uint32_t dis_download_manual_encrypt_err:1;
-        uint32_t reserved_21:4;
+        /** usb_device_drefh_err : RO; bitpos: [22:21]; default: 0;
+         *  Indicates a programming error of USB_DEVICE_DREFH.
+         */
+        uint32_t usb_device_drefh_err:2;
+        /** usb_otg11_drefh_err : RO; bitpos: [24:23]; default: 0;
+         *  Indicates a programming error of USB_OTG11_DREFH.
+         */
+        uint32_t usb_otg11_drefh_err:2;
         /** usb_phy_sel_err : RO; bitpos: [25]; default: 0;
          *  Indicates a programming error of USB_PHY_SEL.
          */
@@ -1783,22 +1825,22 @@ typedef union {
  */
 typedef union {
     struct {
-        /** 0pxa_tieh_sel_0_err : RO; bitpos: [1:0]; default: 0;
+        /** pxa0_tieh_sel_0_err : RO; bitpos: [1:0]; default: 0;
          *  Indicates a programming error of 0PXA_TIEH_SEL_0.
          */
-        uint32_t rd_0pxa_tieh_sel_0_err:2;
-        /** 0pxa_tieh_sel_1_err : RO; bitpos: [3:2]; default: 0;
+        uint32_t pxa0_tieh_sel_0_err:2;
+        /** pxa0_tieh_sel_1_err : RO; bitpos: [3:2]; default: 0;
          *  Indicates a programming error of 0PXA_TIEH_SEL_1.
          */
-        uint32_t rd_0pxa_tieh_sel_1_err:2;
-        /** 0pxa_tieh_sel_2_err : RO; bitpos: [5:4]; default: 0;
+        uint32_t pxa0_tieh_sel_1_err:2;
+        /** pxa0_tieh_sel_2_err : RO; bitpos: [5:4]; default: 0;
          *  Indicates a programming error of 0PXA_TIEH_SEL_2.
          */
-        uint32_t rd_0pxa_tieh_sel_2_err:2;
-        /** 0pxa_tieh_sel_3_err : RO; bitpos: [7:6]; default: 0;
+        uint32_t pxa0_tieh_sel_2_err:2;
+        /** pxa0_tieh_sel_3_err : RO; bitpos: [7:6]; default: 0;
          *  Indicates a programming error of 0PXA_TIEH_SEL_3.
          */
-        uint32_t rd_0pxa_tieh_sel_3_err:2;
+        uint32_t pxa0_tieh_sel_3_err:2;
         /** km_disable_deploy_mode_err : RO; bitpos: [11:8]; default: 0;
          *  TBD.
          */
@@ -1996,7 +2038,30 @@ typedef union {
          *  Indicates the state of the eFuse state machine.
          */
         uint32_t state:4;
-        uint32_t reserved_4:6;
+        /** otp_load_sw : RO; bitpos: [4]; default: 0;
+         *  The value of OTP_LOAD_SW.
+         */
+        uint32_t otp_load_sw:1;
+        /** otp_vddq_c_sync2 : RO; bitpos: [5]; default: 0;
+         *  The value of OTP_VDDQ_C_SYNC2.
+         */
+        uint32_t otp_vddq_c_sync2:1;
+        /** otp_strobe_sw : RO; bitpos: [6]; default: 0;
+         *  The value of OTP_STROBE_SW.
+         */
+        uint32_t otp_strobe_sw:1;
+        /** otp_csb_sw : RO; bitpos: [7]; default: 0;
+         *  The value of OTP_CSB_SW.
+         */
+        uint32_t otp_csb_sw:1;
+        /** otp_pgenb_sw : RO; bitpos: [8]; default: 0;
+         *  The value of OTP_PGENB_SW.
+         */
+        uint32_t otp_pgenb_sw:1;
+        /** otp_vddq_is_sw : RO; bitpos: [9]; default: 0;
+         *  The value of OTP_VDDQ_IS_SW.
+         */
+        uint32_t otp_vddq_is_sw:1;
         /** blk0_valid_bit_cnt : RO; bitpos: [19:10]; default: 0;
          *  Indicates the number of block valid bit.
          */