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+// Copyright 2010-2019 Espressif Systems (Shanghai) PTE LTD
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+//
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+// Licensed under the Apache License, Version 2.0 (the "License");
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+// you may not use this file except in compliance with the License.
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+// You may obtain a copy of the License at
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+//
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+// http://www.apache.org/licenses/LICENSE-2.0
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+//
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+// Unless required by applicable law or agreed to in writing, software
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+// distributed under the License is distributed on an "AS IS" BASIS,
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+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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+// See the License for the specific language governing permissions and
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+// limitations under the License.
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+
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+#pragma once
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+
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+#ifdef __cplusplus
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+extern "C" {
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+#endif
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+
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+/** Definition of a common transaction. Also holds the return value. */
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+typedef struct {
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+ uint8_t command; ///< Command to send, always 8bits
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+ uint8_t mosi_len; ///< Output data length, in bytes
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+ uint8_t miso_len; ///< Input data length, in bytes
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+ uint8_t address_bitlen; ///< Length of address in bits, set to 0 if command does not need an address
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+ uint32_t address; ///< Address to perform operation on
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+ const uint8_t *mosi_data; ///< Output data to salve
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+ uint8_t *miso_data; ///< [out] Input data from slave, little endian
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+} spi_flash_trans_t;
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+
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+/** @brief Mode used for reading from SPI flash */
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+typedef enum {
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+ SPI_FLASH_SLOWRD = 0, ///< Data read using single I/O, some limits on speed
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+ SPI_FLASH_FASTRD, ///< Data read using single I/O, no limit on speed
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+ SPI_FLASH_DOUT, ///< Data read using dual I/O
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+ SPI_FLASH_DIO, ///< Both address & data transferred using dual I/O
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+ SPI_FLASH_QOUT, ///< Data read using quad I/O
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+ SPI_FLASH_QIO, ///< Both address & data transferred using quad I/O
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+
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+ SPI_FLASH_READ_MODE_MAX, ///< The fastest io mode supported by the host is ``ESP_FLASH_READ_MODE_MAX-1``.
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+} esp_flash_io_mode_t;
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+
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+struct spi_flash_host_driver_s;
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+typedef struct spi_flash_host_driver_s spi_flash_host_driver_t;
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+
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+/** SPI Flash Host driver instance */
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+typedef struct {
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+ const struct spi_flash_host_driver_s* driver; ///< Pointer to the implementation function table
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+ // Implementations can wrap this structure into their own ones, and append other data here
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+} spi_flash_host_inst_t ;
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+
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+/** Host driver configuration and context structure. */
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+struct spi_flash_host_driver_s {
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+ /**
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+ * Configure the device-related register before transactions. This saves
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+ * some time to re-configure those registers when we send continuously
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+ */
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+ esp_err_t (*dev_config)(spi_flash_host_inst_t *host);
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+ /**
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+ * Send an user-defined spi transaction to the device.
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+ */
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+ esp_err_t (*common_command)(spi_flash_host_inst_t *host, spi_flash_trans_t *t);
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+ /**
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+ * Read flash ID.
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+ */
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+ esp_err_t (*read_id)(spi_flash_host_inst_t *host, uint32_t *id);
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+ /**
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+ * Erase whole flash chip.
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+ */
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+ void (*erase_chip)(spi_flash_host_inst_t *host);
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+ /**
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+ * Erase a specific sector by its start address.
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+ */
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+ void (*erase_sector)(spi_flash_host_inst_t *host, uint32_t start_address);
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+ /**
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+ * Erase a specific block by its start address.
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+ */
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+ void (*erase_block)(spi_flash_host_inst_t *host, uint32_t start_address);
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+ /**
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+ * Read the status of the flash chip.
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+ */
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+ esp_err_t (*read_status)(spi_flash_host_inst_t *host, uint8_t *out_sr);
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+ /**
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+ * Disable write protection.
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+ */
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+ esp_err_t (*set_write_protect)(spi_flash_host_inst_t *host, bool wp);
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+ /**
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+ * Program a page of the flash. Check ``max_write_bytes`` for the maximum allowed writing length.
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+ */
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+ void (*program_page)(spi_flash_host_inst_t *host, const void *buffer, uint32_t address, uint32_t length);
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+ /** Check whether given buffer can be directly used to write */
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+ bool (*supports_direct_write)(spi_flash_host_inst_t *host, const void *p);
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+ /**
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+ * Slicer for write data. The `program_page` should be called iteratively with the return value
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+ * of this function.
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+ *
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+ * @param address Beginning flash address to write
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+ * @param len Length request to write
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+ * @param align_addr Output of the aligned address to write to
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+ * @param page_size Physical page size of the flash chip
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+ * @return Length that can be actually written in one `program_page` call
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+ */
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+ int (*write_data_slicer)(spi_flash_host_inst_t *host, uint32_t address, uint32_t len, uint32_t *align_addr,
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+ uint32_t page_size);
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+ /**
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+ * Read data from the flash. Check ``max_read_bytes`` for the maximum allowed reading length.
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+ */
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+ esp_err_t (*read)(spi_flash_host_inst_t *host, void *buffer, uint32_t address, uint32_t read_len);
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+ /** Check whether given buffer can be directly used to read */
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+ bool (*supports_direct_read)(spi_flash_host_inst_t *host, const void *p);
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+ /**
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+ * Slicer for read data. The `read` should be called iteratively with the return value
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+ * of this function.
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+ *
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+ * @param address Beginning flash address to read
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+ * @param len Length request to read
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+ * @param align_addr Output of the aligned address to read
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+ * @param page_size Physical page size of the flash chip
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+ * @return Length that can be actually read in one `read` call
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+ */
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+ int (*read_data_slicer)(spi_flash_host_inst_t *host, uint32_t address, uint32_t len, uint32_t *align_addr, uint32_t page_size);
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+ /**
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+ * Check whether the host is idle to perform new operations.
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+ */
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+ bool (*host_idle)(spi_flash_host_inst_t *host);
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+ /**
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+ * Configure the host to work at different read mode. Responsible to compensate the timing and set IO mode.
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+ */
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+ esp_err_t (*configure_host_io_mode)(spi_flash_host_inst_t *host, uint32_t command,
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+ uint32_t addr_bitlen, int dummy_bitlen_base,
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+ esp_flash_io_mode_t io_mode);
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+ /**
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+ * Internal use, poll the HW until the last operation is done.
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+ */
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+ void (*poll_cmd_done)(spi_flash_host_inst_t *host);
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+ /**
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+ * For some host (SPI1), they are shared with a cache. When the data is
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+ * modified, the cache needs to be flushed. Left NULL if not supported.
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+ */
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+ esp_err_t (*flush_cache)(spi_flash_host_inst_t* host, uint32_t addr, uint32_t size);
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+};
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+///Slowest io mode supported by ESP32, currently SlowRd
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+#define SPI_FLASH_READ_MODE_MIN SPI_FLASH_SLOWRD
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+
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+#ifdef __cplusplus
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+}
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+#endif
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Jakob Hasse