soc: update iram/dram addr range in ext_mem_defs.h

IRAM0/DRAM0 addr range update, on s3, c3, c2, h4, c6:

IRAM0_ADDRESS_LOW ~ IRAM0_ADDRESS_HIGH
DRAM0_ADDRESS_LOW ~ DRAM0_ADDRESS_HIGH

now are for the real IRAM0 and DRAM0

components/soc/esp32c2/include/soc/ext_mem_defs.h

@@ -15,18 +15,18 @@ extern "C" {
 #include <stdint.h>
 
 /*IRAM0 is connected with Cache IBUS0*/
-#define IRAM0_ADDRESS_LOW               0x40000000
-#define IRAM0_ADDRESS_HIGH(page_size)              IRAM0_CACHE_ADDRESS_HIGH(page_size)
-#define IRAM0_CACHE_ADDRESS_LOW         0x42000000
-#define IRAM0_CACHE_ADDRESS_HIGH(page_size)        (IRAM0_CACHE_ADDRESS_LOW + ((page_size) * 64)) // MMU has 64 pages
+#define IRAM0_ADDRESS_LOW                      0x4037C000
+#define IRAM0_ADDRESS_HIGH                     0x403C0000
+#define IRAM0_CACHE_ADDRESS_LOW                0x42000000
+#define IRAM0_CACHE_ADDRESS_HIGH(page_size)    (IRAM0_CACHE_ADDRESS_LOW + ((page_size) * 64)) // MMU has 64 pages
 
 /*DRAM0 is connected with Cache DBUS0*/
-#define DRAM0_ADDRESS_LOW               0x3C000000
-#define DRAM0_ADDRESS_HIGH              0x40000000
-#define DRAM0_CACHE_ADDRESS_LOW         0x3C000000
-#define DRAM0_CACHE_ADDRESS_HIGH(page_size)        (DRAM0_CACHE_ADDRESS_LOW + ((page_size) * 64))
-#define DRAM0_CACHE_OPERATION_HIGH(page_size)      DRAM0_CACHE_ADDRESS_HIGH(page_size)
-#define ESP_CACHE_TEMP_ADDR             0x3C000000
+#define DRAM0_ADDRESS_LOW                      0x3FCA0000
+#define DRAM0_ADDRESS_HIGH                     0x3FCE0000
+#define DRAM0_CACHE_ADDRESS_LOW                0x3C000000
+#define DRAM0_CACHE_ADDRESS_HIGH(page_size)    (DRAM0_CACHE_ADDRESS_LOW + ((page_size) * 64)) // MMU has 64 pages
+#define DRAM0_CACHE_OPERATION_HIGH(page_size)  DRAM0_CACHE_ADDRESS_HIGH(page_size)
+#define ESP_CACHE_TEMP_ADDR                    0x3C000000
 
 #define BUS_SIZE(bus_name, page_size)                 (bus_name##_ADDRESS_HIGH(page_size) - bus_name##_ADDRESS_LOW)
 #define ADDRESS_IN_BUS(bus_name, vaddr, page_size)    ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH(page_size))

components/soc/esp32c3/include/soc/ext_mem_defs.h

@@ -13,14 +13,14 @@ extern "C" {
 #endif
 
 /*IRAM0 is connected with Cache IBUS0*/
-#define IRAM0_ADDRESS_LOW               0x40000000
-#define IRAM0_ADDRESS_HIGH              0x44000000
+#define IRAM0_ADDRESS_LOW               0x4037C000
+#define IRAM0_ADDRESS_HIGH              0x403E0000
 #define IRAM0_CACHE_ADDRESS_LOW	        0x42000000
 #define IRAM0_CACHE_ADDRESS_HIGH        0x42800000
 
 /*DRAM0 is connected with Cache DBUS0*/
-#define DRAM0_ADDRESS_LOW               0x3C000000
-#define DRAM0_ADDRESS_HIGH              0x40000000
+#define DRAM0_ADDRESS_LOW               0x3FC80000
+#define DRAM0_ADDRESS_HIGH              0x3FCE0000
 #define DRAM0_CACHE_ADDRESS_LOW         0x3C000000
 #define DRAM0_CACHE_ADDRESS_HIGH        0x3C800000
 #define DRAM0_CACHE_OPERATION_HIGH      DRAM0_CACHE_ADDRESS_HIGH

components/soc/esp32c6/include/soc/ext_mem_defs.h

@@ -13,16 +13,14 @@
 extern "C" {
 #endif
 
-/*IRAM0 is connected with Cache IBUS0*/
-#define IRAM0_CACHE_ADDRESS_LOW             0x42000000
-#define IRAM0_CACHE_ADDRESS_HIGH(page_size) (IRAM0_CACHE_ADDRESS_LOW + ((page_size) * 256))
-#define IRAM0_ADDRESS_LOW                   0x40000000
-#define IRAM0_ADDRESS_HIGH(page_size)       IRAM0_CACHE_ADDRESS_HIGH(page_size)
-
-/*DRAM0 is connected with Cache DBUS0*/
-#define DRAM0_ADDRESS_LOW                        0x42000000
-#define DRAM0_ADDRESS_HIGH                       0x43000000
-#define DRAM0_CACHE_ADDRESS_LOW                  IRAM0_CACHE_ADDRESS_LOW     //I/D share the same vaddr range
+#define IRAM0_ADDRESS_LOW                        0x40800000
+#define IRAM0_ADDRESS_HIGH                       0x40880000
+#define IRAM0_CACHE_ADDRESS_LOW                  0x42000000
+#define IRAM0_CACHE_ADDRESS_HIGH(page_size)      (IRAM0_CACHE_ADDRESS_LOW + ((page_size) * 256))
+
+#define DRAM0_ADDRESS_LOW                        IRAM0_ADDRESS_LOW                      //I/D share the same vaddr range
+#define DRAM0_ADDRESS_HIGH                       IRAM0_ADDRESS_HIGH                     //I/D share the same vaddr range
+#define DRAM0_CACHE_ADDRESS_LOW                  IRAM0_CACHE_ADDRESS_LOW                //I/D share the same vaddr range
 #define DRAM0_CACHE_ADDRESS_HIGH(page_size)      IRAM0_CACHE_ADDRESS_HIGH(page_size)    //I/D share the same vaddr range
 #define DRAM0_CACHE_OPERATION_HIGH(page_size)    DRAM0_CACHE_ADDRESS_HIGH(page_size)
 #define ESP_CACHE_TEMP_ADDR                      0x42000000

components/soc/esp32h4/include/soc/ext_mem_defs.h

@@ -13,14 +13,14 @@ extern "C" {
 #endif
 
 /*IRAM0 is connected with Cache IBUS0*/
-#define IRAM0_ADDRESS_LOW               0x40000000
-#define IRAM0_ADDRESS_HIGH              0x44000000
-#define IRAM0_CACHE_ADDRESS_LOW	        0x42000000
+#define IRAM0_ADDRESS_LOW               0x4037C000
+#define IRAM0_ADDRESS_HIGH              0x403E0000
+#define IRAM0_CACHE_ADDRESS_LOW         0x42000000
 #define IRAM0_CACHE_ADDRESS_HIGH        0x42800000
 
 /*DRAM0 is connected with Cache DBUS0*/
-#define DRAM0_ADDRESS_LOW               0x3C000000
-#define DRAM0_ADDRESS_HIGH              0x40000000
+#define DRAM0_ADDRESS_LOW               0x3FC80000
+#define DRAM0_ADDRESS_HIGH              0x3FCE0000
 #define DRAM0_CACHE_ADDRESS_LOW         0x3C000000
 #define DRAM0_CACHE_ADDRESS_HIGH        0x3C800000
 #define DRAM0_CACHE_OPERATION_HIGH      DRAM0_CACHE_ADDRESS_HIGH

components/soc/esp32s3/include/soc/ext_mem_defs.h

@@ -12,14 +12,14 @@ extern "C" {
 #endif
 
 /*IRAM0 is connected with Cache IBUS0*/
-#define IRAM0_ADDRESS_LOW               0x40000000
-#define IRAM0_ADDRESS_HIGH              0x44000000
+#define IRAM0_ADDRESS_LOW               0x40370000
+#define IRAM0_ADDRESS_HIGH              0x403E0000
 #define IRAM0_CACHE_ADDRESS_LOW         0x42000000
 #define IRAM0_CACHE_ADDRESS_HIGH        0x44000000
 
 /*DRAM0 is connected with Cache DBUS0*/
-#define DRAM0_ADDRESS_LOW               0x3C000000
-#define DRAM0_ADDRESS_HIGH              0x40000000
+#define DRAM0_ADDRESS_LOW               0x3FC88000
+#define DRAM0_ADDRESS_HIGH              0x3FD00000
 #define DRAM0_CACHE_ADDRESS_LOW         0x3C000000
 #define DRAM0_CACHE_ADDRESS_HIGH        0x3E000000
 #define DRAM0_CACHE_OPERATION_HIGH      DRAM0_CACHE_ADDRESS_HIGH