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@@ -17,7 +17,7 @@ extern "C" {
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/** USB_SERIAL_JTAG_EP1_REG register
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* USB_SERIAL_JTAG_EP1_REG.
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*/
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-#define USB_SERIAL_JTAG_EP1_REG (SOC_DPORT_USB_BASE + 0x0)
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+#define USB_SERIAL_JTAG_EP1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x0)
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/* USB_SERIAL_JTAG_RDWR_BYTE : R/W; bitpos: [8:0]; default: 0;
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* Write and read byte data to/from UART Tx/Rx FIFO through this field.
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* When USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT is set then user can write
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@@ -36,7 +36,7 @@ extern "C" {
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/** USB_SERIAL_JTAG_CONF0_REG register
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* USB_SERIAL_JTAG_CONF0_REG.
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*/
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-#define USB_SERIAL_JTAG_CONF0_REG (SOC_DPORT_USB_BASE + 0x18)
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+#define USB_SERIAL_JTAG_CONF0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x18)
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/* USB_SERIAL_JTAG_PHY_SEL : R/W; bitpos: [0]; default: 0;
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* Select internal/external PHY. 1’b0: internal PHY, 1’b1: external
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* PHY
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@@ -145,7 +145,7 @@ extern "C" {
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/** USB_SERIAL_JTAG_TEST_REG register
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* USB_SERIAL_JTAG_TEST_REG.
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*/
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-#define USB_SERIAL_JTAG_TEST_REG (SOC_DPORT_USB_BASE + 0x1c)
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+#define USB_SERIAL_JTAG_TEST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x1c)
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/* USB_SERIAL_JTAG_TEST_ENABLE : R/W; bitpos: [0]; default: 0;
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* Enable test of the USB
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* pad
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@@ -182,7 +182,7 @@ extern "C" {
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/** USB_SERIAL_JTAG_MISC_CONF_REG register
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* USB_SERIAL_JTAG_MISC_CONF_REG.
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*/
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-#define USB_SERIAL_JTAG_MISC_CONF_REG (SOC_DPORT_USB_BASE + 0x44)
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+#define USB_SERIAL_JTAG_MISC_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x44)
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/* USB_SERIAL_JTAG_CLK_EN : R/W; bitpos: [0]; default: 0;
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* 1'h1: Force clock on for register. 1'h0: Support clock only when
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* application writes
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@@ -196,7 +196,7 @@ extern "C" {
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/** USB_SERIAL_JTAG_MEM_CONF_REG register
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* USB_SERIAL_JTAG_MEM_CONF_REG.
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*/
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-#define USB_SERIAL_JTAG_MEM_CONF_REG (SOC_DPORT_USB_BASE + 0x48)
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+#define USB_SERIAL_JTAG_MEM_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x48)
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/* USB_SERIAL_JTAG_USB_MEM_PD : R/W; bitpos: [0]; default: 0;
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* 1: power down usb
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* memory.
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@@ -220,7 +220,7 @@ extern "C" {
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/** USB_SERIAL_JTAG_EP1_CONF_REG register
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* USB_SERIAL_JTAG_EP1_CONF_REG.
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*/
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-#define USB_SERIAL_JTAG_EP1_CONF_REG (SOC_DPORT_USB_BASE + 0x4)
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+#define USB_SERIAL_JTAG_EP1_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x4)
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/* USB_SERIAL_JTAG_WR_DONE : WT; bitpos: [0]; default: 0;
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* Set this bit to indicate writing byte data to UART Tx FIFO is done.
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* This bit then stays 0 until data in UART Tx FIFO is read by the USB
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@@ -252,7 +252,7 @@ extern "C" {
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/** USB_SERIAL_JTAG_JFIFO_ST_REG register
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* USB_SERIAL_JTAG_JFIFO_ST_REG.
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*/
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-#define USB_SERIAL_JTAG_JFIFO_ST_REG (SOC_DPORT_USB_BASE + 0x20)
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+#define USB_SERIAL_JTAG_JFIFO_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x20)
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/* USB_SERIAL_JTAG_IN_FIFO_CNT : RO; bitpos: [2:0]; default: 0;
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* JTAG in fifo
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* counter.
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@@ -321,7 +321,7 @@ extern "C" {
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/** USB_SERIAL_JTAG_FRAM_NUM_REG register
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* USB_SERIAL_JTAG_FRAM_NUM_REG.
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*/
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-#define USB_SERIAL_JTAG_FRAM_NUM_REG (SOC_DPORT_USB_BASE + 0x24)
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+#define USB_SERIAL_JTAG_FRAM_NUM_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x24)
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/* USB_SERIAL_JTAG_SOF_FRAME_INDEX : RO; bitpos: [11:0]; default: 0;
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* Frame index of received SOF
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* frame.
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@@ -334,7 +334,7 @@ extern "C" {
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/** USB_SERIAL_JTAG_IN_EP0_ST_REG register
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* USB_SERIAL_JTAG_IN_EP0_ST_REG.
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*/
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-#define USB_SERIAL_JTAG_IN_EP0_ST_REG (SOC_DPORT_USB_BASE + 0x28)
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+#define USB_SERIAL_JTAG_IN_EP0_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x28)
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/* USB_SERIAL_JTAG_IN_EP0_STATE : RO; bitpos: [2:0]; default: 1;
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* State of IN Endpoint
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* 0.
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@@ -363,7 +363,7 @@ extern "C" {
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/** USB_SERIAL_JTAG_IN_EP1_ST_REG register
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* USB_SERIAL_JTAG_IN_EP1_ST_REG.
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*/
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-#define USB_SERIAL_JTAG_IN_EP1_ST_REG (SOC_DPORT_USB_BASE + 0x2c)
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+#define USB_SERIAL_JTAG_IN_EP1_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x2c)
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/* USB_SERIAL_JTAG_IN_EP1_STATE : RO; bitpos: [2:0]; default: 1;
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* State of IN Endpoint
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* 1.
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@@ -392,7 +392,7 @@ extern "C" {
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/** USB_SERIAL_JTAG_IN_EP2_ST_REG register
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* USB_SERIAL_JTAG_IN_EP2_ST_REG.
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*/
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-#define USB_SERIAL_JTAG_IN_EP2_ST_REG (SOC_DPORT_USB_BASE + 0x30)
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+#define USB_SERIAL_JTAG_IN_EP2_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x30)
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/* USB_SERIAL_JTAG_IN_EP2_STATE : RO; bitpos: [2:0]; default: 1;
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* State of IN Endpoint
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* 2.
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@@ -421,7 +421,7 @@ extern "C" {
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/** USB_SERIAL_JTAG_IN_EP3_ST_REG register
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* USB_SERIAL_JTAG_IN_EP3_ST_REG.
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*/
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-#define USB_SERIAL_JTAG_IN_EP3_ST_REG (SOC_DPORT_USB_BASE + 0x34)
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+#define USB_SERIAL_JTAG_IN_EP3_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x34)
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/* USB_SERIAL_JTAG_IN_EP3_STATE : RO; bitpos: [2:0]; default: 1;
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* State of IN Endpoint
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* 3.
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@@ -450,7 +450,7 @@ extern "C" {
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/** USB_SERIAL_JTAG_OUT_EP0_ST_REG register
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* USB_SERIAL_JTAG_OUT_EP0_ST_REG.
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*/
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-#define USB_SERIAL_JTAG_OUT_EP0_ST_REG (SOC_DPORT_USB_BASE + 0x38)
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+#define USB_SERIAL_JTAG_OUT_EP0_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x38)
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/* USB_SERIAL_JTAG_OUT_EP0_STATE : RO; bitpos: [2:0]; default: 0;
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* State of OUT Endpoint
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* 0.
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@@ -481,7 +481,7 @@ extern "C" {
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/** USB_SERIAL_JTAG_OUT_EP1_ST_REG register
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* USB_SERIAL_JTAG_OUT_EP1_ST_REG.
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*/
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-#define USB_SERIAL_JTAG_OUT_EP1_ST_REG (SOC_DPORT_USB_BASE + 0x3c)
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+#define USB_SERIAL_JTAG_OUT_EP1_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x3c)
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/* USB_SERIAL_JTAG_OUT_EP1_STATE : RO; bitpos: [2:0]; default: 0;
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* State of OUT Endpoint
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* 1.
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@@ -520,7 +520,7 @@ extern "C" {
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/** USB_SERIAL_JTAG_OUT_EP2_ST_REG register
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* USB_SERIAL_JTAG_OUT_EP2_ST_REG.
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*/
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-#define USB_SERIAL_JTAG_OUT_EP2_ST_REG (SOC_DPORT_USB_BASE + 0x40)
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+#define USB_SERIAL_JTAG_OUT_EP2_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x40)
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/* USB_SERIAL_JTAG_OUT_EP2_STATE : RO; bitpos: [2:0]; default: 0;
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* State of OUT Endpoint
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* 2.
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@@ -554,7 +554,7 @@ extern "C" {
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/** USB_SERIAL_JTAG_INT_RAW_REG register
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* USB_SERIAL_JTAG_INT_RAW_REG.
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*/
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-#define USB_SERIAL_JTAG_INT_RAW_REG (SOC_DPORT_USB_BASE + 0x8)
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+#define USB_SERIAL_JTAG_INT_RAW_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x8)
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/* USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
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* The raw interrupt bit turns to high level when a flush command is
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* received for IN endpoint 2 of
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@@ -661,7 +661,7 @@ extern "C" {
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/** USB_SERIAL_JTAG_INT_ST_REG register
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* USB_SERIAL_JTAG_INT_ST_REG.
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*/
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-#define USB_SERIAL_JTAG_INT_ST_REG (SOC_DPORT_USB_BASE + 0xc)
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+#define USB_SERIAL_JTAG_INT_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0xc)
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/* USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST : RO; bitpos: [0]; default: 0;
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* The raw interrupt status bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT
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* interrupt.
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@@ -767,7 +767,7 @@ extern "C" {
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/** USB_SERIAL_JTAG_INT_ENA_REG register
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* USB_SERIAL_JTAG_INT_ENA_REG.
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*/
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-#define USB_SERIAL_JTAG_INT_ENA_REG (SOC_DPORT_USB_BASE + 0x10)
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+#define USB_SERIAL_JTAG_INT_ENA_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x10)
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/* USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA : R/W; bitpos: [0]; default: 0;
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* The interrupt enable bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT
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* interrupt.
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@@ -872,7 +872,7 @@ extern "C" {
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/** USB_SERIAL_JTAG_INT_CLR_REG register
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* USB_SERIAL_JTAG_INT_CLR_REG.
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*/
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-#define USB_SERIAL_JTAG_INT_CLR_REG (SOC_DPORT_USB_BASE + 0x14)
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+#define USB_SERIAL_JTAG_INT_CLR_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x14)
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/* USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR : WT; bitpos: [0]; default: 0;
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* Set this bit to clear the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT
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* interrupt.
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@@ -976,7 +976,7 @@ extern "C" {
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/** USB_SERIAL_JTAG_DATE_REG register
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* USB_SERIAL_JTAG_DATE_REG.
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*/
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-#define USB_SERIAL_JTAG_DATE_REG (SOC_DPORT_USB_BASE + 0x80)
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+#define USB_SERIAL_JTAG_DATE_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x80)
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/* USB_SERIAL_JTAG_DATE : R/W; bitpos: [32:0]; default: 33583872;
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* register
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* version.
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