Merge branch 'feature/bringup_i2c_for_s3' into 'master'

I2C:  Add support for esp32s3 and add source clock allocator

Closes IDF-2011

See merge request espressif/esp-idf!10923

components/driver/i2c.c

@@ -1,4 +1,4 @@
-// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
+// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
@@ -70,6 +70,7 @@ static const char *I2C_TAG = "i2c";
 #define I2C_DATA_LEN_ERR_STR           "i2c data read length error"
 #define I2C_PSRAM_BUFFER_WARN_STR      "Using buffer allocated from psram"
 #define I2C_LOCK_ERR_STR               "Power lock creation error"
+#define I2C_CLK_FLAG_ERR_STR           "i2c clock choice is invalid, please check flag and frequency"
 #define I2C_FIFO_FULL_THRESH_VAL       (28)
 #define I2C_FIFO_EMPTY_THRESH_VAL      (5)
 #define I2C_IO_INIT_LEVEL              (1)
@@ -92,6 +93,12 @@ static const char *I2C_TAG = "i2c";
     .hw_enabled = false,\
 }
 
+// Freq limitation when using different clock sources
+#define I2C_CLK_LIMIT_REF_TICK            (1 * 1000 * 1000 / 20)    /*!< Limited by REF_TICK, no more than REF_TICK/20*/
+#define I2C_CLK_LIMIT_APB                 (80 * 1000 * 1000 / 20)   /*!< Limited by APB, no more than APB/20*/
+#define I2C_CLK_LIMIT_RTC                 (20 * 1000 * 1000 / 20)   /*!< Limited by RTC, no more than RTC/20*/
+#define I2C_CLK_LIMIT_XTAL                (40 * 1000 * 1000 / 20)   /*!< Limited by RTC, no more than XTAL/20*/
+
 typedef struct {
     i2c_hw_cmd_t hw_cmd;
     uint8_t *data;     /*!< data address */
@@ -161,11 +168,34 @@ typedef struct {
 #endif
 } i2c_context_t;
 
+typedef struct
+{
+    uint8_t character;          /*!< I2C source clock characteristic */
+    uint32_t clk_freq;          /*!< I2C source clock frequency */
+} i2c_clk_alloc_t;
+
 static i2c_context_t i2c_context[I2C_NUM_MAX] = {
     I2C_CONTEX_INIT_DEF(I2C_NUM_0),
     I2C_CONTEX_INIT_DEF(I2C_NUM_1),
 };
 
+// i2c clock characteristic, The order is the same as i2c_sclk_t.
+static i2c_clk_alloc_t i2c_clk_alloc[I2C_SCLK_MAX] = {
+    {0, 0},
+#if SOC_I2C_SUPPORT_APB
+    {0, I2C_CLK_LIMIT_APB},                                                                /*!< I2C APB clock characteristic*/
+#endif
+#if SOC_I2C_SUPPORT_XTAL
+    {0, I2C_CLK_LIMIT_XTAL},                                                               /*!< I2C XTAL characteristic*/
+#endif
+#if SOC_I2C_SUPPORT_RTC
+    {I2C_SCLK_SRC_FLAG_LIGHT_SLEEP, I2C_CLK_LIMIT_RTC},                                    /*!< I2C 20M RTC characteristic*/
+#endif
+#if SOC_I2C_SUPPORT_REF_TICK
+    {I2C_SCLK_SRC_FLAG_AWARE_DFS | I2C_SCLK_SRC_FLAG_LIGHT_SLEEP, I2C_CLK_LIMIT_REF_TICK}, /*!< I2C REF_TICK characteristic*/
+#endif
+};
+
 static i2c_obj_t *p_i2c_obj[I2C_NUM_MAX] = {0};
 static void i2c_isr_handler_default(void *arg);
 static void IRAM_ATTR i2c_master_cmd_begin_static(i2c_port_t i2c_num);
@@ -590,6 +620,21 @@ static esp_err_t i2c_hw_fsm_reset(i2c_port_t i2c_num)
     return ESP_OK;
 }
 
+static i2c_sclk_t i2c_get_clk_src(const i2c_config_t *i2c_conf)
+{
+    for (i2c_sclk_t clk = I2C_SCLK_DEFAULT + 1; clk < I2C_SCLK_MAX; clk++) {
+#if CONFIG_IDF_TARGET_ESP32S3
+        if (clk == I2C_SCLK_RTC) { // RTC clock for s3 is unaccessable now.
+            continue;
+        }
+#endif
+        if (((i2c_conf->clk_flags | i2c_clk_alloc[clk].character) == i2c_clk_alloc[clk].character) && (i2c_conf->master.clk_speed <= i2c_clk_alloc[clk].clk_freq)) {
+            return clk;
+        }
+    }
+    return I2C_SCLK_MAX;     // flag invalid;
+}
+
 esp_err_t i2c_param_config(i2c_port_t i2c_num, const i2c_config_t *i2c_conf)
 {
     I2C_CHECK(i2c_num < I2C_NUM_MAX, I2C_NUM_ERROR_STR, ESP_ERR_INVALID_ARG);
@@ -614,11 +659,13 @@ esp_err_t i2c_param_config(i2c_port_t i2c_num, const i2c_config_t *i2c_conf)
         i2c_hal_set_sda_timing(&(i2c_context[i2c_num].hal), I2C_SLAVE_SDA_SAMPLE_DEFAULT, I2C_SLAVE_SDA_HOLD_DEFAULT);
         i2c_hal_set_tout(&(i2c_context[i2c_num].hal), I2C_SLAVE_TIMEOUT_DEFAULT);
         i2c_hal_enable_slave_rx_it(&(i2c_context[i2c_num].hal));
+        i2c_hal_update_config(&(i2c_context[i2c_num].hal));
     } else {
         i2c_hal_master_init(&(i2c_context[i2c_num].hal), i2c_num);
         //Default, we enable hardware filter
         i2c_hal_set_filter(&(i2c_context[i2c_num].hal), I2C_FILTER_CYC_NUM_DEF);
-        i2c_hal_set_bus_timing(&(i2c_context[i2c_num].hal), i2c_conf->master.clk_speed, I2C_SCLK_APB);
+        I2C_CHECK(i2c_get_clk_src(i2c_conf) != I2C_SCLK_MAX, I2C_CLK_FLAG_ERR_STR, ESP_ERR_INVALID_ARG);
+        i2c_hal_set_bus_timing(&(i2c_context[i2c_num].hal), i2c_conf->master.clk_speed, i2c_get_clk_src(i2c_conf));
     }
     I2C_EXIT_CRITICAL(&(i2c_context[i2c_num].spinlock));
     return ESP_OK;
@@ -882,7 +929,7 @@ esp_err_t i2c_master_start(i2c_cmd_handle_t cmd_handle)
     cmd.hw_cmd.ack_en = 0;
     cmd.hw_cmd.ack_exp = 0;
     cmd.hw_cmd.ack_val = 0;
-    cmd.hw_cmd.op_code = I2C_CMD_RESTART;
+    cmd.hw_cmd.op_code = I2C_LL_CMD_RESTART;
     cmd.hw_cmd.byte_num = 0;
     cmd.data = NULL;
     return i2c_cmd_link_append(cmd_handle, &cmd);
@@ -895,7 +942,7 @@ esp_err_t i2c_master_stop(i2c_cmd_handle_t cmd_handle)
     cmd.hw_cmd.ack_en = 0;
     cmd.hw_cmd.ack_exp = 0;
     cmd.hw_cmd.ack_val = 0;
-    cmd.hw_cmd.op_code = I2C_CMD_STOP;
+    cmd.hw_cmd.op_code = I2C_LL_CMD_STOP;
     cmd.hw_cmd.byte_num = 0;
     cmd.data = NULL;
     return i2c_cmd_link_append(cmd_handle, &cmd);
@@ -916,7 +963,7 @@ esp_err_t i2c_master_write(i2c_cmd_handle_t cmd_handle, const uint8_t *data, siz
         cmd.hw_cmd.ack_en = ack_en;
         cmd.hw_cmd.ack_exp = 0;
         cmd.hw_cmd.ack_val = 0;
-        cmd.hw_cmd.op_code = I2C_CMD_WRITE;
+        cmd.hw_cmd.op_code = I2C_LL_CMD_WRITE;
         cmd.hw_cmd.byte_num = len_tmp;
         cmd.data = (uint8_t*) data + data_offset;
         ret = i2c_cmd_link_append(cmd_handle, &cmd);
@@ -935,7 +982,7 @@ esp_err_t i2c_master_write_byte(i2c_cmd_handle_t cmd_handle, uint8_t data, bool
     cmd.hw_cmd.ack_en = ack_en;
     cmd.hw_cmd.ack_exp = 0;
     cmd.hw_cmd.ack_val = 0;
-    cmd.hw_cmd.op_code = I2C_CMD_WRITE;
+    cmd.hw_cmd.op_code = I2C_LL_CMD_WRITE;
     cmd.hw_cmd.byte_num = 1;
     cmd.data = NULL;
     cmd.byte_cmd = data;
@@ -955,7 +1002,7 @@ static esp_err_t i2c_master_read_static(i2c_cmd_handle_t cmd_handle, uint8_t *da
         cmd.hw_cmd.ack_exp = 0;
         cmd.hw_cmd.ack_val = ack & 0x1;
         cmd.hw_cmd.byte_num = len_tmp;
-        cmd.hw_cmd.op_code = I2C_CMD_READ;
+        cmd.hw_cmd.op_code = I2C_LL_CMD_READ;
         cmd.data = data + data_offset;
         ret = i2c_cmd_link_append(cmd_handle, &cmd);
         data_offset += len_tmp;
@@ -977,7 +1024,7 @@ esp_err_t i2c_master_read_byte(i2c_cmd_handle_t cmd_handle, uint8_t *data, i2c_a
     cmd.hw_cmd.ack_exp = 0;
     cmd.hw_cmd.ack_val = ((ack == I2C_MASTER_LAST_NACK) ? I2C_MASTER_NACK : (ack & 0x1));
     cmd.hw_cmd.byte_num = 1;
-    cmd.hw_cmd.op_code = I2C_CMD_READ;
+    cmd.hw_cmd.op_code = I2C_LL_CMD_READ;
     cmd.data = data;
     return i2c_cmd_link_append(cmd_handle, &cmd);
 }
@@ -1036,12 +1083,12 @@ static void IRAM_ATTR i2c_master_cmd_begin_static(i2c_port_t i2c_num)
         return;
     }
     const i2c_hw_cmd_t hw_end_cmd = {
-        .op_code = I2C_CMD_END
+        .op_code = I2C_LL_CMD_END
     };
     while (p_i2c->cmd_link.head) {
         i2c_cmd_t *cmd = &p_i2c->cmd_link.head->cmd;
         i2c_hw_cmd_t hw_cmd = cmd->hw_cmd;
-        if (cmd->hw_cmd.op_code == I2C_CMD_WRITE) {
+        if (cmd->hw_cmd.op_code == I2C_LL_CMD_WRITE) {
             uint8_t wr_filled = 0;
             uint8_t *write_pr = NULL;
             //TODO: to reduce interrupt number
@@ -1066,7 +1113,7 @@ static void IRAM_ATTR i2c_master_cmd_begin_static(i2c_port_t i2c_num)
             }
             p_i2c->status = I2C_STATUS_WRITE;
             break;
-        } else if (cmd->hw_cmd.op_code == I2C_CMD_READ) {
+        } else if (cmd->hw_cmd.op_code == I2C_LL_CMD_READ) {
             //TODO: to reduce interrupt number
             p_i2c->rx_cnt = cmd->hw_cmd.byte_num > SOC_I2C_FIFO_LEN ? SOC_I2C_FIFO_LEN : cmd->hw_cmd.byte_num;
             cmd->hw_cmd.byte_num -= p_i2c->rx_cnt;
@@ -1086,6 +1133,7 @@ static void IRAM_ATTR i2c_master_cmd_begin_static(i2c_port_t i2c_num)
             break;
         }
     }
+    i2c_hal_update_config(&(i2c_context[i2c_num].hal));
     i2c_hal_trans_start(&(i2c_context[i2c_num].hal));
     return;
 }
@@ -1096,7 +1144,7 @@ static bool is_cmd_link_buffer_internal(i2c_cmd_link_t *link)
 {
     i2c_cmd_link_t *cmd_link = link;
     while (cmd_link != NULL)  {
-        if (cmd_link->cmd.hw_cmd.op_code == I2C_CMD_WRITE || cmd_link->cmd.hw_cmd.op_code == I2C_CMD_READ) {
+        if (cmd_link->cmd.hw_cmd.op_code == I2C_LL_CMD_WRITE || cmd_link->cmd.hw_cmd.op_code == I2C_LL_CMD_READ) {
             if (cmd_link->cmd.data != NULL && !esp_ptr_internal(cmd_link->cmd.data)) {
                 return false;
             }

components/driver/include/driver/i2c.h

@@ -1,4 +1,4 @@
-// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
+// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.

components/driver/test/test_i2c.c

@@ -19,8 +19,6 @@
 #include "driver/periph_ctrl.h"
 #include "esp_rom_gpio.h"
 
-#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3)
-
 #define DATA_LENGTH          512  /*!<Data buffer length for test buffer*/
 #define RW_TEST_LENGTH       129  /*!<Data length for r/w test, any value from 0-DATA_LENGTH*/
 #define DELAY_TIME_BETWEEN_ITEMS_MS   1234 /*!< delay time between different test items */
@@ -75,6 +73,7 @@ static i2c_config_t i2c_master_init(void)
         .master.clk_speed = I2C_MASTER_FREQ_HZ,
         .sda_io_num = I2C_MASTER_SDA_IO,
         .scl_io_num = I2C_MASTER_SCL_IO,
+        .clk_flags = 0,
     };
     return conf_master;
 }
@@ -249,7 +248,7 @@ TEST_CASE("I2C driver memory leaking check", "[i2c]")
     TEST_ASSERT_INT_WITHIN(100, size, esp_get_free_heap_size());
 }
 
-#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2)
+#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2, ESP32S3)
 
 // print the reading buffer
 static void disp_buf(uint8_t *buf, int len)
@@ -590,7 +589,12 @@ TEST_CASE("test i2c_slave_write_buffer is not blocked when ticks_to_wait=0", "[i
 
 TEST_CASE("I2C general API test", "[i2c]")
 {
-    const int i2c_num = 1;
+#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2
+#define I2C_TEST_TIME 0x3ff
+#else
+#define I2C_TEST_TIME 0x1f
+#endif
+    const int i2c_num = 0;
     i2c_config_t conf_master = {
         .mode = I2C_MODE_MASTER,
         .sda_pullup_en = GPIO_PULLUP_ENABLE,
@@ -601,7 +605,7 @@ TEST_CASE("I2C general API test", "[i2c]")
     };
     TEST_ESP_OK(i2c_param_config( i2c_num, &conf_master));
     int time_get0, time_get1;
-    for(int i = 10; i < 0x3ff; i++) {
+    for(int i = 10; i < I2C_TEST_TIME; i++) {
         //set period test
         TEST_ESP_OK(i2c_set_period(i2c_num, i, i));
         TEST_ESP_OK(i2c_get_period(i2c_num, &time_get0, &time_get1));
@@ -625,6 +629,7 @@ TEST_CASE("I2C general API test", "[i2c]")
     }
 }
 
+#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3)
 //Init uart baud rate detection
 static void uart_aut_baud_det_init(int rxd_io_num)
 {

components/hal/esp32/include/hal/i2c_ll.h

@@ -67,6 +67,13 @@ typedef struct {
     uint16_t tout;              /*!< I2C bus timeout period */
 } i2c_clk_cal_t;
 
+// I2C operation mode command
+#define I2C_LL_CMD_RESTART    0    /*!<I2C restart command */
+#define I2C_LL_CMD_WRITE      1    /*!<I2C write command */
+#define I2C_LL_CMD_READ       2    /*!<I2C read command */
+#define I2C_LL_CMD_STOP       3    /*!<I2C stop command */
+#define I2C_LL_CMD_END        4    /*!<I2C end command */
+
 // Get the I2C hardware instance
 #define I2C_LL_GET_HW(i2c_num)        (((i2c_num) == 0) ? &I2C0 : &I2C1)
 // Get the I2C hardware FIFO address
@@ -79,10 +86,8 @@ typedef struct {
 #define I2C_LL_SLAVE_TX_INT           (I2C_TXFIFO_EMPTY_INT_ENA_M)
 // I2C slave RX interrupt bitmap
 #define I2C_LL_SLAVE_RX_INT           (I2C_RXFIFO_FULL_INT_ENA_M | I2C_TRANS_COMPLETE_INT_ENA_M)
-//I2C base clock freq 80M
-#define I2C_BASE_CLK_FREQ             (80000000)
-
-
+// I2C source clock frequency
+#define I2C_LL_CLK_SRC_FREQ(src_clk)  (80*1000*1000)
 /**
  * @brief  Calculate I2C bus frequency
  *
@@ -856,6 +861,18 @@ static inline void i2c_ll_slave_init(i2c_dev_t *hw)
     hw->fifo_conf.fifo_addr_cfg_en = 0;
 }
 
+/**
+ * @brief  Update I2C configuration
+ *
+ * @param  hw Beginning address of the peripheral registers
+ *
+ * @return None
+ */
+static inline void i2c_ll_update(i2c_dev_t *hw)
+{
+    ;// ESP32 do not support
+}
+
 #ifdef __cplusplus
 }
 #endif

components/hal/esp32s2/include/hal/i2c_ll.h

@@ -68,6 +68,13 @@ typedef struct {
     uint16_t tout;              /*!< I2C bus timeout period */
 } i2c_clk_cal_t;
 
+// I2C operation mode command
+#define I2C_LL_CMD_RESTART    0    /*!<I2C restart command */
+#define I2C_LL_CMD_WRITE      1    /*!<I2C write command */
+#define I2C_LL_CMD_READ       2    /*!<I2C read command */
+#define I2C_LL_CMD_STOP       3    /*!<I2C stop command */
+#define I2C_LL_CMD_END        4    /*!<I2C end command */
+
 // Get the I2C hardware instance
 #define I2C_LL_GET_HW(i2c_num)        (((i2c_num) == 0) ? &I2C0 : &I2C1)
 // Get the I2C hardware FIFO address
@@ -80,8 +87,8 @@ typedef struct {
 #define I2C_LL_SLAVE_TX_INT           (I2C_TXFIFO_WM_INT_ENA_M)
 // I2C slave RX interrupt bitmap
 #define I2C_LL_SLAVE_RX_INT           (I2C_RXFIFO_WM_INT_ENA_M | I2C_TRANS_COMPLETE_INT_ENA_M)
-
-
+// I2C source clock
+#define I2C_LL_CLK_SRC_FREQ(src_clk)  (((src_clk) == I2C_SCLK_REF_TICK) ? 1000*1000 : 80*1000*1000); // Another clock is APB clock
 /**
  * @brief  Calculate I2C bus frequency
  *
@@ -781,7 +788,8 @@ static inline void i2c_ll_master_clr_bus(i2c_dev_t *hw)
  */
 static inline void i2c_ll_set_source_clk(i2c_dev_t *hw, i2c_sclk_t src_clk)
 {
-    hw->ctr.ref_always_on = src_clk;
+    // src_clk : (1) for APB_CLK, (0) for REF_CLK
+    hw->ctr.ref_always_on = (src_clk == I2C_SCLK_REF_TICK) ? 0 : 1;
 }
 
 /**
@@ -846,8 +854,6 @@ static inline void i2c_ll_master_init(i2c_dev_t *hw)
     ctrl_reg.ms_mode = 1;
     ctrl_reg.sda_force_out = 1;
     ctrl_reg.scl_force_out = 1;
-    //Disable REF tick;
-    ctrl_reg.ref_always_on = 1;
     hw->ctr.val = ctrl_reg.val;
 }
 
@@ -881,13 +887,23 @@ static inline void i2c_ll_slave_init(i2c_dev_t *hw)
     //Open-drain output via GPIO
     ctrl_reg.sda_force_out = 1;
     ctrl_reg.scl_force_out = 1;
-    //Disable REF tick;
-    ctrl_reg.ref_always_on = 1;
     hw->ctr.val = ctrl_reg.val;
     hw->fifo_conf.fifo_addr_cfg_en = 0;
     hw->scl_stretch_conf.slave_scl_stretch_en = 0;
 }
 
+/**
+ * @brief  Update I2C configuration
+ *
+ * @param  hw Beginning address of the peripheral registers
+ *
+ * @return None
+ */
+static inline void i2c_ll_update(i2c_dev_t *hw)
+{
+    ;// ESP32S2 do not support
+}
+
 #ifdef __cplusplus
 }
 #endif

components/hal/esp32s3/include/hal/i2c_ll.h

@@ -1,4 +1,4 @@
-// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
@@ -23,7 +23,6 @@ extern "C" {
 #endif
 
 #define I2C_LL_INTR_MASK          (0x3fff) /*!< I2C all interrupt bitmap */
-
 /**
  * @brief I2C hardware cmd register filed.
  */
@@ -58,8 +57,10 @@ typedef enum {
  * @brief Data structure for calculating I2C bus timing.
  */
 typedef struct {
+    uint16_t clkm_div;          /*!< I2C core clock devider */
     uint16_t scl_low;           /*!< I2C scl low period */
     uint16_t scl_high;          /*!< I2C scl hight period */
+    uint16_t scl_wait_high;     /*!< I2C scl wait_high period */
     uint16_t sda_hold;          /*!< I2C scl low period */
     uint16_t sda_sample;        /*!< I2C sda sample time */
     uint16_t setup;             /*!< I2C start and stop condition setup period */
@@ -67,24 +68,33 @@ typedef struct {
     uint16_t tout;              /*!< I2C bus timeout period */
 } i2c_clk_cal_t;
 
+// I2C operation mode command
+#define I2C_LL_CMD_RESTART    6    /*!<I2C restart command */
+#define I2C_LL_CMD_WRITE      1    /*!<I2C write command */
+#define I2C_LL_CMD_READ       3    /*!<I2C read command */
+#define I2C_LL_CMD_STOP       2    /*!<I2C stop command */
+#define I2C_LL_CMD_END        4    /*!<I2C end command */
+
 // Get the I2C hardware instance
 #define I2C_LL_GET_HW(i2c_num)        (((i2c_num) == 0) ? &I2C0 : &I2C1)
 // Get the I2C hardware FIFO address
 #define I2C_LL_GET_FIFO_ADDR(i2c_num) (I2C_DATA_APB_REG(i2c_num))
 // I2C master TX interrupt bitmap
-#define I2C_LL_MASTER_TX_INT          (I2C_ACK_ERR_INT_ENA_M|I2C_TIME_OUT_INT_ENA_M|I2C_TRANS_COMPLETE_INT_ENA_M|I2C_ARBITRATION_LOST_INT_ENA_M|I2C_END_DETECT_INT_ENA_M)
+#define I2C_LL_MASTER_TX_INT          (I2C_NACK_INT_ENA_M|I2C_TIME_OUT_INT_ENA_M|I2C_TRANS_COMPLETE_INT_ENA_M|I2C_ARBITRATION_LOST_INT_ENA_M|I2C_END_DETECT_INT_ENA_M)
 // I2C master RX interrupt bitmap
 #define I2C_LL_MASTER_RX_INT          (I2C_TIME_OUT_INT_ENA_M|I2C_TRANS_COMPLETE_INT_ENA_M|I2C_ARBITRATION_LOST_INT_ENA_M|I2C_END_DETECT_INT_ENA_M)
 // I2C slave TX interrupt bitmap
-#define I2C_LL_SLAVE_TX_INT           (I2C_TXFIFO_EMPTY_INT_ENA_M)
+#define I2C_LL_SLAVE_TX_INT           (I2C_TXFIFO_WM_INT_ENA_M)
 // I2C slave RX interrupt bitmap
-#define I2C_LL_SLAVE_RX_INT           (I2C_RXFIFO_FULL_INT_ENA_M | I2C_TRANS_COMPLETE_INT_ENA_M)
-//I2C base clock freq 80M
-#define I2C_BASE_CLK_FREQ             (80000000)
-
+#define I2C_LL_SLAVE_RX_INT           (I2C_RXFIFO_WM_INT_ENA_M | I2C_TRANS_COMPLETE_INT_ENA_M)
+// I2C source clock
+#define I2C_LL_CLK_SRC_FREQ(src_clk)  (((src_clk) == I2C_SCLK_RTC) ? 8*1000*1000 : 40*1000*1000); // Another clock is XTAL clock
 
 /**
  * @brief  Calculate I2C bus frequency
+ *         Note that the clock accuracy is affected by the external pull-up resistor,
+ *         here we try to to calculate a configuration parameter which is close to the required clock.
+ *         But in I2C communication, the clock accuracy is not very concerned.
  *
  * @param  source_clk I2C source clock
  * @param  bus_freq I2C bus frequency
@@ -94,14 +104,35 @@ typedef struct {
  */
 static inline void i2c_ll_cal_bus_clk(uint32_t source_clk, uint32_t bus_freq, i2c_clk_cal_t *clk_cal)
 {
-    uint32_t half_cycle = source_clk / bus_freq / 2;
+    uint32_t clkm_div = source_clk / (bus_freq * 1024) +1;
+    uint32_t sclk_freq = source_clk / clkm_div;
+    uint32_t half_cycle = sclk_freq / bus_freq / 2;
+    //SCL
+    clk_cal->clkm_div = clkm_div;
     clk_cal->scl_low = half_cycle;
-    clk_cal->scl_high = half_cycle;
+    // default, scl_wait_high < scl_high
+    clk_cal->scl_high = (bus_freq <= 50000) ?  half_cycle : (half_cycle / 5 * 4 + 4);
+    clk_cal->scl_wait_high = half_cycle - clk_cal->scl_high;
     clk_cal->sda_hold = half_cycle / 2;
-    clk_cal->sda_sample = clk_cal->scl_high / 2;
+    // scl_wait_high < sda_sample <= scl_high
+    clk_cal->sda_sample = half_cycle / 2;
     clk_cal->setup = half_cycle;
     clk_cal->hold = half_cycle;
-    clk_cal->tout = half_cycle * 20; //default we set the timeout value to 10 bus cycles.
+    //default we set the timeout value to about 10 bus cycles
+    // log(20*half_cycle)/log(2) = log(half_cycle)/log(2) +  log(20)/log(2)
+    clk_cal->tout = (int)(sizeof(half_cycle) * 8 - __builtin_clz(5 * half_cycle)) + 2;
+}
+
+/**
+ * @brief  Update I2C configuration
+ *
+ * @param  hw Beginning address of the peripheral registers
+ *
+ * @return None
+ */
+static inline void i2c_ll_update(i2c_dev_t *hw)
+{
+    hw->ctr.conf_upgate = 1;
 }
 
 /**
@@ -114,8 +145,9 @@ static inline void i2c_ll_cal_bus_clk(uint32_t source_clk, uint32_t bus_freq, i2
  */
 static inline void i2c_ll_set_bus_timing(i2c_dev_t *hw, i2c_clk_cal_t *bus_cfg)
 {
+    hw->clk_conf.sclk_div_num = bus_cfg->clkm_div - 1;
     //scl period
-    hw->scl_low_period.period = bus_cfg->scl_low;
+    hw->scl_low_period.period = bus_cfg->scl_low - 1;
     hw->scl_high_period.period = bus_cfg->scl_high;
     //sda sample
     hw->sda_hold.time = bus_cfg->sda_hold;
@@ -124,9 +156,10 @@ static inline void i2c_ll_set_bus_timing(i2c_dev_t *hw, i2c_clk_cal_t *bus_cfg)
     hw->scl_rstart_setup.time = bus_cfg->setup;
     hw->scl_stop_setup.time = bus_cfg->setup;
     //hold
-    hw->scl_start_hold.time = bus_cfg->hold;
+    hw->scl_start_hold.time = bus_cfg->hold - 1;
     hw->scl_stop_hold.time = bus_cfg->hold;
-    hw->timeout.tout = bus_cfg->tout;
+    hw->timeout.time_out_value = bus_cfg->tout;
+    hw->timeout.time_out_en = 1;
 }
 
 /**
@@ -159,15 +192,17 @@ static inline void i2c_ll_rxfifo_rst(i2c_dev_t *hw)
  * @brief  Configure I2C SCL timing
  *
  * @param  hw Beginning address of the peripheral registers
- * @param  hight_period The I2C SCL hight period (in APB cycle)
- * @param  low_period The I2C SCL low period (in APB cycle)
+ * @param  high_period The I2C SCL hight period (in core clock cycle, hight_period > 2)
+ * @param  low_period The I2C SCL low period (in core clock cycle, low_period > 1)
  *
  * @return None.
  */
-static inline void i2c_ll_set_scl_timing(i2c_dev_t *hw, int hight_period, int low_period)
+static inline void i2c_ll_set_scl_timing(i2c_dev_t *hw, int high_period, int low_period)
 {
-    hw->scl_low_period.period = low_period;
-    hw->scl_high_period.period = hight_period;
+    int high_period_output = high_period - 10; // The rising edge by open-drain output + internal pullup (about 50K) is slow
+    hw->scl_low_period.period = low_period - 1;
+    hw->scl_high_period.period = high_period_output;
+    hw->scl_high_period.scl_wait_high_period = high_period - high_period_output;
 }
 
 /**
@@ -238,13 +273,13 @@ static inline void i2c_ll_set_fifo_mode(i2c_dev_t *hw, bool fifo_mode_en)
  * @brief  Configure I2C timeout
  *
  * @param  hw Beginning address of the peripheral registers
- * @param  tout_num The I2C timeout value needs to be set (in APB cycle)
+ * @param  tout_num The I2C timeout value needs to be set (2^tout in core clock cycle)
  *
  * @return None
  */
 static inline void i2c_ll_set_tout(i2c_dev_t *hw, int tout)
 {
-    hw->timeout.tout = tout;
+    hw->timeout.time_out_value = tout;
 }
 
 /**
@@ -280,23 +315,23 @@ static inline void i2c_ll_write_cmd_reg(i2c_dev_t *hw, i2c_hw_cmd_t cmd, int cmd
  * @brief Configure I2C start timing
  *
  * @param  hw Beginning address of the peripheral registers
- * @param  start_setup The start condition setup period (in APB cycle)
- * @param  start_hold The start condition hold period (in APB cycle)
+ * @param  start_setup The start condition setup period (in core clock cycle)
+ * @param  start_hold The start condition hold period (in core clock cycle)
  *
  * @return None
  */
 static inline void i2c_ll_set_start_timing(i2c_dev_t *hw, int start_setup, int start_hold)
 {
     hw->scl_rstart_setup.time = start_setup;
-    hw->scl_start_hold.time = start_hold;
+    hw->scl_start_hold.time = start_hold - 1;
 }
 
 /**
  * @brief Configure I2C stop timing
  *
  * @param  hw Beginning address of the peripheral registers
- * @param  stop_setup The stop condition setup period (in APB cycle)
- * @param  stop_hold The stop condition hold period (in APB cycle)
+ * @param  stop_setup The stop condition setup period (in core clock cycle)
+ * @param  stop_hold The stop condition hold period (in core clock cycle)
  *
  * @return None
  */
@@ -310,8 +345,8 @@ static inline void i2c_ll_set_stop_timing(i2c_dev_t *hw, int stop_setup, int sto
  * @brief Configure I2C stop timing
  *
  * @param  hw Beginning address of the peripheral registers
- * @param  sda_sample The SDA sample time (in APB cycle)
- * @param  sda_hold The SDA hold time (in APB cycle)
+ * @param  sda_sample The SDA sample time (in core clock cycle)
+ * @param  sda_hold The SDA hold time (in core clock cycle)
  *
  * @return None
  */
@@ -331,7 +366,7 @@ static inline void i2c_ll_set_sda_timing(i2c_dev_t *hw, int sda_sample, int sda_
  */
 static inline void i2c_ll_set_txfifo_empty_thr(i2c_dev_t *hw, uint8_t empty_thr)
 {
-    hw->fifo_conf.tx_fifo_empty_thrhd = empty_thr;
+    hw->fifo_conf.tx_fifo_wm_thrhd = empty_thr;
 }
 
 /**
@@ -344,7 +379,7 @@ static inline void i2c_ll_set_txfifo_empty_thr(i2c_dev_t *hw, uint8_t empty_thr)
  */
 static inline void i2c_ll_set_rxfifo_full_thr(i2c_dev_t *hw, uint8_t full_thr)
 {
-    hw->fifo_conf.rx_fifo_full_thrhd = full_thr;
+    hw->fifo_conf.rx_fifo_wm_thrhd = full_thr;
 }
 
 /**
@@ -461,7 +496,7 @@ static inline uint32_t i2c_ll_get_txfifo_len(i2c_dev_t *hw)
  */
 static inline uint32_t i2c_ll_get_tout(i2c_dev_t *hw)
 {
-    return hw->timeout.tout;
+    return hw->timeout.time_out_value;
 }
 
 /**
@@ -488,7 +523,7 @@ static inline void i2c_ll_trans_start(i2c_dev_t *hw)
 static inline void i2c_ll_get_start_timing(i2c_dev_t *hw, int *setup_time, int *hold_time)
 {
     *setup_time = hw->scl_rstart_setup.time;
-    *hold_time = hw->scl_start_hold.time;
+    *hold_time = hw->scl_start_hold.time + 1;
 }
 
 /**
@@ -517,8 +552,8 @@ static inline void i2c_ll_get_stop_timing(i2c_dev_t *hw, int *setup_time, int *h
  */
 static inline void i2c_ll_get_scl_timing(i2c_dev_t *hw, int *high_period, int *low_period)
 {
-    *high_period = hw->scl_high_period.period;
-    *low_period = hw->scl_low_period.period;
+    *high_period = hw->scl_high_period.period + hw->scl_high_period.scl_wait_high_period;
+    *low_period = hw->scl_low_period.period + 1;
 }
 
 /**
@@ -532,9 +567,8 @@ static inline void i2c_ll_get_scl_timing(i2c_dev_t *hw, int *high_period, int *l
  */
 static inline void i2c_ll_write_txfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len)
 {
-    uint32_t fifo_addr = (hw == &I2C0) ? 0x6001301c : 0x6002701c;
-    for(int i = 0; i < len; i++) {
-        WRITE_PERI_REG(fifo_addr, ptr[i]);
+    for (int i = 0; i< len; i++) {
+        hw->fifo_data.data = ptr[i];
     }
 }
 
@@ -565,14 +599,14 @@ static inline void i2c_ll_read_rxfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len)
  */
 static inline void i2c_ll_set_filter(i2c_dev_t *hw, uint8_t filter_num)
 {
-    if(filter_num > 0) {
-        hw->scl_filter_cfg.thres = filter_num;
-        hw->sda_filter_cfg.thres = filter_num;
-        hw->scl_filter_cfg.en = 1;
-        hw->sda_filter_cfg.en = 1;
+    if (filter_num > 0) {
+        hw->filter_cfg.scl_thres = filter_num;
+        hw->filter_cfg.sda_thres = filter_num;
+        hw->filter_cfg.scl_en = 1;
+        hw->filter_cfg.sda_en = 1;
     } else {
-        hw->scl_filter_cfg.en = 0;
-        hw->sda_filter_cfg.en = 0;
+        hw->filter_cfg.scl_en = 0;
+        hw->filter_cfg.sda_en = 0;
     }
 }
 
@@ -585,7 +619,7 @@ static inline void i2c_ll_set_filter(i2c_dev_t *hw, uint8_t filter_num)
  */
 static inline uint8_t i2c_ll_get_filter(i2c_dev_t *hw)
 {
-    return hw->sda_filter_cfg.thres;
+    return hw->filter_cfg.scl_thres;
 }
 
 /**
@@ -743,7 +777,7 @@ static inline void i2c_ll_slave_clr_rx_it(i2c_dev_t *hw)
  */
 static inline void i2c_ll_master_fsm_rst(i2c_dev_t *hw)
 {
-   ;//ESP32 do not support
+    hw->ctr.fsm_rst = 1;
 }
 
 /**
@@ -758,7 +792,10 @@ static inline void i2c_ll_master_fsm_rst(i2c_dev_t *hw)
  */
 static inline void i2c_ll_master_clr_bus(i2c_dev_t *hw)
 {
-    ;//ESP32 do not support
+    hw->scl_sp_conf.scl_rst_slv_num = 9;
+    hw->scl_sp_conf.scl_rst_slv_en = 0;
+    hw->ctr.conf_upgate = 1;
+    hw->scl_sp_conf.scl_rst_slv_en = 1;
 }
 
 /**
@@ -771,7 +808,7 @@ static inline void i2c_ll_master_clr_bus(i2c_dev_t *hw)
  */
 static inline void i2c_ll_set_source_clk(i2c_dev_t *hw, i2c_sclk_t src_clk)
 {
-    ;//Not support on ESP32
+    hw->clk_conf.sclk_sel = (src_clk == I2C_SCLK_RTC) ? 1 : 0;
 }
 
 /**
@@ -787,7 +824,7 @@ static inline void i2c_ll_master_get_event(i2c_dev_t *hw, i2c_intr_event_t *even
     typeof(hw->int_status) int_sts = hw->int_status;
     if (int_sts.arbitration_lost) {
         *event = I2C_INTR_EVENT_ARBIT_LOST;
-    } else if (int_sts.ack_err) {
+    } else if (int_sts.nack) {
         *event = I2C_INTR_EVENT_NACK;
     } else if (int_sts.time_out) {
         *event = I2C_INTR_EVENT_TOUT;
@@ -811,11 +848,11 @@ static inline void i2c_ll_master_get_event(i2c_dev_t *hw, i2c_intr_event_t *even
 static inline void i2c_ll_slave_get_event(i2c_dev_t *hw, i2c_intr_event_t *event)
 {
     typeof(hw->int_status) int_sts = hw->int_status;
-    if (int_sts.tx_fifo_empty) {
+    if (int_sts.tx_fifo_wm) {
         *event = I2C_INTR_EVENT_TXFIFO_EMPTY;
     } else if (int_sts.trans_complete) {
         *event = I2C_INTR_EVENT_TRANS_DONE;
-    } else if (int_sts.rx_fifo_full) {
+    } else if (int_sts.rx_fifo_wm) {
         *event = I2C_INTR_EVENT_RXFIFO_FULL;
     } else {
         *event = I2C_INTR_EVENT_ERR;
@@ -834,6 +871,7 @@ static inline void i2c_ll_master_init(i2c_dev_t *hw)
     typeof(hw->ctr) ctrl_reg;
     ctrl_reg.val = 0;
     ctrl_reg.ms_mode = 1;
+    ctrl_reg.clk_en = 1;
     ctrl_reg.sda_force_out = 1;
     ctrl_reg.scl_force_out = 1;
     hw->ctr.val = ctrl_reg.val;

components/hal/i2c_hal.c

@@ -176,9 +176,11 @@ void i2c_hal_disable_slave_rx_it(i2c_hal_context_t *hal)
 
 void i2c_hal_set_bus_timing(i2c_hal_context_t *hal, uint32_t scl_freq, i2c_sclk_t src_clk)
 {
-    uint32_t sclk = (src_clk == I2C_SCLK_REF_TICK) ? 1000000 : 80000000;
+    i2c_ll_set_source_clk(hal->dev, src_clk);
+    uint32_t sclk = I2C_LL_CLK_SRC_FREQ(src_clk);
     i2c_clk_cal_t clk_cal = {0};
-    i2c_ll_cal_bus_clk(sclk, scl_freq, &clk_cal);
+    uint32_t scl_hw_freq = (scl_freq == I2C_CLK_FREQ_MAX) ? (src_clk / 20) : scl_freq; // FREQ_MAX use the highest freq of the chosen clk.
+    i2c_ll_cal_bus_clk(sclk, scl_hw_freq, &clk_cal);
     i2c_ll_set_bus_timing(hal->dev, &clk_cal);
 }
 
@@ -216,3 +218,8 @@ void i2c_hal_master_init(i2c_hal_context_t *hal, int i2c_num)
     i2c_ll_txfifo_rst(hal->dev);
     i2c_ll_rxfifo_rst(hal->dev);
 }
+
+void i2c_hal_update_config(i2c_hal_context_t *hal)
+{
+    i2c_ll_update(hal->dev);
+}

components/hal/include/hal/i2c_hal.h

@@ -522,3 +522,13 @@ void i2c_hal_master_handle_rx_event(i2c_hal_context_t *hal, i2c_intr_event_t *ev
  * @return None
  */
 void i2c_hal_slave_handle_event(i2c_hal_context_t *hal, i2c_intr_event_t *event);
+
+/**
+ * @brief Synchronize I2C status
+ *
+ * @param hal Context of the HAL layer
+ *
+ * @return None
+ *
+ */
+void i2c_hal_update_config(i2c_hal_context_t *hal);

components/hal/include/hal/i2c_types.h

@@ -38,14 +38,6 @@ typedef enum {
     I2C_MASTER_READ,        /*!< I2C read data */
 } i2c_rw_t;
 
-typedef enum{
-    I2C_CMD_RESTART = 0,   /*!<I2C restart command */
-    I2C_CMD_WRITE,         /*!<I2C write command */
-    I2C_CMD_READ,          /*!<I2C read command */
-    I2C_CMD_STOP,          /*!<I2C stop command */
-    I2C_CMD_END            /*!<I2C end command */
-} i2c_opmode_t;
-
 typedef enum {
     I2C_DATA_MODE_MSB_FIRST = 0,  /*!< I2C data msb first */
     I2C_DATA_MODE_LSB_FIRST = 1,  /*!< I2C data lsb first */
@@ -65,11 +57,36 @@ typedef enum {
     I2C_MASTER_ACK_MAX,
 } i2c_ack_type_t;
 
+/**
+ * @brief I2C clock source, sorting from smallest to largest,
+ *        place them in order.
+ *        This can be expanded in the future use.
+ */
 typedef enum {
-    I2C_SCLK_REF_TICK,       /*!< I2C source clock from REF_TICK */
-    I2C_SCLK_APB,            /*!< I2C source clock from APB */
+    I2C_SCLK_DEFAULT = 0,    /*!< I2C source clock not selected*/
+#if SOC_I2C_SUPPORT_APB
+    I2C_SCLK_APB,            /*!< I2C source clock from APB, 80M*/
+#endif
+#if SOC_I2C_SUPPORT_XTAL
+    I2C_SCLK_XTAL,           /*!< I2C source clock from XTAL, 40M */
+#endif
+#if SOC_I2C_SUPPORT_RTC
+    I2C_SCLK_RTC,            /*!< I2C source clock from 8M RTC, 8M */
+#endif
+#if SOC_I2C_SUPPORT_REF_TICK
+    I2C_SCLK_REF_TICK,       /*!< I2C source clock from REF_TICK, 1M */
+#endif
+    I2C_SCLK_MAX,
 } i2c_sclk_t;
 
+// I2C clk flags for users to use, can be expanded in the future.
+#define I2C_SCLK_SRC_FLAG_FOR_NOMAL       (0)         /*!< Any one clock source that is available for the specified frequency may be choosen*/
+#define I2C_SCLK_SRC_FLAG_AWARE_DFS       (1 << 0)    /*!< For REF tick clock, it won't change with APB.*/
+#define I2C_SCLK_SRC_FLAG_LIGHT_SLEEP     (1 << 1)    /*!< For light sleep mode.*/
+
+/// Use the highest speed that is available for the clock source picked by clk_flags
+#define I2C_CLK_FREQ_MAX                  (-1)
+
 /**
  * @brief I2C initialization parameters
  */
@@ -89,8 +106,19 @@ typedef struct{
             uint16_t slave_addr;    /*!< I2C address for slave mode */
         } slave;                    /*!< I2C slave config */
     };
+    uint32_t clk_flags;             /*!< Bitwise of ``I2C_SCLK_SRC_FLAG_**FOR_DFS**`` for clk source choice*/
 } i2c_config_t;
 
+#if CONFIG_IDF_TARGET_ESP32
+typedef enum{
+    I2C_CMD_RESTART = 0,   /*!<I2C restart command */
+    I2C_CMD_WRITE,         /*!<I2C write command */
+    I2C_CMD_READ,          /*!<I2C read command */
+    I2C_CMD_STOP,          /*!<I2C stop command */
+    I2C_CMD_END            /*!<I2C end command */
+} i2c_opmode_t __attribute__((deprecated));
+#endif
+
 #ifdef __cplusplus
 }
 #endif

components/soc/esp32/include/soc/soc_caps.h

@@ -120,6 +120,8 @@
 
 #define SOC_I2C_FIFO_LEN        (32) /*!< I2C hardware FIFO depth */
 
+#define SOC_I2C_SUPPORT_APB     (1)
+
 /*-------------------------- I2S CAPS ----------------------------------------*/
 // ESP32 have 2 I2S
 #define SOC_I2S_NUM                 (2)

components/soc/esp32s2/include/soc/soc_caps.h

@@ -113,6 +113,9 @@
 //ESP32-S2 support hardware clear bus
 #define SOC_I2C_SUPPORT_HW_CLR_BUS  (1)
 
+#define SOC_I2C_SUPPORT_REF_TICK   (1)
+#define SOC_I2C_SUPPORT_APB        (1)
+
 /*-------------------------- I2S CAPS ----------------------------------------*/
 // ESP32-S2 have 2 I2S
 #define SOC_I2S_NUM            (1)

components/soc/esp32s3/include/soc/i2c_caps.h

@@ -28,6 +28,9 @@ extern "C" {
 //ESP32-S3 support hardware clear bus
 #define SOC_I2C_SUPPORT_HW_CLR_BUS  (1)
 
+#define SOC_I2C_SUPPORT_XTAL       (1)
+#define SOC_I2C_SUPPORT_RTC        (1)
+
 #ifdef __cplusplus
 }
 #endif

components/soc/esp32s3/include/soc/i2c_reg.h

@@ -1,4 +1,4 @@
-// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
@@ -19,1051 +19,971 @@ extern "C" {
 
 #include "soc.h"
 
-#define I2C_SCL_LOW_PERIOD_REG(i) (REG_I2C_BASE(i) + 0x0000)
-/* I2C_SCL_LOW_PERIOD : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
-/*description: */
-#define I2C_SCL_LOW_PERIOD 0x00003FFF
-#define I2C_SCL_LOW_PERIOD_M ((I2C_SCL_LOW_PERIOD_V) << (I2C_SCL_LOW_PERIOD_S))
-#define I2C_SCL_LOW_PERIOD_V 0x3FFF
-#define I2C_SCL_LOW_PERIOD_S 0
-
-#define I2C_CTR_REG(i) (REG_I2C_BASE(i) + 0x0004)
-/* I2C_REF_ALWAYS_ON : R/W ;bitpos:[11] ;default: 1'b1 ; */
-/*description: */
-#define I2C_REF_ALWAYS_ON (BIT(11))
-#define I2C_REF_ALWAYS_ON_M (BIT(11))
-#define I2C_REF_ALWAYS_ON_V 0x1
-#define I2C_REF_ALWAYS_ON_S 11
-/* I2C_FSM_RST : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: */
-#define I2C_FSM_RST (BIT(10))
-#define I2C_FSM_RST_M (BIT(10))
-#define I2C_FSM_RST_V 0x1
-#define I2C_FSM_RST_S 10
-/* I2C_ARBITRATION_EN : R/W ;bitpos:[9] ;default: 1'b1 ; */
-/*description: */
-#define I2C_ARBITRATION_EN (BIT(9))
-#define I2C_ARBITRATION_EN_M (BIT(9))
-#define I2C_ARBITRATION_EN_V 0x1
-#define I2C_ARBITRATION_EN_S 9
-/* I2C_CLK_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: */
-#define I2C_CLK_EN (BIT(8))
-#define I2C_CLK_EN_M (BIT(8))
-#define I2C_CLK_EN_V 0x1
-#define I2C_CLK_EN_S 8
-/* I2C_RX_LSB_FIRST : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: */
-#define I2C_RX_LSB_FIRST (BIT(7))
-#define I2C_RX_LSB_FIRST_M (BIT(7))
-#define I2C_RX_LSB_FIRST_V 0x1
-#define I2C_RX_LSB_FIRST_S 7
-/* I2C_TX_LSB_FIRST : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define I2C_TX_LSB_FIRST (BIT(6))
-#define I2C_TX_LSB_FIRST_M (BIT(6))
-#define I2C_TX_LSB_FIRST_V 0x1
-#define I2C_TX_LSB_FIRST_S 6
-/* I2C_TRANS_START : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define I2C_TRANS_START (BIT(5))
-#define I2C_TRANS_START_M (BIT(5))
-#define I2C_TRANS_START_V 0x1
-#define I2C_TRANS_START_S 5
-/* I2C_MS_MODE : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define I2C_MS_MODE (BIT(4))
-#define I2C_MS_MODE_M (BIT(4))
-#define I2C_MS_MODE_V 0x1
-#define I2C_MS_MODE_S 4
-/* I2C_ACK_LEVEL : R/W ;bitpos:[3] ;default: 1'b1 ; */
-/*description: */
-#define I2C_ACK_LEVEL (BIT(3))
-#define I2C_ACK_LEVEL_M (BIT(3))
-#define I2C_ACK_LEVEL_V 0x1
-#define I2C_ACK_LEVEL_S 3
-/* I2C_SAMPLE_SCL_LEVEL : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define I2C_SAMPLE_SCL_LEVEL (BIT(2))
-#define I2C_SAMPLE_SCL_LEVEL_M (BIT(2))
-#define I2C_SAMPLE_SCL_LEVEL_V 0x1
-#define I2C_SAMPLE_SCL_LEVEL_S 2
-/* I2C_SCL_FORCE_OUT : R/W ;bitpos:[1] ;default: 1'b1 ; */
-/*description: */
-#define I2C_SCL_FORCE_OUT (BIT(1))
-#define I2C_SCL_FORCE_OUT_M (BIT(1))
-#define I2C_SCL_FORCE_OUT_V 0x1
-#define I2C_SCL_FORCE_OUT_S 1
-/* I2C_SDA_FORCE_OUT : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: */
-#define I2C_SDA_FORCE_OUT (BIT(0))
-#define I2C_SDA_FORCE_OUT_M (BIT(0))
-#define I2C_SDA_FORCE_OUT_V 0x1
-#define I2C_SDA_FORCE_OUT_S 0
-
-#define I2C_SR_REG(i) (REG_I2C_BASE(i) + 0x0008)
-/* I2C_SCL_STATE_LAST : RO ;bitpos:[30:28] ;default: 3'b0 ; */
-/*description: */
-#define I2C_SCL_STATE_LAST 0x00000007
-#define I2C_SCL_STATE_LAST_M ((I2C_SCL_STATE_LAST_V) << (I2C_SCL_STATE_LAST_S))
-#define I2C_SCL_STATE_LAST_V 0x7
-#define I2C_SCL_STATE_LAST_S 28
-/* I2C_SCL_MAIN_STATE_LAST : RO ;bitpos:[26:24] ;default: 3'b0 ; */
-/*description: */
-#define I2C_SCL_MAIN_STATE_LAST 0x00000007
-#define I2C_SCL_MAIN_STATE_LAST_M ((I2C_SCL_MAIN_STATE_LAST_V) << (I2C_SCL_MAIN_STATE_LAST_S))
-#define I2C_SCL_MAIN_STATE_LAST_V 0x7
-#define I2C_SCL_MAIN_STATE_LAST_S 24
-/* I2C_TXFIFO_CNT : RO ;bitpos:[23:18] ;default: 6'b0 ; */
-/*description: */
-#define I2C_TXFIFO_CNT 0x0000003F
-#define I2C_TXFIFO_CNT_M ((I2C_TXFIFO_CNT_V) << (I2C_TXFIFO_CNT_S))
-#define I2C_TXFIFO_CNT_V 0x3F
-#define I2C_TXFIFO_CNT_S 18
-/* I2C_RXFIFO_CNT : RO ;bitpos:[13:8] ;default: 6'b0 ; */
-/*description: */
-#define I2C_RXFIFO_CNT 0x0000003F
-#define I2C_RXFIFO_CNT_M ((I2C_RXFIFO_CNT_V) << (I2C_RXFIFO_CNT_S))
-#define I2C_RXFIFO_CNT_V 0x3F
-#define I2C_RXFIFO_CNT_S 8
-/* I2C_BYTE_TRANS : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define I2C_BYTE_TRANS (BIT(6))
-#define I2C_BYTE_TRANS_M (BIT(6))
-#define I2C_BYTE_TRANS_V 0x1
-#define I2C_BYTE_TRANS_S 6
-/* I2C_SLAVE_ADDRESSED : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define I2C_SLAVE_ADDRESSED (BIT(5))
-#define I2C_SLAVE_ADDRESSED_M (BIT(5))
-#define I2C_SLAVE_ADDRESSED_V 0x1
-#define I2C_SLAVE_ADDRESSED_S 5
-/* I2C_BUS_BUSY : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define I2C_BUS_BUSY (BIT(4))
-#define I2C_BUS_BUSY_M (BIT(4))
-#define I2C_BUS_BUSY_V 0x1
-#define I2C_BUS_BUSY_S 4
-/* I2C_ARB_LOST : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define I2C_ARB_LOST (BIT(3))
-#define I2C_ARB_LOST_M (BIT(3))
-#define I2C_ARB_LOST_V 0x1
-#define I2C_ARB_LOST_S 3
-/* I2C_TIME_OUT : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define I2C_TIME_OUT (BIT(2))
-#define I2C_TIME_OUT_M (BIT(2))
-#define I2C_TIME_OUT_V 0x1
-#define I2C_TIME_OUT_S 2
-/* I2C_SLAVE_RW : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define I2C_SLAVE_RW (BIT(1))
-#define I2C_SLAVE_RW_M (BIT(1))
-#define I2C_SLAVE_RW_V 0x1
-#define I2C_SLAVE_RW_S 1
-/* I2C_ACK_REC : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define I2C_ACK_REC (BIT(0))
-#define I2C_ACK_REC_M (BIT(0))
-#define I2C_ACK_REC_V 0x1
-#define I2C_ACK_REC_S 0
-
-#define I2C_TO_REG(i) (REG_I2C_BASE(i) + 0x000c)
-/* I2C_TIME_OUT_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */
-/*description: */
-#define I2C_TIME_OUT_EN (BIT(24))
-#define I2C_TIME_OUT_EN_M (BIT(24))
-#define I2C_TIME_OUT_EN_V 0x1
-#define I2C_TIME_OUT_EN_S 24
-/* I2C_TIME_OUT_REG : R/W ;bitpos:[23:0] ;default: 24'b0 ; */
-/*description: */
-#define I2C_TIME_OUT_REG 0x00FFFFFF
-#define I2C_TIME_OUT_REG_M ((I2C_TIME_OUT_REG_V) << (I2C_TIME_OUT_REG_S))
-#define I2C_TIME_OUT_REG_V 0xFFFFFF
-#define I2C_TIME_OUT_REG_S 0
-
-#define I2C_SLAVE_ADDR_REG(i) (REG_I2C_BASE(i) + 0x0010)
-/* I2C_ADDR_10BIT_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: */
-#define I2C_ADDR_10BIT_EN (BIT(31))
-#define I2C_ADDR_10BIT_EN_M (BIT(31))
-#define I2C_ADDR_10BIT_EN_V 0x1
-#define I2C_ADDR_10BIT_EN_S 31
-/* I2C_SLAVE_ADDR : R/W ;bitpos:[14:0] ;default: 15'b0 ; */
-/*description: */
-#define I2C_SLAVE_ADDR 0x00007FFF
-#define I2C_SLAVE_ADDR_M ((I2C_SLAVE_ADDR_V) << (I2C_SLAVE_ADDR_S))
-#define I2C_SLAVE_ADDR_V 0x7FFF
-#define I2C_SLAVE_ADDR_S 0
-
-#define I2C_RXFIFO_ST_REG(i) (REG_I2C_BASE(i) + 0x0014)
-/* I2C_RXFIFO_INIT_WADDR : RO ;bitpos:[31:27] ;default: 5'b0 ; */
-/*description: */
-#define I2C_RXFIFO_INIT_WADDR 0x0000001F
-#define I2C_RXFIFO_INIT_WADDR_M ((I2C_RXFIFO_INIT_WADDR_V) << (I2C_RXFIFO_INIT_WADDR_S))
-#define I2C_RXFIFO_INIT_WADDR_V 0x1F
-#define I2C_RXFIFO_INIT_WADDR_S 27
-/* I2C_TXFIFO_INIT_RADDR : RO ;bitpos:[26:22] ;default: 5'b0 ; */
-/*description: */
-#define I2C_TXFIFO_INIT_RADDR 0x0000001F
-#define I2C_TXFIFO_INIT_RADDR_M ((I2C_TXFIFO_INIT_RADDR_V) << (I2C_TXFIFO_INIT_RADDR_S))
-#define I2C_TXFIFO_INIT_RADDR_V 0x1F
-#define I2C_TXFIFO_INIT_RADDR_S 22
-/* I2C_TX_UPDATE : WO ;bitpos:[21] ;default: 1'b0 ; */
-/*description: */
-#define I2C_TX_UPDATE (BIT(21))
-#define I2C_TX_UPDATE_M (BIT(21))
-#define I2C_TX_UPDATE_V 0x1
-#define I2C_TX_UPDATE_S 21
-/* I2C_RX_UPDATE : WO ;bitpos:[20] ;default: 1'b0 ; */
-/*description: */
-#define I2C_RX_UPDATE (BIT(20))
-#define I2C_RX_UPDATE_M (BIT(20))
-#define I2C_RX_UPDATE_V 0x1
-#define I2C_RX_UPDATE_S 20
-/* I2C_TXFIFO_END_ADDR : RO ;bitpos:[19:15] ;default: 5'b0 ; */
-/*description: */
-#define I2C_TXFIFO_END_ADDR 0x0000001F
-#define I2C_TXFIFO_END_ADDR_M ((I2C_TXFIFO_END_ADDR_V) << (I2C_TXFIFO_END_ADDR_S))
-#define I2C_TXFIFO_END_ADDR_V 0x1F
-#define I2C_TXFIFO_END_ADDR_S 15
-/* I2C_TXFIFO_START_ADDR : RO ;bitpos:[14:10] ;default: 5'b0 ; */
-/*description: */
-#define I2C_TXFIFO_START_ADDR 0x0000001F
-#define I2C_TXFIFO_START_ADDR_M ((I2C_TXFIFO_START_ADDR_V) << (I2C_TXFIFO_START_ADDR_S))
-#define I2C_TXFIFO_START_ADDR_V 0x1F
-#define I2C_TXFIFO_START_ADDR_S 10
-/* I2C_RXFIFO_END_ADDR : RO ;bitpos:[9:5] ;default: 5'b0 ; */
-/*description: */
-#define I2C_RXFIFO_END_ADDR 0x0000001F
-#define I2C_RXFIFO_END_ADDR_M ((I2C_RXFIFO_END_ADDR_V) << (I2C_RXFIFO_END_ADDR_S))
-#define I2C_RXFIFO_END_ADDR_V 0x1F
-#define I2C_RXFIFO_END_ADDR_S 5
-/* I2C_RXFIFO_START_ADDR : RO ;bitpos:[4:0] ;default: 5'b0 ; */
-/*description: */
-#define I2C_RXFIFO_START_ADDR 0x0000001F
-#define I2C_RXFIFO_START_ADDR_M ((I2C_RXFIFO_START_ADDR_V) << (I2C_RXFIFO_START_ADDR_S))
-#define I2C_RXFIFO_START_ADDR_V 0x1F
-#define I2C_RXFIFO_START_ADDR_S 0
-
-#define I2C_FIFO_CONF_REG(i) (REG_I2C_BASE(i) + 0x0018)
-/* I2C_NONFIFO_TX_THRES : R/W ;bitpos:[25:20] ;default: 6'h15 ; */
-/*description: */
-#define I2C_NONFIFO_TX_THRES 0x0000003F
-#define I2C_NONFIFO_TX_THRES_M ((I2C_NONFIFO_TX_THRES_V) << (I2C_NONFIFO_TX_THRES_S))
-#define I2C_NONFIFO_TX_THRES_V 0x3F
-#define I2C_NONFIFO_TX_THRES_S 20
-/* I2C_NONFIFO_RX_THRES : R/W ;bitpos:[19:14] ;default: 6'h15 ; */
-/*description: */
-#define I2C_NONFIFO_RX_THRES 0x0000003F
-#define I2C_NONFIFO_RX_THRES_M ((I2C_NONFIFO_RX_THRES_V) << (I2C_NONFIFO_RX_THRES_S))
-#define I2C_NONFIFO_RX_THRES_V 0x3F
-#define I2C_NONFIFO_RX_THRES_S 14
-/* I2C_TX_FIFO_RST : R/W ;bitpos:[13] ;default: 1'b0 ; */
-/*description: */
-#define I2C_TX_FIFO_RST (BIT(13))
-#define I2C_TX_FIFO_RST_M (BIT(13))
-#define I2C_TX_FIFO_RST_V 0x1
-#define I2C_TX_FIFO_RST_S 13
-/* I2C_RX_FIFO_RST : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: */
-#define I2C_RX_FIFO_RST (BIT(12))
-#define I2C_RX_FIFO_RST_M (BIT(12))
-#define I2C_RX_FIFO_RST_V 0x1
-#define I2C_RX_FIFO_RST_S 12
-/* I2C_FIFO_ADDR_CFG_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: */
-#define I2C_FIFO_ADDR_CFG_EN (BIT(11))
-#define I2C_FIFO_ADDR_CFG_EN_M (BIT(11))
-#define I2C_FIFO_ADDR_CFG_EN_V 0x1
-#define I2C_FIFO_ADDR_CFG_EN_S 11
-/* I2C_NONFIFO_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: */
-#define I2C_NONFIFO_EN (BIT(10))
-#define I2C_NONFIFO_EN_M (BIT(10))
-#define I2C_NONFIFO_EN_V 0x1
-#define I2C_NONFIFO_EN_S 10
-/* I2C_TXFIFO_EMPTY_THRHD : R/W ;bitpos:[9:5] ;default: 5'h4 ; */
-/*description: */
-#define I2C_TXFIFO_EMPTY_THRHD 0x0000001F
-#define I2C_TXFIFO_EMPTY_THRHD_M ((I2C_TXFIFO_EMPTY_THRHD_V) << (I2C_TXFIFO_EMPTY_THRHD_S))
-#define I2C_TXFIFO_EMPTY_THRHD_V 0x1F
-#define I2C_TXFIFO_EMPTY_THRHD_S 5
-/* I2C_RXFIFO_FULL_THRHD : R/W ;bitpos:[4:0] ;default: 5'hb ; */
-/*description: */
-#define I2C_RXFIFO_FULL_THRHD 0x0000001F
-#define I2C_RXFIFO_FULL_THRHD_M ((I2C_RXFIFO_FULL_THRHD_V) << (I2C_RXFIFO_FULL_THRHD_S))
-#define I2C_RXFIFO_FULL_THRHD_V 0x1F
-#define I2C_RXFIFO_FULL_THRHD_S 0
-
-#define I2C_DATA_APB_REG(i) (0x60013000 + (i)*0x14000 + 0x001c)
-
-#define I2C_DATA_REG(i) (REG_I2C_BASE(i) + 0x001c)
-/* I2C_FIFO_RDATA : RO ;bitpos:[7:0] ;default: 8'b0 ; */
-/*description: */
-#define I2C_FIFO_RDATA 0x000000FF
-#define I2C_FIFO_RDATA_M ((I2C_FIFO_RDATA_V) << (I2C_FIFO_RDATA_S))
-#define I2C_FIFO_RDATA_V 0xFF
-#define I2C_FIFO_RDATA_S 0
-
-#define I2C_INT_RAW_REG(i) (REG_I2C_BASE(i) + 0x0020)
-/* I2C_DET_START_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */
-/*description: */
-#define I2C_DET_START_INT_RAW (BIT(15))
-#define I2C_DET_START_INT_RAW_M (BIT(15))
-#define I2C_DET_START_INT_RAW_V 0x1
-#define I2C_DET_START_INT_RAW_S 15
-/* I2C_SCL_MAIN_ST_TO_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */
-/*description: */
-#define I2C_SCL_MAIN_ST_TO_INT_RAW (BIT(14))
-#define I2C_SCL_MAIN_ST_TO_INT_RAW_M (BIT(14))
-#define I2C_SCL_MAIN_ST_TO_INT_RAW_V 0x1
-#define I2C_SCL_MAIN_ST_TO_INT_RAW_S 14
-/* I2C_SCL_ST_TO_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */
-/*description: */
-#define I2C_SCL_ST_TO_INT_RAW (BIT(13))
-#define I2C_SCL_ST_TO_INT_RAW_M (BIT(13))
-#define I2C_SCL_ST_TO_INT_RAW_V 0x1
-#define I2C_SCL_ST_TO_INT_RAW_S 13
-/* I2C_TX_SEND_EMPTY_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */
-/*description: */
-#define I2C_TX_SEND_EMPTY_INT_RAW (BIT(12))
-#define I2C_TX_SEND_EMPTY_INT_RAW_M (BIT(12))
-#define I2C_TX_SEND_EMPTY_INT_RAW_V 0x1
-#define I2C_TX_SEND_EMPTY_INT_RAW_S 12
-/* I2C_RX_REC_FULL_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */
-/*description: */
-#define I2C_RX_REC_FULL_INT_RAW (BIT(11))
-#define I2C_RX_REC_FULL_INT_RAW_M (BIT(11))
-#define I2C_RX_REC_FULL_INT_RAW_V 0x1
-#define I2C_RX_REC_FULL_INT_RAW_S 11
-/* I2C_ACK_ERR_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: */
-#define I2C_ACK_ERR_INT_RAW (BIT(10))
-#define I2C_ACK_ERR_INT_RAW_M (BIT(10))
-#define I2C_ACK_ERR_INT_RAW_V 0x1
-#define I2C_ACK_ERR_INT_RAW_S 10
-/* I2C_TRANS_START_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: */
-#define I2C_TRANS_START_INT_RAW (BIT(9))
-#define I2C_TRANS_START_INT_RAW_M (BIT(9))
-#define I2C_TRANS_START_INT_RAW_V 0x1
-#define I2C_TRANS_START_INT_RAW_S 9
-/* I2C_TIME_OUT_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: */
-#define I2C_TIME_OUT_INT_RAW (BIT(8))
-#define I2C_TIME_OUT_INT_RAW_M (BIT(8))
-#define I2C_TIME_OUT_INT_RAW_V 0x1
-#define I2C_TIME_OUT_INT_RAW_S 8
-/* I2C_TRANS_COMPLETE_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: */
-#define I2C_TRANS_COMPLETE_INT_RAW (BIT(7))
-#define I2C_TRANS_COMPLETE_INT_RAW_M (BIT(7))
-#define I2C_TRANS_COMPLETE_INT_RAW_V 0x1
-#define I2C_TRANS_COMPLETE_INT_RAW_S 7
-/* I2C_MASTER_TRAN_COMP_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define I2C_MASTER_TRAN_COMP_INT_RAW (BIT(6))
-#define I2C_MASTER_TRAN_COMP_INT_RAW_M (BIT(6))
-#define I2C_MASTER_TRAN_COMP_INT_RAW_V 0x1
-#define I2C_MASTER_TRAN_COMP_INT_RAW_S 6
-/* I2C_ARBITRATION_LOST_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define I2C_ARBITRATION_LOST_INT_RAW (BIT(5))
-#define I2C_ARBITRATION_LOST_INT_RAW_M (BIT(5))
-#define I2C_ARBITRATION_LOST_INT_RAW_V 0x1
-#define I2C_ARBITRATION_LOST_INT_RAW_S 5
-/* I2C_SLAVE_TRAN_COMP_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define I2C_SLAVE_TRAN_COMP_INT_RAW (BIT(4))
-#define I2C_SLAVE_TRAN_COMP_INT_RAW_M (BIT(4))
-#define I2C_SLAVE_TRAN_COMP_INT_RAW_V 0x1
-#define I2C_SLAVE_TRAN_COMP_INT_RAW_S 4
-/* I2C_END_DETECT_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define I2C_END_DETECT_INT_RAW (BIT(3))
-#define I2C_END_DETECT_INT_RAW_M (BIT(3))
-#define I2C_END_DETECT_INT_RAW_V 0x1
-#define I2C_END_DETECT_INT_RAW_S 3
-/* I2C_RXFIFO_OVF_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define I2C_RXFIFO_OVF_INT_RAW (BIT(2))
-#define I2C_RXFIFO_OVF_INT_RAW_M (BIT(2))
-#define I2C_RXFIFO_OVF_INT_RAW_V 0x1
-#define I2C_RXFIFO_OVF_INT_RAW_S 2
-/* I2C_TXFIFO_EMPTY_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define I2C_TXFIFO_EMPTY_INT_RAW (BIT(1))
-#define I2C_TXFIFO_EMPTY_INT_RAW_M (BIT(1))
-#define I2C_TXFIFO_EMPTY_INT_RAW_V 0x1
-#define I2C_TXFIFO_EMPTY_INT_RAW_S 1
-/* I2C_RXFIFO_FULL_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define I2C_RXFIFO_FULL_INT_RAW (BIT(0))
-#define I2C_RXFIFO_FULL_INT_RAW_M (BIT(0))
-#define I2C_RXFIFO_FULL_INT_RAW_V 0x1
-#define I2C_RXFIFO_FULL_INT_RAW_S 0
-
-#define I2C_INT_CLR_REG(i) (REG_I2C_BASE(i) + 0x0024)
-/* I2C_DET_START_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */
-/*description: */
-#define I2C_DET_START_INT_CLR (BIT(15))
-#define I2C_DET_START_INT_CLR_M (BIT(15))
-#define I2C_DET_START_INT_CLR_V 0x1
-#define I2C_DET_START_INT_CLR_S 15
-/* I2C_SCL_MAIN_ST_TO_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */
-/*description: */
-#define I2C_SCL_MAIN_ST_TO_INT_CLR (BIT(14))
-#define I2C_SCL_MAIN_ST_TO_INT_CLR_M (BIT(14))
-#define I2C_SCL_MAIN_ST_TO_INT_CLR_V 0x1
-#define I2C_SCL_MAIN_ST_TO_INT_CLR_S 14
-/* I2C_SCL_ST_TO_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */
-/*description: */
-#define I2C_SCL_ST_TO_INT_CLR (BIT(13))
-#define I2C_SCL_ST_TO_INT_CLR_M (BIT(13))
-#define I2C_SCL_ST_TO_INT_CLR_V 0x1
-#define I2C_SCL_ST_TO_INT_CLR_S 13
-/* I2C_TX_SEND_EMPTY_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */
-/*description: */
-#define I2C_TX_SEND_EMPTY_INT_CLR (BIT(12))
-#define I2C_TX_SEND_EMPTY_INT_CLR_M (BIT(12))
-#define I2C_TX_SEND_EMPTY_INT_CLR_V 0x1
-#define I2C_TX_SEND_EMPTY_INT_CLR_S 12
-/* I2C_RX_REC_FULL_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */
-/*description: */
-#define I2C_RX_REC_FULL_INT_CLR (BIT(11))
-#define I2C_RX_REC_FULL_INT_CLR_M (BIT(11))
-#define I2C_RX_REC_FULL_INT_CLR_V 0x1
-#define I2C_RX_REC_FULL_INT_CLR_S 11
-/* I2C_ACK_ERR_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: */
-#define I2C_ACK_ERR_INT_CLR (BIT(10))
-#define I2C_ACK_ERR_INT_CLR_M (BIT(10))
-#define I2C_ACK_ERR_INT_CLR_V 0x1
-#define I2C_ACK_ERR_INT_CLR_S 10
-/* I2C_TRANS_START_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: */
-#define I2C_TRANS_START_INT_CLR (BIT(9))
-#define I2C_TRANS_START_INT_CLR_M (BIT(9))
-#define I2C_TRANS_START_INT_CLR_V 0x1
-#define I2C_TRANS_START_INT_CLR_S 9
-/* I2C_TIME_OUT_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: */
-#define I2C_TIME_OUT_INT_CLR (BIT(8))
-#define I2C_TIME_OUT_INT_CLR_M (BIT(8))
-#define I2C_TIME_OUT_INT_CLR_V 0x1
-#define I2C_TIME_OUT_INT_CLR_S 8
-/* I2C_TRANS_COMPLETE_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: */
-#define I2C_TRANS_COMPLETE_INT_CLR (BIT(7))
-#define I2C_TRANS_COMPLETE_INT_CLR_M (BIT(7))
-#define I2C_TRANS_COMPLETE_INT_CLR_V 0x1
-#define I2C_TRANS_COMPLETE_INT_CLR_S 7
-/* I2C_MASTER_TRAN_COMP_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define I2C_MASTER_TRAN_COMP_INT_CLR (BIT(6))
-#define I2C_MASTER_TRAN_COMP_INT_CLR_M (BIT(6))
-#define I2C_MASTER_TRAN_COMP_INT_CLR_V 0x1
-#define I2C_MASTER_TRAN_COMP_INT_CLR_S 6
-/* I2C_ARBITRATION_LOST_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define I2C_ARBITRATION_LOST_INT_CLR (BIT(5))
-#define I2C_ARBITRATION_LOST_INT_CLR_M (BIT(5))
-#define I2C_ARBITRATION_LOST_INT_CLR_V 0x1
-#define I2C_ARBITRATION_LOST_INT_CLR_S 5
-/* I2C_SLAVE_TRAN_COMP_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define I2C_SLAVE_TRAN_COMP_INT_CLR (BIT(4))
-#define I2C_SLAVE_TRAN_COMP_INT_CLR_M (BIT(4))
-#define I2C_SLAVE_TRAN_COMP_INT_CLR_V 0x1
-#define I2C_SLAVE_TRAN_COMP_INT_CLR_S 4
-/* I2C_END_DETECT_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define I2C_END_DETECT_INT_CLR (BIT(3))
-#define I2C_END_DETECT_INT_CLR_M (BIT(3))
-#define I2C_END_DETECT_INT_CLR_V 0x1
-#define I2C_END_DETECT_INT_CLR_S 3
-/* I2C_RXFIFO_OVF_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define I2C_RXFIFO_OVF_INT_CLR (BIT(2))
-#define I2C_RXFIFO_OVF_INT_CLR_M (BIT(2))
-#define I2C_RXFIFO_OVF_INT_CLR_V 0x1
-#define I2C_RXFIFO_OVF_INT_CLR_S 2
-/* I2C_TXFIFO_EMPTY_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define I2C_TXFIFO_EMPTY_INT_CLR (BIT(1))
-#define I2C_TXFIFO_EMPTY_INT_CLR_M (BIT(1))
-#define I2C_TXFIFO_EMPTY_INT_CLR_V 0x1
-#define I2C_TXFIFO_EMPTY_INT_CLR_S 1
-/* I2C_RXFIFO_FULL_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define I2C_RXFIFO_FULL_INT_CLR (BIT(0))
-#define I2C_RXFIFO_FULL_INT_CLR_M (BIT(0))
-#define I2C_RXFIFO_FULL_INT_CLR_V 0x1
-#define I2C_RXFIFO_FULL_INT_CLR_S 0
-
-#define I2C_INT_ENA_REG(i) (REG_I2C_BASE(i) + 0x0028)
-/* I2C_DET_START_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: */
-#define I2C_DET_START_INT_ENA (BIT(15))
-#define I2C_DET_START_INT_ENA_M (BIT(15))
-#define I2C_DET_START_INT_ENA_V 0x1
-#define I2C_DET_START_INT_ENA_S 15
-/* I2C_SCL_MAIN_ST_TO_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: */
-#define I2C_SCL_MAIN_ST_TO_INT_ENA (BIT(14))
-#define I2C_SCL_MAIN_ST_TO_INT_ENA_M (BIT(14))
-#define I2C_SCL_MAIN_ST_TO_INT_ENA_V 0x1
-#define I2C_SCL_MAIN_ST_TO_INT_ENA_S 14
-/* I2C_SCL_ST_TO_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */
-/*description: */
-#define I2C_SCL_ST_TO_INT_ENA (BIT(13))
-#define I2C_SCL_ST_TO_INT_ENA_M (BIT(13))
-#define I2C_SCL_ST_TO_INT_ENA_V 0x1
-#define I2C_SCL_ST_TO_INT_ENA_S 13
-/* I2C_TX_SEND_EMPTY_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: */
-#define I2C_TX_SEND_EMPTY_INT_ENA (BIT(12))
-#define I2C_TX_SEND_EMPTY_INT_ENA_M (BIT(12))
-#define I2C_TX_SEND_EMPTY_INT_ENA_V 0x1
-#define I2C_TX_SEND_EMPTY_INT_ENA_S 12
-/* I2C_RX_REC_FULL_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: */
-#define I2C_RX_REC_FULL_INT_ENA (BIT(11))
-#define I2C_RX_REC_FULL_INT_ENA_M (BIT(11))
-#define I2C_RX_REC_FULL_INT_ENA_V 0x1
-#define I2C_RX_REC_FULL_INT_ENA_S 11
-/* I2C_ACK_ERR_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: */
-#define I2C_ACK_ERR_INT_ENA (BIT(10))
-#define I2C_ACK_ERR_INT_ENA_M (BIT(10))
-#define I2C_ACK_ERR_INT_ENA_V 0x1
-#define I2C_ACK_ERR_INT_ENA_S 10
-/* I2C_TRANS_START_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: */
-#define I2C_TRANS_START_INT_ENA (BIT(9))
-#define I2C_TRANS_START_INT_ENA_M (BIT(9))
-#define I2C_TRANS_START_INT_ENA_V 0x1
-#define I2C_TRANS_START_INT_ENA_S 9
-/* I2C_TIME_OUT_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: */
-#define I2C_TIME_OUT_INT_ENA (BIT(8))
-#define I2C_TIME_OUT_INT_ENA_M (BIT(8))
-#define I2C_TIME_OUT_INT_ENA_V 0x1
-#define I2C_TIME_OUT_INT_ENA_S 8
-/* I2C_TRANS_COMPLETE_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: */
-#define I2C_TRANS_COMPLETE_INT_ENA (BIT(7))
-#define I2C_TRANS_COMPLETE_INT_ENA_M (BIT(7))
-#define I2C_TRANS_COMPLETE_INT_ENA_V 0x1
-#define I2C_TRANS_COMPLETE_INT_ENA_S 7
-/* I2C_MASTER_TRAN_COMP_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define I2C_MASTER_TRAN_COMP_INT_ENA (BIT(6))
-#define I2C_MASTER_TRAN_COMP_INT_ENA_M (BIT(6))
-#define I2C_MASTER_TRAN_COMP_INT_ENA_V 0x1
-#define I2C_MASTER_TRAN_COMP_INT_ENA_S 6
-/* I2C_ARBITRATION_LOST_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define I2C_ARBITRATION_LOST_INT_ENA (BIT(5))
-#define I2C_ARBITRATION_LOST_INT_ENA_M (BIT(5))
-#define I2C_ARBITRATION_LOST_INT_ENA_V 0x1
-#define I2C_ARBITRATION_LOST_INT_ENA_S 5
-/* I2C_SLAVE_TRAN_COMP_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define I2C_SLAVE_TRAN_COMP_INT_ENA (BIT(4))
-#define I2C_SLAVE_TRAN_COMP_INT_ENA_M (BIT(4))
-#define I2C_SLAVE_TRAN_COMP_INT_ENA_V 0x1
-#define I2C_SLAVE_TRAN_COMP_INT_ENA_S 4
-/* I2C_END_DETECT_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define I2C_END_DETECT_INT_ENA (BIT(3))
-#define I2C_END_DETECT_INT_ENA_M (BIT(3))
-#define I2C_END_DETECT_INT_ENA_V 0x1
-#define I2C_END_DETECT_INT_ENA_S 3
-/* I2C_RXFIFO_OVF_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define I2C_RXFIFO_OVF_INT_ENA (BIT(2))
-#define I2C_RXFIFO_OVF_INT_ENA_M (BIT(2))
-#define I2C_RXFIFO_OVF_INT_ENA_V 0x1
-#define I2C_RXFIFO_OVF_INT_ENA_S 2
-/* I2C_TXFIFO_EMPTY_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define I2C_TXFIFO_EMPTY_INT_ENA (BIT(1))
-#define I2C_TXFIFO_EMPTY_INT_ENA_M (BIT(1))
-#define I2C_TXFIFO_EMPTY_INT_ENA_V 0x1
-#define I2C_TXFIFO_EMPTY_INT_ENA_S 1
-/* I2C_RXFIFO_FULL_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define I2C_RXFIFO_FULL_INT_ENA (BIT(0))
-#define I2C_RXFIFO_FULL_INT_ENA_M (BIT(0))
-#define I2C_RXFIFO_FULL_INT_ENA_V 0x1
-#define I2C_RXFIFO_FULL_INT_ENA_S 0
-
-#define I2C_INT_STATUS_REG(i) (REG_I2C_BASE(i) + 0x002c)
-/* I2C_DET_START_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */
-/*description: */
-#define I2C_DET_START_INT_ST (BIT(15))
-#define I2C_DET_START_INT_ST_M (BIT(15))
-#define I2C_DET_START_INT_ST_V 0x1
-#define I2C_DET_START_INT_ST_S 15
-/* I2C_SCL_MAIN_ST_TO_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */
-/*description: */
-#define I2C_SCL_MAIN_ST_TO_INT_ST (BIT(14))
-#define I2C_SCL_MAIN_ST_TO_INT_ST_M (BIT(14))
-#define I2C_SCL_MAIN_ST_TO_INT_ST_V 0x1
-#define I2C_SCL_MAIN_ST_TO_INT_ST_S 14
-/* I2C_SCL_ST_TO_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */
-/*description: */
-#define I2C_SCL_ST_TO_INT_ST (BIT(13))
-#define I2C_SCL_ST_TO_INT_ST_M (BIT(13))
-#define I2C_SCL_ST_TO_INT_ST_V 0x1
-#define I2C_SCL_ST_TO_INT_ST_S 13
-/* I2C_TX_SEND_EMPTY_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */
-/*description: */
-#define I2C_TX_SEND_EMPTY_INT_ST (BIT(12))
-#define I2C_TX_SEND_EMPTY_INT_ST_M (BIT(12))
-#define I2C_TX_SEND_EMPTY_INT_ST_V 0x1
-#define I2C_TX_SEND_EMPTY_INT_ST_S 12
-/* I2C_RX_REC_FULL_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
-/*description: */
-#define I2C_RX_REC_FULL_INT_ST (BIT(11))
-#define I2C_RX_REC_FULL_INT_ST_M (BIT(11))
-#define I2C_RX_REC_FULL_INT_ST_V 0x1
-#define I2C_RX_REC_FULL_INT_ST_S 11
-/* I2C_ACK_ERR_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: */
-#define I2C_ACK_ERR_INT_ST (BIT(10))
-#define I2C_ACK_ERR_INT_ST_M (BIT(10))
-#define I2C_ACK_ERR_INT_ST_V 0x1
-#define I2C_ACK_ERR_INT_ST_S 10
-/* I2C_TRANS_START_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: */
-#define I2C_TRANS_START_INT_ST (BIT(9))
-#define I2C_TRANS_START_INT_ST_M (BIT(9))
-#define I2C_TRANS_START_INT_ST_V 0x1
-#define I2C_TRANS_START_INT_ST_S 9
-/* I2C_TIME_OUT_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: */
-#define I2C_TIME_OUT_INT_ST (BIT(8))
-#define I2C_TIME_OUT_INT_ST_M (BIT(8))
-#define I2C_TIME_OUT_INT_ST_V 0x1
-#define I2C_TIME_OUT_INT_ST_S 8
-/* I2C_TRANS_COMPLETE_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: */
-#define I2C_TRANS_COMPLETE_INT_ST (BIT(7))
-#define I2C_TRANS_COMPLETE_INT_ST_M (BIT(7))
-#define I2C_TRANS_COMPLETE_INT_ST_V 0x1
-#define I2C_TRANS_COMPLETE_INT_ST_S 7
-/* I2C_MASTER_TRAN_COMP_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define I2C_MASTER_TRAN_COMP_INT_ST (BIT(6))
-#define I2C_MASTER_TRAN_COMP_INT_ST_M (BIT(6))
-#define I2C_MASTER_TRAN_COMP_INT_ST_V 0x1
-#define I2C_MASTER_TRAN_COMP_INT_ST_S 6
-/* I2C_ARBITRATION_LOST_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define I2C_ARBITRATION_LOST_INT_ST (BIT(5))
-#define I2C_ARBITRATION_LOST_INT_ST_M (BIT(5))
-#define I2C_ARBITRATION_LOST_INT_ST_V 0x1
-#define I2C_ARBITRATION_LOST_INT_ST_S 5
-/* I2C_SLAVE_TRAN_COMP_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define I2C_SLAVE_TRAN_COMP_INT_ST (BIT(4))
-#define I2C_SLAVE_TRAN_COMP_INT_ST_M (BIT(4))
-#define I2C_SLAVE_TRAN_COMP_INT_ST_V 0x1
-#define I2C_SLAVE_TRAN_COMP_INT_ST_S 4
-/* I2C_END_DETECT_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define I2C_END_DETECT_INT_ST (BIT(3))
-#define I2C_END_DETECT_INT_ST_M (BIT(3))
-#define I2C_END_DETECT_INT_ST_V 0x1
-#define I2C_END_DETECT_INT_ST_S 3
-/* I2C_RXFIFO_OVF_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define I2C_RXFIFO_OVF_INT_ST (BIT(2))
-#define I2C_RXFIFO_OVF_INT_ST_M (BIT(2))
-#define I2C_RXFIFO_OVF_INT_ST_V 0x1
-#define I2C_RXFIFO_OVF_INT_ST_S 2
-/* I2C_TXFIFO_EMPTY_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define I2C_TXFIFO_EMPTY_INT_ST (BIT(1))
-#define I2C_TXFIFO_EMPTY_INT_ST_M (BIT(1))
-#define I2C_TXFIFO_EMPTY_INT_ST_V 0x1
-#define I2C_TXFIFO_EMPTY_INT_ST_S 1
-/* I2C_RXFIFO_FULL_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define I2C_RXFIFO_FULL_INT_ST (BIT(0))
-#define I2C_RXFIFO_FULL_INT_ST_M (BIT(0))
-#define I2C_RXFIFO_FULL_INT_ST_V 0x1
-#define I2C_RXFIFO_FULL_INT_ST_S 0
-
-#define I2C_SDA_HOLD_REG(i) (REG_I2C_BASE(i) + 0x0030)
-/* I2C_SDA_HOLD_TIME : R/W ;bitpos:[9:0] ;default: 10'b0 ; */
-/*description: */
-#define I2C_SDA_HOLD_TIME 0x000003FF
-#define I2C_SDA_HOLD_TIME_M ((I2C_SDA_HOLD_TIME_V) << (I2C_SDA_HOLD_TIME_S))
-#define I2C_SDA_HOLD_TIME_V 0x3FF
-#define I2C_SDA_HOLD_TIME_S 0
-
-#define I2C_SDA_SAMPLE_REG(i) (REG_I2C_BASE(i) + 0x0034)
-/* I2C_SDA_SAMPLE_TIME : R/W ;bitpos:[9:0] ;default: 10'b0 ; */
-/*description: */
-#define I2C_SDA_SAMPLE_TIME 0x000003FF
-#define I2C_SDA_SAMPLE_TIME_M ((I2C_SDA_SAMPLE_TIME_V) << (I2C_SDA_SAMPLE_TIME_S))
-#define I2C_SDA_SAMPLE_TIME_V 0x3FF
-#define I2C_SDA_SAMPLE_TIME_S 0
-
-#define I2C_SCL_HIGH_PERIOD_REG(i) (REG_I2C_BASE(i) + 0x0038)
-/* I2C_SCL_WAIT_HIGH_PERIOD : R/W ;bitpos:[27:14] ;default: 14'b0 ; */
-/*description: */
-#define I2C_SCL_WAIT_HIGH_PERIOD 0x00003FFF
-#define I2C_SCL_WAIT_HIGH_PERIOD_M ((I2C_SCL_WAIT_HIGH_PERIOD_V) << (I2C_SCL_WAIT_HIGH_PERIOD_S))
-#define I2C_SCL_WAIT_HIGH_PERIOD_V 0x3FFF
-#define I2C_SCL_WAIT_HIGH_PERIOD_S 14
-/* I2C_SCL_HIGH_PERIOD : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
-/*description: */
-#define I2C_SCL_HIGH_PERIOD 0x00003FFF
-#define I2C_SCL_HIGH_PERIOD_M ((I2C_SCL_HIGH_PERIOD_V) << (I2C_SCL_HIGH_PERIOD_S))
-#define I2C_SCL_HIGH_PERIOD_V 0x3FFF
-#define I2C_SCL_HIGH_PERIOD_S 0
-
-#define I2C_SCL_START_HOLD_REG(i) (REG_I2C_BASE(i) + 0x0040)
-/* I2C_SCL_START_HOLD_TIME : R/W ;bitpos:[9:0] ;default: 10'b1000 ; */
-/*description: */
-#define I2C_SCL_START_HOLD_TIME 0x000003FF
-#define I2C_SCL_START_HOLD_TIME_M ((I2C_SCL_START_HOLD_TIME_V) << (I2C_SCL_START_HOLD_TIME_S))
-#define I2C_SCL_START_HOLD_TIME_V 0x3FF
-#define I2C_SCL_START_HOLD_TIME_S 0
-
-#define I2C_SCL_RSTART_SETUP_REG(i) (REG_I2C_BASE(i) + 0x0044)
-/* I2C_SCL_RSTART_SETUP_TIME : R/W ;bitpos:[9:0] ;default: 10'b1000 ; */
-/*description: */
-#define I2C_SCL_RSTART_SETUP_TIME 0x000003FF
-#define I2C_SCL_RSTART_SETUP_TIME_M ((I2C_SCL_RSTART_SETUP_TIME_V) << (I2C_SCL_RSTART_SETUP_TIME_S))
-#define I2C_SCL_RSTART_SETUP_TIME_V 0x3FF
-#define I2C_SCL_RSTART_SETUP_TIME_S 0
-
-#define I2C_SCL_STOP_HOLD_REG(i) (REG_I2C_BASE(i) + 0x0048)
-/* I2C_SCL_STOP_HOLD_TIME : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
-/*description: */
-#define I2C_SCL_STOP_HOLD_TIME 0x00003FFF
-#define I2C_SCL_STOP_HOLD_TIME_M ((I2C_SCL_STOP_HOLD_TIME_V) << (I2C_SCL_STOP_HOLD_TIME_S))
-#define I2C_SCL_STOP_HOLD_TIME_V 0x3FFF
-#define I2C_SCL_STOP_HOLD_TIME_S 0
-
-#define I2C_SCL_STOP_SETUP_REG(i) (REG_I2C_BASE(i) + 0x004C)
-/* I2C_SCL_STOP_SETUP_TIME : R/W ;bitpos:[9:0] ;default: 10'b0 ; */
-/*description: */
-#define I2C_SCL_STOP_SETUP_TIME 0x000003FF
-#define I2C_SCL_STOP_SETUP_TIME_M ((I2C_SCL_STOP_SETUP_TIME_V) << (I2C_SCL_STOP_SETUP_TIME_S))
-#define I2C_SCL_STOP_SETUP_TIME_V 0x3FF
-#define I2C_SCL_STOP_SETUP_TIME_S 0
-
-#define I2C_SCL_FILTER_CFG_REG(i) (REG_I2C_BASE(i) + 0x0050)
-/* I2C_SCL_FILTER_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */
-/*description: */
-#define I2C_SCL_FILTER_EN (BIT(3))
-#define I2C_SCL_FILTER_EN_M (BIT(3))
-#define I2C_SCL_FILTER_EN_V 0x1
-#define I2C_SCL_FILTER_EN_S 3
-/* I2C_SCL_FILTER_THRES : R/W ;bitpos:[2:0] ;default: 3'b0 ; */
-/*description: */
-#define I2C_SCL_FILTER_THRES 0x00000007
-#define I2C_SCL_FILTER_THRES_M ((I2C_SCL_FILTER_THRES_V) << (I2C_SCL_FILTER_THRES_S))
-#define I2C_SCL_FILTER_THRES_V 0x7
-#define I2C_SCL_FILTER_THRES_S 0
-
-#define I2C_SDA_FILTER_CFG_REG(i) (REG_I2C_BASE(i) + 0x0054)
-/* I2C_SDA_FILTER_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */
-/*description: */
-#define I2C_SDA_FILTER_EN (BIT(3))
-#define I2C_SDA_FILTER_EN_M (BIT(3))
-#define I2C_SDA_FILTER_EN_V 0x1
-#define I2C_SDA_FILTER_EN_S 3
-/* I2C_SDA_FILTER_THRES : R/W ;bitpos:[2:0] ;default: 3'b0 ; */
-/*description: */
-#define I2C_SDA_FILTER_THRES 0x00000007
-#define I2C_SDA_FILTER_THRES_M ((I2C_SDA_FILTER_THRES_V) << (I2C_SDA_FILTER_THRES_S))
-#define I2C_SDA_FILTER_THRES_V 0x7
-#define I2C_SDA_FILTER_THRES_S 0
-
-#define I2C_COMD0_REG(i) (REG_I2C_BASE(i) + 0x0058)
-/* I2C_COMMAND0_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: */
-#define I2C_COMMAND0_DONE (BIT(31))
-#define I2C_COMMAND0_DONE_M (BIT(31))
-#define I2C_COMMAND0_DONE_V 0x1
-#define I2C_COMMAND0_DONE_S 31
-/* I2C_COMMAND0 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
-/*description: */
-#define I2C_COMMAND0 0x00003FFF
-#define I2C_COMMAND0_M ((I2C_COMMAND0_V) << (I2C_COMMAND0_S))
-#define I2C_COMMAND0_V 0x3FFF
-#define I2C_COMMAND0_S 0
-
-#define I2C_COMD1_REG(i) (REG_I2C_BASE(i) + 0x005C)
-/* I2C_COMMAND1_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: */
-#define I2C_COMMAND1_DONE (BIT(31))
-#define I2C_COMMAND1_DONE_M (BIT(31))
-#define I2C_COMMAND1_DONE_V 0x1
-#define I2C_COMMAND1_DONE_S 31
-/* I2C_COMMAND1 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
-/*description: */
-#define I2C_COMMAND1 0x00003FFF
-#define I2C_COMMAND1_M ((I2C_COMMAND1_V) << (I2C_COMMAND1_S))
-#define I2C_COMMAND1_V 0x3FFF
-#define I2C_COMMAND1_S 0
-
-#define I2C_COMD2_REG(i) (REG_I2C_BASE(i) + 0x0060)
-/* I2C_COMMAND2_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: */
-#define I2C_COMMAND2_DONE (BIT(31))
-#define I2C_COMMAND2_DONE_M (BIT(31))
-#define I2C_COMMAND2_DONE_V 0x1
-#define I2C_COMMAND2_DONE_S 31
-/* I2C_COMMAND2 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
-/*description: */
-#define I2C_COMMAND2 0x00003FFF
-#define I2C_COMMAND2_M ((I2C_COMMAND2_V) << (I2C_COMMAND2_S))
-#define I2C_COMMAND2_V 0x3FFF
-#define I2C_COMMAND2_S 0
-
-#define I2C_COMD3_REG(i) (REG_I2C_BASE(i) + 0x0064)
-/* I2C_COMMAND3_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: */
-#define I2C_COMMAND3_DONE (BIT(31))
-#define I2C_COMMAND3_DONE_M (BIT(31))
-#define I2C_COMMAND3_DONE_V 0x1
-#define I2C_COMMAND3_DONE_S 31
-/* I2C_COMMAND3 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
-/*description: */
-#define I2C_COMMAND3 0x00003FFF
-#define I2C_COMMAND3_M ((I2C_COMMAND3_V) << (I2C_COMMAND3_S))
-#define I2C_COMMAND3_V 0x3FFF
-#define I2C_COMMAND3_S 0
-
-#define I2C_COMD4_REG(i) (REG_I2C_BASE(i) + 0x0068)
-/* I2C_COMMAND4_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: */
-#define I2C_COMMAND4_DONE (BIT(31))
-#define I2C_COMMAND4_DONE_M (BIT(31))
-#define I2C_COMMAND4_DONE_V 0x1
-#define I2C_COMMAND4_DONE_S 31
-/* I2C_COMMAND4 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
-/*description: */
-#define I2C_COMMAND4 0x00003FFF
-#define I2C_COMMAND4_M ((I2C_COMMAND4_V) << (I2C_COMMAND4_S))
-#define I2C_COMMAND4_V 0x3FFF
-#define I2C_COMMAND4_S 0
-
-#define I2C_COMD5_REG(i) (REG_I2C_BASE(i) + 0x006C)
-/* I2C_COMMAND5_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: */
-#define I2C_COMMAND5_DONE (BIT(31))
-#define I2C_COMMAND5_DONE_M (BIT(31))
-#define I2C_COMMAND5_DONE_V 0x1
-#define I2C_COMMAND5_DONE_S 31
-/* I2C_COMMAND5 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
-/*description: */
-#define I2C_COMMAND5 0x00003FFF
-#define I2C_COMMAND5_M ((I2C_COMMAND5_V) << (I2C_COMMAND5_S))
-#define I2C_COMMAND5_V 0x3FFF
-#define I2C_COMMAND5_S 0
-
-#define I2C_COMD6_REG(i) (REG_I2C_BASE(i) + 0x0070)
-/* I2C_COMMAND6_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: */
-#define I2C_COMMAND6_DONE (BIT(31))
-#define I2C_COMMAND6_DONE_M (BIT(31))
-#define I2C_COMMAND6_DONE_V 0x1
-#define I2C_COMMAND6_DONE_S 31
-/* I2C_COMMAND6 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
-/*description: */
-#define I2C_COMMAND6 0x00003FFF
-#define I2C_COMMAND6_M ((I2C_COMMAND6_V) << (I2C_COMMAND6_S))
-#define I2C_COMMAND6_V 0x3FFF
-#define I2C_COMMAND6_S 0
-
-#define I2C_COMD7_REG(i) (REG_I2C_BASE(i) + 0x0074)
-/* I2C_COMMAND7_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: */
-#define I2C_COMMAND7_DONE (BIT(31))
-#define I2C_COMMAND7_DONE_M (BIT(31))
-#define I2C_COMMAND7_DONE_V 0x1
-#define I2C_COMMAND7_DONE_S 31
-/* I2C_COMMAND7 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
-/*description: */
-#define I2C_COMMAND7 0x00003FFF
-#define I2C_COMMAND7_M ((I2C_COMMAND7_V) << (I2C_COMMAND7_S))
-#define I2C_COMMAND7_V 0x3FFF
-#define I2C_COMMAND7_S 0
-
-#define I2C_COMD8_REG(i) (REG_I2C_BASE(i) + 0x0078)
-/* I2C_COMMAND8_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: */
-#define I2C_COMMAND8_DONE (BIT(31))
-#define I2C_COMMAND8_DONE_M (BIT(31))
-#define I2C_COMMAND8_DONE_V 0x1
-#define I2C_COMMAND8_DONE_S 31
-/* I2C_COMMAND8 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
-/*description: */
-#define I2C_COMMAND8 0x00003FFF
-#define I2C_COMMAND8_M ((I2C_COMMAND8_V) << (I2C_COMMAND8_S))
-#define I2C_COMMAND8_V 0x3FFF
-#define I2C_COMMAND8_S 0
-
-#define I2C_COMD9_REG(i) (REG_I2C_BASE(i) + 0x007C)
-/* I2C_COMMAND9_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: */
-#define I2C_COMMAND9_DONE (BIT(31))
-#define I2C_COMMAND9_DONE_M (BIT(31))
-#define I2C_COMMAND9_DONE_V 0x1
-#define I2C_COMMAND9_DONE_S 31
-/* I2C_COMMAND9 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
-/*description: */
-#define I2C_COMMAND9 0x00003FFF
-#define I2C_COMMAND9_M ((I2C_COMMAND9_V) << (I2C_COMMAND9_S))
-#define I2C_COMMAND9_V 0x3FFF
-#define I2C_COMMAND9_S 0
-
-#define I2C_COMD10_REG(i) (REG_I2C_BASE(i) + 0x0080)
-/* I2C_COMMAND10_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: */
-#define I2C_COMMAND10_DONE (BIT(31))
-#define I2C_COMMAND10_DONE_M (BIT(31))
-#define I2C_COMMAND10_DONE_V 0x1
-#define I2C_COMMAND10_DONE_S 31
-/* I2C_COMMAND10 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
-/*description: */
-#define I2C_COMMAND10 0x00003FFF
-#define I2C_COMMAND10_M ((I2C_COMMAND10_V) << (I2C_COMMAND10_S))
-#define I2C_COMMAND10_V 0x3FFF
-#define I2C_COMMAND10_S 0
-
-#define I2C_COMD11_REG(i) (REG_I2C_BASE(i) + 0x0084)
-/* I2C_COMMAND11_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: */
-#define I2C_COMMAND11_DONE (BIT(31))
-#define I2C_COMMAND11_DONE_M (BIT(31))
-#define I2C_COMMAND11_DONE_V 0x1
-#define I2C_COMMAND11_DONE_S 31
-/* I2C_COMMAND11 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
-/*description: */
-#define I2C_COMMAND11 0x00003FFF
-#define I2C_COMMAND11_M ((I2C_COMMAND11_V) << (I2C_COMMAND11_S))
-#define I2C_COMMAND11_V 0x3FFF
-#define I2C_COMMAND11_S 0
-
-#define I2C_COMD12_REG(i) (REG_I2C_BASE(i) + 0x0088)
-/* I2C_COMMAND12_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: */
-#define I2C_COMMAND12_DONE (BIT(31))
-#define I2C_COMMAND12_DONE_M (BIT(31))
-#define I2C_COMMAND12_DONE_V 0x1
-#define I2C_COMMAND12_DONE_S 31
-/* I2C_COMMAND12 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
-/*description: */
-#define I2C_COMMAND12 0x00003FFF
-#define I2C_COMMAND12_M ((I2C_COMMAND12_V) << (I2C_COMMAND12_S))
-#define I2C_COMMAND12_V 0x3FFF
-#define I2C_COMMAND12_S 0
-
-#define I2C_COMD13_REG(i) (REG_I2C_BASE(i) + 0x008C)
-/* I2C_COMMAND13_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: */
-#define I2C_COMMAND13_DONE (BIT(31))
-#define I2C_COMMAND13_DONE_M (BIT(31))
-#define I2C_COMMAND13_DONE_V 0x1
-#define I2C_COMMAND13_DONE_S 31
-/* I2C_COMMAND13 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
-/*description: */
-#define I2C_COMMAND13 0x00003FFF
-#define I2C_COMMAND13_M ((I2C_COMMAND13_V) << (I2C_COMMAND13_S))
-#define I2C_COMMAND13_V 0x3FFF
-#define I2C_COMMAND13_S 0
-
-#define I2C_COMD14_REG(i) (REG_I2C_BASE(i) + 0x0090)
-/* I2C_COMMAND14_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: */
-#define I2C_COMMAND14_DONE (BIT(31))
-#define I2C_COMMAND14_DONE_M (BIT(31))
-#define I2C_COMMAND14_DONE_V 0x1
-#define I2C_COMMAND14_DONE_S 31
-/* I2C_COMMAND14 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
-/*description: */
-#define I2C_COMMAND14 0x00003FFF
-#define I2C_COMMAND14_M ((I2C_COMMAND14_V) << (I2C_COMMAND14_S))
-#define I2C_COMMAND14_V 0x3FFF
-#define I2C_COMMAND14_S 0
-
-#define I2C_COMD15_REG(i) (REG_I2C_BASE(i) + 0x0094)
-/* I2C_COMMAND15_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: */
-#define I2C_COMMAND15_DONE (BIT(31))
-#define I2C_COMMAND15_DONE_M (BIT(31))
-#define I2C_COMMAND15_DONE_V 0x1
-#define I2C_COMMAND15_DONE_S 31
-/* I2C_COMMAND15 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
-/*description: */
-#define I2C_COMMAND15 0x00003FFF
-#define I2C_COMMAND15_M ((I2C_COMMAND15_V) << (I2C_COMMAND15_S))
-#define I2C_COMMAND15_V 0x3FFF
-#define I2C_COMMAND15_S 0
-
-#define I2C_SCL_ST_TIME_OUT_REG(i) (REG_I2C_BASE(i) + 0x0098)
-/* I2C_SCL_ST_TO_REG : R/W ;bitpos:[23:0] ;default: 24'h100 ; */
-/*description: */
-#define I2C_SCL_ST_TO_REG 0x00FFFFFF
-#define I2C_SCL_ST_TO_REG_M ((I2C_SCL_ST_TO_REG_V) << (I2C_SCL_ST_TO_REG_S))
-#define I2C_SCL_ST_TO_REG_V 0xFFFFFF
-#define I2C_SCL_ST_TO_REG_S 0
-
-#define I2C_SCL_MAIN_ST_TIME_OUT_REG(i) (REG_I2C_BASE(i) + 0x009c)
-/* I2C_SCL_MAIN_ST_TO_REG : R/W ;bitpos:[23:0] ;default: 24'h100 ; */
-/*description: */
-#define I2C_SCL_MAIN_ST_TO_REG 0x00FFFFFF
-#define I2C_SCL_MAIN_ST_TO_REG_M ((I2C_SCL_MAIN_ST_TO_REG_V) << (I2C_SCL_MAIN_ST_TO_REG_S))
-#define I2C_SCL_MAIN_ST_TO_REG_V 0xFFFFFF
-#define I2C_SCL_MAIN_ST_TO_REG_S 0
-
-#define I2C_SCL_SP_CONF_REG(i) (REG_I2C_BASE(i) + 0x00a0)
-/* I2C_SDA_PD_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: */
-#define I2C_SDA_PD_EN (BIT(7))
-#define I2C_SDA_PD_EN_M (BIT(7))
-#define I2C_SDA_PD_EN_V 0x1
-#define I2C_SDA_PD_EN_S 7
-/* I2C_SCL_PD_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define I2C_SCL_PD_EN (BIT(6))
-#define I2C_SCL_PD_EN_M (BIT(6))
-#define I2C_SCL_PD_EN_V 0x1
-#define I2C_SCL_PD_EN_S 6
-/* I2C_SCL_RST_SLV_NUM : R/W ;bitpos:[5:1] ;default: 5'b0 ; */
-/*description: */
-#define I2C_SCL_RST_SLV_NUM 0x0000001F
-#define I2C_SCL_RST_SLV_NUM_M ((I2C_SCL_RST_SLV_NUM_V) << (I2C_SCL_RST_SLV_NUM_S))
-#define I2C_SCL_RST_SLV_NUM_V 0x1F
-#define I2C_SCL_RST_SLV_NUM_S 1
-/* I2C_SCL_RST_SLV_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define I2C_SCL_RST_SLV_EN (BIT(0))
-#define I2C_SCL_RST_SLV_EN_M (BIT(0))
-#define I2C_SCL_RST_SLV_EN_V 0x1
-#define I2C_SCL_RST_SLV_EN_S 0
-
-#define I2C_DATE_REG(i) (REG_I2C_BASE(i) + 0x00F8)
-/* I2C_DATE : R/W ;bitpos:[31:0] ;default: 32'h18073100 ; */
-/*description: */
-#define I2C_DATE 0xFFFFFFFF
-#define I2C_DATE_M ((I2C_DATE_V) << (I2C_DATE_S))
-#define I2C_DATE_V 0xFFFFFFFF
-#define I2C_DATE_S 0
-
-#define I2C_FIFO_START_ADDR_REG(i) (REG_I2C_BASE(i) + 0x0100)
+#define I2C_SCL_LOW_PERIOD_REG(i)          (REG_I2C_BASE(i) + 0x0000)
+        /* I2C_SCL_LOW_PERIOD : R/W ;bitpos:[8:0] ;default: 9'b0 ; */
+        /*description: */
+#define I2C_SCL_LOW_PERIOD  0x000001FF
+#define I2C_SCL_LOW_PERIOD_M  ((I2C_SCL_LOW_PERIOD_V)<<(I2C_SCL_LOW_PERIOD_S))
+#define I2C_SCL_LOW_PERIOD_V  0x1FF
+#define I2C_SCL_LOW_PERIOD_S  0
+
+#define I2C_CTR_REG(i)          (REG_I2C_BASE(i) + 0x0004)
+        /* I2C_CONF_UPGATE : WO ;bitpos:[11] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_CONF_UPGATE  (BIT(11))
+#define I2C_CONF_UPGATE_M  (BIT(11))
+#define I2C_CONF_UPGATE_V  0x1
+#define I2C_CONF_UPGATE_S  11
+        /* I2C_FSM_RST : WO ;bitpos:[10] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_FSM_RST  (BIT(10))
+#define I2C_FSM_RST_M  (BIT(10))
+#define I2C_FSM_RST_V  0x1
+#define I2C_FSM_RST_S  10
+        /* I2C_ARBITRATION_EN : R/W ;bitpos:[9] ;default: 1'b1 ; */
+        /*description: */
+#define I2C_ARBITRATION_EN  (BIT(9))
+#define I2C_ARBITRATION_EN_M  (BIT(9))
+#define I2C_ARBITRATION_EN_V  0x1
+#define I2C_ARBITRATION_EN_S  9
+        /* I2C_CLK_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_CLK_EN  (BIT(8))
+#define I2C_CLK_EN_M  (BIT(8))
+#define I2C_CLK_EN_V  0x1
+#define I2C_CLK_EN_S  8
+        /* I2C_RX_LSB_FIRST : R/W ;bitpos:[7] ;default: 1'h0 ; */
+        /*description: */
+#define I2C_RX_LSB_FIRST  (BIT(7))
+#define I2C_RX_LSB_FIRST_M  (BIT(7))
+#define I2C_RX_LSB_FIRST_V  0x1
+#define I2C_RX_LSB_FIRST_S  7
+        /* I2C_TX_LSB_FIRST : R/W ;bitpos:[6] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_TX_LSB_FIRST  (BIT(6))
+#define I2C_TX_LSB_FIRST_M  (BIT(6))
+#define I2C_TX_LSB_FIRST_V  0x1
+#define I2C_TX_LSB_FIRST_S  6
+        /* I2C_TRANS_START : WO ;bitpos:[5] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_TRANS_START  (BIT(5))
+#define I2C_TRANS_START_M  (BIT(5))
+#define I2C_TRANS_START_V  0x1
+#define I2C_TRANS_START_S  5
+        /* I2C_MS_MODE : R/W ;bitpos:[4] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_MS_MODE  (BIT(4))
+#define I2C_MS_MODE_M  (BIT(4))
+#define I2C_MS_MODE_V  0x1
+#define I2C_MS_MODE_S  4
+        /* I2C_RX_FULL_ACK_LEVEL : R/W ;bitpos:[3] ;default: 1'b1 ; */
+        /*description: */
+#define I2C_RX_FULL_ACK_LEVEL  (BIT(3))
+#define I2C_RX_FULL_ACK_LEVEL_M  (BIT(3))
+#define I2C_RX_FULL_ACK_LEVEL_V  0x1
+#define I2C_RX_FULL_ACK_LEVEL_S  3
+        /* I2C_SAMPLE_SCL_LEVEL : R/W ;bitpos:[2] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_SAMPLE_SCL_LEVEL  (BIT(2))
+#define I2C_SAMPLE_SCL_LEVEL_M  (BIT(2))
+#define I2C_SAMPLE_SCL_LEVEL_V  0x1
+#define I2C_SAMPLE_SCL_LEVEL_S  2
+        /* I2C_SCL_FORCE_OUT : R/W ;bitpos:[1] ;default: 1'b1 ; */
+        /*description: */
+#define I2C_SCL_FORCE_OUT  (BIT(1))
+#define I2C_SCL_FORCE_OUT_M  (BIT(1))
+#define I2C_SCL_FORCE_OUT_V  0x1
+#define I2C_SCL_FORCE_OUT_S  1
+        /* I2C_SDA_FORCE_OUT : R/W ;bitpos:[0] ;default: 1'b1 ; */
+        /*description: */
+#define I2C_SDA_FORCE_OUT  (BIT(0))
+#define I2C_SDA_FORCE_OUT_M  (BIT(0))
+#define I2C_SDA_FORCE_OUT_V  0x1
+#define I2C_SDA_FORCE_OUT_S  0
+
+#define I2C_SR_REG(i)          (REG_I2C_BASE(i) + 0x0008)
+        /* I2C_SCL_STATE_LAST : RO ;bitpos:[30:28] ;default: 3'b0 ; */
+        /*description: */
+#define I2C_SCL_STATE_LAST  0x00000007
+#define I2C_SCL_STATE_LAST_M  ((I2C_SCL_STATE_LAST_V)<<(I2C_SCL_STATE_LAST_S))
+#define I2C_SCL_STATE_LAST_V  0x7
+#define I2C_SCL_STATE_LAST_S  28
+        /* I2C_SCL_MAIN_STATE_LAST : RO ;bitpos:[26:24] ;default: 3'b0 ; */
+        /*description: */
+#define I2C_SCL_MAIN_STATE_LAST  0x00000007
+#define I2C_SCL_MAIN_STATE_LAST_M  ((I2C_SCL_MAIN_STATE_LAST_V)<<(I2C_SCL_MAIN_STATE_LAST_S))
+#define I2C_SCL_MAIN_STATE_LAST_V  0x7
+#define I2C_SCL_MAIN_STATE_LAST_S  24
+        /* I2C_TXFIFO_CNT : RO ;bitpos:[23:18] ;default: 6'b0 ; */
+        /*description: */
+#define I2C_TXFIFO_CNT  0x0000003F
+#define I2C_TXFIFO_CNT_M  ((I2C_TXFIFO_CNT_V)<<(I2C_TXFIFO_CNT_S))
+#define I2C_TXFIFO_CNT_V  0x3F
+#define I2C_TXFIFO_CNT_S  18
+        /* I2C_STRETCH_CAUSE : RO ;bitpos:[15:14] ;default: 2'h3 ; */
+        /*description: */
+#define I2C_STRETCH_CAUSE  0x00000003
+#define I2C_STRETCH_CAUSE_M  ((I2C_STRETCH_CAUSE_V)<<(I2C_STRETCH_CAUSE_S))
+#define I2C_STRETCH_CAUSE_V  0x3
+#define I2C_STRETCH_CAUSE_S  14
+        /* I2C_RXFIFO_CNT : RO ;bitpos:[13:8] ;default: 6'b0 ; */
+        /*description: */
+#define I2C_RXFIFO_CNT  0x0000003F
+#define I2C_RXFIFO_CNT_M  ((I2C_RXFIFO_CNT_V)<<(I2C_RXFIFO_CNT_S))
+#define I2C_RXFIFO_CNT_V  0x3F
+#define I2C_RXFIFO_CNT_S  8
+        /* I2C_SLAVE_ADDRESSED : RO ;bitpos:[5] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_SLAVE_ADDRESSED  (BIT(5))
+#define I2C_SLAVE_ADDRESSED_M  (BIT(5))
+#define I2C_SLAVE_ADDRESSED_V  0x1
+#define I2C_SLAVE_ADDRESSED_S  5
+        /* I2C_BUS_BUSY : RO ;bitpos:[4] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_BUS_BUSY  (BIT(4))
+#define I2C_BUS_BUSY_M  (BIT(4))
+#define I2C_BUS_BUSY_V  0x1
+#define I2C_BUS_BUSY_S  4
+        /* I2C_ARB_LOST : RO ;bitpos:[3] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_ARB_LOST  (BIT(3))
+#define I2C_ARB_LOST_M  (BIT(3))
+#define I2C_ARB_LOST_V  0x1
+#define I2C_ARB_LOST_S  3
+        /* I2C_SLAVE_RW : RO ;bitpos:[1] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_SLAVE_RW  (BIT(1))
+#define I2C_SLAVE_RW_M  (BIT(1))
+#define I2C_SLAVE_RW_V  0x1
+#define I2C_SLAVE_RW_S  1
+        /* I2C_RESP_REC : RO ;bitpos:[0] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_RESP_REC  (BIT(0))
+#define I2C_RESP_REC_M  (BIT(0))
+#define I2C_RESP_REC_V  0x1
+#define I2C_RESP_REC_S  0
+
+#define I2C_TO_REG(i)          (REG_I2C_BASE(i) + 0x000c)
+        /* I2C_TIME_OUT_EN : R/W ;bitpos:[5] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_TIME_OUT_EN  (BIT(5))
+#define I2C_TIME_OUT_EN_M  (BIT(5))
+#define I2C_TIME_OUT_EN_V  0x1
+#define I2C_TIME_OUT_EN_S  5
+        /* I2C_TIME_OUT_VALUE : R/W ;bitpos:[4:0] ;default: 5'h10 ; */
+        /*description: */
+#define I2C_TIME_OUT_REG  0x0000001F
+#define I2C_TIME_OUT_REG_M  ((I2C_TIME_OUT_REG_V)<<(I2C_TIME_OUT_REG_S))
+#define I2C_TIME_OUT_REG_V  0x1F
+#define I2C_TIME_OUT_REG_S  0
+
+#define I2C_SLAVE_ADDR_REG(i)          (REG_I2C_BASE(i) + 0x0010)
+        /* I2C_ADDR_10BIT_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_ADDR_10BIT_EN  (BIT(31))
+#define I2C_ADDR_10BIT_EN_M  (BIT(31))
+#define I2C_ADDR_10BIT_EN_V  0x1
+#define I2C_ADDR_10BIT_EN_S  31
+        /* I2C_SLAVE_ADDR : R/W ;bitpos:[14:0] ;default: 15'b0 ; */
+        /*description: */
+#define I2C_SLAVE_ADDR  0x00007FFF
+#define I2C_SLAVE_ADDR_M  ((I2C_SLAVE_ADDR_V)<<(I2C_SLAVE_ADDR_S))
+#define I2C_SLAVE_ADDR_V  0x7FFF
+#define I2C_SLAVE_ADDR_S  0
+
+#define I2C_FIFO_ST_REG(i)          (REG_I2C_BASE(i) + 0x0014)
+        /* I2C_SLAVE_RW_POINT : RO ;bitpos:[29:22] ;default: 8'b0 ; */
+        /*description: */
+#define I2C_SLAVE_RW_POINT  0x000000FF
+#define I2C_SLAVE_RW_POINT_M  ((I2C_SLAVE_RW_POINT_V)<<(I2C_SLAVE_RW_POINT_S))
+#define I2C_SLAVE_RW_POINT_V  0xFF
+#define I2C_SLAVE_RW_POINT_S  22
+        /* I2C_TXFIFO_WADDR : RO ;bitpos:[19:15] ;default: 5'b0 ; */
+        /*description: */
+#define I2C_TXFIFO_WADDR  0x0000001F
+#define I2C_TXFIFO_WADDR_M  ((I2C_TXFIFO_WADDR_V)<<(I2C_TXFIFO_WADDR_S))
+#define I2C_TXFIFO_WADDR_V  0x1F
+#define I2C_TXFIFO_WADDR_S  15
+        /* I2C_TXFIFO_RADDR : RO ;bitpos:[14:10] ;default: 5'b0 ; */
+        /*description: */
+#define I2C_TXFIFO_RADDR  0x0000001F
+#define I2C_TXFIFO_RADDR_M  ((I2C_TXFIFO_RADDR_V)<<(I2C_TXFIFO_RADDR_S))
+#define I2C_TXFIFO_RADDR_V  0x1F
+#define I2C_TXFIFO_RADDR_S  10
+        /* I2C_RXFIFO_WADDR : RO ;bitpos:[9:5] ;default: 5'b0 ; */
+        /*description: */
+#define I2C_RXFIFO_WADDR  0x0000001F
+#define I2C_RXFIFO_WADDR_M  ((I2C_RXFIFO_WADDR_V)<<(I2C_RXFIFO_WADDR_S))
+#define I2C_RXFIFO_WADDR_V  0x1F
+#define I2C_RXFIFO_WADDR_S  5
+        /* I2C_RXFIFO_RADDR : RO ;bitpos:[4:0] ;default: 5'b0 ; */
+        /*description: */
+#define I2C_RXFIFO_RADDR  0x0000001F
+#define I2C_RXFIFO_RADDR_M  ((I2C_RXFIFO_RADDR_V)<<(I2C_RXFIFO_RADDR_S))
+#define I2C_RXFIFO_RADDR_V  0x1F
+#define I2C_RXFIFO_RADDR_S  0
+
+#define I2C_FIFO_CONF_REG(i)          (REG_I2C_BASE(i) + 0x0018)
+        /* I2C_TX_FIFO_RST : R/W ;bitpos:[13] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_TX_FIFO_RST  (BIT(13))
+#define I2C_TX_FIFO_RST_M  (BIT(13))
+#define I2C_TX_FIFO_RST_V  0x1
+#define I2C_TX_FIFO_RST_S  13
+        /* I2C_RX_FIFO_RST : R/W ;bitpos:[12] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_RX_FIFO_RST  (BIT(12))
+#define I2C_RX_FIFO_RST_M  (BIT(12))
+#define I2C_RX_FIFO_RST_V  0x1
+#define I2C_RX_FIFO_RST_S  12
+        /* I2C_FIFO_ADDR_CFG_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_FIFO_ADDR_CFG_EN  (BIT(11))
+#define I2C_FIFO_ADDR_CFG_EN_M  (BIT(11))
+#define I2C_FIFO_ADDR_CFG_EN_V  0x1
+#define I2C_FIFO_ADDR_CFG_EN_S  11
+        /* I2C_NONFIFO_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_NONFIFO_EN  (BIT(10))
+#define I2C_NONFIFO_EN_M  (BIT(10))
+#define I2C_NONFIFO_EN_V  0x1
+#define I2C_NONFIFO_EN_S  10
+        /* I2C_TXFIFO_WM_THRHD : R/W ;bitpos:[9:5] ;default: 5'h4 ; */
+        /*description: */
+#define I2C_TXFIFO_WM_THRHD  0x0000001F
+#define I2C_TXFIFO_WM_THRHD_M  ((I2C_TXFIFO_WM_THRHD_V)<<(I2C_TXFIFO_WM_THRHD_S))
+#define I2C_TXFIFO_WM_THRHD_V  0x1F
+#define I2C_TXFIFO_WM_THRHD_S  5
+        /* I2C_RXFIFO_WM_THRHD : R/W ;bitpos:[4:0] ;default: 5'hb ; */
+        /*description: */
+#define I2C_RXFIFO_WM_THRHD  0x0000001F
+#define I2C_RXFIFO_WM_THRHD_M  ((I2C_RXFIFO_WM_THRHD_V)<<(I2C_RXFIFO_WM_THRHD_S))
+#define I2C_RXFIFO_WM_THRHD_V  0x1F
+#define I2C_RXFIFO_WM_THRHD_S  0
+
+#define I2C_DATA_REG(i)          (REG_I2C_BASE(i) + 0x001c)
+        /* I2C_FIFO_RDATA : RO ;bitpos:[7:0] ;default: 8'b0 ; */
+        /*description: */
+#define I2C_FIFO_RDATA  0x000000FF
+#define I2C_FIFO_RDATA_M  ((I2C_FIFO_RDATA_V)<<(I2C_FIFO_RDATA_S))
+#define I2C_FIFO_RDATA_V  0xFF
+#define I2C_FIFO_RDATA_S  0
+
+#define I2C_INT_RAW_REG(i)          (REG_I2C_BASE(i) + 0x0020)
+        /* I2C_SLAVE_STRETCH_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_SLAVE_STRETCH_INT_RAW  (BIT(16))
+#define I2C_SLAVE_STRETCH_INT_RAW_M  (BIT(16))
+#define I2C_SLAVE_STRETCH_INT_RAW_V  0x1
+#define I2C_SLAVE_STRETCH_INT_RAW_S  16
+        /* I2C_DET_START_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_DET_START_INT_RAW  (BIT(15))
+#define I2C_DET_START_INT_RAW_M  (BIT(15))
+#define I2C_DET_START_INT_RAW_V  0x1
+#define I2C_DET_START_INT_RAW_S  15
+        /* I2C_SCL_MAIN_ST_TO_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_SCL_MAIN_ST_TO_INT_RAW  (BIT(14))
+#define I2C_SCL_MAIN_ST_TO_INT_RAW_M  (BIT(14))
+#define I2C_SCL_MAIN_ST_TO_INT_RAW_V  0x1
+#define I2C_SCL_MAIN_ST_TO_INT_RAW_S  14
+        /* I2C_SCL_ST_TO_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_SCL_ST_TO_INT_RAW  (BIT(13))
+#define I2C_SCL_ST_TO_INT_RAW_M  (BIT(13))
+#define I2C_SCL_ST_TO_INT_RAW_V  0x1
+#define I2C_SCL_ST_TO_INT_RAW_S  13
+        /* I2C_RXFIFO_UDF_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_RXFIFO_UDF_INT_RAW  (BIT(12))
+#define I2C_RXFIFO_UDF_INT_RAW_M  (BIT(12))
+#define I2C_RXFIFO_UDF_INT_RAW_V  0x1
+#define I2C_RXFIFO_UDF_INT_RAW_S  12
+        /* I2C_TXFIFO_OVF_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_TXFIFO_OVF_INT_RAW  (BIT(11))
+#define I2C_TXFIFO_OVF_INT_RAW_M  (BIT(11))
+#define I2C_TXFIFO_OVF_INT_RAW_V  0x1
+#define I2C_TXFIFO_OVF_INT_RAW_S  11
+        /* I2C_NACK_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_NACK_INT_RAW  (BIT(10))
+#define I2C_NACK_INT_RAW_M  (BIT(10))
+#define I2C_NACK_INT_RAW_V  0x1
+#define I2C_NACK_INT_RAW_S  10
+        /* I2C_TRANS_START_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_TRANS_START_INT_RAW  (BIT(9))
+#define I2C_TRANS_START_INT_RAW_M  (BIT(9))
+#define I2C_TRANS_START_INT_RAW_V  0x1
+#define I2C_TRANS_START_INT_RAW_S  9
+        /* I2C_TIME_OUT_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_TIME_OUT_INT_RAW  (BIT(8))
+#define I2C_TIME_OUT_INT_RAW_M  (BIT(8))
+#define I2C_TIME_OUT_INT_RAW_V  0x1
+#define I2C_TIME_OUT_INT_RAW_S  8
+        /* I2C_TRANS_COMPLETE_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_TRANS_COMPLETE_INT_RAW  (BIT(7))
+#define I2C_TRANS_COMPLETE_INT_RAW_M  (BIT(7))
+#define I2C_TRANS_COMPLETE_INT_RAW_V  0x1
+#define I2C_TRANS_COMPLETE_INT_RAW_S  7
+        /* I2C_MST_TXFIFO_UDF_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_MST_TXFIFO_UDF_INT_RAW  (BIT(6))
+#define I2C_MST_TXFIFO_UDF_INT_RAW_M  (BIT(6))
+#define I2C_MST_TXFIFO_UDF_INT_RAW_V  0x1
+#define I2C_MST_TXFIFO_UDF_INT_RAW_S  6
+        /* I2C_ARBITRATION_LOST_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_ARBITRATION_LOST_INT_RAW  (BIT(5))
+#define I2C_ARBITRATION_LOST_INT_RAW_M  (BIT(5))
+#define I2C_ARBITRATION_LOST_INT_RAW_V  0x1
+#define I2C_ARBITRATION_LOST_INT_RAW_S  5
+        /* I2C_BYTE_TRANS_DONE_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_BYTE_TRANS_DONE_INT_RAW  (BIT(4))
+#define I2C_BYTE_TRANS_DONE_INT_RAW_M  (BIT(4))
+#define I2C_BYTE_TRANS_DONE_INT_RAW_V  0x1
+#define I2C_BYTE_TRANS_DONE_INT_RAW_S  4
+        /* I2C_END_DETECT_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_END_DETECT_INT_RAW  (BIT(3))
+#define I2C_END_DETECT_INT_RAW_M  (BIT(3))
+#define I2C_END_DETECT_INT_RAW_V  0x1
+#define I2C_END_DETECT_INT_RAW_S  3
+        /* I2C_RXFIFO_OVF_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_RXFIFO_OVF_INT_RAW  (BIT(2))
+#define I2C_RXFIFO_OVF_INT_RAW_M  (BIT(2))
+#define I2C_RXFIFO_OVF_INT_RAW_V  0x1
+#define I2C_RXFIFO_OVF_INT_RAW_S  2
+        /* I2C_TXFIFO_WM_INT_RAW : RO ;bitpos:[1] ;default: 1'b1 ; */
+        /*description: */
+#define I2C_TXFIFO_WM_INT_RAW  (BIT(1))
+#define I2C_TXFIFO_WM_INT_RAW_M  (BIT(1))
+#define I2C_TXFIFO_WM_INT_RAW_V  0x1
+#define I2C_TXFIFO_WM_INT_RAW_S  1
+        /* I2C_RXFIFO_WM_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_RXFIFO_WM_INT_RAW  (BIT(0))
+#define I2C_RXFIFO_WM_INT_RAW_M  (BIT(0))
+#define I2C_RXFIFO_WM_INT_RAW_V  0x1
+#define I2C_RXFIFO_WM_INT_RAW_S  0
+
+#define I2C_INT_CLR_REG(i)          (REG_I2C_BASE(i) + 0x0024)
+        /* I2C_SLAVE_STRETCH_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_SLAVE_STRETCH_INT_CLR  (BIT(16))
+#define I2C_SLAVE_STRETCH_INT_CLR_M  (BIT(16))
+#define I2C_SLAVE_STRETCH_INT_CLR_V  0x1
+#define I2C_SLAVE_STRETCH_INT_CLR_S  16
+        /* I2C_DET_START_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_DET_START_INT_CLR  (BIT(15))
+#define I2C_DET_START_INT_CLR_M  (BIT(15))
+#define I2C_DET_START_INT_CLR_V  0x1
+#define I2C_DET_START_INT_CLR_S  15
+        /* I2C_SCL_MAIN_ST_TO_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_SCL_MAIN_ST_TO_INT_CLR  (BIT(14))
+#define I2C_SCL_MAIN_ST_TO_INT_CLR_M  (BIT(14))
+#define I2C_SCL_MAIN_ST_TO_INT_CLR_V  0x1
+#define I2C_SCL_MAIN_ST_TO_INT_CLR_S  14
+        /* I2C_SCL_ST_TO_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_SCL_ST_TO_INT_CLR  (BIT(13))
+#define I2C_SCL_ST_TO_INT_CLR_M  (BIT(13))
+#define I2C_SCL_ST_TO_INT_CLR_V  0x1
+#define I2C_SCL_ST_TO_INT_CLR_S  13
+        /* I2C_RXFIFO_UDF_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_RXFIFO_UDF_INT_CLR  (BIT(12))
+#define I2C_RXFIFO_UDF_INT_CLR_M  (BIT(12))
+#define I2C_RXFIFO_UDF_INT_CLR_V  0x1
+#define I2C_RXFIFO_UDF_INT_CLR_S  12
+        /* I2C_TXFIFO_OVF_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_TXFIFO_OVF_INT_CLR  (BIT(11))
+#define I2C_TXFIFO_OVF_INT_CLR_M  (BIT(11))
+#define I2C_TXFIFO_OVF_INT_CLR_V  0x1
+#define I2C_TXFIFO_OVF_INT_CLR_S  11
+        /* I2C_NACK_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_NACK_INT_CLR  (BIT(10))
+#define I2C_NACK_INT_CLR_M  (BIT(10))
+#define I2C_NACK_INT_CLR_V  0x1
+#define I2C_NACK_INT_CLR_S  10
+        /* I2C_TRANS_START_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_TRANS_START_INT_CLR  (BIT(9))
+#define I2C_TRANS_START_INT_CLR_M  (BIT(9))
+#define I2C_TRANS_START_INT_CLR_V  0x1
+#define I2C_TRANS_START_INT_CLR_S  9
+        /* I2C_TIME_OUT_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_TIME_OUT_INT_CLR  (BIT(8))
+#define I2C_TIME_OUT_INT_CLR_M  (BIT(8))
+#define I2C_TIME_OUT_INT_CLR_V  0x1
+#define I2C_TIME_OUT_INT_CLR_S  8
+        /* I2C_TRANS_COMPLETE_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_TRANS_COMPLETE_INT_CLR  (BIT(7))
+#define I2C_TRANS_COMPLETE_INT_CLR_M  (BIT(7))
+#define I2C_TRANS_COMPLETE_INT_CLR_V  0x1
+#define I2C_TRANS_COMPLETE_INT_CLR_S  7
+        /* I2C_MST_TXFIFO_UDF_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_MST_TXFIFO_UDF_INT_CLR  (BIT(6))
+#define I2C_MST_TXFIFO_UDF_INT_CLR_M  (BIT(6))
+#define I2C_MST_TXFIFO_UDF_INT_CLR_V  0x1
+#define I2C_MST_TXFIFO_UDF_INT_CLR_S  6
+        /* I2C_ARBITRATION_LOST_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_ARBITRATION_LOST_INT_CLR  (BIT(5))
+#define I2C_ARBITRATION_LOST_INT_CLR_M  (BIT(5))
+#define I2C_ARBITRATION_LOST_INT_CLR_V  0x1
+#define I2C_ARBITRATION_LOST_INT_CLR_S  5
+        /* I2C_BYTE_TRANS_DONE_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_BYTE_TRANS_DONE_INT_CLR  (BIT(4))
+#define I2C_BYTE_TRANS_DONE_INT_CLR_M  (BIT(4))
+#define I2C_BYTE_TRANS_DONE_INT_CLR_V  0x1
+#define I2C_BYTE_TRANS_DONE_INT_CLR_S  4
+        /* I2C_END_DETECT_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_END_DETECT_INT_CLR  (BIT(3))
+#define I2C_END_DETECT_INT_CLR_M  (BIT(3))
+#define I2C_END_DETECT_INT_CLR_V  0x1
+#define I2C_END_DETECT_INT_CLR_S  3
+        /* I2C_RXFIFO_OVF_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_RXFIFO_OVF_INT_CLR  (BIT(2))
+#define I2C_RXFIFO_OVF_INT_CLR_M  (BIT(2))
+#define I2C_RXFIFO_OVF_INT_CLR_V  0x1
+#define I2C_RXFIFO_OVF_INT_CLR_S  2
+        /* I2C_TXFIFO_WM_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_TXFIFO_WM_INT_CLR  (BIT(1))
+#define I2C_TXFIFO_WM_INT_CLR_M  (BIT(1))
+#define I2C_TXFIFO_WM_INT_CLR_V  0x1
+#define I2C_TXFIFO_WM_INT_CLR_S  1
+        /* I2C_RXFIFO_WM_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_RXFIFO_WM_INT_CLR  (BIT(0))
+#define I2C_RXFIFO_WM_INT_CLR_M  (BIT(0))
+#define I2C_RXFIFO_WM_INT_CLR_V  0x1
+#define I2C_RXFIFO_WM_INT_CLR_S  0
+
+#define I2C_INT_ENA_REG(i)          (REG_I2C_BASE(i) + 0x0028)
+        /* I2C_SLAVE_STRETCH_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_SLAVE_STRETCH_INT_ENA  (BIT(16))
+#define I2C_SLAVE_STRETCH_INT_ENA_M  (BIT(16))
+#define I2C_SLAVE_STRETCH_INT_ENA_V  0x1
+#define I2C_SLAVE_STRETCH_INT_ENA_S  16
+        /* I2C_DET_START_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_DET_START_INT_ENA  (BIT(15))
+#define I2C_DET_START_INT_ENA_M  (BIT(15))
+#define I2C_DET_START_INT_ENA_V  0x1
+#define I2C_DET_START_INT_ENA_S  15
+        /* I2C_SCL_MAIN_ST_TO_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_SCL_MAIN_ST_TO_INT_ENA  (BIT(14))
+#define I2C_SCL_MAIN_ST_TO_INT_ENA_M  (BIT(14))
+#define I2C_SCL_MAIN_ST_TO_INT_ENA_V  0x1
+#define I2C_SCL_MAIN_ST_TO_INT_ENA_S  14
+        /* I2C_SCL_ST_TO_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_SCL_ST_TO_INT_ENA  (BIT(13))
+#define I2C_SCL_ST_TO_INT_ENA_M  (BIT(13))
+#define I2C_SCL_ST_TO_INT_ENA_V  0x1
+#define I2C_SCL_ST_TO_INT_ENA_S  13
+        /* I2C_RXFIFO_UDF_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_RXFIFO_UDF_INT_ENA  (BIT(12))
+#define I2C_RXFIFO_UDF_INT_ENA_M  (BIT(12))
+#define I2C_RXFIFO_UDF_INT_ENA_V  0x1
+#define I2C_RXFIFO_UDF_INT_ENA_S  12
+        /* I2C_TXFIFO_OVF_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_TXFIFO_OVF_INT_ENA  (BIT(11))
+#define I2C_TXFIFO_OVF_INT_ENA_M  (BIT(11))
+#define I2C_TXFIFO_OVF_INT_ENA_V  0x1
+#define I2C_TXFIFO_OVF_INT_ENA_S  11
+        /* I2C_NACK_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_NACK_INT_ENA  (BIT(10))
+#define I2C_NACK_INT_ENA_M  (BIT(10))
+#define I2C_NACK_INT_ENA_V  0x1
+#define I2C_NACK_INT_ENA_S  10
+        /* I2C_TRANS_START_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_TRANS_START_INT_ENA  (BIT(9))
+#define I2C_TRANS_START_INT_ENA_M  (BIT(9))
+#define I2C_TRANS_START_INT_ENA_V  0x1
+#define I2C_TRANS_START_INT_ENA_S  9
+        /* I2C_TIME_OUT_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_TIME_OUT_INT_ENA  (BIT(8))
+#define I2C_TIME_OUT_INT_ENA_M  (BIT(8))
+#define I2C_TIME_OUT_INT_ENA_V  0x1
+#define I2C_TIME_OUT_INT_ENA_S  8
+        /* I2C_TRANS_COMPLETE_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_TRANS_COMPLETE_INT_ENA  (BIT(7))
+#define I2C_TRANS_COMPLETE_INT_ENA_M  (BIT(7))
+#define I2C_TRANS_COMPLETE_INT_ENA_V  0x1
+#define I2C_TRANS_COMPLETE_INT_ENA_S  7
+        /* I2C_MST_TXFIFO_UDF_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_MST_TXFIFO_UDF_INT_ENA  (BIT(6))
+#define I2C_MST_TXFIFO_UDF_INT_ENA_M  (BIT(6))
+#define I2C_MST_TXFIFO_UDF_INT_ENA_V  0x1
+#define I2C_MST_TXFIFO_UDF_INT_ENA_S  6
+        /* I2C_ARBITRATION_LOST_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_ARBITRATION_LOST_INT_ENA  (BIT(5))
+#define I2C_ARBITRATION_LOST_INT_ENA_M  (BIT(5))
+#define I2C_ARBITRATION_LOST_INT_ENA_V  0x1
+#define I2C_ARBITRATION_LOST_INT_ENA_S  5
+        /* I2C_BYTE_TRANS_DONE_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_BYTE_TRANS_DONE_INT_ENA  (BIT(4))
+#define I2C_BYTE_TRANS_DONE_INT_ENA_M  (BIT(4))
+#define I2C_BYTE_TRANS_DONE_INT_ENA_V  0x1
+#define I2C_BYTE_TRANS_DONE_INT_ENA_S  4
+        /* I2C_END_DETECT_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_END_DETECT_INT_ENA  (BIT(3))
+#define I2C_END_DETECT_INT_ENA_M  (BIT(3))
+#define I2C_END_DETECT_INT_ENA_V  0x1
+#define I2C_END_DETECT_INT_ENA_S  3
+        /* I2C_RXFIFO_OVF_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_RXFIFO_OVF_INT_ENA  (BIT(2))
+#define I2C_RXFIFO_OVF_INT_ENA_M  (BIT(2))
+#define I2C_RXFIFO_OVF_INT_ENA_V  0x1
+#define I2C_RXFIFO_OVF_INT_ENA_S  2
+        /* I2C_TXFIFO_WM_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_TXFIFO_WM_INT_ENA  (BIT(1))
+#define I2C_TXFIFO_WM_INT_ENA_M  (BIT(1))
+#define I2C_TXFIFO_WM_INT_ENA_V  0x1
+#define I2C_TXFIFO_WM_INT_ENA_S  1
+        /* I2C_RXFIFO_WM_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_RXFIFO_WM_INT_ENA  (BIT(0))
+#define I2C_RXFIFO_WM_INT_ENA_M  (BIT(0))
+#define I2C_RXFIFO_WM_INT_ENA_V  0x1
+#define I2C_RXFIFO_WM_INT_ENA_S  0
+
+#define I2C_INT_STATUS_REG(i)          (REG_I2C_BASE(i) + 0x002c)
+        /* I2C_SLAVE_STRETCH_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_SLAVE_STRETCH_INT_ST  (BIT(16))
+#define I2C_SLAVE_STRETCH_INT_ST_M  (BIT(16))
+#define I2C_SLAVE_STRETCH_INT_ST_V  0x1
+#define I2C_SLAVE_STRETCH_INT_ST_S  16
+        /* I2C_DET_START_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_DET_START_INT_ST  (BIT(15))
+#define I2C_DET_START_INT_ST_M  (BIT(15))
+#define I2C_DET_START_INT_ST_V  0x1
+#define I2C_DET_START_INT_ST_S  15
+        /* I2C_SCL_MAIN_ST_TO_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_SCL_MAIN_ST_TO_INT_ST  (BIT(14))
+#define I2C_SCL_MAIN_ST_TO_INT_ST_M  (BIT(14))
+#define I2C_SCL_MAIN_ST_TO_INT_ST_V  0x1
+#define I2C_SCL_MAIN_ST_TO_INT_ST_S  14
+        /* I2C_SCL_ST_TO_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_SCL_ST_TO_INT_ST  (BIT(13))
+#define I2C_SCL_ST_TO_INT_ST_M  (BIT(13))
+#define I2C_SCL_ST_TO_INT_ST_V  0x1
+#define I2C_SCL_ST_TO_INT_ST_S  13
+        /* I2C_RXFIFO_UDF_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_RXFIFO_UDF_INT_ST  (BIT(12))
+#define I2C_RXFIFO_UDF_INT_ST_M  (BIT(12))
+#define I2C_RXFIFO_UDF_INT_ST_V  0x1
+#define I2C_RXFIFO_UDF_INT_ST_S  12
+        /* I2C_TXFIFO_OVF_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_TXFIFO_OVF_INT_ST  (BIT(11))
+#define I2C_TXFIFO_OVF_INT_ST_M  (BIT(11))
+#define I2C_TXFIFO_OVF_INT_ST_V  0x1
+#define I2C_TXFIFO_OVF_INT_ST_S  11
+        /* I2C_NACK_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_NACK_INT_ST  (BIT(10))
+#define I2C_NACK_INT_ST_M  (BIT(10))
+#define I2C_NACK_INT_ST_V  0x1
+#define I2C_NACK_INT_ST_S  10
+        /* I2C_TRANS_START_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_TRANS_START_INT_ST  (BIT(9))
+#define I2C_TRANS_START_INT_ST_M  (BIT(9))
+#define I2C_TRANS_START_INT_ST_V  0x1
+#define I2C_TRANS_START_INT_ST_S  9
+        /* I2C_TIME_OUT_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_TIME_OUT_INT_ST  (BIT(8))
+#define I2C_TIME_OUT_INT_ST_M  (BIT(8))
+#define I2C_TIME_OUT_INT_ST_V  0x1
+#define I2C_TIME_OUT_INT_ST_S  8
+        /* I2C_TRANS_COMPLETE_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_TRANS_COMPLETE_INT_ST  (BIT(7))
+#define I2C_TRANS_COMPLETE_INT_ST_M  (BIT(7))
+#define I2C_TRANS_COMPLETE_INT_ST_V  0x1
+#define I2C_TRANS_COMPLETE_INT_ST_S  7
+        /* I2C_MST_TXFIFO_UDF_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_MST_TXFIFO_UDF_INT_ST  (BIT(6))
+#define I2C_MST_TXFIFO_UDF_INT_ST_M  (BIT(6))
+#define I2C_MST_TXFIFO_UDF_INT_ST_V  0x1
+#define I2C_MST_TXFIFO_UDF_INT_ST_S  6
+        /* I2C_ARBITRATION_LOST_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_ARBITRATION_LOST_INT_ST  (BIT(5))
+#define I2C_ARBITRATION_LOST_INT_ST_M  (BIT(5))
+#define I2C_ARBITRATION_LOST_INT_ST_V  0x1
+#define I2C_ARBITRATION_LOST_INT_ST_S  5
+        /* I2C_BYTE_TRANS_DONE_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_BYTE_TRANS_DONE_INT_ST  (BIT(4))
+#define I2C_BYTE_TRANS_DONE_INT_ST_M  (BIT(4))
+#define I2C_BYTE_TRANS_DONE_INT_ST_V  0x1
+#define I2C_BYTE_TRANS_DONE_INT_ST_S  4
+        /* I2C_END_DETECT_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_END_DETECT_INT_ST  (BIT(3))
+#define I2C_END_DETECT_INT_ST_M  (BIT(3))
+#define I2C_END_DETECT_INT_ST_V  0x1
+#define I2C_END_DETECT_INT_ST_S  3
+        /* I2C_RXFIFO_OVF_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_RXFIFO_OVF_INT_ST  (BIT(2))
+#define I2C_RXFIFO_OVF_INT_ST_M  (BIT(2))
+#define I2C_RXFIFO_OVF_INT_ST_V  0x1
+#define I2C_RXFIFO_OVF_INT_ST_S  2
+        /* I2C_TXFIFO_WM_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_TXFIFO_WM_INT_ST  (BIT(1))
+#define I2C_TXFIFO_WM_INT_ST_M  (BIT(1))
+#define I2C_TXFIFO_WM_INT_ST_V  0x1
+#define I2C_TXFIFO_WM_INT_ST_S  1
+        /* I2C_RXFIFO_WM_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_RXFIFO_WM_INT_ST  (BIT(0))
+#define I2C_RXFIFO_WM_INT_ST_M  (BIT(0))
+#define I2C_RXFIFO_WM_INT_ST_V  0x1
+#define I2C_RXFIFO_WM_INT_ST_S  0
+
+#define I2C_SDA_HOLD_REG(i)          (REG_I2C_BASE(i) + 0x0030)
+        /* I2C_SDA_HOLD_TIME : R/W ;bitpos:[8:0] ;default: 9'b0 ; */
+        /*description: */
+#define I2C_SDA_HOLD_TIME  0x000001FF
+#define I2C_SDA_HOLD_TIME_M  ((I2C_SDA_HOLD_TIME_V)<<(I2C_SDA_HOLD_TIME_S))
+#define I2C_SDA_HOLD_TIME_V  0x1FF
+#define I2C_SDA_HOLD_TIME_S  0
+
+#define I2C_SDA_SAMPLE_REG(i)          (REG_I2C_BASE(i) + 0x0034)
+        /* I2C_SDA_SAMPLE_TIME : R/W ;bitpos:[8:0] ;default: 9'b0 ; */
+        /*description: */
+#define I2C_SDA_SAMPLE_TIME  0x000001FF
+#define I2C_SDA_SAMPLE_TIME_M  ((I2C_SDA_SAMPLE_TIME_V)<<(I2C_SDA_SAMPLE_TIME_S))
+#define I2C_SDA_SAMPLE_TIME_V  0x1FF
+#define I2C_SDA_SAMPLE_TIME_S  0
+
+#define I2C_SCL_HIGH_PERIOD_REG(i)          (REG_I2C_BASE(i) + 0x0038)
+        /* I2C_SCL_WAIT_HIGH_PERIOD : R/W ;bitpos:[15:9] ;default: 7'b0 ; */
+        /*description: */
+#define I2C_SCL_WAIT_HIGH_PERIOD  0x0000007F
+#define I2C_SCL_WAIT_HIGH_PERIOD_M  ((I2C_SCL_WAIT_HIGH_PERIOD_V)<<(I2C_SCL_WAIT_HIGH_PERIOD_S))
+#define I2C_SCL_WAIT_HIGH_PERIOD_V  0x7F
+#define I2C_SCL_WAIT_HIGH_PERIOD_S  9
+        /* I2C_SCL_HIGH_PERIOD : R/W ;bitpos:[8:0] ;default: 9'b0 ; */
+        /*description: */
+#define I2C_SCL_HIGH_PERIOD  0x000001FF
+#define I2C_SCL_HIGH_PERIOD_M  ((I2C_SCL_HIGH_PERIOD_V)<<(I2C_SCL_HIGH_PERIOD_S))
+#define I2C_SCL_HIGH_PERIOD_V  0x1FF
+#define I2C_SCL_HIGH_PERIOD_S  0
+
+#define I2C_SCL_START_HOLD_REG(i)          (REG_I2C_BASE(i) + 0x0040)
+        /* I2C_SCL_START_HOLD_TIME : R/W ;bitpos:[8:0] ;default: 9'b1000 ; */
+        /*description: */
+#define I2C_SCL_START_HOLD_TIME  0x000001FF
+#define I2C_SCL_START_HOLD_TIME_M  ((I2C_SCL_START_HOLD_TIME_V)<<(I2C_SCL_START_HOLD_TIME_S))
+#define I2C_SCL_START_HOLD_TIME_V  0x1FF
+#define I2C_SCL_START_HOLD_TIME_S  0
+
+#define I2C_SCL_RSTART_SETUP_REG(i)          (REG_I2C_BASE(i) + 0x0044)
+        /* I2C_SCL_RSTART_SETUP_TIME : R/W ;bitpos:[8:0] ;default: 9'b1000 ; */
+        /*description: */
+#define I2C_SCL_RSTART_SETUP_TIME  0x000001FF
+#define I2C_SCL_RSTART_SETUP_TIME_M  ((I2C_SCL_RSTART_SETUP_TIME_V)<<(I2C_SCL_RSTART_SETUP_TIME_S))
+#define I2C_SCL_RSTART_SETUP_TIME_V  0x1FF
+#define I2C_SCL_RSTART_SETUP_TIME_S  0
+
+#define I2C_SCL_STOP_HOLD_REG(i)          (REG_I2C_BASE(i) + 0x0048)
+        /* I2C_SCL_STOP_HOLD_TIME : R/W ;bitpos:[8:0] ;default: 9'b1000 ; */
+        /*description: */
+#define I2C_SCL_STOP_HOLD_TIME  0x000001FF
+#define I2C_SCL_STOP_HOLD_TIME_M  ((I2C_SCL_STOP_HOLD_TIME_V)<<(I2C_SCL_STOP_HOLD_TIME_S))
+#define I2C_SCL_STOP_HOLD_TIME_V  0x1FF
+#define I2C_SCL_STOP_HOLD_TIME_S  0
+
+#define I2C_SCL_STOP_SETUP_REG(i)          (REG_I2C_BASE(i) + 0x004C)
+        /* I2C_SCL_STOP_SETUP_TIME : R/W ;bitpos:[8:0] ;default: 9'b1000 ; */
+        /*description: */
+#define I2C_SCL_STOP_SETUP_TIME  0x000001FF
+#define I2C_SCL_STOP_SETUP_TIME_M  ((I2C_SCL_STOP_SETUP_TIME_V)<<(I2C_SCL_STOP_SETUP_TIME_S))
+#define I2C_SCL_STOP_SETUP_TIME_V  0x1FF
+#define I2C_SCL_STOP_SETUP_TIME_S  0
+
+#define I2C_FILTER_CFG_REG(i)          (REG_I2C_BASE(i) + 0x0050)
+        /* I2C_SDA_FILTER_EN : R/W ;bitpos:[5] ;default: 1'b1 ; */
+        /*description: */
+#define I2C_SDA_FILTER_EN  (BIT(5))
+#define I2C_SDA_FILTER_EN_M  (BIT(5))
+#define I2C_SDA_FILTER_EN_V  0x1
+#define I2C_SDA_FILTER_EN_S  5
+        /* I2C_SCL_FILTER_EN : R/W ;bitpos:[4] ;default: 1'b1 ; */
+        /*description: */
+#define I2C_SCL_FILTER_EN  (BIT(4))
+#define I2C_SCL_FILTER_EN_M  (BIT(4))
+#define I2C_SCL_FILTER_EN_V  0x1
+#define I2C_SCL_FILTER_EN_S  4
+        /* I2C_FILTER_THRES : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+        /*description: */
+#define I2C_FILTER_THRES  0x0000000F
+#define I2C_FILTER_THRES_M  ((I2C_FILTER_THRES_V)<<(I2C_FILTER_THRES_S))
+#define I2C_FILTER_THRES_V  0xF
+#define I2C_FILTER_THRES_S  0
+
+#define I2C_CLK_CONF_REG(i)          (REG_I2C_BASE(i) + 0x0054)
+        /* I2C_SCLK_ACTIVE : R/W ;bitpos:[21] ;default: 1'b1 ; */
+        /*description: */
+#define I2C_SCLK_ACTIVE  (BIT(21))
+#define I2C_SCLK_ACTIVE_M  (BIT(21))
+#define I2C_SCLK_ACTIVE_V  0x1
+#define I2C_SCLK_ACTIVE_S  21
+        /* I2C_SCLK_SEL : R/W ;bitpos:[20] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_SCLK_SEL  (BIT(20))
+#define I2C_SCLK_SEL_M  (BIT(20))
+#define I2C_SCLK_SEL_V  0x1
+#define I2C_SCLK_SEL_S  20
+        /* I2C_SCLK_DIV_B : R/W ;bitpos:[19:14] ;default: 6'b0 ; */
+        /*description: */
+#define I2C_SCLK_DIV_B  0x0000003F
+#define I2C_SCLK_DIV_B_M  ((I2C_SCLK_DIV_B_V)<<(I2C_SCLK_DIV_B_S))
+#define I2C_SCLK_DIV_B_V  0x3F
+#define I2C_SCLK_DIV_B_S  14
+        /* I2C_SCLK_DIV_A : R/W ;bitpos:[13:8] ;default: 6'b0 ; */
+        /*description: */
+#define I2C_SCLK_DIV_A  0x0000003F
+#define I2C_SCLK_DIV_A_M  ((I2C_SCLK_DIV_A_V)<<(I2C_SCLK_DIV_A_S))
+#define I2C_SCLK_DIV_A_V  0x3F
+#define I2C_SCLK_DIV_A_S  8
+        /* I2C_SCLK_DIV_NUM : R/W ;bitpos:[7:0] ;default: 8'b0 ; */
+        /*description: */
+#define I2C_SCLK_DIV_NUM  0x000000FF
+#define I2C_SCLK_DIV_NUM_M  ((I2C_SCLK_DIV_NUM_V)<<(I2C_SCLK_DIV_NUM_S))
+#define I2C_SCLK_DIV_NUM_V  0xFF
+#define I2C_SCLK_DIV_NUM_S  0
+
+#define I2C_COMD0_REG(i)          (REG_I2C_BASE(i) + 0x0058)
+        /* I2C_COMMAND0_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_COMMAND0_DONE  (BIT(31))
+#define I2C_COMMAND0_DONE_M  (BIT(31))
+#define I2C_COMMAND0_DONE_V  0x1
+#define I2C_COMMAND0_DONE_S  31
+        /* I2C_COMMAND0 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
+        /*description: */
+#define I2C_COMMAND0  0x00003FFF
+#define I2C_COMMAND0_M  ((I2C_COMMAND0_V)<<(I2C_COMMAND0_S))
+#define I2C_COMMAND0_V  0x3FFF
+#define I2C_COMMAND0_S  0
+
+#define I2C_COMD1_REG(i)          (REG_I2C_BASE(i) + 0x005C)
+        /* I2C_COMMAND1_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_COMMAND1_DONE  (BIT(31))
+#define I2C_COMMAND1_DONE_M  (BIT(31))
+#define I2C_COMMAND1_DONE_V  0x1
+#define I2C_COMMAND1_DONE_S  31
+        /* I2C_COMMAND1 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
+        /*description: */
+#define I2C_COMMAND1  0x00003FFF
+#define I2C_COMMAND1_M  ((I2C_COMMAND1_V)<<(I2C_COMMAND1_S))
+#define I2C_COMMAND1_V  0x3FFF
+#define I2C_COMMAND1_S  0
+
+#define I2C_COMD2_REG(i)          (REG_I2C_BASE(i) + 0x0060)
+        /* I2C_COMMAND2_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_COMMAND2_DONE  (BIT(31))
+#define I2C_COMMAND2_DONE_M  (BIT(31))
+#define I2C_COMMAND2_DONE_V  0x1
+#define I2C_COMMAND2_DONE_S  31
+        /* I2C_COMMAND2 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
+        /*description: */
+#define I2C_COMMAND2  0x00003FFF
+#define I2C_COMMAND2_M  ((I2C_COMMAND2_V)<<(I2C_COMMAND2_S))
+#define I2C_COMMAND2_V  0x3FFF
+#define I2C_COMMAND2_S  0
+
+#define I2C_COMD3_REG(i)          (REG_I2C_BASE(i) + 0x0064)
+        /* I2C_COMMAND3_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_COMMAND3_DONE  (BIT(31))
+#define I2C_COMMAND3_DONE_M  (BIT(31))
+#define I2C_COMMAND3_DONE_V  0x1
+#define I2C_COMMAND3_DONE_S  31
+        /* I2C_COMMAND3 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
+        /*description: */
+#define I2C_COMMAND3  0x00003FFF
+#define I2C_COMMAND3_M  ((I2C_COMMAND3_V)<<(I2C_COMMAND3_S))
+#define I2C_COMMAND3_V  0x3FFF
+#define I2C_COMMAND3_S  0
+
+#define I2C_COMD4_REG(i)          (REG_I2C_BASE(i) + 0x0068)
+        /* I2C_COMMAND4_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_COMMAND4_DONE  (BIT(31))
+#define I2C_COMMAND4_DONE_M  (BIT(31))
+#define I2C_COMMAND4_DONE_V  0x1
+#define I2C_COMMAND4_DONE_S  31
+        /* I2C_COMMAND4 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
+        /*description: */
+#define I2C_COMMAND4  0x00003FFF
+#define I2C_COMMAND4_M  ((I2C_COMMAND4_V)<<(I2C_COMMAND4_S))
+#define I2C_COMMAND4_V  0x3FFF
+#define I2C_COMMAND4_S  0
+
+#define I2C_COMD5_REG(i)          (REG_I2C_BASE(i) + 0x006C)
+        /* I2C_COMMAND5_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_COMMAND5_DONE  (BIT(31))
+#define I2C_COMMAND5_DONE_M  (BIT(31))
+#define I2C_COMMAND5_DONE_V  0x1
+#define I2C_COMMAND5_DONE_S  31
+        /* I2C_COMMAND5 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
+        /*description: */
+#define I2C_COMMAND5  0x00003FFF
+#define I2C_COMMAND5_M  ((I2C_COMMAND5_V)<<(I2C_COMMAND5_S))
+#define I2C_COMMAND5_V  0x3FFF
+#define I2C_COMMAND5_S  0
+
+#define I2C_COMD6_REG(i)          (REG_I2C_BASE(i) + 0x0070)
+        /* I2C_COMMAND6_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_COMMAND6_DONE  (BIT(31))
+#define I2C_COMMAND6_DONE_M  (BIT(31))
+#define I2C_COMMAND6_DONE_V  0x1
+#define I2C_COMMAND6_DONE_S  31
+        /* I2C_COMMAND6 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
+        /*description: */
+#define I2C_COMMAND6  0x00003FFF
+#define I2C_COMMAND6_M  ((I2C_COMMAND6_V)<<(I2C_COMMAND6_S))
+#define I2C_COMMAND6_V  0x3FFF
+#define I2C_COMMAND6_S  0
+
+#define I2C_COMD7_REG(i)          (REG_I2C_BASE(i) + 0x0074)
+        /* I2C_COMMAND7_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_COMMAND7_DONE  (BIT(31))
+#define I2C_COMMAND7_DONE_M  (BIT(31))
+#define I2C_COMMAND7_DONE_V  0x1
+#define I2C_COMMAND7_DONE_S  31
+        /* I2C_COMMAND7 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
+        /*description: */
+#define I2C_COMMAND7  0x00003FFF
+#define I2C_COMMAND7_M  ((I2C_COMMAND7_V)<<(I2C_COMMAND7_S))
+#define I2C_COMMAND7_V  0x3FFF
+#define I2C_COMMAND7_S  0
+
+#define I2C_SCL_ST_TIME_OUT_REG(i)          (REG_I2C_BASE(i) + 0x0078)
+        /* I2C_SCL_ST_TO_REG : R/W ;bitpos:[4:0] ;default: 5'h10 ; */
+        /*description: */
+#define I2C_SCL_ST_TO_REG  0x0000001F
+#define I2C_SCL_ST_TO_REG_M  ((I2C_SCL_ST_TO_REG_V)<<(I2C_SCL_ST_TO_REG_S))
+#define I2C_SCL_ST_TO_REG_V  0x1F
+#define I2C_SCL_ST_TO_REG_S  0
+
+#define I2C_SCL_MAIN_ST_TIME_OUT_REG(i)          (REG_I2C_BASE(i) + 0x007c)
+        /* I2C_SCL_MAIN_ST_TO_REG : R/W ;bitpos:[4:0] ;default: 5'h10 ; */
+        /*description: */
+#define I2C_SCL_MAIN_ST_TO_REG  0x0000001F
+#define I2C_SCL_MAIN_ST_TO_REG_M  ((I2C_SCL_MAIN_ST_TO_REG_V)<<(I2C_SCL_MAIN_ST_TO_REG_S))
+#define I2C_SCL_MAIN_ST_TO_REG_V  0x1F
+#define I2C_SCL_MAIN_ST_TO_REG_S  0
+
+#define I2C_SCL_SP_CONF_REG(i)          (REG_I2C_BASE(i) + 0x0080)
+        /* I2C_SDA_PD_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_SDA_PD_EN  (BIT(7))
+#define I2C_SDA_PD_EN_M  (BIT(7))
+#define I2C_SDA_PD_EN_V  0x1
+#define I2C_SDA_PD_EN_S  7
+        /* I2C_SCL_PD_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_SCL_PD_EN  (BIT(6))
+#define I2C_SCL_PD_EN_M  (BIT(6))
+#define I2C_SCL_PD_EN_V  0x1
+#define I2C_SCL_PD_EN_S  6
+        /* I2C_SCL_RST_SLV_NUM : R/W ;bitpos:[5:1] ;default: 5'b0 ; */
+        /*description: */
+#define I2C_SCL_RST_SLV_NUM  0x0000001F
+#define I2C_SCL_RST_SLV_NUM_M  ((I2C_SCL_RST_SLV_NUM_V)<<(I2C_SCL_RST_SLV_NUM_S))
+#define I2C_SCL_RST_SLV_NUM_V  0x1F
+#define I2C_SCL_RST_SLV_NUM_S  1
+        /* I2C_SCL_RST_SLV_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_SCL_RST_SLV_EN  (BIT(0))
+#define I2C_SCL_RST_SLV_EN_M  (BIT(0))
+#define I2C_SCL_RST_SLV_EN_V  0x1
+#define I2C_SCL_RST_SLV_EN_S  0
+
+#define I2C_SCL_STRETCH_CONF_REG(i)          (REG_I2C_BASE(i) + 0x0084)
+        /* I2C_SLAVE_SCL_STRETCH_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_SLAVE_SCL_STRETCH_CLR  (BIT(11))
+#define I2C_SLAVE_SCL_STRETCH_CLR_M  (BIT(11))
+#define I2C_SLAVE_SCL_STRETCH_CLR_V  0x1
+#define I2C_SLAVE_SCL_STRETCH_CLR_S  11
+        /* I2C_SLAVE_SCL_STRETCH_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
+        /*description: */
+#define I2C_SLAVE_SCL_STRETCH_EN  (BIT(10))
+#define I2C_SLAVE_SCL_STRETCH_EN_M  (BIT(10))
+#define I2C_SLAVE_SCL_STRETCH_EN_V  0x1
+#define I2C_SLAVE_SCL_STRETCH_EN_S  10
+        /* I2C_STRETCH_PROTECT_NUM : R/W ;bitpos:[9:0] ;default: 10'b0 ; */
+        /*description: */
+#define I2C_STRETCH_PROTECT_NUM  0x000003FF
+#define I2C_STRETCH_PROTECT_NUM_M  ((I2C_STRETCH_PROTECT_NUM_V)<<(I2C_STRETCH_PROTECT_NUM_S))
+#define I2C_STRETCH_PROTECT_NUM_V  0x3FF
+#define I2C_STRETCH_PROTECT_NUM_S  0
+
+#define I2C_DATE_REG(i)          (REG_I2C_BASE(i) + 0x00F8)
+        /* I2C_DATE : R/W ;bitpos:[31:0] ;default: 32'h20011601 ; */
+        /*description: */
+#define I2C_DATE  0xFFFFFFFF
+#define I2C_DATE_M  ((I2C_DATE_V)<<(I2C_DATE_S))
+#define I2C_DATE_V  0xFFFFFFFF
+#define I2C_DATE_S  0
+
+#define I2C_TXFIFO_START_ADDR_REG(i)          (REG_I2C_BASE(i) + 0x0100)
+
+#define I2C_RXFIFO_START_ADDR_REG(i)          (REG_I2C_BASE(i) + 0x0180)
 
 #ifdef __cplusplus
 }

components/soc/esp32s3/include/soc/i2c_struct.h

@@ -1,4 +1,4 @@
-// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
@@ -22,41 +22,43 @@ extern "C" {
 typedef volatile struct {
     union {
         struct {
-            uint32_t period:        14;
-            uint32_t reserved14:    18;
+            uint32_t period:         9;
+            uint32_t reserved9:     23;
         };
         uint32_t val;
     } scl_low_period;
     union {
         struct {
-            uint32_t sda_force_out:    1;
-            uint32_t scl_force_out:    1;
-            uint32_t sample_scl_level: 1;
-            uint32_t ack_level:        1;
-            uint32_t ms_mode:          1;
-            uint32_t trans_start:      1;
-            uint32_t tx_lsb_first:     1;
-            uint32_t rx_lsb_first:     1;
-            uint32_t clk_en:           1;
-            uint32_t arbitration_en:   1;
-            uint32_t fsm_rst:          1;
-            uint32_t ref_always_on:    1;
-            uint32_t reserved12:      20;
+            uint32_t sda_force_out:        1;
+            uint32_t scl_force_out:        1;
+            uint32_t sample_scl_level:     1;
+            uint32_t rx_full_ack_level:    1;
+            uint32_t ms_mode:              1;
+            uint32_t trans_start:          1;
+            uint32_t tx_lsb_first:         1;
+            uint32_t rx_lsb_first:         1;
+            uint32_t clk_en:               1;
+            uint32_t arbitration_en:       1;
+            uint32_t fsm_rst:              1;
+            uint32_t conf_upgate:          1;
+            uint32_t slv_tx_auto_start_en: 1;
+            uint32_t reserved13:          19;
         };
         uint32_t val;
     } ctr;
     union {
         struct {
-            uint32_t ack_rec:             1;
+            uint32_t resp_rec:            1;
             uint32_t slave_rw:            1;
-            uint32_t time_out:            1;
+            uint32_t reserved2:           1;
             uint32_t arb_lost:            1;
             uint32_t bus_busy:            1;
             uint32_t slave_addressed:     1;
-            uint32_t byte_trans:          1;
+            uint32_t reserved6:           1;
             uint32_t reserved7:           1;
             uint32_t rx_fifo_cnt:         6;
-            uint32_t reserved14:          4;
+            uint32_t stretch_cause:       2;
+            uint32_t reserved16:          2;
             uint32_t tx_fifo_cnt:         6;
             uint32_t scl_main_state_last: 3;
             uint32_t reserved27:          1;
@@ -67,9 +69,9 @@ typedef volatile struct {
     } status_reg;
     union {
         struct {
-            uint32_t tout:       24;
-            uint32_t time_out_en: 1;
-            uint32_t reserved25:  7;
+            uint32_t time_out_value: 5;
+            uint32_t time_out_en:    1;
+            uint32_t reserved6:     26;
         };
         uint32_t val;
     } timeout;
@@ -83,216 +85,222 @@ typedef volatile struct {
     } slave_addr;
     union {
         struct {
-            uint32_t rx_fifo_start_addr: 5;
-            uint32_t rx_fifo_end_addr:  5;
-            uint32_t tx_fifo_start_addr: 5;
-            uint32_t tx_fifo_end_addr:  5;
-            uint32_t rx_update:         1;
-            uint32_t tx_update:         1;
-            uint32_t tx_fifo_init_raddr: 5;
-            uint32_t rx_fifo_init_waddr: 5;
+            uint32_t rx_fifo_raddr:  5;
+            uint32_t rx_fifo_waddr:  5;
+            uint32_t tx_fifo_raddr:  5;
+            uint32_t tx_fifo_waddr:  5;
+            uint32_t reserved20:     1;
+            uint32_t reserved21:     1;
+            uint32_t slave_rw_point: 8;
+            uint32_t reserved30:     2;
         };
         uint32_t val;
     } fifo_st;
     union {
         struct {
-            uint32_t rx_fifo_full_thrhd: 5;
-            uint32_t tx_fifo_empty_thrhd: 5;
-            uint32_t nonfifo_en:         1;
-            uint32_t fifo_addr_cfg_en:   1;
-            uint32_t rx_fifo_rst:        1;
-            uint32_t tx_fifo_rst:        1;
-            uint32_t nonfifo_rx_thres:   6;
-            uint32_t nonfifo_tx_thres:   6;
-            uint32_t reserved26:         6;
+            uint32_t rx_fifo_wm_thrhd: 5;
+            uint32_t tx_fifo_wm_thrhd: 5;
+            uint32_t nonfifo_en:       1;
+            uint32_t fifo_addr_cfg_en: 1;
+            uint32_t rx_fifo_rst:      1;
+            uint32_t tx_fifo_rst:      1;
+            uint32_t fifo_prt_en:      1;
+            uint32_t reserved15:       5;
+            uint32_t reserved20:       6;
+            uint32_t reserved26:       1;
+            uint32_t reserved27:       5;
         };
         uint32_t val;
     } fifo_conf;
     union {
         struct {
-            uint8_t data;
-            uint8_t reserved[3];
+            uint32_t data;
         };
         uint32_t val;
     } fifo_data;
     union {
         struct {
-            uint32_t rx_fifo_full:             1;
-            uint32_t tx_fifo_empty:            1;
+            uint32_t rx_fifo_wm:               1;
+            uint32_t tx_fifo_wm:               1;
             uint32_t rx_fifo_ovf:              1;
             uint32_t end_detect:               1;
-            uint32_t slave_tran_comp:          1;
+            uint32_t byte_trans_done:          1;
             uint32_t arbitration_lost:         1;
-            uint32_t master_tran_comp:         1;
+            uint32_t mst_tx_fifo_udf:          1;
             uint32_t trans_complete:           1;
             uint32_t time_out:                 1;
             uint32_t trans_start:              1;
-            uint32_t ack_err:                  1;
-            uint32_t rx_rec_full:              1;
-            uint32_t tx_send_empty:            1;
+            uint32_t nack:                     1;
+            uint32_t tx_fifo_ovf:              1;
+            uint32_t rx_fifo_udf:              1;
             uint32_t scl_st_to:                1;
             uint32_t scl_main_st_to:           1;
             uint32_t det_start:                1;
-            uint32_t reserved16:              16;
+            uint32_t slave_stretch:            1;
+            uint32_t reserved17:              15;
         };
         uint32_t val;
     } int_raw;
     union {
         struct {
-            uint32_t rx_fifo_full:             1;
-            uint32_t tx_fifo_empty:            1;
+            uint32_t rx_fifo_wm:               1;
+            uint32_t tx_fifo_wm:               1;
             uint32_t rx_fifo_ovf:              1;
             uint32_t end_detect:               1;
-            uint32_t slave_tran_comp:          1;
+            uint32_t byte_trans_done:          1;
             uint32_t arbitration_lost:         1;
-            uint32_t master_tran_comp:         1;
+            uint32_t mst_tx_fifo_udf:          1;
             uint32_t trans_complete:           1;
             uint32_t time_out:                 1;
             uint32_t trans_start:              1;
-            uint32_t ack_err:                  1;
-            uint32_t rx_rec_full:              1;
-            uint32_t tx_send_empty:            1;
+            uint32_t nack:                     1;
+            uint32_t tx_fifo_ovf:              1;
+            uint32_t rx_fifo_udf:              1;
             uint32_t scl_st_to:                1;
             uint32_t scl_main_st_to:           1;
             uint32_t det_start:                1;
-            uint32_t reserved16:              16;
+            uint32_t slave_stretch:            1;
+            uint32_t reserved17:              15;
         };
         uint32_t val;
     } int_clr;
     union {
         struct {
-            uint32_t rx_fifo_full:             1;
-            uint32_t tx_fifo_empty:            1;
+            uint32_t rx_fifo_wm:               1;
+            uint32_t tx_fifo_wm:               1;
             uint32_t rx_fifo_ovf:              1;
             uint32_t end_detect:               1;
-            uint32_t slave_tran_comp:          1;
+            uint32_t byte_trans_done:          1;
             uint32_t arbitration_lost:         1;
-            uint32_t master_tran_comp:         1;
+            uint32_t mst_tx_fifo_udf:          1;
             uint32_t trans_complete:           1;
             uint32_t time_out:                 1;
             uint32_t trans_start:              1;
-            uint32_t ack_err:                  1;
-            uint32_t rx_rec_full:              1;
-            uint32_t tx_send_empty:            1;
+            uint32_t nack:                     1;
+            uint32_t tx_fifo_ovf:              1;
+            uint32_t rx_fifo_udf:              1;
             uint32_t scl_st_to:                1;
             uint32_t scl_main_st_to:           1;
             uint32_t det_start:                1;
-            uint32_t reserved16:              16;
+            uint32_t slave_stretch:            1;
+            uint32_t reserved17:              15;
         };
         uint32_t val;
     } int_ena;
     union {
         struct {
-            uint32_t rx_fifo_full:            1;
-            uint32_t tx_fifo_empty:           1;
+            uint32_t rx_fifo_wm:              1;
+            uint32_t tx_fifo_wm:              1;
             uint32_t rx_fifo_ovf:             1;
             uint32_t end_detect:              1;
-            uint32_t slave_tran_comp:         1;
+            uint32_t byte_trans_done:         1;
             uint32_t arbitration_lost:        1;
-            uint32_t master_tran_comp:        1;
+            uint32_t mst_tx_fifo_udf:         1;
             uint32_t trans_complete:          1;
             uint32_t time_out:                1;
             uint32_t trans_start:             1;
-            uint32_t ack_err:                 1;
-            uint32_t rx_rec_full:             1;
-            uint32_t tx_send_empty:           1;
+            uint32_t nack:                    1;
+            uint32_t tx_fifo_ovf:             1;
+            uint32_t rx_fifo_udf:             1;
             uint32_t scl_st_to:               1;
             uint32_t scl_main_st_to:          1;
             uint32_t det_start:               1;
-            uint32_t reserved16:             16;
+            uint32_t slave_stretch:           1;
+            uint32_t reserved17:             15;
         };
         uint32_t val;
     } int_status;
     union {
         struct {
-            uint32_t time:         10;
-            uint32_t reserved10:   22;
+            uint32_t time:          9;
+            uint32_t reserved9:    23;
         };
         uint32_t val;
     } sda_hold;
     union {
         struct {
-            uint32_t time:           10;
-            uint32_t reserved10:     22;
+            uint32_t time:            9;
+            uint32_t reserved9:      23;
         };
         uint32_t val;
     } sda_sample;
     union {
         struct {
-            uint32_t period:              14;
-            uint32_t scl_wait_high_period: 14;
-            uint32_t reserved28:           4;
+            uint32_t period:               9;
+            uint32_t scl_wait_high_period: 7;
+            uint32_t reserved16:          16;
         };
         uint32_t val;
     } scl_high_period;
     uint32_t reserved_3c;
     union {
         struct {
-            uint32_t time:               10;
-            uint32_t reserved10:         22;
+            uint32_t time:                9;
+            uint32_t reserved9:          23;
         };
         uint32_t val;
     } scl_start_hold;
     union {
         struct {
-            uint32_t time:                 10;
-            uint32_t reserved10:           22;
+            uint32_t time:                  9;
+            uint32_t reserved9:            23;
         };
         uint32_t val;
     } scl_rstart_setup;
     union {
         struct {
-            uint32_t time:              14;
-            uint32_t reserved14:        18;
+            uint32_t time:               9;
+            uint32_t reserved9:         23;
         };
         uint32_t val;
     } scl_stop_hold;
     union {
         struct {
-            uint32_t time:               10;
-            uint32_t reserved10:         22;
+            uint32_t time:                9;
+            uint32_t reserved9:          23;
         };
         uint32_t val;
     } scl_stop_setup;
     union {
         struct {
-            uint32_t thres:            3;
-            uint32_t en:               1;
-            uint32_t reserved4:       28;
+            uint32_t scl_thres:            4;
+            uint32_t sda_thres:            4;
+            uint32_t scl_en:               1;
+            uint32_t sda_en:               1;
+            uint32_t reserved10:      22;
         };
         uint32_t val;
-    } scl_filter_cfg;
+    } filter_cfg;
     union {
         struct {
-            uint32_t thres:            3;
-            uint32_t en:               1;
-            uint32_t reserved4:       28;
+            uint32_t sclk_div_num: 8;
+            uint32_t sclk_div_a:   6;
+            uint32_t sclk_div_b:   6;
+            uint32_t sclk_sel:     1;
+            uint32_t sclk_active:  1;
+            uint32_t reserved22:  10;
         };
         uint32_t val;
-    } sda_filter_cfg;
+    } clk_conf;
     union {
         struct {
-            uint32_t byte_num:      8;              /*Byte_num represent the number of data need to be send or data need to be received.*/
-            uint32_t ack_en:        1;              /*ack_check_en  ack_exp and ack value are used to control  the ack bit.*/
-            uint32_t ack_exp:       1;              /*ack_check_en  ack_exp and ack value are used to control  the ack bit.*/
-            uint32_t ack_val:       1;              /*ack_check_en  ack_exp and ack value are used to control  the ack bit.*/
-            uint32_t op_code:       3;              /*op_code is the command  0：RSTART   1：WRITE  2：READ  3：STOP . 4:END.*/
+            uint32_t command0:     14;
             uint32_t reserved14:   17;
             uint32_t done:          1;
         };
         uint32_t val;
-    } command[16];
+    } command[8];
     union {
         struct {
-            uint32_t scl_st_to: 24;
-            uint32_t reserved24: 8;
+            uint32_t scl_st_to:  5;                 /*no more than 23*/
+            uint32_t reserved5: 27;
         };
         uint32_t val;
     } scl_st_time_out;
     union {
         struct {
-            uint32_t scl_main_st_to: 24;
-            uint32_t reserved24:     8;
+            uint32_t scl_main_st_to: 5;             /*no more than 23*/
+            uint32_t reserved5:     27;
         };
         uint32_t val;
     } scl_main_st_time_out;
@@ -306,6 +314,22 @@ typedef volatile struct {
         };
         uint32_t val;
     } scl_sp_conf;
+    union {
+        struct {
+            uint32_t stretch_protect_num:  10;
+            uint32_t slave_scl_stretch_en:  1;
+            uint32_t slave_scl_stretch_clr: 1;
+            uint32_t reserved12:           20;
+        };
+        uint32_t val;
+    } scl_stretch_conf;
+    uint32_t reserved_88;
+    uint32_t reserved_8c;
+    uint32_t reserved_90;
+    uint32_t reserved_94;
+    uint32_t reserved_98;
+    uint32_t reserved_9c;
+    uint32_t reserved_a0;
     uint32_t reserved_a4;
     uint32_t reserved_a8;
     uint32_t reserved_ac;
@@ -329,7 +353,39 @@ typedef volatile struct {
     uint32_t reserved_f4;
     uint32_t date;                                  /**/
     uint32_t reserved_fc;
-    uint32_t ram_data[32];                       /**/
+    uint32_t txfifo_start_addr;                     /**/
+    uint32_t reserved_104;
+    uint32_t reserved_108;
+    uint32_t reserved_10c;
+    uint32_t reserved_110;
+    uint32_t reserved_114;
+    uint32_t reserved_118;
+    uint32_t reserved_11c;
+    uint32_t reserved_120;
+    uint32_t reserved_124;
+    uint32_t reserved_128;
+    uint32_t reserved_12c;
+    uint32_t reserved_130;
+    uint32_t reserved_134;
+    uint32_t reserved_138;
+    uint32_t reserved_13c;
+    uint32_t reserved_140;
+    uint32_t reserved_144;
+    uint32_t reserved_148;
+    uint32_t reserved_14c;
+    uint32_t reserved_150;
+    uint32_t reserved_154;
+    uint32_t reserved_158;
+    uint32_t reserved_15c;
+    uint32_t reserved_160;
+    uint32_t reserved_164;
+    uint32_t reserved_168;
+    uint32_t reserved_16c;
+    uint32_t reserved_170;
+    uint32_t reserved_174;
+    uint32_t reserved_178;
+    uint32_t reserved_17c;
+    uint32_t fifo_start_addr;                     /**/
 } i2c_dev_t;
 
 extern i2c_dev_t I2C0;