support h2 eco2 fosc calibration

components/esp_hw_support/port/esp32h2/rtc_clk_init.c

@@ -19,6 +19,7 @@
 #include "esp_hw_log.h"
 #include "sdkconfig.h"
 #include "esp_rom_uart.h"
+#include "hal/clk_tree_ll.h"
 
 static const char *TAG = "rtc_clk_init";
 
@@ -39,6 +40,8 @@ void rtc_clk_init(rtc_clk_config_t cfg)
     REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_OC_SCK_DCAP, cfg.slow_clk_dcap);
     REG_SET_FIELD(LP_CLKRST_RC32K_CNTL_REG, LP_CLKRST_RC32K_DFREQ, cfg.rc32k_dfreq);
 
+    clk_ll_rc_fast_tick_conf();
+
     rtc_xtal_freq_t xtal_freq = cfg.xtal_freq;
     esp_rom_uart_tx_wait_idle(0);
     rtc_clk_xtal_freq_update(xtal_freq);

components/esp_hw_support/port/esp32h2/rtc_time.c

@@ -12,6 +12,8 @@
 #include "soc/timer_group_reg.h"
 #include "esp_rom_sys.h"
 #include "assert.h"
+#include "hal/efuse_hal.h"
+#include "soc/chip_revision.h"
 
 static const char *TAG = "rtc_time";
 
@@ -129,6 +131,15 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
     while (true) {
         if (GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY)) {
             cal_val = REG_GET_FIELD(TIMG_RTCCALICFG1_REG(0), TIMG_RTC_CALI_VALUE);
+
+            /*The Fosc CLK of calibration circuit is divided by 32 for ECO2.
+              So we need to multiply the frequency of the Fosc for ECO2 and above chips by 32 times.
+              And ensure that this modification will not affect ECO0 and ECO1.*/
+            if (ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 2)) {
+                if (cal_clk == RTC_CAL_RC_FAST) {
+                    cal_val = cal_val >> 5;
+                }
+            }
             break;
         }
         if (GET_PERI_REG_MASK(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT)) {

components/hal/esp32h2/include/hal/clk_tree_ll.h

@@ -39,6 +39,13 @@ extern "C" {
     .dbuf = 1, \
 }
 
+/*
+Set the frequency division factor of ref_tick
+The FOSC of rtc calibration uses the 32 frequency division clock for ECO2,
+So the frequency division factor of ref_tick must be greater than or equal to 32
+*/
+#define REG_FOSC_TICK_NUM  255
+
 /**
  * @brief XTAL32K_CLK enable modes
  */
@@ -735,6 +742,14 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_rtc_slow_load_cal(v
     return REG_READ(RTC_SLOW_CLK_CAL_REG);
 }
 
+/*
+Set the frequency division factor of ref_tick
+*/
+static inline void clk_ll_rc_fast_tick_conf(void)
+{
+    PCR.ctrl_tick_conf.fosc_tick_num = REG_FOSC_TICK_NUM;
+}
+
 #ifdef __cplusplus
 }
 #endif