feat(esp_timer): Support systimer for ESP32P4

components/app_trace/sys_view/Sample/FreeRTOSV10.4/Config/esp/SEGGER_SYSVIEW_Config_FreeRTOS.c

@@ -137,7 +137,7 @@ gptimer_handle_t s_sv_gptimer;
 #endif
 
 #elif CONFIG_FREERTOS_SYSTICK_USES_SYSTIMER
-    #define SYSTICK_INTR_ID (ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE)
+    #define SYSTICK_INTR_ID (ETS_SYSTIMER_TARGET0_INTR_SOURCE)
 #endif // CONFIG_FREERTOS_TICK_SUPPORT_CORETIMER
 
 // SystemView is single core specific: it implies that SEGGER_SYSVIEW_LOCK()

components/esp_hw_support/hw_random.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2016-2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2016-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -34,6 +34,18 @@
 #define APB_CYCLE_WAIT_NUM (16)
 #endif
 
+#if CONFIG_IDF_TARGET_ESP32P4
+#include "esp_log.h"
+static const char *TAG = "hw_random";
+
+uint32_t IRAM_ATTR esp_random(void)
+{
+    // TODO: IDF-6522
+    ESP_EARLY_LOGW(TAG, "esp_random() has not been implemented yet");
+    return 0xDEADBEEF;
+}
+#else // !CONFIG_IDF_TARGET_ESP32P4
+
 uint32_t IRAM_ATTR esp_random(void)
 {
     /* The PRNG which implements WDEV_RANDOM register gets 2 bits
@@ -77,6 +89,7 @@ uint32_t IRAM_ATTR esp_random(void)
     last_ccount = ccount;
     return result ^ REG_READ(WDEV_RND_REG);
 }
+#endif //!CONFIG_IDF_TARGET_ESP32P4
 
 void esp_fill_random(void *buf, size_t len)
 {

components/esp_hw_support/port/esp32p4/systimer.c

@@ -7,9 +7,12 @@
 #include "esp_private/systimer.h"
 
 /**
- * //TODO: IDF-7487
  * @brief systimer's clock source is fixed to XTAL (40MHz), and has a fixed fractional divider (2.5).
  *        So the resolution of the systimer is 40MHz/2.5 = 16MHz.
+ *
+ * FPGA esp32p4 image:
+ *  - v10.0.0 (old) has 20MHz
+ *  - v12.0.0 has 16MHz
  */
 
 uint64_t systimer_ticks_to_us(uint64_t ticks)

components/esp_rom/patches/esp_rom_systimer.c

@@ -64,7 +64,7 @@ void systimer_hal_counter_value_advance(systimer_hal_context_t *hal, uint32_t co
 }
 #endif // CONFIG_IDF_TARGET_ESP32C2
 
-#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2
+#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4
 void systimer_hal_init(systimer_hal_context_t *hal)
 {
     hal->dev = &SYSTIMER;
@@ -78,6 +78,6 @@ void systimer_hal_deinit(systimer_hal_context_t *hal)
     systimer_ll_enable_clock(hal->dev, false);
     hal->dev = NULL;
 }
-#endif // CONFIG_IDF_TARGET_ESP32C6
+#endif // CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4
 
 #endif // CONFIG_HAL_SYSTIMER_USE_ROM_IMPL

components/esp_timer/src/esp_timer_impl_systimer.c

@@ -192,16 +192,9 @@ esp_err_t esp_timer_impl_init(intr_handler_t alarm_handler)
 #endif
                     | ESP_INTR_FLAG_IRAM;
 
-#if !CONFIG_IDF_TARGET_ESP32P4
-//TODO: IDF-7486
-    esp_err_t err = esp_intr_alloc(ETS_SYSTIMER_TARGET2_EDGE_INTR_SOURCE, isr_flags,
-                                   &timer_alarm_isr, NULL,
-                                   &s_timer_interrupt_handle[(ISR_HANDLERS == 1) ? 0 : xPortGetCoreID()]);
-#else
     esp_err_t err = esp_intr_alloc(ETS_SYSTIMER_TARGET2_INTR_SOURCE, isr_flags,
                                    &timer_alarm_isr, NULL,
                                    &s_timer_interrupt_handle[(ISR_HANDLERS == 1) ? 0 : xPortGetCoreID()]);
-#endif
     if (err != ESP_OK) {
         ESP_EARLY_LOGE(TAG, "esp_intr_alloc failed (0x%x)", err);
         return err;

components/esp_timer/test_apps/main/test_esp_timer_light_sleep.c

@@ -13,7 +13,7 @@
 #include "esp_rom_sys.h"
 #include "esp_sleep.h"
 
-#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32C6) // TODO IDF-6770
+#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32P4) // TODO IDF-7528
 
 static void timer_cb1(void *arg)
 {
@@ -53,4 +53,4 @@ TEST_CASE("Test the periodic timer does not handle lost events during light slee
     TEST_ESP_OK(esp_timer_delete(periodic_timer));
 }
 
-#endif //#!TEMPORARY_DISABLED_FOR_TARGETS(ESP32C6)
+#endif //#!TEMPORARY_DISABLED_FOR_TARGETS(ESP32P4)

components/esp_timer/test_apps/main/test_ets_timer.c

@@ -15,19 +15,7 @@
 #include "spi_flash_mmap.h"
 #include "esp_rom_sys.h"
 #include "esp_private/spi_flash_os.h"
-#if CONFIG_IDF_TARGET_ESP32
-#include "esp32/rom/ets_sys.h"  // for ETSTimer type
-#elif CONFIG_IDF_TARGET_ESP32S2
-#include "esp32s2/rom/ets_sys.h"
-#elif CONFIG_IDF_TARGET_ESP32S3
-#include "esp32s3/rom/ets_sys.h"
-#elif CONFIG_IDF_TARGET_ESP32C3
-#include "esp32c3/rom/ets_sys.h"
-#elif CONFIG_IDF_TARGET_ESP32C2
-#include "esp32c2/rom/ets_sys.h"
-#elif CONFIG_IDF_TARGET_ESP32C6
-#include "esp32c6/rom/ets_sys.h"
-#endif
+#include "rom/ets_sys.h"
 
 static void test_correct_delay_timer_func(void* arg)
 {

components/freertos/port_systick.c

@@ -21,7 +21,7 @@
         #define SYSTICK_INTR_ID     (ETS_INTERNAL_TIMER1_INTR_SOURCE + ETS_INTERNAL_INTR_SOURCE_OFF)
     #endif
 #else /* CONFIG_FREERTOS_SYSTICK_USES_SYSTIMER */
-        #define SYSTICK_INTR_ID     (ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE)
+        #define SYSTICK_INTR_ID     (ETS_SYSTIMER_TARGET0_INTR_SOURCE)
 #endif /* CONFIG_FREERTOS_SYSTICK_USES_CCOUNT */
 
 BaseType_t xPortSysTickHandler(void);
@@ -69,16 +69,7 @@ void vSystimerSetup(void)
     static systimer_hal_context_t systimer_hal;
     /* set system timer interrupt vector */
 
-    /**
-     * TODO: IDF-7487
-     * ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE is renamed to ETS_SYSTIMER_TARGET0_INTR_SOURCE.
-     * It's said that this interrupt is never an edge type, for previous all chips. You may need to check this and unify the name.
-     */
-#if !CONFIG_IDF_TARGET_ESP32P4
-    ESP_ERROR_CHECK(esp_intr_alloc(ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE + cpuid, ESP_INTR_FLAG_IRAM | level, SysTickIsrHandler, &systimer_hal, NULL));
-#else
     ESP_ERROR_CHECK(esp_intr_alloc(ETS_SYSTIMER_TARGET0_INTR_SOURCE + cpuid, ESP_INTR_FLAG_IRAM | level, SysTickIsrHandler, &systimer_hal, NULL));
-#endif
 
     if (cpuid == 0) {
         periph_module_enable(PERIPH_SYSTIMER_MODULE);

components/hal/esp32p4/include/hal/systimer_ll.h

@@ -10,6 +10,7 @@
 #include "soc/systimer_struct.h"
 #include "soc/clk_tree_defs.h"
 #include "hal/assert.h"
+#include "soc/hp_sys_clkrst_struct.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -18,8 +19,6 @@ extern "C" {
 // All these functions get invoked either from ISR or HAL that linked to IRAM.
 // Always inline these functions even no gcc optimization is applied.
 
-//TODO: IDF-7486
-
 /******************* Clock *************************/
 
 __attribute__((always_inline)) static inline void systimer_ll_enable_clock(systimer_dev_t *dev, bool en)
@@ -30,17 +29,24 @@ __attribute__((always_inline)) static inline void systimer_ll_enable_clock(systi
 // Set clock source: XTAL(default) or RC_FAST
 static inline void systimer_ll_set_clock_source(soc_periph_systimer_clk_src_t clk_src)
 {
+    HP_SYS_CLKRST.peri_clk_ctrl21.reg_systimer_clk_src_sel = (clk_src == SYSTIMER_CLK_SRC_RC_FAST) ? 1 : 0;
 }
 
+/// use a macro to wrap the function, force the caller to use it in a critical section
+/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
+#define systimer_ll_set_clock_source(...) (void)__DECLARE_RCC_ATOMIC_ENV; systimer_ll_set_clock_source(__VA_ARGS__)
+
+
 static inline soc_periph_systimer_clk_src_t systimer_ll_get_clock_source(void)
 {
-    return SYSTIMER_CLK_SRC_XTAL;
+    return (HP_SYS_CLKRST.peri_clk_ctrl21.reg_systimer_clk_src_sel == 1) ? SYSTIMER_CLK_SRC_RC_FAST : SYSTIMER_CLK_SRC_XTAL;
 }
 
 /********************** ETM *****************************/
 
 __attribute__((always_inline)) static inline void systimer_ll_enable_etm(systimer_dev_t *dev, bool en)
 {
+    dev->conf.etm_en = en;
 }
 
 /******************* Counter *************************/

components/hal/include/hal/systimer_hal.h

@@ -128,6 +128,9 @@ void systimer_hal_set_steps_per_tick(systimer_hal_context_t *hal, int clock_sour
 
 /**
  * @brief Set Systimer clock source
+ *
+ * Use this function as - PERIPH_RCC_ATOMIC(){ systimer_hal_set_clock_source(hal, clk_src); }
+ * due to Reset and Clock Control registers are mixing with other peripherals, so we need to use a critical section
  */
 void systimer_hal_set_clock_source(systimer_hal_context_t *hal, systimer_clock_source_t clk_src);
 

components/hal/systimer_hal.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -12,6 +12,7 @@
 #include "hal/systimer_types.h"
 #include "hal/assert.h"
 
+
 void systimer_hal_init(systimer_hal_context_t *hal)
 {
     hal->dev = &SYSTIMER;

components/soc/esp32c2/include/soc/interrupts.h

@@ -41,10 +41,13 @@ typedef enum {
     ETS_TG0_T0_LEVEL_INTR_SOURCE,               /**< interrupt of TIMER_GROUP0, TIMER0, level*/
     ETS_TG0_WDT_LEVEL_INTR_SOURCE,              /**< interrupt of TIMER_GROUP0, WATCH DOG, level*/
     ETS_CACHE_IA_INTR_SOURCE,                   /**< interrupt of Cache Invalied Access, LEVEL*/
-    ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE,      /**< interrupt of system timer 0, EDGE*/
-    ETS_SYSTIMER_TARGET1_EDGE_INTR_SOURCE,      /**< interrupt of system timer 1, EDGE*/
-    ETS_SYSTIMER_TARGET2_EDGE_INTR_SOURCE,      /**< interrupt of system timer 2, EDGE*/
-    ETS_SPI_MEM_REJECT_CACHE_INTR_SOURCE,       /**< interrupt of SPI0 Cache access and SPI1 access rejected, LEVEL*/
+    ETS_SYSTIMER_TARGET0_INTR_SOURCE,           /**< interrupt of system timer 0 */
+    ETS_SYSTIMER_TARGET1_INTR_SOURCE,           /**< interrupt of system timer 1 */
+    ETS_SYSTIMER_TARGET2_INTR_SOURCE,           /**< interrupt of system timer 2 */
+    ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE = ETS_SYSTIMER_TARGET0_INTR_SOURCE, /**< use ETS_SYSTIMER_TARGET0_INTR_SOURCE */
+    ETS_SYSTIMER_TARGET1_EDGE_INTR_SOURCE = ETS_SYSTIMER_TARGET1_INTR_SOURCE, /**< use ETS_SYSTIMER_TARGET1_INTR_SOURCE */
+    ETS_SYSTIMER_TARGET2_EDGE_INTR_SOURCE = ETS_SYSTIMER_TARGET2_INTR_SOURCE, /**< use ETS_SYSTIMER_TARGET2_INTR_SOURCE */
+    ETS_SPI_MEM_REJECT_CACHE_INTR_SOURCE = 29,  /**< interrupt of SPI0 Cache access and SPI1 access rejected, LEVEL*/
     ETS_ICACHE_PRELOAD0_INTR_SOURCE,            /**< interrupt of ICache perload operation, LEVEL*/
     ETS_ICACHE_SYNC0_INTR_SOURCE,               /**< interrupt of instruction cache sync done, LEVEL*/
     ETS_APB_ADC_INTR_SOURCE,                    /**< interrupt of APB ADC, LEVEL*/

components/soc/esp32c3/include/soc/interrupts.h

@@ -52,10 +52,13 @@ typedef enum {
     ETS_TG1_T0_LEVEL_INTR_SOURCE,               /**< interrupt of TIMER_GROUP1, TIMER0, level*/
     ETS_TG1_WDT_LEVEL_INTR_SOURCE,              /**< interrupt of TIMER_GROUP1, WATCHDOG, level*/
     ETS_CACHE_IA_INTR_SOURCE,                   /**< interrupt of Cache Invalied Access, LEVEL*/
-    ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE,      /**< interrupt of system timer 0, EDGE*/
-    ETS_SYSTIMER_TARGET1_EDGE_INTR_SOURCE,      /**< interrupt of system timer 1, EDGE*/
-    ETS_SYSTIMER_TARGET2_EDGE_INTR_SOURCE,      /**< interrupt of system timer 2, EDGE*/
-    ETS_SPI_MEM_REJECT_CACHE_INTR_SOURCE,       /**< interrupt of SPI0 Cache access and SPI1 access rejected, LEVEL*/
+    ETS_SYSTIMER_TARGET0_INTR_SOURCE,           /**< interrupt of system timer 0 */
+    ETS_SYSTIMER_TARGET1_INTR_SOURCE,           /**< interrupt of system timer 1 */
+    ETS_SYSTIMER_TARGET2_INTR_SOURCE,           /**< interrupt of system timer 2 */
+    ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE = ETS_SYSTIMER_TARGET0_INTR_SOURCE, /**< use ETS_SYSTIMER_TARGET0_INTR_SOURCE */
+    ETS_SYSTIMER_TARGET1_EDGE_INTR_SOURCE = ETS_SYSTIMER_TARGET1_INTR_SOURCE, /**< use ETS_SYSTIMER_TARGET1_INTR_SOURCE */
+    ETS_SYSTIMER_TARGET2_EDGE_INTR_SOURCE = ETS_SYSTIMER_TARGET2_INTR_SOURCE, /**< use ETS_SYSTIMER_TARGET2_INTR_SOURCE */
+    ETS_SPI_MEM_REJECT_CACHE_INTR_SOURCE = 40,  /**< interrupt of SPI0 Cache access and SPI1 access rejected, LEVEL*/
     ETS_ICACHE_PRELOAD0_INTR_SOURCE,            /**< interrupt of ICache perload operation, LEVEL*/
     ETS_ICACHE_SYNC0_INTR_SOURCE,               /**< interrupt of instruction cache sync done, LEVEL*/
     ETS_APB_ADC_INTR_SOURCE,                    /**< interrupt of APB ADC, LEVEL*/

components/soc/esp32c6/include/soc/interrupts.h

@@ -72,10 +72,13 @@ typedef enum {
     ETS_TG1_T0_LEVEL_INTR_SOURCE,               /**< interrupt of TIMER_GROUP1, TIMER0, level*/
     ETS_TG1_T1_LEVEL_INTR_SOURCE,               /**< interrupt of TIMER_GROUP1, TIMER1, level*/
     ETS_TG1_WDT_LEVEL_INTR_SOURCE,              /**< interrupt of TIMER_GROUP1, WATCHDOG, level*/
-    ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE,      /**< interrupt of system timer 0, EDGE*/
-    ETS_SYSTIMER_TARGET1_EDGE_INTR_SOURCE,      /**< interrupt of system timer 1, EDGE*/
-    ETS_SYSTIMER_TARGET2_EDGE_INTR_SOURCE,      /**< interrupt of system timer 2, EDGE*/
-    ETS_APB_ADC_INTR_SOURCE,                    /**< interrupt of APB ADC, LEVEL*/
+    ETS_SYSTIMER_TARGET0_INTR_SOURCE,           /**< interrupt of system timer 0 */
+    ETS_SYSTIMER_TARGET1_INTR_SOURCE,           /**< interrupt of system timer 1 */
+    ETS_SYSTIMER_TARGET2_INTR_SOURCE,           /**< interrupt of system timer 2 */
+    ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE = ETS_SYSTIMER_TARGET0_INTR_SOURCE, /**< use ETS_SYSTIMER_TARGET0_INTR_SOURCE */
+    ETS_SYSTIMER_TARGET1_EDGE_INTR_SOURCE = ETS_SYSTIMER_TARGET1_INTR_SOURCE, /**< use ETS_SYSTIMER_TARGET1_INTR_SOURCE */
+    ETS_SYSTIMER_TARGET2_EDGE_INTR_SOURCE = ETS_SYSTIMER_TARGET2_INTR_SOURCE, /**< use ETS_SYSTIMER_TARGET2_INTR_SOURCE */
+    ETS_APB_ADC_INTR_SOURCE = 60,               /**< interrupt of APB ADC, LEVEL*/
     ETS_MCPWM0_INTR_SOURCE,                     /**< interrupt of MCPWM0, LEVEL*/
     ETS_PCNT_INTR_SOURCE,
     ETS_PARL_IO_INTR_SOURCE,

components/soc/esp32h2/include/soc/interrupts.h

@@ -60,10 +60,13 @@ typedef enum {
     ETS_TG0_WDT_LEVEL_INTR_SOURCE,              /**< interrupt of TIMER_GROUP0, WATCH DOG, level*/
     ETS_TG1_T0_LEVEL_INTR_SOURCE,               /**< interrupt of TIMER_GROUP1, TIMER0, level*/
     ETS_TG1_WDT_LEVEL_INTR_SOURCE,              /**< interrupt of TIMER_GROUP1, WATCHDOG, level*/
-    ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE,      /**< interrupt of system timer 0, EDGE*/
-    ETS_SYSTIMER_TARGET1_EDGE_INTR_SOURCE,      /**< interrupt of system timer 1, EDGE*/
-    ETS_SYSTIMER_TARGET2_EDGE_INTR_SOURCE,      /**< interrupt of system timer 2, EDGE*/
-    ETS_APB_ADC_INTR_SOURCE,                    /**< interrupt of APB ADC, LEVEL*/
+    ETS_SYSTIMER_TARGET0_INTR_SOURCE,           /**< interrupt of system timer 0 */
+    ETS_SYSTIMER_TARGET1_INTR_SOURCE,           /**< interrupt of system timer 1 */
+    ETS_SYSTIMER_TARGET2_INTR_SOURCE,           /**< interrupt of system timer 2 */
+    ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE = ETS_SYSTIMER_TARGET0_INTR_SOURCE, /**< use ETS_SYSTIMER_TARGET0_INTR_SOURCE */
+    ETS_SYSTIMER_TARGET1_EDGE_INTR_SOURCE = ETS_SYSTIMER_TARGET1_INTR_SOURCE, /**< use ETS_SYSTIMER_TARGET1_INTR_SOURCE */
+    ETS_SYSTIMER_TARGET2_EDGE_INTR_SOURCE = ETS_SYSTIMER_TARGET2_INTR_SOURCE, /**< use ETS_SYSTIMER_TARGET2_INTR_SOURCE */
+    ETS_APB_ADC_INTR_SOURCE = 48,               /**< interrupt of APB ADC, LEVEL*/
     ETS_MCPWM0_INTR_SOURCE,
     ETS_PCNT_INTR_SOURCE,
     ETS_PARL_IO_TX_INTR_SOURCE,

components/soc/esp32p4/include/soc/clk_tree_defs.h

@@ -155,7 +155,6 @@ typedef enum {
 
 //////////////////////////////////////////////////SYSTIMER//////////////////////////////////////////////////////////////
 
-//TODO: IDF-7486
 /**
  * @brief Type of SYSTIMER clock source
  */

components/soc/esp32p4/include/soc/systimer_reg.h

@@ -1,5 +1,5 @@
 /**
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
  *
  *  SPDX-License-Identifier: Apache-2.0
  */
@@ -12,7 +12,7 @@ extern "C" {
 #endif
 
 /** SYSTIMER_CONF_REG register
- *  SYSTIMER_CONF.
+ *  Configure system timer clock
  */
 #define SYSTIMER_CONF_REG (DR_REG_SYSTIMER_BASE + 0x0)
 /** SYSTIMER_SYSTIMER_CLK_FO : R/W; bitpos: [0]; default: 0;
@@ -20,100 +20,107 @@ extern "C" {
  */
 #define SYSTIMER_SYSTIMER_CLK_FO    (BIT(0))
 #define SYSTIMER_SYSTIMER_CLK_FO_M  (SYSTIMER_SYSTIMER_CLK_FO_V << SYSTIMER_SYSTIMER_CLK_FO_S)
-#define SYSTIMER_SYSTIMER_CLK_FO_V  0x00000001
+#define SYSTIMER_SYSTIMER_CLK_FO_V  0x00000001U
 #define SYSTIMER_SYSTIMER_CLK_FO_S  0
+/** SYSTIMER_ETM_EN : R/W; bitpos: [1]; default: 0;
+ *  enable systimer's etm task and event
+ */
+#define SYSTIMER_ETM_EN    (BIT(1))
+#define SYSTIMER_ETM_EN_M  (SYSTIMER_ETM_EN_V << SYSTIMER_ETM_EN_S)
+#define SYSTIMER_ETM_EN_V  0x00000001U
+#define SYSTIMER_ETM_EN_S  1
 /** SYSTIMER_TARGET2_WORK_EN : R/W; bitpos: [22]; default: 0;
  *  target2 work enable
  */
 #define SYSTIMER_TARGET2_WORK_EN    (BIT(22))
 #define SYSTIMER_TARGET2_WORK_EN_M  (SYSTIMER_TARGET2_WORK_EN_V << SYSTIMER_TARGET2_WORK_EN_S)
-#define SYSTIMER_TARGET2_WORK_EN_V  0x00000001
+#define SYSTIMER_TARGET2_WORK_EN_V  0x00000001U
 #define SYSTIMER_TARGET2_WORK_EN_S  22
 /** SYSTIMER_TARGET1_WORK_EN : R/W; bitpos: [23]; default: 0;
  *  target1 work enable
  */
 #define SYSTIMER_TARGET1_WORK_EN    (BIT(23))
 #define SYSTIMER_TARGET1_WORK_EN_M  (SYSTIMER_TARGET1_WORK_EN_V << SYSTIMER_TARGET1_WORK_EN_S)
-#define SYSTIMER_TARGET1_WORK_EN_V  0x00000001
+#define SYSTIMER_TARGET1_WORK_EN_V  0x00000001U
 #define SYSTIMER_TARGET1_WORK_EN_S  23
 /** SYSTIMER_TARGET0_WORK_EN : R/W; bitpos: [24]; default: 0;
  *  target0 work enable
  */
 #define SYSTIMER_TARGET0_WORK_EN    (BIT(24))
 #define SYSTIMER_TARGET0_WORK_EN_M  (SYSTIMER_TARGET0_WORK_EN_V << SYSTIMER_TARGET0_WORK_EN_S)
-#define SYSTIMER_TARGET0_WORK_EN_V  0x00000001
+#define SYSTIMER_TARGET0_WORK_EN_V  0x00000001U
 #define SYSTIMER_TARGET0_WORK_EN_S  24
 /** SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN : R/W; bitpos: [25]; default: 1;
  *  If timer unit1 is stalled when core1 stalled
  */
 #define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN    (BIT(25))
 #define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_M  (SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_V << SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_S)
-#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_V  0x00000001
+#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_V  0x00000001U
 #define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_S  25
 /** SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN : R/W; bitpos: [26]; default: 1;
  *  If timer unit1 is stalled when core0 stalled
  */
 #define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN    (BIT(26))
 #define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_M  (SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_V << SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_S)
-#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_V  0x00000001
+#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_V  0x00000001U
 #define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_S  26
 /** SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN : R/W; bitpos: [27]; default: 0;
  *  If timer unit0 is stalled when core1 stalled
  */
 #define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN    (BIT(27))
 #define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_M  (SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_V << SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_S)
-#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_V  0x00000001
+#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_V  0x00000001U
 #define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_S  27
 /** SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN : R/W; bitpos: [28]; default: 0;
  *  If timer unit0 is stalled when core0 stalled
  */
 #define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN    (BIT(28))
 #define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_M  (SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_V << SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_S)
-#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_V  0x00000001
+#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_V  0x00000001U
 #define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_S  28
 /** SYSTIMER_TIMER_UNIT1_WORK_EN : R/W; bitpos: [29]; default: 0;
  *  timer unit1 work enable
  */
 #define SYSTIMER_TIMER_UNIT1_WORK_EN    (BIT(29))
 #define SYSTIMER_TIMER_UNIT1_WORK_EN_M  (SYSTIMER_TIMER_UNIT1_WORK_EN_V << SYSTIMER_TIMER_UNIT1_WORK_EN_S)
-#define SYSTIMER_TIMER_UNIT1_WORK_EN_V  0x00000001
+#define SYSTIMER_TIMER_UNIT1_WORK_EN_V  0x00000001U
 #define SYSTIMER_TIMER_UNIT1_WORK_EN_S  29
 /** SYSTIMER_TIMER_UNIT0_WORK_EN : R/W; bitpos: [30]; default: 1;
  *  timer unit0 work enable
  */
 #define SYSTIMER_TIMER_UNIT0_WORK_EN    (BIT(30))
 #define SYSTIMER_TIMER_UNIT0_WORK_EN_M  (SYSTIMER_TIMER_UNIT0_WORK_EN_V << SYSTIMER_TIMER_UNIT0_WORK_EN_S)
-#define SYSTIMER_TIMER_UNIT0_WORK_EN_V  0x00000001
+#define SYSTIMER_TIMER_UNIT0_WORK_EN_V  0x00000001U
 #define SYSTIMER_TIMER_UNIT0_WORK_EN_S  30
 /** SYSTIMER_CLK_EN : R/W; bitpos: [31]; default: 0;
  *  register file clk gating
  */
 #define SYSTIMER_CLK_EN    (BIT(31))
 #define SYSTIMER_CLK_EN_M  (SYSTIMER_CLK_EN_V << SYSTIMER_CLK_EN_S)
-#define SYSTIMER_CLK_EN_V  0x00000001
+#define SYSTIMER_CLK_EN_V  0x00000001U
 #define SYSTIMER_CLK_EN_S  31
 
 /** SYSTIMER_UNIT0_OP_REG register
- *  SYSTIMER_UNIT0_OP.
+ *  system timer unit0 value update register
  */
 #define SYSTIMER_UNIT0_OP_REG (DR_REG_SYSTIMER_BASE + 0x4)
 /** SYSTIMER_TIMER_UNIT0_VALUE_VALID : R/SS/WTC; bitpos: [29]; default: 0;
- *  reg_timer_unit0_value_valid
+ *  timer value is sync and valid
  */
 #define SYSTIMER_TIMER_UNIT0_VALUE_VALID    (BIT(29))
 #define SYSTIMER_TIMER_UNIT0_VALUE_VALID_M  (SYSTIMER_TIMER_UNIT0_VALUE_VALID_V << SYSTIMER_TIMER_UNIT0_VALUE_VALID_S)
-#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_V  0x00000001
+#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_V  0x00000001U
 #define SYSTIMER_TIMER_UNIT0_VALUE_VALID_S  29
 /** SYSTIMER_TIMER_UNIT0_UPDATE : WT; bitpos: [30]; default: 0;
  *  update timer_unit0
  */
 #define SYSTIMER_TIMER_UNIT0_UPDATE    (BIT(30))
 #define SYSTIMER_TIMER_UNIT0_UPDATE_M  (SYSTIMER_TIMER_UNIT0_UPDATE_V << SYSTIMER_TIMER_UNIT0_UPDATE_S)
-#define SYSTIMER_TIMER_UNIT0_UPDATE_V  0x00000001
+#define SYSTIMER_TIMER_UNIT0_UPDATE_V  0x00000001U
 #define SYSTIMER_TIMER_UNIT0_UPDATE_S  30
 
 /** SYSTIMER_UNIT1_OP_REG register
- *  SYSTIMER_UNIT1_OP.
+ *  system timer unit1 value update register
  */
 #define SYSTIMER_UNIT1_OP_REG (DR_REG_SYSTIMER_BASE + 0x8)
 /** SYSTIMER_TIMER_UNIT1_VALUE_VALID : R/SS/WTC; bitpos: [29]; default: 0;
@@ -121,324 +128,324 @@ extern "C" {
  */
 #define SYSTIMER_TIMER_UNIT1_VALUE_VALID    (BIT(29))
 #define SYSTIMER_TIMER_UNIT1_VALUE_VALID_M  (SYSTIMER_TIMER_UNIT1_VALUE_VALID_V << SYSTIMER_TIMER_UNIT1_VALUE_VALID_S)
-#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_V  0x00000001
+#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_V  0x00000001U
 #define SYSTIMER_TIMER_UNIT1_VALUE_VALID_S  29
 /** SYSTIMER_TIMER_UNIT1_UPDATE : WT; bitpos: [30]; default: 0;
  *  update timer unit1
  */
 #define SYSTIMER_TIMER_UNIT1_UPDATE    (BIT(30))
 #define SYSTIMER_TIMER_UNIT1_UPDATE_M  (SYSTIMER_TIMER_UNIT1_UPDATE_V << SYSTIMER_TIMER_UNIT1_UPDATE_S)
-#define SYSTIMER_TIMER_UNIT1_UPDATE_V  0x00000001
+#define SYSTIMER_TIMER_UNIT1_UPDATE_V  0x00000001U
 #define SYSTIMER_TIMER_UNIT1_UPDATE_S  30
 
 /** SYSTIMER_UNIT0_LOAD_HI_REG register
- *  SYSTIMER_UNIT0_LOAD_HI.
+ *  system timer unit0 value high load register
  */
 #define SYSTIMER_UNIT0_LOAD_HI_REG (DR_REG_SYSTIMER_BASE + 0xc)
 /** SYSTIMER_TIMER_UNIT0_LOAD_HI : R/W; bitpos: [19:0]; default: 0;
- *  timer unit0 load high 32 bit
+ *  timer unit0 load high 20 bits
  */
-#define SYSTIMER_TIMER_UNIT0_LOAD_HI    0x000FFFFF
+#define SYSTIMER_TIMER_UNIT0_LOAD_HI    0x000FFFFFU
 #define SYSTIMER_TIMER_UNIT0_LOAD_HI_M  (SYSTIMER_TIMER_UNIT0_LOAD_HI_V << SYSTIMER_TIMER_UNIT0_LOAD_HI_S)
-#define SYSTIMER_TIMER_UNIT0_LOAD_HI_V  0x000FFFFF
+#define SYSTIMER_TIMER_UNIT0_LOAD_HI_V  0x000FFFFFU
 #define SYSTIMER_TIMER_UNIT0_LOAD_HI_S  0
 
 /** SYSTIMER_UNIT0_LOAD_LO_REG register
- *  SYSTIMER_UNIT0_LOAD_LO.
+ *  system timer unit0 value low load register
  */
 #define SYSTIMER_UNIT0_LOAD_LO_REG (DR_REG_SYSTIMER_BASE + 0x10)
 /** SYSTIMER_TIMER_UNIT0_LOAD_LO : R/W; bitpos: [31:0]; default: 0;
- *  timer unit0 load low 32 bit
+ *  timer unit0 load low 32 bits
  */
-#define SYSTIMER_TIMER_UNIT0_LOAD_LO    0xFFFFFFFF
+#define SYSTIMER_TIMER_UNIT0_LOAD_LO    0xFFFFFFFFU
 #define SYSTIMER_TIMER_UNIT0_LOAD_LO_M  (SYSTIMER_TIMER_UNIT0_LOAD_LO_V << SYSTIMER_TIMER_UNIT0_LOAD_LO_S)
-#define SYSTIMER_TIMER_UNIT0_LOAD_LO_V  0xFFFFFFFF
+#define SYSTIMER_TIMER_UNIT0_LOAD_LO_V  0xFFFFFFFFU
 #define SYSTIMER_TIMER_UNIT0_LOAD_LO_S  0
 
 /** SYSTIMER_UNIT1_LOAD_HI_REG register
- *  SYSTIMER_UNIT1_LOAD_HI.
+ *  system timer unit1 value high load register
  */
 #define SYSTIMER_UNIT1_LOAD_HI_REG (DR_REG_SYSTIMER_BASE + 0x14)
 /** SYSTIMER_TIMER_UNIT1_LOAD_HI : R/W; bitpos: [19:0]; default: 0;
- *  timer unit1 load high 32 bit
+ *  timer unit1 load high 20 bits
  */
-#define SYSTIMER_TIMER_UNIT1_LOAD_HI    0x000FFFFF
+#define SYSTIMER_TIMER_UNIT1_LOAD_HI    0x000FFFFFU
 #define SYSTIMER_TIMER_UNIT1_LOAD_HI_M  (SYSTIMER_TIMER_UNIT1_LOAD_HI_V << SYSTIMER_TIMER_UNIT1_LOAD_HI_S)
-#define SYSTIMER_TIMER_UNIT1_LOAD_HI_V  0x000FFFFF
+#define SYSTIMER_TIMER_UNIT1_LOAD_HI_V  0x000FFFFFU
 #define SYSTIMER_TIMER_UNIT1_LOAD_HI_S  0
 
 /** SYSTIMER_UNIT1_LOAD_LO_REG register
- *  SYSTIMER_UNIT1_LOAD_LO.
+ *  system timer unit1 value low load register
  */
 #define SYSTIMER_UNIT1_LOAD_LO_REG (DR_REG_SYSTIMER_BASE + 0x18)
 /** SYSTIMER_TIMER_UNIT1_LOAD_LO : R/W; bitpos: [31:0]; default: 0;
- *  timer unit1 load low 32 bit
+ *  timer unit1 load low 32 bits
  */
-#define SYSTIMER_TIMER_UNIT1_LOAD_LO    0xFFFFFFFF
+#define SYSTIMER_TIMER_UNIT1_LOAD_LO    0xFFFFFFFFU
 #define SYSTIMER_TIMER_UNIT1_LOAD_LO_M  (SYSTIMER_TIMER_UNIT1_LOAD_LO_V << SYSTIMER_TIMER_UNIT1_LOAD_LO_S)
-#define SYSTIMER_TIMER_UNIT1_LOAD_LO_V  0xFFFFFFFF
+#define SYSTIMER_TIMER_UNIT1_LOAD_LO_V  0xFFFFFFFFU
 #define SYSTIMER_TIMER_UNIT1_LOAD_LO_S  0
 
 /** SYSTIMER_TARGET0_HI_REG register
- *  SYSTIMER_TARGET0_HI.
+ *  system timer comp0 value high register
  */
 #define SYSTIMER_TARGET0_HI_REG (DR_REG_SYSTIMER_BASE + 0x1c)
 /** SYSTIMER_TIMER_TARGET0_HI : R/W; bitpos: [19:0]; default: 0;
- *  timer taget0 high 32 bit
+ *  timer taget0 high 20 bits
  */
-#define SYSTIMER_TIMER_TARGET0_HI    0x000FFFFF
+#define SYSTIMER_TIMER_TARGET0_HI    0x000FFFFFU
 #define SYSTIMER_TIMER_TARGET0_HI_M  (SYSTIMER_TIMER_TARGET0_HI_V << SYSTIMER_TIMER_TARGET0_HI_S)
-#define SYSTIMER_TIMER_TARGET0_HI_V  0x000FFFFF
+#define SYSTIMER_TIMER_TARGET0_HI_V  0x000FFFFFU
 #define SYSTIMER_TIMER_TARGET0_HI_S  0
 
 /** SYSTIMER_TARGET0_LO_REG register
- *  SYSTIMER_TARGET0_LO.
+ *  system timer comp0 value low register
  */
 #define SYSTIMER_TARGET0_LO_REG (DR_REG_SYSTIMER_BASE + 0x20)
 /** SYSTIMER_TIMER_TARGET0_LO : R/W; bitpos: [31:0]; default: 0;
- *  timer taget0 low 32 bit
+ *  timer taget0 low 32 bits
  */
-#define SYSTIMER_TIMER_TARGET0_LO    0xFFFFFFFF
+#define SYSTIMER_TIMER_TARGET0_LO    0xFFFFFFFFU
 #define SYSTIMER_TIMER_TARGET0_LO_M  (SYSTIMER_TIMER_TARGET0_LO_V << SYSTIMER_TIMER_TARGET0_LO_S)
-#define SYSTIMER_TIMER_TARGET0_LO_V  0xFFFFFFFF
+#define SYSTIMER_TIMER_TARGET0_LO_V  0xFFFFFFFFU
 #define SYSTIMER_TIMER_TARGET0_LO_S  0
 
 /** SYSTIMER_TARGET1_HI_REG register
- *  SYSTIMER_TARGET1_HI.
+ *  system timer comp1 value high register
  */
 #define SYSTIMER_TARGET1_HI_REG (DR_REG_SYSTIMER_BASE + 0x24)
 /** SYSTIMER_TIMER_TARGET1_HI : R/W; bitpos: [19:0]; default: 0;
- *  timer taget1 high 32 bit
+ *  timer taget1 high 20 bits
  */
-#define SYSTIMER_TIMER_TARGET1_HI    0x000FFFFF
+#define SYSTIMER_TIMER_TARGET1_HI    0x000FFFFFU
 #define SYSTIMER_TIMER_TARGET1_HI_M  (SYSTIMER_TIMER_TARGET1_HI_V << SYSTIMER_TIMER_TARGET1_HI_S)
-#define SYSTIMER_TIMER_TARGET1_HI_V  0x000FFFFF
+#define SYSTIMER_TIMER_TARGET1_HI_V  0x000FFFFFU
 #define SYSTIMER_TIMER_TARGET1_HI_S  0
 
 /** SYSTIMER_TARGET1_LO_REG register
- *  SYSTIMER_TARGET1_LO.
+ *  system timer comp1 value low register
  */
 #define SYSTIMER_TARGET1_LO_REG (DR_REG_SYSTIMER_BASE + 0x28)
 /** SYSTIMER_TIMER_TARGET1_LO : R/W; bitpos: [31:0]; default: 0;
- *  timer taget1 low 32 bit
+ *  timer taget1 low 32 bits
  */
-#define SYSTIMER_TIMER_TARGET1_LO    0xFFFFFFFF
+#define SYSTIMER_TIMER_TARGET1_LO    0xFFFFFFFFU
 #define SYSTIMER_TIMER_TARGET1_LO_M  (SYSTIMER_TIMER_TARGET1_LO_V << SYSTIMER_TIMER_TARGET1_LO_S)
-#define SYSTIMER_TIMER_TARGET1_LO_V  0xFFFFFFFF
+#define SYSTIMER_TIMER_TARGET1_LO_V  0xFFFFFFFFU
 #define SYSTIMER_TIMER_TARGET1_LO_S  0
 
 /** SYSTIMER_TARGET2_HI_REG register
- *  SYSTIMER_TARGET2_HI.
+ *  system timer comp2 value high register
  */
 #define SYSTIMER_TARGET2_HI_REG (DR_REG_SYSTIMER_BASE + 0x2c)
 /** SYSTIMER_TIMER_TARGET2_HI : R/W; bitpos: [19:0]; default: 0;
- *  timer taget2 high 32 bit
+ *  timer taget2 high 20 bits
  */
-#define SYSTIMER_TIMER_TARGET2_HI    0x000FFFFF
+#define SYSTIMER_TIMER_TARGET2_HI    0x000FFFFFU
 #define SYSTIMER_TIMER_TARGET2_HI_M  (SYSTIMER_TIMER_TARGET2_HI_V << SYSTIMER_TIMER_TARGET2_HI_S)
-#define SYSTIMER_TIMER_TARGET2_HI_V  0x000FFFFF
+#define SYSTIMER_TIMER_TARGET2_HI_V  0x000FFFFFU
 #define SYSTIMER_TIMER_TARGET2_HI_S  0
 
 /** SYSTIMER_TARGET2_LO_REG register
- *  SYSTIMER_TARGET2_LO.
+ *  system timer comp2 value low register
  */
 #define SYSTIMER_TARGET2_LO_REG (DR_REG_SYSTIMER_BASE + 0x30)
 /** SYSTIMER_TIMER_TARGET2_LO : R/W; bitpos: [31:0]; default: 0;
- *  timer taget2 low 32 bit
+ *  timer taget2 low 32 bits
  */
-#define SYSTIMER_TIMER_TARGET2_LO    0xFFFFFFFF
+#define SYSTIMER_TIMER_TARGET2_LO    0xFFFFFFFFU
 #define SYSTIMER_TIMER_TARGET2_LO_M  (SYSTIMER_TIMER_TARGET2_LO_V << SYSTIMER_TIMER_TARGET2_LO_S)
-#define SYSTIMER_TIMER_TARGET2_LO_V  0xFFFFFFFF
+#define SYSTIMER_TIMER_TARGET2_LO_V  0xFFFFFFFFU
 #define SYSTIMER_TIMER_TARGET2_LO_S  0
 
 /** SYSTIMER_TARGET0_CONF_REG register
- *  SYSTIMER_TARGET0_CONF.
+ *  system timer comp0 target mode register
  */
 #define SYSTIMER_TARGET0_CONF_REG (DR_REG_SYSTIMER_BASE + 0x34)
 /** SYSTIMER_TARGET0_PERIOD : R/W; bitpos: [25:0]; default: 0;
  *  target0 period
  */
-#define SYSTIMER_TARGET0_PERIOD    0x03FFFFFF
+#define SYSTIMER_TARGET0_PERIOD    0x03FFFFFFU
 #define SYSTIMER_TARGET0_PERIOD_M  (SYSTIMER_TARGET0_PERIOD_V << SYSTIMER_TARGET0_PERIOD_S)
-#define SYSTIMER_TARGET0_PERIOD_V  0x03FFFFFF
+#define SYSTIMER_TARGET0_PERIOD_V  0x03FFFFFFU
 #define SYSTIMER_TARGET0_PERIOD_S  0
 /** SYSTIMER_TARGET0_PERIOD_MODE : R/W; bitpos: [30]; default: 0;
  *  Set target0 to period mode
  */
 #define SYSTIMER_TARGET0_PERIOD_MODE    (BIT(30))
 #define SYSTIMER_TARGET0_PERIOD_MODE_M  (SYSTIMER_TARGET0_PERIOD_MODE_V << SYSTIMER_TARGET0_PERIOD_MODE_S)
-#define SYSTIMER_TARGET0_PERIOD_MODE_V  0x00000001
+#define SYSTIMER_TARGET0_PERIOD_MODE_V  0x00000001U
 #define SYSTIMER_TARGET0_PERIOD_MODE_S  30
 /** SYSTIMER_TARGET0_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0;
  *  select which unit to compare
  */
 #define SYSTIMER_TARGET0_TIMER_UNIT_SEL    (BIT(31))
 #define SYSTIMER_TARGET0_TIMER_UNIT_SEL_M  (SYSTIMER_TARGET0_TIMER_UNIT_SEL_V << SYSTIMER_TARGET0_TIMER_UNIT_SEL_S)
-#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_V  0x00000001
+#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_V  0x00000001U
 #define SYSTIMER_TARGET0_TIMER_UNIT_SEL_S  31
 
 /** SYSTIMER_TARGET1_CONF_REG register
- *  SYSTIMER_TARGET1_CONF.
+ *  system timer comp1 target mode register
  */
 #define SYSTIMER_TARGET1_CONF_REG (DR_REG_SYSTIMER_BASE + 0x38)
 /** SYSTIMER_TARGET1_PERIOD : R/W; bitpos: [25:0]; default: 0;
  *  target1 period
  */
-#define SYSTIMER_TARGET1_PERIOD    0x03FFFFFF
+#define SYSTIMER_TARGET1_PERIOD    0x03FFFFFFU
 #define SYSTIMER_TARGET1_PERIOD_M  (SYSTIMER_TARGET1_PERIOD_V << SYSTIMER_TARGET1_PERIOD_S)
-#define SYSTIMER_TARGET1_PERIOD_V  0x03FFFFFF
+#define SYSTIMER_TARGET1_PERIOD_V  0x03FFFFFFU
 #define SYSTIMER_TARGET1_PERIOD_S  0
 /** SYSTIMER_TARGET1_PERIOD_MODE : R/W; bitpos: [30]; default: 0;
  *  Set target1 to period mode
  */
 #define SYSTIMER_TARGET1_PERIOD_MODE    (BIT(30))
 #define SYSTIMER_TARGET1_PERIOD_MODE_M  (SYSTIMER_TARGET1_PERIOD_MODE_V << SYSTIMER_TARGET1_PERIOD_MODE_S)
-#define SYSTIMER_TARGET1_PERIOD_MODE_V  0x00000001
+#define SYSTIMER_TARGET1_PERIOD_MODE_V  0x00000001U
 #define SYSTIMER_TARGET1_PERIOD_MODE_S  30
 /** SYSTIMER_TARGET1_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0;
  *  select which unit to compare
  */
 #define SYSTIMER_TARGET1_TIMER_UNIT_SEL    (BIT(31))
 #define SYSTIMER_TARGET1_TIMER_UNIT_SEL_M  (SYSTIMER_TARGET1_TIMER_UNIT_SEL_V << SYSTIMER_TARGET1_TIMER_UNIT_SEL_S)
-#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_V  0x00000001
+#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_V  0x00000001U
 #define SYSTIMER_TARGET1_TIMER_UNIT_SEL_S  31
 
 /** SYSTIMER_TARGET2_CONF_REG register
- *  SYSTIMER_TARGET2_CONF.
+ *  system timer comp2 target mode register
  */
 #define SYSTIMER_TARGET2_CONF_REG (DR_REG_SYSTIMER_BASE + 0x3c)
 /** SYSTIMER_TARGET2_PERIOD : R/W; bitpos: [25:0]; default: 0;
  *  target2 period
  */
-#define SYSTIMER_TARGET2_PERIOD    0x03FFFFFF
+#define SYSTIMER_TARGET2_PERIOD    0x03FFFFFFU
 #define SYSTIMER_TARGET2_PERIOD_M  (SYSTIMER_TARGET2_PERIOD_V << SYSTIMER_TARGET2_PERIOD_S)
-#define SYSTIMER_TARGET2_PERIOD_V  0x03FFFFFF
+#define SYSTIMER_TARGET2_PERIOD_V  0x03FFFFFFU
 #define SYSTIMER_TARGET2_PERIOD_S  0
 /** SYSTIMER_TARGET2_PERIOD_MODE : R/W; bitpos: [30]; default: 0;
  *  Set target2 to period mode
  */
 #define SYSTIMER_TARGET2_PERIOD_MODE    (BIT(30))
 #define SYSTIMER_TARGET2_PERIOD_MODE_M  (SYSTIMER_TARGET2_PERIOD_MODE_V << SYSTIMER_TARGET2_PERIOD_MODE_S)
-#define SYSTIMER_TARGET2_PERIOD_MODE_V  0x00000001
+#define SYSTIMER_TARGET2_PERIOD_MODE_V  0x00000001U
 #define SYSTIMER_TARGET2_PERIOD_MODE_S  30
 /** SYSTIMER_TARGET2_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0;
  *  select which unit to compare
  */
 #define SYSTIMER_TARGET2_TIMER_UNIT_SEL    (BIT(31))
 #define SYSTIMER_TARGET2_TIMER_UNIT_SEL_M  (SYSTIMER_TARGET2_TIMER_UNIT_SEL_V << SYSTIMER_TARGET2_TIMER_UNIT_SEL_S)
-#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_V  0x00000001
+#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_V  0x00000001U
 #define SYSTIMER_TARGET2_TIMER_UNIT_SEL_S  31
 
 /** SYSTIMER_UNIT0_VALUE_HI_REG register
- *  SYSTIMER_UNIT0_VALUE_HI.
+ *  system timer unit0 value high register
  */
 #define SYSTIMER_UNIT0_VALUE_HI_REG (DR_REG_SYSTIMER_BASE + 0x40)
 /** SYSTIMER_TIMER_UNIT0_VALUE_HI : RO; bitpos: [19:0]; default: 0;
- *  timer read value high 32bit
+ *  timer read value high 20bits
  */
-#define SYSTIMER_TIMER_UNIT0_VALUE_HI    0x000FFFFF
+#define SYSTIMER_TIMER_UNIT0_VALUE_HI    0x000FFFFFU
 #define SYSTIMER_TIMER_UNIT0_VALUE_HI_M  (SYSTIMER_TIMER_UNIT0_VALUE_HI_V << SYSTIMER_TIMER_UNIT0_VALUE_HI_S)
-#define SYSTIMER_TIMER_UNIT0_VALUE_HI_V  0x000FFFFF
+#define SYSTIMER_TIMER_UNIT0_VALUE_HI_V  0x000FFFFFU
 #define SYSTIMER_TIMER_UNIT0_VALUE_HI_S  0
 
 /** SYSTIMER_UNIT0_VALUE_LO_REG register
- *  SYSTIMER_UNIT0_VALUE_LO.
+ *  system timer unit0 value low register
  */
 #define SYSTIMER_UNIT0_VALUE_LO_REG (DR_REG_SYSTIMER_BASE + 0x44)
 /** SYSTIMER_TIMER_UNIT0_VALUE_LO : RO; bitpos: [31:0]; default: 0;
- *  timer read value low 32bit
+ *  timer read value low 32bits
  */
-#define SYSTIMER_TIMER_UNIT0_VALUE_LO    0xFFFFFFFF
+#define SYSTIMER_TIMER_UNIT0_VALUE_LO    0xFFFFFFFFU
 #define SYSTIMER_TIMER_UNIT0_VALUE_LO_M  (SYSTIMER_TIMER_UNIT0_VALUE_LO_V << SYSTIMER_TIMER_UNIT0_VALUE_LO_S)
-#define SYSTIMER_TIMER_UNIT0_VALUE_LO_V  0xFFFFFFFF
+#define SYSTIMER_TIMER_UNIT0_VALUE_LO_V  0xFFFFFFFFU
 #define SYSTIMER_TIMER_UNIT0_VALUE_LO_S  0
 
 /** SYSTIMER_UNIT1_VALUE_HI_REG register
- *  SYSTIMER_UNIT1_VALUE_HI.
+ *  system timer unit1 value high register
  */
 #define SYSTIMER_UNIT1_VALUE_HI_REG (DR_REG_SYSTIMER_BASE + 0x48)
 /** SYSTIMER_TIMER_UNIT1_VALUE_HI : RO; bitpos: [19:0]; default: 0;
- *  timer read value high 32bit
+ *  timer read value high 20bits
  */
-#define SYSTIMER_TIMER_UNIT1_VALUE_HI    0x000FFFFF
+#define SYSTIMER_TIMER_UNIT1_VALUE_HI    0x000FFFFFU
 #define SYSTIMER_TIMER_UNIT1_VALUE_HI_M  (SYSTIMER_TIMER_UNIT1_VALUE_HI_V << SYSTIMER_TIMER_UNIT1_VALUE_HI_S)
-#define SYSTIMER_TIMER_UNIT1_VALUE_HI_V  0x000FFFFF
+#define SYSTIMER_TIMER_UNIT1_VALUE_HI_V  0x000FFFFFU
 #define SYSTIMER_TIMER_UNIT1_VALUE_HI_S  0
 
 /** SYSTIMER_UNIT1_VALUE_LO_REG register
- *  SYSTIMER_UNIT1_VALUE_LO.
+ *  system timer unit1 value low register
  */
 #define SYSTIMER_UNIT1_VALUE_LO_REG (DR_REG_SYSTIMER_BASE + 0x4c)
 /** SYSTIMER_TIMER_UNIT1_VALUE_LO : RO; bitpos: [31:0]; default: 0;
- *  timer read value low 32bit
+ *  timer read value low 32bits
  */
-#define SYSTIMER_TIMER_UNIT1_VALUE_LO    0xFFFFFFFF
+#define SYSTIMER_TIMER_UNIT1_VALUE_LO    0xFFFFFFFFU
 #define SYSTIMER_TIMER_UNIT1_VALUE_LO_M  (SYSTIMER_TIMER_UNIT1_VALUE_LO_V << SYSTIMER_TIMER_UNIT1_VALUE_LO_S)
-#define SYSTIMER_TIMER_UNIT1_VALUE_LO_V  0xFFFFFFFF
+#define SYSTIMER_TIMER_UNIT1_VALUE_LO_V  0xFFFFFFFFU
 #define SYSTIMER_TIMER_UNIT1_VALUE_LO_S  0
 
 /** SYSTIMER_COMP0_LOAD_REG register
- *  SYSTIMER_COMP0_LOAD.
+ *  system timer comp0 conf sync register
  */
 #define SYSTIMER_COMP0_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x50)
 /** SYSTIMER_TIMER_COMP0_LOAD : WT; bitpos: [0]; default: 0;
- *  timer comp0 load value
+ *  timer comp0 sync enable signal
  */
 #define SYSTIMER_TIMER_COMP0_LOAD    (BIT(0))
 #define SYSTIMER_TIMER_COMP0_LOAD_M  (SYSTIMER_TIMER_COMP0_LOAD_V << SYSTIMER_TIMER_COMP0_LOAD_S)
-#define SYSTIMER_TIMER_COMP0_LOAD_V  0x00000001
+#define SYSTIMER_TIMER_COMP0_LOAD_V  0x00000001U
 #define SYSTIMER_TIMER_COMP0_LOAD_S  0
 
 /** SYSTIMER_COMP1_LOAD_REG register
- *  SYSTIMER_COMP1_LOAD.
+ *  system timer comp1 conf sync register
  */
 #define SYSTIMER_COMP1_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x54)
 /** SYSTIMER_TIMER_COMP1_LOAD : WT; bitpos: [0]; default: 0;
- *  timer comp1 load value
+ *  timer comp1 sync enable signal
  */
 #define SYSTIMER_TIMER_COMP1_LOAD    (BIT(0))
 #define SYSTIMER_TIMER_COMP1_LOAD_M  (SYSTIMER_TIMER_COMP1_LOAD_V << SYSTIMER_TIMER_COMP1_LOAD_S)
-#define SYSTIMER_TIMER_COMP1_LOAD_V  0x00000001
+#define SYSTIMER_TIMER_COMP1_LOAD_V  0x00000001U
 #define SYSTIMER_TIMER_COMP1_LOAD_S  0
 
 /** SYSTIMER_COMP2_LOAD_REG register
- *  SYSTIMER_COMP2_LOAD.
+ *  system timer comp2 conf sync register
  */
 #define SYSTIMER_COMP2_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x58)
 /** SYSTIMER_TIMER_COMP2_LOAD : WT; bitpos: [0]; default: 0;
- *  timer comp2 load value
+ *  timer comp2 sync enable signal
  */
 #define SYSTIMER_TIMER_COMP2_LOAD    (BIT(0))
 #define SYSTIMER_TIMER_COMP2_LOAD_M  (SYSTIMER_TIMER_COMP2_LOAD_V << SYSTIMER_TIMER_COMP2_LOAD_S)
-#define SYSTIMER_TIMER_COMP2_LOAD_V  0x00000001
+#define SYSTIMER_TIMER_COMP2_LOAD_V  0x00000001U
 #define SYSTIMER_TIMER_COMP2_LOAD_S  0
 
 /** SYSTIMER_UNIT0_LOAD_REG register
- *  SYSTIMER_UNIT0_LOAD.
+ *  system timer unit0 conf sync register
  */
 #define SYSTIMER_UNIT0_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x5c)
 /** SYSTIMER_TIMER_UNIT0_LOAD : WT; bitpos: [0]; default: 0;
- *  timer unit0 load value
+ *  timer unit0 sync enable signal
  */
 #define SYSTIMER_TIMER_UNIT0_LOAD    (BIT(0))
 #define SYSTIMER_TIMER_UNIT0_LOAD_M  (SYSTIMER_TIMER_UNIT0_LOAD_V << SYSTIMER_TIMER_UNIT0_LOAD_S)
-#define SYSTIMER_TIMER_UNIT0_LOAD_V  0x00000001
+#define SYSTIMER_TIMER_UNIT0_LOAD_V  0x00000001U
 #define SYSTIMER_TIMER_UNIT0_LOAD_S  0
 
 /** SYSTIMER_UNIT1_LOAD_REG register
- *  SYSTIMER_UNIT1_LOAD.
+ *  system timer unit1 conf sync register
  */
 #define SYSTIMER_UNIT1_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x60)
 /** SYSTIMER_TIMER_UNIT1_LOAD : WT; bitpos: [0]; default: 0;
- *  timer unit1 load value
+ *  timer unit1 sync enable signal
  */
 #define SYSTIMER_TIMER_UNIT1_LOAD    (BIT(0))
 #define SYSTIMER_TIMER_UNIT1_LOAD_M  (SYSTIMER_TIMER_UNIT1_LOAD_V << SYSTIMER_TIMER_UNIT1_LOAD_S)
-#define SYSTIMER_TIMER_UNIT1_LOAD_V  0x00000001
+#define SYSTIMER_TIMER_UNIT1_LOAD_V  0x00000001U
 #define SYSTIMER_TIMER_UNIT1_LOAD_S  0
 
 /** SYSTIMER_INT_ENA_REG register
- *  SYSTIMER_INT_ENA.
+ *  systimer interrupt enable register
  */
 #define SYSTIMER_INT_ENA_REG (DR_REG_SYSTIMER_BASE + 0x64)
 /** SYSTIMER_TARGET0_INT_ENA : R/W; bitpos: [0]; default: 0;
@@ -446,25 +453,25 @@ extern "C" {
  */
 #define SYSTIMER_TARGET0_INT_ENA    (BIT(0))
 #define SYSTIMER_TARGET0_INT_ENA_M  (SYSTIMER_TARGET0_INT_ENA_V << SYSTIMER_TARGET0_INT_ENA_S)
-#define SYSTIMER_TARGET0_INT_ENA_V  0x00000001
+#define SYSTIMER_TARGET0_INT_ENA_V  0x00000001U
 #define SYSTIMER_TARGET0_INT_ENA_S  0
 /** SYSTIMER_TARGET1_INT_ENA : R/W; bitpos: [1]; default: 0;
  *  interupt1 enable
  */
 #define SYSTIMER_TARGET1_INT_ENA    (BIT(1))
 #define SYSTIMER_TARGET1_INT_ENA_M  (SYSTIMER_TARGET1_INT_ENA_V << SYSTIMER_TARGET1_INT_ENA_S)
-#define SYSTIMER_TARGET1_INT_ENA_V  0x00000001
+#define SYSTIMER_TARGET1_INT_ENA_V  0x00000001U
 #define SYSTIMER_TARGET1_INT_ENA_S  1
 /** SYSTIMER_TARGET2_INT_ENA : R/W; bitpos: [2]; default: 0;
  *  interupt2 enable
  */
 #define SYSTIMER_TARGET2_INT_ENA    (BIT(2))
 #define SYSTIMER_TARGET2_INT_ENA_M  (SYSTIMER_TARGET2_INT_ENA_V << SYSTIMER_TARGET2_INT_ENA_S)
-#define SYSTIMER_TARGET2_INT_ENA_V  0x00000001
+#define SYSTIMER_TARGET2_INT_ENA_V  0x00000001U
 #define SYSTIMER_TARGET2_INT_ENA_S  2
 
 /** SYSTIMER_INT_RAW_REG register
- *  SYSTIMER_INT_RAW.
+ *  systimer interrupt raw register
  */
 #define SYSTIMER_INT_RAW_REG (DR_REG_SYSTIMER_BASE + 0x68)
 /** SYSTIMER_TARGET0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
@@ -472,25 +479,25 @@ extern "C" {
  */
 #define SYSTIMER_TARGET0_INT_RAW    (BIT(0))
 #define SYSTIMER_TARGET0_INT_RAW_M  (SYSTIMER_TARGET0_INT_RAW_V << SYSTIMER_TARGET0_INT_RAW_S)
-#define SYSTIMER_TARGET0_INT_RAW_V  0x00000001
+#define SYSTIMER_TARGET0_INT_RAW_V  0x00000001U
 #define SYSTIMER_TARGET0_INT_RAW_S  0
 /** SYSTIMER_TARGET1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
  *  interupt1 raw
  */
 #define SYSTIMER_TARGET1_INT_RAW    (BIT(1))
 #define SYSTIMER_TARGET1_INT_RAW_M  (SYSTIMER_TARGET1_INT_RAW_V << SYSTIMER_TARGET1_INT_RAW_S)
-#define SYSTIMER_TARGET1_INT_RAW_V  0x00000001
+#define SYSTIMER_TARGET1_INT_RAW_V  0x00000001U
 #define SYSTIMER_TARGET1_INT_RAW_S  1
 /** SYSTIMER_TARGET2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
  *  interupt2 raw
  */
 #define SYSTIMER_TARGET2_INT_RAW    (BIT(2))
 #define SYSTIMER_TARGET2_INT_RAW_M  (SYSTIMER_TARGET2_INT_RAW_V << SYSTIMER_TARGET2_INT_RAW_S)
-#define SYSTIMER_TARGET2_INT_RAW_V  0x00000001
+#define SYSTIMER_TARGET2_INT_RAW_V  0x00000001U
 #define SYSTIMER_TARGET2_INT_RAW_S  2
 
 /** SYSTIMER_INT_CLR_REG register
- *  SYSTIMER_INT_CLR.
+ *  systimer interrupt clear register
  */
 #define SYSTIMER_INT_CLR_REG (DR_REG_SYSTIMER_BASE + 0x6c)
 /** SYSTIMER_TARGET0_INT_CLR : WT; bitpos: [0]; default: 0;
@@ -498,59 +505,131 @@ extern "C" {
  */
 #define SYSTIMER_TARGET0_INT_CLR    (BIT(0))
 #define SYSTIMER_TARGET0_INT_CLR_M  (SYSTIMER_TARGET0_INT_CLR_V << SYSTIMER_TARGET0_INT_CLR_S)
-#define SYSTIMER_TARGET0_INT_CLR_V  0x00000001
+#define SYSTIMER_TARGET0_INT_CLR_V  0x00000001U
 #define SYSTIMER_TARGET0_INT_CLR_S  0
 /** SYSTIMER_TARGET1_INT_CLR : WT; bitpos: [1]; default: 0;
  *  interupt1 clear
  */
 #define SYSTIMER_TARGET1_INT_CLR    (BIT(1))
 #define SYSTIMER_TARGET1_INT_CLR_M  (SYSTIMER_TARGET1_INT_CLR_V << SYSTIMER_TARGET1_INT_CLR_S)
-#define SYSTIMER_TARGET1_INT_CLR_V  0x00000001
+#define SYSTIMER_TARGET1_INT_CLR_V  0x00000001U
 #define SYSTIMER_TARGET1_INT_CLR_S  1
 /** SYSTIMER_TARGET2_INT_CLR : WT; bitpos: [2]; default: 0;
  *  interupt2 clear
  */
 #define SYSTIMER_TARGET2_INT_CLR    (BIT(2))
 #define SYSTIMER_TARGET2_INT_CLR_M  (SYSTIMER_TARGET2_INT_CLR_V << SYSTIMER_TARGET2_INT_CLR_S)
-#define SYSTIMER_TARGET2_INT_CLR_V  0x00000001
+#define SYSTIMER_TARGET2_INT_CLR_V  0x00000001U
 #define SYSTIMER_TARGET2_INT_CLR_S  2
 
 /** SYSTIMER_INT_ST_REG register
- *  SYSTIMER_INT_ST.
+ *  systimer interrupt status register
  */
 #define SYSTIMER_INT_ST_REG (DR_REG_SYSTIMER_BASE + 0x70)
 /** SYSTIMER_TARGET0_INT_ST : RO; bitpos: [0]; default: 0;
- *  reg_target0_int_st
+ *  interupt0 status
  */
 #define SYSTIMER_TARGET0_INT_ST    (BIT(0))
 #define SYSTIMER_TARGET0_INT_ST_M  (SYSTIMER_TARGET0_INT_ST_V << SYSTIMER_TARGET0_INT_ST_S)
-#define SYSTIMER_TARGET0_INT_ST_V  0x00000001
+#define SYSTIMER_TARGET0_INT_ST_V  0x00000001U
 #define SYSTIMER_TARGET0_INT_ST_S  0
 /** SYSTIMER_TARGET1_INT_ST : RO; bitpos: [1]; default: 0;
- *  reg_target1_int_st
+ *  interupt1 status
  */
 #define SYSTIMER_TARGET1_INT_ST    (BIT(1))
 #define SYSTIMER_TARGET1_INT_ST_M  (SYSTIMER_TARGET1_INT_ST_V << SYSTIMER_TARGET1_INT_ST_S)
-#define SYSTIMER_TARGET1_INT_ST_V  0x00000001
+#define SYSTIMER_TARGET1_INT_ST_V  0x00000001U
 #define SYSTIMER_TARGET1_INT_ST_S  1
 /** SYSTIMER_TARGET2_INT_ST : RO; bitpos: [2]; default: 0;
- *  reg_target2_int_st
+ *  interupt2 status
  */
 #define SYSTIMER_TARGET2_INT_ST    (BIT(2))
 #define SYSTIMER_TARGET2_INT_ST_M  (SYSTIMER_TARGET2_INT_ST_V << SYSTIMER_TARGET2_INT_ST_S)
-#define SYSTIMER_TARGET2_INT_ST_V  0x00000001
+#define SYSTIMER_TARGET2_INT_ST_V  0x00000001U
 #define SYSTIMER_TARGET2_INT_ST_S  2
 
+/** SYSTIMER_REAL_TARGET0_LO_REG register
+ *  system timer comp0 actual target value low register
+ */
+#define SYSTIMER_REAL_TARGET0_LO_REG (DR_REG_SYSTIMER_BASE + 0x74)
+/** SYSTIMER_TARGET0_LO_RO : RO; bitpos: [31:0]; default: 0;
+ *  actual target value value low 32bits
+ */
+#define SYSTIMER_TARGET0_LO_RO    0xFFFFFFFFU
+#define SYSTIMER_TARGET0_LO_RO_M  (SYSTIMER_TARGET0_LO_RO_V << SYSTIMER_TARGET0_LO_RO_S)
+#define SYSTIMER_TARGET0_LO_RO_V  0xFFFFFFFFU
+#define SYSTIMER_TARGET0_LO_RO_S  0
+
+/** SYSTIMER_REAL_TARGET0_HI_REG register
+ *  system timer comp0 actual target value high register
+ */
+#define SYSTIMER_REAL_TARGET0_HI_REG (DR_REG_SYSTIMER_BASE + 0x78)
+/** SYSTIMER_TARGET0_HI_RO : RO; bitpos: [19:0]; default: 0;
+ *  actual target value value high 20bits
+ */
+#define SYSTIMER_TARGET0_HI_RO    0x000FFFFFU
+#define SYSTIMER_TARGET0_HI_RO_M  (SYSTIMER_TARGET0_HI_RO_V << SYSTIMER_TARGET0_HI_RO_S)
+#define SYSTIMER_TARGET0_HI_RO_V  0x000FFFFFU
+#define SYSTIMER_TARGET0_HI_RO_S  0
+
+/** SYSTIMER_REAL_TARGET1_LO_REG register
+ *  system timer comp1 actual target value low register
+ */
+#define SYSTIMER_REAL_TARGET1_LO_REG (DR_REG_SYSTIMER_BASE + 0x7c)
+/** SYSTIMER_TARGET1_LO_RO : RO; bitpos: [31:0]; default: 0;
+ *  actual target value value low 32bits
+ */
+#define SYSTIMER_TARGET1_LO_RO    0xFFFFFFFFU
+#define SYSTIMER_TARGET1_LO_RO_M  (SYSTIMER_TARGET1_LO_RO_V << SYSTIMER_TARGET1_LO_RO_S)
+#define SYSTIMER_TARGET1_LO_RO_V  0xFFFFFFFFU
+#define SYSTIMER_TARGET1_LO_RO_S  0
+
+/** SYSTIMER_REAL_TARGET1_HI_REG register
+ *  system timer comp1 actual target value high register
+ */
+#define SYSTIMER_REAL_TARGET1_HI_REG (DR_REG_SYSTIMER_BASE + 0x80)
+/** SYSTIMER_TARGET1_HI_RO : RO; bitpos: [19:0]; default: 0;
+ *  actual target value value high 20bits
+ */
+#define SYSTIMER_TARGET1_HI_RO    0x000FFFFFU
+#define SYSTIMER_TARGET1_HI_RO_M  (SYSTIMER_TARGET1_HI_RO_V << SYSTIMER_TARGET1_HI_RO_S)
+#define SYSTIMER_TARGET1_HI_RO_V  0x000FFFFFU
+#define SYSTIMER_TARGET1_HI_RO_S  0
+
+/** SYSTIMER_REAL_TARGET2_LO_REG register
+ *  system timer comp2 actual target value low register
+ */
+#define SYSTIMER_REAL_TARGET2_LO_REG (DR_REG_SYSTIMER_BASE + 0x84)
+/** SYSTIMER_TARGET2_LO_RO : RO; bitpos: [31:0]; default: 0;
+ *  actual target value value low 32bits
+ */
+#define SYSTIMER_TARGET2_LO_RO    0xFFFFFFFFU
+#define SYSTIMER_TARGET2_LO_RO_M  (SYSTIMER_TARGET2_LO_RO_V << SYSTIMER_TARGET2_LO_RO_S)
+#define SYSTIMER_TARGET2_LO_RO_V  0xFFFFFFFFU
+#define SYSTIMER_TARGET2_LO_RO_S  0
+
+/** SYSTIMER_REAL_TARGET2_HI_REG register
+ *  system timer comp2 actual target value high register
+ */
+#define SYSTIMER_REAL_TARGET2_HI_REG (DR_REG_SYSTIMER_BASE + 0x88)
+/** SYSTIMER_TARGET2_HI_RO : RO; bitpos: [19:0]; default: 0;
+ *  actual target value value high 20bits
+ */
+#define SYSTIMER_TARGET2_HI_RO    0x000FFFFFU
+#define SYSTIMER_TARGET2_HI_RO_M  (SYSTIMER_TARGET2_HI_RO_V << SYSTIMER_TARGET2_HI_RO_S)
+#define SYSTIMER_TARGET2_HI_RO_V  0x000FFFFFU
+#define SYSTIMER_TARGET2_HI_RO_S  0
+
 /** SYSTIMER_DATE_REG register
- *  SYSTIMER_DATE.
+ *  system timer version control register
  */
 #define SYSTIMER_DATE_REG (DR_REG_SYSTIMER_BASE + 0xfc)
-/** SYSTIMER_DATE : R/W; bitpos: [31:0]; default: 33579377;
- *  reg_date
+/** SYSTIMER_DATE : R/W; bitpos: [31:0]; default: 35655795;
+ *  systimer register version
  */
-#define SYSTIMER_DATE    0xFFFFFFFF
+#define SYSTIMER_DATE    0xFFFFFFFFU
 #define SYSTIMER_DATE_M  (SYSTIMER_DATE_V << SYSTIMER_DATE_S)
-#define SYSTIMER_DATE_V  0xFFFFFFFF
+#define SYSTIMER_DATE_V  0xFFFFFFFFU
 #define SYSTIMER_DATE_S  0
 
 #ifdef __cplusplus

components/soc/esp32p4/include/soc/systimer_struct.h

@@ -1,5 +1,5 @@
 /**
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
  *
  *  SPDX-License-Identifier: Apache-2.0
  */
@@ -10,73 +10,79 @@
 extern "C" {
 #endif
 
-/** Configuration Register */
+/** Group: SYSTEM TIMER CLK CONTROL REGISTER */
 /** Type of conf register
- *  SYSTIMER_CONF.
+ *  Configure system timer clock
  */
 typedef union {
     struct {
         /** systimer_clk_fo : R/W; bitpos: [0]; default: 0;
          *  systimer clock force on
          */
-        uint32_t systimer_clk_fo: 1;
-        uint32_t reserved_1: 21;
+        uint32_t systimer_clk_fo:1;
+        /** etm_en : R/W; bitpos: [1]; default: 0;
+         *  enable systimer's etm task and event
+         */
+        uint32_t etm_en:1;
+        uint32_t reserved_2:20;
         /** target2_work_en : R/W; bitpos: [22]; default: 0;
          *  target2 work enable
          */
-        uint32_t target2_work_en: 1;
+        uint32_t target2_work_en:1;
         /** target1_work_en : R/W; bitpos: [23]; default: 0;
          *  target1 work enable
          */
-        uint32_t target1_work_en: 1;
+        uint32_t target1_work_en:1;
         /** target0_work_en : R/W; bitpos: [24]; default: 0;
          *  target0 work enable
          */
-        uint32_t target0_work_en: 1;
+        uint32_t target0_work_en:1;
         /** timer_unit1_core1_stall_en : R/W; bitpos: [25]; default: 1;
          *  If timer unit1 is stalled when core1 stalled
          */
-        uint32_t timer_unit1_core1_stall_en: 1;
+        uint32_t timer_unit1_core1_stall_en:1;
         /** timer_unit1_core0_stall_en : R/W; bitpos: [26]; default: 1;
          *  If timer unit1 is stalled when core0 stalled
          */
-        uint32_t timer_unit1_core0_stall_en: 1;
+        uint32_t timer_unit1_core0_stall_en:1;
         /** timer_unit0_core1_stall_en : R/W; bitpos: [27]; default: 0;
          *  If timer unit0 is stalled when core1 stalled
          */
-        uint32_t timer_unit0_core1_stall_en: 1;
+        uint32_t timer_unit0_core1_stall_en:1;
         /** timer_unit0_core0_stall_en : R/W; bitpos: [28]; default: 0;
          *  If timer unit0 is stalled when core0 stalled
          */
-        uint32_t timer_unit0_core0_stall_en: 1;
+        uint32_t timer_unit0_core0_stall_en:1;
         /** timer_unit1_work_en : R/W; bitpos: [29]; default: 0;
          *  timer unit1 work enable
          */
-        uint32_t timer_unit1_work_en: 1;
+        uint32_t timer_unit1_work_en:1;
         /** timer_unit0_work_en : R/W; bitpos: [30]; default: 1;
          *  timer unit0 work enable
          */
-        uint32_t timer_unit0_work_en: 1;
+        uint32_t timer_unit0_work_en:1;
         /** clk_en : R/W; bitpos: [31]; default: 0;
          *  register file clk gating
          */
-        uint32_t clk_en: 1;
+        uint32_t clk_en:1;
     };
     uint32_t val;
 } systimer_conf_reg_t;
 
+
+/** Group: SYSTEM TIMER UNIT CONTROL AND CONFIGURATION REGISTER */
 /** Type of unit_op register
- *  SYSTIMER_UNIT_OP.
+ *  system timer unit value update register
  */
 typedef union {
     struct {
         uint32_t reserved_0: 29;
         /** timer_unit_value_valid : R/SS/WTC; bitpos: [29]; default: 0;
-         *  reg_timer_unit0_value_valid
+         *  timer value is sync and valid
          */
         uint32_t timer_unit_value_valid: 1;
         /** timer_unit_update : WT; bitpos: [30]; default: 0;
-         *  update timer_unit0
+         *  update timer_unit
          */
         uint32_t timer_unit_update: 1;
         uint32_t reserved31: 1;
@@ -85,13 +91,13 @@ typedef union {
 } systimer_unit_op_reg_t;
 
 /** Type of unit_load register
- *  SYSTIMER_UNIT_LOAD
+ *  system timer unit value high and low load register
  */
 typedef struct {
     union {
         struct {
             /** timer_unit_load_hi : R/W; bitpos: [19:0]; default: 0;
-             *  timer unit load high 32 bit
+             *  timer unit load high 20 bit
              */
             uint32_t timer_unit_load_hi: 20;
             uint32_t reserved20: 12;
@@ -109,14 +115,55 @@ typedef struct {
     } lo;
 } systimer_unit_load_val_reg_t;
 
+/** Type of unit_value_hi register
+ *  system timer unit value high and low register
+ */
+typedef struct {
+    union {
+        struct {
+            /** timer_unit_value_hi : RO; bitpos: [19:0]; default: 0;
+             *  timer read value high 20 bit
+             */
+            uint32_t timer_unit_value_hi: 20;
+            uint32_t reserved20: 12;
+        };
+        uint32_t val;
+    } hi;
+    union {
+        struct {
+            /** timer_unit_value_lo : RO; bitpos: [31:0]; default: 0;
+             *  timer read value low 32 bit
+             */
+            uint32_t timer_unit_value_lo: 32;
+        };
+        uint32_t val;
+    } lo;
+} systimer_unit_value_reg_t;
+
+/** Type of unit_load register
+ *  system timer unit conf sync register
+ */
+typedef union {
+    struct {
+        /** timer_unit_load : WT; bitpos: [0]; default: 0;
+         *  timer unit load value
+         */
+        uint32_t timer_unit_load: 1;
+        uint32_t reserved1: 31;
+    };
+    uint32_t val;
+} systimer_unit_load_reg_t;
+
+
+/** Group: SYSTEM TIMER COMP CONTROL AND CONFIGURATION REGISTER */
 /** Type of target register
- *  SYSTIMER_TARGET.
+ *  system timer comp value high and low register
  */
 typedef struct {
     union {
         struct {
             /** timer_target_hi : R/W; bitpos: [19:0]; default: 0;
-             *  timer target high 32 bit
+             *  timer target high 20 bit
              */
             uint32_t timer_target_hi: 20;
             uint32_t reserved20: 12;
@@ -135,7 +182,7 @@ typedef struct {
 } systimer_target_val_reg_t;
 
 /** Type of target_conf register
- *  SYSTIMER_TARGET_CONF.
+ *  system timer comp target mode register
  */
 typedef union {
     struct {
@@ -156,38 +203,13 @@ typedef union {
     uint32_t val;
 } systimer_target_conf_reg_t;
 
-/** Type of unit_value_hi register
- *  SYSTIMER_UNIT_VALUE_HI.
- */
-typedef struct {
-    union {
-        struct {
-            /** timer_unit_value_hi : RO; bitpos: [19:0]; default: 0;
-             *  timer read value high 20bit
-             */
-            uint32_t timer_unit_value_hi: 20;
-            uint32_t reserved20: 12;
-        };
-        uint32_t val;
-    } hi;
-    union {
-        struct {
-            /** timer_unit_value_lo : RO; bitpos: [31:0]; default: 0;
-             *  timer read value low 32bit
-             */
-            uint32_t timer_unit_value_lo: 32;
-        };
-        uint32_t val;
-    } lo;
-} systimer_unit_value_reg_t;
-
 /** Type of comp_load register
- *  SYSTIMER_COMP_LOAD.
+ *  system timer comp conf sync register
  */
 typedef union {
     struct {
         /** timer_comp_load : WT; bitpos: [0]; default: 0;
-         *  timer comp load value
+         *  timer comp sync enable signal
          */
         uint32_t timer_comp_load: 1;
         uint32_t reserved1: 31;
@@ -195,118 +217,132 @@ typedef union {
     uint32_t val;
 } systimer_comp_load_reg_t;
 
-/** Type of unit_load register
- *  SYSTIMER_UNIT_LOAD.
- */
-typedef union {
-    struct {
-        /** timer_unit_load : WT; bitpos: [0]; default: 0;
-         *  timer unit load value
-         */
-        uint32_t timer_unit_load: 1;
-        uint32_t reserved1: 31;
-    };
-    uint32_t val;
-} systimer_unit_load_reg_t;
 
-/** Interrupt Register */
+/** Group: SYSTEM TIMER INTERRUPT REGISTER */
 /** Type of int_ena register
- *  SYSTIMER_INT_ENA.
+ *  systimer interrupt enable register
  */
 typedef union {
     struct {
         /** target0_int_ena : R/W; bitpos: [0]; default: 0;
          *  interupt0 enable
          */
-        uint32_t target0_int_ena: 1;
+        uint32_t target0_int_ena:1;
         /** target1_int_ena : R/W; bitpos: [1]; default: 0;
          *  interupt1 enable
          */
-        uint32_t target1_int_ena: 1;
+        uint32_t target1_int_ena:1;
         /** target2_int_ena : R/W; bitpos: [2]; default: 0;
          *  interupt2 enable
          */
-        uint32_t target2_int_ena: 1;
+        uint32_t target2_int_ena:1;
         uint32_t reserved_3:29;
     };
     uint32_t val;
 } systimer_int_ena_reg_t;
 
 /** Type of int_raw register
- *  SYSTIMER_INT_RAW.
+ *  systimer interrupt raw register
  */
 typedef union {
     struct {
         /** target0_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
          *  interupt0 raw
          */
-        uint32_t target0_int_raw: 1;
+        uint32_t target0_int_raw:1;
         /** target1_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
          *  interupt1 raw
          */
-        uint32_t target1_int_raw: 1;
+        uint32_t target1_int_raw:1;
         /** target2_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
          *  interupt2 raw
          */
-        uint32_t target2_int_raw: 1;
+        uint32_t target2_int_raw:1;
         uint32_t reserved_3:29;
     };
     uint32_t val;
 } systimer_int_raw_reg_t;
 
 /** Type of int_clr register
- *  SYSTIMER_INT_CLR.
+ *  systimer interrupt clear register
  */
 typedef union {
     struct {
         /** target0_int_clr : WT; bitpos: [0]; default: 0;
          *  interupt0 clear
          */
-        uint32_t target0_int_clr: 1;
+        uint32_t target0_int_clr:1;
         /** target1_int_clr : WT; bitpos: [1]; default: 0;
          *  interupt1 clear
          */
-        uint32_t target1_int_clr: 1;
+        uint32_t target1_int_clr:1;
         /** target2_int_clr : WT; bitpos: [2]; default: 0;
          *  interupt2 clear
          */
-        uint32_t target2_int_clr: 1;
+        uint32_t target2_int_clr:1;
         uint32_t reserved_3:29;
     };
     uint32_t val;
 } systimer_int_clr_reg_t;
 
 /** Type of int_st register
- *  SYSTIMER_INT_ST.
+ *  systimer interrupt status register
  */
 typedef union {
     struct {
         /** target0_int_st : RO; bitpos: [0]; default: 0;
-         *  reg_target0_int_st
+         *  interupt0 status
          */
-        uint32_t target0_int_st: 1;
+        uint32_t target0_int_st:1;
         /** target1_int_st : RO; bitpos: [1]; default: 0;
-         *  reg_target1_int_st
+         *  interupt1 status
          */
-        uint32_t target1_int_st: 1;
+        uint32_t target1_int_st:1;
         /** target2_int_st : RO; bitpos: [2]; default: 0;
-         *  reg_target2_int_st
+         *  interupt2 status
          */
-        uint32_t target2_int_st: 1;
+        uint32_t target2_int_st:1;
         uint32_t reserved_3:29;
     };
     uint32_t val;
 } systimer_int_st_reg_t;
 
 
-/** Version Register */
+/** Group: SYSTEM TIMER COMP STATUS REGISTER */
+/** Type of real_target_hi/lo register
+ *  system timer comp actual target value low register
+ */
+typedef struct {
+    union {
+        struct {
+            /** target_lo_ro : RO; bitpos: [31:0]; default: 0;
+             *  actual target value value low 32 bits
+             */
+            uint32_t target_lo_ro: 32;
+        };
+        uint32_t val;
+    } lo;
+    union {
+        struct {
+            /** target_hi_ro : RO; bitpos: [19:0]; default: 0;
+             *  actual target value value high 20 bits
+             */
+            uint32_t target_hi_ro: 20;
+            uint32_t reserved20: 12;
+        };
+        uint32_t val;
+    } hi;
+} systimer_real_target_reg_t;
+
+
+/** Group: VERSION REGISTER */
 /** Type of date register
- *  SYSTIMER_DATE.
+ *  system timer version control register
  */
 typedef union {
     struct {
-        /** date : R/W; bitpos: [31:0]; default: 33579377;
-         *  reg_date
+        /** date : R/W; bitpos: [31:0]; default: 35655795;
+         *  systimer register version
          */
         uint32_t date: 32;
     };
@@ -327,40 +363,8 @@ typedef struct systimer_dev_t {
     volatile systimer_int_raw_reg_t int_raw;
     volatile systimer_int_clr_reg_t int_clr;
     volatile systimer_int_st_reg_t int_st;
-    uint32_t reserved_074;
-    uint32_t reserved_078;
-    uint32_t reserved_07c;
-    uint32_t reserved_080;
-    uint32_t reserved_084;
-    uint32_t reserved_088;
-    uint32_t reserved_08c;
-    uint32_t reserved_090;
-    uint32_t reserved_094;
-    uint32_t reserved_098;
-    uint32_t reserved_09c;
-    uint32_t reserved_0a0;
-    uint32_t reserved_0a4;
-    uint32_t reserved_0a8;
-    uint32_t reserved_0ac;
-    uint32_t reserved_0b0;
-    uint32_t reserved_0b4;
-    uint32_t reserved_0b8;
-    uint32_t reserved_0bc;
-    uint32_t reserved_0c0;
-    uint32_t reserved_0c4;
-    uint32_t reserved_0c8;
-    uint32_t reserved_0cc;
-    uint32_t reserved_0d0;
-    uint32_t reserved_0d4;
-    uint32_t reserved_0d8;
-    uint32_t reserved_0dc;
-    uint32_t reserved_0e0;
-    uint32_t reserved_0e4;
-    uint32_t reserved_0e8;
-    uint32_t reserved_0ec;
-    uint32_t reserved_0f0;
-    uint32_t reserved_0f4;
-    uint32_t reserved_0f8;
+    volatile systimer_real_target_reg_t real_target[3];
+    uint32_t reserved_08c[28];
     volatile systimer_date_reg_t date;
 } systimer_dev_t;
 

components/soc/esp32s2/include/soc/interrupts.h

@@ -85,10 +85,13 @@ typedef enum {
     ETS_TG1_WDT_EDGE_INTR_SOURCE,               /**< interrupt of TIMER_GROUP1, WATCHDOG, EDGE*/
     ETS_TG1_LACT_EDGE_INTR_SOURCE,              /**< interrupt of TIMER_GROUP0, LACT, EDGE*/
     ETS_CACHE_IA_INTR_SOURCE,                   /**< interrupt of Cache Invalied Access, LEVEL*/
-    ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE,      /**< interrupt of system timer 0, EDGE*/
-    ETS_SYSTIMER_TARGET1_EDGE_INTR_SOURCE,      /**< interrupt of system timer 1, EDGE*/
-    ETS_SYSTIMER_TARGET2_EDGE_INTR_SOURCE,      /**< interrupt of system timer 2, EDGE*/
-    ETS_ASSIST_DEBUG_INTR_SOURCE,               /**< interrupt of Assist debug module, LEVEL*/
+    ETS_SYSTIMER_TARGET0_INTR_SOURCE,           /**< interrupt of system timer 0 */
+    ETS_SYSTIMER_TARGET1_INTR_SOURCE,           /**< interrupt of system timer 1 */
+    ETS_SYSTIMER_TARGET2_INTR_SOURCE,           /**< interrupt of system timer 2 */
+    ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE = ETS_SYSTIMER_TARGET0_INTR_SOURCE, /**< use ETS_SYSTIMER_TARGET0_INTR_SOURCE */
+    ETS_SYSTIMER_TARGET1_EDGE_INTR_SOURCE = ETS_SYSTIMER_TARGET1_INTR_SOURCE, /**< use ETS_SYSTIMER_TARGET1_INTR_SOURCE */
+    ETS_SYSTIMER_TARGET2_EDGE_INTR_SOURCE = ETS_SYSTIMER_TARGET2_INTR_SOURCE, /**< use ETS_SYSTIMER_TARGET2_INTR_SOURCE */
+    ETS_ASSIST_DEBUG_INTR_SOURCE = 74,          /**< interrupt of Assist debug module, LEVEL*/
     ETS_PMS_PRO_IRAM0_ILG_INTR_SOURCE,          /**< interrupt of illegal IRAM1 access, LEVEL*/
     ETS_PMS_PRO_DRAM0_ILG_INTR_SOURCE,          /**< interrupt of illegal DRAM0 access, LEVEL*/
     ETS_PMS_PRO_DPORT_ILG_INTR_SOURCE,          /**< interrupt of illegal DPORT access, LEVEL*/

components/soc/esp32s3/include/soc/interrupts.h

@@ -70,10 +70,13 @@ typedef enum {
     ETS_TG1_T1_LEVEL_INTR_SOURCE,               /**< interrupt of TIMER_GROUP1, TIMER1, EDGE*/
     ETS_TG1_WDT_LEVEL_INTR_SOURCE,              /**< interrupt of TIMER_GROUP1, WATCHDOG, EDGE*/
     ETS_CACHE_IA_INTR_SOURCE,                   /**< interrupt of Cache Invalied Access, LEVEL*/
-    ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE,      /**< interrupt of system timer 0, EDGE*/
-    ETS_SYSTIMER_TARGET1_EDGE_INTR_SOURCE,      /**< interrupt of system timer 1, EDGE*/
-    ETS_SYSTIMER_TARGET2_EDGE_INTR_SOURCE,      /**< interrupt of system timer 2, EDGE*/
-    ETS_SPI_MEM_REJECT_CACHE_INTR_SOURCE,       /**< interrupt of SPI0 Cache access and SPI1 access rejected, LEVEL*/
+    ETS_SYSTIMER_TARGET0_INTR_SOURCE,           /**< interrupt of system timer 0 */
+    ETS_SYSTIMER_TARGET1_INTR_SOURCE,           /**< interrupt of system timer 1 */
+    ETS_SYSTIMER_TARGET2_INTR_SOURCE,           /**< interrupt of system timer 2 */
+    ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE = ETS_SYSTIMER_TARGET0_INTR_SOURCE, /**< use ETS_SYSTIMER_TARGET0_INTR_SOURCE */
+    ETS_SYSTIMER_TARGET1_EDGE_INTR_SOURCE = ETS_SYSTIMER_TARGET1_INTR_SOURCE, /**< use ETS_SYSTIMER_TARGET1_INTR_SOURCE */
+    ETS_SYSTIMER_TARGET2_EDGE_INTR_SOURCE = ETS_SYSTIMER_TARGET2_INTR_SOURCE, /**< use ETS_SYSTIMER_TARGET2_INTR_SOURCE */
+    ETS_SPI_MEM_REJECT_CACHE_INTR_SOURCE = 60,  /**< interrupt of SPI0 Cache access and SPI1 access rejected, LEVEL*/
     ETS_DCACHE_PRELOAD0_INTR_SOURCE,            /**< interrupt of DCache preload operation, LEVEL*/
     ETS_ICACHE_PRELOAD0_INTR_SOURCE,            /**< interrupt of ICache perload operation, LEVEL*/
     ETS_DCACHE_SYNC0_INTR_SOURCE,               /**< interrupt of data cache sync done, LEVEL*/

docs/docs_not_updated/esp32p4.txt

@@ -171,7 +171,6 @@ api-reference/system/chip_revision.rst
 api-reference/system/ulp_instruction_set.rst
 api-reference/system/async_memcpy.rst
 api-reference/system/random.rst
-api-reference/system/esp_timer.rst
 api-reference/system/esp_event.rst
 api-reference/system/system_time.rst
 api-reference/system/log.rst

docs/en/api-reference/system/esp_timer.rst

@@ -5,7 +5,7 @@ High Resolution Timer (ESP Timer)
 
 {IDF_TARGET_HR_TIMER:default = "SYSTIMER", esp32 = "LAC timer"}
 
-{IDF_TARGET_HR_TIMER_Resolution:default = "Not updated", esp32 = "64", esp32s2 = "64", esp32c3 = "52", esp32s3 = "52", esp32c2 = "52", esp32c6 = "52", esp32h2 = "52"}
+{IDF_TARGET_HR_TIMER_Resolution:default = "Not updated", esp32 = "64", esp32s2 = "64", esp32c3 = "52", esp32s3 = "52", esp32c2 = "52", esp32c6 = "52", esp32h2 = "52", esp32p4 = "52"}
 
 
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