Refactor: move regi2c_*.h header files from esp_hw_support to soc component

When creating G0 layer, some regi2c_*.h headers were moved out from
esp_hw_support (G1) to soc (G0). In order to be consistent with that change,
move all the remaining regi2c_*.h headers to soc too.

components/bootloader_support/src/esp32c3/bootloader_esp32c3.c

@@ -32,8 +32,8 @@
 #include "bootloader_flash_config.h"
 #include "bootloader_mem.h"
 #include "esp_private/regi2c_ctrl.h"
-#include "regi2c_lp_bias.h"
-#include "regi2c_bias.h"
+#include "soc/regi2c_lp_bias.h"
+#include "soc/regi2c_bias.h"
 #include "bootloader_console.h"
 #include "bootloader_flash_priv.h"
 #include "bootloader_soc.h"

components/esp_hw_support/port/esp32c2/rtc_init.c

@@ -15,8 +15,8 @@
 #include "soc/extmem_reg.h"
 #include "soc/system_reg.h"
 #include "regi2c_ctrl.h"
-#include "regi2c_dig_reg.h"
-#include "regi2c_lp_bias.h"
+#include "soc/regi2c_dig_reg.h"
+#include "soc/regi2c_lp_bias.h"
 #include "esp_hw_log.h"
 #include "esp_efuse.h"
 #include "esp_efuse_table.h"

components/esp_hw_support/port/esp32c2/rtc_sleep.c

@@ -18,8 +18,8 @@
 #include "esp32c2/rom/ets_sys.h"
 #include "esp32c2/rom/rtc.h"
 #include "regi2c_ctrl.h"
-#include "regi2c_lp_bias.h"
-#include "regi2c_dig_reg.h"
+#include "soc/regi2c_lp_bias.h"
+#include "soc/regi2c_dig_reg.h"
 #include "esp_efuse.h"
 
 /**

components/esp_hw_support/port/esp32c3/rtc_init.c

@@ -15,8 +15,8 @@
 #include "soc/extmem_reg.h"
 #include "soc/system_reg.h"
 #include "regi2c_ctrl.h"
-#include "regi2c_dig_reg.h"
-#include "regi2c_lp_bias.h"
+#include "soc/regi2c_dig_reg.h"
+#include "soc/regi2c_lp_bias.h"
 #include "esp_hw_log.h"
 #include "esp_efuse.h"
 #include "esp_efuse_table.h"

components/esp_hw_support/port/esp32c3/rtc_sleep.c

@@ -19,8 +19,8 @@
 #include "esp32c3/rom/ets_sys.h"
 #include "esp32c3/rom/rtc.h"
 #include "regi2c_ctrl.h"
-#include "regi2c_dig_reg.h"
-#include "regi2c_lp_bias.h"
+#include "soc/regi2c_dig_reg.h"
+#include "soc/regi2c_lp_bias.h"
 #include "esp_efuse.h"
 
 /**

components/esp_hw_support/port/esp32h2/rtc_sleep.c

@@ -19,8 +19,8 @@
 #include "esp32h2/rom/ets_sys.h"
 #include "esp32h2/rom/rtc.h"
 #include "regi2c_ctrl.h"
-#include "regi2c_bias.h"
-#include "regi2c_ulp.h"
+#include "soc/regi2c_bias.h"
+#include "soc/regi2c_ulp.h"
 #include "esp_efuse.h"
 #include "i2c_pmu.h"
 #include "esp_hw_log.h"

components/esp_hw_support/port/esp32s2/rtc_init.c

@@ -13,7 +13,7 @@
 #include "soc/gpio_reg.h"
 #include "soc/spi_mem_reg.h"
 #include "soc/extmem_reg.h"
-#include "regi2c_ulp.h"
+#include "soc/regi2c_ulp.h"
 #include "regi2c_ctrl.h"
 #include "esp_hw_log.h"
 #include "esp_efuse.h"

components/esp_hw_support/port/esp32s3/rtc_clk.c

@@ -20,7 +20,7 @@
 #include "hal/clk_tree_ll.h"
 #include "hal/regi2c_ctrl_ll.h"
 #include "esp_private/regi2c_ctrl.h"
-#include "regi2c_dig_reg.h"
+#include "soc/regi2c_dig_reg.h"
 #include "sdkconfig.h"
 
 static const char *TAG = "rtc_clk";

components/esp_hw_support/port/esp32s3/rtc_init.c

@@ -15,9 +15,9 @@
 #include "soc/extmem_reg.h"
 #include "soc/syscon_reg.h"
 #include "regi2c_ctrl.h"
-#include "regi2c_lp_bias.h"
-#include "regi2c_ulp.h"
-#include "regi2c_dig_reg.h"
+#include "soc/regi2c_lp_bias.h"
+#include "soc/regi2c_ulp.h"
+#include "soc/regi2c_dig_reg.h"
 #include "esp_hw_log.h"
 #include "esp_err.h"
 #include "esp_attr.h"

components/esp_hw_support/port/esp32s3/rtc_sleep.c

@@ -16,7 +16,7 @@
 #include "soc/nrx_reg.h"
 #include "soc/fe_reg.h"
 #include "regi2c_ctrl.h"
-#include "regi2c_dig_reg.h"
+#include "soc/regi2c_dig_reg.h"
 
 #define RTC_CNTL_MEM_FOLW_CPU (RTC_CNTL_SLOWMEM_FOLW_CPU | RTC_CNTL_FASTMEM_FOLW_CPU)
 

components/hal/esp32/include/hal/clk_tree_ll.h

@@ -14,9 +14,9 @@
 #include "soc/rtc_io_reg.h"
 #include "soc/dport_reg.h"
 #include "soc/syscon_reg.h"
-#include "esp_private/regi2c_ctrl.h"
-#include "regi2c_bbpll.h"
-#include "regi2c_apll.h"
+#include "hal/regi2c_ctrl.h"
+#include "soc/regi2c_bbpll.h"
+#include "soc/regi2c_apll.h"
 #include "hal/assert.h"
 #include "esp32/rom/rtc.h"
 

components/hal/esp32c2/include/hal/clk_tree_ll.h

@@ -12,8 +12,8 @@
 #include "soc/rtc.h"
 #include "soc/system_reg.h"
 #include "soc/rtc_cntl_reg.h"
-#include "esp_private/regi2c_ctrl.h"
-#include "regi2c_bbpll.h"
+#include "hal/regi2c_ctrl.h"
+#include "soc/regi2c_bbpll.h"
 #include "hal/assert.h"
 #include "hal/log.h"
 #include "esp32c2/rom/rtc.h"

components/hal/esp32c2/include/hal/temperature_sensor_ll.h

@@ -16,7 +16,7 @@
 
 #include <stdbool.h>
 #include <stdlib.h>
-#include "esp_private/regi2c_ctrl.h"
+#include "hal/regi2c_ctrl.h"
 #include "soc/regi2c_saradc.h"
 #include "soc/apb_saradc_struct.h"
 #include "soc/soc.h"

components/hal/esp32c3/include/hal/clk_tree_ll.h

@@ -12,8 +12,8 @@
 #include "soc/rtc.h"
 #include "soc/system_reg.h"
 #include "soc/rtc_cntl_reg.h"
-#include "esp_private/regi2c_ctrl.h"
-#include "regi2c_bbpll.h"
+#include "hal/regi2c_ctrl.h"
+#include "soc/regi2c_bbpll.h"
 #include "hal/assert.h"
 #include "hal/log.h"
 #include "esp32c3/rom/rtc.h"

components/hal/esp32c3/include/hal/temperature_sensor_ll.h

@@ -16,7 +16,7 @@
 
 #include <stdbool.h>
 #include <stdlib.h>
-#include "esp_private/regi2c_ctrl.h"
+#include "hal/regi2c_ctrl.h"
 #include "soc/regi2c_saradc.h"
 #include "soc/apb_saradc_struct.h"
 #include "soc/soc.h"

components/hal/esp32h2/include/hal/clk_tree_ll.h

@@ -12,8 +12,8 @@
 #include "soc/system_reg.h"
 #include "soc/clkrst_reg.h"
 #include "soc/rtc_cntl_reg.h"
-#include "esp_private/regi2c_ctrl.h"
-#include "regi2c_bbpll.h"
+#include "hal/regi2c_ctrl.h"
+#include "soc/regi2c_bbpll.h"
 #include "hal/assert.h"
 #include "hal/log.h"
 #include "esp32h2/rom/rtc.h"

components/hal/esp32h2/include/hal/temperature_sensor_ll.h

@@ -16,7 +16,7 @@
 
 #include <stdbool.h>
 #include <stdlib.h>
-#include "esp_private/regi2c_ctrl.h"
+#include "hal/regi2c_ctrl.h"
 #include "soc/regi2c_saradc.h"
 #include "soc/apb_saradc_struct.h"
 #include "soc/soc.h"

components/hal/esp32s2/include/hal/clk_tree_ll.h

@@ -13,9 +13,9 @@
 #include "soc/rtc_cntl_reg.h"
 #include "soc/dport_reg.h"
 #include "soc/syscon_reg.h"
-#include "esp_private/regi2c_ctrl.h"
-#include "regi2c_bbpll.h"
-#include "regi2c_apll.h"
+#include "hal/regi2c_ctrl.h"
+#include "soc/regi2c_bbpll.h"
+#include "soc/regi2c_apll.h"
 #include "hal/assert.h"
 #include "esp32s2/rom/rtc.h"
 

components/hal/esp32s2/include/hal/temperature_sensor_ll.h

@@ -15,7 +15,7 @@
 #pragma once
 
 #include <stdbool.h>
-#include "esp_private/regi2c_ctrl.h"
+#include "hal/regi2c_ctrl.h"
 #include "soc/regi2c_saradc.h"
 #include "soc/apb_saradc_struct.h"
 #include "soc/rtc_cntl_reg.h"

components/hal/esp32s3/include/hal/clk_tree_ll.h

@@ -12,8 +12,8 @@
 #include "soc/rtc.h"
 #include "soc/system_reg.h"
 #include "soc/rtc_cntl_reg.h"
-#include "esp_private/regi2c_ctrl.h"
-#include "regi2c_bbpll.h"
+#include "hal/regi2c_ctrl.h"
+#include "soc/regi2c_bbpll.h"
 #include "hal/assert.h"
 #include "hal/log.h"
 #include "esp32s3/rom/rtc.h"

components/hal/esp32s3/include/hal/temperature_sensor_ll.h

@@ -15,7 +15,7 @@
 #pragma once
 
 #include <stdbool.h>
-#include "esp_private/regi2c_ctrl.h"
+#include "hal/regi2c_ctrl.h"
 #include "soc/regi2c_saradc.h"
 #include "soc/apb_saradc_struct.h"
 #include "soc/rtc_cntl_reg.h"

components/soc/esp32c2/i2c_bbpll.h

@@ -1,175 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#pragma once
-
-/**
- * @file i2c_apll.h
- * @brief Register definitions for digital PLL (BBPLL)
- *
- * This file lists register fields of BBPLL, located on an internal configuration
- * bus. These definitions are used via macros defined in i2c_rtc_clk.h, by
- * rtc_clk_cpu_freq_set function in rtc_clk.c.
- */
-
-#define I2C_BBPLL           0x66
-#define I2C_BBPLL_HOSTID    1
-
-#define I2C_BBPLL_IR_CAL_DELAY        0
-#define I2C_BBPLL_IR_CAL_DELAY_MSB    3
-#define I2C_BBPLL_IR_CAL_DELAY_LSB    0
-
-#define I2C_BBPLL_IR_CAL_CK_DIV        0
-#define I2C_BBPLL_IR_CAL_CK_DIV_MSB    7
-#define I2C_BBPLL_IR_CAL_CK_DIV_LSB    4
-
-#define I2C_BBPLL_IR_CAL_EXT_CAP        1
-#define I2C_BBPLL_IR_CAL_EXT_CAP_MSB    3
-#define I2C_BBPLL_IR_CAL_EXT_CAP_LSB    0
-
-#define I2C_BBPLL_IR_CAL_ENX_CAP        1
-#define I2C_BBPLL_IR_CAL_ENX_CAP_MSB    4
-#define I2C_BBPLL_IR_CAL_ENX_CAP_LSB    4
-
-#define I2C_BBPLL_IR_CAL_RSTB        1
-#define I2C_BBPLL_IR_CAL_RSTB_MSB    5
-#define I2C_BBPLL_IR_CAL_RSTB_LSB    5
-
-#define I2C_BBPLL_IR_CAL_START        1
-#define I2C_BBPLL_IR_CAL_START_MSB    6
-#define I2C_BBPLL_IR_CAL_START_LSB    6
-
-#define I2C_BBPLL_IR_CAL_UNSTOP        1
-#define I2C_BBPLL_IR_CAL_UNSTOP_MSB    7
-#define I2C_BBPLL_IR_CAL_UNSTOP_LSB    7
-
-#define I2C_BBPLL_OC_REF_DIV        2
-#define I2C_BBPLL_OC_REF_DIV_MSB    3
-#define I2C_BBPLL_OC_REF_DIV_LSB    0
-
-#define I2C_BBPLL_OC_DCHGP        2
-#define I2C_BBPLL_OC_DCHGP_MSB    6
-#define I2C_BBPLL_OC_DCHGP_LSB    4
-
-#define I2C_BBPLL_OC_ENB_FCAL        2
-#define I2C_BBPLL_OC_ENB_FCAL_MSB    7
-#define I2C_BBPLL_OC_ENB_FCAL_LSB    7
-
-#define I2C_BBPLL_OC_DIV_7_0        3
-#define I2C_BBPLL_OC_DIV_7_0_MSB    7
-#define I2C_BBPLL_OC_DIV_7_0_LSB    0
-
-#define I2C_BBPLL_RSTB_DIV_ADC        4
-#define I2C_BBPLL_RSTB_DIV_ADC_MSB    0
-#define I2C_BBPLL_RSTB_DIV_ADC_LSB    0
-
-#define I2C_BBPLL_MODE_HF        4
-#define I2C_BBPLL_MODE_HF_MSB    1
-#define I2C_BBPLL_MODE_HF_LSB    1
-
-#define I2C_BBPLL_DIV_ADC        4
-#define I2C_BBPLL_DIV_ADC_MSB    3
-#define I2C_BBPLL_DIV_ADC_LSB    2
-
-#define I2C_BBPLL_DIV_DAC        4
-#define I2C_BBPLL_DIV_DAC_MSB    4
-#define I2C_BBPLL_DIV_DAC_LSB    4
-
-#define I2C_BBPLL_DIV_CPU        4
-#define I2C_BBPLL_DIV_CPU_MSB    5
-#define I2C_BBPLL_DIV_CPU_LSB    5
-
-#define I2C_BBPLL_OC_ENB_VCON        4
-#define I2C_BBPLL_OC_ENB_VCON_MSB    6
-#define I2C_BBPLL_OC_ENB_VCON_LSB    6
-
-#define I2C_BBPLL_OC_TSCHGP        4
-#define I2C_BBPLL_OC_TSCHGP_MSB    7
-#define I2C_BBPLL_OC_TSCHGP_LSB    7
-
-#define I2C_BBPLL_OC_DR1        5
-#define I2C_BBPLL_OC_DR1_MSB    2
-#define I2C_BBPLL_OC_DR1_LSB    0
-
-#define I2C_BBPLL_OC_DR3        5
-#define I2C_BBPLL_OC_DR3_MSB    6
-#define I2C_BBPLL_OC_DR3_LSB    4
-
-#define I2C_BBPLL_EN_USB        5
-#define I2C_BBPLL_EN_USB_MSB    7
-#define I2C_BBPLL_EN_USB_LSB    7
-
-#define I2C_BBPLL_OC_DCUR        6
-#define I2C_BBPLL_OC_DCUR_MSB    2
-#define I2C_BBPLL_OC_DCUR_LSB    0
-
-#define I2C_BBPLL_INC_CUR        6
-#define I2C_BBPLL_INC_CUR_MSB    3
-#define I2C_BBPLL_INC_CUR_LSB    3
-
-#define I2C_BBPLL_OC_DHREF_SEL        6
-#define I2C_BBPLL_OC_DHREF_SEL_MSB    5
-#define I2C_BBPLL_OC_DHREF_SEL_LSB    4
-
-#define I2C_BBPLL_OC_DLREF_SEL        6
-#define I2C_BBPLL_OC_DLREF_SEL_MSB    7
-#define I2C_BBPLL_OC_DLREF_SEL_LSB    6
-
-#define I2C_BBPLL_OR_CAL_CAP        8
-#define I2C_BBPLL_OR_CAL_CAP_MSB    3
-#define I2C_BBPLL_OR_CAL_CAP_LSB    0
-
-#define I2C_BBPLL_OR_CAL_UDF        8
-#define I2C_BBPLL_OR_CAL_UDF_MSB    4
-#define I2C_BBPLL_OR_CAL_UDF_LSB    4
-
-#define I2C_BBPLL_OR_CAL_OVF        8
-#define I2C_BBPLL_OR_CAL_OVF_MSB    5
-#define I2C_BBPLL_OR_CAL_OVF_LSB    5
-
-#define I2C_BBPLL_OR_CAL_END        8
-#define I2C_BBPLL_OR_CAL_END_MSB    6
-#define I2C_BBPLL_OR_CAL_END_LSB    6
-
-#define I2C_BBPLL_OR_LOCK        8
-#define I2C_BBPLL_OR_LOCK_MSB    7
-#define I2C_BBPLL_OR_LOCK_LSB    7
-
-#define I2C_BBPLL_BBADC_DELAY1        9
-#define I2C_BBPLL_BBADC_DELAY1_MSB    1
-#define I2C_BBPLL_BBADC_DELAY1_LSB    0
-
-#define I2C_BBPLL_BBADC_DELAY2        9
-#define I2C_BBPLL_BBADC_DELAY2_MSB    3
-#define I2C_BBPLL_BBADC_DELAY2_LSB    2
-
-#define I2C_BBPLL_BBADC_DVDD        9
-#define I2C_BBPLL_BBADC_DVDD_MSB    5
-#define I2C_BBPLL_BBADC_DVDD_LSB    4
-
-#define I2C_BBPLL_BBADC_DREF        9
-#define I2C_BBPLL_BBADC_DREF_MSB    7
-#define I2C_BBPLL_BBADC_DREF_LSB    6
-
-#define I2C_BBPLL_BBADC_DCUR        10
-#define I2C_BBPLL_BBADC_DCUR_MSB    1
-#define I2C_BBPLL_BBADC_DCUR_LSB    0
-
-#define I2C_BBPLL_BBADC_INPUT_SHORT        10
-#define I2C_BBPLL_BBADC_INPUT_SHORT_MSB    2
-#define I2C_BBPLL_BBADC_INPUT_SHORT_LSB    2
-
-#define I2C_BBPLL_ENT_PLL        10
-#define I2C_BBPLL_ENT_PLL_MSB    3
-#define I2C_BBPLL_ENT_PLL_LSB    3
-
-#define I2C_BBPLL_DTEST        10
-#define I2C_BBPLL_DTEST_MSB    5
-#define I2C_BBPLL_DTEST_LSB    4
-
-#define I2C_BBPLL_ENT_ADC        10
-#define I2C_BBPLL_ENT_ADC_MSB    7
-#define I2C_BBPLL_ENT_ADC_LSB    6

components/soc/esp32c3/i2c_bbpll.h

@@ -1,183 +0,0 @@
-// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#pragma once
-
-/**
- * @file i2c_apll.h
- * @brief Register definitions for digital PLL (BBPLL)
- *
- * This file lists register fields of BBPLL, located on an internal configuration
- * bus. These definitions are used via macros defined in i2c_rtc_clk.h, by
- * rtc_clk_cpu_freq_set function in rtc_clk.c.
- */
-
-#define I2C_BBPLL           0x66
-#define I2C_BBPLL_HOSTID    1
-
-#define I2C_BBPLL_IR_CAL_DELAY        0
-#define I2C_BBPLL_IR_CAL_DELAY_MSB    3
-#define I2C_BBPLL_IR_CAL_DELAY_LSB    0
-
-#define I2C_BBPLL_IR_CAL_CK_DIV        0
-#define I2C_BBPLL_IR_CAL_CK_DIV_MSB    7
-#define I2C_BBPLL_IR_CAL_CK_DIV_LSB    4
-
-#define I2C_BBPLL_IR_CAL_EXT_CAP        1
-#define I2C_BBPLL_IR_CAL_EXT_CAP_MSB    3
-#define I2C_BBPLL_IR_CAL_EXT_CAP_LSB    0
-
-#define I2C_BBPLL_IR_CAL_ENX_CAP        1
-#define I2C_BBPLL_IR_CAL_ENX_CAP_MSB    4
-#define I2C_BBPLL_IR_CAL_ENX_CAP_LSB    4
-
-#define I2C_BBPLL_IR_CAL_RSTB        1
-#define I2C_BBPLL_IR_CAL_RSTB_MSB    5
-#define I2C_BBPLL_IR_CAL_RSTB_LSB    5
-
-#define I2C_BBPLL_IR_CAL_START        1
-#define I2C_BBPLL_IR_CAL_START_MSB    6
-#define I2C_BBPLL_IR_CAL_START_LSB    6
-
-#define I2C_BBPLL_IR_CAL_UNSTOP        1
-#define I2C_BBPLL_IR_CAL_UNSTOP_MSB    7
-#define I2C_BBPLL_IR_CAL_UNSTOP_LSB    7
-
-#define I2C_BBPLL_OC_REF_DIV        2
-#define I2C_BBPLL_OC_REF_DIV_MSB    3
-#define I2C_BBPLL_OC_REF_DIV_LSB    0
-
-#define I2C_BBPLL_OC_DCHGP        2
-#define I2C_BBPLL_OC_DCHGP_MSB    6
-#define I2C_BBPLL_OC_DCHGP_LSB    4
-
-#define I2C_BBPLL_OC_ENB_FCAL        2
-#define I2C_BBPLL_OC_ENB_FCAL_MSB    7
-#define I2C_BBPLL_OC_ENB_FCAL_LSB    7
-
-#define I2C_BBPLL_OC_DIV_7_0        3
-#define I2C_BBPLL_OC_DIV_7_0_MSB    7
-#define I2C_BBPLL_OC_DIV_7_0_LSB    0
-
-#define I2C_BBPLL_RSTB_DIV_ADC        4
-#define I2C_BBPLL_RSTB_DIV_ADC_MSB    0
-#define I2C_BBPLL_RSTB_DIV_ADC_LSB    0
-
-#define I2C_BBPLL_MODE_HF        4
-#define I2C_BBPLL_MODE_HF_MSB    1
-#define I2C_BBPLL_MODE_HF_LSB    1
-
-#define I2C_BBPLL_DIV_ADC        4
-#define I2C_BBPLL_DIV_ADC_MSB    3
-#define I2C_BBPLL_DIV_ADC_LSB    2
-
-#define I2C_BBPLL_DIV_DAC        4
-#define I2C_BBPLL_DIV_DAC_MSB    4
-#define I2C_BBPLL_DIV_DAC_LSB    4
-
-#define I2C_BBPLL_DIV_CPU        4
-#define I2C_BBPLL_DIV_CPU_MSB    5
-#define I2C_BBPLL_DIV_CPU_LSB    5
-
-#define I2C_BBPLL_OC_ENB_VCON        4
-#define I2C_BBPLL_OC_ENB_VCON_MSB    6
-#define I2C_BBPLL_OC_ENB_VCON_LSB    6
-
-#define I2C_BBPLL_OC_TSCHGP        4
-#define I2C_BBPLL_OC_TSCHGP_MSB    7
-#define I2C_BBPLL_OC_TSCHGP_LSB    7
-
-#define I2C_BBPLL_OC_DR1        5
-#define I2C_BBPLL_OC_DR1_MSB    2
-#define I2C_BBPLL_OC_DR1_LSB    0
-
-#define I2C_BBPLL_OC_DR3        5
-#define I2C_BBPLL_OC_DR3_MSB    6
-#define I2C_BBPLL_OC_DR3_LSB    4
-
-#define I2C_BBPLL_EN_USB        5
-#define I2C_BBPLL_EN_USB_MSB    7
-#define I2C_BBPLL_EN_USB_LSB    7
-
-#define I2C_BBPLL_OC_DCUR        6
-#define I2C_BBPLL_OC_DCUR_MSB    2
-#define I2C_BBPLL_OC_DCUR_LSB    0
-
-#define I2C_BBPLL_INC_CUR        6
-#define I2C_BBPLL_INC_CUR_MSB    3
-#define I2C_BBPLL_INC_CUR_LSB    3
-
-#define I2C_BBPLL_OC_DHREF_SEL        6
-#define I2C_BBPLL_OC_DHREF_SEL_MSB    5
-#define I2C_BBPLL_OC_DHREF_SEL_LSB    4
-
-#define I2C_BBPLL_OC_DLREF_SEL        6
-#define I2C_BBPLL_OC_DLREF_SEL_MSB    7
-#define I2C_BBPLL_OC_DLREF_SEL_LSB    6
-
-#define I2C_BBPLL_OR_CAL_CAP        8
-#define I2C_BBPLL_OR_CAL_CAP_MSB    3
-#define I2C_BBPLL_OR_CAL_CAP_LSB    0
-
-#define I2C_BBPLL_OR_CAL_UDF        8
-#define I2C_BBPLL_OR_CAL_UDF_MSB    4
-#define I2C_BBPLL_OR_CAL_UDF_LSB    4
-
-#define I2C_BBPLL_OR_CAL_OVF        8
-#define I2C_BBPLL_OR_CAL_OVF_MSB    5
-#define I2C_BBPLL_OR_CAL_OVF_LSB    5
-
-#define I2C_BBPLL_OR_CAL_END        8
-#define I2C_BBPLL_OR_CAL_END_MSB    6
-#define I2C_BBPLL_OR_CAL_END_LSB    6
-
-#define I2C_BBPLL_OR_LOCK        8
-#define I2C_BBPLL_OR_LOCK_MSB    7
-#define I2C_BBPLL_OR_LOCK_LSB    7
-
-#define I2C_BBPLL_BBADC_DELAY1        9
-#define I2C_BBPLL_BBADC_DELAY1_MSB    1
-#define I2C_BBPLL_BBADC_DELAY1_LSB    0
-
-#define I2C_BBPLL_BBADC_DELAY2        9
-#define I2C_BBPLL_BBADC_DELAY2_MSB    3
-#define I2C_BBPLL_BBADC_DELAY2_LSB    2
-
-#define I2C_BBPLL_BBADC_DVDD        9
-#define I2C_BBPLL_BBADC_DVDD_MSB    5
-#define I2C_BBPLL_BBADC_DVDD_LSB    4
-
-#define I2C_BBPLL_BBADC_DREF        9
-#define I2C_BBPLL_BBADC_DREF_MSB    7
-#define I2C_BBPLL_BBADC_DREF_LSB    6
-
-#define I2C_BBPLL_BBADC_DCUR        10
-#define I2C_BBPLL_BBADC_DCUR_MSB    1
-#define I2C_BBPLL_BBADC_DCUR_LSB    0
-
-#define I2C_BBPLL_BBADC_INPUT_SHORT        10
-#define I2C_BBPLL_BBADC_INPUT_SHORT_MSB    2
-#define I2C_BBPLL_BBADC_INPUT_SHORT_LSB    2
-
-#define I2C_BBPLL_ENT_PLL        10
-#define I2C_BBPLL_ENT_PLL_MSB    3
-#define I2C_BBPLL_ENT_PLL_LSB    3
-
-#define I2C_BBPLL_DTEST        10
-#define I2C_BBPLL_DTEST_MSB    5
-#define I2C_BBPLL_DTEST_LSB    4
-
-#define I2C_BBPLL_ENT_ADC        10
-#define I2C_BBPLL_ENT_ADC_MSB    7
-#define I2C_BBPLL_ENT_ADC_LSB    6

components/soc/esp32h2/i2c_bbpll.h

@@ -1,120 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#pragma once
-
-/**
- * @file i2c_apll.h
- * @brief Register definitions for digital PLL (BBPLL)
- *
- * This file lists register fields of BBPLL, located on an internal configuration
- * bus. These definitions are used via macros defined in i2c_rtc_clk.h, by
- * rtc_clk_cpu_freq_set function in rtc_clk.c.
- */
-
-#define I2C_BBPLL           0x66
-#define I2C_BBPLL_HOSTID    0
-
-
-#define I2C_BBPLL_IR_CAL_DELAY        0
-#define I2C_BBPLL_IR_CAL_DELAY_MSB    3
-#define I2C_BBPLL_IR_CAL_DELAY_LSB    0
-
-#define I2C_BBPLL_IR_CAL_CK_DIV        0
-#define I2C_BBPLL_IR_CAL_CK_DIV_MSB    7
-#define I2C_BBPLL_IR_CAL_CK_DIV_LSB    4
-
-#define I2C_BBPLL_IR_CAL_EXT_CAP        1
-#define I2C_BBPLL_IR_CAL_EXT_CAP_MSB    3
-#define I2C_BBPLL_IR_CAL_EXT_CAP_LSB    0
-
-#define I2C_BBPLL_IR_CAL_ENX_CAP        1
-#define I2C_BBPLL_IR_CAL_ENX_CAP_MSB    4
-#define I2C_BBPLL_IR_CAL_ENX_CAP_LSB    4
-
-#define I2C_BBPLL_IR_CAL_RSTB        1
-#define I2C_BBPLL_IR_CAL_RSTB_MSB    5
-#define I2C_BBPLL_IR_CAL_RSTB_LSB    5
-
-#define I2C_BBPLL_IR_CAL_START        1
-#define I2C_BBPLL_IR_CAL_START_MSB    6
-#define I2C_BBPLL_IR_CAL_START_LSB    6
-
-#define I2C_BBPLL_IR_CAL_UNSTOP        1
-#define I2C_BBPLL_IR_CAL_UNSTOP_MSB    7
-#define I2C_BBPLL_IR_CAL_UNSTOP_LSB    7
-
-#define I2C_BBPLL_OC_REF_DIV        2
-#define I2C_BBPLL_OC_REF_DIV_MSB    3
-#define I2C_BBPLL_OC_REF_DIV_LSB    0
-
-#define I2C_BBPLL_OC_DIV        3
-#define I2C_BBPLL_OC_DIV_MSB    5
-#define I2C_BBPLL_OC_DIV_LSB    0
-
-#define I2C_BBPLL_OC_CHGP_DCUR        4
-#define I2C_BBPLL_OC_CHGP_DCUR_MSB    2
-#define I2C_BBPLL_OC_CHGP_DCUR_LSB    0
-
-#define I2C_BBPLL_OC_BUFF_DCUR        4
-#define I2C_BBPLL_OC_BUFF_DCUR_MSB    5
-#define I2C_BBPLL_OC_BUFF_DCUR_LSB    3
-
-#define I2C_BBPLL_OC_TSCHGP        4
-#define I2C_BBPLL_OC_TSCHGP_MSB    6
-#define I2C_BBPLL_OC_TSCHGP_LSB    6
-
-#define I2C_BBPLL_OC_ENB_FCAL        4
-#define I2C_BBPLL_OC_ENB_FCAL_MSB    7
-#define I2C_BBPLL_OC_ENB_FCAL_LSB    7
-
-#define I2C_BBPLL_OC_LPF_DR        5
-#define I2C_BBPLL_OC_LPF_DR_MSB    1
-#define I2C_BBPLL_OC_LPF_DR_LSB    0
-
-#define I2C_BBPLL_OC_VCO_DCUR        5
-#define I2C_BBPLL_OC_VCO_DCUR_MSB    3
-#define I2C_BBPLL_OC_VCO_DCUR_LSB    2
-
-#define I2C_BBPLL_OC_DHREF_SEL        5
-#define I2C_BBPLL_OC_DHREF_SEL_MSB    5
-#define I2C_BBPLL_OC_DHREF_SEL_LSB    4
-
-#define I2C_BBPLL_OC_DLREF_SEL        5
-#define I2C_BBPLL_OC_DLREF_SEL_MSB    7
-#define I2C_BBPLL_OC_DLREF_SEL_LSB    6
-
-#define I2C_BBPLL_OR_CAL_CAP        8
-#define I2C_BBPLL_OR_CAL_CAP_MSB    3
-#define I2C_BBPLL_OR_CAL_CAP_LSB    0
-
-#define I2C_BBPLL_OR_CAL_UDF        8
-#define I2C_BBPLL_OR_CAL_UDF_MSB    4
-#define I2C_BBPLL_OR_CAL_UDF_LSB    4
-
-#define I2C_BBPLL_OR_CAL_OVF        8
-#define I2C_BBPLL_OR_CAL_OVF_MSB    5
-#define I2C_BBPLL_OR_CAL_OVF_LSB    5
-
-#define I2C_BBPLL_OR_CAL_END        8
-#define I2C_BBPLL_OR_CAL_END_MSB    6
-#define I2C_BBPLL_OR_CAL_END_LSB    6
-
-#define I2C_BBPLL_OR_LOCK        8
-#define I2C_BBPLL_OR_LOCK_MSB    7
-#define I2C_BBPLL_OR_LOCK_LSB    7
-
-#define I2C_BBPLL_DTEST        10
-#define I2C_BBPLL_DTEST_MSB    1
-#define I2C_BBPLL_DTEST_LSB    0
-
-#define I2C_BBPLL_ENT_PLL        10
-#define I2C_BBPLL_ENT_PLL_MSB    2
-#define I2C_BBPLL_ENT_PLL_LSB    2
-
-#define I2C_BBPLL_DIV_CPU        10
-#define I2C_BBPLL_DIV_CPU_MSB    3
-#define I2C_BBPLL_DIV_CPU_LSB    3