feat(dw_gdma): initial low level driver

feat(dw_gdma): initial low level driver

components/hal/CMakeLists.txt

@@ -108,6 +108,10 @@ if(NOT BOOTLOADER_BUILD)
         list(APPEND srcs "gdma_hal_axi.c")
     endif()
 
+    if(CONFIG_SOC_DW_GDMA_SUPPORTED)
+        list(APPEND srcs "dw_gdma_hal.c")
+    endif()
+
     if(CONFIG_SOC_I2S_SUPPORTED)
         list(APPEND srcs "i2s_hal.c")
     endif()

components/hal/dw_gdma_hal.c

@@ -0,0 +1,15 @@
+/*
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdlib.h>
+#include <sys/param.h>
+#include "hal/dw_gdma_hal.h"
+#include "hal/dw_gdma_ll.h"
+
+void dw_gdma_hal_init(dw_gdma_hal_context_t *hal, const dw_gdma_hal_config_t *config)
+{
+    hal->dev = DW_GDMA_LL_GET_HW();
+}

components/hal/esp32p4/include/hal/dw_gdma_ll.h

@@ -0,0 +1,841 @@
+/*
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "hal/assert.h"
+#include "soc/dw_gdma_struct.h"
+#include "soc/hp_sys_clkrst_struct.h"
+
+#define DW_GDMA_LL_GET_HW() (&DW_GDMA)
+
+#define DW_GDMA_LL_MASTER_PORT_MIPI_DSI 0 // DW_GDMA master 0 can access DSI bridge
+#define DW_GDMA_LL_MASTER_PORT_MIPI_CSI 0 // DW_GDMA master 0 can access CSI bridge
+#define DW_GDMA_LL_MASTER_PORT_MEMORY   1 // DW_GDMA master 1 can only access L2MEM & ROM & MSPI Flash/PSRAM
+
+// Common event bitmap
+#define DW_GDMA_LL_COMMON_EVENT_SLVIF_DEC_ERR                  (0x1 << 0)
+#define DW_GDMA_LL_COMMON_EVENT_SLVIF_WR2RO_ERR                (0x1 << 1)
+#define DW_GDMA_LL_COMMON_EVENT_SLVIF_RD2WO_ERR                (0x1 << 2)
+#define DW_GDMA_LL_COMMON_EVENT_SLVIF_WRONHOLD_ERR             (0x1 << 3)
+#define DW_GDMA_LL_COMMON_EVENT_SLVIF_WRPARITY_ERR             (0x1 << 7)
+#define DW_GDMA_LL_COMMON_EVENT_SLVIF_UNDEFINEDREG_DEC_ERR     (0x1 << 8)
+#define DW_GDMA_LL_COMMON_EVENT_MXIF1_RCH0_ECCPROT_CORRERR     (0x1 << 9)
+#define DW_GDMA_LL_COMMON_EVENT_MXIF1_RCH0_ECCPROT_UNCORRERR   (0x1 << 10)
+#define DW_GDMA_LL_COMMON_EVENT_MXIF1_RECCPROT_CORRERR         (0x1 << 11)
+#define DW_GDMA_LL_COMMON_EVENT_MXIF1_RECCPROT_UNCORRERR       (0x1 << 12)
+#define DW_GDMA_LL_COMMON_EVENT_MXIF1_BCH_ECCPROT_CORRERR      (0x1 << 13)
+#define DW_GDMA_LL_COMMON_EVENT_MXIF1_BCH_ECCPROT_UNCORRERR    (0x1 << 14)
+#define DW_GDMA_LL_COMMON_EVENT_MXIF2_RCH0_ECCPROT_CORRERR     (0x1 << 15)
+#define DW_GDMA_LL_COMMON_EVENT_MXIF2_RCH0_ECCPROT_UNCORRERR   (0x1 << 16)
+#define DW_GDMA_LL_COMMON_EVENT_MXIF2_RECCPROT_CORRERR         (0x1 << 17)
+#define DW_GDMA_LL_COMMON_EVENT_MXIF2_RECCPROT_UNCORRERR       (0x1 << 18)
+#define DW_GDMA_LL_COMMON_EVENT_MXIF2_BCH_ECCPROT_CORRERR      (0x1 << 19)
+#define DW_GDMA_LL_COMMON_EVENT_MXIF2_BCH_ECCPROT_UNCORRERR    (0x1 << 20)
+
+// Channel event bitmap
+#define DW_GDMA_LL_CHANNEL_EVENT_BLOCK_TFR_DONE                 (0x1 << 0)
+#define DW_GDMA_LL_CHANNEL_EVENT_DMA_TFR_DONE                   (0x1 << 1)
+#define DW_GDMA_LL_CHANNEL_EVENT_SRC_TRANSCOMP                  (0x1 << 3)
+#define DW_GDMA_LL_CHANNEL_EVENT_DST_TRANSCOMP                  (0x1 << 4)
+#define DW_GDMA_LL_CHANNEL_EVENT_SRC_DEC_ERR                    (0x1 << 5)
+#define DW_GDMA_LL_CHANNEL_EVENT_DST_DEC_ERR                    (0x1 << 6)
+#define DW_GDMA_LL_CHANNEL_EVENT_SRC_SLV_ERR                    (0x1 << 7)
+#define DW_GDMA_LL_CHANNEL_EVENT_DST_SLV_ERR                    (0x1 << 8)
+#define DW_GDMA_LL_CHANNEL_EVENT_LLI_RD_DEC_ERR                 (0x1 << 9)
+#define DW_GDMA_LL_CHANNEL_EVENT_LLI_WR_DEC_ERR                 (0x1 << 10)
+#define DW_GDMA_LL_CHANNEL_EVENT_LLI_RD_SLV_ERR                 (0x1 << 11)
+#define DW_GDMA_LL_CHANNEL_EVENT_LLI_WR_SLV_ERR                 (0x1 << 12)
+#define DW_GDMA_LL_CHANNEL_EVENT_SHADOWREG_OR_LLI_INVALID_ERR   (0x1 << 13)
+#define DW_GDMA_LL_CHANNEL_EVENT_LOCK_CLEARED                   (0x1 << 27)
+#define DW_GDMA_LL_CHANNEL_EVENT_SRC_SUSPENDED                  (0x1 << 28)
+#define DW_GDMA_LL_CHANNEL_EVENT_SUSPENDED                      (0x1 << 29)
+#define DW_GDMA_LL_CHANNEL_EVENT_DISABLED                       (0x1 << 30)
+#define DW_GDMA_LL_CHANNEL_EVENT_ABORTED                        (0x1 << 31)
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief DW_GDMA transfer width
+ */
+typedef enum {
+    DW_GDMA_LL_TRANS_WIDTH_8,   /*!< Data transfer width: 8 bits */
+    DW_GDMA_LL_TRANS_WIDTH_16,  /*!< Data transfer width: 16 bits */
+    DW_GDMA_LL_TRANS_WIDTH_32,  /*!< Data transfer width: 32 bits */
+    DW_GDMA_LL_TRANS_WIDTH_64,  /*!< Data transfer width: 64 bits */
+    DW_GDMA_LL_TRANS_WIDTH_128, /*!< Data transfer width: 128 bits */
+    DW_GDMA_LL_TRANS_WIDTH_256, /*!< Data transfer width: 256 bits */
+    DW_GDMA_LL_TRANS_WIDTH_512, /*!< Data transfer width: 512 bits */
+} dw_gdma_ll_transfer_width_t;
+
+/**
+ * @brief DW_GDMA burst items
+ */
+typedef enum {
+    DW_GDMA_LL_BURST_ITEMS_1,    /*!< 1 data items in the burst transaction */
+    DW_GDMA_LL_BURST_ITEMS_4,    /*!< 4 data items in the burst transaction */
+    DW_GDMA_LL_BURST_ITEMS_8,    /*!< 8 data items in the burst transaction */
+    DW_GDMA_LL_BURST_ITEMS_16,   /*!< 16 data items in the burst transaction */
+    DW_GDMA_LL_BURST_ITEMS_32,   /*!< 32 data items in the burst transaction */
+    DW_GDMA_LL_BURST_ITEMS_64,   /*!< 64 data items in the burst transaction */
+    DW_GDMA_LL_BURST_ITEMS_128,  /*!< 128 data items in the burst transaction */
+    DW_GDMA_LL_BURST_ITEMS_256,  /*!< 256 data items in the burst transaction */
+    DW_GDMA_LL_BURST_ITEMS_512,  /*!< 512 data items in the burst transaction */
+    DW_GDMA_LL_BURST_ITEMS_1024, /*!< 1024 data items in the burst transaction */
+} dw_gdma_ll_burst_items_t;
+
+/**
+ * @brief Multi block transfer type
+ */
+typedef enum {
+    DW_GDMA_LL_MULTI_BLOCK_CONTIGUOUS,  /*!< Contiguous */
+    DW_GDMA_LL_MULTI_BLOCK_RELOAD,      /*!< Reload */
+    DW_GDMA_LL_MULTI_BLOCK_SHADOW_REG,  /*!< Shadow register */
+    DW_GDMA_LL_MULTI_BLOCK_LINK_LIST,   /*!< Link list */
+} dw_gdma_ll_multi_block_type_t;
+
+/**
+ * @brief Transfer type and flow control
+ */
+typedef enum {
+    DW_GDMA_LL_FLOW_M2M_DMAC, /*!< Flow: memory to memory, controller: DMA engine */
+    DW_GDMA_LL_FLOW_M2P_DMAC, /*!< Flow: memory to peripheral, controller: DMA engine */
+    DW_GDMA_LL_FLOW_P2M_DMAC, /*!< Flow: peripheral to memory, controller: DMA engine */
+    DW_GDMA_LL_FLOW_P2P_DMAC, /*!< Flow: peripheral to peripheral, controller: DMA engine */
+    DW_GDMA_LL_FLOW_P2M_SRC,  /*!< Flow: peripheral to memory, controller: source peripheral */
+    DW_GDMA_LL_FLOW_P2P_SRC,  /*!< Flow: peripheral to peripheral, controller: source peripheral */
+    DW_GDMA_LL_FLOW_M2P_DST,  /*!< Flow: memory to peripheral, controller: destination peripheral */
+    DW_GDMA_LL_FLOW_P2P_DST,  /*!< Flow: peripheral to peripheral, controller: destination peripheral */
+} dw_gdma_ll_trans_flow_t;
+
+/**
+ * @brief Handshake interface
+ */
+typedef enum {
+    DW_GDMA_LL_HANDSHAKE_HW, /*!< Transaction requests are initiated by hardware */
+    DW_GDMA_LL_HANDSHAKE_SW, /*!< Transaction requests are initiated by software */
+} dw_gdma_ll_handshake_interface_t;
+
+/**
+ * @brief Handshake number for different peripherals
+ */
+typedef enum {
+    DW_GDMA_LL_HW_HANDSHAKE_PERIPH_DSI, /*!< Handshake peripheral is DSI */
+    DW_GDMA_LL_HW_HANDSHAKE_PERIPH_CSI, /*!< Handshake peripheral is CSI */
+    DW_GDMA_LL_HW_HANDSHAKE_PERIPH_ISP, /*!< Handshake peripheral is ISP */
+} dw_gdma_ll_hw_handshake_periph_t;
+
+/**
+ * @brief Channel lock level
+ */
+typedef enum {
+    DW_GDMA_LL_LOCK_LEVEL_FULL_TRANS,  /*!< Lock over complete DMA transfer */
+    DW_GDMA_LL_LOCK_LEVEL_BLOCK_TRANS, /*!< Lock over DMA block transfer */
+} dw_gdma_ll_lock_level_t;
+
+/**
+ * @brief Enable the bus clock for the DMA module
+ */
+static inline void dw_gdma_ll_enable_bus_clock(int group_id, bool enable)
+{
+    (void) group_id;
+    HP_SYS_CLKRST.soc_clk_ctrl0.reg_gdma_cpu_clk_en = enable;
+    HP_SYS_CLKRST.soc_clk_ctrl1.reg_gdma_sys_clk_en = enable;
+}
+
+/// use a macro to wrap the function, force the caller to use it in a critical section
+/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
+#define dw_gdma_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; dw_gdma_ll_enable_bus_clock(__VA_ARGS__)
+
+/**
+ * @brief Reset the DMA module
+ */
+static inline void dw_gdma_ll_reset_register(int group_id)
+{
+    (void)group_id;
+    HP_SYS_CLKRST.hp_rst_en0.reg_rst_en_gdma = 1;
+    HP_SYS_CLKRST.hp_rst_en0.reg_rst_en_gdma = 0;
+}
+
+/// use a macro to wrap the function, force the caller to use it in a critical section
+/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
+#define dw_gdma_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; dw_gdma_ll_reset_register(__VA_ARGS__)
+
+/**
+ * @brief Reset the DMA controller by software
+ *
+ * @param dev Pointer to the DW_GDMA registers
+ */
+static inline void dw_gdma_ll_reset(dw_gdma_dev_t *dev)
+{
+    dev->reset0.dmac_rst = 1;
+    while (dev->reset0.dmac_rst);
+}
+
+/**
+ * @brief Enable the DMA controller
+ *
+ * @note If disable the controller while any channel is active, the controller won't stop
+ *       until all activity on all channels are terminated.
+ *
+ * @param dev Pointer to the DW_GDMA registers
+ * @param en True to enable, false to disable
+ */
+static inline void dw_gdma_ll_enable_controller(dw_gdma_dev_t *dev, bool en)
+{
+    dev->cfg0.dmac_en = en;
+}
+
+/**
+ * @brief Enable the interrupt generation globally
+ *
+ * @param dev Pointer to the DW_GDMA registers
+ * @param en True to enable, false to disable
+ */
+static inline void dw_gdma_ll_enable_intr_global(dw_gdma_dev_t *dev, bool en)
+{
+    dev->cfg0.int_en = en;
+}
+
+/**
+ * @brief Check if the common register interrupt is active
+ *
+ * @param dev Pointer to the DW_GDMA registers
+ * @return True: common register interrupt is active, False: common register interrupt is inactive
+ */
+static inline bool dw_gdma_ll_is_common_intr_active(dw_gdma_dev_t *dev)
+{
+    return dev->int_st0.commonreg_intstat;
+}
+
+/**
+ * @brief Clear the common interrupt by mask
+ *
+ * @param dev Pointer to the DW_GDMA registers
+ * @param mask Mask of the interrupt to clear
+ */
+static inline void dw_gdma_ll_clear_common_intr(dw_gdma_dev_t *dev, uint32_t mask)
+{
+    dev->common_int_clr0.val = mask;
+}
+
+/**
+ * @brief Enable the generation of common interrupt
+ *
+ * @param dev Pointer to the DW_GDMA registers
+ * @param mask Mask of the interrupt to enable
+ * @param en True to enable, false to disable
+ */
+static inline void dw_gdma_ll_enable_common_intr_generation(dw_gdma_dev_t *dev, uint32_t mask, bool en)
+{
+    if (en) {
+        dev->common_int_st_ena0.val |= mask;
+    } else {
+        dev->common_int_st_ena0.val &= ~mask;
+    }
+}
+
+/**
+ * @brief Enable the propagation of common interrupt to the CPU
+ *
+ * @param dev Pointer to the DW_GDMA registers
+ * @param mask Mask of the interrupt to enable
+ * @param en True to enable, false to disable
+ */
+static inline void dw_gdma_ll_enable_common_intr_propagation(dw_gdma_dev_t *dev, uint32_t mask, bool en)
+{
+    if (en) {
+        dev->common_int_sig_ena0.val |= mask;
+    } else {
+        dev->common_int_sig_ena0.val &= ~mask;
+    }
+}
+
+/**
+ * @brief Get the common interrupt status
+ *
+ * @note This register captures Slave interface access errors
+ *
+ * @param dev Pointer to the DW_GDMA registers
+ * @return Mask of the common interrupt status
+ */
+static inline uint32_t dw_gdma_ll_get_common_intr_status(dw_gdma_dev_t *dev)
+{
+    return dev->common_int_st0.val;
+}
+
+/**
+ * @brief Enable the generation of the channel interrupt
+ *
+ * @param dev Pointer to the DW_GDMA registers
+ * @param channel Channel number
+ * @param mask Mask of the interrupt to enable
+ * @param en True to enable, false to disable
+ */
+static inline void dw_gdma_ll_channel_enable_intr_generation(dw_gdma_dev_t *dev, uint8_t channel, uint32_t mask, bool en)
+{
+    if (en) {
+        dev->ch[channel].int_st_ena0.val |= mask;
+    } else {
+        dev->ch[channel].int_st_ena0.val &= ~mask;
+    }
+}
+
+/**
+ * @brief Enable the propagation of channel interrupt to the CPU
+ *
+ * @param dev Pointer to the DW_GDMA registers
+ * @param channel Channel number
+ * @param mask Mask of the interrupt to enable
+ * @param en True to enable, false to disable
+ */
+static inline void dw_gdma_ll_channel_enable_intr_propagation(dw_gdma_dev_t *dev, uint8_t channel, uint32_t mask, bool en)
+{
+    if (en) {
+        dev->ch[channel].int_sig_ena0.val |= mask;
+    } else {
+        dev->ch[channel].int_sig_ena0.val &= ~mask;
+    }
+}
+
+/**
+ * @brief Get the channel interrupt status
+ *
+ * @param dev Pointer to the DW_GDMA registers
+ * @param channel Channel number
+ * @return Mask of the channel interrupt status
+ */
+static inline uint32_t dw_gdma_ll_channel_get_inr_status(dw_gdma_dev_t *dev, uint8_t channel)
+{
+    return dev->ch[channel].int_st0.val;
+}
+
+/**
+ * @brief Clear the channel interrupt by mask
+ *
+ * @param dev Pointer to the DW_GDMA registers
+ * @param channel Channel number
+ * @param mask Mask of the interrupt to clear
+ */
+static inline void dw_gdma_ll_channel_clear_intr(dw_gdma_dev_t *dev, uint8_t channel, uint32_t mask)
+{
+    dev->ch[channel].int_clr0.val = mask;
+}
+
+/**
+ * @brief Enable the DMA channel to start the transfer
+ *
+ * @note When the DMA transfer finished, the channel will be disabled automatically
+ *
+ * @param dev Pointer to the DW_GDMA registers
+ * @param channel Channel number
+ * @param en True to enable, false to disable
+ */
+static inline void dw_gdma_ll_channel_enable(dw_gdma_dev_t *dev, uint8_t channel, bool en)
+{
+    if (en) {
+        dev->chen0.val = 0x101 << channel;
+    } else {
+        dev->chen0.val = 0x100 << channel;
+    }
+}
+
+/**
+ * @brief Suspend the DMA channel
+ *
+ * @note There is no guarantee that the current dma transaction will complete
+ * @note The suspend bit is cleared when the channel is disabled
+ *
+ * @param dev Pointer to the DW_GDMA registers
+ * @param channel Channel number
+ * @param en True to enter suspend mode, false to exit suspend mode
+ */
+static inline void dw_gdma_ll_channel_suspend(dw_gdma_dev_t *dev, uint8_t channel, bool en)
+{
+    if (en) {
+        dev->chen0.val = 0x1010000 << channel;
+    } else {
+        dev->chen0.val = 0x1000000 << channel;
+    }
+}
+
+/**
+ * @brief Abort the DMA channel
+ *
+ * @note Abort should only be used in situations where a particular channel hangs due to no response.
+ *
+ * @param dev Pointer to the DW_GDMA registers
+ * @param channel Channel number
+ */
+static inline void dw_gdma_ll_channel_abort(dw_gdma_dev_t *dev, uint8_t channel)
+{
+    // the abort bit clears itself after the abort is done
+    dev->chen1.val = 0x101 << channel;
+}
+
+/**
+ * @brief Check if the DMA channel interrupt is active
+ *
+ * @param dev Pointer to the DW_GDMA registers
+ * @param channel Channel number
+ * @return True: channel interrupt is active, False: channel interrupt is inactive
+ */
+static inline bool dw_gdma_ll_channel_is_interrupt_active(dw_gdma_dev_t *dev, uint8_t channel)
+{
+    return dev->int_st0.val & (1 << channel);
+}
+
+/**
+ * @brief Set the source address of the DMA transfer
+ *
+ * @param dev Pointer to the DW_GDMA registers
+ * @param channel Channel number
+ * @param src_addr Source address
+ */
+static inline void dw_gdma_ll_channel_set_src_addr(dw_gdma_dev_t *dev, uint8_t channel, uint32_t src_addr)
+{
+    dev->ch[channel].sar0.sar0 = src_addr;
+}
+
+/**
+ * @brief Set the destination address of the DMA transfer
+ *
+ * @param dev Pointer to the DW_GDMA registers
+ * @param channel Channel number
+ * @param dst_addr Destination address
+ */
+static inline void dw_gdma_ll_channel_set_dst_addr(dw_gdma_dev_t *dev, uint8_t channel, uint32_t dst_addr)
+{
+    dev->ch[channel].dar0.dar0 = dst_addr;
+}
+
+/**
+ * @brief Set the number of data to be transferred
+ *
+ * @note data_transfer_width * item_amount determins the total bytes in one block transfer.
+ *
+ * @param dev Pointer to the DW_GDMA registers
+ * @param channel Channel number
+ * @param item_numbers Number of transfer items
+ */
+static inline void dw_gdma_ll_channel_set_trans_amount(dw_gdma_dev_t *dev, uint8_t channel, uint32_t item_numbers)
+{
+    dev->ch[channel].block_ts0.block_ts = item_numbers - 1;
+}
+
+/**
+ * @brief Set the source master port
+ *
+ * @note The choice of master port depends on the location of the source data.
+ *
+ * @param dev Pointer to the DW_GDMA registers
+ * @param channel Channel number
+ * @param port Source master port
+ */
+static inline void dw_gdma_ll_channel_set_src_master_port(dw_gdma_dev_t *dev, uint8_t channel, uint32_t port)
+{
+    dev->ch[channel].ctl0.sms = port;
+}
+
+/**
+ * @brief Set the destination master port
+ *
+ * @note The choice of master port depends on the location of the destination data.
+ *
+ * @param dev Pointer to the DW_GDMA registers
+ * @param channel Channel number
+ * @param port Destination master port
+ */
+static inline void dw_gdma_ll_channel_set_dst_master_port(dw_gdma_dev_t *dev, uint8_t channel, uint32_t port)
+{
+    dev->ch[channel].ctl0.dms = port;
+}
+
+/**
+ * @brief Enable the source address increment
+ *
+ * @note Increase the source address by the data width after each transfer
+ *
+ * @param dev Pointer to the DW_GDMA registers
+ * @param channel Channel number
+ * @param en True to enable, false to disable
+ */
+static inline void dw_gdma_ll_channel_enable_src_addr_increment(dw_gdma_dev_t *dev, uint8_t channel, bool en)
+{
+    dev->ch[channel].ctl0.sinc = !en;
+}
+
+/**
+ * @brief Enable the destination address increment
+ *
+ * @note Increase the destination address by the data width after each transfer
+ *
+ * @param dev Pointer to the DW_GDMA registers
+ * @param channel Channel number
+ * @param en True to enable, false to disable
+ */
+static inline void dw_gdma_ll_channel_enable_dst_addr_increment(dw_gdma_dev_t *dev, uint8_t channel, bool en)
+{
+    dev->ch[channel].ctl0.dinc = !en;
+}
+
+/**
+ * @brief Set the transfer width of the source data
+ *
+ * @param dev Pointer to the DW_GDMA registers
+ * @param channel Channel number
+ * @param width Transfer width
+ */
+static inline void dw_gdma_ll_channel_set_src_trans_width(dw_gdma_dev_t *dev, uint8_t channel, dw_gdma_ll_transfer_width_t width)
+{
+    dev->ch[channel].ctl0.src_tr_width = width;
+}
+
+/**
+ * @brief Set the transfer width of the destination data
+ *
+ * @param dev Pointer to the DW_GDMA registers
+ * @param channel Channel number
+ * @param width Transfer width
+ */
+static inline void dw_gdma_ll_channel_set_dst_trans_width(dw_gdma_dev_t *dev, uint8_t channel, dw_gdma_ll_transfer_width_t width)
+{
+    dev->ch[channel].ctl0.dst_tr_width = width;
+}
+
+/**
+ * @brief Set the number of data items that can be transferred in a single burst transaction for the source master port
+ *
+ * @param dev Pointer to the DW_GDMA registers
+ * @param channel Channel number
+ * @param items Number of data items
+ */
+static inline void dw_gdma_ll_channel_set_src_burst_items(dw_gdma_dev_t *dev, uint8_t channel, dw_gdma_ll_burst_items_t items)
+{
+    dev->ch[channel].ctl0.src_msize = items;
+}
+
+/**
+ * @brief Set the number of data items that can be transferred in a single burst transaction for the destination master port
+ *
+ * @param dev Pointer to the DW_GDMA registers
+ * @param channel Channel number
+ * @param items Number of data items
+ */
+static inline void dw_gdma_ll_channel_set_dst_burst_items(dw_gdma_dev_t *dev, uint8_t channel, dw_gdma_ll_burst_items_t items)
+{
+    dev->ch[channel].ctl0.dst_msize = items;
+}
+
+/**
+ * @brief Set the source burst length
+ *
+ * @note This controls how many times the DMA controller will ask for data from the source device in a single burst transaction.
+ *
+ * @param dev Pointer to the DW_GDMA registers
+ * @param channel Channel number
+ * @param len Burst length
+ */
+static inline void dw_gdma_ll_channel_set_src_burst_len(dw_gdma_dev_t *dev, uint8_t channel, uint32_t len)
+{
+    dev->ch[channel].ctl1.arlen_en = 1;
+    dev->ch[channel].ctl1.arlen = len - 1;
+}
+
+/**
+ * @brief Set the destination burst length
+ *
+ * @param dev Pointer to the DW_GDMA registers
+ * @param channel Channel number
+ * @param len Burst length
+ */
+static inline void dw_gdma_ll_channel_set_dst_burst_len(dw_gdma_dev_t *dev, uint8_t channel, uint32_t len)
+{
+    dev->ch[channel].ctl1.awlen_en = 1;
+    dev->ch[channel].ctl1.awlen = len - 1;
+}
+
+/**
+ * @brief Enable to generate an interrupt when the block transfer is done
+ *
+ * @param dev Pointer to the DW_GDMA registers
+ * @param channel Channel number
+ * @param en True to enable, false to disable
+ */
+static inline void dw_gdma_ll_channel_enable_intr_block_trans_done(dw_gdma_dev_t *dev, uint8_t channel, bool en)
+{
+    dev->ch[channel].ctl1.ioc_blktfr = en;
+}
+
+/**
+ * @brief Set the multi block transfer type for the source peripheral
+ *
+ * @param dev Pointer to the DW_GDMA registers
+ * @param channel Channel number
+ * @param type Multi block transfer type
+ */
+static inline void dw_gdma_ll_channel_set_src_multi_block_type(dw_gdma_dev_t *dev, uint8_t channel, dw_gdma_ll_multi_block_type_t type)
+{
+    dev->ch[channel].cfg0.src_multblk_type = type;
+}
+
+/**
+ * @brief Set the multi block transfer type for the destination peripheral
+ *
+ * @param dev Pointer to the DW_GDMA registers
+ * @param channel Channel number
+ * @param type Multi block transfer type
+ */
+static inline void dw_gdma_ll_channel_set_dst_multi_block_type(dw_gdma_dev_t *dev, uint8_t channel, dw_gdma_ll_multi_block_type_t type)
+{
+    dev->ch[channel].cfg0.dst_multblk_type = type;
+}
+
+/**
+ * @brief Set the unique ID for the source peripheral
+ *
+ * @note This ID is related to Out-of-order transaction
+ *
+ * @param dev Pointer to the DW_GDMA registers
+ * @param channel Channel number
+ * @param uid Unique ID
+ */
+static inline void dw_gdma_ll_channel_set_src_uid(dw_gdma_dev_t *dev, uint8_t channel, uint32_t uid)
+{
+    dev->ch[channel].cfg0.rd_uid = uid;
+}
+
+/**
+ * @brief Set the unique ID for the destination peripheral
+ *
+ * @note This ID is related to Out-of-order transaction
+ *
+ * @param dev Pointer to the DW_GDMA registers
+ * @param channel Channel number
+ * @param uid Unique ID
+ */
+static inline void dw_gdma_ll_channel_set_dst_uid(dw_gdma_dev_t *dev, uint8_t channel, uint32_t uid)
+{
+    dev->ch[channel].cfg0.wr_uid = uid;
+}
+
+/**
+ * @brief Set transfer type and flow control
+ *
+ * @param dev Pointer to the DW_GDMA registers
+ * @param channel Channel number
+ * @param flow Transfer flow control
+ */
+static inline void dw_gdma_ll_channel_set_trans_flow(dw_gdma_dev_t *dev, uint8_t channel, dw_gdma_ll_trans_flow_t flow)
+{
+    dev->ch[channel].cfg1.tt_fc = flow;
+}
+
+/**
+ * @brief Set the handshaking interface for source requests
+ *
+ * @note If source peripheral is memory, this configuration is ignored.
+ *
+ * @param dev Pointer to the DW_GDMA registers
+ * @param channel Channel number
+ * @param hs Handshaking interface
+ */
+static inline void dw_gdma_ll_channel_set_src_handshake_interface(dw_gdma_dev_t *dev, uint8_t channel, dw_gdma_ll_handshake_interface_t hs)
+{
+    dev->ch[channel].cfg1.hs_sel_src = hs;
+}
+
+/**
+ * @brief Set the handshaking interface for destination requests
+ *
+ * @note If destination peripheral is memory, this configuration is ignored.
+ *
+ * @param dev Pointer to the DW_GDMA registers
+ * @param channel Channel number
+ * @param hs Handshaking interface
+ */
+static inline void dw_gdma_ll_channel_set_dst_handshake_interface(dw_gdma_dev_t *dev, uint8_t channel, dw_gdma_ll_handshake_interface_t hs)
+{
+    dev->ch[channel].cfg1.hs_sel_dst = hs;
+}
+
+/**
+ * @brief Set the source handshaking peripheral
+ *
+ * @note Only valid for hardware handshake interface
+ *
+ * @param dev Pointer to the DW_GDMA registers
+ * @param channel Channel number
+ * @param periph Peripheral ID
+ */
+static inline void dw_gdma_ll_channel_set_src_handshake_periph(dw_gdma_dev_t *dev, uint8_t channel, dw_gdma_ll_hw_handshake_periph_t periph)
+{
+    dev->ch[channel].cfg1.src_per = periph;
+}
+
+/**
+ * @brief Set the destination handshaking peripheral
+ *
+ * @note Only valid for hardware handshake interface
+ *
+ * @param dev Pointer to the DW_GDMA registers
+ * @param channel Channel number
+ * @param periph Peripheral ID
+ */
+static inline void dw_gdma_ll_channel_set_dst_handshake_periph(dw_gdma_dev_t *dev, uint8_t channel, dw_gdma_ll_hw_handshake_periph_t periph)
+{
+    dev->ch[channel].cfg1.dst_per = periph;
+}
+
+/**
+ * @brief Set channel priority
+ *
+ * @param dev Pointer to the DW_GDMA registers
+ * @param channel Channel number
+ * @param priority Priority number, bigger number means higher priority
+ */
+static inline void dw_gdma_ll_channel_set_priority(dw_gdma_dev_t *dev, uint8_t channel, uint32_t priority)
+{
+    dev->ch[channel].cfg1.ch_prior = priority;
+}
+
+/**
+ * @brief Lock the DMA channel, so the channel can have exclusive access to the bus
+ *
+ * @note channel locking is supported only for M2M transfer at Block transfer and DMA transfer levels
+ *
+ * @param dev Pointer to the DW_GDMA registers
+ * @param channel Channel number
+ * @param lock_level At which level the lock is applied
+ */
+static inline void dw_gdma_ll_channel_lock(dw_gdma_dev_t *dev, uint8_t channel, dw_gdma_ll_lock_level_t lock_level)
+{
+    dev->ch[channel].cfg1.lock_ch_l = lock_level;
+    dev->ch[channel].cfg1.lock_ch = 1;
+}
+
+/**
+ * @brief Unlock the DMA channel
+ *
+ * @param dev Pointer to the DW_GDMA registers
+ * @param channel Channel number
+ */
+static inline void dw_gdma_ll_channel_unlock(dw_gdma_dev_t *dev, uint8_t channel)
+{
+    dev->ch[channel].cfg1.lock_ch = 0;
+}
+
+/**
+ * @brief Set the outstanding request limit for the source peripheral
+ *
+ * @note The actual number of outstanding requests are limited by the capabilities of the source and destination interfaces.
+ *
+ * @param dev Pointer to the DW_GDMA registers
+ * @param channel Channel number
+ * @param limit Outstanding request limit
+ */
+static inline void dw_gdma_ll_channel_set_src_outstanding_limit(dw_gdma_dev_t *dev, uint8_t channel, uint32_t limit)
+{
+    dev->ch[channel].cfg1.src_osr_lmt = limit - 1;
+}
+
+/**
+ * @brief Set the outstanding request limit for the destination peripheral
+ *
+ * @note The actual number of outstanding requests are limited by the capabilities of the source and destination interfaces.
+ * @param dev Pointer to the DW_GDMA registers
+ * @param channel Channel number
+ * @param limit Outstanding request limit
+ */
+static inline void dw_gdma_ll_channel_set_dst_outstanding_limit(dw_gdma_dev_t *dev, uint8_t channel, uint32_t limit)
+{
+    dev->ch[channel].cfg1.dst_osr_lmt = limit - 1;
+}
+
+/**
+ * @brief Set the address of the first link list item
+ *
+ * @param dev Pointer to the DW_GDMA registers
+ * @param channel Channel number
+ * @param addr Address of the first link list item, it must be aligned 64
+ */
+static inline void dw_gdma_ll_channel_set_link_list_head_addr(dw_gdma_dev_t *dev, uint8_t channel, uint32_t addr)
+{
+    dev->ch[channel].llp0.loc0 = addr >> 6;
+}
+
+/**
+ * @brief Set the master port of the memory which holds the link list
+ *
+ * @param dev Pointer to the DW_GDMA registers
+ * @param channel Channel number
+ * @param port Master port
+ */
+static inline void dw_gdma_ll_channel_set_link_list_master_port(dw_gdma_dev_t *dev, uint8_t channel, uint32_t port)
+{
+    dev->ch[channel].llp0.lms = port;
+}
+
+/**
+ * @brief Get the total number of data that transferred for the previous block transfer.
+ *
+ * @note for normal transfer, this value is the same as the value of `dw_gdma_ll_channel_set_trans_amount`
+ * @note if any error occurs, the transfer might be terminated early, this function returns actual data transferred without error.
+ *
+ * @param dev Pointer to the DW_GDMA registers
+ * @param channel Channel number
+ * @return Total number of data that transferred for the previous block transfer
+ */
+static inline uint32_t dw_gdma_ll_channel_get_trans_amount(dw_gdma_dev_t *dev, uint8_t channel)
+{
+    return dev->ch[channel].status0.cmpltd_blk_tfr_size;
+}
+
+/**
+ * @brief Resume the multi-block transfer
+ *
+ * @note This function is only valid for linked list or shadow register based multi-block transfer
+ *
+ * @param dev Pointer to the DW_GDMA registers
+ * @param channel Channel number
+ */
+static inline void dw_gdma_ll_channel_resume_multi_block_transfer(dw_gdma_dev_t *dev, uint8_t channel)
+{
+    // this register is write-only, we can't do read-modify-write
+    dev->ch[channel].blk_tfr_resumereq0.val = 0x01;
+}
+
+/**
+ * @brief Set the address to fetch the source status of the DMA channel
+ *
+ * @param dev Pointer to the DW_GDMA registers
+ * @param channel Channel number
+ * @param addr Address to fetch the source status of the DMA channel
+ */
+static inline void dw_gdma_ll_channel_set_src_status_fetch_addr(dw_gdma_dev_t *dev, uint8_t channel, uint32_t addr)
+{
+    dev->ch[channel].sstatar0.sstatar0 = addr;
+}
+
+/**
+ * @brief Set the address to fetch the destination status of the DMA channel
+ *
+ * @param dev Pointer to the DW_GDMA registers
+ * @param channel Channel number
+ * @param addr Address to fetch the destination status of the DMA channel
+ */
+static inline void dw_gdma_ll_channel_set_dst_status_fetch_addr(dw_gdma_dev_t *dev, uint8_t channel, uint32_t addr)
+{
+    dev->ch[channel].dstatar0.dstatar0 = addr;
+}
+
+#ifdef __cplusplus
+}
+#endif

components/hal/gdma_hal_ahb_v1.c

@@ -106,6 +106,7 @@ void gdma_ahb_hal_set_strategy(gdma_hal_context_t *hal, int chan_id, gdma_channe
 {
     if (dir == GDMA_CHANNEL_DIRECTION_RX) {
         gdma_ll_rx_enable_owner_check(hal->dev, chan_id, en_owner_check);
+        // RX direction always has the descriptor write-back feature enabled
     } else {
         gdma_ll_tx_enable_owner_check(hal->dev, chan_id, en_owner_check);
         gdma_ll_tx_enable_auto_write_back(hal->dev, chan_id, en_desc_write_back);

components/hal/gdma_hal_ahb_v2.c

@@ -95,6 +95,7 @@ void gdma_ahb_hal_set_strategy(gdma_hal_context_t *hal, int chan_id, gdma_channe
 {
     if (dir == GDMA_CHANNEL_DIRECTION_RX) {
         ahb_dma_ll_rx_enable_owner_check(hal->ahb_dma_dev, chan_id, en_owner_check);
+        // RX direction always has the descriptor write-back feature enabled
     } else {
         ahb_dma_ll_tx_enable_owner_check(hal->ahb_dma_dev, chan_id, en_owner_check);
         ahb_dma_ll_tx_enable_auto_write_back(hal->ahb_dma_dev, chan_id, en_desc_write_back);

components/hal/gdma_hal_axi.c

@@ -95,6 +95,7 @@ void gdma_axi_hal_set_strategy(gdma_hal_context_t *hal, int chan_id, gdma_channe
 {
     if (dir == GDMA_CHANNEL_DIRECTION_RX) {
         axi_dma_ll_rx_enable_owner_check(hal->axi_dma_dev, chan_id, en_owner_check);
+        // RX direction always has the descriptor write-back feature enabled
     } else {
         axi_dma_ll_tx_enable_owner_check(hal->axi_dma_dev, chan_id, en_owner_check);
         axi_dma_ll_tx_enable_auto_write_back(hal->axi_dma_dev, chan_id, en_desc_write_back);

components/hal/include/hal/adc_hal.h

@@ -16,7 +16,6 @@
 #endif
 
 #if SOC_GDMA_SUPPORTED
-#include "soc/gdma_struct.h"
 #include "hal/gdma_ll.h"
 #endif
 

components/hal/include/hal/dw_gdma_hal.h

@@ -0,0 +1,46 @@
+/*
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include <stdbool.h>
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief DW_GDMA SOC layer representation
+ */
+typedef struct dw_gdma_dev_t *dw_gdma_soc_handle_t;
+
+/**
+ * @brief DW_GDMA HAL driver context
+ */
+typedef struct {
+    dw_gdma_soc_handle_t dev;  /*!< Pointer to the DW_GDMA registers */
+} dw_gdma_hal_context_t;
+
+/**
+ * @brief DW_GDMA HAL driver configuration
+ */
+typedef struct {
+} dw_gdma_hal_config_t;
+
+/**
+ * @brief DW_GDMA HAL driver initialization
+ *
+ * @note Caller should malloc the memory for the hal context
+ *
+ * @param hal Pointer to the HAL driver context
+ * @param config Pointer to the HAL driver configuration
+ */
+void dw_gdma_hal_init(dw_gdma_hal_context_t *hal, const dw_gdma_hal_config_t *config);
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32p4/include/soc/dw_gdma_struct.h

@@ -0,0 +1,1780 @@
+/**
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Version Register */
+/** Type of id0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dmac_id : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dmac_id: 32;
+    };
+    uint32_t val;
+} dmac_id0_reg_t;
+
+/** Type of compver0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dmac_compver : RO; bitpos: [31:0]; default: 842018858;
+         *  NA
+         */
+        uint32_t dmac_compver: 32;
+    };
+    uint32_t val;
+} dmac_compver0_reg_t;
+
+/** Group: Configuration Registers */
+/** Type of cfg0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dmac_en : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t dmac_en: 1;
+        /** int_en : R/W; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t int_en: 1;
+        uint32_t reserved_2: 30;
+    };
+    uint32_t val;
+} dmac_cfg0_reg_t;
+
+/** Type of chen0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch1_en : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_en: 1;
+        /** ch2_en : R/W; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_en: 1;
+        /** ch3_en : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_en: 1;
+        /** ch4_en : R/W; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_en: 1;
+        uint32_t reserved_4: 4;
+        /** ch1_en_we : WO; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_en_we: 1;
+        /** ch2_en_we : WO; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_en_we: 1;
+        /** ch3_en_we : WO; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_en_we: 1;
+        /** ch4_en_we : WO; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_en_we: 1;
+        uint32_t reserved_12: 4;
+        /** ch1_susp : R/W; bitpos: [16]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_susp: 1;
+        /** ch2_susp : R/W; bitpos: [17]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_susp: 1;
+        /** ch3_susp : R/W; bitpos: [18]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_susp: 1;
+        /** ch4_susp : R/W; bitpos: [19]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_susp: 1;
+        uint32_t reserved_20: 4;
+        /** ch1_susp_we : WO; bitpos: [24]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_susp_we: 1;
+        /** ch2_susp_we : WO; bitpos: [25]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_susp_we: 1;
+        /** ch3_susp_we : WO; bitpos: [26]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_susp_we: 1;
+        /** ch4_susp_we : WO; bitpos: [27]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_susp_we: 1;
+        uint32_t reserved_28: 4;
+    };
+    uint32_t val;
+} dmac_chen0_reg_t;
+
+/** Type of chen1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch1_abort : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_abort: 1;
+        /** ch2_abort : R/W; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_abort: 1;
+        /** ch3_abort : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_abort: 1;
+        /** ch4_abort : R/W; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_abort: 1;
+        uint32_t reserved_4: 4;
+        /** ch1_abort_we : WO; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_abort_we: 1;
+        /** ch2_abort_we : WO; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_abort_we: 1;
+        /** ch3_abort_we : WO; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_abort_we: 1;
+        /** ch4_abort_we : WO; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_abort_we: 1;
+        uint32_t reserved_12: 20;
+    };
+    uint32_t val;
+} dmac_chen1_reg_t;
+
+/** Type of reset0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dmac_rst : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t dmac_rst: 1;
+        uint32_t reserved_1: 31;
+    };
+    uint32_t val;
+} dmac_reset0_reg_t;
+
+/** Type of lowpower_cfg0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** gbl_cslp_en : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t gbl_cslp_en: 1;
+        /** chnl_cslp_en : R/W; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t chnl_cslp_en: 1;
+        /** sbiu_cslp_en : R/W; bitpos: [2]; default: 1;
+         *  NA
+         */
+        uint32_t sbiu_cslp_en: 1;
+        /** mxif_cslp_en : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t mxif_cslp_en: 1;
+        uint32_t reserved_4: 28;
+    };
+    uint32_t val;
+} dmac_lowpower_cfg0_reg_t;
+
+/** Type of lowpower_cfg1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** glch_lpdly : R/W; bitpos: [7:0]; default: 64;
+         *  NA
+         */
+        uint32_t glch_lpdly: 8;
+        /** sbiu_lpdly : R/W; bitpos: [15:8]; default: 64;
+         *  NA
+         */
+        uint32_t sbiu_lpdly: 8;
+        /** mxif_lpdly : R/W; bitpos: [23:16]; default: 64;
+         *  NA
+         */
+        uint32_t mxif_lpdly: 8;
+        uint32_t reserved_24: 8;
+    };
+    uint32_t val;
+} dmac_lowpower_cfg1_reg_t;
+
+/** Type of chn_sar0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** sar0 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t sar0: 32;
+    };
+    uint32_t val;
+} dmac_chn_sar0_reg_t;
+
+/** Type of chn_sar1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** sar1 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t sar1: 32;
+    };
+    uint32_t val;
+} dmac_chn_sar1_reg_t;
+
+/** Type of chn_dar0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dar0 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dar0: 32;
+    };
+    uint32_t val;
+} dmac_chn_dar0_reg_t;
+
+/** Type of chn_dar1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dar1 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dar1: 32;
+    };
+    uint32_t val;
+} dmac_chn_dar1_reg_t;
+
+/** Type of chn_block_ts0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** block_ts : R/W; bitpos: [21:0]; default: 0;
+         *  NA
+         */
+        uint32_t block_ts: 22;
+        uint32_t reserved_22: 10;
+    };
+    uint32_t val;
+} dmac_chn_block_ts0_reg_t;
+
+/** Type of chn_ctl0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** sms : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t sms: 1;
+        uint32_t reserved_1: 1;
+        /** dms : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t dms: 1;
+        uint32_t reserved_3: 1;
+        /** sinc : R/W; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t sinc: 1;
+        uint32_t reserved_5: 1;
+        /** dinc : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t dinc: 1;
+        uint32_t reserved_7: 1;
+        /** src_tr_width : R/W; bitpos: [10:8]; default: 2;
+         *  NA
+         */
+        uint32_t src_tr_width: 3;
+        /** dst_tr_width : R/W; bitpos: [13:11]; default: 2;
+         *  NA
+         */
+        uint32_t dst_tr_width: 3;
+        /** src_msize : R/W; bitpos: [17:14]; default: 0;
+         *  NA
+         */
+        uint32_t src_msize: 4;
+        /** dst_msize : R/W; bitpos: [21:18]; default: 0;
+         *  NA
+         */
+        uint32_t dst_msize: 4;
+        /** ar_cache : R/W; bitpos: [25:22]; default: 0;
+         *  NA
+         */
+        uint32_t ar_cache: 4;
+        /** aw_cache : R/W; bitpos: [29:26]; default: 0;
+         *  NA
+         */
+        uint32_t aw_cache: 4;
+        /** nonposted_lastwrite_en : R/W; bitpos: [30]; default: 0;
+         *  NA
+         */
+        uint32_t nonposted_lastwrite_en: 1;
+        uint32_t reserved_31: 1;
+    };
+    uint32_t val;
+} dmac_chn_ctl0_reg_t;
+
+/** Type of chn_ctl1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ar_prot : R/W; bitpos: [2:0]; default: 0;
+         *  NA
+         */
+        uint32_t ar_prot: 3;
+        /** aw_prot : R/W; bitpos: [5:3]; default: 0;
+         *  NA
+         */
+        uint32_t aw_prot: 3;
+        /** arlen_en : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t arlen_en: 1;
+        /** arlen : R/W; bitpos: [14:7]; default: 0;
+         *  NA
+         */
+        uint32_t arlen: 8;
+        /** awlen_en : R/W; bitpos: [15]; default: 0;
+         *  NA
+         */
+        uint32_t awlen_en: 1;
+        /** awlen : R/W; bitpos: [23:16]; default: 0;
+         *  NA
+         */
+        uint32_t awlen: 8;
+        /** src_stat_en : R/W; bitpos: [24]; default: 0;
+         *  NA
+         */
+        uint32_t src_stat_en: 1;
+        /** dst_stat_en : R/W; bitpos: [25]; default: 0;
+         *  NA
+         */
+        uint32_t dst_stat_en: 1;
+        /** ioc_blktfr : R/W; bitpos: [26]; default: 0;
+         *  NA
+         */
+        uint32_t ioc_blktfr: 1;
+        uint32_t reserved_27: 3;
+        /** shadowreg_or_lli_last : R/W; bitpos: [30]; default: 0;
+         *  NA
+         */
+        uint32_t shadowreg_or_lli_last: 1;
+        /** shadowreg_or_lli_valid : R/W; bitpos: [31]; default: 0;
+         *  NA
+         */
+        uint32_t shadowreg_or_lli_valid: 1;
+    };
+    uint32_t val;
+} dmac_chn_ctl1_reg_t;
+
+/** Type of chn_cfg0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** src_multblk_type : R/W; bitpos: [1:0]; default: 0;
+         *  NA
+         */
+        uint32_t src_multblk_type: 2;
+        /** dst_multblk_type : R/W; bitpos: [3:2]; default: 0;
+         *  NA
+         */
+        uint32_t dst_multblk_type: 2;
+        uint32_t reserved_4: 14;
+        /** rd_uid : RO; bitpos: [21:18]; default: 0;
+         *  NA
+         */
+        uint32_t rd_uid: 4;
+        uint32_t reserved_22: 3;
+        /** wr_uid : RO; bitpos: [28:25]; default: 0;
+         *  NA
+         */
+        uint32_t wr_uid: 4;
+        uint32_t reserved_29: 3;
+    };
+    uint32_t val;
+} dmac_chn_cfg0_reg_t;
+
+/** Type of chn_cfg1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** tt_fc : R/W; bitpos: [2:0]; default: 3;
+         *  NA
+         */
+        uint32_t tt_fc: 3;
+        /** hs_sel_src : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t hs_sel_src: 1;
+        /** hs_sel_dst : R/W; bitpos: [4]; default: 1;
+         *  NA
+         */
+        uint32_t hs_sel_dst: 1;
+        /** src_hwhs_pol : RO; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t src_hwhs_pol: 1;
+        /** dst_hwhs_pol : RO; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t dst_hwhs_pol: 1;
+        /** src_per : R/W; bitpos: [8:7]; default: 0;
+         *  NA
+         */
+        uint32_t src_per: 2;
+        uint32_t reserved_9: 3;
+        /** dst_per : R/W; bitpos: [13:12]; default: 0;
+         *  NA
+         */
+        uint32_t dst_per: 2;
+        uint32_t reserved_14: 3;
+        /** ch_prior : R/W; bitpos: [19:17]; default: 3;
+         *  NA
+         */
+        uint32_t ch_prior: 3;
+        /** lock_ch : RO; bitpos: [20]; default: 0;
+         *  NA
+         */
+        uint32_t lock_ch: 1;
+        /** lock_ch_l : RO; bitpos: [22:21]; default: 0;
+         *  NA
+         */
+        uint32_t lock_ch_l: 2;
+        /** src_osr_lmt : R/W; bitpos: [26:23]; default: 0;
+         *  NA
+         */
+        uint32_t src_osr_lmt: 4;
+        /** dst_osr_lmt : R/W; bitpos: [30:27]; default: 0;
+         *  NA
+         */
+        uint32_t dst_osr_lmt: 4;
+        uint32_t reserved_31: 1;
+    };
+    uint32_t val;
+} dmac_chn_cfg1_reg_t;
+
+/** Type of chn_llp0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** lms : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t lms: 1;
+        uint32_t reserved_1: 5;
+        /** loc0 : R/W; bitpos: [31:6]; default: 0;
+         *  NA
+         */
+        uint32_t loc0: 26;
+    };
+    uint32_t val;
+} dmac_chn_llp0_reg_t;
+
+/** Type of chn_llp1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** loc1 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t loc1: 32;
+    };
+    uint32_t val;
+} dmac_chn_llp1_reg_t;
+
+/** Type of chn_swhssrc0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** swhs_req_src : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t swhs_req_src: 1;
+        /** swhs_req_src_we : WO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t swhs_req_src_we: 1;
+        /** swhs_sglreq_src : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t swhs_sglreq_src: 1;
+        /** swhs_sglreq_src_we : WO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t swhs_sglreq_src_we: 1;
+        /** swhs_lst_src : R/W; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t swhs_lst_src: 1;
+        /** swhs_lst_src_we : WO; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t swhs_lst_src_we: 1;
+        uint32_t reserved_6: 26;
+    };
+    uint32_t val;
+} dmac_chn_swhssrc0_reg_t;
+
+/** Type of chn_swhsdst0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** swhs_req_dst : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t swhs_req_dst: 1;
+        /** swhs_req_dst_we : WO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t swhs_req_dst_we: 1;
+        /** swhs_sglreq_dst : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t swhs_sglreq_dst: 1;
+        /** swhs_sglreq_dst_we : WO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t swhs_sglreq_dst_we: 1;
+        /** swhs_lst_dst : R/W; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t swhs_lst_dst: 1;
+        /** swhs_lst_dst_we : WO; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t swhs_lst_dst_we: 1;
+        uint32_t reserved_6: 26;
+    };
+    uint32_t val;
+} dmac_chn_swhsdst0_reg_t;
+
+/** Type of chn_blk_tfr_resumereq0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** blk_tfr_resumereq : WO; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t blk_tfr_resumereq: 1;
+        uint32_t reserved_1: 31;
+    };
+    uint32_t val;
+} dmac_chn_blk_tfr_resumereq0_reg_t;
+
+/** Type of chn_axi_id0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** axi_read_id_suffix : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t axi_read_id_suffix: 1;
+        uint32_t reserved_1: 15;
+        /** axi_write_id_suffix : R/W; bitpos: [16]; default: 0;
+         *  NA
+         */
+        uint32_t axi_write_id_suffix: 1;
+        uint32_t reserved_17: 15;
+    };
+    uint32_t val;
+} dmac_chn_axi_id0_reg_t;
+
+/** Type of chn_axi_qos0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** axi_awqos : R/W; bitpos: [3:0]; default: 0;
+         *  NA
+         */
+        uint32_t axi_awqos: 4;
+        /** axi_arqos : R/W; bitpos: [7:4]; default: 0;
+         *  NA
+         */
+        uint32_t axi_arqos: 4;
+        uint32_t reserved_8: 24;
+    };
+    uint32_t val;
+} dmac_chn_axi_qos0_reg_t;
+
+/** Group: Interrupt Registers */
+/** Type of intstatus0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch1_intstat : RO; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_intstat: 1;
+        /** ch2_intstat : RO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_intstat: 1;
+        /** ch3_intstat : RO; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_intstat: 1;
+        /** ch4_intstat : RO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_intstat: 1;
+        uint32_t reserved_4: 12;
+        /** commonreg_intstat : RO; bitpos: [16]; default: 0;
+         *  NA
+         */
+        uint32_t commonreg_intstat: 1;
+        uint32_t reserved_17: 15;
+    };
+    uint32_t val;
+} dmac_intstatus0_reg_t;
+
+/** Type of commonreg_intclear0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** clear_slvif_commonreg_dec_err_intstat : WO; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t clear_slvif_commonreg_dec_err_intstat: 1;
+        /** clear_slvif_commonreg_wr2ro_err_intstat : WO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t clear_slvif_commonreg_wr2ro_err_intstat: 1;
+        /** clear_slvif_commonreg_rd2wo_err_intstat : WO; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t clear_slvif_commonreg_rd2wo_err_intstat: 1;
+        /** clear_slvif_commonreg_wronhold_err_intstat : WO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t clear_slvif_commonreg_wronhold_err_intstat: 1;
+        uint32_t reserved_4: 3;
+        /** clear_slvif_commonreg_wrparity_err_intstat : WO; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t clear_slvif_commonreg_wrparity_err_intstat: 1;
+        /** clear_slvif_undefinedreg_dec_err_intstat : WO; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t clear_slvif_undefinedreg_dec_err_intstat: 1;
+        /** clear_mxif1_rch0_eccprot_correrr_intstat : WO; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t clear_mxif1_rch0_eccprot_correrr_intstat: 1;
+        /** clear_mxif1_rch0_eccprot_uncorrerr_intstat : WO; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t clear_mxif1_rch0_eccprot_uncorrerr_intstat: 1;
+        /** clear_mxif1_rch1_eccprot_correrr_intstat : WO; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t clear_mxif1_rch1_eccprot_correrr_intstat: 1;
+        /** clear_mxif1_rch1_eccprot_uncorrerr_intstat : WO; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t clear_mxif1_rch1_eccprot_uncorrerr_intstat: 1;
+        /** clear_mxif1_bch_eccprot_correrr_intstat : WO; bitpos: [13]; default: 0;
+         *  NA
+         */
+        uint32_t clear_mxif1_bch_eccprot_correrr_intstat: 1;
+        /** clear_mxif1_bch_eccprot_uncorrerr_intstat : WO; bitpos: [14]; default: 0;
+         *  NA
+         */
+        uint32_t clear_mxif1_bch_eccprot_uncorrerr_intstat: 1;
+        /** clear_mxif2_rch0_eccprot_correrr_intstat : WO; bitpos: [15]; default: 0;
+         *  NA
+         */
+        uint32_t clear_mxif2_rch0_eccprot_correrr_intstat: 1;
+        /** clear_mxif2_rch0_eccprot_uncorrerr_intstat : WO; bitpos: [16]; default: 0;
+         *  NA
+         */
+        uint32_t clear_mxif2_rch0_eccprot_uncorrerr_intstat: 1;
+        /** clear_mxif2_rch1_eccprot_correrr_intstat : WO; bitpos: [17]; default: 0;
+         *  NA
+         */
+        uint32_t clear_mxif2_rch1_eccprot_correrr_intstat: 1;
+        /** clear_mxif2_rch1_eccprot_uncorrerr_intstat : WO; bitpos: [18]; default: 0;
+         *  NA
+         */
+        uint32_t clear_mxif2_rch1_eccprot_uncorrerr_intstat: 1;
+        /** clear_mxif2_bch_eccprot_correrr_intstat : WO; bitpos: [19]; default: 0;
+         *  NA
+         */
+        uint32_t clear_mxif2_bch_eccprot_correrr_intstat: 1;
+        /** clear_mxif2_bch_eccprot_uncorrerr_intstat : WO; bitpos: [20]; default: 0;
+         *  NA
+         */
+        uint32_t clear_mxif2_bch_eccprot_uncorrerr_intstat: 1;
+        uint32_t reserved_21: 11;
+    };
+    uint32_t val;
+} dmac_commonreg_intclear0_reg_t;
+
+/** Type of commonreg_intstatus_enable0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** enable_slvif_commonreg_dec_err_intstat : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_commonreg_dec_err_intstat: 1;
+        /** enable_slvif_commonreg_wr2ro_err_intstat : R/W; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_commonreg_wr2ro_err_intstat: 1;
+        /** enable_slvif_commonreg_rd2wo_err_intstat : R/W; bitpos: [2]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_commonreg_rd2wo_err_intstat: 1;
+        /** enable_slvif_commonreg_wronhold_err_intstat : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_commonreg_wronhold_err_intstat: 1;
+        uint32_t reserved_4: 3;
+        /** enable_slvif_commonreg_wrparity_err_intstat : RO; bitpos: [7]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_commonreg_wrparity_err_intstat: 1;
+        /** enable_slvif_undefinedreg_dec_err_intstat : R/W; bitpos: [8]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_undefinedreg_dec_err_intstat: 1;
+        /** enable_mxif1_rch0_eccprot_correrr_intstat : RO; bitpos: [9]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif1_rch0_eccprot_correrr_intstat: 1;
+        /** enable_mxif1_rch0_eccprot_uncorrerr_intstat : RO; bitpos: [10]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif1_rch0_eccprot_uncorrerr_intstat: 1;
+        /** enable_mxif1_rch1_eccprot_correrr_intstat : RO; bitpos: [11]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif1_rch1_eccprot_correrr_intstat: 1;
+        /** enable_mxif1_rch1_eccprot_uncorrerr_intstat : RO; bitpos: [12]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif1_rch1_eccprot_uncorrerr_intstat: 1;
+        /** enable_mxif1_bch_eccprot_correrr_intstat : RO; bitpos: [13]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif1_bch_eccprot_correrr_intstat: 1;
+        /** enable_mxif1_bch_eccprot_uncorrerr_intstat : RO; bitpos: [14]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif1_bch_eccprot_uncorrerr_intstat: 1;
+        /** enable_mxif2_rch0_eccprot_correrr_intstat : RO; bitpos: [15]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif2_rch0_eccprot_correrr_intstat: 1;
+        /** enable_mxif2_rch0_eccprot_uncorrerr_intstat : RO; bitpos: [16]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif2_rch0_eccprot_uncorrerr_intstat: 1;
+        /** enable_mxif2_rch1_eccprot_correrr_intstat : RO; bitpos: [17]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif2_rch1_eccprot_correrr_intstat: 1;
+        /** enable_mxif2_rch1_eccprot_uncorrerr_intstat : RO; bitpos: [18]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif2_rch1_eccprot_uncorrerr_intstat: 1;
+        /** enable_mxif2_bch_eccprot_correrr_intstat : RO; bitpos: [19]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif2_bch_eccprot_correrr_intstat: 1;
+        /** enable_mxif2_bch_eccprot_uncorrerr_intstat : RO; bitpos: [20]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif2_bch_eccprot_uncorrerr_intstat: 1;
+        uint32_t reserved_21: 11;
+    };
+    uint32_t val;
+} dmac_commonreg_intstatus_enable0_reg_t;
+
+/** Type of commonreg_intsignal_enable0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** enable_slvif_commonreg_dec_err_intsignal : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_commonreg_dec_err_intsignal: 1;
+        /** enable_slvif_commonreg_wr2ro_err_intsignal : R/W; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_commonreg_wr2ro_err_intsignal: 1;
+        /** enable_slvif_commonreg_rd2wo_err_intsignal : R/W; bitpos: [2]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_commonreg_rd2wo_err_intsignal: 1;
+        /** enable_slvif_commonreg_wronhold_err_intsignal : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_commonreg_wronhold_err_intsignal: 1;
+        uint32_t reserved_4: 3;
+        /** enable_slvif_commonreg_wrparity_err_intsignal : RO; bitpos: [7]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_commonreg_wrparity_err_intsignal: 1;
+        /** enable_slvif_undefinedreg_dec_err_intsignal : R/W; bitpos: [8]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_undefinedreg_dec_err_intsignal: 1;
+        /** enable_mxif1_rch0_eccprot_correrr_intsignal : RO; bitpos: [9]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif1_rch0_eccprot_correrr_intsignal: 1;
+        /** enable_mxif1_rch0_eccprot_uncorrerr_intsignal : RO; bitpos: [10]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif1_rch0_eccprot_uncorrerr_intsignal: 1;
+        /** enable_mxif1_rch1_eccprot_correrr_intsignal : RO; bitpos: [11]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif1_rch1_eccprot_correrr_intsignal: 1;
+        /** enable_mxif1_rch1_eccprot_uncorrerr_intsignal : RO; bitpos: [12]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif1_rch1_eccprot_uncorrerr_intsignal: 1;
+        /** enable_mxif1_bch_eccprot_correrr_intsignal : RO; bitpos: [13]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif1_bch_eccprot_correrr_intsignal: 1;
+        /** enable_mxif1_bch_eccprot_uncorrerr_intsignal : RO; bitpos: [14]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif1_bch_eccprot_uncorrerr_intsignal: 1;
+        /** enable_mxif2_rch0_eccprot_correrr_intsignal : RO; bitpos: [15]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif2_rch0_eccprot_correrr_intsignal: 1;
+        /** enable_mxif2_rch0_eccprot_uncorrerr_intsignal : RO; bitpos: [16]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif2_rch0_eccprot_uncorrerr_intsignal: 1;
+        /** enable_mxif2_rch1_eccprot_correrr_intsignal : RO; bitpos: [17]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif2_rch1_eccprot_correrr_intsignal: 1;
+        /** enable_mxif2_rch1_eccprot_uncorrerr_intsignal : RO; bitpos: [18]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif2_rch1_eccprot_uncorrerr_intsignal: 1;
+        /** enable_mxif2_bch_eccprot_correrr_intsignal : RO; bitpos: [19]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif2_bch_eccprot_correrr_intsignal: 1;
+        /** enable_mxif2_bch_eccprot_uncorrerr_intsignal : RO; bitpos: [20]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif2_bch_eccprot_uncorrerr_intsignal: 1;
+        uint32_t reserved_21: 11;
+    };
+    uint32_t val;
+} dmac_commonreg_intsignal_enable0_reg_t;
+
+/** Type of commonreg_intstatus0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** slvif_commonreg_dec_err_intstat : RO; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t slvif_commonreg_dec_err_intstat: 1;
+        /** slvif_commonreg_wr2ro_err_intstat : RO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t slvif_commonreg_wr2ro_err_intstat: 1;
+        /** slvif_commonreg_rd2wo_err_intstat : RO; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t slvif_commonreg_rd2wo_err_intstat: 1;
+        /** slvif_commonreg_wronhold_err_intstat : RO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t slvif_commonreg_wronhold_err_intstat: 1;
+        uint32_t reserved_4: 3;
+        /** slvif_commonreg_wrparity_err_intstat : RO; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t slvif_commonreg_wrparity_err_intstat: 1;
+        /** slvif_undefinedreg_dec_err_intstat : RO; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t slvif_undefinedreg_dec_err_intstat: 1;
+        /** mxif1_rch0_eccprot_correrr_intstat : RO; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t mxif1_rch0_eccprot_correrr_intstat: 1;
+        /** mxif1_rch0_eccprot_uncorrerr_intstat : RO; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t mxif1_rch0_eccprot_uncorrerr_intstat: 1;
+        /** mxif1_rch1_eccprot_correrr_intstat : RO; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t mxif1_rch1_eccprot_correrr_intstat: 1;
+        /** mxif1_rch1_eccprot_uncorrerr_intstat : RO; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t mxif1_rch1_eccprot_uncorrerr_intstat: 1;
+        /** mxif1_bch_eccprot_correrr_intstat : RO; bitpos: [13]; default: 0;
+         *  NA
+         */
+        uint32_t mxif1_bch_eccprot_correrr_intstat: 1;
+        /** mxif1_bch_eccprot_uncorrerr_intstat : RO; bitpos: [14]; default: 0;
+         *  NA
+         */
+        uint32_t mxif1_bch_eccprot_uncorrerr_intstat: 1;
+        /** mxif2_rch0_eccprot_correrr_intstat : RO; bitpos: [15]; default: 0;
+         *  NA
+         */
+        uint32_t mxif2_rch0_eccprot_correrr_intstat: 1;
+        /** mxif2_rch0_eccprot_uncorrerr_intstat : RO; bitpos: [16]; default: 0;
+         *  NA
+         */
+        uint32_t mxif2_rch0_eccprot_uncorrerr_intstat: 1;
+        /** mxif2_rch1_eccprot_correrr_intstat : RO; bitpos: [17]; default: 0;
+         *  NA
+         */
+        uint32_t mxif2_rch1_eccprot_correrr_intstat: 1;
+        /** mxif2_rch1_eccprot_uncorrerr_intstat : RO; bitpos: [18]; default: 0;
+         *  NA
+         */
+        uint32_t mxif2_rch1_eccprot_uncorrerr_intstat: 1;
+        /** mxif2_bch_eccprot_correrr_intstat : RO; bitpos: [19]; default: 0;
+         *  NA
+         */
+        uint32_t mxif2_bch_eccprot_correrr_intstat: 1;
+        /** mxif2_bch_eccprot_uncorrerr_intstat : RO; bitpos: [20]; default: 0;
+         *  NA
+         */
+        uint32_t mxif2_bch_eccprot_uncorrerr_intstat: 1;
+        uint32_t reserved_21: 11;
+    };
+    uint32_t val;
+} dmac_commonreg_intstatus0_reg_t;
+
+/** Type of chn_intstatus_enable0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** enable_block_tfr_done_intstat : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t enable_block_tfr_done_intstat: 1;
+        /** enable_dma_tfr_done_intstat : R/W; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t enable_dma_tfr_done_intstat: 1;
+        uint32_t reserved_2: 1;
+        /** enable_src_transcomp_intstat : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t enable_src_transcomp_intstat: 1;
+        /** enable_dst_transcomp_intstat : R/W; bitpos: [4]; default: 1;
+         *  NA
+         */
+        uint32_t enable_dst_transcomp_intstat: 1;
+        /** enable_src_dec_err_intstat : R/W; bitpos: [5]; default: 1;
+         *  NA
+         */
+        uint32_t enable_src_dec_err_intstat: 1;
+        /** enable_dst_dec_err_intstat : R/W; bitpos: [6]; default: 1;
+         *  NA
+         */
+        uint32_t enable_dst_dec_err_intstat: 1;
+        /** enable_src_slv_err_intstat : R/W; bitpos: [7]; default: 1;
+         *  NA
+         */
+        uint32_t enable_src_slv_err_intstat: 1;
+        /** enable_dst_slv_err_intstat : R/W; bitpos: [8]; default: 1;
+         *  NA
+         */
+        uint32_t enable_dst_slv_err_intstat: 1;
+        /** enable_lli_rd_dec_err_intstat : R/W; bitpos: [9]; default: 1;
+         *  NA
+         */
+        uint32_t enable_lli_rd_dec_err_intstat: 1;
+        /** enable_lli_wr_dec_err_intstat : R/W; bitpos: [10]; default: 1;
+         *  NA
+         */
+        uint32_t enable_lli_wr_dec_err_intstat: 1;
+        /** enable_lli_rd_slv_err_intstat : R/W; bitpos: [11]; default: 1;
+         *  NA
+         */
+        uint32_t enable_lli_rd_slv_err_intstat: 1;
+        /** enable_lli_wr_slv_err_intstat : R/W; bitpos: [12]; default: 1;
+         *  NA
+         */
+        uint32_t enable_lli_wr_slv_err_intstat: 1;
+        /** enable_shadowreg_or_lli_invalid_err_intstat : R/W; bitpos: [13]; default: 1;
+         *  NA
+         */
+        uint32_t enable_shadowreg_or_lli_invalid_err_intstat: 1;
+        /** enable_slvif_multiblktype_err_intstat : R/W; bitpos: [14]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_multiblktype_err_intstat: 1;
+        uint32_t reserved_15: 1;
+        /** enable_slvif_dec_err_intstat : R/W; bitpos: [16]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_dec_err_intstat: 1;
+        /** enable_slvif_wr2ro_err_intstat : R/W; bitpos: [17]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_wr2ro_err_intstat: 1;
+        /** enable_slvif_rd2rwo_err_intstat : R/W; bitpos: [18]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_rd2rwo_err_intstat: 1;
+        /** enable_slvif_wronchen_err_intstat : R/W; bitpos: [19]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_wronchen_err_intstat: 1;
+        /** enable_slvif_shadowreg_wron_valid_err_intstat : R/W; bitpos: [20]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_shadowreg_wron_valid_err_intstat: 1;
+        /** enable_slvif_wronhold_err_intstat : R/W; bitpos: [21]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_wronhold_err_intstat: 1;
+        uint32_t reserved_22: 3;
+        /** enable_slvif_wrparity_err_intstat : RO; bitpos: [25]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_wrparity_err_intstat: 1;
+        uint32_t reserved_26: 1;
+        /** enable_ch_lock_cleared_intstat : R/W; bitpos: [27]; default: 1;
+         *  NA
+         */
+        uint32_t enable_ch_lock_cleared_intstat: 1;
+        /** enable_ch_src_suspended_intstat : R/W; bitpos: [28]; default: 1;
+         *  NA
+         */
+        uint32_t enable_ch_src_suspended_intstat: 1;
+        /** enable_ch_suspended_intstat : R/W; bitpos: [29]; default: 1;
+         *  NA
+         */
+        uint32_t enable_ch_suspended_intstat: 1;
+        /** enable_ch_disabled_intstat : R/W; bitpos: [30]; default: 1;
+         *  NA
+         */
+        uint32_t enable_ch_disabled_intstat: 1;
+        /** enable_ch_aborted_intstat : R/W; bitpos: [31]; default: 1;
+         *  NA
+         */
+        uint32_t enable_ch_aborted_intstat: 1;
+    };
+    uint32_t val;
+} dmac_chn_intstatus_enable0_reg_t;
+
+/** Type of chn_intstatus_enable1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** enable_ecc_prot_chmem_correrr_intstat : RO; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t enable_ecc_prot_chmem_correrr_intstat: 1;
+        /** enable_ecc_prot_chmem_uncorrerr_intstat : RO; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t enable_ecc_prot_chmem_uncorrerr_intstat: 1;
+        /** enable_ecc_prot_uidmem_correrr_intstat : RO; bitpos: [2]; default: 1;
+         *  NA
+         */
+        uint32_t enable_ecc_prot_uidmem_correrr_intstat: 1;
+        /** enable_ecc_prot_uidmem_uncorrerr_intstat : RO; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t enable_ecc_prot_uidmem_uncorrerr_intstat: 1;
+        uint32_t reserved_4: 28;
+    };
+    uint32_t val;
+} dmac_chn_intstatus_enable1_reg_t;
+
+/** Type of chn_intstatus0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** block_tfr_done_intstat : RO; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t block_tfr_done_intstat: 1;
+        /** dma_tfr_done_intstat : RO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t dma_tfr_done_intstat: 1;
+        uint32_t reserved_2: 1;
+        /** src_transcomp_intstat : RO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t src_transcomp_intstat: 1;
+        /** dst_transcomp_intstat : RO; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t dst_transcomp_intstat: 1;
+        /** src_dec_err_intstat : RO; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t src_dec_err_intstat: 1;
+        /** dst_dec_err_intstat : RO; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t dst_dec_err_intstat: 1;
+        /** src_slv_err_intstat : RO; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t src_slv_err_intstat: 1;
+        /** dst_slv_err_intstat : RO; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t dst_slv_err_intstat: 1;
+        /** lli_rd_dec_err_intstat : RO; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t lli_rd_dec_err_intstat: 1;
+        /** lli_wr_dec_err_intstat : RO; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t lli_wr_dec_err_intstat: 1;
+        /** lli_rd_slv_err_intstat : RO; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t lli_rd_slv_err_intstat: 1;
+        /** lli_wr_slv_err_intstat : RO; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t lli_wr_slv_err_intstat: 1;
+        /** shadowreg_or_lli_invalid_err_intstat : RO; bitpos: [13]; default: 0;
+         *  NA
+         */
+        uint32_t shadowreg_or_lli_invalid_err_intstat: 1;
+        /** slvif_multiblktype_err_intstat : RO; bitpos: [14]; default: 0;
+         *  NA
+         */
+        uint32_t slvif_multiblktype_err_intstat: 1;
+        uint32_t reserved_15: 1;
+        /** slvif_dec_err_intstat : RO; bitpos: [16]; default: 0;
+         *  NA
+         */
+        uint32_t slvif_dec_err_intstat: 1;
+        /** slvif_wr2ro_err_intstat : RO; bitpos: [17]; default: 0;
+         *  NA
+         */
+        uint32_t slvif_wr2ro_err_intstat: 1;
+        /** slvif_rd2rwo_err_intstat : RO; bitpos: [18]; default: 0;
+         *  NA
+         */
+        uint32_t slvif_rd2rwo_err_intstat: 1;
+        /** slvif_wronchen_err_intstat : RO; bitpos: [19]; default: 0;
+         *  NA
+         */
+        uint32_t slvif_wronchen_err_intstat: 1;
+        /** slvif_shadowreg_wron_valid_err_intstat : RO; bitpos: [20]; default: 0;
+         *  NA
+         */
+        uint32_t slvif_shadowreg_wron_valid_err_intstat: 1;
+        /** slvif_wronhold_err_intstat : RO; bitpos: [21]; default: 0;
+         *  NA
+         */
+        uint32_t slvif_wronhold_err_intstat: 1;
+        uint32_t reserved_22: 3;
+        /** slvif_wrparity_err_intstat : RO; bitpos: [25]; default: 0;
+         *  NA
+         */
+        uint32_t slvif_wrparity_err_intstat: 1;
+        uint32_t reserved_26: 1;
+        /** ch_lock_cleared_intstat : RO; bitpos: [27]; default: 0;
+         *  NA
+         */
+        uint32_t ch_lock_cleared_intstat: 1;
+        /** ch_src_suspended_intstat : RO; bitpos: [28]; default: 0;
+         *  NA
+         */
+        uint32_t ch_src_suspended_intstat: 1;
+        /** ch_suspended_intstat : RO; bitpos: [29]; default: 0;
+         *  NA
+         */
+        uint32_t ch_suspended_intstat: 1;
+        /** ch_disabled_intstat : RO; bitpos: [30]; default: 0;
+         *  NA
+         */
+        uint32_t ch_disabled_intstat: 1;
+        /** ch_aborted_intstat : RO; bitpos: [31]; default: 0;
+         *  NA
+         */
+        uint32_t ch_aborted_intstat: 1;
+    };
+    uint32_t val;
+} dmac_chn_intstatus0_reg_t;
+
+/** Type of chn_intstatus1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ecc_prot_chmem_correrr_intstat : RO; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ecc_prot_chmem_correrr_intstat: 1;
+        /** ecc_prot_chmem_uncorrerr_intstat : RO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t ecc_prot_chmem_uncorrerr_intstat: 1;
+        /** ecc_prot_uidmem_correrr_intstat : RO; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t ecc_prot_uidmem_correrr_intstat: 1;
+        /** ecc_prot_uidmem_uncorrerr_intstat : RO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t ecc_prot_uidmem_uncorrerr_intstat: 1;
+        uint32_t reserved_4: 28;
+    };
+    uint32_t val;
+} dmac_chn_intstatus1_reg_t;
+
+/** Type of chn_intsignal_enable0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** enable_block_tfr_done_intsignal : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t enable_block_tfr_done_intsignal: 1;
+        /** enable_dma_tfr_done_intsignal : R/W; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t enable_dma_tfr_done_intsignal: 1;
+        uint32_t reserved_2: 1;
+        /** enable_src_transcomp_intsignal : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t enable_src_transcomp_intsignal: 1;
+        /** enable_dst_transcomp_intsignal : R/W; bitpos: [4]; default: 1;
+         *  NA
+         */
+        uint32_t enable_dst_transcomp_intsignal: 1;
+        /** enable_src_dec_err_intsignal : R/W; bitpos: [5]; default: 1;
+         *  NA
+         */
+        uint32_t enable_src_dec_err_intsignal: 1;
+        /** enable_dst_dec_err_intsignal : R/W; bitpos: [6]; default: 1;
+         *  NA
+         */
+        uint32_t enable_dst_dec_err_intsignal: 1;
+        /** enable_src_slv_err_intsignal : R/W; bitpos: [7]; default: 1;
+         *  NA
+         */
+        uint32_t enable_src_slv_err_intsignal: 1;
+        /** enable_dst_slv_err_intsignal : R/W; bitpos: [8]; default: 1;
+         *  NA
+         */
+        uint32_t enable_dst_slv_err_intsignal: 1;
+        /** enable_lli_rd_dec_err_intsignal : R/W; bitpos: [9]; default: 1;
+         *  NA
+         */
+        uint32_t enable_lli_rd_dec_err_intsignal: 1;
+        /** enable_lli_wr_dec_err_intsignal : R/W; bitpos: [10]; default: 1;
+         *  NA
+         */
+        uint32_t enable_lli_wr_dec_err_intsignal: 1;
+        /** enable_lli_rd_slv_err_intsignal : R/W; bitpos: [11]; default: 1;
+         *  NA
+         */
+        uint32_t enable_lli_rd_slv_err_intsignal: 1;
+        /** enable_lli_wr_slv_err_intsignal : R/W; bitpos: [12]; default: 1;
+         *  NA
+         */
+        uint32_t enable_lli_wr_slv_err_intsignal: 1;
+        /** enable_shadowreg_or_lli_invalid_err_intsignal : R/W; bitpos: [13]; default: 1;
+         *  NA
+         */
+        uint32_t enable_shadowreg_or_lli_invalid_err_intsignal: 1;
+        /** enable_slvif_multiblktype_err_intsignal : R/W; bitpos: [14]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_multiblktype_err_intsignal: 1;
+        uint32_t reserved_15: 1;
+        /** enable_slvif_dec_err_intsignal : R/W; bitpos: [16]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_dec_err_intsignal: 1;
+        /** enable_slvif_wr2ro_err_intsignal : R/W; bitpos: [17]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_wr2ro_err_intsignal: 1;
+        /** enable_slvif_rd2rwo_err_intsignal : R/W; bitpos: [18]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_rd2rwo_err_intsignal: 1;
+        /** enable_slvif_wronchen_err_intsignal : R/W; bitpos: [19]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_wronchen_err_intsignal: 1;
+        /** enable_slvif_shadowreg_wron_valid_err_intsignal : R/W; bitpos: [20]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_shadowreg_wron_valid_err_intsignal: 1;
+        /** enable_slvif_wronhold_err_intsignal : R/W; bitpos: [21]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_wronhold_err_intsignal: 1;
+        uint32_t reserved_22: 3;
+        /** enable_slvif_wrparity_err_intsignal : RO; bitpos: [25]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_wrparity_err_intsignal: 1;
+        uint32_t reserved_26: 1;
+        /** enable_ch_lock_cleared_intsignal : R/W; bitpos: [27]; default: 1;
+         *  NA
+         */
+        uint32_t enable_ch_lock_cleared_intsignal: 1;
+        /** enable_ch_src_suspended_intsignal : R/W; bitpos: [28]; default: 1;
+         *  NA
+         */
+        uint32_t enable_ch_src_suspended_intsignal: 1;
+        /** enable_ch_suspended_intsignal : R/W; bitpos: [29]; default: 1;
+         *  NA
+         */
+        uint32_t enable_ch_suspended_intsignal: 1;
+        /** enable_ch_disabled_intsignal : R/W; bitpos: [30]; default: 1;
+         *  NA
+         */
+        uint32_t enable_ch_disabled_intsignal: 1;
+        /** enable_ch_aborted_intsignal : R/W; bitpos: [31]; default: 1;
+         *  NA
+         */
+        uint32_t enable_ch_aborted_intsignal: 1;
+    };
+    uint32_t val;
+} dmac_chn_intsignal_enable0_reg_t;
+
+/** Type of chn_intsignal_enable1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** enable_ecc_prot_chmem_correrr_intsignal : RO; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t enable_ecc_prot_chmem_correrr_intsignal: 1;
+        /** enable_ecc_prot_chmem_uncorrerr_intsignal : RO; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t enable_ecc_prot_chmem_uncorrerr_intsignal: 1;
+        /** enable_ecc_prot_uidmem_correrr_intsignal : RO; bitpos: [2]; default: 1;
+         *  NA
+         */
+        uint32_t enable_ecc_prot_uidmem_correrr_intsignal: 1;
+        /** enable_ecc_prot_uidmem_uncorrerr_intsignal : RO; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t enable_ecc_prot_uidmem_uncorrerr_intsignal: 1;
+        uint32_t reserved_4: 28;
+    };
+    uint32_t val;
+} dmac_chn_intsignal_enable1_reg_t;
+
+/** Type of chn_intclear0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** clear_block_tfr_done_intstat : WO; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t clear_block_tfr_done_intstat: 1;
+        /** clear_dma_tfr_done_intstat : WO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t clear_dma_tfr_done_intstat: 1;
+        uint32_t reserved_2: 1;
+        /** clear_src_transcomp_intstat : WO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t clear_src_transcomp_intstat: 1;
+        /** clear_dst_transcomp_intstat : WO; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t clear_dst_transcomp_intstat: 1;
+        /** clear_src_dec_err_intstat : WO; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t clear_src_dec_err_intstat: 1;
+        /** clear_dst_dec_err_intstat : WO; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t clear_dst_dec_err_intstat: 1;
+        /** clear_src_slv_err_intstat : WO; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t clear_src_slv_err_intstat: 1;
+        /** clear_dst_slv_err_intstat : WO; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t clear_dst_slv_err_intstat: 1;
+        /** clear_lli_rd_dec_err_intstat : WO; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t clear_lli_rd_dec_err_intstat: 1;
+        /** clear_lli_wr_dec_err_intstat : WO; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t clear_lli_wr_dec_err_intstat: 1;
+        /** clear_lli_rd_slv_err_intstat : WO; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t clear_lli_rd_slv_err_intstat: 1;
+        /** clear_lli_wr_slv_err_intstat : WO; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t clear_lli_wr_slv_err_intstat: 1;
+        /** clear_shadowreg_or_lli_invalid_err_intstat : WO; bitpos: [13]; default: 0;
+         *  NA
+         */
+        uint32_t clear_shadowreg_or_lli_invalid_err_intstat: 1;
+        /** clear_slvif_multiblktype_err_intstat : WO; bitpos: [14]; default: 0;
+         *  NA
+         */
+        uint32_t clear_slvif_multiblktype_err_intstat: 1;
+        uint32_t reserved_15: 1;
+        /** clear_slvif_dec_err_intstat : WO; bitpos: [16]; default: 0;
+         *  NA
+         */
+        uint32_t clear_slvif_dec_err_intstat: 1;
+        /** clear_slvif_wr2ro_err_intstat : WO; bitpos: [17]; default: 0;
+         *  NA
+         */
+        uint32_t clear_slvif_wr2ro_err_intstat: 1;
+        /** clear_slvif_rd2rwo_err_intstat : WO; bitpos: [18]; default: 0;
+         *  NA
+         */
+        uint32_t clear_slvif_rd2rwo_err_intstat: 1;
+        /** clear_slvif_wronchen_err_intstat : WO; bitpos: [19]; default: 0;
+         *  NA
+         */
+        uint32_t clear_slvif_wronchen_err_intstat: 1;
+        /** clear_slvif_shadowreg_wron_valid_err_intstat : WO; bitpos: [20]; default: 0;
+         *  NA
+         */
+        uint32_t clear_slvif_shadowreg_wron_valid_err_intstat: 1;
+        /** clear_slvif_wronhold_err_intstat : WO; bitpos: [21]; default: 0;
+         *  NA
+         */
+        uint32_t clear_slvif_wronhold_err_intstat: 1;
+        uint32_t reserved_22: 3;
+        /** clear_slvif_wrparity_err_intstat : WO; bitpos: [25]; default: 0;
+         *  NA
+         */
+        uint32_t clear_slvif_wrparity_err_intstat: 1;
+        uint32_t reserved_26: 1;
+        /** clear_ch_lock_cleared_intstat : WO; bitpos: [27]; default: 0;
+         *  NA
+         */
+        uint32_t clear_ch_lock_cleared_intstat: 1;
+        /** clear_ch_src_suspended_intstat : WO; bitpos: [28]; default: 0;
+         *  NA
+         */
+        uint32_t clear_ch_src_suspended_intstat: 1;
+        /** clear_ch_suspended_intstat : WO; bitpos: [29]; default: 0;
+         *  NA
+         */
+        uint32_t clear_ch_suspended_intstat: 1;
+        /** clear_ch_disabled_intstat : WO; bitpos: [30]; default: 0;
+         *  NA
+         */
+        uint32_t clear_ch_disabled_intstat: 1;
+        /** clear_ch_aborted_intstat : WO; bitpos: [31]; default: 0;
+         *  NA
+         */
+        uint32_t clear_ch_aborted_intstat: 1;
+    };
+    uint32_t val;
+} dmac_chn_intclear0_reg_t;
+
+/** Type of chn_intclear1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** clear_ecc_prot_chmem_correrr_intstat : WO; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t clear_ecc_prot_chmem_correrr_intstat: 1;
+        /** clear_ecc_prot_chmem_uncorrerr_intstat : WO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t clear_ecc_prot_chmem_uncorrerr_intstat: 1;
+        /** clear_ecc_prot_uidmem_correrr_intstat : WO; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t clear_ecc_prot_uidmem_correrr_intstat: 1;
+        /** clear_ecc_prot_uidmem_uncorrerr_intstat : WO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t clear_ecc_prot_uidmem_uncorrerr_intstat: 1;
+        uint32_t reserved_4: 28;
+    };
+    uint32_t val;
+} dmac_chn_intclear1_reg_t;
+
+/** Group: Status Registers */
+/** Type of chn_status0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** cmpltd_blk_tfr_size : RO; bitpos: [21:0]; default: 0;
+         *  NA
+         */
+        uint32_t cmpltd_blk_tfr_size: 22;
+        uint32_t reserved_22: 10;
+    };
+    uint32_t val;
+} dmac_chn_status0_reg_t;
+
+/** Type of chn_status1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** data_left_in_fifo : RO; bitpos: [14:0]; default: 0;
+         *  NA
+         */
+        uint32_t data_left_in_fifo: 15;
+        uint32_t reserved_15: 17;
+    };
+    uint32_t val;
+} dmac_chn_status1_reg_t;
+
+/** Type of chn_sstat0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** sstat : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t sstat: 32;
+    };
+    uint32_t val;
+} dmac_chn_sstat0_reg_t;
+
+/** Type of chn_dstat0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dstat : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dstat: 32;
+    };
+    uint32_t val;
+} dmac_chn_dstat0_reg_t;
+
+/** Type of chn_sstatar0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** sstatar0 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t sstatar0: 32;
+    };
+    uint32_t val;
+} dmac_chn_sstatar0_reg_t;
+
+/** Type of chn_sstatar1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** sstatar1 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t sstatar1: 32;
+    };
+    uint32_t val;
+} dmac_chn_sstatar1_reg_t;
+
+/** Type of chn_dstatar0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dstatar0 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dstatar0: 32;
+    };
+    uint32_t val;
+} dmac_chn_dstatar0_reg_t;
+
+/** Type of chn_dstatar1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dstatar1 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dstatar1: 32;
+    };
+    uint32_t val;
+} dmac_chn_dstatar1_reg_t;
+
+typedef struct {
+    volatile dmac_chn_sar0_reg_t sar0;
+    volatile dmac_chn_sar1_reg_t sar1;
+    volatile dmac_chn_dar0_reg_t dar0;
+    volatile dmac_chn_dar1_reg_t dar1;
+    volatile dmac_chn_block_ts0_reg_t block_ts0;
+    uint32_t reserved_114;
+    volatile dmac_chn_ctl0_reg_t ctl0;
+    volatile dmac_chn_ctl1_reg_t ctl1;
+    volatile dmac_chn_cfg0_reg_t cfg0;
+    volatile dmac_chn_cfg1_reg_t cfg1;
+    volatile dmac_chn_llp0_reg_t llp0;
+    volatile dmac_chn_llp1_reg_t llp1;
+    volatile dmac_chn_status0_reg_t status0;
+    volatile dmac_chn_status1_reg_t status1;
+    volatile dmac_chn_swhssrc0_reg_t swhssrc0;
+    uint32_t reserved_13c;
+    volatile dmac_chn_swhsdst0_reg_t swhsdst0;
+    uint32_t reserved_144;
+    volatile dmac_chn_blk_tfr_resumereq0_reg_t blk_tfr_resumereq0;
+    uint32_t reserved_14c;
+    volatile dmac_chn_axi_id0_reg_t axi_id0;
+    uint32_t reserved_154;
+    volatile dmac_chn_axi_qos0_reg_t axi_qos0;
+    uint32_t reserved_15c;
+    volatile dmac_chn_sstat0_reg_t sstat0;
+    uint32_t reserved_164;
+    volatile dmac_chn_dstat0_reg_t dstat0;
+    uint32_t reserved_16c;
+    volatile dmac_chn_sstatar0_reg_t sstatar0;
+    volatile dmac_chn_sstatar1_reg_t sstatar1;
+    volatile dmac_chn_dstatar0_reg_t dstatar0;
+    volatile dmac_chn_dstatar1_reg_t dstatar1;
+    volatile dmac_chn_intstatus_enable0_reg_t int_st_ena0;
+    volatile dmac_chn_intstatus_enable1_reg_t int_st_ena1;
+    volatile dmac_chn_intstatus0_reg_t int_st0;
+    volatile dmac_chn_intstatus1_reg_t int_st1;
+    volatile dmac_chn_intsignal_enable0_reg_t int_sig_ena0;
+    volatile dmac_chn_intsignal_enable1_reg_t int_sig_ena1;
+    volatile dmac_chn_intclear0_reg_t int_clr0;
+    volatile dmac_chn_intclear1_reg_t int_clr1;
+    uint32_t reserved_1a0[24];
+} dmac_channel_reg_t;
+
+typedef struct dw_gdma_dev_t {
+    volatile dmac_id0_reg_t id0;
+    uint32_t reserved_004;
+    volatile dmac_compver0_reg_t compver0;
+    uint32_t reserved_00c;
+    volatile dmac_cfg0_reg_t cfg0;
+    uint32_t reserved_014;
+    volatile dmac_chen0_reg_t chen0;
+    volatile dmac_chen1_reg_t chen1;
+    uint32_t reserved_020[4];
+    volatile dmac_intstatus0_reg_t int_st0;
+    uint32_t reserved_034;
+    volatile dmac_commonreg_intclear0_reg_t common_int_clr0;
+    uint32_t reserved_03c;
+    volatile dmac_commonreg_intstatus_enable0_reg_t common_int_st_ena0;
+    uint32_t reserved_044;
+    volatile dmac_commonreg_intsignal_enable0_reg_t common_int_sig_ena0;
+    uint32_t reserved_04c;
+    volatile dmac_commonreg_intstatus0_reg_t common_int_st0;
+    uint32_t reserved_054;
+    volatile dmac_reset0_reg_t reset0;
+    uint32_t reserved_05c;
+    volatile dmac_lowpower_cfg0_reg_t lowpower_cfg0;
+    volatile dmac_lowpower_cfg1_reg_t lowpower_cfg1;
+    uint32_t reserved_068[38];
+    volatile dmac_channel_reg_t ch[4];
+} dw_gdma_dev_t;
+
+extern dw_gdma_dev_t DW_GDMA;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(dw_gdma_dev_t) == 0x500, "Invalid size of dw_gdma_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32p4/include/soc/gdma_struct.h

@@ -1,5183 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: Version Register */
-/** Type of id0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** dmac_id : RO; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t dmac_id:32;
-    };
-    uint32_t val;
-} dmac_id0_reg_t;
-
-/** Type of compver0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** dmac_compver : RO; bitpos: [31:0]; default: 842018858;
-         *  NA
-         */
-        uint32_t dmac_compver:32;
-    };
-    uint32_t val;
-} dmac_compver0_reg_t;
-
-
-/** Group: Configuration Registers */
-/** Type of cfg0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** dmac_en : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t dmac_en:1;
-        /** int_en : R/W; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t int_en:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} dmac_cfg0_reg_t;
-
-/** Type of chen0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch1_en : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_en:1;
-        /** ch2_en : R/W; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_en:1;
-        /** ch3_en : R/W; bitpos: [2]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_en:1;
-        /** ch4_en : R/W; bitpos: [3]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_en:1;
-        uint32_t reserved_4:4;
-        /** ch1_en_we : WO; bitpos: [8]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_en_we:1;
-        /** ch2_en_we : WO; bitpos: [9]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_en_we:1;
-        /** ch3_en_we : WO; bitpos: [10]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_en_we:1;
-        /** ch4_en_we : WO; bitpos: [11]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_en_we:1;
-        uint32_t reserved_12:4;
-        /** ch1_susp : R/W; bitpos: [16]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_susp:1;
-        /** ch2_susp : R/W; bitpos: [17]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_susp:1;
-        /** ch3_susp : R/W; bitpos: [18]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_susp:1;
-        /** ch4_susp : R/W; bitpos: [19]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_susp:1;
-        uint32_t reserved_20:4;
-        /** ch1_susp_we : WO; bitpos: [24]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_susp_we:1;
-        /** ch2_susp_we : WO; bitpos: [25]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_susp_we:1;
-        /** ch3_susp_we : WO; bitpos: [26]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_susp_we:1;
-        /** ch4_susp_we : WO; bitpos: [27]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_susp_we:1;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} dmac_chen0_reg_t;
-
-/** Type of chen1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch1_abort : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_abort:1;
-        /** ch2_abort : R/W; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_abort:1;
-        /** ch3_abort : R/W; bitpos: [2]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_abort:1;
-        /** ch4_abort : R/W; bitpos: [3]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_abort:1;
-        uint32_t reserved_4:4;
-        /** ch1_abort_we : WO; bitpos: [8]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_abort_we:1;
-        /** ch2_abort_we : WO; bitpos: [9]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_abort_we:1;
-        /** ch3_abort_we : WO; bitpos: [10]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_abort_we:1;
-        /** ch4_abort_we : WO; bitpos: [11]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_abort_we:1;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} dmac_chen1_reg_t;
-
-/** Type of reset0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** dmac_rst : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t dmac_rst:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} dmac_reset0_reg_t;
-
-/** Type of lowpower_cfg0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** gbl_cslp_en : R/W; bitpos: [0]; default: 1;
-         *  NA
-         */
-        uint32_t gbl_cslp_en:1;
-        /** chnl_cslp_en : R/W; bitpos: [1]; default: 1;
-         *  NA
-         */
-        uint32_t chnl_cslp_en:1;
-        /** sbiu_cslp_en : R/W; bitpos: [2]; default: 1;
-         *  NA
-         */
-        uint32_t sbiu_cslp_en:1;
-        /** mxif_cslp_en : R/W; bitpos: [3]; default: 1;
-         *  NA
-         */
-        uint32_t mxif_cslp_en:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} dmac_lowpower_cfg0_reg_t;
-
-/** Type of lowpower_cfg1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** glch_lpdly : R/W; bitpos: [7:0]; default: 64;
-         *  NA
-         */
-        uint32_t glch_lpdly:8;
-        /** sbiu_lpdly : R/W; bitpos: [15:8]; default: 64;
-         *  NA
-         */
-        uint32_t sbiu_lpdly:8;
-        /** mxif_lpdly : R/W; bitpos: [23:16]; default: 64;
-         *  NA
-         */
-        uint32_t mxif_lpdly:8;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} dmac_lowpower_cfg1_reg_t;
-
-/** Type of ch1_sar0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch1_sar0 : R/W; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_sar0:32;
-    };
-    uint32_t val;
-} dmac_ch1_sar0_reg_t;
-
-/** Type of ch1_sar1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch1_sar1 : R/W; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_sar1:32;
-    };
-    uint32_t val;
-} dmac_ch1_sar1_reg_t;
-
-/** Type of ch1_dar0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch1_dar0 : R/W; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_dar0:32;
-    };
-    uint32_t val;
-} dmac_ch1_dar0_reg_t;
-
-/** Type of ch1_dar1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch1_dar1 : R/W; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_dar1:32;
-    };
-    uint32_t val;
-} dmac_ch1_dar1_reg_t;
-
-/** Type of ch1_block_ts0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch1_block_ts : R/W; bitpos: [21:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_block_ts:22;
-        uint32_t reserved_22:10;
-    };
-    uint32_t val;
-} dmac_ch1_block_ts0_reg_t;
-
-/** Type of ch1_ctl0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch1_sms : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_sms:1;
-        uint32_t reserved_1:1;
-        /** ch1_dms : R/W; bitpos: [2]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_dms:1;
-        uint32_t reserved_3:1;
-        /** ch1_sinc : R/W; bitpos: [4]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_sinc:1;
-        uint32_t reserved_5:1;
-        /** ch1_dinc : R/W; bitpos: [6]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_dinc:1;
-        uint32_t reserved_7:1;
-        /** ch1_src_tr_width : R/W; bitpos: [10:8]; default: 2;
-         *  NA
-         */
-        uint32_t ch1_src_tr_width:3;
-        /** ch1_dst_tr_width : R/W; bitpos: [13:11]; default: 2;
-         *  NA
-         */
-        uint32_t ch1_dst_tr_width:3;
-        /** ch1_src_msize : R/W; bitpos: [17:14]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_src_msize:4;
-        /** ch1_dst_msize : R/W; bitpos: [21:18]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_dst_msize:4;
-        /** ch1_ar_cache : R/W; bitpos: [25:22]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_ar_cache:4;
-        /** ch1_aw_cache : R/W; bitpos: [29:26]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_aw_cache:4;
-        /** ch1_nonposted_lastwrite_en : R/W; bitpos: [30]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_nonposted_lastwrite_en:1;
-        uint32_t reserved_31:1;
-    };
-    uint32_t val;
-} dmac_ch1_ctl0_reg_t;
-
-/** Type of ch1_ctl1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch1_ar_prot : R/W; bitpos: [2:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_ar_prot:3;
-        /** ch1_aw_prot : R/W; bitpos: [5:3]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_aw_prot:3;
-        /** ch1_arlen_en : R/W; bitpos: [6]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_arlen_en:1;
-        /** ch1_arlen : R/W; bitpos: [14:7]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_arlen:8;
-        /** ch1_awlen_en : R/W; bitpos: [15]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_awlen_en:1;
-        /** ch1_awlen : R/W; bitpos: [23:16]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_awlen:8;
-        /** ch1_src_stat_en : R/W; bitpos: [24]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_src_stat_en:1;
-        /** ch1_dst_stat_en : R/W; bitpos: [25]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_dst_stat_en:1;
-        /** ch1_ioc_blktfr : R/W; bitpos: [26]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_ioc_blktfr:1;
-        uint32_t reserved_27:3;
-        /** ch1_shadowreg_or_lli_last : R/W; bitpos: [30]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_shadowreg_or_lli_last:1;
-        /** ch1_shadowreg_or_lli_valid : R/W; bitpos: [31]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_shadowreg_or_lli_valid:1;
-    };
-    uint32_t val;
-} dmac_ch1_ctl1_reg_t;
-
-/** Type of ch1_cfg0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch1_src_multblk_type : R/W; bitpos: [1:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_src_multblk_type:2;
-        /** ch1_dst_multblk_type : R/W; bitpos: [3:2]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_dst_multblk_type:2;
-        uint32_t reserved_4:14;
-        /** ch1_rd_uid : RO; bitpos: [21:18]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_rd_uid:4;
-        uint32_t reserved_22:3;
-        /** ch1_wr_uid : RO; bitpos: [28:25]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_wr_uid:4;
-        uint32_t reserved_29:3;
-    };
-    uint32_t val;
-} dmac_ch1_cfg0_reg_t;
-
-/** Type of ch1_cfg1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch1_tt_fc : R/W; bitpos: [2:0]; default: 3;
-         *  NA
-         */
-        uint32_t ch1_tt_fc:3;
-        /** ch1_hs_sel_src : R/W; bitpos: [3]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_hs_sel_src:1;
-        /** ch1_hs_sel_dst : R/W; bitpos: [4]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_hs_sel_dst:1;
-        /** ch1_src_hwhs_pol : RO; bitpos: [5]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_src_hwhs_pol:1;
-        /** ch1_dst_hwhs_pol : RO; bitpos: [6]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_dst_hwhs_pol:1;
-        /** ch1_src_per : R/W; bitpos: [8:7]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_src_per:2;
-        uint32_t reserved_9:3;
-        /** ch1_dst_per : R/W; bitpos: [13:12]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_dst_per:2;
-        uint32_t reserved_14:3;
-        /** ch1_ch_prior : R/W; bitpos: [19:17]; default: 3;
-         *  NA
-         */
-        uint32_t ch1_ch_prior:3;
-        /** ch1_lock_ch : RO; bitpos: [20]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_lock_ch:1;
-        /** ch1_lock_ch_l : RO; bitpos: [22:21]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_lock_ch_l:2;
-        /** ch1_src_osr_lmt : R/W; bitpos: [26:23]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_src_osr_lmt:4;
-        /** ch1_dst_osr_lmt : R/W; bitpos: [30:27]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_dst_osr_lmt:4;
-        uint32_t reserved_31:1;
-    };
-    uint32_t val;
-} dmac_ch1_cfg1_reg_t;
-
-/** Type of ch1_llp0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch1_lms : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_lms:1;
-        uint32_t reserved_1:5;
-        /** ch1_loc0 : R/W; bitpos: [31:6]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_loc0:26;
-    };
-    uint32_t val;
-} dmac_ch1_llp0_reg_t;
-
-/** Type of ch1_llp1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch1_loc1 : R/W; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_loc1:32;
-    };
-    uint32_t val;
-} dmac_ch1_llp1_reg_t;
-
-/** Type of ch1_swhssrc0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch1_swhs_req_src : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_swhs_req_src:1;
-        /** ch1_swhs_req_src_we : WO; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_swhs_req_src_we:1;
-        /** ch1_swhs_sglreq_src : R/W; bitpos: [2]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_swhs_sglreq_src:1;
-        /** ch1_swhs_sglreq_src_we : WO; bitpos: [3]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_swhs_sglreq_src_we:1;
-        /** ch1_swhs_lst_src : R/W; bitpos: [4]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_swhs_lst_src:1;
-        /** ch1_swhs_lst_src_we : WO; bitpos: [5]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_swhs_lst_src_we:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} dmac_ch1_swhssrc0_reg_t;
-
-/** Type of ch1_swhsdst0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch1_swhs_req_dst : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_swhs_req_dst:1;
-        /** ch1_swhs_req_dst_we : WO; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_swhs_req_dst_we:1;
-        /** ch1_swhs_sglreq_dst : R/W; bitpos: [2]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_swhs_sglreq_dst:1;
-        /** ch1_swhs_sglreq_dst_we : WO; bitpos: [3]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_swhs_sglreq_dst_we:1;
-        /** ch1_swhs_lst_dst : R/W; bitpos: [4]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_swhs_lst_dst:1;
-        /** ch1_swhs_lst_dst_we : WO; bitpos: [5]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_swhs_lst_dst_we:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} dmac_ch1_swhsdst0_reg_t;
-
-/** Type of ch1_blk_tfr_resumereq0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch1_blk_tfr_resumereq : WO; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_blk_tfr_resumereq:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} dmac_ch1_blk_tfr_resumereq0_reg_t;
-
-/** Type of ch1_axi_id0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch1_axi_read_id_suffix : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_axi_read_id_suffix:1;
-        uint32_t reserved_1:15;
-        /** ch1_axi_write_id_suffix : R/W; bitpos: [16]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_axi_write_id_suffix:1;
-        uint32_t reserved_17:15;
-    };
-    uint32_t val;
-} dmac_ch1_axi_id0_reg_t;
-
-/** Type of ch1_axi_qos0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch1_axi_awqos : R/W; bitpos: [3:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_axi_awqos:4;
-        /** ch1_axi_arqos : R/W; bitpos: [7:4]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_axi_arqos:4;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} dmac_ch1_axi_qos0_reg_t;
-
-/** Type of ch2_sar0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch2_sar0 : R/W; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_sar0:32;
-    };
-    uint32_t val;
-} dmac_ch2_sar0_reg_t;
-
-/** Type of ch2_sar1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch2_sar1 : R/W; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_sar1:32;
-    };
-    uint32_t val;
-} dmac_ch2_sar1_reg_t;
-
-/** Type of ch2_dar0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch2_dar0 : R/W; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_dar0:32;
-    };
-    uint32_t val;
-} dmac_ch2_dar0_reg_t;
-
-/** Type of ch2_dar1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch2_dar1 : R/W; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_dar1:32;
-    };
-    uint32_t val;
-} dmac_ch2_dar1_reg_t;
-
-/** Type of ch2_block_ts0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch2_block_ts : R/W; bitpos: [21:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_block_ts:22;
-        uint32_t reserved_22:10;
-    };
-    uint32_t val;
-} dmac_ch2_block_ts0_reg_t;
-
-/** Type of ch2_ctl0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch2_sms : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_sms:1;
-        uint32_t reserved_1:1;
-        /** ch2_dms : R/W; bitpos: [2]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_dms:1;
-        uint32_t reserved_3:1;
-        /** ch2_sinc : R/W; bitpos: [4]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_sinc:1;
-        uint32_t reserved_5:1;
-        /** ch2_dinc : R/W; bitpos: [6]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_dinc:1;
-        uint32_t reserved_7:1;
-        /** ch2_src_tr_width : R/W; bitpos: [10:8]; default: 2;
-         *  NA
-         */
-        uint32_t ch2_src_tr_width:3;
-        /** ch2_dst_tr_width : R/W; bitpos: [13:11]; default: 2;
-         *  NA
-         */
-        uint32_t ch2_dst_tr_width:3;
-        /** ch2_src_msize : R/W; bitpos: [17:14]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_src_msize:4;
-        /** ch2_dst_msize : R/W; bitpos: [21:18]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_dst_msize:4;
-        /** ch2_ar_cache : R/W; bitpos: [25:22]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_ar_cache:4;
-        /** ch2_aw_cache : R/W; bitpos: [29:26]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_aw_cache:4;
-        /** ch2_nonposted_lastwrite_en : R/W; bitpos: [30]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_nonposted_lastwrite_en:1;
-        uint32_t reserved_31:1;
-    };
-    uint32_t val;
-} dmac_ch2_ctl0_reg_t;
-
-/** Type of ch2_ctl1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch2_ar_prot : R/W; bitpos: [2:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_ar_prot:3;
-        /** ch2_aw_prot : R/W; bitpos: [5:3]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_aw_prot:3;
-        /** ch2_arlen_en : R/W; bitpos: [6]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_arlen_en:1;
-        /** ch2_arlen : R/W; bitpos: [14:7]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_arlen:8;
-        /** ch2_awlen_en : R/W; bitpos: [15]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_awlen_en:1;
-        /** ch2_awlen : R/W; bitpos: [23:16]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_awlen:8;
-        /** ch2_src_stat_en : R/W; bitpos: [24]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_src_stat_en:1;
-        /** ch2_dst_stat_en : R/W; bitpos: [25]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_dst_stat_en:1;
-        /** ch2_ioc_blktfr : R/W; bitpos: [26]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_ioc_blktfr:1;
-        uint32_t reserved_27:3;
-        /** ch2_shadowreg_or_lli_last : R/W; bitpos: [30]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_shadowreg_or_lli_last:1;
-        /** ch2_shadowreg_or_lli_valid : R/W; bitpos: [31]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_shadowreg_or_lli_valid:1;
-    };
-    uint32_t val;
-} dmac_ch2_ctl1_reg_t;
-
-/** Type of ch2_cfg0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch2_src_multblk_type : R/W; bitpos: [1:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_src_multblk_type:2;
-        /** ch2_dst_multblk_type : R/W; bitpos: [3:2]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_dst_multblk_type:2;
-        uint32_t reserved_4:14;
-        /** ch2_rd_uid : RO; bitpos: [21:18]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_rd_uid:4;
-        uint32_t reserved_22:3;
-        /** ch2_wr_uid : RO; bitpos: [28:25]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_wr_uid:4;
-        uint32_t reserved_29:3;
-    };
-    uint32_t val;
-} dmac_ch2_cfg0_reg_t;
-
-/** Type of ch2_cfg1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch2_tt_fc : R/W; bitpos: [2:0]; default: 3;
-         *  NA
-         */
-        uint32_t ch2_tt_fc:3;
-        /** ch2_hs_sel_src : R/W; bitpos: [3]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_hs_sel_src:1;
-        /** ch2_hs_sel_dst : R/W; bitpos: [4]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_hs_sel_dst:1;
-        /** ch2_src_hwhs_pol : RO; bitpos: [5]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_src_hwhs_pol:1;
-        /** ch2_dst_hwhs_pol : RO; bitpos: [6]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_dst_hwhs_pol:1;
-        /** ch2_src_per : R/W; bitpos: [8:7]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_src_per:2;
-        uint32_t reserved_9:3;
-        /** ch2_dst_per : R/W; bitpos: [13:12]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_dst_per:2;
-        uint32_t reserved_14:3;
-        /** ch2_ch_prior : R/W; bitpos: [19:17]; default: 2;
-         *  NA
-         */
-        uint32_t ch2_ch_prior:3;
-        /** ch2_lock_ch : RO; bitpos: [20]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_lock_ch:1;
-        /** ch2_lock_ch_l : RO; bitpos: [22:21]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_lock_ch_l:2;
-        /** ch2_src_osr_lmt : R/W; bitpos: [26:23]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_src_osr_lmt:4;
-        /** ch2_dst_osr_lmt : R/W; bitpos: [30:27]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_dst_osr_lmt:4;
-        uint32_t reserved_31:1;
-    };
-    uint32_t val;
-} dmac_ch2_cfg1_reg_t;
-
-/** Type of ch2_llp0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch2_lms : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_lms:1;
-        uint32_t reserved_1:5;
-        /** ch2_loc0 : R/W; bitpos: [31:6]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_loc0:26;
-    };
-    uint32_t val;
-} dmac_ch2_llp0_reg_t;
-
-/** Type of ch2_llp1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch2_loc1 : R/W; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_loc1:32;
-    };
-    uint32_t val;
-} dmac_ch2_llp1_reg_t;
-
-/** Type of ch2_swhssrc0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch2_swhs_req_src : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_swhs_req_src:1;
-        /** ch2_swhs_req_src_we : WO; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_swhs_req_src_we:1;
-        /** ch2_swhs_sglreq_src : R/W; bitpos: [2]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_swhs_sglreq_src:1;
-        /** ch2_swhs_sglreq_src_we : WO; bitpos: [3]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_swhs_sglreq_src_we:1;
-        /** ch2_swhs_lst_src : R/W; bitpos: [4]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_swhs_lst_src:1;
-        /** ch2_swhs_lst_src_we : WO; bitpos: [5]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_swhs_lst_src_we:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} dmac_ch2_swhssrc0_reg_t;
-
-/** Type of ch2_swhsdst0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch2_swhs_req_dst : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_swhs_req_dst:1;
-        /** ch2_swhs_req_dst_we : WO; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_swhs_req_dst_we:1;
-        /** ch2_swhs_sglreq_dst : R/W; bitpos: [2]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_swhs_sglreq_dst:1;
-        /** ch2_swhs_sglreq_dst_we : WO; bitpos: [3]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_swhs_sglreq_dst_we:1;
-        /** ch2_swhs_lst_dst : R/W; bitpos: [4]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_swhs_lst_dst:1;
-        /** ch2_swhs_lst_dst_we : WO; bitpos: [5]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_swhs_lst_dst_we:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} dmac_ch2_swhsdst0_reg_t;
-
-/** Type of ch2_blk_tfr_resumereq0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch2_blk_tfr_resumereq : WO; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_blk_tfr_resumereq:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} dmac_ch2_blk_tfr_resumereq0_reg_t;
-
-/** Type of ch2_axi_id0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch2_axi_read_id_suffix : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_axi_read_id_suffix:1;
-        uint32_t reserved_1:15;
-        /** ch2_axi_write_id_suffix : R/W; bitpos: [16]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_axi_write_id_suffix:1;
-        uint32_t reserved_17:15;
-    };
-    uint32_t val;
-} dmac_ch2_axi_id0_reg_t;
-
-/** Type of ch2_axi_qos0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch2_axi_awqos : R/W; bitpos: [3:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_axi_awqos:4;
-        /** ch2_axi_arqos : R/W; bitpos: [7:4]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_axi_arqos:4;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} dmac_ch2_axi_qos0_reg_t;
-
-/** Type of ch3_sar0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch3_sar0 : R/W; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_sar0:32;
-    };
-    uint32_t val;
-} dmac_ch3_sar0_reg_t;
-
-/** Type of ch3_sar1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch3_sar1 : R/W; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_sar1:32;
-    };
-    uint32_t val;
-} dmac_ch3_sar1_reg_t;
-
-/** Type of ch3_dar0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch3_dar0 : R/W; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_dar0:32;
-    };
-    uint32_t val;
-} dmac_ch3_dar0_reg_t;
-
-/** Type of ch3_dar1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch3_dar1 : R/W; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_dar1:32;
-    };
-    uint32_t val;
-} dmac_ch3_dar1_reg_t;
-
-/** Type of ch3_block_ts0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch3_block_ts : R/W; bitpos: [21:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_block_ts:22;
-        uint32_t reserved_22:10;
-    };
-    uint32_t val;
-} dmac_ch3_block_ts0_reg_t;
-
-/** Type of ch3_ctl0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch3_sms : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_sms:1;
-        uint32_t reserved_1:1;
-        /** ch3_dms : R/W; bitpos: [2]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_dms:1;
-        uint32_t reserved_3:1;
-        /** ch3_sinc : R/W; bitpos: [4]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_sinc:1;
-        uint32_t reserved_5:1;
-        /** ch3_dinc : R/W; bitpos: [6]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_dinc:1;
-        uint32_t reserved_7:1;
-        /** ch3_src_tr_width : R/W; bitpos: [10:8]; default: 2;
-         *  NA
-         */
-        uint32_t ch3_src_tr_width:3;
-        /** ch3_dst_tr_width : R/W; bitpos: [13:11]; default: 2;
-         *  NA
-         */
-        uint32_t ch3_dst_tr_width:3;
-        /** ch3_src_msize : R/W; bitpos: [17:14]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_src_msize:4;
-        /** ch3_dst_msize : R/W; bitpos: [21:18]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_dst_msize:4;
-        /** ch3_ar_cache : R/W; bitpos: [25:22]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_ar_cache:4;
-        /** ch3_aw_cache : R/W; bitpos: [29:26]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_aw_cache:4;
-        /** ch3_nonposted_lastwrite_en : R/W; bitpos: [30]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_nonposted_lastwrite_en:1;
-        uint32_t reserved_31:1;
-    };
-    uint32_t val;
-} dmac_ch3_ctl0_reg_t;
-
-/** Type of ch3_ctl1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch3_ar_prot : R/W; bitpos: [2:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_ar_prot:3;
-        /** ch3_aw_prot : R/W; bitpos: [5:3]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_aw_prot:3;
-        /** ch3_arlen_en : R/W; bitpos: [6]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_arlen_en:1;
-        /** ch3_arlen : R/W; bitpos: [14:7]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_arlen:8;
-        /** ch3_awlen_en : R/W; bitpos: [15]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_awlen_en:1;
-        /** ch3_awlen : R/W; bitpos: [23:16]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_awlen:8;
-        /** ch3_src_stat_en : R/W; bitpos: [24]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_src_stat_en:1;
-        /** ch3_dst_stat_en : R/W; bitpos: [25]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_dst_stat_en:1;
-        /** ch3_ioc_blktfr : R/W; bitpos: [26]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_ioc_blktfr:1;
-        uint32_t reserved_27:3;
-        /** ch3_shadowreg_or_lli_last : R/W; bitpos: [30]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_shadowreg_or_lli_last:1;
-        /** ch3_shadowreg_or_lli_valid : R/W; bitpos: [31]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_shadowreg_or_lli_valid:1;
-    };
-    uint32_t val;
-} dmac_ch3_ctl1_reg_t;
-
-/** Type of ch3_cfg0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch3_src_multblk_type : R/W; bitpos: [1:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_src_multblk_type:2;
-        /** ch3_dst_multblk_type : R/W; bitpos: [3:2]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_dst_multblk_type:2;
-        uint32_t reserved_4:14;
-        /** ch3_rd_uid : RO; bitpos: [21:18]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_rd_uid:4;
-        uint32_t reserved_22:3;
-        /** ch3_wr_uid : RO; bitpos: [28:25]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_wr_uid:4;
-        uint32_t reserved_29:3;
-    };
-    uint32_t val;
-} dmac_ch3_cfg0_reg_t;
-
-/** Type of ch3_cfg1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch3_tt_fc : R/W; bitpos: [2:0]; default: 3;
-         *  NA
-         */
-        uint32_t ch3_tt_fc:3;
-        /** ch3_hs_sel_src : R/W; bitpos: [3]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_hs_sel_src:1;
-        /** ch3_hs_sel_dst : R/W; bitpos: [4]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_hs_sel_dst:1;
-        /** ch3_src_hwhs_pol : RO; bitpos: [5]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_src_hwhs_pol:1;
-        /** ch3_dst_hwhs_pol : RO; bitpos: [6]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_dst_hwhs_pol:1;
-        /** ch3_src_per : R/W; bitpos: [8:7]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_src_per:2;
-        uint32_t reserved_9:3;
-        /** ch3_dst_per : R/W; bitpos: [13:12]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_dst_per:2;
-        uint32_t reserved_14:3;
-        /** ch3_ch_prior : R/W; bitpos: [19:17]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_ch_prior:3;
-        /** ch3_lock_ch : RO; bitpos: [20]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_lock_ch:1;
-        /** ch3_lock_ch_l : RO; bitpos: [22:21]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_lock_ch_l:2;
-        /** ch3_src_osr_lmt : R/W; bitpos: [26:23]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_src_osr_lmt:4;
-        /** ch3_dst_osr_lmt : R/W; bitpos: [30:27]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_dst_osr_lmt:4;
-        uint32_t reserved_31:1;
-    };
-    uint32_t val;
-} dmac_ch3_cfg1_reg_t;
-
-/** Type of ch3_llp0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch3_lms : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_lms:1;
-        uint32_t reserved_1:5;
-        /** ch3_loc0 : R/W; bitpos: [31:6]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_loc0:26;
-    };
-    uint32_t val;
-} dmac_ch3_llp0_reg_t;
-
-/** Type of ch3_llp1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch3_loc1 : R/W; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_loc1:32;
-    };
-    uint32_t val;
-} dmac_ch3_llp1_reg_t;
-
-/** Type of ch3_swhssrc0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch3_swhs_req_src : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_swhs_req_src:1;
-        /** ch3_swhs_req_src_we : WO; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_swhs_req_src_we:1;
-        /** ch3_swhs_sglreq_src : R/W; bitpos: [2]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_swhs_sglreq_src:1;
-        /** ch3_swhs_sglreq_src_we : WO; bitpos: [3]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_swhs_sglreq_src_we:1;
-        /** ch3_swhs_lst_src : R/W; bitpos: [4]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_swhs_lst_src:1;
-        /** ch3_swhs_lst_src_we : WO; bitpos: [5]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_swhs_lst_src_we:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} dmac_ch3_swhssrc0_reg_t;
-
-/** Type of ch3_swhsdst0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch3_swhs_req_dst : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_swhs_req_dst:1;
-        /** ch3_swhs_req_dst_we : WO; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_swhs_req_dst_we:1;
-        /** ch3_swhs_sglreq_dst : R/W; bitpos: [2]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_swhs_sglreq_dst:1;
-        /** ch3_swhs_sglreq_dst_we : WO; bitpos: [3]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_swhs_sglreq_dst_we:1;
-        /** ch3_swhs_lst_dst : R/W; bitpos: [4]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_swhs_lst_dst:1;
-        /** ch3_swhs_lst_dst_we : WO; bitpos: [5]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_swhs_lst_dst_we:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} dmac_ch3_swhsdst0_reg_t;
-
-/** Type of ch3_blk_tfr_resumereq0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch3_blk_tfr_resumereq : WO; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_blk_tfr_resumereq:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} dmac_ch3_blk_tfr_resumereq0_reg_t;
-
-/** Type of ch3_axi_id0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch3_axi_read_id_suffix : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_axi_read_id_suffix:1;
-        uint32_t reserved_1:15;
-        /** ch3_axi_write_id_suffix : R/W; bitpos: [16]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_axi_write_id_suffix:1;
-        uint32_t reserved_17:15;
-    };
-    uint32_t val;
-} dmac_ch3_axi_id0_reg_t;
-
-/** Type of ch3_axi_qos0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch3_axi_awqos : R/W; bitpos: [3:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_axi_awqos:4;
-        /** ch3_axi_arqos : R/W; bitpos: [7:4]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_axi_arqos:4;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} dmac_ch3_axi_qos0_reg_t;
-
-/** Type of ch4_sar0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch4_sar0 : R/W; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_sar0:32;
-    };
-    uint32_t val;
-} dmac_ch4_sar0_reg_t;
-
-/** Type of ch4_sar1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch4_sar1 : R/W; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_sar1:32;
-    };
-    uint32_t val;
-} dmac_ch4_sar1_reg_t;
-
-/** Type of ch4_dar0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch4_dar0 : R/W; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_dar0:32;
-    };
-    uint32_t val;
-} dmac_ch4_dar0_reg_t;
-
-/** Type of ch4_dar1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch4_dar1 : R/W; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_dar1:32;
-    };
-    uint32_t val;
-} dmac_ch4_dar1_reg_t;
-
-/** Type of ch4_block_ts0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch4_block_ts : R/W; bitpos: [21:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_block_ts:22;
-        uint32_t reserved_22:10;
-    };
-    uint32_t val;
-} dmac_ch4_block_ts0_reg_t;
-
-/** Type of ch4_ctl0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch4_sms : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_sms:1;
-        uint32_t reserved_1:1;
-        /** ch4_dms : R/W; bitpos: [2]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_dms:1;
-        uint32_t reserved_3:1;
-        /** ch4_sinc : R/W; bitpos: [4]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_sinc:1;
-        uint32_t reserved_5:1;
-        /** ch4_dinc : R/W; bitpos: [6]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_dinc:1;
-        uint32_t reserved_7:1;
-        /** ch4_src_tr_width : R/W; bitpos: [10:8]; default: 2;
-         *  NA
-         */
-        uint32_t ch4_src_tr_width:3;
-        /** ch4_dst_tr_width : R/W; bitpos: [13:11]; default: 2;
-         *  NA
-         */
-        uint32_t ch4_dst_tr_width:3;
-        /** ch4_src_msize : R/W; bitpos: [17:14]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_src_msize:4;
-        /** ch4_dst_msize : R/W; bitpos: [21:18]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_dst_msize:4;
-        /** ch4_ar_cache : R/W; bitpos: [25:22]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_ar_cache:4;
-        /** ch4_aw_cache : R/W; bitpos: [29:26]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_aw_cache:4;
-        /** ch4_nonposted_lastwrite_en : R/W; bitpos: [30]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_nonposted_lastwrite_en:1;
-        uint32_t reserved_31:1;
-    };
-    uint32_t val;
-} dmac_ch4_ctl0_reg_t;
-
-/** Type of ch4_ctl1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch4_ar_prot : R/W; bitpos: [2:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_ar_prot:3;
-        /** ch4_aw_prot : R/W; bitpos: [5:3]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_aw_prot:3;
-        /** ch4_arlen_en : R/W; bitpos: [6]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_arlen_en:1;
-        /** ch4_arlen : R/W; bitpos: [14:7]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_arlen:8;
-        /** ch4_awlen_en : R/W; bitpos: [15]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_awlen_en:1;
-        /** ch4_awlen : R/W; bitpos: [23:16]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_awlen:8;
-        /** ch4_src_stat_en : R/W; bitpos: [24]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_src_stat_en:1;
-        /** ch4_dst_stat_en : R/W; bitpos: [25]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_dst_stat_en:1;
-        /** ch4_ioc_blktfr : R/W; bitpos: [26]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_ioc_blktfr:1;
-        uint32_t reserved_27:3;
-        /** ch4_shadowreg_or_lli_last : R/W; bitpos: [30]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_shadowreg_or_lli_last:1;
-        /** ch4_shadowreg_or_lli_valid : R/W; bitpos: [31]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_shadowreg_or_lli_valid:1;
-    };
-    uint32_t val;
-} dmac_ch4_ctl1_reg_t;
-
-/** Type of ch4_cfg0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch4_src_multblk_type : R/W; bitpos: [1:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_src_multblk_type:2;
-        /** ch4_dst_multblk_type : R/W; bitpos: [3:2]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_dst_multblk_type:2;
-        uint32_t reserved_4:14;
-        /** ch4_rd_uid : RO; bitpos: [21:18]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_rd_uid:4;
-        uint32_t reserved_22:3;
-        /** ch4_wr_uid : RO; bitpos: [28:25]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_wr_uid:4;
-        uint32_t reserved_29:3;
-    };
-    uint32_t val;
-} dmac_ch4_cfg0_reg_t;
-
-/** Type of ch4_cfg1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch4_tt_fc : R/W; bitpos: [2:0]; default: 3;
-         *  NA
-         */
-        uint32_t ch4_tt_fc:3;
-        /** ch4_hs_sel_src : R/W; bitpos: [3]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_hs_sel_src:1;
-        /** ch4_hs_sel_dst : R/W; bitpos: [4]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_hs_sel_dst:1;
-        /** ch4_src_hwhs_pol : RO; bitpos: [5]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_src_hwhs_pol:1;
-        /** ch4_dst_hwhs_pol : RO; bitpos: [6]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_dst_hwhs_pol:1;
-        /** ch4_src_per : R/W; bitpos: [8:7]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_src_per:2;
-        uint32_t reserved_9:3;
-        /** ch4_dst_per : R/W; bitpos: [13:12]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_dst_per:2;
-        uint32_t reserved_14:3;
-        /** ch4_ch_prior : R/W; bitpos: [19:17]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_ch_prior:3;
-        /** ch4_lock_ch : RO; bitpos: [20]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_lock_ch:1;
-        /** ch4_lock_ch_l : RO; bitpos: [22:21]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_lock_ch_l:2;
-        /** ch4_src_osr_lmt : R/W; bitpos: [26:23]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_src_osr_lmt:4;
-        /** ch4_dst_osr_lmt : R/W; bitpos: [30:27]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_dst_osr_lmt:4;
-        uint32_t reserved_31:1;
-    };
-    uint32_t val;
-} dmac_ch4_cfg1_reg_t;
-
-/** Type of ch4_llp0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch4_lms : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_lms:1;
-        uint32_t reserved_1:5;
-        /** ch4_loc0 : R/W; bitpos: [31:6]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_loc0:26;
-    };
-    uint32_t val;
-} dmac_ch4_llp0_reg_t;
-
-/** Type of ch4_llp1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch4_loc1 : R/W; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_loc1:32;
-    };
-    uint32_t val;
-} dmac_ch4_llp1_reg_t;
-
-/** Type of ch4_swhssrc0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch4_swhs_req_src : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_swhs_req_src:1;
-        /** ch4_swhs_req_src_we : WO; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_swhs_req_src_we:1;
-        /** ch4_swhs_sglreq_src : R/W; bitpos: [2]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_swhs_sglreq_src:1;
-        /** ch4_swhs_sglreq_src_we : WO; bitpos: [3]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_swhs_sglreq_src_we:1;
-        /** ch4_swhs_lst_src : R/W; bitpos: [4]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_swhs_lst_src:1;
-        /** ch4_swhs_lst_src_we : WO; bitpos: [5]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_swhs_lst_src_we:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} dmac_ch4_swhssrc0_reg_t;
-
-/** Type of ch4_swhsdst0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch4_swhs_req_dst : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_swhs_req_dst:1;
-        /** ch4_swhs_req_dst_we : WO; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_swhs_req_dst_we:1;
-        /** ch4_swhs_sglreq_dst : R/W; bitpos: [2]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_swhs_sglreq_dst:1;
-        /** ch4_swhs_sglreq_dst_we : WO; bitpos: [3]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_swhs_sglreq_dst_we:1;
-        /** ch4_swhs_lst_dst : R/W; bitpos: [4]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_swhs_lst_dst:1;
-        /** ch4_swhs_lst_dst_we : WO; bitpos: [5]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_swhs_lst_dst_we:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} dmac_ch4_swhsdst0_reg_t;
-
-/** Type of ch4_blk_tfr_resumereq0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch4_blk_tfr_resumereq : WO; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_blk_tfr_resumereq:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} dmac_ch4_blk_tfr_resumereq0_reg_t;
-
-/** Type of ch4_axi_id0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch4_axi_read_id_suffix : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_axi_read_id_suffix:1;
-        uint32_t reserved_1:15;
-        /** ch4_axi_write_id_suffix : R/W; bitpos: [16]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_axi_write_id_suffix:1;
-        uint32_t reserved_17:15;
-    };
-    uint32_t val;
-} dmac_ch4_axi_id0_reg_t;
-
-/** Type of ch4_axi_qos0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch4_axi_awqos : R/W; bitpos: [3:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_axi_awqos:4;
-        /** ch4_axi_arqos : R/W; bitpos: [7:4]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_axi_arqos:4;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} dmac_ch4_axi_qos0_reg_t;
-
-
-/** Group: Interrupt Registers */
-/** Type of intstatus0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch1_intstat : RO; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_intstat:1;
-        /** ch2_intstat : RO; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_intstat:1;
-        /** ch3_intstat : RO; bitpos: [2]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_intstat:1;
-        /** ch4_intstat : RO; bitpos: [3]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_intstat:1;
-        uint32_t reserved_4:12;
-        /** commonreg_intstat : RO; bitpos: [16]; default: 0;
-         *  NA
-         */
-        uint32_t commonreg_intstat:1;
-        uint32_t reserved_17:15;
-    };
-    uint32_t val;
-} dmac_intstatus0_reg_t;
-
-/** Type of commonreg_intclear0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** clear_slvif_commonreg_dec_err_intstat : WO; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t clear_slvif_commonreg_dec_err_intstat:1;
-        /** clear_slvif_commonreg_wr2ro_err_intstat : WO; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t clear_slvif_commonreg_wr2ro_err_intstat:1;
-        /** clear_slvif_commonreg_rd2wo_err_intstat : WO; bitpos: [2]; default: 0;
-         *  NA
-         */
-        uint32_t clear_slvif_commonreg_rd2wo_err_intstat:1;
-        /** clear_slvif_commonreg_wronhold_err_intstat : WO; bitpos: [3]; default: 0;
-         *  NA
-         */
-        uint32_t clear_slvif_commonreg_wronhold_err_intstat:1;
-        uint32_t reserved_4:3;
-        /** clear_slvif_commonreg_wrparity_err_intstat : WO; bitpos: [7]; default: 0;
-         *  NA
-         */
-        uint32_t clear_slvif_commonreg_wrparity_err_intstat:1;
-        /** clear_slvif_undefinedreg_dec_err_intstat : WO; bitpos: [8]; default: 0;
-         *  NA
-         */
-        uint32_t clear_slvif_undefinedreg_dec_err_intstat:1;
-        /** clear_mxif1_rch0_eccprot_correrr_intstat : WO; bitpos: [9]; default: 0;
-         *  NA
-         */
-        uint32_t clear_mxif1_rch0_eccprot_correrr_intstat:1;
-        /** clear_mxif1_rch0_eccprot_uncorrerr_intstat : WO; bitpos: [10]; default: 0;
-         *  NA
-         */
-        uint32_t clear_mxif1_rch0_eccprot_uncorrerr_intstat:1;
-        /** clear_mxif1_rch1_eccprot_correrr_intstat : WO; bitpos: [11]; default: 0;
-         *  NA
-         */
-        uint32_t clear_mxif1_rch1_eccprot_correrr_intstat:1;
-        /** clear_mxif1_rch1_eccprot_uncorrerr_intstat : WO; bitpos: [12]; default: 0;
-         *  NA
-         */
-        uint32_t clear_mxif1_rch1_eccprot_uncorrerr_intstat:1;
-        /** clear_mxif1_bch_eccprot_correrr_intstat : WO; bitpos: [13]; default: 0;
-         *  NA
-         */
-        uint32_t clear_mxif1_bch_eccprot_correrr_intstat:1;
-        /** clear_mxif1_bch_eccprot_uncorrerr_intstat : WO; bitpos: [14]; default: 0;
-         *  NA
-         */
-        uint32_t clear_mxif1_bch_eccprot_uncorrerr_intstat:1;
-        /** clear_mxif2_rch0_eccprot_correrr_intstat : WO; bitpos: [15]; default: 0;
-         *  NA
-         */
-        uint32_t clear_mxif2_rch0_eccprot_correrr_intstat:1;
-        /** clear_mxif2_rch0_eccprot_uncorrerr_intstat : WO; bitpos: [16]; default: 0;
-         *  NA
-         */
-        uint32_t clear_mxif2_rch0_eccprot_uncorrerr_intstat:1;
-        /** clear_mxif2_rch1_eccprot_correrr_intstat : WO; bitpos: [17]; default: 0;
-         *  NA
-         */
-        uint32_t clear_mxif2_rch1_eccprot_correrr_intstat:1;
-        /** clear_mxif2_rch1_eccprot_uncorrerr_intstat : WO; bitpos: [18]; default: 0;
-         *  NA
-         */
-        uint32_t clear_mxif2_rch1_eccprot_uncorrerr_intstat:1;
-        /** clear_mxif2_bch_eccprot_correrr_intstat : WO; bitpos: [19]; default: 0;
-         *  NA
-         */
-        uint32_t clear_mxif2_bch_eccprot_correrr_intstat:1;
-        /** clear_mxif2_bch_eccprot_uncorrerr_intstat : WO; bitpos: [20]; default: 0;
-         *  NA
-         */
-        uint32_t clear_mxif2_bch_eccprot_uncorrerr_intstat:1;
-        uint32_t reserved_21:11;
-    };
-    uint32_t val;
-} dmac_commonreg_intclear0_reg_t;
-
-/** Type of commonreg_intstatus_enable0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** enable_slvif_commonreg_dec_err_intstat : R/W; bitpos: [0]; default: 1;
-         *  NA
-         */
-        uint32_t enable_slvif_commonreg_dec_err_intstat:1;
-        /** enable_slvif_commonreg_wr2ro_err_intstat : R/W; bitpos: [1]; default: 1;
-         *  NA
-         */
-        uint32_t enable_slvif_commonreg_wr2ro_err_intstat:1;
-        /** enable_slvif_commonreg_rd2wo_err_intstat : R/W; bitpos: [2]; default: 1;
-         *  NA
-         */
-        uint32_t enable_slvif_commonreg_rd2wo_err_intstat:1;
-        /** enable_slvif_commonreg_wronhold_err_intstat : R/W; bitpos: [3]; default: 1;
-         *  NA
-         */
-        uint32_t enable_slvif_commonreg_wronhold_err_intstat:1;
-        uint32_t reserved_4:3;
-        /** enable_slvif_commonreg_wrparity_err_intstat : RO; bitpos: [7]; default: 1;
-         *  NA
-         */
-        uint32_t enable_slvif_commonreg_wrparity_err_intstat:1;
-        /** enable_slvif_undefinedreg_dec_err_intstat : R/W; bitpos: [8]; default: 1;
-         *  NA
-         */
-        uint32_t enable_slvif_undefinedreg_dec_err_intstat:1;
-        /** enable_mxif1_rch0_eccprot_correrr_intstat : RO; bitpos: [9]; default: 1;
-         *  NA
-         */
-        uint32_t enable_mxif1_rch0_eccprot_correrr_intstat:1;
-        /** enable_mxif1_rch0_eccprot_uncorrerr_intstat : RO; bitpos: [10]; default: 1;
-         *  NA
-         */
-        uint32_t enable_mxif1_rch0_eccprot_uncorrerr_intstat:1;
-        /** enable_mxif1_rch1_eccprot_correrr_intstat : RO; bitpos: [11]; default: 1;
-         *  NA
-         */
-        uint32_t enable_mxif1_rch1_eccprot_correrr_intstat:1;
-        /** enable_mxif1_rch1_eccprot_uncorrerr_intstat : RO; bitpos: [12]; default: 1;
-         *  NA
-         */
-        uint32_t enable_mxif1_rch1_eccprot_uncorrerr_intstat:1;
-        /** enable_mxif1_bch_eccprot_correrr_intstat : RO; bitpos: [13]; default: 1;
-         *  NA
-         */
-        uint32_t enable_mxif1_bch_eccprot_correrr_intstat:1;
-        /** enable_mxif1_bch_eccprot_uncorrerr_intstat : RO; bitpos: [14]; default: 1;
-         *  NA
-         */
-        uint32_t enable_mxif1_bch_eccprot_uncorrerr_intstat:1;
-        /** enable_mxif2_rch0_eccprot_correrr_intstat : RO; bitpos: [15]; default: 1;
-         *  NA
-         */
-        uint32_t enable_mxif2_rch0_eccprot_correrr_intstat:1;
-        /** enable_mxif2_rch0_eccprot_uncorrerr_intstat : RO; bitpos: [16]; default: 1;
-         *  NA
-         */
-        uint32_t enable_mxif2_rch0_eccprot_uncorrerr_intstat:1;
-        /** enable_mxif2_rch1_eccprot_correrr_intstat : RO; bitpos: [17]; default: 1;
-         *  NA
-         */
-        uint32_t enable_mxif2_rch1_eccprot_correrr_intstat:1;
-        /** enable_mxif2_rch1_eccprot_uncorrerr_intstat : RO; bitpos: [18]; default: 1;
-         *  NA
-         */
-        uint32_t enable_mxif2_rch1_eccprot_uncorrerr_intstat:1;
-        /** enable_mxif2_bch_eccprot_correrr_intstat : RO; bitpos: [19]; default: 1;
-         *  NA
-         */
-        uint32_t enable_mxif2_bch_eccprot_correrr_intstat:1;
-        /** enable_mxif2_bch_eccprot_uncorrerr_intstat : RO; bitpos: [20]; default: 1;
-         *  NA
-         */
-        uint32_t enable_mxif2_bch_eccprot_uncorrerr_intstat:1;
-        uint32_t reserved_21:11;
-    };
-    uint32_t val;
-} dmac_commonreg_intstatus_enable0_reg_t;
-
-/** Type of commonreg_intsignal_enable0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** enable_slvif_commonreg_dec_err_intsignal : R/W; bitpos: [0]; default: 1;
-         *  NA
-         */
-        uint32_t enable_slvif_commonreg_dec_err_intsignal:1;
-        /** enable_slvif_commonreg_wr2ro_err_intsignal : R/W; bitpos: [1]; default: 1;
-         *  NA
-         */
-        uint32_t enable_slvif_commonreg_wr2ro_err_intsignal:1;
-        /** enable_slvif_commonreg_rd2wo_err_intsignal : R/W; bitpos: [2]; default: 1;
-         *  NA
-         */
-        uint32_t enable_slvif_commonreg_rd2wo_err_intsignal:1;
-        /** enable_slvif_commonreg_wronhold_err_intsignal : R/W; bitpos: [3]; default: 1;
-         *  NA
-         */
-        uint32_t enable_slvif_commonreg_wronhold_err_intsignal:1;
-        uint32_t reserved_4:3;
-        /** enable_slvif_commonreg_wrparity_err_intsignal : RO; bitpos: [7]; default: 1;
-         *  NA
-         */
-        uint32_t enable_slvif_commonreg_wrparity_err_intsignal:1;
-        /** enable_slvif_undefinedreg_dec_err_intsignal : R/W; bitpos: [8]; default: 1;
-         *  NA
-         */
-        uint32_t enable_slvif_undefinedreg_dec_err_intsignal:1;
-        /** enable_mxif1_rch0_eccprot_correrr_intsignal : RO; bitpos: [9]; default: 1;
-         *  NA
-         */
-        uint32_t enable_mxif1_rch0_eccprot_correrr_intsignal:1;
-        /** enable_mxif1_rch0_eccprot_uncorrerr_intsignal : RO; bitpos: [10]; default: 1;
-         *  NA
-         */
-        uint32_t enable_mxif1_rch0_eccprot_uncorrerr_intsignal:1;
-        /** enable_mxif1_rch1_eccprot_correrr_intsignal : RO; bitpos: [11]; default: 1;
-         *  NA
-         */
-        uint32_t enable_mxif1_rch1_eccprot_correrr_intsignal:1;
-        /** enable_mxif1_rch1_eccprot_uncorrerr_intsignal : RO; bitpos: [12]; default: 1;
-         *  NA
-         */
-        uint32_t enable_mxif1_rch1_eccprot_uncorrerr_intsignal:1;
-        /** enable_mxif1_bch_eccprot_correrr_intsignal : RO; bitpos: [13]; default: 1;
-         *  NA
-         */
-        uint32_t enable_mxif1_bch_eccprot_correrr_intsignal:1;
-        /** enable_mxif1_bch_eccprot_uncorrerr_intsignal : RO; bitpos: [14]; default: 1;
-         *  NA
-         */
-        uint32_t enable_mxif1_bch_eccprot_uncorrerr_intsignal:1;
-        /** enable_mxif2_rch0_eccprot_correrr_intsignal : RO; bitpos: [15]; default: 1;
-         *  NA
-         */
-        uint32_t enable_mxif2_rch0_eccprot_correrr_intsignal:1;
-        /** enable_mxif2_rch0_eccprot_uncorrerr_intsignal : RO; bitpos: [16]; default: 1;
-         *  NA
-         */
-        uint32_t enable_mxif2_rch0_eccprot_uncorrerr_intsignal:1;
-        /** enable_mxif2_rch1_eccprot_correrr_intsignal : RO; bitpos: [17]; default: 1;
-         *  NA
-         */
-        uint32_t enable_mxif2_rch1_eccprot_correrr_intsignal:1;
-        /** enable_mxif2_rch1_eccprot_uncorrerr_intsignal : RO; bitpos: [18]; default: 1;
-         *  NA
-         */
-        uint32_t enable_mxif2_rch1_eccprot_uncorrerr_intsignal:1;
-        /** enable_mxif2_bch_eccprot_correrr_intsignal : RO; bitpos: [19]; default: 1;
-         *  NA
-         */
-        uint32_t enable_mxif2_bch_eccprot_correrr_intsignal:1;
-        /** enable_mxif2_bch_eccprot_uncorrerr_intsignal : RO; bitpos: [20]; default: 1;
-         *  NA
-         */
-        uint32_t enable_mxif2_bch_eccprot_uncorrerr_intsignal:1;
-        uint32_t reserved_21:11;
-    };
-    uint32_t val;
-} dmac_commonreg_intsignal_enable0_reg_t;
-
-/** Type of commonreg_intstatus0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** slvif_commonreg_dec_err_intstat : RO; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t slvif_commonreg_dec_err_intstat:1;
-        /** slvif_commonreg_wr2ro_err_intstat : RO; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t slvif_commonreg_wr2ro_err_intstat:1;
-        /** slvif_commonreg_rd2wo_err_intstat : RO; bitpos: [2]; default: 0;
-         *  NA
-         */
-        uint32_t slvif_commonreg_rd2wo_err_intstat:1;
-        /** slvif_commonreg_wronhold_err_intstat : RO; bitpos: [3]; default: 0;
-         *  NA
-         */
-        uint32_t slvif_commonreg_wronhold_err_intstat:1;
-        uint32_t reserved_4:3;
-        /** slvif_commonreg_wrparity_err_intstat : RO; bitpos: [7]; default: 0;
-         *  NA
-         */
-        uint32_t slvif_commonreg_wrparity_err_intstat:1;
-        /** slvif_undefinedreg_dec_err_intstat : RO; bitpos: [8]; default: 0;
-         *  NA
-         */
-        uint32_t slvif_undefinedreg_dec_err_intstat:1;
-        /** mxif1_rch0_eccprot_correrr_intstat : RO; bitpos: [9]; default: 0;
-         *  NA
-         */
-        uint32_t mxif1_rch0_eccprot_correrr_intstat:1;
-        /** mxif1_rch0_eccprot_uncorrerr_intstat : RO; bitpos: [10]; default: 0;
-         *  NA
-         */
-        uint32_t mxif1_rch0_eccprot_uncorrerr_intstat:1;
-        /** mxif1_rch1_eccprot_correrr_intstat : RO; bitpos: [11]; default: 0;
-         *  NA
-         */
-        uint32_t mxif1_rch1_eccprot_correrr_intstat:1;
-        /** mxif1_rch1_eccprot_uncorrerr_intstat : RO; bitpos: [12]; default: 0;
-         *  NA
-         */
-        uint32_t mxif1_rch1_eccprot_uncorrerr_intstat:1;
-        /** mxif1_bch_eccprot_correrr_intstat : RO; bitpos: [13]; default: 0;
-         *  NA
-         */
-        uint32_t mxif1_bch_eccprot_correrr_intstat:1;
-        /** mxif1_bch_eccprot_uncorrerr_intstat : RO; bitpos: [14]; default: 0;
-         *  NA
-         */
-        uint32_t mxif1_bch_eccprot_uncorrerr_intstat:1;
-        /** mxif2_rch0_eccprot_correrr_intstat : RO; bitpos: [15]; default: 0;
-         *  NA
-         */
-        uint32_t mxif2_rch0_eccprot_correrr_intstat:1;
-        /** mxif2_rch0_eccprot_uncorrerr_intstat : RO; bitpos: [16]; default: 0;
-         *  NA
-         */
-        uint32_t mxif2_rch0_eccprot_uncorrerr_intstat:1;
-        /** mxif2_rch1_eccprot_correrr_intstat : RO; bitpos: [17]; default: 0;
-         *  NA
-         */
-        uint32_t mxif2_rch1_eccprot_correrr_intstat:1;
-        /** mxif2_rch1_eccprot_uncorrerr_intstat : RO; bitpos: [18]; default: 0;
-         *  NA
-         */
-        uint32_t mxif2_rch1_eccprot_uncorrerr_intstat:1;
-        /** mxif2_bch_eccprot_correrr_intstat : RO; bitpos: [19]; default: 0;
-         *  NA
-         */
-        uint32_t mxif2_bch_eccprot_correrr_intstat:1;
-        /** mxif2_bch_eccprot_uncorrerr_intstat : RO; bitpos: [20]; default: 0;
-         *  NA
-         */
-        uint32_t mxif2_bch_eccprot_uncorrerr_intstat:1;
-        uint32_t reserved_21:11;
-    };
-    uint32_t val;
-} dmac_commonreg_intstatus0_reg_t;
-
-/** Type of ch1_intstatus_enable0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch1_enable_block_tfr_done_intstat : R/W; bitpos: [0]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_block_tfr_done_intstat:1;
-        /** ch1_enable_dma_tfr_done_intstat : R/W; bitpos: [1]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_dma_tfr_done_intstat:1;
-        uint32_t reserved_2:1;
-        /** ch1_enable_src_transcomp_intstat : R/W; bitpos: [3]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_src_transcomp_intstat:1;
-        /** ch1_enable_dst_transcomp_intstat : R/W; bitpos: [4]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_dst_transcomp_intstat:1;
-        /** ch1_enable_src_dec_err_intstat : R/W; bitpos: [5]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_src_dec_err_intstat:1;
-        /** ch1_enable_dst_dec_err_intstat : R/W; bitpos: [6]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_dst_dec_err_intstat:1;
-        /** ch1_enable_src_slv_err_intstat : R/W; bitpos: [7]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_src_slv_err_intstat:1;
-        /** ch1_enable_dst_slv_err_intstat : R/W; bitpos: [8]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_dst_slv_err_intstat:1;
-        /** ch1_enable_lli_rd_dec_err_intstat : R/W; bitpos: [9]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_lli_rd_dec_err_intstat:1;
-        /** ch1_enable_lli_wr_dec_err_intstat : R/W; bitpos: [10]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_lli_wr_dec_err_intstat:1;
-        /** ch1_enable_lli_rd_slv_err_intstat : R/W; bitpos: [11]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_lli_rd_slv_err_intstat:1;
-        /** ch1_enable_lli_wr_slv_err_intstat : R/W; bitpos: [12]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_lli_wr_slv_err_intstat:1;
-        /** ch1_enable_shadowreg_or_lli_invalid_err_intstat : R/W; bitpos: [13]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_shadowreg_or_lli_invalid_err_intstat:1;
-        /** ch1_enable_slvif_multiblktype_err_intstat : R/W; bitpos: [14]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_slvif_multiblktype_err_intstat:1;
-        uint32_t reserved_15:1;
-        /** ch1_enable_slvif_dec_err_intstat : R/W; bitpos: [16]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_slvif_dec_err_intstat:1;
-        /** ch1_enable_slvif_wr2ro_err_intstat : R/W; bitpos: [17]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_slvif_wr2ro_err_intstat:1;
-        /** ch1_enable_slvif_rd2rwo_err_intstat : R/W; bitpos: [18]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_slvif_rd2rwo_err_intstat:1;
-        /** ch1_enable_slvif_wronchen_err_intstat : R/W; bitpos: [19]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_slvif_wronchen_err_intstat:1;
-        /** ch1_enable_slvif_shadowreg_wron_valid_err_intstat : R/W; bitpos: [20]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_slvif_shadowreg_wron_valid_err_intstat:1;
-        /** ch1_enable_slvif_wronhold_err_intstat : R/W; bitpos: [21]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_slvif_wronhold_err_intstat:1;
-        uint32_t reserved_22:3;
-        /** ch1_enable_slvif_wrparity_err_intstat : RO; bitpos: [25]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_slvif_wrparity_err_intstat:1;
-        uint32_t reserved_26:1;
-        /** ch1_enable_ch_lock_cleared_intstat : R/W; bitpos: [27]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_ch_lock_cleared_intstat:1;
-        /** ch1_enable_ch_src_suspended_intstat : R/W; bitpos: [28]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_ch_src_suspended_intstat:1;
-        /** ch1_enable_ch_suspended_intstat : R/W; bitpos: [29]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_ch_suspended_intstat:1;
-        /** ch1_enable_ch_disabled_intstat : R/W; bitpos: [30]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_ch_disabled_intstat:1;
-        /** ch1_enable_ch_aborted_intstat : R/W; bitpos: [31]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_ch_aborted_intstat:1;
-    };
-    uint32_t val;
-} dmac_ch1_intstatus_enable0_reg_t;
-
-/** Type of ch1_intstatus_enable1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch1_enable_ecc_prot_chmem_correrr_intstat : RO; bitpos: [0]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_ecc_prot_chmem_correrr_intstat:1;
-        /** ch1_enable_ecc_prot_chmem_uncorrerr_intstat : RO; bitpos: [1]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_ecc_prot_chmem_uncorrerr_intstat:1;
-        /** ch1_enable_ecc_prot_uidmem_correrr_intstat : RO; bitpos: [2]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_ecc_prot_uidmem_correrr_intstat:1;
-        /** ch1_enable_ecc_prot_uidmem_uncorrerr_intstat : RO; bitpos: [3]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_ecc_prot_uidmem_uncorrerr_intstat:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} dmac_ch1_intstatus_enable1_reg_t;
-
-/** Type of ch1_intstatus0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch1_block_tfr_done_intstat : RO; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_block_tfr_done_intstat:1;
-        /** ch1_dma_tfr_done_intstat : RO; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_dma_tfr_done_intstat:1;
-        uint32_t reserved_2:1;
-        /** ch1_src_transcomp_intstat : RO; bitpos: [3]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_src_transcomp_intstat:1;
-        /** ch1_dst_transcomp_intstat : RO; bitpos: [4]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_dst_transcomp_intstat:1;
-        /** ch1_src_dec_err_intstat : RO; bitpos: [5]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_src_dec_err_intstat:1;
-        /** ch1_dst_dec_err_intstat : RO; bitpos: [6]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_dst_dec_err_intstat:1;
-        /** ch1_src_slv_err_intstat : RO; bitpos: [7]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_src_slv_err_intstat:1;
-        /** ch1_dst_slv_err_intstat : RO; bitpos: [8]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_dst_slv_err_intstat:1;
-        /** ch1_lli_rd_dec_err_intstat : RO; bitpos: [9]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_lli_rd_dec_err_intstat:1;
-        /** ch1_lli_wr_dec_err_intstat : RO; bitpos: [10]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_lli_wr_dec_err_intstat:1;
-        /** ch1_lli_rd_slv_err_intstat : RO; bitpos: [11]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_lli_rd_slv_err_intstat:1;
-        /** ch1_lli_wr_slv_err_intstat : RO; bitpos: [12]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_lli_wr_slv_err_intstat:1;
-        /** ch1_shadowreg_or_lli_invalid_err_intstat : RO; bitpos: [13]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_shadowreg_or_lli_invalid_err_intstat:1;
-        /** ch1_slvif_multiblktype_err_intstat : RO; bitpos: [14]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_slvif_multiblktype_err_intstat:1;
-        uint32_t reserved_15:1;
-        /** ch1_slvif_dec_err_intstat : RO; bitpos: [16]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_slvif_dec_err_intstat:1;
-        /** ch1_slvif_wr2ro_err_intstat : RO; bitpos: [17]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_slvif_wr2ro_err_intstat:1;
-        /** ch1_slvif_rd2rwo_err_intstat : RO; bitpos: [18]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_slvif_rd2rwo_err_intstat:1;
-        /** ch1_slvif_wronchen_err_intstat : RO; bitpos: [19]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_slvif_wronchen_err_intstat:1;
-        /** ch1_slvif_shadowreg_wron_valid_err_intstat : RO; bitpos: [20]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_slvif_shadowreg_wron_valid_err_intstat:1;
-        /** ch1_slvif_wronhold_err_intstat : RO; bitpos: [21]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_slvif_wronhold_err_intstat:1;
-        uint32_t reserved_22:3;
-        /** ch1_slvif_wrparity_err_intstat : RO; bitpos: [25]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_slvif_wrparity_err_intstat:1;
-        uint32_t reserved_26:1;
-        /** ch1_ch_lock_cleared_intstat : RO; bitpos: [27]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_ch_lock_cleared_intstat:1;
-        /** ch1_ch_src_suspended_intstat : RO; bitpos: [28]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_ch_src_suspended_intstat:1;
-        /** ch1_ch_suspended_intstat : RO; bitpos: [29]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_ch_suspended_intstat:1;
-        /** ch1_ch_disabled_intstat : RO; bitpos: [30]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_ch_disabled_intstat:1;
-        /** ch1_ch_aborted_intstat : RO; bitpos: [31]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_ch_aborted_intstat:1;
-    };
-    uint32_t val;
-} dmac_ch1_intstatus0_reg_t;
-
-/** Type of ch1_intstatus1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch1_ecc_prot_chmem_correrr_intstat : RO; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_ecc_prot_chmem_correrr_intstat:1;
-        /** ch1_ecc_prot_chmem_uncorrerr_intstat : RO; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_ecc_prot_chmem_uncorrerr_intstat:1;
-        /** ch1_ecc_prot_uidmem_correrr_intstat : RO; bitpos: [2]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_ecc_prot_uidmem_correrr_intstat:1;
-        /** ch1_ecc_prot_uidmem_uncorrerr_intstat : RO; bitpos: [3]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_ecc_prot_uidmem_uncorrerr_intstat:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} dmac_ch1_intstatus1_reg_t;
-
-/** Type of ch1_intsignal_enable0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch1_enable_block_tfr_done_intsignal : R/W; bitpos: [0]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_block_tfr_done_intsignal:1;
-        /** ch1_enable_dma_tfr_done_intsignal : R/W; bitpos: [1]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_dma_tfr_done_intsignal:1;
-        uint32_t reserved_2:1;
-        /** ch1_enable_src_transcomp_intsignal : R/W; bitpos: [3]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_src_transcomp_intsignal:1;
-        /** ch1_enable_dst_transcomp_intsignal : R/W; bitpos: [4]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_dst_transcomp_intsignal:1;
-        /** ch1_enable_src_dec_err_intsignal : R/W; bitpos: [5]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_src_dec_err_intsignal:1;
-        /** ch1_enable_dst_dec_err_intsignal : R/W; bitpos: [6]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_dst_dec_err_intsignal:1;
-        /** ch1_enable_src_slv_err_intsignal : R/W; bitpos: [7]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_src_slv_err_intsignal:1;
-        /** ch1_enable_dst_slv_err_intsignal : R/W; bitpos: [8]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_dst_slv_err_intsignal:1;
-        /** ch1_enable_lli_rd_dec_err_intsignal : R/W; bitpos: [9]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_lli_rd_dec_err_intsignal:1;
-        /** ch1_enable_lli_wr_dec_err_intsignal : R/W; bitpos: [10]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_lli_wr_dec_err_intsignal:1;
-        /** ch1_enable_lli_rd_slv_err_intsignal : R/W; bitpos: [11]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_lli_rd_slv_err_intsignal:1;
-        /** ch1_enable_lli_wr_slv_err_intsignal : R/W; bitpos: [12]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_lli_wr_slv_err_intsignal:1;
-        /** ch1_enable_shadowreg_or_lli_invalid_err_intsignal : R/W; bitpos: [13]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_shadowreg_or_lli_invalid_err_intsignal:1;
-        /** ch1_enable_slvif_multiblktype_err_intsignal : R/W; bitpos: [14]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_slvif_multiblktype_err_intsignal:1;
-        uint32_t reserved_15:1;
-        /** ch1_enable_slvif_dec_err_intsignal : R/W; bitpos: [16]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_slvif_dec_err_intsignal:1;
-        /** ch1_enable_slvif_wr2ro_err_intsignal : R/W; bitpos: [17]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_slvif_wr2ro_err_intsignal:1;
-        /** ch1_enable_slvif_rd2rwo_err_intsignal : R/W; bitpos: [18]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_slvif_rd2rwo_err_intsignal:1;
-        /** ch1_enable_slvif_wronchen_err_intsignal : R/W; bitpos: [19]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_slvif_wronchen_err_intsignal:1;
-        /** ch1_enable_slvif_shadowreg_wron_valid_err_intsignal : R/W; bitpos: [20]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_slvif_shadowreg_wron_valid_err_intsignal:1;
-        /** ch1_enable_slvif_wronhold_err_intsignal : R/W; bitpos: [21]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_slvif_wronhold_err_intsignal:1;
-        uint32_t reserved_22:3;
-        /** ch1_enable_slvif_wrparity_err_intsignal : RO; bitpos: [25]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_slvif_wrparity_err_intsignal:1;
-        uint32_t reserved_26:1;
-        /** ch1_enable_ch_lock_cleared_intsignal : R/W; bitpos: [27]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_ch_lock_cleared_intsignal:1;
-        /** ch1_enable_ch_src_suspended_intsignal : R/W; bitpos: [28]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_ch_src_suspended_intsignal:1;
-        /** ch1_enable_ch_suspended_intsignal : R/W; bitpos: [29]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_ch_suspended_intsignal:1;
-        /** ch1_enable_ch_disabled_intsignal : R/W; bitpos: [30]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_ch_disabled_intsignal:1;
-        /** ch1_enable_ch_aborted_intsignal : R/W; bitpos: [31]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_ch_aborted_intsignal:1;
-    };
-    uint32_t val;
-} dmac_ch1_intsignal_enable0_reg_t;
-
-/** Type of ch1_intsignal_enable1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch1_enable_ecc_prot_chmem_correrr_intsignal : RO; bitpos: [0]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_ecc_prot_chmem_correrr_intsignal:1;
-        /** ch1_enable_ecc_prot_chmem_uncorrerr_intsignal : RO; bitpos: [1]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_ecc_prot_chmem_uncorrerr_intsignal:1;
-        /** ch1_enable_ecc_prot_uidmem_correrr_intsignal : RO; bitpos: [2]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_ecc_prot_uidmem_correrr_intsignal:1;
-        /** ch1_enable_ecc_prot_uidmem_uncorrerr_intsignal : RO; bitpos: [3]; default: 1;
-         *  NA
-         */
-        uint32_t ch1_enable_ecc_prot_uidmem_uncorrerr_intsignal:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} dmac_ch1_intsignal_enable1_reg_t;
-
-/** Type of ch1_intclear0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch1_clear_block_tfr_done_intstat : WO; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_clear_block_tfr_done_intstat:1;
-        /** ch1_clear_dma_tfr_done_intstat : WO; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_clear_dma_tfr_done_intstat:1;
-        uint32_t reserved_2:1;
-        /** ch1_clear_src_transcomp_intstat : WO; bitpos: [3]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_clear_src_transcomp_intstat:1;
-        /** ch1_clear_dst_transcomp_intstat : WO; bitpos: [4]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_clear_dst_transcomp_intstat:1;
-        /** ch1_clear_src_dec_err_intstat : WO; bitpos: [5]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_clear_src_dec_err_intstat:1;
-        /** ch1_clear_dst_dec_err_intstat : WO; bitpos: [6]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_clear_dst_dec_err_intstat:1;
-        /** ch1_clear_src_slv_err_intstat : WO; bitpos: [7]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_clear_src_slv_err_intstat:1;
-        /** ch1_clear_dst_slv_err_intstat : WO; bitpos: [8]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_clear_dst_slv_err_intstat:1;
-        /** ch1_clear_lli_rd_dec_err_intstat : WO; bitpos: [9]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_clear_lli_rd_dec_err_intstat:1;
-        /** ch1_clear_lli_wr_dec_err_intstat : WO; bitpos: [10]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_clear_lli_wr_dec_err_intstat:1;
-        /** ch1_clear_lli_rd_slv_err_intstat : WO; bitpos: [11]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_clear_lli_rd_slv_err_intstat:1;
-        /** ch1_clear_lli_wr_slv_err_intstat : WO; bitpos: [12]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_clear_lli_wr_slv_err_intstat:1;
-        /** ch1_clear_shadowreg_or_lli_invalid_err_intstat : WO; bitpos: [13]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_clear_shadowreg_or_lli_invalid_err_intstat:1;
-        /** ch1_clear_slvif_multiblktype_err_intstat : WO; bitpos: [14]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_clear_slvif_multiblktype_err_intstat:1;
-        uint32_t reserved_15:1;
-        /** ch1_clear_slvif_dec_err_intstat : WO; bitpos: [16]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_clear_slvif_dec_err_intstat:1;
-        /** ch1_clear_slvif_wr2ro_err_intstat : WO; bitpos: [17]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_clear_slvif_wr2ro_err_intstat:1;
-        /** ch1_clear_slvif_rd2rwo_err_intstat : WO; bitpos: [18]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_clear_slvif_rd2rwo_err_intstat:1;
-        /** ch1_clear_slvif_wronchen_err_intstat : WO; bitpos: [19]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_clear_slvif_wronchen_err_intstat:1;
-        /** ch1_clear_slvif_shadowreg_wron_valid_err_intstat : WO; bitpos: [20]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_clear_slvif_shadowreg_wron_valid_err_intstat:1;
-        /** ch1_clear_slvif_wronhold_err_intstat : WO; bitpos: [21]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_clear_slvif_wronhold_err_intstat:1;
-        uint32_t reserved_22:3;
-        /** ch1_clear_slvif_wrparity_err_intstat : WO; bitpos: [25]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_clear_slvif_wrparity_err_intstat:1;
-        uint32_t reserved_26:1;
-        /** ch1_clear_ch_lock_cleared_intstat : WO; bitpos: [27]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_clear_ch_lock_cleared_intstat:1;
-        /** ch1_clear_ch_src_suspended_intstat : WO; bitpos: [28]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_clear_ch_src_suspended_intstat:1;
-        /** ch1_clear_ch_suspended_intstat : WO; bitpos: [29]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_clear_ch_suspended_intstat:1;
-        /** ch1_clear_ch_disabled_intstat : WO; bitpos: [30]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_clear_ch_disabled_intstat:1;
-        /** ch1_clear_ch_aborted_intstat : WO; bitpos: [31]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_clear_ch_aborted_intstat:1;
-    };
-    uint32_t val;
-} dmac_ch1_intclear0_reg_t;
-
-/** Type of ch1_intclear1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch1_clear_ecc_prot_chmem_correrr_intstat : WO; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_clear_ecc_prot_chmem_correrr_intstat:1;
-        /** ch1_clear_ecc_prot_chmem_uncorrerr_intstat : WO; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_clear_ecc_prot_chmem_uncorrerr_intstat:1;
-        /** ch1_clear_ecc_prot_uidmem_correrr_intstat : WO; bitpos: [2]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_clear_ecc_prot_uidmem_correrr_intstat:1;
-        /** ch1_clear_ecc_prot_uidmem_uncorrerr_intstat : WO; bitpos: [3]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_clear_ecc_prot_uidmem_uncorrerr_intstat:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} dmac_ch1_intclear1_reg_t;
-
-/** Type of ch2_intstatus_enable0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch2_enable_block_tfr_done_intstat : R/W; bitpos: [0]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_block_tfr_done_intstat:1;
-        /** ch2_enable_dma_tfr_done_intstat : R/W; bitpos: [1]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_dma_tfr_done_intstat:1;
-        uint32_t reserved_2:1;
-        /** ch2_enable_src_transcomp_intstat : R/W; bitpos: [3]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_src_transcomp_intstat:1;
-        /** ch2_enable_dst_transcomp_intstat : R/W; bitpos: [4]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_dst_transcomp_intstat:1;
-        /** ch2_enable_src_dec_err_intstat : R/W; bitpos: [5]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_src_dec_err_intstat:1;
-        /** ch2_enable_dst_dec_err_intstat : R/W; bitpos: [6]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_dst_dec_err_intstat:1;
-        /** ch2_enable_src_slv_err_intstat : R/W; bitpos: [7]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_src_slv_err_intstat:1;
-        /** ch2_enable_dst_slv_err_intstat : R/W; bitpos: [8]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_dst_slv_err_intstat:1;
-        /** ch2_enable_lli_rd_dec_err_intstat : R/W; bitpos: [9]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_lli_rd_dec_err_intstat:1;
-        /** ch2_enable_lli_wr_dec_err_intstat : R/W; bitpos: [10]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_lli_wr_dec_err_intstat:1;
-        /** ch2_enable_lli_rd_slv_err_intstat : R/W; bitpos: [11]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_lli_rd_slv_err_intstat:1;
-        /** ch2_enable_lli_wr_slv_err_intstat : R/W; bitpos: [12]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_lli_wr_slv_err_intstat:1;
-        /** ch2_enable_shadowreg_or_lli_invalid_err_intstat : R/W; bitpos: [13]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_shadowreg_or_lli_invalid_err_intstat:1;
-        /** ch2_enable_slvif_multiblktype_err_intstat : R/W; bitpos: [14]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_slvif_multiblktype_err_intstat:1;
-        uint32_t reserved_15:1;
-        /** ch2_enable_slvif_dec_err_intstat : R/W; bitpos: [16]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_slvif_dec_err_intstat:1;
-        /** ch2_enable_slvif_wr2ro_err_intstat : R/W; bitpos: [17]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_slvif_wr2ro_err_intstat:1;
-        /** ch2_enable_slvif_rd2rwo_err_intstat : R/W; bitpos: [18]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_slvif_rd2rwo_err_intstat:1;
-        /** ch2_enable_slvif_wronchen_err_intstat : R/W; bitpos: [19]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_slvif_wronchen_err_intstat:1;
-        /** ch2_enable_slvif_shadowreg_wron_valid_err_intstat : R/W; bitpos: [20]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_slvif_shadowreg_wron_valid_err_intstat:1;
-        /** ch2_enable_slvif_wronhold_err_intstat : R/W; bitpos: [21]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_slvif_wronhold_err_intstat:1;
-        uint32_t reserved_22:3;
-        /** ch2_enable_slvif_wrparity_err_intstat : RO; bitpos: [25]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_slvif_wrparity_err_intstat:1;
-        uint32_t reserved_26:1;
-        /** ch2_enable_ch_lock_cleared_intstat : R/W; bitpos: [27]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_ch_lock_cleared_intstat:1;
-        /** ch2_enable_ch_src_suspended_intstat : R/W; bitpos: [28]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_ch_src_suspended_intstat:1;
-        /** ch2_enable_ch_suspended_intstat : R/W; bitpos: [29]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_ch_suspended_intstat:1;
-        /** ch2_enable_ch_disabled_intstat : R/W; bitpos: [30]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_ch_disabled_intstat:1;
-        /** ch2_enable_ch_aborted_intstat : R/W; bitpos: [31]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_ch_aborted_intstat:1;
-    };
-    uint32_t val;
-} dmac_ch2_intstatus_enable0_reg_t;
-
-/** Type of ch2_intstatus_enable1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch2_enable_ecc_prot_chmem_correrr_intstat : RO; bitpos: [0]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_ecc_prot_chmem_correrr_intstat:1;
-        /** ch2_enable_ecc_prot_chmem_uncorrerr_intstat : RO; bitpos: [1]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_ecc_prot_chmem_uncorrerr_intstat:1;
-        /** ch2_enable_ecc_prot_uidmem_correrr_intstat : RO; bitpos: [2]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_ecc_prot_uidmem_correrr_intstat:1;
-        /** ch2_enable_ecc_prot_uidmem_uncorrerr_intstat : RO; bitpos: [3]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_ecc_prot_uidmem_uncorrerr_intstat:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} dmac_ch2_intstatus_enable1_reg_t;
-
-/** Type of ch2_intstatus0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch2_block_tfr_done_intstat : RO; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_block_tfr_done_intstat:1;
-        /** ch2_dma_tfr_done_intstat : RO; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_dma_tfr_done_intstat:1;
-        uint32_t reserved_2:1;
-        /** ch2_src_transcomp_intstat : RO; bitpos: [3]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_src_transcomp_intstat:1;
-        /** ch2_dst_transcomp_intstat : RO; bitpos: [4]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_dst_transcomp_intstat:1;
-        /** ch2_src_dec_err_intstat : RO; bitpos: [5]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_src_dec_err_intstat:1;
-        /** ch2_dst_dec_err_intstat : RO; bitpos: [6]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_dst_dec_err_intstat:1;
-        /** ch2_src_slv_err_intstat : RO; bitpos: [7]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_src_slv_err_intstat:1;
-        /** ch2_dst_slv_err_intstat : RO; bitpos: [8]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_dst_slv_err_intstat:1;
-        /** ch2_lli_rd_dec_err_intstat : RO; bitpos: [9]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_lli_rd_dec_err_intstat:1;
-        /** ch2_lli_wr_dec_err_intstat : RO; bitpos: [10]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_lli_wr_dec_err_intstat:1;
-        /** ch2_lli_rd_slv_err_intstat : RO; bitpos: [11]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_lli_rd_slv_err_intstat:1;
-        /** ch2_lli_wr_slv_err_intstat : RO; bitpos: [12]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_lli_wr_slv_err_intstat:1;
-        /** ch2_shadowreg_or_lli_invalid_err_intstat : RO; bitpos: [13]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_shadowreg_or_lli_invalid_err_intstat:1;
-        /** ch2_slvif_multiblktype_err_intstat : RO; bitpos: [14]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_slvif_multiblktype_err_intstat:1;
-        uint32_t reserved_15:1;
-        /** ch2_slvif_dec_err_intstat : RO; bitpos: [16]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_slvif_dec_err_intstat:1;
-        /** ch2_slvif_wr2ro_err_intstat : RO; bitpos: [17]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_slvif_wr2ro_err_intstat:1;
-        /** ch2_slvif_rd2rwo_err_intstat : RO; bitpos: [18]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_slvif_rd2rwo_err_intstat:1;
-        /** ch2_slvif_wronchen_err_intstat : RO; bitpos: [19]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_slvif_wronchen_err_intstat:1;
-        /** ch2_slvif_shadowreg_wron_valid_err_intstat : RO; bitpos: [20]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_slvif_shadowreg_wron_valid_err_intstat:1;
-        /** ch2_slvif_wronhold_err_intstat : RO; bitpos: [21]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_slvif_wronhold_err_intstat:1;
-        uint32_t reserved_22:3;
-        /** ch2_slvif_wrparity_err_intstat : RO; bitpos: [25]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_slvif_wrparity_err_intstat:1;
-        uint32_t reserved_26:1;
-        /** ch2_ch_lock_cleared_intstat : RO; bitpos: [27]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_ch_lock_cleared_intstat:1;
-        /** ch2_ch_src_suspended_intstat : RO; bitpos: [28]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_ch_src_suspended_intstat:1;
-        /** ch2_ch_suspended_intstat : RO; bitpos: [29]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_ch_suspended_intstat:1;
-        /** ch2_ch_disabled_intstat : RO; bitpos: [30]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_ch_disabled_intstat:1;
-        /** ch2_ch_aborted_intstat : RO; bitpos: [31]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_ch_aborted_intstat:1;
-    };
-    uint32_t val;
-} dmac_ch2_intstatus0_reg_t;
-
-/** Type of ch2_intstatus1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch2_ecc_prot_chmem_correrr_intstat : RO; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_ecc_prot_chmem_correrr_intstat:1;
-        /** ch2_ecc_prot_chmem_uncorrerr_intstat : RO; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_ecc_prot_chmem_uncorrerr_intstat:1;
-        /** ch2_ecc_prot_uidmem_correrr_intstat : RO; bitpos: [2]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_ecc_prot_uidmem_correrr_intstat:1;
-        /** ch2_ecc_prot_uidmem_uncorrerr_intstat : RO; bitpos: [3]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_ecc_prot_uidmem_uncorrerr_intstat:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} dmac_ch2_intstatus1_reg_t;
-
-/** Type of ch2_intsignal_enable0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch2_enable_block_tfr_done_intsignal : R/W; bitpos: [0]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_block_tfr_done_intsignal:1;
-        /** ch2_enable_dma_tfr_done_intsignal : R/W; bitpos: [1]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_dma_tfr_done_intsignal:1;
-        uint32_t reserved_2:1;
-        /** ch2_enable_src_transcomp_intsignal : R/W; bitpos: [3]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_src_transcomp_intsignal:1;
-        /** ch2_enable_dst_transcomp_intsignal : R/W; bitpos: [4]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_dst_transcomp_intsignal:1;
-        /** ch2_enable_src_dec_err_intsignal : R/W; bitpos: [5]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_src_dec_err_intsignal:1;
-        /** ch2_enable_dst_dec_err_intsignal : R/W; bitpos: [6]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_dst_dec_err_intsignal:1;
-        /** ch2_enable_src_slv_err_intsignal : R/W; bitpos: [7]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_src_slv_err_intsignal:1;
-        /** ch2_enable_dst_slv_err_intsignal : R/W; bitpos: [8]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_dst_slv_err_intsignal:1;
-        /** ch2_enable_lli_rd_dec_err_intsignal : R/W; bitpos: [9]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_lli_rd_dec_err_intsignal:1;
-        /** ch2_enable_lli_wr_dec_err_intsignal : R/W; bitpos: [10]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_lli_wr_dec_err_intsignal:1;
-        /** ch2_enable_lli_rd_slv_err_intsignal : R/W; bitpos: [11]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_lli_rd_slv_err_intsignal:1;
-        /** ch2_enable_lli_wr_slv_err_intsignal : R/W; bitpos: [12]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_lli_wr_slv_err_intsignal:1;
-        /** ch2_enable_shadowreg_or_lli_invalid_err_intsignal : R/W; bitpos: [13]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_shadowreg_or_lli_invalid_err_intsignal:1;
-        /** ch2_enable_slvif_multiblktype_err_intsignal : R/W; bitpos: [14]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_slvif_multiblktype_err_intsignal:1;
-        uint32_t reserved_15:1;
-        /** ch2_enable_slvif_dec_err_intsignal : R/W; bitpos: [16]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_slvif_dec_err_intsignal:1;
-        /** ch2_enable_slvif_wr2ro_err_intsignal : R/W; bitpos: [17]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_slvif_wr2ro_err_intsignal:1;
-        /** ch2_enable_slvif_rd2rwo_err_intsignal : R/W; bitpos: [18]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_slvif_rd2rwo_err_intsignal:1;
-        /** ch2_enable_slvif_wronchen_err_intsignal : R/W; bitpos: [19]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_slvif_wronchen_err_intsignal:1;
-        /** ch2_enable_slvif_shadowreg_wron_valid_err_intsignal : R/W; bitpos: [20]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_slvif_shadowreg_wron_valid_err_intsignal:1;
-        /** ch2_enable_slvif_wronhold_err_intsignal : R/W; bitpos: [21]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_slvif_wronhold_err_intsignal:1;
-        uint32_t reserved_22:3;
-        /** ch2_enable_slvif_wrparity_err_intsignal : RO; bitpos: [25]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_slvif_wrparity_err_intsignal:1;
-        uint32_t reserved_26:1;
-        /** ch2_enable_ch_lock_cleared_intsignal : R/W; bitpos: [27]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_ch_lock_cleared_intsignal:1;
-        /** ch2_enable_ch_src_suspended_intsignal : R/W; bitpos: [28]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_ch_src_suspended_intsignal:1;
-        /** ch2_enable_ch_suspended_intsignal : R/W; bitpos: [29]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_ch_suspended_intsignal:1;
-        /** ch2_enable_ch_disabled_intsignal : R/W; bitpos: [30]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_ch_disabled_intsignal:1;
-        /** ch2_enable_ch_aborted_intsignal : R/W; bitpos: [31]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_ch_aborted_intsignal:1;
-    };
-    uint32_t val;
-} dmac_ch2_intsignal_enable0_reg_t;
-
-/** Type of ch2_intsignal_enable1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch2_enable_ecc_prot_chmem_correrr_intsignal : RO; bitpos: [0]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_ecc_prot_chmem_correrr_intsignal:1;
-        /** ch2_enable_ecc_prot_chmem_uncorrerr_intsignal : RO; bitpos: [1]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_ecc_prot_chmem_uncorrerr_intsignal:1;
-        /** ch2_enable_ecc_prot_uidmem_correrr_intsignal : RO; bitpos: [2]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_ecc_prot_uidmem_correrr_intsignal:1;
-        /** ch2_enable_ecc_prot_uidmem_uncorrerr_intsignal : RO; bitpos: [3]; default: 1;
-         *  NA
-         */
-        uint32_t ch2_enable_ecc_prot_uidmem_uncorrerr_intsignal:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} dmac_ch2_intsignal_enable1_reg_t;
-
-/** Type of ch2_intclear0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch2_clear_block_tfr_done_intstat : WO; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_clear_block_tfr_done_intstat:1;
-        /** ch2_clear_dma_tfr_done_intstat : WO; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_clear_dma_tfr_done_intstat:1;
-        uint32_t reserved_2:1;
-        /** ch2_clear_src_transcomp_intstat : WO; bitpos: [3]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_clear_src_transcomp_intstat:1;
-        /** ch2_clear_dst_transcomp_intstat : WO; bitpos: [4]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_clear_dst_transcomp_intstat:1;
-        /** ch2_clear_src_dec_err_intstat : WO; bitpos: [5]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_clear_src_dec_err_intstat:1;
-        /** ch2_clear_dst_dec_err_intstat : WO; bitpos: [6]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_clear_dst_dec_err_intstat:1;
-        /** ch2_clear_src_slv_err_intstat : WO; bitpos: [7]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_clear_src_slv_err_intstat:1;
-        /** ch2_clear_dst_slv_err_intstat : WO; bitpos: [8]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_clear_dst_slv_err_intstat:1;
-        /** ch2_clear_lli_rd_dec_err_intstat : WO; bitpos: [9]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_clear_lli_rd_dec_err_intstat:1;
-        /** ch2_clear_lli_wr_dec_err_intstat : WO; bitpos: [10]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_clear_lli_wr_dec_err_intstat:1;
-        /** ch2_clear_lli_rd_slv_err_intstat : WO; bitpos: [11]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_clear_lli_rd_slv_err_intstat:1;
-        /** ch2_clear_lli_wr_slv_err_intstat : WO; bitpos: [12]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_clear_lli_wr_slv_err_intstat:1;
-        /** ch2_clear_shadowreg_or_lli_invalid_err_intstat : WO; bitpos: [13]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_clear_shadowreg_or_lli_invalid_err_intstat:1;
-        /** ch2_clear_slvif_multiblktype_err_intstat : WO; bitpos: [14]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_clear_slvif_multiblktype_err_intstat:1;
-        uint32_t reserved_15:1;
-        /** ch2_clear_slvif_dec_err_intstat : WO; bitpos: [16]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_clear_slvif_dec_err_intstat:1;
-        /** ch2_clear_slvif_wr2ro_err_intstat : WO; bitpos: [17]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_clear_slvif_wr2ro_err_intstat:1;
-        /** ch2_clear_slvif_rd2rwo_err_intstat : WO; bitpos: [18]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_clear_slvif_rd2rwo_err_intstat:1;
-        /** ch2_clear_slvif_wronchen_err_intstat : WO; bitpos: [19]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_clear_slvif_wronchen_err_intstat:1;
-        /** ch2_clear_slvif_shadowreg_wron_valid_err_intstat : WO; bitpos: [20]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_clear_slvif_shadowreg_wron_valid_err_intstat:1;
-        /** ch2_clear_slvif_wronhold_err_intstat : WO; bitpos: [21]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_clear_slvif_wronhold_err_intstat:1;
-        uint32_t reserved_22:3;
-        /** ch2_clear_slvif_wrparity_err_intstat : WO; bitpos: [25]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_clear_slvif_wrparity_err_intstat:1;
-        uint32_t reserved_26:1;
-        /** ch2_clear_ch_lock_cleared_intstat : WO; bitpos: [27]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_clear_ch_lock_cleared_intstat:1;
-        /** ch2_clear_ch_src_suspended_intstat : WO; bitpos: [28]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_clear_ch_src_suspended_intstat:1;
-        /** ch2_clear_ch_suspended_intstat : WO; bitpos: [29]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_clear_ch_suspended_intstat:1;
-        /** ch2_clear_ch_disabled_intstat : WO; bitpos: [30]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_clear_ch_disabled_intstat:1;
-        /** ch2_clear_ch_aborted_intstat : WO; bitpos: [31]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_clear_ch_aborted_intstat:1;
-    };
-    uint32_t val;
-} dmac_ch2_intclear0_reg_t;
-
-/** Type of ch2_intclear1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch2_clear_ecc_prot_chmem_correrr_intstat : WO; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_clear_ecc_prot_chmem_correrr_intstat:1;
-        /** ch2_clear_ecc_prot_chmem_uncorrerr_intstat : WO; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_clear_ecc_prot_chmem_uncorrerr_intstat:1;
-        /** ch2_clear_ecc_prot_uidmem_correrr_intstat : WO; bitpos: [2]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_clear_ecc_prot_uidmem_correrr_intstat:1;
-        /** ch2_clear_ecc_prot_uidmem_uncorrerr_intstat : WO; bitpos: [3]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_clear_ecc_prot_uidmem_uncorrerr_intstat:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} dmac_ch2_intclear1_reg_t;
-
-/** Type of ch3_intstatus_enable0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch3_enable_block_tfr_done_intstat : R/W; bitpos: [0]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_block_tfr_done_intstat:1;
-        /** ch3_enable_dma_tfr_done_intstat : R/W; bitpos: [1]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_dma_tfr_done_intstat:1;
-        uint32_t reserved_2:1;
-        /** ch3_enable_src_transcomp_intstat : R/W; bitpos: [3]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_src_transcomp_intstat:1;
-        /** ch3_enable_dst_transcomp_intstat : R/W; bitpos: [4]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_dst_transcomp_intstat:1;
-        /** ch3_enable_src_dec_err_intstat : R/W; bitpos: [5]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_src_dec_err_intstat:1;
-        /** ch3_enable_dst_dec_err_intstat : R/W; bitpos: [6]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_dst_dec_err_intstat:1;
-        /** ch3_enable_src_slv_err_intstat : R/W; bitpos: [7]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_src_slv_err_intstat:1;
-        /** ch3_enable_dst_slv_err_intstat : R/W; bitpos: [8]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_dst_slv_err_intstat:1;
-        /** ch3_enable_lli_rd_dec_err_intstat : R/W; bitpos: [9]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_lli_rd_dec_err_intstat:1;
-        /** ch3_enable_lli_wr_dec_err_intstat : R/W; bitpos: [10]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_lli_wr_dec_err_intstat:1;
-        /** ch3_enable_lli_rd_slv_err_intstat : R/W; bitpos: [11]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_lli_rd_slv_err_intstat:1;
-        /** ch3_enable_lli_wr_slv_err_intstat : R/W; bitpos: [12]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_lli_wr_slv_err_intstat:1;
-        /** ch3_enable_shadowreg_or_lli_invalid_err_intstat : R/W; bitpos: [13]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_shadowreg_or_lli_invalid_err_intstat:1;
-        /** ch3_enable_slvif_multiblktype_err_intstat : R/W; bitpos: [14]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_slvif_multiblktype_err_intstat:1;
-        uint32_t reserved_15:1;
-        /** ch3_enable_slvif_dec_err_intstat : R/W; bitpos: [16]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_slvif_dec_err_intstat:1;
-        /** ch3_enable_slvif_wr2ro_err_intstat : R/W; bitpos: [17]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_slvif_wr2ro_err_intstat:1;
-        /** ch3_enable_slvif_rd2rwo_err_intstat : R/W; bitpos: [18]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_slvif_rd2rwo_err_intstat:1;
-        /** ch3_enable_slvif_wronchen_err_intstat : R/W; bitpos: [19]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_slvif_wronchen_err_intstat:1;
-        /** ch3_enable_slvif_shadowreg_wron_valid_err_intstat : R/W; bitpos: [20]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_slvif_shadowreg_wron_valid_err_intstat:1;
-        /** ch3_enable_slvif_wronhold_err_intstat : R/W; bitpos: [21]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_slvif_wronhold_err_intstat:1;
-        uint32_t reserved_22:3;
-        /** ch3_enable_slvif_wrparity_err_intstat : RO; bitpos: [25]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_slvif_wrparity_err_intstat:1;
-        uint32_t reserved_26:1;
-        /** ch3_enable_ch_lock_cleared_intstat : R/W; bitpos: [27]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_ch_lock_cleared_intstat:1;
-        /** ch3_enable_ch_src_suspended_intstat : R/W; bitpos: [28]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_ch_src_suspended_intstat:1;
-        /** ch3_enable_ch_suspended_intstat : R/W; bitpos: [29]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_ch_suspended_intstat:1;
-        /** ch3_enable_ch_disabled_intstat : R/W; bitpos: [30]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_ch_disabled_intstat:1;
-        /** ch3_enable_ch_aborted_intstat : R/W; bitpos: [31]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_ch_aborted_intstat:1;
-    };
-    uint32_t val;
-} dmac_ch3_intstatus_enable0_reg_t;
-
-/** Type of ch3_intstatus_enable1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch3_enable_ecc_prot_chmem_correrr_intstat : RO; bitpos: [0]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_ecc_prot_chmem_correrr_intstat:1;
-        /** ch3_enable_ecc_prot_chmem_uncorrerr_intstat : RO; bitpos: [1]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_ecc_prot_chmem_uncorrerr_intstat:1;
-        /** ch3_enable_ecc_prot_uidmem_correrr_intstat : RO; bitpos: [2]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_ecc_prot_uidmem_correrr_intstat:1;
-        /** ch3_enable_ecc_prot_uidmem_uncorrerr_intstat : RO; bitpos: [3]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_ecc_prot_uidmem_uncorrerr_intstat:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} dmac_ch3_intstatus_enable1_reg_t;
-
-/** Type of ch3_intstatus0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch3_block_tfr_done_intstat : RO; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_block_tfr_done_intstat:1;
-        /** ch3_dma_tfr_done_intstat : RO; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_dma_tfr_done_intstat:1;
-        uint32_t reserved_2:1;
-        /** ch3_src_transcomp_intstat : RO; bitpos: [3]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_src_transcomp_intstat:1;
-        /** ch3_dst_transcomp_intstat : RO; bitpos: [4]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_dst_transcomp_intstat:1;
-        /** ch3_src_dec_err_intstat : RO; bitpos: [5]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_src_dec_err_intstat:1;
-        /** ch3_dst_dec_err_intstat : RO; bitpos: [6]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_dst_dec_err_intstat:1;
-        /** ch3_src_slv_err_intstat : RO; bitpos: [7]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_src_slv_err_intstat:1;
-        /** ch3_dst_slv_err_intstat : RO; bitpos: [8]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_dst_slv_err_intstat:1;
-        /** ch3_lli_rd_dec_err_intstat : RO; bitpos: [9]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_lli_rd_dec_err_intstat:1;
-        /** ch3_lli_wr_dec_err_intstat : RO; bitpos: [10]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_lli_wr_dec_err_intstat:1;
-        /** ch3_lli_rd_slv_err_intstat : RO; bitpos: [11]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_lli_rd_slv_err_intstat:1;
-        /** ch3_lli_wr_slv_err_intstat : RO; bitpos: [12]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_lli_wr_slv_err_intstat:1;
-        /** ch3_shadowreg_or_lli_invalid_err_intstat : RO; bitpos: [13]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_shadowreg_or_lli_invalid_err_intstat:1;
-        /** ch3_slvif_multiblktype_err_intstat : RO; bitpos: [14]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_slvif_multiblktype_err_intstat:1;
-        uint32_t reserved_15:1;
-        /** ch3_slvif_dec_err_intstat : RO; bitpos: [16]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_slvif_dec_err_intstat:1;
-        /** ch3_slvif_wr2ro_err_intstat : RO; bitpos: [17]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_slvif_wr2ro_err_intstat:1;
-        /** ch3_slvif_rd2rwo_err_intstat : RO; bitpos: [18]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_slvif_rd2rwo_err_intstat:1;
-        /** ch3_slvif_wronchen_err_intstat : RO; bitpos: [19]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_slvif_wronchen_err_intstat:1;
-        /** ch3_slvif_shadowreg_wron_valid_err_intstat : RO; bitpos: [20]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_slvif_shadowreg_wron_valid_err_intstat:1;
-        /** ch3_slvif_wronhold_err_intstat : RO; bitpos: [21]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_slvif_wronhold_err_intstat:1;
-        uint32_t reserved_22:3;
-        /** ch3_slvif_wrparity_err_intstat : RO; bitpos: [25]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_slvif_wrparity_err_intstat:1;
-        uint32_t reserved_26:1;
-        /** ch3_ch_lock_cleared_intstat : RO; bitpos: [27]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_ch_lock_cleared_intstat:1;
-        /** ch3_ch_src_suspended_intstat : RO; bitpos: [28]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_ch_src_suspended_intstat:1;
-        /** ch3_ch_suspended_intstat : RO; bitpos: [29]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_ch_suspended_intstat:1;
-        /** ch3_ch_disabled_intstat : RO; bitpos: [30]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_ch_disabled_intstat:1;
-        /** ch3_ch_aborted_intstat : RO; bitpos: [31]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_ch_aborted_intstat:1;
-    };
-    uint32_t val;
-} dmac_ch3_intstatus0_reg_t;
-
-/** Type of ch3_intstatus1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch3_ecc_prot_chmem_correrr_intstat : RO; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_ecc_prot_chmem_correrr_intstat:1;
-        /** ch3_ecc_prot_chmem_uncorrerr_intstat : RO; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_ecc_prot_chmem_uncorrerr_intstat:1;
-        /** ch3_ecc_prot_uidmem_correrr_intstat : RO; bitpos: [2]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_ecc_prot_uidmem_correrr_intstat:1;
-        /** ch3_ecc_prot_uidmem_uncorrerr_intstat : RO; bitpos: [3]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_ecc_prot_uidmem_uncorrerr_intstat:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} dmac_ch3_intstatus1_reg_t;
-
-/** Type of ch3_intsignal_enable0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch3_enable_block_tfr_done_intsignal : R/W; bitpos: [0]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_block_tfr_done_intsignal:1;
-        /** ch3_enable_dma_tfr_done_intsignal : R/W; bitpos: [1]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_dma_tfr_done_intsignal:1;
-        uint32_t reserved_2:1;
-        /** ch3_enable_src_transcomp_intsignal : R/W; bitpos: [3]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_src_transcomp_intsignal:1;
-        /** ch3_enable_dst_transcomp_intsignal : R/W; bitpos: [4]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_dst_transcomp_intsignal:1;
-        /** ch3_enable_src_dec_err_intsignal : R/W; bitpos: [5]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_src_dec_err_intsignal:1;
-        /** ch3_enable_dst_dec_err_intsignal : R/W; bitpos: [6]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_dst_dec_err_intsignal:1;
-        /** ch3_enable_src_slv_err_intsignal : R/W; bitpos: [7]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_src_slv_err_intsignal:1;
-        /** ch3_enable_dst_slv_err_intsignal : R/W; bitpos: [8]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_dst_slv_err_intsignal:1;
-        /** ch3_enable_lli_rd_dec_err_intsignal : R/W; bitpos: [9]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_lli_rd_dec_err_intsignal:1;
-        /** ch3_enable_lli_wr_dec_err_intsignal : R/W; bitpos: [10]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_lli_wr_dec_err_intsignal:1;
-        /** ch3_enable_lli_rd_slv_err_intsignal : R/W; bitpos: [11]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_lli_rd_slv_err_intsignal:1;
-        /** ch3_enable_lli_wr_slv_err_intsignal : R/W; bitpos: [12]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_lli_wr_slv_err_intsignal:1;
-        /** ch3_enable_shadowreg_or_lli_invalid_err_intsignal : R/W; bitpos: [13]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_shadowreg_or_lli_invalid_err_intsignal:1;
-        /** ch3_enable_slvif_multiblktype_err_intsignal : R/W; bitpos: [14]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_slvif_multiblktype_err_intsignal:1;
-        uint32_t reserved_15:1;
-        /** ch3_enable_slvif_dec_err_intsignal : R/W; bitpos: [16]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_slvif_dec_err_intsignal:1;
-        /** ch3_enable_slvif_wr2ro_err_intsignal : R/W; bitpos: [17]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_slvif_wr2ro_err_intsignal:1;
-        /** ch3_enable_slvif_rd2rwo_err_intsignal : R/W; bitpos: [18]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_slvif_rd2rwo_err_intsignal:1;
-        /** ch3_enable_slvif_wronchen_err_intsignal : R/W; bitpos: [19]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_slvif_wronchen_err_intsignal:1;
-        /** ch3_enable_slvif_shadowreg_wron_valid_err_intsignal : R/W; bitpos: [20]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_slvif_shadowreg_wron_valid_err_intsignal:1;
-        /** ch3_enable_slvif_wronhold_err_intsignal : R/W; bitpos: [21]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_slvif_wronhold_err_intsignal:1;
-        uint32_t reserved_22:3;
-        /** ch3_enable_slvif_wrparity_err_intsignal : RO; bitpos: [25]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_slvif_wrparity_err_intsignal:1;
-        uint32_t reserved_26:1;
-        /** ch3_enable_ch_lock_cleared_intsignal : R/W; bitpos: [27]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_ch_lock_cleared_intsignal:1;
-        /** ch3_enable_ch_src_suspended_intsignal : R/W; bitpos: [28]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_ch_src_suspended_intsignal:1;
-        /** ch3_enable_ch_suspended_intsignal : R/W; bitpos: [29]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_ch_suspended_intsignal:1;
-        /** ch3_enable_ch_disabled_intsignal : R/W; bitpos: [30]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_ch_disabled_intsignal:1;
-        /** ch3_enable_ch_aborted_intsignal : R/W; bitpos: [31]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_ch_aborted_intsignal:1;
-    };
-    uint32_t val;
-} dmac_ch3_intsignal_enable0_reg_t;
-
-/** Type of ch3_intsignal_enable1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch3_enable_ecc_prot_chmem_correrr_intsignal : RO; bitpos: [0]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_ecc_prot_chmem_correrr_intsignal:1;
-        /** ch3_enable_ecc_prot_chmem_uncorrerr_intsignal : RO; bitpos: [1]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_ecc_prot_chmem_uncorrerr_intsignal:1;
-        /** ch3_enable_ecc_prot_uidmem_correrr_intsignal : RO; bitpos: [2]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_ecc_prot_uidmem_correrr_intsignal:1;
-        /** ch3_enable_ecc_prot_uidmem_uncorrerr_intsignal : RO; bitpos: [3]; default: 1;
-         *  NA
-         */
-        uint32_t ch3_enable_ecc_prot_uidmem_uncorrerr_intsignal:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} dmac_ch3_intsignal_enable1_reg_t;
-
-/** Type of ch3_intclear0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch3_clear_block_tfr_done_intstat : WO; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_clear_block_tfr_done_intstat:1;
-        /** ch3_clear_dma_tfr_done_intstat : WO; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_clear_dma_tfr_done_intstat:1;
-        uint32_t reserved_2:1;
-        /** ch3_clear_src_transcomp_intstat : WO; bitpos: [3]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_clear_src_transcomp_intstat:1;
-        /** ch3_clear_dst_transcomp_intstat : WO; bitpos: [4]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_clear_dst_transcomp_intstat:1;
-        /** ch3_clear_src_dec_err_intstat : WO; bitpos: [5]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_clear_src_dec_err_intstat:1;
-        /** ch3_clear_dst_dec_err_intstat : WO; bitpos: [6]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_clear_dst_dec_err_intstat:1;
-        /** ch3_clear_src_slv_err_intstat : WO; bitpos: [7]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_clear_src_slv_err_intstat:1;
-        /** ch3_clear_dst_slv_err_intstat : WO; bitpos: [8]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_clear_dst_slv_err_intstat:1;
-        /** ch3_clear_lli_rd_dec_err_intstat : WO; bitpos: [9]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_clear_lli_rd_dec_err_intstat:1;
-        /** ch3_clear_lli_wr_dec_err_intstat : WO; bitpos: [10]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_clear_lli_wr_dec_err_intstat:1;
-        /** ch3_clear_lli_rd_slv_err_intstat : WO; bitpos: [11]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_clear_lli_rd_slv_err_intstat:1;
-        /** ch3_clear_lli_wr_slv_err_intstat : WO; bitpos: [12]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_clear_lli_wr_slv_err_intstat:1;
-        /** ch3_clear_shadowreg_or_lli_invalid_err_intstat : WO; bitpos: [13]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_clear_shadowreg_or_lli_invalid_err_intstat:1;
-        /** ch3_clear_slvif_multiblktype_err_intstat : WO; bitpos: [14]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_clear_slvif_multiblktype_err_intstat:1;
-        uint32_t reserved_15:1;
-        /** ch3_clear_slvif_dec_err_intstat : WO; bitpos: [16]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_clear_slvif_dec_err_intstat:1;
-        /** ch3_clear_slvif_wr2ro_err_intstat : WO; bitpos: [17]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_clear_slvif_wr2ro_err_intstat:1;
-        /** ch3_clear_slvif_rd2rwo_err_intstat : WO; bitpos: [18]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_clear_slvif_rd2rwo_err_intstat:1;
-        /** ch3_clear_slvif_wronchen_err_intstat : WO; bitpos: [19]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_clear_slvif_wronchen_err_intstat:1;
-        /** ch3_clear_slvif_shadowreg_wron_valid_err_intstat : WO; bitpos: [20]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_clear_slvif_shadowreg_wron_valid_err_intstat:1;
-        /** ch3_clear_slvif_wronhold_err_intstat : WO; bitpos: [21]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_clear_slvif_wronhold_err_intstat:1;
-        uint32_t reserved_22:3;
-        /** ch3_clear_slvif_wrparity_err_intstat : WO; bitpos: [25]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_clear_slvif_wrparity_err_intstat:1;
-        uint32_t reserved_26:1;
-        /** ch3_clear_ch_lock_cleared_intstat : WO; bitpos: [27]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_clear_ch_lock_cleared_intstat:1;
-        /** ch3_clear_ch_src_suspended_intstat : WO; bitpos: [28]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_clear_ch_src_suspended_intstat:1;
-        /** ch3_clear_ch_suspended_intstat : WO; bitpos: [29]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_clear_ch_suspended_intstat:1;
-        /** ch3_clear_ch_disabled_intstat : WO; bitpos: [30]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_clear_ch_disabled_intstat:1;
-        /** ch3_clear_ch_aborted_intstat : WO; bitpos: [31]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_clear_ch_aborted_intstat:1;
-    };
-    uint32_t val;
-} dmac_ch3_intclear0_reg_t;
-
-/** Type of ch3_intclear1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch3_clear_ecc_prot_chmem_correrr_intstat : WO; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_clear_ecc_prot_chmem_correrr_intstat:1;
-        /** ch3_clear_ecc_prot_chmem_uncorrerr_intstat : WO; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_clear_ecc_prot_chmem_uncorrerr_intstat:1;
-        /** ch3_clear_ecc_prot_uidmem_correrr_intstat : WO; bitpos: [2]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_clear_ecc_prot_uidmem_correrr_intstat:1;
-        /** ch3_clear_ecc_prot_uidmem_uncorrerr_intstat : WO; bitpos: [3]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_clear_ecc_prot_uidmem_uncorrerr_intstat:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} dmac_ch3_intclear1_reg_t;
-
-/** Type of ch4_intstatus_enable0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch4_enable_block_tfr_done_intstat : R/W; bitpos: [0]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_block_tfr_done_intstat:1;
-        /** ch4_enable_dma_tfr_done_intstat : R/W; bitpos: [1]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_dma_tfr_done_intstat:1;
-        uint32_t reserved_2:1;
-        /** ch4_enable_src_transcomp_intstat : R/W; bitpos: [3]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_src_transcomp_intstat:1;
-        /** ch4_enable_dst_transcomp_intstat : R/W; bitpos: [4]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_dst_transcomp_intstat:1;
-        /** ch4_enable_src_dec_err_intstat : R/W; bitpos: [5]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_src_dec_err_intstat:1;
-        /** ch4_enable_dst_dec_err_intstat : R/W; bitpos: [6]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_dst_dec_err_intstat:1;
-        /** ch4_enable_src_slv_err_intstat : R/W; bitpos: [7]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_src_slv_err_intstat:1;
-        /** ch4_enable_dst_slv_err_intstat : R/W; bitpos: [8]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_dst_slv_err_intstat:1;
-        /** ch4_enable_lli_rd_dec_err_intstat : R/W; bitpos: [9]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_lli_rd_dec_err_intstat:1;
-        /** ch4_enable_lli_wr_dec_err_intstat : R/W; bitpos: [10]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_lli_wr_dec_err_intstat:1;
-        /** ch4_enable_lli_rd_slv_err_intstat : R/W; bitpos: [11]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_lli_rd_slv_err_intstat:1;
-        /** ch4_enable_lli_wr_slv_err_intstat : R/W; bitpos: [12]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_lli_wr_slv_err_intstat:1;
-        /** ch4_enable_shadowreg_or_lli_invalid_err_intstat : R/W; bitpos: [13]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_shadowreg_or_lli_invalid_err_intstat:1;
-        /** ch4_enable_slvif_multiblktype_err_intstat : R/W; bitpos: [14]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_slvif_multiblktype_err_intstat:1;
-        uint32_t reserved_15:1;
-        /** ch4_enable_slvif_dec_err_intstat : R/W; bitpos: [16]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_slvif_dec_err_intstat:1;
-        /** ch4_enable_slvif_wr2ro_err_intstat : R/W; bitpos: [17]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_slvif_wr2ro_err_intstat:1;
-        /** ch4_enable_slvif_rd2rwo_err_intstat : R/W; bitpos: [18]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_slvif_rd2rwo_err_intstat:1;
-        /** ch4_enable_slvif_wronchen_err_intstat : R/W; bitpos: [19]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_slvif_wronchen_err_intstat:1;
-        /** ch4_enable_slvif_shadowreg_wron_valid_err_intstat : R/W; bitpos: [20]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_slvif_shadowreg_wron_valid_err_intstat:1;
-        /** ch4_enable_slvif_wronhold_err_intstat : R/W; bitpos: [21]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_slvif_wronhold_err_intstat:1;
-        uint32_t reserved_22:3;
-        /** ch4_enable_slvif_wrparity_err_intstat : RO; bitpos: [25]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_slvif_wrparity_err_intstat:1;
-        uint32_t reserved_26:1;
-        /** ch4_enable_ch_lock_cleared_intstat : R/W; bitpos: [27]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_ch_lock_cleared_intstat:1;
-        /** ch4_enable_ch_src_suspended_intstat : R/W; bitpos: [28]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_ch_src_suspended_intstat:1;
-        /** ch4_enable_ch_suspended_intstat : R/W; bitpos: [29]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_ch_suspended_intstat:1;
-        /** ch4_enable_ch_disabled_intstat : R/W; bitpos: [30]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_ch_disabled_intstat:1;
-        /** ch4_enable_ch_aborted_intstat : R/W; bitpos: [31]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_ch_aborted_intstat:1;
-    };
-    uint32_t val;
-} dmac_ch4_intstatus_enable0_reg_t;
-
-/** Type of ch4_intstatus_enable1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch4_enable_ecc_prot_chmem_correrr_intstat : RO; bitpos: [0]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_ecc_prot_chmem_correrr_intstat:1;
-        /** ch4_enable_ecc_prot_chmem_uncorrerr_intstat : RO; bitpos: [1]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_ecc_prot_chmem_uncorrerr_intstat:1;
-        /** ch4_enable_ecc_prot_uidmem_correrr_intstat : RO; bitpos: [2]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_ecc_prot_uidmem_correrr_intstat:1;
-        /** ch4_enable_ecc_prot_uidmem_uncorrerr_intstat : RO; bitpos: [3]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_ecc_prot_uidmem_uncorrerr_intstat:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} dmac_ch4_intstatus_enable1_reg_t;
-
-/** Type of ch4_intstatus0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch4_block_tfr_done_intstat : RO; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_block_tfr_done_intstat:1;
-        /** ch4_dma_tfr_done_intstat : RO; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_dma_tfr_done_intstat:1;
-        uint32_t reserved_2:1;
-        /** ch4_src_transcomp_intstat : RO; bitpos: [3]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_src_transcomp_intstat:1;
-        /** ch4_dst_transcomp_intstat : RO; bitpos: [4]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_dst_transcomp_intstat:1;
-        /** ch4_src_dec_err_intstat : RO; bitpos: [5]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_src_dec_err_intstat:1;
-        /** ch4_dst_dec_err_intstat : RO; bitpos: [6]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_dst_dec_err_intstat:1;
-        /** ch4_src_slv_err_intstat : RO; bitpos: [7]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_src_slv_err_intstat:1;
-        /** ch4_dst_slv_err_intstat : RO; bitpos: [8]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_dst_slv_err_intstat:1;
-        /** ch4_lli_rd_dec_err_intstat : RO; bitpos: [9]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_lli_rd_dec_err_intstat:1;
-        /** ch4_lli_wr_dec_err_intstat : RO; bitpos: [10]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_lli_wr_dec_err_intstat:1;
-        /** ch4_lli_rd_slv_err_intstat : RO; bitpos: [11]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_lli_rd_slv_err_intstat:1;
-        /** ch4_lli_wr_slv_err_intstat : RO; bitpos: [12]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_lli_wr_slv_err_intstat:1;
-        /** ch4_shadowreg_or_lli_invalid_err_intstat : RO; bitpos: [13]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_shadowreg_or_lli_invalid_err_intstat:1;
-        /** ch4_slvif_multiblktype_err_intstat : RO; bitpos: [14]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_slvif_multiblktype_err_intstat:1;
-        uint32_t reserved_15:1;
-        /** ch4_slvif_dec_err_intstat : RO; bitpos: [16]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_slvif_dec_err_intstat:1;
-        /** ch4_slvif_wr2ro_err_intstat : RO; bitpos: [17]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_slvif_wr2ro_err_intstat:1;
-        /** ch4_slvif_rd2rwo_err_intstat : RO; bitpos: [18]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_slvif_rd2rwo_err_intstat:1;
-        /** ch4_slvif_wronchen_err_intstat : RO; bitpos: [19]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_slvif_wronchen_err_intstat:1;
-        /** ch4_slvif_shadowreg_wron_valid_err_intstat : RO; bitpos: [20]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_slvif_shadowreg_wron_valid_err_intstat:1;
-        /** ch4_slvif_wronhold_err_intstat : RO; bitpos: [21]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_slvif_wronhold_err_intstat:1;
-        uint32_t reserved_22:3;
-        /** ch4_slvif_wrparity_err_intstat : RO; bitpos: [25]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_slvif_wrparity_err_intstat:1;
-        uint32_t reserved_26:1;
-        /** ch4_ch_lock_cleared_intstat : RO; bitpos: [27]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_ch_lock_cleared_intstat:1;
-        /** ch4_ch_src_suspended_intstat : RO; bitpos: [28]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_ch_src_suspended_intstat:1;
-        /** ch4_ch_suspended_intstat : RO; bitpos: [29]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_ch_suspended_intstat:1;
-        /** ch4_ch_disabled_intstat : RO; bitpos: [30]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_ch_disabled_intstat:1;
-        /** ch4_ch_aborted_intstat : RO; bitpos: [31]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_ch_aborted_intstat:1;
-    };
-    uint32_t val;
-} dmac_ch4_intstatus0_reg_t;
-
-/** Type of ch4_intstatus1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch4_ecc_prot_chmem_correrr_intstat : RO; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_ecc_prot_chmem_correrr_intstat:1;
-        /** ch4_ecc_prot_chmem_uncorrerr_intstat : RO; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_ecc_prot_chmem_uncorrerr_intstat:1;
-        /** ch4_ecc_prot_uidmem_correrr_intstat : RO; bitpos: [2]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_ecc_prot_uidmem_correrr_intstat:1;
-        /** ch4_ecc_prot_uidmem_uncorrerr_intstat : RO; bitpos: [3]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_ecc_prot_uidmem_uncorrerr_intstat:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} dmac_ch4_intstatus1_reg_t;
-
-/** Type of ch4_intsignal_enable0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch4_enable_block_tfr_done_intsignal : R/W; bitpos: [0]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_block_tfr_done_intsignal:1;
-        /** ch4_enable_dma_tfr_done_intsignal : R/W; bitpos: [1]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_dma_tfr_done_intsignal:1;
-        uint32_t reserved_2:1;
-        /** ch4_enable_src_transcomp_intsignal : R/W; bitpos: [3]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_src_transcomp_intsignal:1;
-        /** ch4_enable_dst_transcomp_intsignal : R/W; bitpos: [4]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_dst_transcomp_intsignal:1;
-        /** ch4_enable_src_dec_err_intsignal : R/W; bitpos: [5]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_src_dec_err_intsignal:1;
-        /** ch4_enable_dst_dec_err_intsignal : R/W; bitpos: [6]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_dst_dec_err_intsignal:1;
-        /** ch4_enable_src_slv_err_intsignal : R/W; bitpos: [7]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_src_slv_err_intsignal:1;
-        /** ch4_enable_dst_slv_err_intsignal : R/W; bitpos: [8]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_dst_slv_err_intsignal:1;
-        /** ch4_enable_lli_rd_dec_err_intsignal : R/W; bitpos: [9]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_lli_rd_dec_err_intsignal:1;
-        /** ch4_enable_lli_wr_dec_err_intsignal : R/W; bitpos: [10]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_lli_wr_dec_err_intsignal:1;
-        /** ch4_enable_lli_rd_slv_err_intsignal : R/W; bitpos: [11]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_lli_rd_slv_err_intsignal:1;
-        /** ch4_enable_lli_wr_slv_err_intsignal : R/W; bitpos: [12]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_lli_wr_slv_err_intsignal:1;
-        /** ch4_enable_shadowreg_or_lli_invalid_err_intsignal : R/W; bitpos: [13]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_shadowreg_or_lli_invalid_err_intsignal:1;
-        /** ch4_enable_slvif_multiblktype_err_intsignal : R/W; bitpos: [14]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_slvif_multiblktype_err_intsignal:1;
-        uint32_t reserved_15:1;
-        /** ch4_enable_slvif_dec_err_intsignal : R/W; bitpos: [16]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_slvif_dec_err_intsignal:1;
-        /** ch4_enable_slvif_wr2ro_err_intsignal : R/W; bitpos: [17]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_slvif_wr2ro_err_intsignal:1;
-        /** ch4_enable_slvif_rd2rwo_err_intsignal : R/W; bitpos: [18]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_slvif_rd2rwo_err_intsignal:1;
-        /** ch4_enable_slvif_wronchen_err_intsignal : R/W; bitpos: [19]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_slvif_wronchen_err_intsignal:1;
-        /** ch4_enable_slvif_shadowreg_wron_valid_err_intsignal : R/W; bitpos: [20]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_slvif_shadowreg_wron_valid_err_intsignal:1;
-        /** ch4_enable_slvif_wronhold_err_intsignal : R/W; bitpos: [21]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_slvif_wronhold_err_intsignal:1;
-        uint32_t reserved_22:3;
-        /** ch4_enable_slvif_wrparity_err_intsignal : RO; bitpos: [25]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_slvif_wrparity_err_intsignal:1;
-        uint32_t reserved_26:1;
-        /** ch4_enable_ch_lock_cleared_intsignal : R/W; bitpos: [27]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_ch_lock_cleared_intsignal:1;
-        /** ch4_enable_ch_src_suspended_intsignal : R/W; bitpos: [28]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_ch_src_suspended_intsignal:1;
-        /** ch4_enable_ch_suspended_intsignal : R/W; bitpos: [29]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_ch_suspended_intsignal:1;
-        /** ch4_enable_ch_disabled_intsignal : R/W; bitpos: [30]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_ch_disabled_intsignal:1;
-        /** ch4_enable_ch_aborted_intsignal : R/W; bitpos: [31]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_ch_aborted_intsignal:1;
-    };
-    uint32_t val;
-} dmac_ch4_intsignal_enable0_reg_t;
-
-/** Type of ch4_intsignal_enable1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch4_enable_ecc_prot_chmem_correrr_intsignal : RO; bitpos: [0]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_ecc_prot_chmem_correrr_intsignal:1;
-        /** ch4_enable_ecc_prot_chmem_uncorrerr_intsignal : RO; bitpos: [1]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_ecc_prot_chmem_uncorrerr_intsignal:1;
-        /** ch4_enable_ecc_prot_uidmem_correrr_intsignal : RO; bitpos: [2]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_ecc_prot_uidmem_correrr_intsignal:1;
-        /** ch4_enable_ecc_prot_uidmem_uncorrerr_intsignal : RO; bitpos: [3]; default: 1;
-         *  NA
-         */
-        uint32_t ch4_enable_ecc_prot_uidmem_uncorrerr_intsignal:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} dmac_ch4_intsignal_enable1_reg_t;
-
-/** Type of ch4_intclear0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch4_clear_block_tfr_done_intstat : WO; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_clear_block_tfr_done_intstat:1;
-        /** ch4_clear_dma_tfr_done_intstat : WO; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_clear_dma_tfr_done_intstat:1;
-        uint32_t reserved_2:1;
-        /** ch4_clear_src_transcomp_intstat : WO; bitpos: [3]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_clear_src_transcomp_intstat:1;
-        /** ch4_clear_dst_transcomp_intstat : WO; bitpos: [4]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_clear_dst_transcomp_intstat:1;
-        /** ch4_clear_src_dec_err_intstat : WO; bitpos: [5]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_clear_src_dec_err_intstat:1;
-        /** ch4_clear_dst_dec_err_intstat : WO; bitpos: [6]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_clear_dst_dec_err_intstat:1;
-        /** ch4_clear_src_slv_err_intstat : WO; bitpos: [7]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_clear_src_slv_err_intstat:1;
-        /** ch4_clear_dst_slv_err_intstat : WO; bitpos: [8]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_clear_dst_slv_err_intstat:1;
-        /** ch4_clear_lli_rd_dec_err_intstat : WO; bitpos: [9]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_clear_lli_rd_dec_err_intstat:1;
-        /** ch4_clear_lli_wr_dec_err_intstat : WO; bitpos: [10]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_clear_lli_wr_dec_err_intstat:1;
-        /** ch4_clear_lli_rd_slv_err_intstat : WO; bitpos: [11]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_clear_lli_rd_slv_err_intstat:1;
-        /** ch4_clear_lli_wr_slv_err_intstat : WO; bitpos: [12]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_clear_lli_wr_slv_err_intstat:1;
-        /** ch4_clear_shadowreg_or_lli_invalid_err_intstat : WO; bitpos: [13]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_clear_shadowreg_or_lli_invalid_err_intstat:1;
-        /** ch4_clear_slvif_multiblktype_err_intstat : WO; bitpos: [14]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_clear_slvif_multiblktype_err_intstat:1;
-        uint32_t reserved_15:1;
-        /** ch4_clear_slvif_dec_err_intstat : WO; bitpos: [16]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_clear_slvif_dec_err_intstat:1;
-        /** ch4_clear_slvif_wr2ro_err_intstat : WO; bitpos: [17]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_clear_slvif_wr2ro_err_intstat:1;
-        /** ch4_clear_slvif_rd2rwo_err_intstat : WO; bitpos: [18]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_clear_slvif_rd2rwo_err_intstat:1;
-        /** ch4_clear_slvif_wronchen_err_intstat : WO; bitpos: [19]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_clear_slvif_wronchen_err_intstat:1;
-        /** ch4_clear_slvif_shadowreg_wron_valid_err_intstat : WO; bitpos: [20]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_clear_slvif_shadowreg_wron_valid_err_intstat:1;
-        /** ch4_clear_slvif_wronhold_err_intstat : WO; bitpos: [21]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_clear_slvif_wronhold_err_intstat:1;
-        uint32_t reserved_22:3;
-        /** ch4_clear_slvif_wrparity_err_intstat : WO; bitpos: [25]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_clear_slvif_wrparity_err_intstat:1;
-        uint32_t reserved_26:1;
-        /** ch4_clear_ch_lock_cleared_intstat : WO; bitpos: [27]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_clear_ch_lock_cleared_intstat:1;
-        /** ch4_clear_ch_src_suspended_intstat : WO; bitpos: [28]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_clear_ch_src_suspended_intstat:1;
-        /** ch4_clear_ch_suspended_intstat : WO; bitpos: [29]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_clear_ch_suspended_intstat:1;
-        /** ch4_clear_ch_disabled_intstat : WO; bitpos: [30]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_clear_ch_disabled_intstat:1;
-        /** ch4_clear_ch_aborted_intstat : WO; bitpos: [31]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_clear_ch_aborted_intstat:1;
-    };
-    uint32_t val;
-} dmac_ch4_intclear0_reg_t;
-
-/** Type of ch4_intclear1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch4_clear_ecc_prot_chmem_correrr_intstat : WO; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_clear_ecc_prot_chmem_correrr_intstat:1;
-        /** ch4_clear_ecc_prot_chmem_uncorrerr_intstat : WO; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_clear_ecc_prot_chmem_uncorrerr_intstat:1;
-        /** ch4_clear_ecc_prot_uidmem_correrr_intstat : WO; bitpos: [2]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_clear_ecc_prot_uidmem_correrr_intstat:1;
-        /** ch4_clear_ecc_prot_uidmem_uncorrerr_intstat : WO; bitpos: [3]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_clear_ecc_prot_uidmem_uncorrerr_intstat:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} dmac_ch4_intclear1_reg_t;
-
-
-/** Group: Status Registers */
-/** Type of ch1_status0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch1_cmpltd_blk_tfr_size : RO; bitpos: [21:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_cmpltd_blk_tfr_size:22;
-        uint32_t reserved_22:10;
-    };
-    uint32_t val;
-} dmac_ch1_status0_reg_t;
-
-/** Type of ch1_status1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch1_data_left_in_fifo : RO; bitpos: [14:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_data_left_in_fifo:15;
-        uint32_t reserved_15:17;
-    };
-    uint32_t val;
-} dmac_ch1_status1_reg_t;
-
-/** Type of ch1_sstat0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch1_sstat : RO; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_sstat:32;
-    };
-    uint32_t val;
-} dmac_ch1_sstat0_reg_t;
-
-/** Type of ch1_dstat0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch1_dstat : RO; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_dstat:32;
-    };
-    uint32_t val;
-} dmac_ch1_dstat0_reg_t;
-
-/** Type of ch1_sstatar0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch1_sstatar0 : R/W; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_sstatar0:32;
-    };
-    uint32_t val;
-} dmac_ch1_sstatar0_reg_t;
-
-/** Type of ch1_sstatar1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch1_sstatar1 : R/W; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_sstatar1:32;
-    };
-    uint32_t val;
-} dmac_ch1_sstatar1_reg_t;
-
-/** Type of ch1_dstatar0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch1_dstatar0 : R/W; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_dstatar0:32;
-    };
-    uint32_t val;
-} dmac_ch1_dstatar0_reg_t;
-
-/** Type of ch1_dstatar1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch1_dstatar1 : R/W; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch1_dstatar1:32;
-    };
-    uint32_t val;
-} dmac_ch1_dstatar1_reg_t;
-
-/** Type of ch2_status0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch2_cmpltd_blk_tfr_size : RO; bitpos: [21:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_cmpltd_blk_tfr_size:22;
-        uint32_t reserved_22:10;
-    };
-    uint32_t val;
-} dmac_ch2_status0_reg_t;
-
-/** Type of ch2_status1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch2_data_left_in_fifo : RO; bitpos: [14:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_data_left_in_fifo:15;
-        uint32_t reserved_15:17;
-    };
-    uint32_t val;
-} dmac_ch2_status1_reg_t;
-
-/** Type of ch2_sstat0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch2_sstat : RO; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_sstat:32;
-    };
-    uint32_t val;
-} dmac_ch2_sstat0_reg_t;
-
-/** Type of ch2_dstat0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch2_dstat : RO; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_dstat:32;
-    };
-    uint32_t val;
-} dmac_ch2_dstat0_reg_t;
-
-/** Type of ch2_sstatar0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch2_sstatar0 : R/W; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_sstatar0:32;
-    };
-    uint32_t val;
-} dmac_ch2_sstatar0_reg_t;
-
-/** Type of ch2_sstatar1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch2_sstatar1 : R/W; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_sstatar1:32;
-    };
-    uint32_t val;
-} dmac_ch2_sstatar1_reg_t;
-
-/** Type of ch2_dstatar0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch2_dstatar0 : R/W; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_dstatar0:32;
-    };
-    uint32_t val;
-} dmac_ch2_dstatar0_reg_t;
-
-/** Type of ch2_dstatar1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch2_dstatar1 : R/W; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch2_dstatar1:32;
-    };
-    uint32_t val;
-} dmac_ch2_dstatar1_reg_t;
-
-/** Type of ch3_status0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch3_cmpltd_blk_tfr_size : RO; bitpos: [21:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_cmpltd_blk_tfr_size:22;
-        uint32_t reserved_22:10;
-    };
-    uint32_t val;
-} dmac_ch3_status0_reg_t;
-
-/** Type of ch3_status1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch3_data_left_in_fifo : RO; bitpos: [14:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_data_left_in_fifo:15;
-        uint32_t reserved_15:17;
-    };
-    uint32_t val;
-} dmac_ch3_status1_reg_t;
-
-/** Type of ch3_sstat0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch3_sstat : RO; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_sstat:32;
-    };
-    uint32_t val;
-} dmac_ch3_sstat0_reg_t;
-
-/** Type of ch3_dstat0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch3_dstat : RO; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_dstat:32;
-    };
-    uint32_t val;
-} dmac_ch3_dstat0_reg_t;
-
-/** Type of ch3_sstatar0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch3_sstatar0 : R/W; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_sstatar0:32;
-    };
-    uint32_t val;
-} dmac_ch3_sstatar0_reg_t;
-
-/** Type of ch3_sstatar1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch3_sstatar1 : R/W; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_sstatar1:32;
-    };
-    uint32_t val;
-} dmac_ch3_sstatar1_reg_t;
-
-/** Type of ch3_dstatar0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch3_dstatar0 : R/W; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_dstatar0:32;
-    };
-    uint32_t val;
-} dmac_ch3_dstatar0_reg_t;
-
-/** Type of ch3_dstatar1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch3_dstatar1 : R/W; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch3_dstatar1:32;
-    };
-    uint32_t val;
-} dmac_ch3_dstatar1_reg_t;
-
-/** Type of ch4_status0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch4_cmpltd_blk_tfr_size : RO; bitpos: [21:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_cmpltd_blk_tfr_size:22;
-        uint32_t reserved_22:10;
-    };
-    uint32_t val;
-} dmac_ch4_status0_reg_t;
-
-/** Type of ch4_status1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch4_data_left_in_fifo : RO; bitpos: [14:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_data_left_in_fifo:15;
-        uint32_t reserved_15:17;
-    };
-    uint32_t val;
-} dmac_ch4_status1_reg_t;
-
-/** Type of ch4_sstat0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch4_sstat : RO; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_sstat:32;
-    };
-    uint32_t val;
-} dmac_ch4_sstat0_reg_t;
-
-/** Type of ch4_dstat0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch4_dstat : RO; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_dstat:32;
-    };
-    uint32_t val;
-} dmac_ch4_dstat0_reg_t;
-
-/** Type of ch4_sstatar0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch4_sstatar0 : R/W; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_sstatar0:32;
-    };
-    uint32_t val;
-} dmac_ch4_sstatar0_reg_t;
-
-/** Type of ch4_sstatar1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch4_sstatar1 : R/W; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_sstatar1:32;
-    };
-    uint32_t val;
-} dmac_ch4_sstatar1_reg_t;
-
-/** Type of ch4_dstatar0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch4_dstatar0 : R/W; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_dstatar0:32;
-    };
-    uint32_t val;
-} dmac_ch4_dstatar0_reg_t;
-
-/** Type of ch4_dstatar1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** ch4_dstatar1 : R/W; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t ch4_dstatar1:32;
-    };
-    uint32_t val;
-} dmac_ch4_dstatar1_reg_t;
-
-
-typedef struct {
-    volatile dmac_id0_reg_t id0;
-    uint32_t reserved_004;
-    volatile dmac_compver0_reg_t compver0;
-    uint32_t reserved_00c;
-    volatile dmac_cfg0_reg_t cfg0;
-    uint32_t reserved_014;
-    volatile dmac_chen0_reg_t chen0;
-    volatile dmac_chen1_reg_t chen1;
-    uint32_t reserved_020[4];
-    volatile dmac_intstatus0_reg_t intstatus0;
-    uint32_t reserved_034;
-    volatile dmac_commonreg_intclear0_reg_t commonreg_intclear0;
-    uint32_t reserved_03c;
-    volatile dmac_commonreg_intstatus_enable0_reg_t commonreg_intstatus_enable0;
-    uint32_t reserved_044;
-    volatile dmac_commonreg_intsignal_enable0_reg_t commonreg_intsignal_enable0;
-    uint32_t reserved_04c;
-    volatile dmac_commonreg_intstatus0_reg_t commonreg_intstatus0;
-    uint32_t reserved_054;
-    volatile dmac_reset0_reg_t reset0;
-    uint32_t reserved_05c;
-    volatile dmac_lowpower_cfg0_reg_t lowpower_cfg0;
-    volatile dmac_lowpower_cfg1_reg_t lowpower_cfg1;
-    uint32_t reserved_068[38];
-    volatile dmac_ch1_sar0_reg_t ch1_sar0;
-    volatile dmac_ch1_sar1_reg_t ch1_sar1;
-    volatile dmac_ch1_dar0_reg_t ch1_dar0;
-    volatile dmac_ch1_dar1_reg_t ch1_dar1;
-    volatile dmac_ch1_block_ts0_reg_t ch1_block_ts0;
-    uint32_t reserved_114;
-    volatile dmac_ch1_ctl0_reg_t ch1_ctl0;
-    volatile dmac_ch1_ctl1_reg_t ch1_ctl1;
-    volatile dmac_ch1_cfg0_reg_t ch1_cfg0;
-    volatile dmac_ch1_cfg1_reg_t ch1_cfg1;
-    volatile dmac_ch1_llp0_reg_t ch1_llp0;
-    volatile dmac_ch1_llp1_reg_t ch1_llp1;
-    volatile dmac_ch1_status0_reg_t ch1_status0;
-    volatile dmac_ch1_status1_reg_t ch1_status1;
-    volatile dmac_ch1_swhssrc0_reg_t ch1_swhssrc0;
-    uint32_t reserved_13c;
-    volatile dmac_ch1_swhsdst0_reg_t ch1_swhsdst0;
-    uint32_t reserved_144;
-    volatile dmac_ch1_blk_tfr_resumereq0_reg_t ch1_blk_tfr_resumereq0;
-    uint32_t reserved_14c;
-    volatile dmac_ch1_axi_id0_reg_t ch1_axi_id0;
-    uint32_t reserved_154;
-    volatile dmac_ch1_axi_qos0_reg_t ch1_axi_qos0;
-    uint32_t reserved_15c;
-    volatile dmac_ch1_sstat0_reg_t ch1_sstat0;
-    uint32_t reserved_164;
-    volatile dmac_ch1_dstat0_reg_t ch1_dstat0;
-    uint32_t reserved_16c;
-    volatile dmac_ch1_sstatar0_reg_t ch1_sstatar0;
-    volatile dmac_ch1_sstatar1_reg_t ch1_sstatar1;
-    volatile dmac_ch1_dstatar0_reg_t ch1_dstatar0;
-    volatile dmac_ch1_dstatar1_reg_t ch1_dstatar1;
-    volatile dmac_ch1_intstatus_enable0_reg_t ch1_intstatus_enable0;
-    volatile dmac_ch1_intstatus_enable1_reg_t ch1_intstatus_enable1;
-    volatile dmac_ch1_intstatus0_reg_t ch1_intstatus0;
-    volatile dmac_ch1_intstatus1_reg_t ch1_intstatus1;
-    volatile dmac_ch1_intsignal_enable0_reg_t ch1_intsignal_enable0;
-    volatile dmac_ch1_intsignal_enable1_reg_t ch1_intsignal_enable1;
-    volatile dmac_ch1_intclear0_reg_t ch1_intclear0;
-    volatile dmac_ch1_intclear1_reg_t ch1_intclear1;
-    uint32_t reserved_1a0[24];
-    volatile dmac_ch2_sar0_reg_t ch2_sar0;
-    volatile dmac_ch2_sar1_reg_t ch2_sar1;
-    volatile dmac_ch2_dar0_reg_t ch2_dar0;
-    volatile dmac_ch2_dar1_reg_t ch2_dar1;
-    volatile dmac_ch2_block_ts0_reg_t ch2_block_ts0;
-    uint32_t reserved_214;
-    volatile dmac_ch2_ctl0_reg_t ch2_ctl0;
-    volatile dmac_ch2_ctl1_reg_t ch2_ctl1;
-    volatile dmac_ch2_cfg0_reg_t ch2_cfg0;
-    volatile dmac_ch2_cfg1_reg_t ch2_cfg1;
-    volatile dmac_ch2_llp0_reg_t ch2_llp0;
-    volatile dmac_ch2_llp1_reg_t ch2_llp1;
-    volatile dmac_ch2_status0_reg_t ch2_status0;
-    volatile dmac_ch2_status1_reg_t ch2_status1;
-    volatile dmac_ch2_swhssrc0_reg_t ch2_swhssrc0;
-    uint32_t reserved_23c;
-    volatile dmac_ch2_swhsdst0_reg_t ch2_swhsdst0;
-    uint32_t reserved_244;
-    volatile dmac_ch2_blk_tfr_resumereq0_reg_t ch2_blk_tfr_resumereq0;
-    uint32_t reserved_24c;
-    volatile dmac_ch2_axi_id0_reg_t ch2_axi_id0;
-    uint32_t reserved_254;
-    volatile dmac_ch2_axi_qos0_reg_t ch2_axi_qos0;
-    uint32_t reserved_25c;
-    volatile dmac_ch2_sstat0_reg_t ch2_sstat0;
-    uint32_t reserved_264;
-    volatile dmac_ch2_dstat0_reg_t ch2_dstat0;
-    uint32_t reserved_26c;
-    volatile dmac_ch2_sstatar0_reg_t ch2_sstatar0;
-    volatile dmac_ch2_sstatar1_reg_t ch2_sstatar1;
-    volatile dmac_ch2_dstatar0_reg_t ch2_dstatar0;
-    volatile dmac_ch2_dstatar1_reg_t ch2_dstatar1;
-    volatile dmac_ch2_intstatus_enable0_reg_t ch2_intstatus_enable0;
-    volatile dmac_ch2_intstatus_enable1_reg_t ch2_intstatus_enable1;
-    volatile dmac_ch2_intstatus0_reg_t ch2_intstatus0;
-    volatile dmac_ch2_intstatus1_reg_t ch2_intstatus1;
-    volatile dmac_ch2_intsignal_enable0_reg_t ch2_intsignal_enable0;
-    volatile dmac_ch2_intsignal_enable1_reg_t ch2_intsignal_enable1;
-    volatile dmac_ch2_intclear0_reg_t ch2_intclear0;
-    volatile dmac_ch2_intclear1_reg_t ch2_intclear1;
-    uint32_t reserved_2a0[24];
-    volatile dmac_ch3_sar0_reg_t ch3_sar0;
-    volatile dmac_ch3_sar1_reg_t ch3_sar1;
-    volatile dmac_ch3_dar0_reg_t ch3_dar0;
-    volatile dmac_ch3_dar1_reg_t ch3_dar1;
-    volatile dmac_ch3_block_ts0_reg_t ch3_block_ts0;
-    uint32_t reserved_314;
-    volatile dmac_ch3_ctl0_reg_t ch3_ctl0;
-    volatile dmac_ch3_ctl1_reg_t ch3_ctl1;
-    volatile dmac_ch3_cfg0_reg_t ch3_cfg0;
-    volatile dmac_ch3_cfg1_reg_t ch3_cfg1;
-    volatile dmac_ch3_llp0_reg_t ch3_llp0;
-    volatile dmac_ch3_llp1_reg_t ch3_llp1;
-    volatile dmac_ch3_status0_reg_t ch3_status0;
-    volatile dmac_ch3_status1_reg_t ch3_status1;
-    volatile dmac_ch3_swhssrc0_reg_t ch3_swhssrc0;
-    uint32_t reserved_33c;
-    volatile dmac_ch3_swhsdst0_reg_t ch3_swhsdst0;
-    uint32_t reserved_344;
-    volatile dmac_ch3_blk_tfr_resumereq0_reg_t ch3_blk_tfr_resumereq0;
-    uint32_t reserved_34c;
-    volatile dmac_ch3_axi_id0_reg_t ch3_axi_id0;
-    uint32_t reserved_354;
-    volatile dmac_ch3_axi_qos0_reg_t ch3_axi_qos0;
-    uint32_t reserved_35c;
-    volatile dmac_ch3_sstat0_reg_t ch3_sstat0;
-    uint32_t reserved_364;
-    volatile dmac_ch3_dstat0_reg_t ch3_dstat0;
-    uint32_t reserved_36c;
-    volatile dmac_ch3_sstatar0_reg_t ch3_sstatar0;
-    volatile dmac_ch3_sstatar1_reg_t ch3_sstatar1;
-    volatile dmac_ch3_dstatar0_reg_t ch3_dstatar0;
-    volatile dmac_ch3_dstatar1_reg_t ch3_dstatar1;
-    volatile dmac_ch3_intstatus_enable0_reg_t ch3_intstatus_enable0;
-    volatile dmac_ch3_intstatus_enable1_reg_t ch3_intstatus_enable1;
-    volatile dmac_ch3_intstatus0_reg_t ch3_intstatus0;
-    volatile dmac_ch3_intstatus1_reg_t ch3_intstatus1;
-    volatile dmac_ch3_intsignal_enable0_reg_t ch3_intsignal_enable0;
-    volatile dmac_ch3_intsignal_enable1_reg_t ch3_intsignal_enable1;
-    volatile dmac_ch3_intclear0_reg_t ch3_intclear0;
-    volatile dmac_ch3_intclear1_reg_t ch3_intclear1;
-    uint32_t reserved_3a0[24];
-    volatile dmac_ch4_sar0_reg_t ch4_sar0;
-    volatile dmac_ch4_sar1_reg_t ch4_sar1;
-    volatile dmac_ch4_dar0_reg_t ch4_dar0;
-    volatile dmac_ch4_dar1_reg_t ch4_dar1;
-    volatile dmac_ch4_block_ts0_reg_t ch4_block_ts0;
-    uint32_t reserved_414;
-    volatile dmac_ch4_ctl0_reg_t ch4_ctl0;
-    volatile dmac_ch4_ctl1_reg_t ch4_ctl1;
-    volatile dmac_ch4_cfg0_reg_t ch4_cfg0;
-    volatile dmac_ch4_cfg1_reg_t ch4_cfg1;
-    volatile dmac_ch4_llp0_reg_t ch4_llp0;
-    volatile dmac_ch4_llp1_reg_t ch4_llp1;
-    volatile dmac_ch4_status0_reg_t ch4_status0;
-    volatile dmac_ch4_status1_reg_t ch4_status1;
-    volatile dmac_ch4_swhssrc0_reg_t ch4_swhssrc0;
-    uint32_t reserved_43c;
-    volatile dmac_ch4_swhsdst0_reg_t ch4_swhsdst0;
-    uint32_t reserved_444;
-    volatile dmac_ch4_blk_tfr_resumereq0_reg_t ch4_blk_tfr_resumereq0;
-    uint32_t reserved_44c;
-    volatile dmac_ch4_axi_id0_reg_t ch4_axi_id0;
-    uint32_t reserved_454;
-    volatile dmac_ch4_axi_qos0_reg_t ch4_axi_qos0;
-    uint32_t reserved_45c;
-    volatile dmac_ch4_sstat0_reg_t ch4_sstat0;
-    uint32_t reserved_464;
-    volatile dmac_ch4_dstat0_reg_t ch4_dstat0;
-    uint32_t reserved_46c;
-    volatile dmac_ch4_sstatar0_reg_t ch4_sstatar0;
-    volatile dmac_ch4_sstatar1_reg_t ch4_sstatar1;
-    volatile dmac_ch4_dstatar0_reg_t ch4_dstatar0;
-    volatile dmac_ch4_dstatar1_reg_t ch4_dstatar1;
-    volatile dmac_ch4_intstatus_enable0_reg_t ch4_intstatus_enable0;
-    volatile dmac_ch4_intstatus_enable1_reg_t ch4_intstatus_enable1;
-    volatile dmac_ch4_intstatus0_reg_t ch4_intstatus0;
-    volatile dmac_ch4_intstatus1_reg_t ch4_intstatus1;
-    volatile dmac_ch4_intsignal_enable0_reg_t ch4_intsignal_enable0;
-    volatile dmac_ch4_intsignal_enable1_reg_t ch4_intsignal_enable1;
-    volatile dmac_ch4_intclear0_reg_t ch4_intclear0;
-    volatile dmac_ch4_intclear1_reg_t ch4_intclear1;
-} dmac_dev_t;
-
-
-#ifndef __cplusplus
-_Static_assert(sizeof(dmac_dev_t) == 0x4a0, "Invalid size of dmac_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif

components/soc/esp32p4/include/soc/interrupts.h

@@ -39,7 +39,7 @@ typedef enum {
     ETS_SYS_ICM_INTR_SOURCE,
     ETS_USB_DEVICE_INTR_SOURCE,
     ETS_SDIO_HOST_INTR_SOURCE,
-    ETS_GDMA_INTR_SOURCE,
+    ETS_DW_GDMA_INTR_SOURCE,
     ETS_SPI2_INTR_SOURCE,
     ETS_SPI3_INTR_SOURCE,
     ETS_I2S0_INTR_SOURCE,

components/soc/esp32p4/interrupts.c

@@ -31,7 +31,7 @@ const char *const esp_isr_names[] = {
     [ETS_SYS_ICM_INTR_SOURCE]            = "SYS_ICM",
     [ETS_USB_DEVICE_INTR_SOURCE]         = "USB_DEVICE",
     [ETS_SDIO_HOST_INTR_SOURCE]          = "SDIO_HOST",
-    [ETS_GDMA_INTR_SOURCE]               = "GDMA",
+    [ETS_DW_GDMA_INTR_SOURCE]            = "DW_GDMA",
     [ETS_SPI2_INTR_SOURCE]               = "SPI2",
     [ETS_SPI3_INTR_SOURCE]               = "SPI3",
     [ETS_I2S0_INTR_SOURCE]               = "I2S0",

components/soc/esp32p4/ld/esp32p4.peripherals.ld

@@ -90,7 +90,7 @@ PROVIDE ( MIPI_DSI_HOST      = 0x500A0000 );
 PROVIDE ( MIPI_CSI_MEM       = 0x50104000 );
 PROVIDE ( MIPI_DSI_MEM       = 0x50105000 );
 PROVIDE ( ISP                = 0x500A1000 );
-PROVIDE ( GDMA               = 0x50081000 );
+PROVIDE ( DW_GDMA            = 0x50081000 );
 PROVIDE ( I3C_MST            = 0x500DA000 );
 PROVIDE ( I3C_MST_MEM        = 0x500DA000 );
 PROVIDE ( I3C_SLV            = 0x500DB000 );