bootloader_support: mem-related initializations using cpu abstractions

components/bootloader_support/CMakeLists.txt

@@ -2,6 +2,7 @@ set(srcs
     "src/bootloader_clock.c"
     "src/bootloader_common.c"
     "src/bootloader_flash.c"
+    "src/bootloader_mem.c"
     "src/bootloader_random.c"
     "src/bootloader_utility.c"
     "src/esp_image_format.c"

components/bootloader_support/include/bootloader_mem.h

@@ -0,0 +1,24 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void bootloader_init_mem(void);
+
+#ifdef __cplusplus
+}
+#endif

components/bootloader_support/src/bootloader_mem.c

@@ -0,0 +1,48 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#include <stdbool.h>
+
+#include "xtensa/config/core.h"
+#include "hal/cpu_hal.h"
+#include "hal/mpu_hal.h"
+#include "hal/mpu_types.h"
+#include "soc/mpu_caps.h"
+#include "bootloader_mem.h"
+#include "xt_instr_macros.h"
+#include "xtensa/config/specreg.h"
+
+static inline void cpu_configure_region_protection(void)
+{
+    /* Currently, the only supported chips esp32 and esp32s2
+     * have the same configuration. Move this to the port layer once
+     * more chips with different configurations are supported.
+     * 
+     * Both chips have the address space divided into 8 regions, 512MB each.
+     */
+    const int illegal_regions[] = {0, 4, 5, 6, 7}; // 0x00000000, 0x80000000, 0xa0000000, 0xc0000000, 0xe0000000
+    for (int i = 0; i < sizeof(illegal_regions) / sizeof(illegal_regions[0]); ++i) {
+        mpu_hal_set_region_access(illegal_regions[i], MPU_REGION_ILLEGAL);
+    }
+
+    mpu_hal_set_region_access(1, MPU_REGION_RW); // 0x20000000
+}
+
+void bootloader_init_mem(void)
+{
+    cpu_hal_init_hwloop();
+
+    // protect memory region
+    cpu_configure_region_protection();
+}

components/bootloader_support/src/esp32/bootloader_esp32.c

@@ -22,6 +22,7 @@
 #include "bootloader_clock.h"
 #include "bootloader_common.h"
 #include "bootloader_flash_config.h"
+#include "bootloader_mem.h"
 
 #include "soc/cpu.h"
 #include "soc/dport_reg.h"
@@ -426,10 +427,9 @@ void abort(void)
 esp_err_t bootloader_init(void)
 {
     esp_err_t ret = ESP_OK;
-    // workaround for tensilica erratum572
-    cpu_init_memctl();
-    // protect memory region
-    cpu_configure_region_protection();
+
+    bootloader_init_mem();
+
     // check that static RAM is after the stack
 #ifndef NDEBUG
     {

components/bootloader_support/src/esp32s2/bootloader_esp32s2.c

@@ -25,6 +25,7 @@
 #include "bootloader_init.h"
 #include "bootloader_clock.h"
 #include "bootloader_flash_config.h"
+#include "bootloader_mem.h"
 
 #include "esp32s2/rom/cache.h"
 #include "esp32s2/rom/ets_sys.h"
@@ -349,7 +350,9 @@ esp_err_t bootloader_init(void)
     esp_err_t ret = ESP_OK;
     bootloader_super_wdt_auto_feed();
     // protect memory region
-    cpu_configure_region_protection();
+
+    bootloader_init_mem();
+
     /* check that static RAM is after the stack */
 #ifndef NDEBUG
     {

components/esp32/cpu_start.c

@@ -69,6 +69,7 @@
 #include "esp_ota_ops.h"
 #include "esp_efuse.h"
 #include "bootloader_flash_config.h"
+#include "bootloader_mem.h"
 
 #ifdef CONFIG_APP_BUILD_TYPE_ELF_RAM
 #include "esp32/rom/efuse.h"
@@ -126,8 +127,8 @@ void IRAM_ATTR call_start_cpu0(void)
 #else
     RESET_REASON rst_reas[2];
 #endif
-    cpu_configure_region_protection();
-    cpu_init_memctl();
+
+    bootloader_init_mem();
 
     //Move exception vectors to IRAM
     asm volatile (\
@@ -277,8 +278,8 @@ void IRAM_ATTR call_start_cpu1(void)
                   ::"r"(&_init_start));
 
     ets_set_appcpu_boot_addr(0);
-    cpu_configure_region_protection();
-    cpu_init_memctl();
+
+    bootloader_init_mem();
 
 #if CONFIG_ESP_CONSOLE_UART_NONE
     ets_install_putc1(NULL);

components/esp32s2/cpu_start.c

@@ -69,6 +69,7 @@
 #include "esp_private/pm_impl.h"
 #include "trax.h"
 #include "esp_efuse.h"
+#include "bootloader_mem.h"
 
 #define STRINGIFY(s) STRINGIFY2(s)
 #define STRINGIFY2(s) #s
@@ -110,7 +111,7 @@ void IRAM_ATTR call_start_cpu0(void)
 {
     RESET_REASON rst_reas;
 
-    cpu_configure_region_protection();
+    bootloader_init_mem();
 
     //Move exception vectors to IRAM
     asm volatile (\

components/soc/include/soc/cpu.h

@@ -38,51 +38,6 @@ static inline void *get_sp(void)
     return cpu_hal_get_sp();
 }
 
-/* Functions to set page attributes for Region Protection option in the CPU.
- * See Xtensa ISA Reference manual for explanation of arguments (section 4.6.3.2).
- */
-
-static inline void cpu_write_dtlb(uint32_t vpn, unsigned attr)
-{
-    asm volatile ("wdtlb  %1, %0; dsync\n" :: "r" (vpn), "r" (attr));
-}
-
-
-static inline void cpu_write_itlb(unsigned vpn, unsigned attr)
-{
-    asm volatile ("witlb  %1, %0; isync\n" :: "r" (vpn), "r" (attr));
-}
-
-static inline void cpu_init_memctl(void)
-{
-#if XCHAL_ERRATUM_572
-    uint32_t memctl = XCHAL_CACHE_MEMCTL_DEFAULT;
-    WSR(MEMCTL, memctl);
-#endif // XCHAL_ERRATUM_572
-}
-
-/**
- * @brief Configure memory region protection
- *
- * Make page 0 access raise an exception.
- * Also protect some other unused pages so we can catch weirdness.
- * Useful attribute values:
- * 0 — cached, RW
- * 2 — bypass cache, RWX (default value after CPU reset)
- * 15 — no access, raise exception
- */
-
-static inline void cpu_configure_region_protection(void)
-{
-    const uint32_t pages_to_protect[] = {0x00000000, 0x80000000, 0xa0000000, 0xc0000000, 0xe0000000};
-    for (int i = 0; i < sizeof(pages_to_protect)/sizeof(pages_to_protect[0]); ++i) {
-        cpu_write_dtlb(pages_to_protect[i], 0xf);
-        cpu_write_itlb(pages_to_protect[i], 0xf);
-    }
-    cpu_write_dtlb(0x20000000, 0);
-    cpu_write_itlb(0x20000000, 0);
-}
-
 /**
  * @brief Stall CPU using RTC controller
  * @param cpu_id ID of the CPU to stall (0 = PRO, 1 = APP)