esp32s2beta: dport_access simplify

Closes: IDF-755

components/esp32s2beta/cache_err_int.c

@@ -66,6 +66,5 @@ void esp_cache_err_int_init()
 
 int IRAM_ATTR esp_cache_err_get_cpuid()
 {
-    esp_dport_access_int_pause();
     return PRO_CPU_NUM;
 }

components/esp32s2beta/cpu_start.c

@@ -395,9 +395,6 @@ void start_cpu0_default(void)
 #endif
     //esp_cache_err_int_init();
     esp_crosscore_int_init();
-#ifndef CONFIG_FREERTOS_UNICORE
-    esp_dport_access_int_init();
-#endif
     spi_flash_init();
     /* init default OS-aware flash access critical section */
     spi_flash_guard_set(&g_flash_guard_default_ops);
@@ -449,7 +446,6 @@ void start_cpu1_default(void)
     //has started, but it isn't active *on this CPU* yet.
     esp_cache_err_int_init();
     esp_crosscore_int_init();
-    esp_dport_access_int_init();
 
     ESP_EARLY_LOGI(TAG, "Starting scheduler on APP CPU.");
     xPortStartScheduler();

components/esp32s2beta/dport_access.c

@@ -12,302 +12,14 @@
 // See the License for the specific language governing permissions and
 // limitations under the License.
 
-/*
- * DPORT access is used for do protection when dual core access DPORT internal register and APB register via DPORT simultaneously
- * This function will be initialize after FreeRTOS startup.
- * When cpu0 want to access DPORT register, it should notify cpu1 enter in high-priority interrupt for be mute. When cpu1 already in high-priority interrupt,
- * cpu0 can access DPORT register. Currently, cpu1 will wait for cpu0 finish access and exit high-priority interrupt.
- */
-
 #include <stdint.h>
 #include <string.h>
+#include "soc/dport_access.h"
 
-#include <sdkconfig.h>
-#include "esp_attr.h"
-#include "esp_err.h"
-#include "esp_intr_alloc.h"
-#include "esp32s2beta/rom/ets_sys.h"
-#include "esp32s2beta/rom/uart.h"
-
-#include "soc/cpu.h"
-#include "soc/dport_reg.h"
-#include "soc/spi_mem_reg.h"
-
-#include "freertos/FreeRTOS.h"
-#include "freertos/task.h"
-#include "freertos/semphr.h"
-#include "freertos/queue.h"
-#include "freertos/portmacro.h"
-
-#include "xtensa/core-macros.h"
-
-// TODO: dport_access: simplify for esp32s2beta - IDF-755
-
-#ifndef CONFIG_FREERTOS_UNICORE
-static portMUX_TYPE g_dport_mux = portMUX_INITIALIZER_UNLOCKED;
-
-#define DPORT_CORE_STATE_IDLE        0
-#define DPORT_CORE_STATE_RUNNING     1
-static uint32_t volatile dport_core_state[portNUM_PROCESSORS];      //cpu is already run
-
-/* these global variables are accessed from interrupt vector, hence not declared as static */
-uint32_t volatile dport_access_start[portNUM_PROCESSORS];      //dport register could be accessed
-uint32_t volatile dport_access_end[portNUM_PROCESSORS];        //dport register is accessed over
-
-static uint32_t volatile dport_access_ref[portNUM_PROCESSORS];        //dport access reference
-
-#ifdef DPORT_ACCESS_BENCHMARK
-#define DPORT_ACCESS_BENCHMARK_STORE_NUM
-static uint32_t ccount_start[portNUM_PROCESSORS];
-static uint32_t ccount_end[portNUM_PROCESSORS];
-static uint32_t ccount_margin[portNUM_PROCESSORS][DPORT_ACCESS_BENCHMARK_STORE_NUM];
-static uint32_t ccount_margin_cnt;
-#endif
-
-
-static BaseType_t oldInterruptLevel[2];
-#endif // CONFIG_FREERTOS_UNICORE
-
-/* stall other cpu that this cpu is pending to access dport register start */
-void IRAM_ATTR esp_dport_access_stall_other_cpu_start(void)
-{
-#ifndef CONFIG_FREERTOS_UNICORE
-    if (dport_core_state[0] == DPORT_CORE_STATE_IDLE
-        || dport_core_state[1] == DPORT_CORE_STATE_IDLE) {
-        return;
-    }
-
-    BaseType_t intLvl = portENTER_CRITICAL_NESTED();
-
-    int cpu_id = xPortGetCoreID();
-
-#ifdef DPORT_ACCESS_BENCHMARK
-    ccount_start[cpu_id] = XTHAL_GET_CCOUNT();
-#endif
-
-    if (dport_access_ref[cpu_id] == 0) {
-        portENTER_CRITICAL_ISR(&g_dport_mux);
-
-        oldInterruptLevel[cpu_id]=intLvl;
-
-        dport_access_start[cpu_id] = 0;
-        dport_access_end[cpu_id] = 0;
-
-        if (cpu_id == 0) {
-            _DPORT_REG_WRITE(DPORT_CPU_INTR_FROM_CPU_3_REG, DPORT_CPU_INTR_FROM_CPU_3); //interrupt on cpu1
-        } else {
-            _DPORT_REG_WRITE(DPORT_CPU_INTR_FROM_CPU_2_REG, DPORT_CPU_INTR_FROM_CPU_2); //interrupt on cpu0
-        }
-
-        while (!dport_access_start[cpu_id]) {};
-
-        REG_READ(SPI_DATE_REG(3));  //just read a APB register sure that the APB-bus is idle
-    }
-
-    dport_access_ref[cpu_id]++;
-
-    if (dport_access_ref[cpu_id] > 1) {
-        /* Interrupts are already disabled by the parent, we're nested here. */
-        portEXIT_CRITICAL_NESTED(intLvl);
-    }
-#endif /* CONFIG_FREERTOS_UNICORE */
-}
-
-/* stall other cpu that this cpu is pending to access dport register end */
-void IRAM_ATTR esp_dport_access_stall_other_cpu_end(void)
+// Read a sequence of DPORT registers to the buffer.
+void esp_dport_access_read_buffer(uint32_t *buff_out, uint32_t address, uint32_t num_words)
 {
-#ifndef CONFIG_FREERTOS_UNICORE
-    int cpu_id = xPortGetCoreID();
-    if (dport_core_state[0] == DPORT_CORE_STATE_IDLE
-            || dport_core_state[1] == DPORT_CORE_STATE_IDLE) {
-        return;
-    }
-
-    if (dport_access_ref[cpu_id] == 0) {
-        assert(0);
-    }
-
-    dport_access_ref[cpu_id]--;
-
-    if (dport_access_ref[cpu_id] == 0) {
-        dport_access_end[cpu_id] = 1;
-
-        portEXIT_CRITICAL_ISR(&g_dport_mux);
-
-        portEXIT_CRITICAL_NESTED(oldInterruptLevel[cpu_id]);
-    }
-
-#ifdef DPORT_ACCESS_BENCHMARK
-    ccount_end[cpu_id] = XTHAL_GET_CCOUNT();
-    ccount_margin[cpu_id][ccount_margin_cnt] = ccount_end[cpu_id] - ccount_start[cpu_id];
-    ccount_margin_cnt = (ccount_margin_cnt + 1)&(DPORT_ACCESS_BENCHMARK_STORE_NUM - 1);
-#endif
-#endif /* CONFIG_FREERTOS_UNICORE */
-}
-
-void IRAM_ATTR esp_dport_access_stall_other_cpu_start_wrap(void)
-{
-    DPORT_STALL_OTHER_CPU_START();
-}
-
-void IRAM_ATTR esp_dport_access_stall_other_cpu_end_wrap(void)
-{
-    DPORT_STALL_OTHER_CPU_END();
-}
-
-#ifndef CONFIG_FREERTOS_UNICORE
-static void dport_access_init_core(void *arg)
-{
-    int core_id = 0;
-    uint32_t intr_source = ETS_FROM_CPU_INTR2_SOURCE;
-
-
-    core_id = xPortGetCoreID();
-    if (core_id == 1) {
-        intr_source = ETS_FROM_CPU_INTR3_SOURCE;
-    }
-
-    ESP_INTR_DISABLE(ETS_DPORT_INUM);
-    intr_matrix_set(core_id, intr_source, ETS_DPORT_INUM);
-    ESP_INTR_ENABLE(ETS_DPORT_INUM);
-
-    dport_access_ref[core_id] = 0;
-    dport_access_start[core_id] = 0;
-    dport_access_end[core_id] = 0;
-    dport_core_state[core_id] = DPORT_CORE_STATE_RUNNING;
-
-    vTaskDelete(NULL);
-}
-#endif
-
-/*  Defer initialisation until after scheduler is running */
-void esp_dport_access_int_init(void)
-{
-#ifndef CONFIG_FREERTOS_UNICORE
-    portBASE_TYPE res = xTaskCreatePinnedToCore(&dport_access_init_core, "dport", configMINIMAL_STACK_SIZE, NULL, 5, NULL, xPortGetCoreID());
-    assert(res == pdTRUE);
-#endif
-}
-
-void IRAM_ATTR esp_dport_access_int_pause(void)
-{
-#ifndef CONFIG_FREERTOS_UNICORE
-    portENTER_CRITICAL_ISR(&g_dport_mux);
-    dport_core_state[0] = DPORT_CORE_STATE_IDLE;
-    dport_core_state[1] = DPORT_CORE_STATE_IDLE;
-    portEXIT_CRITICAL_ISR(&g_dport_mux);
-#endif
-}
-
-//Used in panic code: the enter_critical stuff may be messed up so we just stop everything without checking the mux.
-void IRAM_ATTR esp_dport_access_int_abort(void)
-{
-#ifndef CONFIG_FREERTOS_UNICORE
-    dport_core_state[0] = DPORT_CORE_STATE_IDLE;
-    dport_core_state[1] = DPORT_CORE_STATE_IDLE;
-#endif
-}
-
-void IRAM_ATTR esp_dport_access_int_resume(void)
-{
-#ifndef CONFIG_FREERTOS_UNICORE
-    portENTER_CRITICAL_ISR(&g_dport_mux);
-    dport_core_state[0] = DPORT_CORE_STATE_RUNNING;
-    dport_core_state[1] = DPORT_CORE_STATE_RUNNING;
-    portEXIT_CRITICAL_ISR(&g_dport_mux);
-#endif
-}
-
-/**
- * @brief Read a sequence of DPORT registers to the buffer, SMP-safe version.
- *
- * This implementation uses a method of the pre-reading of the APB register
- * before reading the register of the DPORT, without stall other CPU.
- * There is disable/enable interrupt.
- *
- * @param[out] buff_out  Contains the read data.
- * @param[in]  address   Initial address for reading registers.
- * @param[in]  num_words The number of words.
- */
-void IRAM_ATTR esp_dport_access_read_buffer(uint32_t *buff_out, uint32_t address, uint32_t num_words)
-{
-    DPORT_INTERRUPT_DISABLE();
     for (uint32_t i = 0;  i < num_words; ++i) {
         buff_out[i] = DPORT_SEQUENCE_REG_READ(address + i * 4);
     }
-    DPORT_INTERRUPT_RESTORE();
-}
-
-/**
- * @brief Read value from register, SMP-safe version.
- *
- * This method uses the pre-reading of the APB register before reading the register of the DPORT.
- * This implementation is useful for reading DORT registers for single reading without stall other CPU.
- * There is disable/enable interrupt.
- *
- * @param reg Register address
- * @return Value
- */
-uint32_t IRAM_ATTR esp_dport_access_reg_read(uint32_t reg)
-{
-#if defined(BOOTLOADER_BUILD) || defined(CONFIG_FREERTOS_UNICORE) || !defined(ESP_PLATFORM)
-    return _DPORT_REG_READ(reg);
-#else
-    uint32_t apb;
-    unsigned int intLvl;
-    __asm__ __volatile__ (\
-                  "movi %[APB], "XTSTR(0x3f400078)"\n"\
-                  "rsil %[LVL], "XTSTR(3)"\n"\
-                  "l32i %[APB], %[APB], 0\n"\
-                  "l32i %[REG], %[REG], 0\n"\
-                  "wsr  %[LVL], "XTSTR(PS)"\n"\
-                  "rsync\n"\
-                  : [APB]"=a"(apb), [REG]"+a"(reg), [LVL]"=a"(intLvl)\
-                  : \
-                  : "memory" \
-                  );
-    return reg;
-#endif
-}
-
-/**
- * @brief Read value from register, NOT SMP-safe version.
- *
- * This method uses the pre-reading of the APB register before reading the register of the DPORT.
- * There is not disable/enable interrupt.
- * The difference from DPORT_REG_READ() is that the user himself must disable interrupts while DPORT reading.
- * This implementation is useful for reading DORT registers in loop without stall other CPU. Note the usage example.
- * The recommended way to read registers sequentially without stall other CPU
- * is to use the method esp_dport_read_buffer(buff_out, address, num_words). It allows you to read registers in the buffer.
- *
- * \code{c}
- * // This example shows how to use it.
- * { // Use curly brackets to limit the visibility of variables in macros DPORT_INTERRUPT_DISABLE/RESTORE.
- *     DPORT_INTERRUPT_DISABLE(); // Disable interrupt only on current CPU.
- *     for (i = 0; i < max; ++i) {
- *        array[i] = esp_dport_access_sequence_reg_read(Address + i * 4); // reading DPORT registers
- *     }
- *     DPORT_INTERRUPT_RESTORE(); // restore the previous interrupt level
- * }
- * \endcode
- *
- * @param reg Register address
- * @return Value
- */
-uint32_t IRAM_ATTR esp_dport_access_sequence_reg_read(uint32_t reg)
-{
-#if defined(BOOTLOADER_BUILD) || defined(CONFIG_FREERTOS_UNICORE) || !defined(ESP_PLATFORM)
-    return _DPORT_REG_READ(reg);
-#else
-    uint32_t apb;
-    __asm__ __volatile__ (\
-                  "movi %[APB], "XTSTR(0x3f400078)"\n"\
-                  "l32i %[APB], %[APB], 0\n"\
-                  "l32i %[REG], %[REG], 0\n"\
-                  : [APB]"=a"(apb), [REG]"+a"(reg)\
-                  : \
-                  : "memory" \
-                  );
-    return reg;
-#endif
 }

components/esp32s2beta/dport_panic_highint_hdl.S

@@ -25,32 +25,17 @@
 /*
 
 Interrupt , a high-priority interrupt, is used for several things:
-- Dport access mediation
 - Cache error panic handler
 - Interrupt watchdog panic handler
 
 */
 
-#define L4_INTR_STACK_SIZE  8
-#define L4_INTR_A2_OFFSET   0
-#define L4_INTR_A3_OFFSET   4
-    .data
-_l4_intr_stack:
-    .space      L4_INTR_STACK_SIZE
-
     .section .iram1,"ax"
     .global     xt_highint4
     .type       xt_highint4,@function
     .align      4
 xt_highint4:
 
-#ifndef CONFIG_FREERTOS_UNICORE
-    /* See if we're here for the dport access interrupt */
-    rsr     a0, INTERRUPT
-    extui   a0, a0, ETS_DPORT_INUM, 1
-    bnez    a0, .handle_dport_access_int
-#endif // CONFIG_FREERTOS_UNICORE
-
     /* Allocate exception frame and save minimal context. */
     mov     a0, sp
     addi    sp, sp, -XT_STK_FRMSZ
@@ -127,77 +112,9 @@ xt_highint4:
     rsr     a0, EXCSAVE_4                   /* restore a0 */
     rfi     4
 
-
-
-
-#ifndef CONFIG_FREERTOS_UNICORE
-
-    .align      4
-.handle_dport_access_int:
-    /* This section is for dport access register protection */
-    /* Allocate exception frame and save minimal context. */
-    /* Because the interrupt cause code has protection that only
-       allows one cpu to enter in the dport section of the L4
-       interrupt at one time, there's no need to have two
-       _l4_intr_stack for each cpu */
-
-    /* This int is edge-triggered and needs clearing. */
-    movi    a0, (1<<ETS_DPORT_INUM)
-    wsr     a0, INTCLEAR
-
-    /* Save A2, A3 so we can use those registers */
-    movi    a0, _l4_intr_stack
-    s32i    a2, a0, L4_INTR_A2_OFFSET
-    s32i    a3, a0, L4_INTR_A3_OFFSET
-
-    /* handle dport interrupt */
-    /* get CORE_ID */
-    getcoreid   a0
-    beqz    a0, 2f
-
-    /* current cpu is 1 */
-    movi    a0, DPORT_CPU_INTR_FROM_CPU_3_REG
-    movi    a2, 0
-    s32i    a2, a0, 0   /* clear intr */
-    movi    a0, 0       /* other cpu id */
-    j       3f
-2:
-    /* current cpu is 0 */
-    movi    a0, DPORT_CPU_INTR_FROM_CPU_2_REG
-    movi    a2, 0
-    s32i    a2, a0, 0   /* clear intr */
-    movi    a0, 1       /* other cpu id */
-3:
-    /* set and wait flag */
-    movi    a2, dport_access_start
-    addx4   a2, a0, a2
-    movi    a3, 1
-    s32i    a3, a2, 0
-    memw
-    movi    a2, dport_access_end
-    addx4   a2, a0, a2
-.check_dport_access_end:
-    l32i    a3, a2, 0
-    beqz    a3, .check_dport_access_end
-
-    /* Done. Restore registers and return. */
-    movi    a0, _l4_intr_stack
-    l32i    a2, a0, L4_INTR_A2_OFFSET
-    l32i    a3, a0, L4_INTR_A3_OFFSET
-    rsync                                   /* ensure register restored */
-
-    rsr     a0, EXCSAVE_4                   /* restore a0 */
-    rfi     4
-
-#endif // CONFIG_FREERTOS_UNICORE
-
 /* The linker has no reason to link in this file; all symbols it exports are already defined
    (weakly!) in the default int handler. Define a symbol here so we can use it to have the
    linker inspect this anyway. */
 
     .global ld_include_panic_highint_hdl
 ld_include_panic_highint_hdl:
-
-
-
-

components/esp32s2beta/esp_adapter.c

@@ -53,10 +53,6 @@
 #include "esp32s2beta/clk.h"
 #endif
 
-
-extern void esp_dport_access_stall_other_cpu_start_wrap(void);
-extern void esp_dport_access_stall_other_cpu_end_wrap(void);
-
 #define TAG "esp_adapter"
 
 /*
@@ -505,6 +501,11 @@ void IRAM_ATTR coex_bb_reset_unlock_wrapper(uint32_t restore)
 #endif
 }
 
+static void IRAM_ATTR esp_empty_wrapper(void)
+{
+
+}
+
 wifi_osi_funcs_t g_wifi_osi_funcs = {
     ._version = ESP_WIFI_OS_ADAPTER_VERSION,
     ._set_isr = set_isr_wrapper,
@@ -549,8 +550,8 @@ wifi_osi_funcs_t g_wifi_osi_funcs = {
     ._free = free,
     ._get_free_heap_size = esp_get_free_heap_size,
     ._rand = esp_random,
-    ._dport_access_stall_other_cpu_start_wrap = esp_dport_access_stall_other_cpu_start_wrap,
-    ._dport_access_stall_other_cpu_end_wrap = esp_dport_access_stall_other_cpu_end_wrap,
+    ._dport_access_stall_other_cpu_start_wrap = esp_empty_wrapper,
+    ._dport_access_stall_other_cpu_end_wrap = esp_empty_wrapper,
     ._phy_rf_deinit = esp_phy_rf_deinit,
     ._phy_load_cal_and_init = esp_phy_load_cal_and_init,
     ._read_mac = esp_read_mac,

components/esp32s2beta/include/esp32s2beta/dport_access.h

@@ -12,8 +12,6 @@
 // See the License for the specific language governing permissions and
 // limitations under the License.
 
-#include <sdkconfig.h>
-
 #ifndef _ESP_DPORT_ACCESS_H_
 #define _ESP_DPORT_ACCESS_H_
 
@@ -21,29 +19,19 @@
 extern "C" {
 #endif
 
-void esp_dport_access_stall_other_cpu_start(void);
-void esp_dport_access_stall_other_cpu_end(void);
-void esp_dport_access_int_init(void);
-void esp_dport_access_int_pause(void);
-void esp_dport_access_int_resume(void);
+/**
+ * @brief Read a sequence of DPORT registers to the buffer.
+ *
+ * @param[out] buff_out  Contains the read data.
+ * @param[in]  address   Initial address for reading registers.
+ * @param[in]  num_words The number of words.
+ */
 void esp_dport_access_read_buffer(uint32_t *buff_out, uint32_t address, uint32_t num_words);
-uint32_t esp_dport_access_reg_read(uint32_t reg);
-uint32_t esp_dport_access_sequence_reg_read(uint32_t reg);
-//This routine does not stop the dport routines in any way that is recoverable. Please
-//only call in case of panic().
-void esp_dport_access_int_abort(void);
 
-#if defined(BOOTLOADER_BUILD) || defined(CONFIG_FREERTOS_UNICORE) || !defined(ESP_PLATFORM) || !defined(CONFIG_CHIP_IS_ESP32)
 #define DPORT_STALL_OTHER_CPU_START()
 #define DPORT_STALL_OTHER_CPU_END()
 #define DPORT_INTERRUPT_DISABLE()
 #define DPORT_INTERRUPT_RESTORE()
-#else
-#define DPORT_STALL_OTHER_CPU_START()   esp_dport_access_stall_other_cpu_start()
-#define DPORT_STALL_OTHER_CPU_END()     esp_dport_access_stall_other_cpu_end()
-#define DPORT_INTERRUPT_DISABLE()       unsigned int intLvl = XTOS_SET_INTLEVEL(XCHAL_EXCM_LEVEL)
-#define DPORT_INTERRUPT_RESTORE()       XTOS_RESTORE_JUST_INTLEVEL(intLvl)
-#endif
 
 #ifdef __cplusplus
 }

components/esp32s2beta/panic.c

@@ -236,7 +236,6 @@ void panicHandler(XtExcFrame *frame)
 #endif //!CONFIG_FREERTOS_UNICORE
 
     haltOtherCore();
-    esp_dport_access_int_abort();
     panicPutStr("Guru Meditation Error: Core ");
     panicPutDec(core_id);
     panicPutStr(" panic'ed (");
@@ -306,7 +305,6 @@ void panicHandler(XtExcFrame *frame)
 void xt_unhandled_exception(XtExcFrame *frame)
 {
     haltOtherCore();
-    esp_dport_access_int_abort();
     if (!abort_called) {
         panicPutStr("Guru Meditation Error: Core ");
         panicPutDec(xPortGetCoreID());

components/esp32s2beta/system_api.c

@@ -274,9 +274,6 @@ void IRAM_ATTR esp_restart_noos()
     esp_cpu_stall(other_core_id);
 #endif
 
-    // Other core is now stalled, can access DPORT registers directly
-    esp_dport_access_int_abort();
-
     // Disable TG0/TG1 watchdogs
     TIMERG0.wdt_wprotect=TIMG_WDT_WKEY_VALUE;
     TIMERG0.wdt_config0.en = 0;