Merge branch 'esp32p4/add_uart_support' into 'master'

UART: Add uart support for ESP32P4

Closes IDF-6511 and IDF-7506

See merge request espressif/esp-idf!25388

components/bootloader_support/src/bootloader_console.c

@@ -77,6 +77,7 @@ void bootloader_console_init(void)
 #if ESP_ROM_UART_CLK_IS_XTAL
     clock_hz = (uint32_t)rtc_clk_xtal_freq_get() * MHZ; // From esp32-s3 on, UART clk source is selected to XTAL in ROM
 #endif
+    int __DECLARE_RCC_ATOMIC_ENV __attribute__ ((unused)); // To avoid build errors/warnings about __DECLARE_RCC_ATOMIC_ENV
     esp_rom_uart_set_clock_baudrate(uart_num, clock_hz, CONFIG_ESP_CONSOLE_UART_BAUDRATE);
 }
 #endif // CONFIG_ESP_CONSOLE_UART

components/driver/include/esp_private/uart_private.h

@@ -0,0 +1,36 @@
+
+/*
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include "soc/soc_caps.h"
+#include "esp_private/periph_ctrl.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if SOC_PERIPH_CLK_CTRL_SHARED
+#define HP_UART_SRC_CLK_ATOMIC()       PERIPH_RCC_ATOMIC()
+#else
+#define HP_UART_SRC_CLK_ATOMIC()
+#endif
+
+#if SOC_RCC_IS_INDEPENDENT
+#define HP_UART_BUS_CLK_ATOMIC()
+#else
+#define HP_UART_BUS_CLK_ATOMIC()       PERIPH_RCC_ATOMIC()
+#endif
+
+#if (SOC_UART_LP_NUM >= 1)
+#define LP_UART_SRC_CLK_ATOMIC()    PERIPH_RCC_ATOMIC()
+#define LP_UART_BUS_CLK_ATOMIC()    PERIPH_RCC_ATOMIC()
+#endif
+
+#ifdef __cplusplus
+}
+#endif

components/driver/test_apps/uart/main/test_uart.c

@@ -389,7 +389,7 @@ TEST_CASE("uart int state restored after flush", "[uart]")
     };
 
     const uart_port_t uart_echo = UART_NUM_1;
-    const int uart_tx_signal = U1TXD_OUT_IDX;
+    const int uart_tx_signal = uart_periph_signal[uart_echo].pins[SOC_UART_TX_PIN_IDX].signal;
     const int uart_tx = UART1_TX_PIN;
     const int uart_rx = UART1_RX_PIN;
     const int buf_size = 256;

components/driver/uart/uart.c

@@ -26,6 +26,8 @@
 #include "driver/gpio.h"
 #include "driver/rtc_io.h"
 #include "driver/uart_select.h"
+#include "driver/lp_io.h"
+#include "esp_private/uart_private.h"
 #include "esp_private/periph_ctrl.h"
 #include "esp_clk_tree.h"
 #include "sdkconfig.h"
@@ -159,6 +161,12 @@ static uart_context_t uart_context[UART_NUM_MAX] = {
 #if SOC_UART_HP_NUM > 2
     UART_CONTEX_INIT_DEF(UART_NUM_2),
 #endif
+#if SOC_UART_HP_NUM > 3
+    UART_CONTEX_INIT_DEF(UART_NUM_3),
+#endif
+#if SOC_UART_HP_NUM > 4
+    UART_CONTEX_INIT_DEF(UART_NUM_4),
+#endif
 #if (SOC_UART_LP_NUM >= 1)
     UART_CONTEX_INIT_DEF(LP_UART_NUM_0),
 #endif
@@ -171,22 +179,32 @@ static void uart_module_enable(uart_port_t uart_num)
     UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
     if (uart_context[uart_num].hw_enabled != true) {
         if (uart_num < SOC_UART_HP_NUM) {
-            periph_module_enable(uart_periph_signal[uart_num].module);
+            HP_UART_BUS_CLK_ATOMIC() {
+                uart_ll_enable_bus_clock(uart_num, true);
+            }
             if (uart_num != CONFIG_ESP_CONSOLE_UART_NUM) {
                 // Workaround for ESP32C3/S3: enable core reset before enabling uart module clock to prevent uart output
                 // garbage value.
 #if SOC_UART_REQUIRE_CORE_RESET
-                uart_hal_set_reset_core(&(uart_context[uart_num].hal), true);
-                periph_module_reset(uart_periph_signal[uart_num].module);
-                uart_hal_set_reset_core(&(uart_context[uart_num].hal), false);
+                HP_UART_SRC_CLK_ATOMIC(){
+                    uart_hal_set_reset_core(&(uart_context[uart_num].hal), true);
+                }
+                HP_UART_BUS_CLK_ATOMIC() {
+                    uart_ll_reset_register(uart_num);
+                }
+                HP_UART_SRC_CLK_ATOMIC(){
+                    uart_hal_set_reset_core(&(uart_context[uart_num].hal), false);
+                }
 #else
-                periph_module_reset(uart_periph_signal[uart_num].module);
+                HP_UART_BUS_CLK_ATOMIC() {
+                    uart_ll_reset_register(uart_num);
+                }
 #endif
             }
         }
 #if (SOC_UART_LP_NUM >= 1)
         else {
-            PERIPH_RCC_ATOMIC() {
+            LP_UART_BUS_CLK_ATOMIC() {
                 lp_uart_ll_enable_bus_clock(uart_num - SOC_UART_HP_NUM, true);
                 lp_uart_ll_reset_register(uart_num - SOC_UART_HP_NUM);
             }
@@ -202,11 +220,13 @@ static void uart_module_disable(uart_port_t uart_num)
     UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
     if (uart_context[uart_num].hw_enabled != false) {
         if (uart_num != CONFIG_ESP_CONSOLE_UART_NUM && uart_num < SOC_UART_HP_NUM) {
-            periph_module_disable(uart_periph_signal[uart_num].module);
+            HP_UART_BUS_CLK_ATOMIC() {
+                uart_ll_enable_bus_clock(uart_num, false);
+            }
         }
 #if (SOC_UART_LP_NUM >= 1)
         else if (uart_num >= SOC_UART_HP_NUM) {
-            PERIPH_RCC_ATOMIC() {
+            LP_UART_BUS_CLK_ATOMIC() {
                 lp_uart_ll_enable_bus_clock(uart_num - SOC_UART_HP_NUM, false);
             }
         }
@@ -286,7 +306,18 @@ esp_err_t uart_set_baudrate(uart_port_t uart_num, uint32_t baud_rate)
     ESP_RETURN_ON_ERROR(esp_clk_tree_src_get_freq_hz(src_clk, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &sclk_freq), UART_TAG, "Invalid src_clk");
 
     UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
-    uart_hal_set_baudrate(&(uart_context[uart_num].hal), baud_rate, sclk_freq);
+
+    if (uart_num < SOC_UART_HP_NUM) {
+        HP_UART_SRC_CLK_ATOMIC() {
+            uart_hal_set_baudrate(&(uart_context[uart_num].hal), baud_rate, sclk_freq);
+        }
+    }
+#if (SOC_UART_LP_NUM >= 1)
+    else {
+        lp_uart_ll_set_baudrate(uart_context[uart_num].hal.dev, baud_rate, sclk_freq);
+    }
+#endif
+
     UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
     return ESP_OK;
 }
@@ -644,42 +675,95 @@ esp_err_t uart_set_pin(uart_port_t uart_num, int tx_io_num, int rx_io_num, int r
         ESP_RETURN_ON_FALSE((cts_io_num < 0 || (GPIO_IS_VALID_GPIO(cts_io_num))), ESP_FAIL, UART_TAG, "cts_io_num error");
     }
 #if (SOC_UART_LP_NUM >= 1)
-    else { // LP_UART has its fixed IOs
+    else { // LP_UART IO check
+
+#if !SOC_LP_GPIO_MATRIX_SUPPORTED
         const uart_periph_sig_t *pins = uart_periph_signal[uart_num].pins;
+        // LP_UART has its fixed IOs
         ESP_RETURN_ON_FALSE((tx_io_num < 0 || (tx_io_num == pins[SOC_UART_TX_PIN_IDX].default_gpio)), ESP_FAIL, UART_TAG, "tx_io_num error");
         ESP_RETURN_ON_FALSE((rx_io_num < 0 || (rx_io_num == pins[SOC_UART_RX_PIN_IDX].default_gpio)), ESP_FAIL, UART_TAG, "rx_io_num error");
         ESP_RETURN_ON_FALSE((rts_io_num < 0 || (rts_io_num == pins[SOC_UART_RTS_PIN_IDX].default_gpio)), ESP_FAIL, UART_TAG, "rts_io_num error");
         ESP_RETURN_ON_FALSE((cts_io_num < 0 || (cts_io_num == pins[SOC_UART_CTS_PIN_IDX].default_gpio)), ESP_FAIL, UART_TAG, "cts_io_num error");
+#else
+        // LP_UART signals can be routed to any LP_IOs
+        ESP_RETURN_ON_FALSE((tx_io_num < 0 || rtc_gpio_is_valid_gpio(tx_io_num)), ESP_FAIL, UART_TAG, "tx_io_num error");
+        ESP_RETURN_ON_FALSE((rx_io_num < 0 || rtc_gpio_is_valid_gpio(rx_io_num)), ESP_FAIL, UART_TAG, "rx_io_num error");
+        ESP_RETURN_ON_FALSE((rts_io_num < 0 || rtc_gpio_is_valid_gpio(rts_io_num)), ESP_FAIL, UART_TAG, "rts_io_num error");
+        ESP_RETURN_ON_FALSE((cts_io_num < 0 || rtc_gpio_is_valid_gpio(cts_io_num)), ESP_FAIL, UART_TAG, "cts_io_num error");
+
+#endif  // SOC_LP_GPIO_MATRIX_SUPPORTED
     }
 #endif
 
     /* In the following statements, if the io_num is negative, no need to configure anything. */
     if (tx_io_num >= 0 && !uart_try_set_iomux_pin(uart_num, tx_io_num, SOC_UART_TX_PIN_IDX)) {
-        gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[tx_io_num], PIN_FUNC_GPIO);
-        gpio_set_level(tx_io_num, 1);
-        esp_rom_gpio_connect_out_signal(tx_io_num, UART_PERIPH_SIGNAL(uart_num, SOC_UART_TX_PIN_IDX), 0, 0);
+        if (uart_num < SOC_UART_HP_NUM) {
+            gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[tx_io_num], PIN_FUNC_GPIO);
+            gpio_set_level(tx_io_num, 1);
+            esp_rom_gpio_connect_out_signal(tx_io_num, UART_PERIPH_SIGNAL(uart_num, SOC_UART_TX_PIN_IDX), 0, 0);
+        }
+#if SOC_LP_GPIO_MATRIX_SUPPORTED
+        else {
+            rtc_gpio_set_direction(tx_io_num, RTC_GPIO_MODE_OUTPUT_ONLY);
+            rtc_gpio_init(tx_io_num);
+            rtc_gpio_iomux_func_sel(tx_io_num, 1);
+
+            lp_gpio_connect_out_signal(tx_io_num, UART_PERIPH_SIGNAL(uart_num, SOC_UART_TX_PIN_IDX), 0, 0);
+        }
+#endif
     }
 
     if (rx_io_num >= 0 && !uart_try_set_iomux_pin(uart_num, rx_io_num, SOC_UART_RX_PIN_IDX)) {
-        gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[rx_io_num], PIN_FUNC_GPIO);
-        gpio_set_pull_mode(rx_io_num, GPIO_PULLUP_ONLY);
-        gpio_set_direction(rx_io_num, GPIO_MODE_INPUT);
-        esp_rom_gpio_connect_in_signal(rx_io_num, UART_PERIPH_SIGNAL(uart_num, SOC_UART_RX_PIN_IDX), 0);
+        if (uart_num < SOC_UART_HP_NUM) {
+            gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[rx_io_num], PIN_FUNC_GPIO);
+            gpio_set_pull_mode(rx_io_num, GPIO_PULLUP_ONLY);
+            gpio_set_direction(rx_io_num, GPIO_MODE_INPUT);
+            esp_rom_gpio_connect_in_signal(rx_io_num, UART_PERIPH_SIGNAL(uart_num, SOC_UART_RX_PIN_IDX), 0);
+        }
+#if SOC_LP_GPIO_MATRIX_SUPPORTED
+        else {
+            rtc_gpio_set_direction(rx_io_num, RTC_GPIO_MODE_INPUT_ONLY);
+            rtc_gpio_init(rx_io_num);
+            rtc_gpio_iomux_func_sel(rx_io_num, 1);
+
+            lp_gpio_connect_in_signal(rx_io_num, UART_PERIPH_SIGNAL(uart_num, SOC_UART_RX_PIN_IDX), 0);
+        }
+#endif
     }
 
     if (rts_io_num >= 0 && !uart_try_set_iomux_pin(uart_num, rts_io_num, SOC_UART_RTS_PIN_IDX)) {
-        gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[rts_io_num], PIN_FUNC_GPIO);
-        gpio_set_direction(rts_io_num, GPIO_MODE_OUTPUT);
-        esp_rom_gpio_connect_out_signal(rts_io_num, UART_PERIPH_SIGNAL(uart_num, SOC_UART_RTS_PIN_IDX), 0, 0);
+        if (uart_num < SOC_UART_HP_NUM) {
+            gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[rts_io_num], PIN_FUNC_GPIO);
+            gpio_set_direction(rts_io_num, GPIO_MODE_OUTPUT);
+            esp_rom_gpio_connect_out_signal(rts_io_num, UART_PERIPH_SIGNAL(uart_num, SOC_UART_RTS_PIN_IDX), 0, 0);
+        }
+#if SOC_LP_GPIO_MATRIX_SUPPORTED
+        else {
+            rtc_gpio_set_direction(rts_io_num, RTC_GPIO_MODE_OUTPUT_ONLY);
+            rtc_gpio_init(rts_io_num);
+            rtc_gpio_iomux_func_sel(rts_io_num, 1);
+            lp_gpio_connect_out_signal(rts_io_num, UART_PERIPH_SIGNAL(uart_num, SOC_UART_RTS_PIN_IDX), 0, 0);
+        }
+#endif
     }
 
     if (cts_io_num >= 0  && !uart_try_set_iomux_pin(uart_num, cts_io_num, SOC_UART_CTS_PIN_IDX)) {
-        gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[cts_io_num], PIN_FUNC_GPIO);
-        gpio_set_pull_mode(cts_io_num, GPIO_PULLUP_ONLY);
-        gpio_set_direction(cts_io_num, GPIO_MODE_INPUT);
-        esp_rom_gpio_connect_in_signal(cts_io_num, UART_PERIPH_SIGNAL(uart_num, SOC_UART_CTS_PIN_IDX), 0);
-    }
+        if (uart_num < SOC_UART_HP_NUM) {
+            gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[cts_io_num], PIN_FUNC_GPIO);
+            gpio_set_pull_mode(cts_io_num, GPIO_PULLUP_ONLY);
+            gpio_set_direction(cts_io_num, GPIO_MODE_INPUT);
+            esp_rom_gpio_connect_in_signal(cts_io_num, UART_PERIPH_SIGNAL(uart_num, SOC_UART_CTS_PIN_IDX), 0);
+        }
+#if SOC_LP_GPIO_MATRIX_SUPPORTED
+        else {
+            rtc_gpio_set_direction(cts_io_num, RTC_GPIO_MODE_INPUT_ONLY);
+            rtc_gpio_init(cts_io_num);
+            rtc_gpio_iomux_func_sel(cts_io_num, 1);
 
+            lp_gpio_connect_in_signal(cts_io_num, UART_PERIPH_SIGNAL(uart_num, SOC_UART_CTS_PIN_IDX), 0);
+        }
+#endif
+    }
     return ESP_OK;
 }
 
@@ -743,16 +827,19 @@ esp_err_t uart_param_config(uart_port_t uart_num, const uart_config_t *uart_conf
     UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock));
     uart_hal_init(&(uart_context[uart_num].hal), uart_num);
     if (uart_num < SOC_UART_HP_NUM) {
-        uart_hal_set_sclk(&(uart_context[uart_num].hal), uart_sclk_sel);
+        HP_UART_SRC_CLK_ATOMIC() {
+            uart_hal_set_sclk(&(uart_context[uart_num].hal), uart_sclk_sel);
+            uart_hal_set_baudrate(&(uart_context[uart_num].hal), uart_config->baud_rate, sclk_freq);
+        }
     }
 #if (SOC_UART_LP_NUM >= 1)
     else {
-        PERIPH_RCC_ATOMIC() {
+        LP_UART_SRC_CLK_ATOMIC() {
             lp_uart_ll_set_source_clk(uart_context[uart_num].hal.dev, (soc_periph_lp_uart_clk_src_t)uart_sclk_sel);
         }
+        lp_uart_ll_set_baudrate(uart_context[uart_num].hal.dev, uart_config->baud_rate, sclk_freq);
     }
 #endif
-    uart_hal_set_baudrate(&(uart_context[uart_num].hal), uart_config->baud_rate, sclk_freq);
     uart_hal_set_parity(&(uart_context[uart_num].hal), uart_config->parity);
     uart_hal_set_data_bit_num(&(uart_context[uart_num].hal), uart_config->data_bits);
     uart_hal_set_stop_bits(&(uart_context[uart_num].hal), uart_config->stop_bits);

components/esp_hw_support/port/esp32p4/esp_clk_tree.c

@@ -25,6 +25,12 @@ uint32_t *freq_value)
     case SOC_MOD_CLK_XTAL:
         clk_src_freq = 40 * MHZ;
         break;
+    case SOC_MOD_CLK_XTAL_D2:
+        clk_src_freq = (40 * MHZ) >> 1;
+        break;
+    case SOC_MOD_CLK_LP_PLL:
+        clk_src_freq = 8 * MHZ;
+        break;
     default:
         break;
     }

components/esp_hw_support/sleep_modes.c

@@ -425,7 +425,7 @@ static void IRAM_ATTR flush_uarts(void)
 #ifdef CONFIG_IDF_TARGET_ESP32
         esp_rom_uart_tx_wait_idle(i);
 #else
-        if (periph_ll_uart_enabled(i)) {
+        if (uart_ll_is_enabled(i)) {
             esp_rom_uart_tx_wait_idle(i);
         }
 #endif
@@ -443,7 +443,7 @@ FORCE_INLINE_ATTR void suspend_uarts(void)
     s_suspended_uarts_bmap = 0;
     for (int i = 0; i < SOC_UART_HP_NUM; ++i) {
 #ifndef CONFIG_IDF_TARGET_ESP32
-        if (!periph_ll_uart_enabled(i)) {
+        if (!uart_ll_is_enabled(i)) {
             continue;
         }
 #endif

components/esp_pm/pm_impl.c

@@ -17,6 +17,7 @@
 #include "esp_cpu.h"
 
 #include "esp_private/crosscore_int.h"
+#include "esp_private/uart_private.h"
 
 #include "soc/rtc.h"
 #include "hal/uart_ll.h"
@@ -897,14 +898,19 @@ void esp_pm_impl_init(void)
 #else
     #error "No UART clock source is aware of DFS"
 #endif // SOC_UART_SUPPORT_xxx
-    while(!uart_ll_is_tx_idle(UART_LL_GET_HW(CONFIG_ESP_CONSOLE_UART_NUM)));
+    while (!uart_ll_is_tx_idle(UART_LL_GET_HW(CONFIG_ESP_CONSOLE_UART_NUM))) {
+        ;
+    }
     /* When DFS is enabled, override system setting and use REFTICK as UART clock source */
-    uart_ll_set_sclk(UART_LL_GET_HW(CONFIG_ESP_CONSOLE_UART_NUM), (soc_module_clk_t)clk_source);
-
+    HP_UART_SRC_CLK_ATOMIC() {
+        uart_ll_set_sclk(UART_LL_GET_HW(CONFIG_ESP_CONSOLE_UART_NUM), (soc_module_clk_t)clk_source);
+    }
     uint32_t sclk_freq;
     esp_err_t err = uart_get_sclk_freq(clk_source, &sclk_freq);
     assert(err == ESP_OK);
-    uart_ll_set_baudrate(UART_LL_GET_HW(CONFIG_ESP_CONSOLE_UART_NUM), CONFIG_ESP_CONSOLE_UART_BAUDRATE, sclk_freq);
+    HP_UART_SRC_CLK_ATOMIC() {
+        uart_ll_set_baudrate(UART_LL_GET_HW(CONFIG_ESP_CONSOLE_UART_NUM), CONFIG_ESP_CONSOLE_UART_BAUDRATE, sclk_freq);
+    }
 #endif // CONFIG_ESP_CONSOLE_UART
 
 #ifdef CONFIG_PM_TRACE

components/esp_rom/include/esp_rom_uart.h

@@ -11,6 +11,7 @@ extern "C" {
 #endif
 
 #include <stdint.h>
+#include "hal/uart_ll.h"
 
 #define ESP_ROM_CDC_ACM_WORK_BUF_MIN 128
 
@@ -33,8 +34,10 @@ void esp_rom_uart_tx_wait_idle(uint8_t uart_no);
  * @param uart_no UART port number
  * @param clock_hz Source clock (in Hz)
  * @param baud_rate Baud rate to set
+ *
+ * @note Only for HP UART
  */
-void esp_rom_uart_set_clock_baudrate(uint8_t uart_no, uint32_t clock_hz, uint32_t baud_rate);
+#define esp_rom_uart_set_clock_baudrate(uart_no, clock_hz, baud_rate) uart_ll_set_baudrate(UART_LL_GET_HW(uart_no), baud_rate, clock_hz)
 
 /**
  * @brief Wait until UART TX FIFO is empty (i.e. flush TX FIFO)

components/esp_rom/patches/esp_rom_uart.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2010-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -23,11 +23,6 @@ IRAM_ATTR void esp_rom_uart_tx_wait_idle(uint8_t uart_no)
 }
 #endif
 
-IRAM_ATTR void esp_rom_uart_set_clock_baudrate(uint8_t uart_no, uint32_t clock_hz, uint32_t baud_rate)
-{
-    uart_ll_set_baudrate(UART_LL_GET_HW(uart_no), baud_rate, clock_hz);
-}
-
 #if CONFIG_IDF_TARGET_ESP32C3
 /**
  * The ESP32-C3 ROM has released two versions, one is the ECO3 version,

components/esp_system/port/cpu_start.c

@@ -682,6 +682,9 @@ void IRAM_ATTR call_start_cpu0(void)
     clock_hz = esp_clk_xtal_freq(); // From esp32-s3 on, UART clock source is selected to XTAL in ROM
 #endif
     esp_rom_uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);
+
+    // In a single thread mode, the freertos is not started yet. So don't have to use a critical section.
+    int __DECLARE_RCC_ATOMIC_ENV __attribute__ ((unused)); // To avoid build errors about spinlock's __DECLARE_RCC_ATOMIC_ENV
     esp_rom_uart_set_clock_baudrate(CONFIG_ESP_CONSOLE_UART_NUM, clock_hz, CONFIG_ESP_CONSOLE_UART_BAUDRATE);
 #endif
 #endif

components/esp_system/test_apps/esp_system_unity_tests/main/test_sleep.c

@@ -26,6 +26,7 @@
 #include "esp_rom_sys.h"
 #include "esp_timer.h"
 #include "esp_private/esp_clk.h"
+#include "esp_private/uart_private.h"
 #include "esp_random.h"
 #include "nvs_flash.h"
 #include "nvs.h"
@@ -229,11 +230,14 @@ TEST_CASE("light sleep and frequency switching", "[deepsleep]")
 #elif SOC_UART_SUPPORT_XTAL_CLK
     clk_source = UART_SCLK_XTAL;
 #endif
-    uart_ll_set_sclk(UART_LL_GET_HW(CONFIG_ESP_CONSOLE_UART_NUM), (soc_module_clk_t)clk_source);
-
+    HP_UART_SRC_CLK_ATOMIC() {
+        uart_ll_set_sclk(UART_LL_GET_HW(CONFIG_ESP_CONSOLE_UART_NUM), (soc_module_clk_t)clk_source);
+    }
     uint32_t sclk_freq;
     TEST_ESP_OK(uart_get_sclk_freq(clk_source, &sclk_freq));
-    uart_ll_set_baudrate(UART_LL_GET_HW(CONFIG_ESP_CONSOLE_UART_NUM), CONFIG_ESP_CONSOLE_UART_BAUDRATE, sclk_freq);
+    HP_UART_SRC_CLK_ATOMIC() {
+        uart_ll_set_baudrate(UART_LL_GET_HW(CONFIG_ESP_CONSOLE_UART_NUM), CONFIG_ESP_CONSOLE_UART_BAUDRATE, sclk_freq);
+    }
 #endif
 
     rtc_cpu_freq_config_t config_xtal, config_default;

components/hal/esp32/include/hal/clk_gate_ll.h

@@ -266,19 +266,6 @@ static inline void periph_ll_wifi_module_disable_clk_set_rst(void)
     DPORT_SET_PERI_REG_MASK(DPORT_CORE_RST_EN_REG, 0);
 }
 
-FORCE_INLINE_ATTR bool periph_ll_uart_enabled(uint32_t uart_num)
-{
-    HAL_ASSERT(uart_num < SOC_UART_HP_NUM);
-    uint32_t uart_rst_bit = ((uart_num == 0) ? DPORT_UART_RST :
-                            (uart_num == 1) ? DPORT_UART1_RST :
-                            (uart_num == 2) ? DPORT_UART2_RST : 0);
-    uint32_t uart_en_bit  = ((uart_num == 0) ? DPORT_UART_CLK_EN :
-                            (uart_num == 1) ? DPORT_UART1_CLK_EN :
-                            (uart_num == 2) ? DPORT_UART2_CLK_EN : 0);
-    return DPORT_REG_GET_BIT(DPORT_PERIP_RST_EN_REG, uart_rst_bit) == 0 &&
-        DPORT_REG_GET_BIT(DPORT_PERIP_CLK_EN_REG, uart_en_bit) != 0;
-}
-
 #ifdef __cplusplus
 }
 #endif

components/hal/esp32/include/hal/uart_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -15,6 +15,7 @@
 #include "esp_attr.h"
 #include "soc/uart_reg.h"
 #include "soc/uart_struct.h"
+#include "soc/dport_reg.h"
 #include "hal/uart_types.h"
 
 #ifdef __cplusplus
@@ -55,6 +56,81 @@ typedef enum {
     UART_INTR_CMD_CHAR_DET     = (0x1<<18),
 } uart_intr_t;
 
+/**
+ * @brief Check if UART is enabled or disabled.
+ *
+ * @param uart_num UART port number, the max port number is (UART_NUM_MAX -1).
+ *
+ * @return true: enabled; false: disabled
+ */
+FORCE_INLINE_ATTR bool uart_ll_is_enabled(uint32_t uart_num)
+{
+    uint32_t uart_rst_bit = ((uart_num == 0) ? DPORT_UART_RST :
+                            (uart_num == 1) ? DPORT_UART1_RST :
+                            (uart_num == 2) ? DPORT_UART2_RST : 0);
+    uint32_t uart_en_bit  = ((uart_num == 0) ? DPORT_UART_CLK_EN :
+                            (uart_num == 1) ? DPORT_UART1_CLK_EN :
+                            (uart_num == 2) ? DPORT_UART2_CLK_EN : 0);
+    return DPORT_REG_GET_BIT(DPORT_PERIP_RST_EN_REG, uart_rst_bit) == 0 &&
+        DPORT_REG_GET_BIT(DPORT_PERIP_CLK_EN_REG, uart_en_bit) != 0;
+}
+
+/**
+ * @brief Enable the bus clock for uart
+ * @param uart_num UART port number, the max port number is (UART_NUM_MAX -1).
+ * @param enable true to enable, false to disable
+ */
+static inline void uart_ll_enable_bus_clock(uart_port_t uart_num, bool enable)
+{
+    uint32_t reg_val = DPORT_READ_PERI_REG(DPORT_PERIP_CLK_EN_REG);
+    switch (uart_num) {
+    case 0:
+        reg_val = reg_val & (~DPORT_UART_CLK_EN);
+        reg_val = reg_val | (enable << 2);
+        break;
+    case 1:
+        reg_val = reg_val & (~DPORT_UART1_CLK_EN);
+        reg_val = reg_val | (enable << 5);
+        break;
+    case 2:
+        reg_val = reg_val & (~DPORT_UART2_CLK_EN);
+        reg_val = reg_val | (enable << 23);
+        break;
+    default:
+        abort();
+        break;
+    }
+    DPORT_WRITE_PERI_REG(DPORT_PERIP_CLK_EN_REG, reg_val);
+}
+#define uart_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; uart_ll_enable_bus_clock(__VA_ARGS__)
+
+/**
+ * @brief Reset UART module
+ * @param uart_num UART port number, the max port number is (UART_NUM_MAX -1).
+ */
+static inline void uart_ll_reset_register(uart_port_t uart_num)
+{
+    switch (uart_num) {
+    case 0:
+        DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_UART_RST);
+        DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_UART_RST);
+        break;
+    case 1:
+        DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_UART1_RST);
+        DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_UART1_RST);
+        break;
+    case 2:
+        DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_UART2_RST);
+        DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_UART2_RST);
+        break;
+    default:
+        abort();
+        break;
+    }
+}
+// SYSTEM.perip_rst_enx are shared registers, so this function must be used in an atomic way
+#define uart_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; uart_ll_reset_register(__VA_ARGS__)
+
 /**
  * @brief  Set the UART source clock.
  *

components/hal/esp32c2/include/hal/clk_gate_ll.h

@@ -216,17 +216,6 @@ static inline void periph_ll_wifi_module_disable_clk_set_rst(void)
     DPORT_SET_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG, 0);
 }
 
-FORCE_INLINE_ATTR bool periph_ll_uart_enabled(uint32_t uart_num)
-{
-    HAL_ASSERT(uart_num < SOC_UART_HP_NUM);
-    uint32_t uart_rst_bit = ((uart_num == 0) ? SYSTEM_UART_RST :
-                            (uart_num == 1) ? SYSTEM_UART1_RST : 0);
-    uint32_t uart_en_bit  = ((uart_num == 0) ? SYSTEM_UART_CLK_EN :
-                            (uart_num == 1) ? SYSTEM_UART1_CLK_EN : 0);
-    return DPORT_REG_GET_BIT(SYSTEM_PERIP_RST_EN0_REG, uart_rst_bit) == 0 &&
-        DPORT_REG_GET_BIT(SYSTEM_PERIP_CLK_EN0_REG, uart_en_bit) != 0;
-}
-
 #ifdef __cplusplus
 }
 #endif

components/hal/esp32c2/include/hal/uart_ll.h

@@ -11,10 +11,13 @@
 
 #include <stdlib.h>
 #include "hal/uart_types.h"
+#include "hal/misc.h"
 #include "soc/uart_reg.h"
 #include "soc/uart_struct.h"
 #include "soc/clk_tree_defs.h"
-#include "hal/misc.h"
+#include "soc/system_struct.h"
+#include "soc/system_reg.h"
+#include "soc/dport_access.h"
 #include "esp_attr.h"
 
 #ifdef __cplusplus
@@ -56,6 +59,68 @@ typedef enum {
     UART_INTR_WAKEUP           = (0x1 << 19),
 } uart_intr_t;
 
+/**
+ * @brief Check if UART is enabled or disabled.
+ *
+ * @param uart_num UART port number, the max port number is (UART_NUM_MAX -1).
+ *
+ * @return true: enabled; false: disabled
+ */
+FORCE_INLINE_ATTR bool uart_ll_is_enabled(uint32_t uart_num)
+{
+    uint32_t uart_rst_bit = ((uart_num == 0) ? SYSTEM_UART_RST :
+                            (uart_num == 1) ? SYSTEM_UART1_RST : 0);
+    uint32_t uart_en_bit  = ((uart_num == 0) ? SYSTEM_UART_CLK_EN :
+                            (uart_num == 1) ? SYSTEM_UART1_CLK_EN : 0);
+    return DPORT_REG_GET_BIT(SYSTEM_PERIP_RST_EN0_REG, uart_rst_bit) == 0 &&
+        DPORT_REG_GET_BIT(SYSTEM_PERIP_CLK_EN0_REG, uart_en_bit) != 0;
+}
+
+/**
+ * @brief Enable the bus clock for uart
+ * @param uart_num UART port number, the max port number is (UART_NUM_MAX -1).
+ * @param enable true to enable, false to disable
+ */
+static inline void uart_ll_enable_bus_clock(uart_port_t uart_num, bool enable)
+{
+    switch (uart_num) {
+    case 0:
+        SYSTEM.perip_clk_en0.uart_clk_en = enable;
+        break;
+    case 1:
+        SYSTEM.perip_clk_en0.uart1_clk_en = enable;
+        break;
+    default:
+        abort();
+        break;
+    }
+}
+// SYSTEM.perip_clk_en0 is a shared register, so this function must be used in an atomic way
+#define uart_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; uart_ll_enable_bus_clock(__VA_ARGS__)
+
+/**
+ * @brief Reset UART module
+ * @param uart_num UART port number, the max port number is (UART_NUM_MAX -1).
+ */
+static inline void uart_ll_reset_register(uart_port_t uart_num)
+{
+    switch (uart_num) {
+    case 0:
+        SYSTEM.perip_rst_en0.uart_rst = 1;
+        SYSTEM.perip_rst_en0.uart_rst = 0;
+        break;
+    case 1:
+        SYSTEM.perip_rst_en0.uart1_rst = 1;
+        SYSTEM.perip_rst_en0.uart1_rst = 0;
+        break;
+    default:
+        abort();
+        break;
+    }
+}
+// SYSTEM.perip_rst_en0 is a shared register, so this function must be used in an atomic way
+#define uart_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; uart_ll_reset_register(__VA_ARGS__)
+
 /**
  * @brief  Configure the UART core reset.
  *
@@ -97,6 +162,7 @@ FORCE_INLINE_ATTR void uart_ll_sclk_disable(uart_dev_t *hw)
     hw->clk_conf.tx_sclk_en = 0;
 }
 
+
 /**
  * @brief  Set the UART source clock.
  *

components/hal/esp32c3/include/hal/clk_gate_ll.h

@@ -265,17 +265,6 @@ static inline void periph_ll_wifi_module_disable_clk_set_rst(void)
     DPORT_SET_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG, 0);
 }
 
-FORCE_INLINE_ATTR bool periph_ll_uart_enabled(uint32_t uart_num)
-{
-    HAL_ASSERT(uart_num < SOC_UART_HP_NUM);
-    uint32_t uart_rst_bit = ((uart_num == 0) ? SYSTEM_UART_RST :
-                            (uart_num == 1) ? SYSTEM_UART1_RST : 0);
-    uint32_t uart_en_bit  = ((uart_num == 0) ? SYSTEM_UART_CLK_EN :
-                            (uart_num == 1) ? SYSTEM_UART1_CLK_EN : 0);
-    return DPORT_REG_GET_BIT(SYSTEM_PERIP_RST_EN0_REG, uart_rst_bit) == 0 &&
-        DPORT_REG_GET_BIT(SYSTEM_PERIP_CLK_EN0_REG, uart_en_bit) != 0;
-}
-
 #ifdef __cplusplus
 }
 #endif

components/hal/esp32c3/include/hal/uart_ll.h

@@ -15,6 +15,9 @@
 #include "hal/uart_types.h"
 #include "soc/uart_reg.h"
 #include "soc/uart_struct.h"
+#include "soc/system_struct.h"
+#include "soc/system_reg.h"
+#include "soc/dport_access.h"
 #include "esp_attr.h"
 
 #ifdef __cplusplus
@@ -56,6 +59,68 @@ typedef enum {
     UART_INTR_WAKEUP           = (0x1 << 19),
 } uart_intr_t;
 
+/**
+ * @brief Check if UART is enabled or disabled.
+ *
+ * @param uart_num UART port number, the max port number is (UART_NUM_MAX -1).
+ *
+ * @return true: enabled; false: disabled
+ */
+FORCE_INLINE_ATTR bool uart_ll_is_enabled(uint32_t uart_num)
+{
+    uint32_t uart_rst_bit = ((uart_num == 0) ? SYSTEM_UART_RST :
+                            (uart_num == 1) ? SYSTEM_UART1_RST : 0);
+    uint32_t uart_en_bit  = ((uart_num == 0) ? SYSTEM_UART_CLK_EN :
+                            (uart_num == 1) ? SYSTEM_UART1_CLK_EN : 0);
+    return DPORT_REG_GET_BIT(SYSTEM_PERIP_RST_EN0_REG, uart_rst_bit) == 0 &&
+        DPORT_REG_GET_BIT(SYSTEM_PERIP_CLK_EN0_REG, uart_en_bit) != 0;
+}
+
+/**
+ * @brief Enable the bus clock for uart
+ * @param uart_num UART port number, the max port number is (UART_NUM_MAX -1).
+ * @param enable true to enable, false to disable
+ */
+static inline void uart_ll_enable_bus_clock(uart_port_t uart_num, bool enable)
+{
+    switch (uart_num) {
+    case 0:
+        SYSTEM.perip_clk_en0.reg_uart_clk_en = enable;
+        break;
+    case 1:
+        SYSTEM.perip_clk_en0.reg_uart1_clk_en = enable;
+        break;
+    default:
+        abort();
+        break;
+    }
+}
+// SYSTEM.perip_clk_enx are shared registers, so this function must be used in an atomic way
+#define uart_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; uart_ll_enable_bus_clock(__VA_ARGS__)
+
+/**
+ * @brief Reset UART module
+ * @param uart_num UART port number, the max port number is (UART_NUM_MAX -1).
+ */
+static inline void uart_ll_reset_register(uart_port_t uart_num)
+{
+    switch (uart_num) {
+    case 0:
+        SYSTEM.perip_rst_en0.reg_uart_rst = 1;
+        SYSTEM.perip_rst_en0.reg_uart_rst = 0;
+        break;
+    case 1:
+        SYSTEM.perip_rst_en0.reg_uart1_rst = 1;
+        SYSTEM.perip_rst_en0.reg_uart1_rst = 0;
+        break;
+    default:
+        abort();
+        break;
+    }
+}
+// SYSTEM.perip_rst_enx are shared registers, so this function must be used in an atomic way
+#define uart_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; uart_ll_reset_register(__VA_ARGS__)
+
 /**
  * @brief  Configure the UART core reset.
  *

components/hal/esp32c6/include/hal/clk_gate_ll.h

@@ -330,19 +330,6 @@ static inline bool IRAM_ATTR periph_ll_periph_enabled(periph_module_t periph)
            REG_GET_BIT(periph_ll_get_clk_en_reg(periph), periph_ll_get_clk_en_mask(periph)) != 0;
 }
 
-FORCE_INLINE_ATTR bool periph_ll_uart_enabled(uint32_t uart_num)
-{
-    HAL_ASSERT(uart_num < SOC_UART_HP_NUM);
-    uint32_t uart_clk_config_reg = ((uart_num == 0) ? PCR_UART0_CONF_REG :
-                                    (uart_num == 1) ? PCR_UART1_CONF_REG : 0);
-    uint32_t uart_rst_bit = ((uart_num == 0) ? PCR_UART0_RST_EN :
-                            (uart_num == 1) ? PCR_UART1_RST_EN : 0);
-    uint32_t uart_en_bit  = ((uart_num == 0) ? PCR_UART0_CLK_EN :
-                            (uart_num == 1) ? PCR_UART1_CLK_EN : 0);
-    return REG_GET_BIT(uart_clk_config_reg, uart_rst_bit) == 0 &&
-        REG_GET_BIT(uart_clk_config_reg, uart_en_bit) != 0;
-}
-
 #ifdef __cplusplus
 }
 #endif

components/hal/esp32c6/include/hal/uart_ll.h

@@ -16,6 +16,7 @@
 #include "soc/uart_struct.h"
 #include "soc/lp_uart_reg.h"
 #include "soc/pcr_struct.h"
+#include "soc/pcr_reg.h"
 #include "soc/lp_clkrst_struct.h"
 #include "soc/lpperi_struct.h"
 #include "hal/assert.h"
@@ -84,6 +85,19 @@ typedef enum {
     UART_INTR_WAKEUP           = (0x1 << 19),
 } uart_intr_t;
 
+/**
+ * @brief Sync the update to UART core clock domain
+ *
+ * @param hw Beginning address of the peripheral registers.
+ *
+ * @return None.
+ */
+FORCE_INLINE_ATTR void uart_ll_update(uart_dev_t *hw)
+{
+    hw->reg_update.reg_update = 1;
+    while (hw->reg_update.reg_update);
+}
+
 /****************************************** LP_UART Specific ********************************************/
 /**
  * @brief  Get the LP_UART source clock.
@@ -130,6 +144,32 @@ static inline void lp_uart_ll_set_source_clk(uart_dev_t *hw, soc_periph_lp_uart_
 /// LP_CLKRST.lpperi is a shared register, so this function must be used in an atomic way
 #define lp_uart_ll_set_source_clk(...) (void)__DECLARE_RCC_ATOMIC_ENV; lp_uart_ll_set_source_clk(__VA_ARGS__)
 
+/**
+ * @brief  Configure the lp uart baud-rate.
+ *
+ * @param  hw Beginning address of the peripheral registers.
+ * @param  baud The baud rate to be set.
+ * @param  sclk_freq Frequency of the clock source of UART, in Hz.
+ *
+ * @return None
+ */
+FORCE_INLINE_ATTR void lp_uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq)
+{
+#define DIV_UP(a, b)    (((a) + (b) - 1) / (b))
+    const uint32_t max_div = BIT(12) - 1;   // UART divider integer part only has 12 bits
+    uint32_t sclk_div = DIV_UP(sclk_freq, (uint64_t)max_div * baud);
+
+    if (sclk_div == 0) abort();
+
+    uint32_t clk_div = ((sclk_freq) << 4) / (baud * sclk_div);
+    // The baud rate configuration register is divided into
+    // an integer part and a fractional part.
+    hw->clkdiv_sync.clkdiv_int = clk_div >> 4;
+    hw->clkdiv_sync.clkdiv_frag = clk_div & 0xf;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clk_conf, sclk_div_num, sclk_div - 1);
+    uart_ll_update(hw);
+}
+
 /**
  * @brief Enable bus clock for the LP UART module
  *
@@ -161,17 +201,68 @@ static inline void lp_uart_ll_reset_register(int hw_id)
 #define lp_uart_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; lp_uart_ll_reset_register(__VA_ARGS__)
 
 /*************************************** General LL functions ******************************************/
+
 /**
- * @brief Sync the update to UART core clock domain
+ * @brief Check if UART is enabled or disabled.
  *
- * @param hw Beginning address of the peripheral registers.
+ * @param uart_num UART port number, the max port number is (UART_NUM_MAX -1).
  *
- * @return None.
+ * @return true: enabled; false: disabled
  */
-FORCE_INLINE_ATTR void uart_ll_update(uart_dev_t *hw)
+FORCE_INLINE_ATTR bool uart_ll_is_enabled(uint32_t uart_num)
 {
-    hw->reg_update.reg_update = 1;
-    while (hw->reg_update.reg_update);
+    HAL_ASSERT(uart_num < SOC_UART_HP_NUM);
+    uint32_t uart_clk_config_reg = ((uart_num == 0) ? PCR_UART0_CONF_REG :
+                                    (uart_num == 1) ? PCR_UART1_CONF_REG : 0);
+    uint32_t uart_rst_bit = ((uart_num == 0) ? PCR_UART0_RST_EN :
+                            (uart_num == 1) ? PCR_UART1_RST_EN : 0);
+    uint32_t uart_en_bit  = ((uart_num == 0) ? PCR_UART0_CLK_EN :
+                            (uart_num == 1) ? PCR_UART1_CLK_EN : 0);
+    return REG_GET_BIT(uart_clk_config_reg, uart_rst_bit) == 0 &&
+        REG_GET_BIT(uart_clk_config_reg, uart_en_bit) != 0;
+}
+
+/**
+ * @brief Enable the bus clock for uart
+ * @param uart_num UART port number, the max port number is (UART_NUM_MAX -1).
+ * @param enable true to enable, false to disable
+ */
+static inline void uart_ll_enable_bus_clock(uart_port_t uart_num, bool enable)
+{
+    switch (uart_num) {
+    case 0:
+        PCR.uart0_conf.uart0_clk_en = enable;
+        break;
+    case 1:
+        PCR.uart1_conf.uart1_clk_en = enable;
+        break;
+    default:
+        // LP_UART
+        abort();
+        break;
+    }
+}
+
+/**
+ * @brief Reset UART module
+ * @param uart_num UART port number, the max port number is (UART_NUM_MAX -1).
+ */
+static inline void uart_ll_reset_register(uart_port_t uart_num)
+{
+    switch (uart_num) {
+    case 0:
+        PCR.uart0_conf.uart0_rst_en = 1;
+        PCR.uart0_conf.uart0_rst_en = 0;
+        break;
+    case 1:
+        PCR.uart1_conf.uart1_rst_en = 1;
+        PCR.uart1_conf.uart1_rst_en = 0;
+        break;
+    default:
+        // LP_UART
+        abort();
+        break;
+    }
 }
 
 /**
@@ -315,7 +406,7 @@ FORCE_INLINE_ATTR void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint3
     hw->clkdiv_sync.clkdiv_int = clk_div >> 4;
     hw->clkdiv_sync.clkdiv_frag = clk_div & 0xf;
     if ((hw) == &LP_UART) {
-        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clk_conf, sclk_div_num, sclk_div - 1);
+        abort();
     } else {
         UART_LL_PCR_REG_U32_SET(hw, sclk_conf, sclk_div_num, sclk_div - 1);
     }

components/hal/esp32h2/include/hal/clk_gate_ll.h

@@ -394,19 +394,6 @@ static inline void periph_ll_wifi_module_disable_clk_set_rst(void)
     // DPORT_SET_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG, 0);
 }
 
-FORCE_INLINE_ATTR bool periph_ll_uart_enabled(uint32_t uart_num)
-{
-    HAL_ASSERT(uart_num < SOC_UART_HP_NUM);
-    uint32_t uart_clk_config_reg = ((uart_num == 0) ? PCR_UART0_CONF_REG :
-                                    (uart_num == 1) ? PCR_UART1_CONF_REG : 0);
-    uint32_t uart_rst_bit = ((uart_num == 0) ? PCR_UART0_RST_EN :
-                            (uart_num == 1) ? PCR_UART1_RST_EN : 0);
-    uint32_t uart_en_bit  = ((uart_num == 0) ? PCR_UART0_CLK_EN :
-                            (uart_num == 1) ? PCR_UART1_CLK_EN : 0);
-    return REG_GET_BIT(uart_clk_config_reg, uart_rst_bit) == 0 &&
-        REG_GET_BIT(uart_clk_config_reg, uart_en_bit) != 0;
-}
-
 #ifdef __cplusplus
 }
 #endif

components/hal/esp32h2/include/hal/uart_ll.h

@@ -17,6 +17,7 @@
 #include "soc/uart_reg.h"
 #include "soc/uart_struct.h"
 #include "soc/pcr_struct.h"
+#include "soc/pcr_reg.h"
 #include "esp_attr.h"
 
 #ifdef __cplusplus
@@ -80,6 +81,66 @@ typedef enum {
     UART_INTR_WAKEUP           = (0x1 << 19),
 } uart_intr_t;
 
+/**
+ * @brief Check if UART is enabled or disabled.
+ *
+ * @param uart_num UART port number, the max port number is (UART_NUM_MAX -1).
+ *
+ * @return true: enabled; false: disabled
+ */
+FORCE_INLINE_ATTR bool uart_ll_is_enabled(uint32_t uart_num)
+{
+    uint32_t uart_clk_config_reg = ((uart_num == 0) ? PCR_UART0_CONF_REG :
+                                    (uart_num == 1) ? PCR_UART1_CONF_REG : 0);
+    uint32_t uart_rst_bit = ((uart_num == 0) ? PCR_UART0_RST_EN :
+                            (uart_num == 1) ? PCR_UART1_RST_EN : 0);
+    uint32_t uart_en_bit  = ((uart_num == 0) ? PCR_UART0_CLK_EN :
+                            (uart_num == 1) ? PCR_UART1_CLK_EN : 0);
+    return REG_GET_BIT(uart_clk_config_reg, uart_rst_bit) == 0 &&
+        REG_GET_BIT(uart_clk_config_reg, uart_en_bit) != 0;
+}
+
+/**
+ * @brief Enable the bus clock for uart
+ * @param uart_num UART port number, the max port number is (UART_NUM_MAX -1).
+ * @param enable true to enable, false to disable
+ */
+static inline void uart_ll_enable_bus_clock(uart_port_t uart_num, bool enable)
+{
+    switch (uart_num) {
+    case 0:
+        PCR.uart0_conf.uart0_clk_en = enable;
+        break;
+    case 1:
+        PCR.uart1_conf.uart1_clk_en = enable;
+        break;
+    default:
+        abort();
+        break;
+    }
+}
+
+/**
+ * @brief Reset UART module
+ * @param uart_num UART port number, the max port number is (UART_NUM_MAX -1).
+ */
+static inline void uart_ll_reset_register(uart_port_t uart_num)
+{
+    switch (uart_num) {
+    case 0:
+        PCR.uart0_conf.uart0_rst_en = 1;
+        PCR.uart0_conf.uart0_rst_en = 0;
+        break;
+    case 1:
+        PCR.uart1_conf.uart1_rst_en = 1;
+        PCR.uart1_conf.uart1_rst_en = 0;
+        break;
+    default:
+        abort();
+        break;
+    }
+}
+
 /**
  * @brief Sync the update to UART core clock domain
  *

components/hal/esp32p4/include/hal/clk_gate_ll.h

@@ -38,16 +38,6 @@ static inline uint32_t periph_ll_get_clk_en_mask(periph_module_t periph)
         return HP_SYS_CLKRST_REG_I2C1_APB_CLK_EN;
     case PERIPH_LCD_MODULE:
         return HP_SYS_CLKRST_REG_LCD_CLK_EN;
-    case PERIPH_UART0_MODULE:
-        return HP_SYS_CLKRST_REG_UART0_CLK_EN;
-    case PERIPH_UART1_MODULE:
-        return HP_SYS_CLKRST_REG_UART1_CLK_EN;
-    case PERIPH_UART2_MODULE:
-        return HP_SYS_CLKRST_REG_UART2_CLK_EN;
-    case PERIPH_UART3_MODULE:
-        return HP_SYS_CLKRST_REG_UART3_CLK_EN;
-    case PERIPH_UART4_MODULE:
-        return HP_SYS_CLKRST_REG_UART4_CLK_EN;
     case PERIPH_TWAI0_MODULE:
         return HP_SYS_CLKRST_REG_TWAI0_CLK_EN;
     case PERIPH_TWAI1_MODULE:
@@ -119,16 +109,6 @@ static inline uint32_t periph_ll_get_rst_en_mask(periph_module_t periph, bool en
         return HP_SYS_CLKRST_REG_RST_EN_PPA;
     case PERIPH_SYSTIMER_MODULE:
         return HP_SYS_CLKRST_REG_RST_EN_STIMER;
-    case PERIPH_UART0_MODULE:
-        return HP_SYS_CLKRST_REG_RST_EN_UART0_CORE;
-    case PERIPH_UART1_MODULE:
-        return HP_SYS_CLKRST_REG_RST_EN_UART1_CORE;
-    case PERIPH_UART2_MODULE:
-        return HP_SYS_CLKRST_REG_RST_EN_UART2_CORE;
-    case PERIPH_UART3_MODULE:
-        return HP_SYS_CLKRST_REG_RST_EN_UART3_CORE;
-    case PERIPH_UART4_MODULE:
-        return HP_SYS_CLKRST_REG_RST_EN_UART4_CORE;
     case PERIPH_UHCI_MODULE:
         return HP_SYS_CLKRST_REG_RST_EN_UHCI;
     case PERIPH_I3C_MODULE:
@@ -210,16 +190,6 @@ static inline uint32_t periph_ll_get_clk_en_reg(periph_module_t periph)
         return HP_SYS_CLKRST_SOC_CLK_CTRL2_REG;
     case PERIPH_LCD_MODULE:
         return HP_SYS_CLKRST_PERI_CLK_CTRL110_REG;
-    case PERIPH_UART0_MODULE:
-        return HP_SYS_CLKRST_PERI_CLK_CTRL111_REG;
-    case PERIPH_UART1_MODULE:
-        return HP_SYS_CLKRST_PERI_CLK_CTRL112_REG;
-    case PERIPH_UART2_MODULE:
-        return HP_SYS_CLKRST_PERI_CLK_CTRL113_REG;
-    case PERIPH_UART3_MODULE:
-        return HP_SYS_CLKRST_PERI_CLK_CTRL114_REG;
-    case PERIPH_UART4_MODULE:
-        return HP_SYS_CLKRST_PERI_CLK_CTRL115_REG;
     case PERIPH_TWAI0_MODULE:
     case PERIPH_TWAI1_MODULE:
     case PERIPH_TWAI2_MODULE:
@@ -268,11 +238,6 @@ static inline uint32_t periph_ll_get_rst_en_reg(periph_module_t periph)
         return HP_SYS_CLKRST_HP_RST_EN0_REG;
     case PERIPH_PPA_MODULE:
     case PERIPH_SYSTIMER_MODULE:
-    case PERIPH_UART0_MODULE:
-    case PERIPH_UART1_MODULE:
-    case PERIPH_UART2_MODULE:
-    case PERIPH_UART3_MODULE:
-    case PERIPH_UART4_MODULE:
     case PERIPH_UHCI_MODULE:
     case PERIPH_I3C_MODULE:
     case PERIPH_I2C0_MODULE:

components/hal/esp32s2/include/hal/clk_gate_ll.h

@@ -279,17 +279,6 @@ static inline void periph_ll_wifi_module_disable_clk_set_rst(void)
     DPORT_SET_PERI_REG_MASK(DPORT_CORE_RST_EN_REG, 0);
 }
 
-FORCE_INLINE_ATTR bool periph_ll_uart_enabled(uint32_t uart_num)
-{
-    HAL_ASSERT(uart_num < SOC_UART_HP_NUM);
-    uint32_t uart_rst_bit = ((uart_num == 0) ? DPORT_UART_RST :
-                            (uart_num == 1) ? DPORT_UART1_RST : 0);
-    uint32_t uart_en_bit  = ((uart_num == 0) ? DPORT_UART_CLK_EN :
-                            (uart_num == 1) ? DPORT_UART1_CLK_EN : 0);
-    return DPORT_REG_GET_BIT(DPORT_PERIP_RST_EN_REG, uart_rst_bit) == 0 &&
-        DPORT_REG_GET_BIT(DPORT_PERIP_CLK_EN_REG, uart_en_bit) != 0;
-}
-
 #ifdef __cplusplus
 }
 #endif

components/hal/esp32s2/include/hal/uart_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -15,6 +15,8 @@
 #include "hal/uart_types.h"
 #include "soc/uart_reg.h"
 #include "soc/uart_struct.h"
+#include "soc/system_reg.h"
+#include "soc/dport_reg.h"
 #include "esp_attr.h"
 
 #ifdef __cplusplus
@@ -53,6 +55,71 @@ typedef enum {
     UART_INTR_WAKEUP           = (0x1 << 19),
 } uart_intr_t;
 
+/**
+ * @brief Check if UART is enabled or disabled.
+ *
+ * @param uart_num UART port number, the max port number is (UART_NUM_MAX -1).
+ *
+ * @return true: enabled; false: disabled
+ */
+FORCE_INLINE_ATTR bool uart_ll_is_enabled(uint32_t uart_num)
+{
+    uint32_t uart_rst_bit = ((uart_num == 0) ? DPORT_UART_RST :
+                            (uart_num == 1) ? DPORT_UART1_RST : 0);
+    uint32_t uart_en_bit  = ((uart_num == 0) ? DPORT_UART_CLK_EN :
+                            (uart_num == 1) ? DPORT_UART1_CLK_EN : 0);
+    return DPORT_REG_GET_BIT(DPORT_PERIP_RST_EN_REG, uart_rst_bit) == 0 &&
+        DPORT_REG_GET_BIT(DPORT_PERIP_CLK_EN_REG, uart_en_bit) != 0;
+}
+
+/**
+ * @brief Enable the bus clock for uart
+ * @param uart_num UART port number, the max port number is (UART_NUM_MAX -1).
+ * @param enable true to enable, false to disable
+ */
+static inline void uart_ll_enable_bus_clock(uart_port_t uart_num, bool enable)
+{
+    uint32_t reg_val = READ_PERI_REG(DPORT_PERIP_CLK_EN0_REG);
+    switch (uart_num) {
+    case 0:
+        reg_val = reg_val & (~DPORT_UART_CLK_EN);
+        reg_val = reg_val | (enable << DPORT_UART_CLK_EN_S);
+        break;
+    case 1:
+        reg_val = reg_val & (~DPORT_UART1_CLK_EN);
+        reg_val = reg_val | (enable << DPORT_UART1_CLK_EN_S);
+        break;
+    default:
+        abort();
+        break;
+    }
+    WRITE_PERI_REG(DPORT_PERIP_CLK_EN0_REG, reg_val);
+}
+#define uart_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; uart_ll_enable_bus_clock(__VA_ARGS__)
+
+/**
+ * @brief Reset UART module
+ * @param uart_num UART port number, the max port number is (UART_NUM_MAX -1).
+ */
+static inline void uart_ll_reset_register(uart_port_t uart_num)
+{
+    switch (uart_num) {
+    case 0:
+        DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_UART_RST);
+        DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_UART_RST);
+        break;
+    case 1:
+        DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_UART1_RST);
+        DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_UART1_RST);
+        break;
+    default:
+        abort();
+        break;
+    }
+}
+// SYSTEM.perip_rst_enx are shared registers, so this function must be used in an atomic way
+#define uart_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; uart_ll_reset_register(__VA_ARGS__)
+
 /**
  * @brief  Set the UART source clock.
  *

components/hal/esp32s3/include/hal/clk_gate_ll.h

@@ -300,19 +300,6 @@ static inline void periph_ll_wifi_module_disable_clk_set_rst(void)
     DPORT_SET_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG, 0);
 }
 
-FORCE_INLINE_ATTR bool periph_ll_uart_enabled(uint32_t uart_num)
-{
-    HAL_ASSERT(uart_num < SOC_UART_HP_NUM);
-    uint32_t uart_rst_bit = ((uart_num == 0) ? SYSTEM_UART_RST :
-                            (uart_num == 1) ? SYSTEM_UART1_RST :
-                            (uart_num == 2) ? SYSTEM_UART2_RST : 0);
-    uint32_t uart_en_bit  = ((uart_num == 0) ? SYSTEM_UART_CLK_EN :
-                            (uart_num == 1) ? SYSTEM_UART1_CLK_EN :
-                            (uart_num == 2) ? SYSTEM_UART2_CLK_EN : 0);
-    return DPORT_REG_GET_BIT(SYSTEM_PERIP_RST_EN0_REG, uart_rst_bit) == 0 &&
-        DPORT_REG_GET_BIT(SYSTEM_PERIP_CLK_EN0_REG, uart_en_bit) != 0;
-}
-
 #ifdef __cplusplus
 }
 #endif

components/hal/esp32s3/include/hal/uart_ll.h

@@ -15,6 +15,9 @@
 #include "hal/uart_types.h"
 #include "soc/uart_reg.h"
 #include "soc/uart_struct.h"
+#include "soc/system_struct.h"
+#include "soc/system_reg.h"
+#include "soc/dport_access.h"
 #include "esp_attr.h"
 
 #ifdef __cplusplus
@@ -56,6 +59,77 @@ typedef enum {
     UART_INTR_WAKEUP           = (0x1 << 19),
 } uart_intr_t;
 
+/**
+ * @brief Check if UART is enabled or disabled.
+ *
+ * @param uart_num UART port number, the max port number is (UART_NUM_MAX -1).
+ *
+ * @return true: enabled; false: disabled
+ */
+FORCE_INLINE_ATTR bool uart_ll_is_enabled(uint32_t uart_num)
+{
+    uint32_t uart_rst_bit = ((uart_num == 0) ? SYSTEM_UART_RST :
+                            (uart_num == 1) ? SYSTEM_UART1_RST :
+                            (uart_num == 2) ? SYSTEM_UART2_RST : 0);
+    uint32_t uart_en_bit  = ((uart_num == 0) ? SYSTEM_UART_CLK_EN :
+                            (uart_num == 1) ? SYSTEM_UART1_CLK_EN :
+                            (uart_num == 2) ? SYSTEM_UART2_CLK_EN : 0);
+    return DPORT_REG_GET_BIT(SYSTEM_PERIP_RST_EN0_REG, uart_rst_bit) == 0 &&
+        DPORT_REG_GET_BIT(SYSTEM_PERIP_CLK_EN0_REG, uart_en_bit) != 0;
+}
+
+/**
+ * @brief Enable the bus clock for uart
+ * @param uart_num UART port number, the max port number is (UART_NUM_MAX -1).
+ * @param enable true to enable, false to disable
+ */
+static inline void uart_ll_enable_bus_clock(uart_port_t uart_num, bool enable)
+{
+    switch (uart_num) {
+    case 0:
+        SYSTEM.perip_clk_en0.uart_clk_en = enable;
+        break;
+    case 1:
+        SYSTEM.perip_clk_en0.uart1_clk_en = enable;
+        break;
+    case 2:
+        SYSTEM.perip_clk_en1.uart2_clk_en = enable;
+        break;
+    default:
+        abort();
+        break;
+    }
+}
+// SYSTEM.perip_clk_enx are shared registers, so this function must be used in an atomic way
+#define uart_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; uart_ll_enable_bus_clock(__VA_ARGS__)
+
+/**
+ * @brief Reset UART module
+ * @param uart_num UART port number, the max port number is (UART_NUM_MAX -1).
+ */
+static inline void uart_ll_reset_register(uart_port_t uart_num)
+{
+    switch (uart_num) {
+    case 0:
+        SYSTEM.perip_rst_en0.uart_rst = 1;
+        SYSTEM.perip_rst_en0.uart_rst = 0;
+        break;
+    case 1:
+        SYSTEM.perip_rst_en0.uart1_rst = 1;
+        SYSTEM.perip_rst_en0.uart1_rst = 0;
+        break;
+    case 2:
+        SYSTEM.perip_rst_en1.uart2_rst = 1;
+        SYSTEM.perip_rst_en1.uart2_rst = 0;
+        break;
+    default:
+        abort();
+        break;
+    }
+}
+// SYSTEM.perip_rst_enx are shared registers, so this function must be used in an atomic way
+#define uart_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; uart_ll_reset_register(__VA_ARGS__)
+
 /**
  * @brief  Configure the UART core reset.
  *

components/hal/include/hal/uart_hal.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -29,6 +29,26 @@ typedef struct {
     uart_dev_t *dev;
 } uart_hal_context_t;
 
+/**
+ * @brief  Configure the UART baud-rate and select the source clock
+ *
+ * @param  hal Context of the HAL layer
+ * @param  baud_rate The baud-rate to be set
+ * @param  sclk_freq Frequency of the clock source of UART, in Hz.
+ *
+ * @return None
+ */
+#define uart_hal_set_baudrate(hal, baud_rate, sclk_freq) uart_ll_set_baudrate((hal)->dev, baud_rate, sclk_freq)
+
+/**
+ * @brief Set the UART source clock type
+ * @param  hal Context of the HAL layer
+ * @param  sclk The UART source clock type.
+ *
+ * @return None
+ */
+#define uart_hal_set_sclk(hal, sclk) uart_ll_set_sclk((hal)->dev, sclk);
+
 /**
  * @brief Clear the UART interrupt status
  *
@@ -188,15 +208,6 @@ void uart_hal_rxfifo_rst(uart_hal_context_t *hal);
  */
 void uart_hal_init(uart_hal_context_t *hal, uart_port_t uart_num);
 
-/**
- * @brief Set the UART source clock type
- * @param  hal Context of the HAL layer
- * @param  sclk The UART source clock type.
- *
- * @return None
- */
-void uart_hal_set_sclk(uart_hal_context_t *hal, soc_module_clk_t sclk);
-
 /**
  * @brief Get the UART source clock type
  *
@@ -207,17 +218,6 @@ void uart_hal_set_sclk(uart_hal_context_t *hal, soc_module_clk_t sclk);
  */
 void uart_hal_get_sclk(uart_hal_context_t *hal, soc_module_clk_t *sclk);
 
-/**
- * @brief  Configure the UART baud-rate and select the source clock
- *
- * @param  hal Context of the HAL layer
- * @param  baud_rate The baud-rate to be set
- * @param  sclk_freq Frequency of the clock source of UART, in Hz.
- *
- * @return None
- */
-void uart_hal_set_baudrate(uart_hal_context_t *hal, uint32_t baud_rate, uint32_t sclk_freq);
-
 /**
  * @brief  Configure the UART stop bit
  *

components/hal/include/hal/uart_types.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -25,6 +25,12 @@ typedef enum {
 #if SOC_UART_HP_NUM > 2
     UART_NUM_2,                         /*!< UART port 2 */
 #endif
+#if SOC_UART_HP_NUM > 3
+    UART_NUM_3,                         /*!< UART port 3 */
+#endif
+#if SOC_UART_HP_NUM > 4
+    UART_NUM_4,                         /*!< UART port 4 */
+#endif
 #if (SOC_UART_LP_NUM >= 1)
     LP_UART_NUM_0,                      /*!< LP UART port 0 */
 #endif

components/hal/uart_hal.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -8,21 +8,11 @@
 #include "hal/uart_hal.h"
 #include "soc/soc_caps.h"
 
-void uart_hal_set_sclk(uart_hal_context_t *hal, soc_module_clk_t sclk)
-{
-    uart_ll_set_sclk(hal->dev, sclk);
-}
-
 void uart_hal_get_sclk(uart_hal_context_t *hal, soc_module_clk_t *sclk)
 {
     uart_ll_get_sclk(hal->dev, sclk);
 }
 
-void uart_hal_set_baudrate(uart_hal_context_t *hal, uint32_t baud_rate, uint32_t sclk_freq)
-{
-    uart_ll_set_baudrate(hal->dev, baud_rate, sclk_freq);
-}
-
 void uart_hal_get_baudrate(uart_hal_context_t *hal, uint32_t *baud_rate, uint32_t sclk_freq)
 {
     *baud_rate = uart_ll_get_baudrate(hal->dev, sclk_freq);

components/soc/esp32c3/include/soc/system_reg.h

@@ -1,16 +1,8 @@
-// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 #ifndef _SOC_SYSTEM_REG_H_
 #define _SOC_SYSTEM_REG_H_
 
@@ -282,12 +274,6 @@ extern "C" {
 #define SYSTEM_TSENS_CLK_EN_M  (BIT(10))
 #define SYSTEM_TSENS_CLK_EN_V  0x1
 #define SYSTEM_TSENS_CLK_EN_S  10
-/* SYSTEM_UART2_CLK_EN : R/W ;bitpos:[9] ;default: 1'b1 ; */
-/*description: */
-#define SYSTEM_UART2_CLK_EN  (BIT(9))
-#define SYSTEM_UART2_CLK_EN_M  (BIT(9))
-#define SYSTEM_UART2_CLK_EN_V  0x1
-#define SYSTEM_UART2_CLK_EN_S  9
 /* SYSTEM_LCD_CAM_CLK_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */
 /*description: */
 #define SYSTEM_LCD_CAM_CLK_EN  (BIT(8))
@@ -538,12 +524,6 @@ extern "C" {
 #define SYSTEM_TSENS_RST_M  (BIT(10))
 #define SYSTEM_TSENS_RST_V  0x1
 #define SYSTEM_TSENS_RST_S  10
-/* SYSTEM_UART2_RST : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: */
-#define SYSTEM_UART2_RST  (BIT(9))
-#define SYSTEM_UART2_RST_M  (BIT(9))
-#define SYSTEM_UART2_RST_V  0x1
-#define SYSTEM_UART2_RST_S  9
 /* SYSTEM_LCD_CAM_RST : R/W ;bitpos:[8] ;default: 1'b1 ; */
 /*description: */
 #define SYSTEM_LCD_CAM_RST  (BIT(8))

components/soc/esp32c3/include/soc/system_struct.h

@@ -1,16 +1,8 @@
-// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 #ifndef _SOC_SYSTEM_STRUCT_H_
 #define _SOC_SYSTEM_STRUCT_H_
 
@@ -104,7 +96,7 @@ typedef volatile struct system_dev_s {
             uint32_t reg_dma_clk_en                :    1;  /*reg_dma_clk_en*/
             uint32_t reg_sdio_host_clk_en          :    1;  /*reg_sdio_host_clk_en*/
             uint32_t reg_lcd_cam_clk_en            :    1;  /*reg_lcd_cam_clk_en*/
-            uint32_t reg_uart2_clk_en              :    1;  /*reg_uart2_clk_en*/
+            uint32_t reserved9                     :    1;  /*reserved*/
             uint32_t reg_tsens_clk_en              :    1;  /*reg_tsens_clk_en*/
             uint32_t reserved11                    :    21;  /*reserved*/
         };
@@ -158,7 +150,7 @@ typedef volatile struct system_dev_s {
             uint32_t reg_dma_rst                   :    1;  /*reg_dma_rst*/
             uint32_t reg_sdio_host_rst             :    1;  /*reg_sdio_host_rst*/
             uint32_t reg_lcd_cam_rst               :    1;  /*reg_lcd_cam_rst*/
-            uint32_t reg_uart2_rst                 :    1;  /*reg_uart2_rst*/
+            uint32_t reserved9                     :    1;  /*reserved*/
             uint32_t reg_tsens_rst                 :    1;  /*reg_tsens_rst*/
             uint32_t reserved11                    :    21;  /*reserved*/
         };

components/soc/esp32c6/include/soc/Kconfig.soc_caps.in

@@ -203,6 +203,10 @@ config SOC_LP_I2C_SUPPORTED
     bool
     default y
 
+config SOC_ULP_LP_UART_SUPPORTED
+    bool
+    default y
+
 config SOC_CLK_TREE_SUPPORTED
     bool
     default y

components/soc/esp32c6/include/soc/soc_caps.h

@@ -75,6 +75,7 @@
 #define SOC_LP_AON_SUPPORTED            1
 #define SOC_LP_PERIPHERALS_SUPPORTED    1
 #define SOC_LP_I2C_SUPPORTED            1
+#define SOC_ULP_LP_UART_SUPPORTED       1
 #define SOC_CLK_TREE_SUPPORTED          1
 #define SOC_ASSIST_DEBUG_SUPPORTED      1
 

components/soc/esp32p4/include/soc/Kconfig.soc_caps.in

@@ -1037,16 +1037,24 @@ config SOC_FLASH_ENCRYPTION_XTS_AES_128
 
 config SOC_UART_NUM
     int
-    default 2
+    default 6
 
 config SOC_UART_HP_NUM
     int
-    default 2
+    default 5
+
+config SOC_UART_LP_NUM
+    int
+    default 1
 
 config SOC_UART_FIFO_LEN
     int
     default 128
 
+config SOC_LP_UART_FIFO_LEN
+    int
+    default 16
+
 config SOC_UART_BITRATE_MAX
     int
     default 5000000

components/soc/esp32p4/include/soc/clk_tree_defs.h

@@ -151,6 +151,9 @@ typedef enum {
     SOC_MOD_CLK_RC_FAST,                       /*!< RC_FAST_CLK comes from the internal 20MHz rc oscillator, passing a clock gating to the peripherals */
     SOC_MOD_CLK_XTAL,                          /*!< XTAL_CLK comes from the external 40MHz crystal */
     SOC_MOD_CLK_APLL,                          /*!< Audio PLL is sourced from PLL, and its frequency is configurable through APLL configuration registers */
+    // For LP peripherals
+    SOC_MOD_CLK_XTAL_D2,                       /*!< XTAL_D2_CLK comes from the external 40MHz crystal, passing a div of 2 to the LP peripherals */
+    SOC_MOD_CLK_LP_PLL,                        /*!< LP_PLL is from 32kHz XTAL oscillator frequency multipliers, it has a fixed frequency of 8MHz */
     SOC_MOD_CLK_INVALID,                       /*!< Indication of the end of the available module clock sources */
 } soc_module_clk_t;
 
@@ -254,7 +257,6 @@ typedef enum {
 
 ///////////////////////////////////////////////////UART/////////////////////////////////////////////////////////////////
 
-//TODO: IDF-6511
 /**
  * @brief Type of UART clock source, reserved for the legacy UART driver
  */
@@ -262,9 +264,28 @@ typedef enum {
     UART_SCLK_PLL_F80M = SOC_MOD_CLK_PLL_F80M,           /*!< UART source clock is PLL_F80M */
     UART_SCLK_RTC = SOC_MOD_CLK_RC_FAST,                /*!< UART source clock is RC_FAST */
     UART_SCLK_XTAL = SOC_MOD_CLK_XTAL,                  /*!< UART source clock is XTAL */
+#if SOC_CLK_TREE_SUPPORTED
     UART_SCLK_DEFAULT = SOC_MOD_CLK_PLL_F80M,           /*!< UART source clock default choice is PLL_F80M */
+#else
+    UART_SCLK_DEFAULT = SOC_MOD_CLK_XTAL,               /*!< UART source clock default choice is XTAL for FPGA environment */
+#endif
 } soc_periph_uart_clk_src_legacy_t;
 
+/**
+ * @brief Type of LP_UART clock source
+ */
+typedef enum {
+    LP_UART_SCLK_LP_FAST = SOC_MOD_CLK_RTC_FAST,        /*!< LP_UART source clock is LP(RTC)_FAST */
+    LP_UART_SCLK_XTAL_D2 = SOC_MOD_CLK_XTAL_D2,         /*!< LP_UART source clock is XTAL_D2 */
+    LP_UART_SCLK_LP_PLL  = SOC_MOD_CLK_LP_PLL,          /*!< LP_UART source clock is LP_PLL (8M PLL) */
+#if SOC_CLK_TREE_SUPPORTED
+    LP_UART_SCLK_DEFAULT = SOC_MOD_CLK_RTC_FAST,
+#else
+    LP_UART_SCLK_DEFAULT = SOC_MOD_CLK_XTAL_D2,         /*!< LP_UART source clock default choice is XTAL_D2 */
+#endif
+
+} soc_periph_lp_uart_clk_src_t;
+
 //////////////////////////////////////////////////MCPWM/////////////////////////////////////////////////////////////////
 
 /**

components/soc/esp32p4/include/soc/lpperi_struct.h

@@ -348,7 +348,7 @@ typedef union {
 } lpperi_date_reg_t;
 
 
-typedef struct {
+typedef struct lpperi_dev_t {
     volatile lpperi_clk_en_reg_t clk_en;
     volatile lpperi_core_clk_sel_reg_t core_clk_sel;
     volatile lpperi_reset_en_reg_t reset_en;
@@ -364,6 +364,7 @@ typedef struct {
     volatile lpperi_date_reg_t date;
 } lpperi_dev_t;
 
+extern lpperi_dev_t LPPERI;
 
 #ifndef __cplusplus
 _Static_assert(sizeof(lpperi_dev_t) == 0x400, "Invalid size of lpperi_dev_t structure");

components/soc/esp32p4/include/soc/soc_caps.h

@@ -72,6 +72,7 @@
 // #define SOC_PMU_SUPPORTED               1  //TODO: IDF-7531
 // #define SOC_PAU_SUPPORTED               1  //TODO: IDF-7531
 // #define SOC_LP_TIMER_SUPPORTED          1  //TODO: IDF-7532
+// #define SOC_ULP_LP_UART_SUPPORTED       1  //TODO: IDF-7533
 #define SOC_LP_GPIO_MATRIX_SUPPORTED    1
 #define SOC_LP_PERIPHERALS_SUPPORTED    1
 #define SOC_SPIRAM_SUPPORTED            1
@@ -470,11 +471,12 @@
 /*-------------------------- MEMPROT CAPS ------------------------------------*/
 
 /*-------------------------- UART CAPS ---------------------------------------*/
-// ESP32-P4 has 2 UARTs
-#define SOC_UART_NUM                    (2)
-#define SOC_UART_HP_NUM                 (2)
-// #define SOC_UART_LP_NUM                 (1U)
+// ESP32-P4 has 6 UARTs (5 HP UART, and 1 LP UART)
+#define SOC_UART_NUM                    (6)
+#define SOC_UART_HP_NUM                 (5)
+#define SOC_UART_LP_NUM                 (1U)
 #define SOC_UART_FIFO_LEN               (128)       /*!< The UART hardware FIFO length */
+#define SOC_LP_UART_FIFO_LEN            (16)        /*!< The LP UART hardware FIFO length */
 #define SOC_UART_BITRATE_MAX            (5000000)   /*!< Max bit rate supported by UART */
 #define SOC_UART_SUPPORT_PLL_F80M_CLK   (1)         /*!< Support PLL_F80M as the clock source */
 #define SOC_UART_SUPPORT_RTC_CLK        (1)         /*!< Support RTC clock as the clock source */

components/soc/esp32p4/include/soc/uart_channel.h

@@ -4,6 +4,36 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-// This file defines GPIO lookup macros for available UART IO_MUX pins on ESP32C6.
+// This file defines GPIO lookup macros for available UART IO_MUX pins on ESP32P4.
 
 #pragma once
+
+//UART0 channels
+#define UART_GPIO37_DIRECT_CHANNEL      UART_NUM_0
+#define UART_NUM_0_TXD_DIRECT_GPIO_NUM  37
+#define UART_GPIO38_DIRECT_CHANNEL      UART_NUM_0
+#define UART_NUM_0_RXD_DIRECT_GPIO_NUM  38
+#define UART_GPIO8_DIRECT_CHANNEL      UART_NUM_0
+#define UART_NUM_0_RTS_DIRECT_GPIO_NUM  8
+#define UART_GPIO9_DIRECT_CHANNEL      UART_NUM_0
+#define UART_NUM_0_CTS_DIRECT_GPIO_NUM  9
+
+#define UART_TXD_GPIO37_DIRECT_CHANNEL  UART_GPIO38_DIRECT_CHANNEL
+#define UART_RXD_GPIO38_DIRECT_CHANNEL  UART_GPIO38_DIRECT_CHANNEL
+#define UART_RTS_GPIO8_DIRECT_CHANNEL   UART_GPIO8_DIRECT_CHANNEL
+#define UART_CTS_GPIO9_DIRECT_CHANNEL   UART_GPIO9_DIRECT_CHANNEL
+
+//UART1 channels
+#define UART_GPIO10_DIRECT_CHANNEL      UART_NUM_1
+#define UART_NUM_1_TXD_DIRECT_GPIO_NUM  10
+#define UART_GPIO11_DIRECT_CHANNEL      UART_NUM_1
+#define UART_NUM_1_RXD_DIRECT_GPIO_NUM  11
+#define UART_GPIO12_DIRECT_CHANNEL      UART_NUM_1
+#define UART_NUM_1_RTS_DIRECT_GPIO_NUM  12
+#define UART_GPIO13_DIRECT_CHANNEL      UART_NUM_1
+#define UART_NUM_1_CTS_DIRECT_GPIO_NUM  13
+
+#define UART_TXD_GPIO10_DIRECT_CHANNEL  UART_GPIO10_DIRECT_CHANNEL
+#define UART_RXD_GPIO11_DIRECT_CHANNEL  UART_GPIO11_DIRECT_CHANNEL
+#define UART_RTS_GPIO12_DIRECT_CHANNEL  UART_GPIO12_DIRECT_CHANNEL
+#define UART_CTS_GPIO13_DIRECT_CHANNEL  UART_GPIO13_DIRECT_CHANNEL

components/soc/esp32p4/include/soc/uart_pins.h

@@ -10,3 +10,68 @@
 
 /* Specify the number of pins for UART */
 #define SOC_UART_PINS_COUNT  (4)
+
+/* Specify the GPIO pin number for each UART signal in the IOMUX */
+#define U0RXD_GPIO_NUM 38
+#define U0TXD_GPIO_NUM 37
+#define U0RTS_GPIO_NUM 8
+#define U0CTS_GPIO_NUM 9
+
+#define U1RXD_GPIO_NUM 11
+#define U1TXD_GPIO_NUM 10
+#define U1RTS_GPIO_NUM 12
+#define U1CTS_GPIO_NUM 13
+
+#define U2RXD_GPIO_NUM (-1)
+#define U2TXD_GPIO_NUM (-1)
+#define U2RTS_GPIO_NUM (-1)
+#define U2CTS_GPIO_NUM (-1)
+
+#define U3RXD_GPIO_NUM (-1)
+#define U3TXD_GPIO_NUM (-1)
+#define U3RTS_GPIO_NUM (-1)
+#define U3CTS_GPIO_NUM (-1)
+
+#define U4RXD_GPIO_NUM (-1)
+#define U4TXD_GPIO_NUM (-1)
+#define U4RTS_GPIO_NUM (-1)
+#define U4CTS_GPIO_NUM (-1)
+
+#define LP_U0RXD_GPIO_NUM 15
+#define LP_U0TXD_GPIO_NUM 14
+#define LP_U0RTS_GPIO_NUM (-1)
+#define LP_U0CTS_GPIO_NUM (-1)
+
+/* The following defines are necessary for reconfiguring the UART
+ * to use IOMUX, at runtime. */
+#define U0TXD_MUX_FUNC  (FUNC_GPIO37_UART0_TXD_PAD)
+#define U0RXD_MUX_FUNC  (FUNC_GPIO38_UART0_RXD_PAD)
+#define U0RTS_MUX_FUNC  (FUNC_GPIO8_UART0_RTS_PAD)
+#define U0CTS_MUX_FUNC  (FUNC_GPIO9_UART0_CTS_PAD)
+
+/* Same goes for UART1 */
+#define U1TXD_MUX_FUNC  (FUNC_GPIO10_UART1_TXD_PAD)
+#define U1RXD_MUX_FUNC  (FUNC_GPIO11_UART1_RXD_PAD)
+#define U1RTS_MUX_FUNC  (FUNC_GPIO12_UART1_RTS_PAD)
+#define U1CTS_MUX_FUNC  (FUNC_GPIO13_UART1_CTS_PAD)
+
+/* No func for the following pins, they shall not be used */
+#define U2TXD_MUX_FUNC  (-1)
+#define U2RXD_MUX_FUNC  (-1)
+#define U2RTS_MUX_FUNC  (-1)
+#define U2CTS_MUX_FUNC  (-1)
+
+#define U3TXD_MUX_FUNC  (-1)
+#define U3RXD_MUX_FUNC  (-1)
+#define U3RTS_MUX_FUNC  (-1)
+#define U3CTS_MUX_FUNC  (-1)
+
+#define U4TXD_MUX_FUNC  (-1)
+#define U4RXD_MUX_FUNC  (-1)
+#define U4RTS_MUX_FUNC  (-1)
+#define U4CTS_MUX_FUNC  (-1)
+
+#define LP_U0TXD_MUX_FUNC  (0)
+#define LP_U0RXD_MUX_FUNC  (0)
+#define LP_U0RTS_MUX_FUNC  (-1)
+#define LP_U0CTS_MUX_FUNC  (-1)

components/soc/esp32p4/include/soc/uart_struct.h

@@ -19,8 +19,7 @@ typedef union {
         /** rxfifo_rd_byte : RO; bitpos: [7:0]; default: 0;
          *  UART $n accesses FIFO via this register.
          */
-        uint32_t rxfifo_rd_byte:8;
-        uint32_t reserved_8:24;
+        uint32_t rxfifo_rd_byte:32;
     };
     uint32_t val;
 } uart_fifo_reg_t;
@@ -881,7 +880,20 @@ typedef union {
  */
 typedef union {
     struct {
-        uint32_t reserved_0:24;
+        /** sclk_div_b : R/W; bitpos: [5:0]; default: 0;
+         *  The  denominator of the frequency divider factor.
+         */
+        uint32_t sclk_div_b:6;      //HP UART's sclk_div_b is in hp_sys_clkrst_struct.h
+        /** sclk_div_a : R/W; bitpos: [11:6]; default: 0;
+         *  The numerator of the frequency divider factor.
+         */
+        uint32_t sclk_div_a:6;      //HP UART's sclk_div_a is in hp_sys_clkrst_struct.h
+        /** sclk_div_num : R/W; bitpos: [19:12]; default: 1;
+         *  The integral part of the frequency divider factor.
+         *  It is only used by LP UART
+         */
+        uint32_t sclk_div_num:8;    //HP UART's sclk_div_num is in hp_sys_clkrst_struct.h
+        uint32_t reserved_20:4;
         /** tx_sclk_en : R/W; bitpos: [24]; default: 1;
          *  Set this bit to enable UART Tx clock.
          */
@@ -1216,7 +1228,7 @@ typedef union {
 } uart_id_reg_t;
 
 
-typedef struct {
+typedef struct uart_dev_t{
     volatile uart_fifo_reg_t fifo;
     volatile uart_int_raw_reg_t int_raw;
     volatile uart_int_st_reg_t int_st;
@@ -1246,12 +1258,12 @@ typedef struct {
     volatile uart_mem_tx_status_reg_t mem_tx_status;
     volatile uart_mem_rx_status_reg_t mem_rx_status;
     volatile uart_fsm_status_reg_t fsm_status;
-    volatile uart_pospulse_reg_t pospulse;
-    volatile uart_negpulse_reg_t negpulse;
-    volatile uart_lowpulse_reg_t lowpulse;
-    volatile uart_highpulse_reg_t highpulse;
-    volatile uart_rxd_cnt_reg_t rxd_cnt;
-    volatile uart_clk_conf_reg_t clk_conf;
+    volatile uart_pospulse_reg_t pospulse;      /* LP_UART instance has this register reserved */
+    volatile uart_negpulse_reg_t negpulse;      /* LP_UART instance has this register reserved */
+    volatile uart_lowpulse_reg_t lowpulse;      /* LP_UART instance has this register reserved */
+    volatile uart_highpulse_reg_t highpulse;    /* LP_UART instance has this register reserved */
+    volatile uart_rxd_cnt_reg_t rxd_cnt;        /* LP_UART instance has this register reserved */
+    volatile uart_clk_conf_reg_t clk_conf;      /* UART0/1/2/3/4 instance have this register reserved, configure in corresponding PCR registers */
     volatile uart_date_reg_t date;
     volatile uart_afifo_status_reg_t afifo_status;
     uint32_t reserved_094;
@@ -1261,6 +1273,10 @@ typedef struct {
 
 extern uart_dev_t UART0;
 extern uart_dev_t UART1;
+extern uart_dev_t UART2;
+extern uart_dev_t UART3;
+extern uart_dev_t UART4;
+extern uart_dev_t LP_UART;
 
 #ifndef __cplusplus
 _Static_assert(sizeof(uart_dev_t) == 0xa0, "Invalid size of uart_dev_t structure");

components/soc/esp32p4/ld/esp32p4.peripherals.ld

@@ -68,6 +68,7 @@ PROVIDE ( PMU           = 0x50115000 );
 PROVIDE ( LP_SYS        = 0x50110000 );
 PROVIDE ( LP_AON_CLKRST = 0x50111000 );
 PROVIDE ( EFUSE         = 0x5012D000 );
+PROVIDE ( LPPERI        = 0x50120000 );
 PROVIDE ( LP_TIMER      = 0x50112000 );
 PROVIDE ( LP_UART       = 0x50121000 );
 PROVIDE ( LP_I2C        = 0x50122000 );

components/soc/esp32p4/uart_periph.c

@@ -5,10 +5,212 @@
  */
 
 #include "soc/uart_periph.h"
+#include "soc/lp_gpio_sig_map.h"
 
 /*
  Bunch of constants for every UART peripheral: GPIO signals, irqs, hw addr of registers etc
 */
 const uart_signal_conn_t uart_periph_signal[SOC_UART_NUM] = {
+   { // HP UART0
+        .pins = {
+            [SOC_UART_TX_PIN_IDX] = {
+                .default_gpio = U0TXD_GPIO_NUM,
+                .iomux_func = U0TXD_MUX_FUNC,
+                .input = 0,
+                .signal = UART0_TXD_PAD_OUT_IDX,
+            },
 
+            [SOC_UART_RX_PIN_IDX] = {
+                .default_gpio = U0RXD_GPIO_NUM,
+                .iomux_func = U0RXD_MUX_FUNC,
+                .input = 1,
+                .signal = UART0_RXD_PAD_IN_IDX,
+            },
+
+            [SOC_UART_RTS_PIN_IDX] = {
+                .default_gpio = U0RTS_GPIO_NUM,
+                .iomux_func = U0RTS_MUX_FUNC,
+                .input = 0,
+                .signal = UART0_RTS_PAD_OUT_IDX,
+            },
+
+            [SOC_UART_CTS_PIN_IDX] = {
+                .default_gpio = U0CTS_GPIO_NUM,
+                .iomux_func = U0CTS_MUX_FUNC,
+                .input = 1,
+                .signal = UART0_CTS_PAD_IN_IDX,
+            }
+        },
+        .irq = ETS_UART0_INTR_SOURCE,
+        .module = PERIPH_UART0_MODULE,
+    },
+
+    { // HP UART1
+        .pins = {
+            [SOC_UART_TX_PIN_IDX] = {
+                .default_gpio = U1TXD_GPIO_NUM,
+                .iomux_func = U1TXD_MUX_FUNC,
+                .input = 0,
+                .signal = UART1_TXD_PAD_OUT_IDX,
+            },
+
+            [SOC_UART_RX_PIN_IDX] = {
+                .default_gpio = U1RXD_GPIO_NUM,
+                .iomux_func = U1RXD_MUX_FUNC,
+                .input = 1,
+                .signal = UART1_RXD_PAD_IN_IDX,
+            },
+
+            [SOC_UART_RTS_PIN_IDX] = {
+                .default_gpio = U1RTS_GPIO_NUM,
+                .iomux_func = U1RTS_MUX_FUNC,
+                .input = 0,
+                .signal = UART1_RTS_PAD_OUT_IDX,
+            },
+
+            [SOC_UART_CTS_PIN_IDX] = {
+                .default_gpio = U1CTS_GPIO_NUM,
+                .iomux_func = U1CTS_MUX_FUNC,
+                .input = 1,
+                .signal = UART1_CTS_PAD_IN_IDX,
+            },
+        },
+        .irq = ETS_UART1_INTR_SOURCE,
+        .module = PERIPH_UART1_MODULE,
+    },
+
+    { // HP UART2
+        .pins = {
+            [SOC_UART_TX_PIN_IDX] = {
+                .default_gpio = U2TXD_GPIO_NUM,
+                .iomux_func = U2TXD_MUX_FUNC,
+                .input = 0,
+                .signal = UART2_TXD_PAD_OUT_IDX,
+            },
+
+            [SOC_UART_RX_PIN_IDX] = {
+                .default_gpio = U2RXD_GPIO_NUM,
+                .iomux_func = U2RXD_MUX_FUNC,
+                .input = 1,
+                .signal = UART2_RXD_PAD_IN_IDX,
+            },
+
+            [SOC_UART_RTS_PIN_IDX] = {
+                .default_gpio = U2RTS_GPIO_NUM,
+                .iomux_func = U2RTS_MUX_FUNC,
+                .input = 0,
+                .signal = UART2_RTS_PAD_OUT_IDX,
+            },
+
+            [SOC_UART_CTS_PIN_IDX] = {
+                .default_gpio = U2CTS_GPIO_NUM,
+                .iomux_func = U2CTS_MUX_FUNC,
+                .input = 1,
+                .signal = UART2_CTS_PAD_IN_IDX,
+            },
+        },
+        .irq = ETS_UART2_INTR_SOURCE,
+        .module = PERIPH_UART2_MODULE,
+    },
+
+    { // HP UART3
+        .pins = {
+            [SOC_UART_TX_PIN_IDX] = {
+                .default_gpio = U3TXD_GPIO_NUM,
+                .iomux_func = U3TXD_MUX_FUNC,
+                .input = 0,
+                .signal = UART3_TXD_PAD_OUT_IDX,
+            },
+
+            [SOC_UART_RX_PIN_IDX] = {
+                .default_gpio = U3RXD_GPIO_NUM,
+                .iomux_func = U3RXD_MUX_FUNC,
+                .input = 1,
+                .signal = UART3_RXD_PAD_IN_IDX,
+            },
+
+            [SOC_UART_RTS_PIN_IDX] = {
+                .default_gpio = U3RTS_GPIO_NUM,
+                .iomux_func = U3RTS_MUX_FUNC,
+                .input = 0,
+                .signal = UART3_RTS_PAD_OUT_IDX,
+            },
+
+            [SOC_UART_CTS_PIN_IDX] = {
+                .default_gpio = U3CTS_GPIO_NUM,
+                .iomux_func = U3CTS_MUX_FUNC,
+                .input = 1,
+                .signal = UART3_CTS_PAD_IN_IDX,
+            },
+        },
+        .irq = ETS_UART3_INTR_SOURCE,
+        .module = PERIPH_UART3_MODULE,
+    },
+
+    { // HP UART4
+        .pins = {
+            [SOC_UART_TX_PIN_IDX] = {
+                .default_gpio = U4TXD_GPIO_NUM,
+                .iomux_func = U4TXD_MUX_FUNC,
+                .input = 0,
+                .signal = UART4_TXD_PAD_OUT_IDX,
+            },
+
+            [SOC_UART_RX_PIN_IDX] = {
+                .default_gpio = U4RXD_GPIO_NUM,
+                .iomux_func = U4RXD_MUX_FUNC,
+                .input = 1,
+                .signal = UART4_RXD_PAD_IN_IDX,
+            },
+
+            [SOC_UART_RTS_PIN_IDX] = {
+                .default_gpio = U4RTS_GPIO_NUM,
+                .iomux_func = U4RTS_MUX_FUNC,
+                .input = 0,
+                .signal = UART4_RTS_PAD_OUT_IDX,
+            },
+
+            [SOC_UART_CTS_PIN_IDX] = {
+                .default_gpio = U4CTS_GPIO_NUM,
+                .iomux_func = U4CTS_MUX_FUNC,
+                .input = 1,
+                .signal = UART4_CTS_PAD_IN_IDX,
+            },
+        },
+        .irq = ETS_UART4_INTR_SOURCE,
+        .module = PERIPH_UART4_MODULE,
+    },
+    { // LP UART0
+        .pins = {
+            [SOC_UART_TX_PIN_IDX] = {
+                .default_gpio = LP_U0TXD_GPIO_NUM,
+                .iomux_func = LP_U0TXD_MUX_FUNC,
+                .input = 0,
+                .signal = LP_UART_TXD_PAD_OUT_IDX,
+            },
+
+            [SOC_UART_RX_PIN_IDX] = {
+                .default_gpio = LP_U0RXD_GPIO_NUM,
+                .iomux_func = LP_U0RXD_MUX_FUNC,
+                .input = 1,
+                .signal = LP_UART_RXD_PAD_IN_IDX,
+            },
+
+            [SOC_UART_RTS_PIN_IDX] = {
+                .default_gpio = LP_U0RTS_GPIO_NUM,
+                .iomux_func = LP_U0RTS_MUX_FUNC,
+                .input = 0,
+                .signal = LP_UART_RTSN_PAD_OUT_IDX,
+            },
+
+            [SOC_UART_CTS_PIN_IDX] = {
+                .default_gpio = LP_U0CTS_GPIO_NUM,
+                .iomux_func = LP_U0CTS_MUX_FUNC,
+                .input = 1,
+                .signal = LP_UART_CTSN_PAD_IN_IDX,
+            },
+        },
+        .irq = ETS_LP_UART_INTR_SOURCE,
+        .module = PERIPH_LP_UART0_MODULE,
+    },
 };

components/ulp/lp_core/lp_core_uart.c

@@ -13,6 +13,7 @@
 #include "hal/rtc_io_types.h"
 #include "esp_clk_tree.h"
 #include "esp_private/periph_ctrl.h"
+#include "esp_private/uart_private.h"
 
 #define LP_UART_PORT_NUM    LP_UART_NUM_0
 #define LP_UART_TX_IDLE_NUM_DEFAULT     (0U)
@@ -47,12 +48,12 @@ static esp_err_t lp_core_uart_param_config(const lp_core_uart_cfg_t *cfg)
     }
 
     // LP UART clock source is mixed with other peripherals in the same register
-    PERIPH_RCC_ATOMIC() {
+    LP_UART_SRC_CLK_ATOMIC() {
         lp_uart_ll_set_source_clk(hal.dev, clk_src);
     }
 
     /* Override protocol parameters from the configuration */
-    uart_hal_set_baudrate(&hal, cfg->uart_proto_cfg.baud_rate, sclk_freq);
+    lp_uart_ll_set_baudrate(hal.dev, cfg->uart_proto_cfg.baud_rate, sclk_freq);
     uart_hal_set_parity(&hal, cfg->uart_proto_cfg.parity);
     uart_hal_set_data_bit_num(&hal, cfg->uart_proto_cfg.data_bits);
     uart_hal_set_stop_bits(&hal, cfg->uart_proto_cfg.stop_bits);

examples/system/.build-test-rules.yml

@@ -204,12 +204,12 @@ examples/system/ulp/lp_core/lp_i2c:
     - if: SOC_LP_I2C_SUPPORTED == 1
 
 examples/system/ulp/lp_core/lp_uart/lp_uart_echo:
-  enable:
-    - if: SOC_UART_LP_NUM > 0
+  disable:
+    - if: SOC_ULP_LP_UART_SUPPORTED != 1
 
 examples/system/ulp/lp_core/lp_uart/lp_uart_print:
-  enable:
-    - if: SOC_UART_LP_NUM > 0
+  disable:
+    - if: SOC_ULP_LP_UART_SUPPORTED != 1
 
 examples/system/ulp/ulp_fsm/ulp:
   disable:

tools/ci/check_copyright_ignore.txt

@@ -687,8 +687,6 @@ components/soc/esp32c3/include/soc/soc_pins.h
 components/soc/esp32c3/include/soc/spi_mem_reg.h
 components/soc/esp32c3/include/soc/spi_pins.h
 components/soc/esp32c3/include/soc/spi_reg.h
-components/soc/esp32c3/include/soc/system_reg.h
-components/soc/esp32c3/include/soc/system_struct.h
 components/soc/esp32c3/include/soc/systimer_reg.h
 components/soc/esp32c3/include/soc/systimer_struct.h
 components/soc/esp32c3/include/soc/uart_pins.h