feature: support_hp_regi2c_for_esp32c6

components/esp_rom/CMakeLists.txt

@@ -23,7 +23,11 @@ else()
 
     # Override regi2c implementation in ROM
     if(CONFIG_ESP_ROM_HAS_REGI2C_BUG OR CONFIG_ESP_ROM_WITHOUT_REGI2C)
-        list(APPEND sources "patches/esp_rom_regi2c_${target}.c")
+        if(target STREQUAL "esp32c6")
+            list(APPEND sources "patches/esp_rom_hp_regi2c_${target}.c")
+        else()
+            list(APPEND sources "patches/esp_rom_regi2c_${target}.c")
+        endif()
     endif()
 
     if(CONFIG_HEAP_TLSF_USE_ROM_IMPL AND CONFIG_ESP_ROM_TLSF_CHECK_PATCH)

components/esp_rom/patches/esp_rom_regi2c_esp32c6.c → components/esp_rom/patches/esp_rom_hp_regi2c_esp32c6.c

@@ -1,11 +1,11 @@
 /*
- * SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 #include "esp_rom_sys.h"
 #include "esp_attr.h"
-#include "soc/lp_i2c_ana_mst_reg.h"
+#include "soc/i2c_ana_mst_reg.h"
 #include "modem/modem_lpcon_reg.h"
 /**
  * BB    - 0x67 - BIT0
@@ -18,11 +18,12 @@
  * SAR   - 0x69 - BIT7
  * PMU   - 0x6d - BIT8
 */
-#define REGI2C_ULP_CAL_DEVICE_EN  (BIT(6))
-#define REGI2C_SAR_I2C_DEVICE_EN  (BIT(7))
-#define REGI2C_BBPLL_DEVICE_EN    (BIT(5))
-#define REGI2C_BIAS_DEVICE_EN     (BIT(4))
-#define REGI2C_DIG_REG_DEVICE_EN  (BIT(8))
+
+#define REGI2C_ULP_CAL_DEVICE_EN  (BIT(6) << 4)
+#define REGI2C_SAR_I2C_DEVICE_EN  (BIT(7) << 4)
+#define REGI2C_BBPLL_DEVICE_EN    (BIT(5) << 4)
+#define REGI2C_BIAS_DEVICE_EN     (BIT(4) << 4)
+#define REGI2C_DIG_REG_DEVICE_EN  (BIT(8) << 4)
 
 #define REGI2C_RTC_BUSY           (BIT(25))
 #define REGI2C_RTC_BUSY_M         (BIT(25))
@@ -68,29 +69,33 @@
 
 /* SLAVE END */
 
-#define REGI2C_RTC_MAGIC_DEFAULT (0x1C610)
+uint8_t esp_rom_regi2c_read(uint8_t block, uint8_t host_id, uint8_t reg_add) __attribute__((alias("regi2c_read_impl")));
+uint8_t esp_rom_regi2c_read_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb) __attribute__((alias("regi2c_read_mask_impl")));
+void esp_rom_regi2c_write(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data) __attribute__((alias("regi2c_write_impl")));
+void esp_rom_regi2c_write_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data) __attribute__((alias("regi2c_write_mask_impl")));
 
 static IRAM_ATTR void regi2c_enable_block(uint8_t block)
 {
     REG_SET_BIT(MODEM_LPCON_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_EN);
-    REG_SET_BIT(LP_I2C_ANA_MST_DATE_REG, LP_I2C_ANA_MST_I2C_MAT_CLK_EN);
+    REG_SET_BIT(MODEM_LPCON_I2C_MST_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_SEL_160M);
 
+    REG_SET_FIELD(I2C_ANA_MST_ANA_CONF2_REG, I2C_ANA_MST_ANA_CONF2, 0);
     /* Before config I2C register, enable corresponding slave. */
     switch (block) {
     case REGI2C_BBPLL  :
-        REG_SET_BIT(LP_I2C_ANA_MST_DEVICE_EN_REG, REGI2C_BBPLL_DEVICE_EN);
+        REG_SET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_BBPLL_DEVICE_EN);
         break;
     case REGI2C_BIAS   :
-        REG_SET_BIT(LP_I2C_ANA_MST_DEVICE_EN_REG, REGI2C_BIAS_DEVICE_EN);
+        REG_SET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_BIAS_DEVICE_EN);
         break;
     case REGI2C_DIG_REG:
-        REG_SET_BIT(LP_I2C_ANA_MST_DEVICE_EN_REG, REGI2C_DIG_REG_DEVICE_EN);
+        REG_SET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_DIG_REG_DEVICE_EN);
         break;
     case REGI2C_ULP_CAL:
-        REG_SET_BIT(LP_I2C_ANA_MST_DEVICE_EN_REG, REGI2C_ULP_CAL_DEVICE_EN);
+        REG_SET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_ULP_CAL_DEVICE_EN);
         break;
     case REGI2C_SAR_I2C:
-        REG_SET_BIT(LP_I2C_ANA_MST_DEVICE_EN_REG, REGI2C_SAR_I2C_DEVICE_EN);
+        REG_SET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_SAR_I2C_DEVICE_EN);
         break;
     default:
         return;
@@ -101,42 +106,42 @@ static IRAM_ATTR void regi2c_disable_block(uint8_t block)
 {
     switch (block) {
     case REGI2C_BBPLL  :
-        REG_CLR_BIT(LP_I2C_ANA_MST_DEVICE_EN_REG, REGI2C_BBPLL_DEVICE_EN);
+        REG_SET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_BBPLL_DEVICE_EN);
         break;
     case REGI2C_BIAS   :
-        REG_CLR_BIT(LP_I2C_ANA_MST_DEVICE_EN_REG, REGI2C_BIAS_DEVICE_EN);
+        REG_SET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_BIAS_DEVICE_EN);
         break;
     case REGI2C_DIG_REG:
-        REG_CLR_BIT(LP_I2C_ANA_MST_DEVICE_EN_REG, REGI2C_DIG_REG_DEVICE_EN);
+        REG_SET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_DIG_REG_DEVICE_EN);
         break;
     case REGI2C_ULP_CAL:
-        REG_CLR_BIT(LP_I2C_ANA_MST_DEVICE_EN_REG, REGI2C_ULP_CAL_DEVICE_EN);
+        REG_SET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_ULP_CAL_DEVICE_EN);
         break;
     case REGI2C_SAR_I2C:
-        REG_CLR_BIT(LP_I2C_ANA_MST_DEVICE_EN_REG, REGI2C_SAR_I2C_DEVICE_EN);
+        REG_SET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_SAR_I2C_DEVICE_EN);
         break;
     default:
         return;
     }
 }
 
-uint8_t IRAM_ATTR esp_rom_regi2c_read(uint8_t block, uint8_t host_id, uint8_t reg_add)
+uint8_t IRAM_ATTR regi2c_read_impl(uint8_t block, uint8_t host_id, uint8_t reg_add)
 {
     regi2c_enable_block(block);
 
     (void)host_id;
     uint32_t temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S)
                     | (reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S;
-    REG_WRITE(LP_I2C_ANA_MST_I2C0_CTRL_REG, temp);
-    while (REG_GET_BIT(LP_I2C_ANA_MST_I2C0_CTRL_REG, LP_I2C_ANA_MST_I2C0_BUSY));
-    uint8_t ret = REG_GET_FIELD(LP_I2C_ANA_MST_I2C0_DATA_REG, LP_I2C_ANA_MST_I2C0_RDATA);
+    REG_WRITE(I2C_ANA_MST_I2C0_CTRL_REG, temp);
+    while (REG_GET_BIT(I2C_ANA_MST_I2C0_CTRL_REG, REGI2C_RTC_BUSY));
+    uint8_t ret = REG_GET_FIELD(I2C_ANA_MST_I2C0_CTRL_REG, REGI2C_RTC_DATA);
 
     regi2c_disable_block(block);
 
     return ret;
 }
 
-uint8_t IRAM_ATTR esp_rom_regi2c_read_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb)
+uint8_t IRAM_ATTR regi2c_read_mask_impl(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb)
 {
     assert(msb - lsb < 8);
     regi2c_enable_block(block);
@@ -144,17 +149,17 @@ uint8_t IRAM_ATTR esp_rom_regi2c_read_mask(uint8_t block, uint8_t host_id, uint8
     (void)host_id;
     uint32_t temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S)
                     | (reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S;
-    REG_WRITE(LP_I2C_ANA_MST_I2C0_CTRL_REG, temp);
-    while (REG_GET_BIT(LP_I2C_ANA_MST_I2C0_CTRL_REG, LP_I2C_ANA_MST_I2C0_BUSY));
-    uint32_t data = REG_GET_FIELD(LP_I2C_ANA_MST_I2C0_DATA_REG, LP_I2C_ANA_MST_I2C0_RDATA);
-    uint8_t ret =  (uint8_t)((data >> lsb) & (~(0xFFFFFFFF << (msb - lsb + 1))));
+    REG_WRITE(I2C_ANA_MST_I2C0_CTRL_REG, temp);
+    while (REG_GET_BIT(I2C_ANA_MST_I2C0_CTRL_REG, REGI2C_RTC_BUSY));
+    uint32_t data = REG_GET_FIELD(I2C_ANA_MST_I2C0_CTRL_REG, REGI2C_RTC_DATA);
+    uint8_t ret = (uint8_t)((data >> lsb) & (~(0xFFFFFFFF << (msb - lsb + 1))));
 
     regi2c_disable_block(block);
 
     return ret;
 }
 
-void IRAM_ATTR esp_rom_regi2c_write(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data)
+void IRAM_ATTR regi2c_write_impl(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data)
 {
     (void)host_id;
     regi2c_enable_block(block);
@@ -163,13 +168,13 @@ void IRAM_ATTR esp_rom_regi2c_write(uint8_t block, uint8_t host_id, uint8_t reg_
                     | ((reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S)
                     | ((0x1 & REGI2C_RTC_WR_CNTL_V) << REGI2C_RTC_WR_CNTL_S) // 0: READ I2C register; 1: Write I2C register;
                     | (((uint32_t)data & REGI2C_RTC_DATA_V) << REGI2C_RTC_DATA_S);
-    REG_WRITE(LP_I2C_ANA_MST_I2C0_CTRL_REG, temp);
-    while (REG_GET_BIT(LP_I2C_ANA_MST_I2C0_CTRL_REG, LP_I2C_ANA_MST_I2C0_BUSY));
+    REG_WRITE(I2C_ANA_MST_I2C0_CTRL_REG, temp);
+    while (REG_GET_BIT(I2C_ANA_MST_I2C0_CTRL_REG, REGI2C_RTC_BUSY));
 
     regi2c_disable_block(block);
 }
 
-void IRAM_ATTR esp_rom_regi2c_write_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data)
+void IRAM_ATTR regi2c_write_mask_impl(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data)
 {
     (void)host_id;
     assert(msb - lsb < 8);
@@ -178,9 +183,9 @@ void IRAM_ATTR esp_rom_regi2c_write_mask(uint8_t block, uint8_t host_id, uint8_t
     /*Read the i2c bus register*/
     uint32_t temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S)
                     | (reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S;
-    REG_WRITE(LP_I2C_ANA_MST_I2C0_CTRL_REG, temp);
-    while (REG_GET_BIT(LP_I2C_ANA_MST_I2C0_CTRL_REG, LP_I2C_ANA_MST_I2C0_BUSY));
-    temp = REG_GET_FIELD(LP_I2C_ANA_MST_I2C0_DATA_REG, LP_I2C_ANA_MST_I2C0_RDATA);
+    REG_WRITE(I2C_ANA_MST_I2C0_CTRL_REG, temp);
+    while (REG_GET_BIT(I2C_ANA_MST_I2C0_CTRL_REG, REGI2C_RTC_BUSY));
+    temp = REG_GET_FIELD(I2C_ANA_MST_I2C0_CTRL_REG, REGI2C_RTC_DATA);
     /*Write the i2c bus register*/
     temp &= ((~(0xFFFFFFFF << lsb)) | (0xFFFFFFFF << (msb + 1)));
     temp = (((uint32_t)data & (~(0xFFFFFFFF << (msb - lsb + 1)))) << lsb) | temp;
@@ -188,8 +193,8 @@ void IRAM_ATTR esp_rom_regi2c_write_mask(uint8_t block, uint8_t host_id, uint8_t
             | ((reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S)
             | ((0x1 & REGI2C_RTC_WR_CNTL_V) << REGI2C_RTC_WR_CNTL_S)
             | ((temp & REGI2C_RTC_DATA_V) << REGI2C_RTC_DATA_S);
-    REG_WRITE(LP_I2C_ANA_MST_I2C0_CTRL_REG, temp);
-    while (REG_GET_BIT(LP_I2C_ANA_MST_I2C0_CTRL_REG, LP_I2C_ANA_MST_I2C0_BUSY));
+    REG_WRITE(I2C_ANA_MST_I2C0_CTRL_REG, temp);
+    while (REG_GET_BIT(I2C_ANA_MST_I2C0_CTRL_REG, REGI2C_RTC_BUSY));
 
     regi2c_disable_block(block);
 }

components/esp_rom/patches/esp_rom_regi2c_esp32h2.c

@@ -72,7 +72,6 @@
 static IRAM_ATTR void regi2c_enable_block(uint8_t block)
 {
     REG_SET_BIT(MODEM_LPCON_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_EN);
-    REG_SET_BIT(I2C_MST_DATE_REG, I2C_MST_CLK_EN);
     REG_SET_FIELD(I2C_MST_ANA_CONF2_REG, I2C_MST_ANA_CONF2, 0);
     /* Before config I2C register, enable corresponding slave. */
     switch (block) {

components/soc/esp32c6/include/soc/i2c_ana_mst_reg.h

@@ -13,91 +13,207 @@
 extern "C" {
 #endif
 
-#define I2C_ANA_MST_I2C0_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x0000)
-#define I2C_ANA_MST_I2C0_BUSY (BIT(25))
-#define I2C_ANA_MST_I2C0_BUSY_S 25
-#define I2C_ANA_MST_I2C0_CTRL 0x01FFFFFF
-#define I2C_ANA_MST_I2C0_CTRL_S 0
-
-#define I2C_ANA_MST_I2C1_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x0004)
-#define I2C_ANA_MST_I2C1_BUSY (BIT(25))
-#define I2C_ANA_MST_I2C1_BUSY_S 25
-#define I2C_ANA_MST_I2C1_CTRL 0x01FFFFFF
-#define I2C_ANA_MST_I2C1_CTRL_S 0
-
-#define I2C_ANA_MST_I2C0_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0x0008)
-#define I2C_ANA_MST_I2C0_STATUS 0x000000FF
-#define I2C_ANA_MST_I2C0_STATUS_S 24
-#define I2C_ANA_MST_I2C0_CONF 0x00FFFFFF
-#define I2C_ANA_MST_I2C0_CONF_S 0
-
-#define I2C_ANA_MST_I2C1_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0x000C)
-#define I2C_ANA_MST_I2C1_STATUS 0x000000FF
-#define I2C_ANA_MST_I2C1_STATUS_S 24
-#define I2C_ANA_MST_I2C1_CONF 0x00FFFFFF
-#define I2C_ANA_MST_I2C1_CONF_S 0
-
-#define I2C_ANA_MST_I2C_BURST_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0x0010)
-#define I2C_ANA_MST_BURST_CTRL 0xFFFFFFFF
-#define I2C_ANA_MST_BURST_CTRL_S 0
-
-#define I2C_ANA_MST_I2C_BURST_STATUS_REG (DR_REG_I2C_ANA_MST_BASE + 0x0014)
-#define I2C_ANA_MST_BURST_TIMEOUT_CNT 0x00000FFF
-#define I2C_ANA_MST_BURST_TIMEOUT_CNT_S 20
-#define I2C_ANA_MST1_BURST_ERR_FLAG (BIT(2))
-#define I2C_ANA_MST1_BURST_ERR_FLAG_S 2
-#define I2C_ANA_MST0_BURST_ERR_FLAG (BIT(1))
-#define I2C_ANA_MST0_BURST_ERR_FLAG_S 1
-#define I2C_ANA_MST_BURST_DONE (BIT(0))
-#define I2C_ANA_MST_BURST_DONE_S 0
-
-#define I2C_ANA_MST_ANA_CONF0_REG (DR_REG_I2C_ANA_MST_BASE + 0x0018)
-#define I2C_ANA_MST_ANA_STATUS0 0x000000FF
-#define I2C_ANA_MST_ANA_STATUS0_S 24
-#define I2C_ANA_MST_ANA_CONF0 0x00FFFFFF
-#define I2C_ANA_MST_ANA_CONF0_S 0
-
-#define I2C_ANA_MST_ANA_CONF1_REG (DR_REG_I2C_ANA_MST_BASE + 0x001C)
-#define I2C_ANA_MST_ANA_STATUS1 0x000000FF
-#define I2C_ANA_MST_ANA_STATUS1_S 24
-#define I2C_ANA_MST_ANA_CONF1 0x00FFFFFF
-#define I2C_ANA_MST_ANA_CONF1_S 0
-
-#define I2C_ANA_MST_ANA_CONF2_REG (DR_REG_I2C_ANA_MST_BASE + 0x0020)
-#define I2C_ANA_MST_ANA_STATUS2 0x000000FF
-#define I2C_ANA_MST_ANA_STATUS2_S 24
-#define I2C_ANA_MST_ANA_CONF2 0x00FFFFFF
-#define I2C_ANA_MST_ANA_CONF2_S 0
-
-#define I2C_ANA_MST_I2C0_CTRL1_REG (DR_REG_I2C_ANA_MST_BASE + 0x0024)
-#define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD 0x0000001F
-#define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_S 6
-#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR 0x0000003F
-#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR_S 0
-
-#define I2C_ANA_MST_I2C1_CTRL1_REG (DR_REG_I2C_ANA_MST_BASE + 0x0028)
-#define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD 0x0000001F
-#define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_S 6
-#define I2C_ANA_MST_I2C1_SCL_PULSE_DUR 0x0000003F
-#define I2C_ANA_MST_I2C1_SCL_PULSE_DUR_S 0
-
-#define I2C_ANA_MST_HW_I2C_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x002C)
-#define I2C_ANA_MST_ARBITER_DIS (BIT(11))
-#define I2C_ANA_MST_ARBITER_DIS_S 11
-#define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD 0x0000001F
-#define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_S 6
-#define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR 0x0000003F
-#define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_S 0
-
-#define I2C_ANA_MST_NOUSE_REG (DR_REG_I2C_ANA_MST_BASE + 0x0030)
-#define I2C_ANA_MST_NOUSE 0xFFFFFFFF
-#define I2C_ANA_MST_NOUSE_S 0
-
-#define I2C_ANA_MST_DATE_REG (DR_REG_I2C_ANA_MST_BASE + 0x0034)
-#define I2C_ANA_MST_CLK_EN (BIT(28))
-#define I2C_ANA_MST_CLK_EN_S 28
-#define I2C_ANA_MST_DATE 0x0FFFFFFF
-#define I2C_ANA_MST_DATE_S 0
+#define I2C_ANA_MST_I2C0_CTRL_REG          (DR_REG_I2C_ANA_MST_BASE + 0x0)
+/* I2C_MST_I2C0_BUSY : RO ;bitpos:[25] ;default: 1'h0 ; */
+/*description: .*/
+#define I2C_ANA_MST_I2C0_BUSY    (BIT(25))
+#define I2C_ANA_MST_I2C0_BUSY_M  (BIT(25))
+#define I2C_ANA_MST_I2C0_BUSY_V  0x1
+#define I2C_ANA_MST_I2C0_BUSY_S  25
+/* I2C_MST_I2C0_CTRL : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
+/*description: .*/
+#define I2C_ANA_MST_I2C0_CTRL    0x01FFFFFF
+#define I2C_ANA_MST_I2C0_CTRL_M  ((I2C_MST_I2C0_CTRL_V)<<(I2C_MST_I2C0_CTRL_S))
+#define I2C_ANA_MST_I2C0_CTRL_V  0x1FFFFFF
+#define I2C_ANA_MST_I2C0_CTRL_S  0
+
+#define I2C_ANA_MST_I2C1_CTRL_REG          (DR_REG_I2C_ANA_MST_BASE + 0x4)
+/* I2C_MST_I2C1_BUSY : RO ;bitpos:[25] ;default: 1'h0 ; */
+/*description: .*/
+#define I2C_ANA_MST_I2C1_BUSY    (BIT(25))
+#define I2C_ANA_MST_I2C1_BUSY_M  (BIT(25))
+#define I2C_ANA_MST_I2C1_BUSY_V  0x1
+#define I2C_ANA_MST_I2C1_BUSY_S  25
+/* I2C_MST_I2C1_CTRL : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
+/*description: .*/
+#define I2C_ANA_MST_I2C1_CTRL    0x01FFFFFF
+#define I2C_ANA_MST_I2C1_CTRL_M  ((I2C_MST_I2C1_CTRL_V)<<(I2C_MST_I2C1_CTRL_S))
+#define I2C_ANA_MST_I2C1_CTRL_V  0x1FFFFFF
+#define I2C_ANA_MST_I2C1_CTRL_S  0
+
+#define I2C_ANA_MST_I2C0_CONF_REG          (DR_REG_I2C_ANA_MST_BASE + 0x8)
+/* I2C_MST_I2C0_STATUS : RO ;bitpos:[31:24] ;default: 8'h0 ; */
+/*description: .*/
+#define I2C_ANA_MST_I2C0_STATUS    0x000000FF
+#define I2C_ANA_MST_I2C0_STATUS_M  ((I2C_MST_I2C0_STATUS_V)<<(I2C_MST_I2C0_STATUS_S))
+#define I2C_ANA_MST_I2C0_STATUS_V  0xFF
+#define I2C_ANA_MST_I2C0_STATUS_S  24
+/* I2C_MST_I2C0_CONF : R/W ;bitpos:[23:0] ;default: 24'h0 ; */
+/*description: .*/
+#define I2C_ANA_MST_I2C0_CONF    0x00FFFFFF
+#define I2C_ANA_MST_I2C0_CONF_M  ((I2C_MST_I2C0_CONF_V)<<(I2C_MST_I2C0_CONF_S))
+#define I2C_ANA_MST_I2C0_CONF_V  0xFFFFFF
+#define I2C_ANA_MST_I2C0_CONF_S  0
+
+#define I2C_ANA_MST_I2C1_CONF_REG          (DR_REG_I2C_ANA_MST_BASE + 0xC)
+/* I2C_MST_I2C1_STATUS : RO ;bitpos:[31:24] ;default: 8'h0 ; */
+/*description: .*/
+#define I2C_ANA_MST_I2C1_STATUS    0x000000FF
+#define I2C_ANA_MST_I2C1_STATUS_M  ((I2C_MST_I2C1_STATUS_V)<<(I2C_MST_I2C1_STATUS_S))
+#define I2C_ANA_MST_I2C1_STATUS_V  0xFF
+#define I2C_ANA_MST_I2C1_STATUS_S  24
+/* I2C_MST_I2C1_CONF : R/W ;bitpos:[23:0] ;default: 24'h0 ; */
+/*description: .*/
+#define I2C_ANA_MST_I2C1_CONF    0x00FFFFFF
+#define I2C_ANA_MST_I2C1_CONF_M  ((I2C_MST_I2C1_CONF_V)<<(I2C_MST_I2C1_CONF_S))
+#define I2C_ANA_MST_I2C1_CONF_V  0xFFFFFF
+#define I2C_ANA_MST_I2C1_CONF_S  0
+
+#define I2C_ANA_MST_I2C_BURST_CONF_REG          (DR_REG_I2C_ANA_MST_BASE + 0x10)
+/* I2C_MST_BURST_CTRL : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: .*/
+#define I2C_ANA_MST_BURST_CTRL    0xFFFFFFFF
+#define I2C_ANA_MST_BURST_CTRL_M  ((I2C_MST_BURST_CTRL_V)<<(I2C_MST_BURST_CTRL_S))
+#define I2C_ANA_MST_BURST_CTRL_V  0xFFFFFFFF
+#define I2C_ANA_MST_BURST_CTRL_S  0
+
+#define I2C_ANA_MST_I2C_BURST_STATUS_REG          (DR_REG_I2C_ANA_MST_BASE + 0x14)
+/* I2C_MST_BURST_TIMEOUT_CNT : R/W ;bitpos:[31:20] ;default: 12'h400 ; */
+/*description: .*/
+#define I2C_ANA_MST_BURST_TIMEOUT_CNT    0x00000FFF
+#define I2C_ANA_MST_BURST_TIMEOUT_CNT_M  ((I2C_MST_BURST_TIMEOUT_CNT_V)<<(I2C_MST_BURST_TIMEOUT_CNT_S))
+#define I2C_ANA_MST_BURST_TIMEOUT_CNT_V  0xFFF
+#define I2C_ANA_MST_BURST_TIMEOUT_CNT_S  20
+/* I2C_MST1_BURST_ERR_FLAG : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_ANA_MST1_BURST_ERR_FLAG    (BIT(2))
+#define I2C_ANA_MST1_BURST_ERR_FLAG_M  (BIT(2))
+#define I2C_ANA_MST1_BURST_ERR_FLAG_V  0x1
+#define I2C_ANA_MST1_BURST_ERR_FLAG_S  2
+/* I2C_MST0_BURST_ERR_FLAG : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_ANA_MST0_BURST_ERR_FLAG    (BIT(1))
+#define I2C_ANA_MST0_BURST_ERR_FLAG_M  (BIT(1))
+#define I2C_ANA_MST0_BURST_ERR_FLAG_V  0x1
+#define I2C_ANA_MST0_BURST_ERR_FLAG_S  1
+/* I2C_MST_BURST_DONE : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_ANA_MST_BURST_DONE    (BIT(0))
+#define I2C_ANA_MST_BURST_DONE_M  (BIT(0))
+#define I2C_ANA_MST_BURST_DONE_V  0x1
+#define I2C_ANA_MST_BURST_DONE_S  0
+
+#define I2C_ANA_MST_ANA_CONF0_REG          (DR_REG_I2C_ANA_MST_BASE + 0x18)
+/* I2C_MST_ANA_STATUS0 : RO ;bitpos:[31:24] ;default: 8'h0 ; */
+/*description: .*/
+#define I2C_ANA_MST_ANA_STATUS0    0x000000FF
+#define I2C_ANA_MST_ANA_STATUS0_M  ((I2C_MST_ANA_STATUS0_V)<<(I2C_MST_ANA_STATUS0_S))
+#define I2C_ANA_MST_ANA_STATUS0_V  0xFF
+#define I2C_ANA_MST_ANA_STATUS0_S  24
+/* I2C_MST_ANA_CONF0 : R/W ;bitpos:[23:0] ;default: 24'h00_e408 ; */
+/*description: .*/
+#define I2C_ANA_MST_ANA_CONF0    0x00FFFFFF
+#define I2C_ANA_MST_ANA_CONF0_M  ((I2C_MST_ANA_CONF0_V)<<(I2C_MST_ANA_CONF0_S))
+#define I2C_ANA_MST_ANA_CONF0_V  0xFFFFFF
+#define I2C_ANA_MST_ANA_CONF0_S  0
+
+#define I2C_ANA_MST_ANA_CONF1_REG          (DR_REG_I2C_ANA_MST_BASE + 0x1C)
+/* I2C_MST_ANA_STATUS1 : RO ;bitpos:[31:24] ;default: 8'h0 ; */
+/*description: .*/
+#define I2C_ANA_MST_ANA_STATUS1    0x000000FF
+#define I2C_ANA_MST_ANA_STATUS1_M  ((I2C_MST_ANA_STATUS1_V)<<(I2C_MST_ANA_STATUS1_S))
+#define I2C_ANA_MST_ANA_STATUS1_V  0xFF
+#define I2C_ANA_MST_ANA_STATUS1_S  24
+/* I2C_MST_AANA_NA_CONF1 : R/W ;bitpos:[23:0] ;default: 24'h00_002d ; */
+/*description: .*/
+#define I2C_ANA_MST_ANA_CONF1    0x00FFFFFF
+#define I2C_ANA_MST_ANA_CONF1_M  ((I2C_MST_ANA_CONF1_V)<<(I2C_MST_ANA_CONF1_S))
+#define I2C_ANA_MST_ANA_CONF1_V  0xFFFFFF
+#define I2C_ANA_MST_ANA_CONF1_S  0
+
+#define I2C_ANA_MST_ANA_CONF2_REG          (DR_REG_I2C_ANA_MST_BASE + 0x20)
+/* I2C_MST_ANA_STATUS2 : RO ;bitpos:[31:24] ;default: 8'h0 ; */
+/*description: .*/
+#define I2C_ANA_MST_ANA_STATUS2    0x000000FF
+#define I2C_ANA_MST_ANA_STATUS2_M  ((I2C_MST_ANA_STATUS2_V)<<(I2C_MST_ANA_STATUS2_S))
+#define I2C_ANA_MST_ANA_STATUS2_V  0xFF
+#define I2C_ANA_MST_ANA_STATUS2_S  24
+/* I2C_MST_ANA_CONF2 : R/W ;bitpos:[23:0] ;default: 24'h00_0004 ; */
+/*description: .*/
+#define I2C_ANA_MST_ANA_CONF2    0x00FFFFFF
+#define I2C_ANA_MST_ANA_CONF2_M  ((I2C_MST_ANA_CONF2_V)<<(I2C_MST_ANA_CONF2_S))
+#define I2C_ANA_MST_ANA_CONF2_V  0xFFFFFF
+#define I2C_ANA_MST_ANA_CONF2_S  0
+
+#define I2C_ANA_MST_I2C0_CTRL1_REG          (DR_REG_I2C_ANA_MST_BASE + 0x24)
+/* I2C_MST_I2C0_SDA_SIDE_GUARD : R/W ;bitpos:[10:6] ;default: 5'h1 ; */
+/*description: .*/
+#define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD    0x0000001F
+#define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_M  ((I2C_MST_I2C0_SDA_SIDE_GUARD_V)<<(I2C_MST_I2C0_SDA_SIDE_GUARD_S))
+#define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_V  0x1F
+#define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_S  6
+/* I2C_MST_I2C0_SCL_PULSE_DUR : R/W ;bitpos:[5:0] ;default: 6'h2 ; */
+/*description: .*/
+#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR    0x0000003F
+#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR_M  ((I2C_MST_I2C0_SCL_PULSE_DUR_V)<<(I2C_MST_I2C0_SCL_PULSE_DUR_S))
+#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR_V  0x3F
+#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR_S  0
+
+#define I2C_ANA_MST_I2C1_CTRL1_REG          (DR_REG_I2C_ANA_MST_BASE + 0x28)
+/* I2C_MST_I2C1_SDA_SIDE_GUARD : R/W ;bitpos:[10:6] ;default: 5'h1 ; */
+/*description: .*/
+#define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD    0x0000001F
+#define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_M  ((I2C_MST_I2C1_SDA_SIDE_GUARD_V)<<(I2C_MST_I2C1_SDA_SIDE_GUARD_S))
+#define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_V  0x1F
+#define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_S  6
+/* I2C_MST_I2C1_SCL_PULSE_DUR : R/W ;bitpos:[5:0] ;default: 6'h2 ; */
+/*description: .*/
+#define I2C_ANA_MST_I2C1_SCL_PULSE_DUR    0x0000003F
+#define I2C_ANA_MST_I2C1_SCL_PULSE_DUR_M  ((I2C_MST_I2C1_SCL_PULSE_DUR_V)<<(I2C_MST_I2C1_SCL_PULSE_DUR_S))
+#define I2C_ANA_MST_I2C1_SCL_PULSE_DUR_V  0x3F
+#define I2C_ANA_MST_I2C1_SCL_PULSE_DUR_S  0
+
+#define I2C_ANA_MST_HW_I2C_CTRL_REG          (DR_REG_I2C_ANA_MST_BASE + 0x2C)
+/* I2C_MST_ARBITER_DIS : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: .*/
+#define I2C_ANA_MST_ARBITER_DIS    (BIT(11))
+#define I2C_ANA_MST_ARBITER_DIS_M  (BIT(11))
+#define I2C_ANA_MST_ARBITER_DIS_V  0x1
+#define I2C_ANA_MST_ARBITER_DIS_S  11
+/* I2C_MST_HW_I2C_SDA_SIDE_GUARD : R/W ;bitpos:[10:6] ;default: 5'h1 ; */
+/*description: .*/
+#define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD    0x0000001F
+#define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_M  ((I2C_MST_HW_I2C_SDA_SIDE_GUARD_V)<<(I2C_MST_HW_I2C_SDA_SIDE_GUARD_S))
+#define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_V  0x1F
+#define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_S  6
+/* I2C_MST_HW_I2C_SCL_PULSE_DUR : R/W ;bitpos:[5:0] ;default: 6'h2 ; */
+/*description: .*/
+#define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR    0x0000003F
+#define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_M  ((I2C_MST_HW_I2C_SCL_PULSE_DUR_V)<<(I2C_MST_HW_I2C_SCL_PULSE_DUR_S))
+#define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_V  0x3F
+#define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_S  0
+
+#define I2C_ANA_MST_NOUSE_REG          (DR_REG_I2C_ANA_MST_BASE + 0x30)
+/* I2C_MST_NOUSE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: .*/
+#define I2C_ANA_MST_NOUSE    0xFFFFFFFF
+#define I2C_ANA_MST_NOUSE_M  ((I2C_MST_NOUSE_V)<<(I2C_MST_NOUSE_S))
+#define I2C_ANA_MST_NOUSE_V  0xFFFFFFFF
+#define I2C_ANA_MST_NOUSE_S  0
+
+#define I2C_ANA_MST_DATE_REG          (DR_REG_I2C_ANA_MST_BASE + 0x34)
+/* I2C_MST_CLK_EN : R/W ;bitpos:[28] ;default: 1'h0 ; */
+/*description: .*/
+#define I2C_ANA_MST_CLK_EN    (BIT(28))
+#define I2C_ANA_MST_CLK_EN_M  (BIT(28))
+#define I2C_ANA_MST_CLK_EN_V  0x1
+#define I2C_ANA_MST_CLK_EN_S  28
+/* I2C_MST_DATE : R/W ;bitpos:[27:0] ;default: 28'h2201300 ; */
+/*description: .*/
+#define I2C_ANA_MST_DATE    0x0FFFFFFF
+#define I2C_ANA_MST_DATE_M  ((I2C_MST_DATE_V)<<(I2C_MST_DATE_S))
+#define I2C_ANA_MST_DATE_V  0xFFFFFFF
+#define I2C_ANA_MST_DATE_S  0
 
 #ifdef __cplusplus
 }