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@@ -24,8 +24,10 @@
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#include "soc/nrx_reg.h"
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#include "soc/fe_reg.h"
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#include "soc/timer_group_reg.h"
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+#include "soc/system_reg.h"
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#include "soc/rtc.h"
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#include "esp32c3/rom/ets_sys.h"
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+#include "esp32c3/rom/rtc.h"
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#include "regi2c_ctrl.h"
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/**
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@@ -140,6 +142,8 @@ void rtc_sleep_set_wakeup_time(uint64_t t)
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WRITE_PERI_REG(RTC_CNTL_SLP_TIMER1_REG, t >> 32);
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}
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+static uint32_t rtc_sleep_finish(uint32_t lslp_mem_inf_fpu);
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+
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uint32_t rtc_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt, uint32_t lslp_mem_inf_fpu)
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{
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REG_SET_FIELD(RTC_CNTL_WAKEUP_STATE_REG, RTC_CNTL_WAKEUP_ENA, wakeup_opt);
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@@ -152,6 +156,88 @@ uint32_t rtc_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt, uint32_t lslp
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RTC_CNTL_SLP_REJECT_INT_RAW | RTC_CNTL_SLP_WAKEUP_INT_RAW) == 0) {
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;
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}
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+
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+ return rtc_sleep_finish(lslp_mem_inf_fpu);
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+}
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+
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+#define STR2(X) #X
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+#define STR(X) STR2(X)
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+
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+uint32_t rtc_deep_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt)
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+{
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+ REG_SET_FIELD(RTC_CNTL_WAKEUP_STATE_REG, RTC_CNTL_WAKEUP_ENA, wakeup_opt);
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+ WRITE_PERI_REG(RTC_CNTL_SLP_REJECT_CONF_REG, reject_opt);
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+
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+ /* Calculate RTC Fast Memory CRC (for wake stub) & go to deep sleep
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+
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+ Because we may be running from RTC memory as stack, we can't easily call any
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+ functions to do this (as registers will spill to stack, corrupting the CRC).
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+
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+ Instead, load all the values we need into registers then use register ops only to calculate
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+ the CRC value, write it to the RTC CRC value register, and immediately go into deep sleep.
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+ */
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+
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+ /* Values used to set the SYSTEM_RTC_FASTMEM_CONFIG_REG value */
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+ const unsigned CRC_START_ADDR = 0;
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+ const unsigned CRC_LEN = 0x7ff;
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+
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+ asm volatile(
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+ /* Start CRC calculation */
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+ "sw %1, 0(%0)\n" // set RTC_MEM_CRC_ADDR & RTC_MEM_CRC_LEN
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+ "or t0, %1, %2\n"
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+ "sw t0, 0(%0)\n" // set RTC_MEM_CRC_START
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+
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+ /* Wait for the CRC calculation to finish */
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+ ".Lwaitcrc:\n"
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+ "fence\n"
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+ "lw t0, 0(%0)\n"
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+ "li t1, "STR(SYSTEM_RTC_MEM_CRC_FINISH)"\n"
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+ "and t0, t0, t1\n"
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+ "beqz t0, .Lwaitcrc\n"
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+ "not %2, %2\n" // %2 -> ~DPORT_RTC_MEM_CRC_START
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+ "and t0, t0, %2\n"
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+ "sw t0, 0(%0)\n" // clear RTC_MEM_CRC_START
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+ "fence\n"
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+ "not %2, %2\n" // %2 -> DPORT_RTC_MEM_CRC_START, probably unnecessary but gcc assumes inputs unchanged
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+
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+ /* Store the calculated value in RTC_MEM_CRC_REG */
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+ "lw t0, 0(%3)\n"
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+ "sw t0, 0(%4)\n"
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+ "fence\n"
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+
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+ /* Set register bit to go into deep sleep */
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+ "lw t0, 0(%5)\n"
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+ "or t0, t0, %6\n"
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+ "sw t0, 0(%5)\n"
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+ "fence\n"
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+
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+ /* Wait for sleep reject interrupt (never finishes if successful) */
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+ ".Lwaitsleep:"
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+ "fence\n"
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+ "lw t0, 0(%7)\n"
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+ "and t0, t0, %8\n"
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+ "beqz t0, .Lwaitsleep\n"
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+
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+ :
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+ :
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+ "r" (SYSTEM_RTC_FASTMEM_CONFIG_REG), // %0
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+ "r" ( (CRC_START_ADDR << SYSTEM_RTC_MEM_CRC_START_S)
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+ | (CRC_LEN << SYSTEM_RTC_MEM_CRC_LEN_S)), // %1
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+ "r" (SYSTEM_RTC_MEM_CRC_START), // %2
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+ "r" (SYSTEM_RTC_FASTMEM_CRC_REG), // %3
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+ "r" (RTC_MEMORY_CRC_REG), // %4
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+ "r" (RTC_CNTL_STATE0_REG), // %5
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+ "r" (RTC_CNTL_SLEEP_EN), // %6
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+ "r" (RTC_CNTL_INT_RAW_REG), // %7
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+ "r" (RTC_CNTL_SLP_REJECT_INT_RAW | RTC_CNTL_SLP_WAKEUP_INT_RAW) // %8
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+ : "t0", "t1" // working registers
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+ );
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+
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+ return rtc_sleep_finish(0);
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+}
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+
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+static uint32_t rtc_sleep_finish(uint32_t lslp_mem_inf_fpu)
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+{
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/* In deep sleep mode, we never get here */
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uint32_t reject = REG_GET_FIELD(RTC_CNTL_INT_RAW_REG, RTC_CNTL_SLP_REJECT_INT_RAW);
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SET_PERI_REG_MASK(RTC_CNTL_INT_CLR_REG,
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@@ -164,8 +250,3 @@ uint32_t rtc_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt, uint32_t lslp
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}
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return reject;
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}
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-
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-uint32_t rtc_deep_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt)
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-{
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- abort(); // ESP32-C3 TODO IDF-2560
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-}
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