Merge branch 'bugfix/s3_sleep_voltage' into 'master'

esp32s3: fixed dangerous power parameters in sleep modes

See merge request espressif/esp-idf!18168

components/esp_hw_support/port/esp32s3/rtc_pm.c

@@ -45,9 +45,7 @@ pm_sw_reject_t pm_set_sleep_mode(pm_sleep_mode_t sleep_mode, void(*pmac_save_par
     switch (sleep_mode) {
     case PM_LIGHT_SLEEP:
         cfg.wifi_pd_en = 1;
-        cfg.dig_dbias_wak = 4;
         cfg.dig_dbias_slp = 0;
-        cfg.rtc_dbias_wak = 0;
         cfg.rtc_dbias_slp = 0;
         rtc_sleep_init(cfg);
         break;

components/esp_hw_support/port/esp32s3/rtc_sleep.c

@@ -69,33 +69,84 @@ void rtc_sleep_get_default_config(uint32_t sleep_flags, rtc_sleep_config_t *out_
         .vddsdio_pd_en = (sleep_flags & RTC_SLEEP_PD_VDDSDIO) ? 1 : 0,
         .xtal_fpu = (sleep_flags & RTC_SLEEP_PD_XTAL) ? 0 : 1,
         .deep_slp_reject = 1,
-        .light_slp_reject = 1
+        .light_slp_reject = 1,
+        .dbg_atten_monitor = RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT,
+        .rtc_dbias_slp = RTC_CNTL_DBIAS_1V10
     };
 
     if (sleep_flags & RTC_SLEEP_PD_DIG) {
-        out_config->dig_dbias_wak = RTC_CNTL_DBIAS_1V10;
-        out_config->dig_dbias_slp = RTC_CNTL_DBIAS_SLP;
-        out_config->rtc_dbias_wak = RTC_CNTL_DBIAS_1V10;
-        out_config->rtc_dbias_slp = RTC_CNTL_DBIAS_SLP;
+        assert(sleep_flags & RTC_SLEEP_PD_XTAL);
+        out_config->dig_dbias_slp = 0;  //not used
+        //rtc voltage from high to low
+        if (sleep_flags & RTC_SLEEP_USE_ADC_TESEN_MONITOR) {
+            /*
+             * rtc voltage in sleep mode >= 1.1v
+             * Support all features:
+             * - ADC/Temperature sensor in monitor mode (ULP) (also need pd_cur_monotor = 0)
+             * - RTC IO as input
+             * - RTC Memory at high temperature
+             * - ULP
+             * - Touch sensor
+             * - 8MD256 as RTC slow clock src
+             */
+            out_config->rtc_regulator_fpu = 1;
+            out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_DEEPSLEEP_NODROP;
+        } else if (sleep_flags & RTC_SLEEP_NO_ULTRA_LOW) {
+            /*
+             * rtc voltage in sleep need stable and not less than 0.7v (default mode):
+             * can't use ADC/Temperature sensor in monitor mode
+             */
+            out_config->rtc_regulator_fpu = 1;
+            out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT;
+        } else {
+            /*
+             * rtc regulator not opened and rtc voltage is about 0.66v (ultra low power):
+               also can't use RTC IO as input, RTC memory can't work under high temperature
+             */
+            out_config->rtc_regulator_fpu = 0;
+            out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_DEEPSLEEP_ULTRA_LOW;
+        }
+    } else {
+        out_config->rtc_regulator_fpu = 1;
+        //voltage from high to low
+        if ((sleep_flags & RTC_SLEEP_DIG_USE_8M) || !(sleep_flags & RTC_SLEEP_PD_XTAL)) {
+            /*
+             * digital voltage not less than 1.1v, rtc voltage not less than 1.1v to keep system stable
+             * Support all features:
+             * - XTAL
+             * - RC 8M used by digital system
+             * - ADC/Temperature sensor in monitor mode (ULP)
+             * - ULP
+             * - Touch sensor
+             * - 8MD256 as RTC slow clock src
+             */
+            out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP;
+            out_config->dig_dbias_slp = RTC_CNTL_DBIAS_1V10;
+        } else {
+            /*
+             * digital voltage not less than 0.6v
+             * if use RTC_SLEEP_USE_ADC_TESEN_MONITOR, rtc voltage need to be >= 0.9v(default voltage), others just use default rtc voltage.
+             * - not support XTAL
+             * - not support RC 8M in digital system
+            */
+            out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT;
+            out_config->dig_dbias_slp = RTC_CNTL_DBIAS_SLP;
+        }
+    }
 
-        out_config->dbg_atten_monitor = RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT;
+    if (!(sleep_flags & RTC_SLEEP_PD_XTAL)) {
+        out_config->bias_sleep_monitor = RTC_CNTL_BIASSLP_MONITOR_ON;
+        out_config->pd_cur_monitor = RTC_CNTL_PD_CUR_MONITOR_ON;
+
+        out_config->bias_sleep_slp = RTC_CNTL_BIASSLP_SLEEP_ON;
+        out_config->pd_cur_slp = RTC_CNTL_PD_CUR_SLEEP_ON;
+    } else {
         out_config->bias_sleep_monitor = RTC_CNTL_BIASSLP_MONITOR_DEFAULT;
-        out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT;
+        out_config->pd_cur_monitor = (sleep_flags & RTC_SLEEP_USE_ADC_TESEN_MONITOR)?
+                                    RTC_CNTL_PD_CUR_MONITOR_ON : RTC_CNTL_PD_CUR_MONITOR_DEFAULT;
+
         out_config->bias_sleep_slp = RTC_CNTL_BIASSLP_SLEEP_DEFAULT;
-        out_config->pd_cur_monitor = RTC_CNTL_PD_CUR_MONITOR_DEFAULT;
         out_config->pd_cur_slp = RTC_CNTL_PD_CUR_SLEEP_DEFAULT;
-    } else {
-        out_config->dig_dbias_wak = RTC_CNTL_DBIAS_1V10;
-        out_config->dig_dbias_slp = !(sleep_flags & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DBIAS_1V10 : RTC_CNTL_DBIAS_SLP;
-        out_config->rtc_dbias_wak = RTC_CNTL_DBIAS_1V10;
-        out_config->rtc_dbias_slp = !(sleep_flags & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DBIAS_1V10 : RTC_CNTL_DBIAS_SLP;
-
-        out_config->dbg_atten_monitor = RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT;
-        out_config->bias_sleep_monitor = RTC_CNTL_BIASSLP_MONITOR_DEFAULT;
-        out_config->dbg_atten_slp = (sleep_flags & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT : RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP;
-        out_config->bias_sleep_slp = !(sleep_flags & RTC_SLEEP_PD_XTAL) ? RTC_CNTL_BIASSLP_SLEEP_ON : RTC_CNTL_BIASSLP_SLEEP_DEFAULT;
-        out_config->pd_cur_monitor = RTC_CNTL_PD_CUR_MONITOR_DEFAULT;
-        out_config->pd_cur_slp = !(sleep_flags & RTC_SLEEP_PD_XTAL) ? RTC_CNTL_PD_CUR_SLEEP_ON : RTC_CNTL_PD_CUR_SLEEP_DEFAULT;
     }
 }
 
@@ -141,10 +192,10 @@ void rtc_sleep_init(rtc_sleep_config_t cfg)
         CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_PD_EN);
     }
 
+    assert(!cfg.pd_cur_monitor || cfg.bias_sleep_monitor);
+    assert(!cfg.pd_cur_slp || cfg.bias_sleep_slp);
     REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG_SLEEP, cfg.rtc_dbias_slp);
-    REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG, cfg.rtc_dbias_wak);
     REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG_SLEEP, cfg.dig_dbias_slp);
-    REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG, cfg.dig_dbias_wak);
 
     REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_MONITOR, cfg.dbg_atten_monitor);
     REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_BIAS_SLEEP_MONITOR, cfg.bias_sleep_monitor);
@@ -154,7 +205,6 @@ void rtc_sleep_init(rtc_sleep_config_t cfg)
     REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_PD_CUR_DEEP_SLP, cfg.pd_cur_slp);
 
     if (cfg.deep_slp) {
-        CLEAR_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU);
         SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN);
         CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG,
                             RTC_CNTL_CKGEN_I2C_PU | RTC_CNTL_PLL_I2C_PU |
@@ -162,12 +212,12 @@ void rtc_sleep_init(rtc_sleep_config_t cfg)
         CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BB_I2C_FORCE_PU);
     } else {
         REG_SET_FIELD(RTC_CNTL_REGULATOR_DRV_CTRL_REG, RTC_CNTL_DG_VDD_DRV_B_SLP, RTC_CNTL_DG_VDD_DRV_B_SLP_DEFAULT);
-        SET_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU);
         CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN);
     }
     /* mem force pu */
     SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_LSLP_MEM_FORCE_PU);
 
+    REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU, cfg.rtc_regulator_fpu);
     if (!cfg.int_8m_pd_en) {
         REG_SET_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU);
     } else {

components/esp_system/test_apps/rtc_power_modes/CMakeLists.txt

@@ -0,0 +1,5 @@
+# This is the project CMakeLists.txt file for the test subproject
+cmake_minimum_required(VERSION 3.5)
+
+include($ENV{IDF_PATH}/tools/cmake/project.cmake)
+project(rtc_power_modes)

components/esp_system/test_apps/rtc_power_modes/README.md

@@ -0,0 +1,19 @@
+| Supported Targets | ESP32-S3 |
+| ----------------- | -------- |
+
+# RTC power test
+
+This test app is to enter 7 different sub power modes we have, so that the power consumption under different power modes can be measured.
+
+Currently there are 6 sub power modes, 3 for deepsleep and 3 for lightsleep. Show as below (priority from high to low).
+
+## Deepsleep
+1. Mode for ADC/Temp Sensor in monitor mode (ULP). To enable this mode, call `rtc_sleep_enable_adc_tesn_monitor`.
+2. Default mode.
+3. Ultra low power mode. To enable this mode, call `rtc_sleep_enable_ultra_low`. Note if mode 1 has higher priority than this.
+
+## Lightsleep
+1. Mode for using 40 MHz XTAL in lightsleep. To enable this mode, call `esp_sleep_pd_config(ESP_PD_DOMAIN_XTAL, ESP_PD_OPTION_ON)`.
+2. Mode for using 8M clock by digital system (peripherals). To enable this mode, initialize LEDC with 8M clock source.
+3. Mode for ADC/Temp Sensor in monitor mode (ULP). To enable this mdoe, call `rtc_sleep_enable_adc_tesn_monitor`.
+4. Default mode.

components/esp_system/test_apps/rtc_power_modes/main/CMakeLists.txt

@@ -0,0 +1,7 @@
+set(srcs "test_app_main.c"
+         "test_rtc_power.c")
+
+# In order for the cases defined by `TEST_CASE` to be linked into the final elf,
+# the component can be registered as WHOLE_ARCHIVE
+idf_component_register(SRCS ${srcs}
+                       WHOLE_ARCHIVE)

components/esp_system/test_apps/rtc_power_modes/main/test_app_main.c

@@ -0,0 +1,27 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "unity.h"
+#include "unity_test_runner.h"
+#include "unity_test_utils.h"
+
+#define LEAKS (400)
+
+
+void setUp(void)
+{
+    unity_utils_record_free_mem();
+}
+
+void tearDown(void)
+{
+    unity_utils_evaluate_leaks_direct(LEAKS);
+}
+
+void app_main(void)
+{
+    unity_run_menu();
+}

components/esp_system/test_apps/rtc_power_modes/main/test_rtc_power.c

@@ -0,0 +1,120 @@
+/*
+ * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdio.h>
+#include <string.h>
+#include "esp_sleep.h"
+#include "unity.h"
+#include "unity_test_utils.h"
+#include "esp_log.h"
+#include "freertos/task.h"
+#include "driver/uart.h"
+#include "freertos/FreeRTOS.h"
+#include "soc/soc_caps.h"
+#include "driver/ledc.h"
+#include "soc/rtc.h"
+
+static const char TAG[] = "rtc_power";
+
+static void test_deepsleep(void)
+{
+    esp_sleep_enable_timer_wakeup(2000000);
+    ESP_LOGI(TAG, "Entering deep sleep");
+    esp_deep_sleep_start();
+}
+
+TEST_CASE("Power Test: Deepsleep (with ADC/TSEN in monitor)", "[pm]")
+{
+    rtc_dig_clk8m_disable();    //This is workaround for bootloader not disable 8M as digital clock source
+
+    extern void rtc_sleep_enable_adc_tesn_monitor(bool);
+    rtc_sleep_enable_adc_tesn_monitor(true);
+    test_deepsleep();
+}
+
+TEST_CASE("Power Test: Deepsleep (default)", "[pm]")
+{
+    rtc_dig_clk8m_disable();    //This is workaround for bootloader not disable 8M as digital clock source
+
+    test_deepsleep();
+}
+
+TEST_CASE("Power Test: Deepsleep (ultra-low power)", "[pm]")
+{
+    rtc_dig_clk8m_disable();    //This is workaround for bootloader not disable 8M as digital clock source
+
+    extern void rtc_sleep_enable_ultra_low(bool);
+    rtc_sleep_enable_ultra_low(true);
+    test_deepsleep();
+}
+
+static void test_lightsleep(void)
+{
+    esp_sleep_enable_timer_wakeup(2000000);
+
+    while (true) {
+        printf("Entering light sleep\n");
+        /* To make sure the complete line is printed before entering sleep mode,
+         * need to wait until UART TX FIFO is empty:
+         */
+        uart_wait_tx_idle_polling(CONFIG_ESP_CONSOLE_UART_NUM);
+
+        /* Enter sleep mode */
+        esp_light_sleep_start();
+
+        /* Determine wake up reason */
+        const char* wakeup_reason;
+        switch (esp_sleep_get_wakeup_cause()) {
+            case ESP_SLEEP_WAKEUP_TIMER:
+                wakeup_reason = "timer";
+                break;
+            default:
+                wakeup_reason = "other";
+                break;
+        }
+        printf("Returned from light sleep, reason: %s\n", wakeup_reason);
+
+        vTaskDelay(1000/portTICK_PERIOD_MS);
+    }
+}
+
+TEST_CASE("Power Test: Lightsleep (XTAL 40M)", "[pm]")
+{
+    rtc_dig_clk8m_disable();    //This is workaround for bootloader not disable 8M as digital clock source
+
+    esp_sleep_pd_config(ESP_PD_DOMAIN_XTAL, ESP_PD_OPTION_ON);
+    test_lightsleep();
+}
+
+TEST_CASE("Power Test: Lightsleep (8M by digital)", "[pm]")
+{
+    rtc_dig_clk8m_disable();    //This is workaround for bootloader not disable 8M as digital clock source
+
+    ledc_timer_config_t config = {
+        .speed_mode = LEDC_LOW_SPEED_MODE,
+        .duty_resolution = LEDC_TIMER_12_BIT,
+        .timer_num = 0,
+        .freq_hz = 2 * 1000,
+        .clk_cfg = LEDC_USE_RTC8M_CLK,
+    };
+    ledc_timer_config(&config);
+    test_lightsleep();
+}
+
+TEST_CASE("Power Test: Lightsleep (with ADC/TSEN in monitor)", "[pm]")
+{
+    rtc_dig_clk8m_disable();    //This is workaround for bootloader not disable 8M as digital clock source
+
+    extern void rtc_sleep_enable_adc_tesn_monitor(bool);
+    rtc_sleep_enable_adc_tesn_monitor(true);
+    test_lightsleep();
+}
+
+TEST_CASE("Power Test: Lightsleep (default)", "[pm]")
+{
+    rtc_dig_clk8m_disable();    //This is workaround for bootloader not disable 8M as digital clock source
+    test_lightsleep();
+}

components/esp_system/test_apps/rtc_power_modes/pytest_rtc_power.py

@@ -0,0 +1,48 @@
+# SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
+# SPDX-License-Identifier: CC0-1.0
+
+import pytest
+from pytest_embedded import Dut
+
+# This is a manual test, not run on CI
+
+
+def deepsleep_test(dut: Dut, case_name: str) -> None:
+    dut.expect_exact('Press ENTER to see the list of tests')
+    dut.write(case_name)
+    reset_reason = 'DEEPSLEEP_RESET' if dut.target == 'esp32' else 'DSLEEP'
+    if dut.target == 'esp32c3':
+        # Known issue: IDF-5003
+        dut.expect(r'rst:.*\(%s\)' % reset_reason, timeout=40)
+    else:
+        dut.expect(r'rst:.*\(%s\)' % reset_reason, timeout=10)
+
+
+@pytest.mark.deepsleep
+def test_rtc_8md256_deepsleep(dut: Dut) -> None:
+    deepsleep_test(dut, '"Can use 8MD256 as RTC clock source in deepsleep"')
+
+
+@pytest.mark.deepsleep
+def test_rtc_8md256_deepsleep_force_rtcperiph(dut: Dut) -> None:
+    deepsleep_test(dut, '"Can use 8MD256 as RTC clock source in deepsleep (force rtc_periph)"')
+
+
+def lightsleep_test(dut: Dut, case_name: str) -> None:
+    dut.expect_exact('Press ENTER to see the list of tests')
+    dut.write(case_name)
+    if dut.target == 'esp32c3':
+        # Known issue: IDF-5003
+        dut.expect(r'Returned from light sleep, reason: timer', timeout=40)
+    else:
+        dut.expect(r'Returned from light sleep, reason: timer', timeout=10)
+
+
+@pytest.mark.deepsleep
+def test_rtc_8md256_lightsleep(dut: Dut) -> None:
+    lightsleep_test(dut, '"Can use 8MD256 as RTC clock source in lightsleep"')
+
+
+@pytest.mark.deepsleep
+def test_rtc_8md256_lightsleep_force_rtcperiph(dut: Dut) -> None:
+    lightsleep_test(dut, '"Can use 8MD256 as RTC clock source in lightsleep (force rtc_periph)"')

components/esp_system/test_apps/rtc_power_modes/sdkconfig.defaults

@@ -0,0 +1,2 @@
+CONFIG_FREERTOS_HZ=1000
+CONFIG_ESP_TASK_WDT=n

components/soc/esp32s3/include/soc/rtc.h

@@ -112,16 +112,21 @@ set sleep_init default param
 */
 #define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT  5
 #define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP  0
-#define RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT  15
+#define RTC_CNTL_DBG_ATTEN_DEEPSLEEP_NODROP  0
+#define RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT  14
+#define RTC_CNTL_DBG_ATTEN_DEEPSLEEP_ULTRA_LOW 15
 #define RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT  0
-#define RTC_CNTL_BIASSLP_MONITOR_DEFAULT  0
+#define RTC_CNTL_BIASSLP_MONITOR_ON  0
+#define RTC_CNTL_BIASSLP_MONITOR_DEFAULT  1
 #define RTC_CNTL_BIASSLP_SLEEP_ON  0
 #define RTC_CNTL_BIASSLP_SLEEP_DEFAULT  1
+#define RTC_CNTL_PD_CUR_MONITOR_ON  0
 #define RTC_CNTL_PD_CUR_MONITOR_DEFAULT  1
 #define RTC_CNTL_PD_CUR_SLEEP_ON  0
 #define RTC_CNTL_PD_CUR_SLEEP_DEFAULT  1
 #define RTC_CNTL_DG_VDD_DRV_B_SLP_DEFAULT 0xf
 
+
 /**
  * @brief Possible main XTAL frequency values.
  *
@@ -585,9 +590,7 @@ typedef struct {
     uint32_t dig_peri_pd_en : 1;        //!< power down digital peripherals
     uint32_t deep_slp : 1;              //!< power down digital domain
     uint32_t wdt_flashboot_mod_en : 1;  //!< enable WDT flashboot mode
-    uint32_t dig_dbias_wak : 5;         //!< set bias for digital domain, in active mode
     uint32_t dig_dbias_slp : 5;         //!< set bias for digital domain, in sleep mode
-    uint32_t rtc_dbias_wak : 5;         //!< set bias for RTC domain, in active mode
     uint32_t rtc_dbias_slp : 5;         //!< set bias for RTC domain, in sleep mode
     uint32_t dbg_atten_monitor : 4;     //!< voltage parameter, in monitor mode
     uint32_t bias_sleep_monitor : 1;    //!< circuit control parameter, in monitor mode
@@ -597,6 +600,7 @@ typedef struct {
     uint32_t pd_cur_slp : 1;            //!< circuit control parameter, in sleep mode
     uint32_t vddsdio_pd_en : 1;         //!< power down VDDSDIO regulator
     uint32_t xtal_fpu : 1;              //!< keep main XTAL powered up in sleep
+    uint32_t rtc_regulator_fpu  : 1;    //!< keep rtc regulator powered up in sleep
     uint32_t deep_slp_reject : 1;       //!< enable deep sleep reject
     uint32_t light_slp_reject : 1;      //!< enable light sleep reject
 } rtc_sleep_config_t;