spi_flash:bringup some flash supports for esp32s3

components/hal/CMakeLists.txt

@@ -58,6 +58,7 @@ if(NOT BOOTLOADER_BUILD)
 
     if(${target} STREQUAL "esp32s3")
         list(APPEND srcs
+            "spi_flash_hal_gpspi.c"
             "esp32s3/brownout_hal.c"
             "esp32s3/systimer_hal.c"
             "esp32s3/touch_sensor_hal.c")

components/hal/spi_flash_hal_iram.c

@@ -68,6 +68,8 @@ bool spi_flash_hal_host_idle(spi_flash_host_inst_t *host)
         idle &= spi_flash_ll_host_idle(&SPI0);
 #elif CONFIG_IDF_TARGET_ESP32S2
         idle &= spi_flash_ll_host_idle(&SPIMEM0);
+#elif CONFIG_IDF_TARGET_ESP32S3
+        idle &= spi_flash_ll_host_idle(&SPIMEM0);
 #endif
     }
 

components/soc/soc/esp32s3/include/soc/spi_caps.h

@@ -50,6 +50,6 @@
 #define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(spi_dev)  (!((void*)spi_dev == (void*)&GPSPI3))
 
 // Peripheral supports output given level during its "dummy phase"
-#define SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUTPUT(spi_dev)    ((void*)spi_dev == (void*)&SPIMEM1)
+#define SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUTPUT(spi_dev)    (!((void*)spi_dev == (void*)&SPIMEM1))
 
 #define SOC_MEMSPI_IS_INDEPENDENT 1

components/spi_flash/test/test_esp_flash.c

@@ -61,6 +61,26 @@ static uint8_t sector_buf[4096];
 #define FSPI_PIN_NUM_WP     38
 #define FSPI_PIN_NUM_CS     34
 
+// Just use the same pins for HSPI
+#define HSPI_PIN_NUM_MOSI   FSPI_PIN_NUM_MOSI
+#define HSPI_PIN_NUM_MISO   FSPI_PIN_NUM_MISO
+#define HSPI_PIN_NUM_CLK    FSPI_PIN_NUM_CLK
+#define HSPI_PIN_NUM_HD     FSPI_PIN_NUM_HD
+#define HSPI_PIN_NUM_WP     FSPI_PIN_NUM_WP
+#define HSPI_PIN_NUM_CS     FSPI_PIN_NUM_CS
+
+#elif CONFIG_IDF_TARGET_ESP32S3
+#define SPI1_CS_IO          26  //the pin which is usually used by the PSRAM cs
+#define SPI1_HD_IO          27  //the pin which is usually used by the PSRAM hd
+#define SPI1_WP_IO          28  //the pin which is usually used by the PSRAM wp
+
+#define FSPI_PIN_NUM_MOSI   35
+#define FSPI_PIN_NUM_MISO   37
+#define FSPI_PIN_NUM_CLK    36
+#define FSPI_PIN_NUM_HD     33
+#define FSPI_PIN_NUM_WP     38
+#define FSPI_PIN_NUM_CS     34
+
 // Just use the same pins for HSPI
 #define HSPI_PIN_NUM_MOSI   FSPI_PIN_NUM_MOSI
 #define HSPI_PIN_NUM_MISO   FSPI_PIN_NUM_MISO
@@ -165,6 +185,29 @@ flashtest_config_t config_list[] = {
     //     .input_delay_ns = 20,
     // },
 };
+#elif CONFIG_IDF_TARGET_ESP32S3
+flashtest_config_t config_list[] = {
+    FLASHTEST_CONFIG_COMMON,
+    /* No runners for esp32s2 for these config yet */
+    {
+        .io_mode = TEST_SPI_READ_MODE,
+        .speed = TEST_SPI_SPEED,
+        .host_id = FSPI_HOST,
+        .cs_id = 0,
+        .cs_io_num = FSPI_PIN_NUM_CS,
+        .input_delay_ns = 0,
+    },
+    // /* current runner doesn't have a flash on HSPI */
+    // {
+    //     .io_mode = TEST_SPI_READ_MODE,
+    //     .speed = TEST_SPI_SPEED,
+    //     .host_id = HSPI_HOST,
+    //     .cs_id = 0,
+    //     // uses GPIO matrix on esp32s2 regardles if FORCE_GPIO_MATRIX
+    //     .cs_io_num = HSPI_PIN_NUM_CS,
+    //     .input_delay_ns = 20,
+    // },
+};
 #endif
 
 static void get_chip_host(esp_flash_t* chip, spi_host_device_t* out_host_id, int* out_cs_id)
@@ -253,7 +296,7 @@ static void setup_bus(spi_host_device_t host_id)
         gpio_set_level(HSPI_PIN_NUM_WP, 1);
 #endif
     }
-#if !DISABLED_FOR_TARGETS(ESP32S2)
+#if !DISABLED_FOR_TARGETS(ESP32S2, ESP32S3)
     else if (host_id == VSPI_HOST) {
         ESP_LOGI(TAG, "setup flash on SPI%d (VSPI) CS0...\n", host_id + 1);
         spi_bus_config_t vspi_bus_cfg = {