soc: Fix esp_ptr_executable() for single core ESP32 config & cache memory

In single core mode, APP CPU cache region is added to the available range.

components/soc/include/soc/soc_memory_layout.h

@@ -155,6 +155,10 @@ inline static bool IRAM_ATTR esp_ptr_executable(const void *p)
     intptr_t ip = (intptr_t) p;
     return (ip >= SOC_IROM_LOW && ip < SOC_IROM_HIGH)
         || (ip >= SOC_IRAM_LOW && ip < SOC_IRAM_HIGH)
+        || (ip >= SOC_IROM_MASK_LOW && ip < SOC_IROM_MASK_HIGH)
+#if defined(SOC_CACHE_APP_LOW) && defined(CONFIG_FREERTOS_UNICORE)
+        || (ip >= SOC_CACHE_APP_LOW && ip < SOC_CACHE_APP_HIGH)
+#endif
         || (ip >= SOC_RTC_IRAM_LOW && ip < SOC_RTC_IRAM_HIGH);
 }