Merge branch 'feature/efuse_add_voltage_level' into 'master'

feature(efuse): add support for setting core voltage in high performance cases

See merge request idf/esp-idf!4124

components/soc/esp32/include/soc/efuse_reg.h

@@ -205,12 +205,28 @@
 #define EFUSE_RD_FLASH_CRYPT_CONFIG_M  ((EFUSE_RD_FLASH_CRYPT_CONFIG_V)<<(EFUSE_RD_FLASH_CRYPT_CONFIG_S))
 #define EFUSE_RD_FLASH_CRYPT_CONFIG_V  0xF
 #define EFUSE_RD_FLASH_CRYPT_CONFIG_S  28
+/* EFUSE_RD_DIG_VOL_L6: RO; bitpos:[27:24]; */
+/*descritpion: This field stores the difference between the digital regulator voltage at level6 and 1.2 V. (RO) 
+  BIT[27] is the sign bit, 0: + , 1: -
+  BIT[26:24] is the difference value, unit: 0.017V 
+  volt_lv6 = BIT[27] ? 1.2 - BIT[26:24] * 0.017 : 1.2 + BIT[26:24] * 0.017     */
+#define EFUSE_RD_DIG_VOL_L6          0x0F
+#define EFUSE_RD_DIG_VOL_L6_M        ((EFUSE_RD_DIG_VOL_L6_V)<<(EFUSE_RD_DIG_VOL_L6_S))
+#define EFUSE_RD_DIG_VOL_L6_V        0x0F
+#define EFUSE_RD_DIG_VOL_L6_S        24
+/* EFUSE_RD_VOL_LEVEL_HP_INV: RO; bitpos:[23:22] */
+/*description: This field stores the voltage level for CPU to run at 240 MHz, or for flash/PSRAM to run at 80 MHz. 
+0x0: level 7; 0x1: level 6; 0x2: level 5; 0x3: level 4. (RO)*/
+#define EFUSE_RD_VOL_LEVEL_HP_INV    0x03
+#define EFUSE_RD_VOL_LEVEL_HP_INV_M  ((EFUSE_RD_VOL_LEVEL_HP_INV_V)<<(EFUSE_RD_VOL_LEVEL_HP_INV_S))
+#define EFUSE_RD_VOL_LEVEL_HP_INV_V  0x03
+#define EFUSE_RD_VOL_LEVEL_HP_INV_S  22
 /* EFUSE_RD_INST_CONFIG : RO ;bitpos:[27:20] ;default: 8'b0 ; */
-/*description: */
-#define EFUSE_RD_INST_CONFIG  0x000000FF
-#define EFUSE_RD_INST_CONFIG_M  ((EFUSE_RD_INST_CONFIG_V)<<(EFUSE_RD_INST_CONFIG_S))
-#define EFUSE_RD_INST_CONFIG_V  0xFF
-#define EFUSE_RD_INST_CONFIG_S  20
+/* Deprecated */
+#define EFUSE_RD_INST_CONFIG  0x000000FF                                              /** Deprecated **/
+#define EFUSE_RD_INST_CONFIG_M  ((EFUSE_RD_INST_CONFIG_V)<<(EFUSE_RD_INST_CONFIG_S))  /** Deprecated **/
+#define EFUSE_RD_INST_CONFIG_V  0xFF                                                  /** Deprecated **/
+#define EFUSE_RD_INST_CONFIG_S  20                                                    /** Deprecated **/
 /* EFUSE_RD_SPI_PAD_CONFIG_CS0 : RO ;bitpos:[19:15] ;default: 5'b0 ; */
 /*description: read for SPI_pad_config_cs0*/
 #define EFUSE_RD_SPI_PAD_CONFIG_CS0  0x0000001F
@@ -464,12 +480,28 @@
 #define EFUSE_FLASH_CRYPT_CONFIG_M  ((EFUSE_FLASH_CRYPT_CONFIG_V)<<(EFUSE_FLASH_CRYPT_CONFIG_S))
 #define EFUSE_FLASH_CRYPT_CONFIG_V  0xF
 #define EFUSE_FLASH_CRYPT_CONFIG_S  28
+/* EFUSE_DIG_VOL_L6: R/W; bitpos:[27:24]; */
+/*descritpion: This field stores the difference between the digital regulator voltage at level6 and 1.2 V. (R/W) 
+  BIT[27] is the sign bit, 0: + , 1: -
+  BIT[26:24] is the difference value, unit: 0.017V 
+  volt_lv6 = BIT[27] ? 1.2 - BIT[26:24] * 0.017 : 1.2 + BIT[26:24] * 0.017     */
+#define EFUSE_DIG_VOL_L6            0x0F
+#define EFUSE_DIG_VOL_L6_M          ((EFUSE_RD_DIG_VOL_L6_V)<<(EFUSE_RD_DIG_VOL_L6_S))
+#define EFUSE_DIG_VOL_L6_V          0x0F
+#define EFUSE_DIG_VOL_L6_S          24
+/* EFUSE_VOL_LEVEL_HP_INV: R/W; bitpos:[23:22] */
+/*description: This field stores the voltage level for CPU to run at 240 MHz, or for flash/PSRAM to run at 80 MHz. 
+0x0: level 7; 0x1: level 6; 0x2: level 5; 0x3: level 4. (R/W)*/
+#define EFUSE_VOL_LEVEL_HP_INV      0x03
+#define EFUSE_VOL_LEVEL_HP_INV_M    ((EFUSE_RD_VOL_LEVEL_HP_INV_V)<<(EFUSE_RD_VOL_LEVEL_HP_INV_S))
+#define EFUSE_VOL_LEVEL_HP_INV_V    0x03
+#define EFUSE_VOL_LEVEL_HP_INV_S    22
 /* EFUSE_INST_CONFIG : R/W ;bitpos:[27:20] ;default: 8'b0 ; */
-/*description: */
-#define EFUSE_INST_CONFIG  0x000000FF
-#define EFUSE_INST_CONFIG_M  ((EFUSE_INST_CONFIG_V)<<(EFUSE_INST_CONFIG_S))
-#define EFUSE_INST_CONFIG_V  0xFF
-#define EFUSE_INST_CONFIG_S  20
+/* Deprecated */
+#define EFUSE_INST_CONFIG  0x000000FF                                        /** Deprecated **/
+#define EFUSE_INST_CONFIG_M  ((EFUSE_INST_CONFIG_V)<<(EFUSE_INST_CONFIG_S))  /** Deprecated **/
+#define EFUSE_INST_CONFIG_V  0xFF                                            /** Deprecated **/
+#define EFUSE_INST_CONFIG_S  20                                              /** Deprecated **/
 /* EFUSE_SPI_PAD_CONFIG_CS0 : R/W ;bitpos:[19:15] ;default: 5'b0 ; */
 /*description: program for SPI_pad_config_cs0*/
 #define EFUSE_SPI_PAD_CONFIG_CS0  0x0000001F

components/soc/esp32/rtc_clk.c

@@ -85,13 +85,16 @@
 /* Core voltage needs to be increased in two cases:
  * 1. running at 240 MHz
  * 2. running with 80MHz Flash frequency
+ * 
+ * There is a record in efuse which indicates the proper voltage for these two cases.
  */
+#define RTC_CNTL_DBIAS_HP_VOLT         (RTC_CNTL_DBIAS_1V25 - (REG_GET_FIELD(EFUSE_BLK0_RDATA5_REG, EFUSE_RD_VOL_LEVEL_HP_INV)))
 #ifdef CONFIG_ESPTOOLPY_FLASHFREQ_80M
-#define DIG_DBIAS_80M_160M  RTC_CNTL_DBIAS_1V25
+#define DIG_DBIAS_80M_160M  RTC_CNTL_DBIAS_HP_VOLT
 #else
 #define DIG_DBIAS_80M_160M  RTC_CNTL_DBIAS_1V10
 #endif
-#define DIG_DBIAS_240M      RTC_CNTL_DBIAS_1V25
+#define DIG_DBIAS_240M      RTC_CNTL_DBIAS_HP_VOLT
 #define DIG_DBIAS_XTAL      RTC_CNTL_DBIAS_1V10
 #define DIG_DBIAS_2M        RTC_CNTL_DBIAS_1V00