|
|
@@ -151,7 +151,8 @@ FORCE_INLINE_ATTR void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint3
|
|
|
*/
|
|
|
FORCE_INLINE_ATTR uint32_t uart_ll_get_baudrate(uart_dev_t *hw, uint32_t sclk_freq)
|
|
|
{
|
|
|
- uart_clkdiv_reg_t div_reg = hw->clkdiv;
|
|
|
+ uart_clkdiv_reg_t div_reg;
|
|
|
+ div_reg.val = hw->clkdiv.val;
|
|
|
return ((sclk_freq << 4)) /
|
|
|
(((div_reg.clkdiv << 4) | div_reg.clkdiv_frag) * (HAL_FORCE_READ_U32_REG_FIELD(hw->clk_conf, sclk_div_num) + 1));
|
|
|
}
|
|
|
@@ -803,7 +804,8 @@ FORCE_INLINE_ATTR void uart_ll_set_loop_back(uart_dev_t *hw, bool loop_back_en)
|
|
|
*/
|
|
|
FORCE_INLINE_ATTR void uart_ll_inverse_signal(uart_dev_t *hw, uint32_t inv_mask)
|
|
|
{
|
|
|
- uart_conf0_reg_t conf0_reg = hw->conf0;
|
|
|
+ uart_conf0_reg_t conf0_reg;
|
|
|
+ conf0_reg.val = hw->conf0.val;
|
|
|
conf0_reg.irda_tx_inv = (inv_mask & UART_SIGNAL_IRDA_TX_INV) ? 1 : 0;
|
|
|
conf0_reg.irda_rx_inv = (inv_mask & UART_SIGNAL_IRDA_RX_INV) ? 1 : 0;
|
|
|
conf0_reg.rxd_inv = (inv_mask & UART_SIGNAL_RXD_INV) ? 1 : 0;
|