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@@ -58,7 +58,7 @@
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#define APLL_CAL_DELAY_2 0x3f
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#define APLL_CAL_DELAY_3 0x1f
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-#define XTAL_32K_DAC_VAL 3
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+#define XTAL_32K_DAC_VAL 1
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#define XTAL_32K_DRES_VAL 3
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#define XTAL_32K_DBIAS_VAL 0
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@@ -114,36 +114,14 @@ static const char* TAG = "rtc_clk";
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static void rtc_clk_32k_enable_common(int dac, int dres, int dbias)
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{
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- CLEAR_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG,
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- RTC_IO_X32P_RDE | RTC_IO_X32P_RUE | RTC_IO_X32N_RUE |
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- RTC_IO_X32N_RDE | RTC_IO_X32N_MUX_SEL | RTC_IO_X32P_MUX_SEL);
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SET_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_X32N_MUX_SEL | RTC_IO_X32P_MUX_SEL);
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- /* Set the parameters of xtal
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- dac --> current
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- dres --> resistance
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- dbias --> bais voltage
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- */
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+ CLEAR_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG,
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+ RTC_IO_X32P_RDE | RTC_IO_X32P_RUE | RTC_IO_X32N_RUE |
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+ RTC_IO_X32N_RDE | RTC_IO_X32N_MUX_SEL | RTC_IO_X32P_MUX_SEL);
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REG_SET_FIELD(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_DAC_XTAL_32K, dac);
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REG_SET_FIELD(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_DRES_XTAL_32K, dres);
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REG_SET_FIELD(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_DBIAS_XTAL_32K, dbias);
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-
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-#ifdef CONFIG_ESP32_RTC_EXTERNAL_CRYSTAL_ADDITIONAL_CURRENT
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- /* TOUCH sensor can provide additional current to external XTAL.
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- In some case, X32N and X32P PAD don't have enough drive capability to start XTAL */
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- SET_PERI_REG_MASK(RTC_IO_TOUCH_CFG_REG, RTC_IO_TOUCH_XPD_BIAS_M);
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- /* Tie PAD Touch8 to VDD
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- NOTE: TOUCH8 and TOUCH9 register settings are reversed except for DAC, so we set RTC_IO_TOUCH_PAD9_REG here instead
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- */
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- SET_PERI_REG_MASK(RTC_IO_TOUCH_PAD9_REG, RTC_IO_TOUCH_PAD9_TIE_OPT_M);
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- /* Set the current used to compensate TOUCH PAD8 */
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- SET_PERI_REG_BITS(RTC_IO_TOUCH_PAD8_REG, RTC_IO_TOUCH_PAD8_DAC, 4, RTC_IO_TOUCH_PAD8_DAC_S);
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- /* Power up TOUCH8
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- So the Touch DAC start to drive some current from VDD to TOUCH8(which is also XTAL-N)
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- */
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- SET_PERI_REG_MASK(RTC_IO_TOUCH_PAD9_REG, RTC_IO_TOUCH_PAD9_XPD_M);
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-#endif // CONFIG_ESP32_RTC_EXTERNAL_CRYSTAL_ADDITIONAL_CURRENT
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- /* Power up external xtal */
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- SET_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_XPD_XTAL_32K_M);
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+ SET_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_XPD_XTAL_32K);
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}
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void rtc_clk_32k_enable(bool enable)
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@@ -151,12 +129,7 @@ void rtc_clk_32k_enable(bool enable)
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if (enable) {
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rtc_clk_32k_enable_common(XTAL_32K_DAC_VAL, XTAL_32K_DRES_VAL, XTAL_32K_DBIAS_VAL);
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} else {
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- /* Disable X32N and X32P pad drive external xtal */
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- CLEAR_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_XPD_XTAL_32K_M);
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-#ifdef CONFIG_ESP32_RTC_EXTERNAL_CRYSTAL_ADDITIONAL_CURRENT
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- /* Power down TOUCH */
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- CLEAR_PERI_REG_MASK(RTC_IO_TOUCH_PAD9_REG, RTC_IO_TOUCH_PAD9_XPD_M);
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-#endif // CONFIG_ESP32_RTC_EXTERNAL_CRYSTAL_ADDITIONAL_CURRENT
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+ CLEAR_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_XPD_XTAL_32K);
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}
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}
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