Merge branch 'esp32h2/enable_ecc_accelerator' into 'master'

esp32h2: Enable ECC accelerator

Closes IDF-3397

See merge request espressif/esp-idf!18647

components/hal/CMakeLists.txt

@@ -86,6 +86,10 @@ if(NOT BOOTLOADER_BUILD)
         list(APPEND srcs "lcd_hal.c")
     endif()
 
+    if(CONFIG_SOC_ECC_SUPPORTED)
+        list(APPEND srcs "ecc_hal.c")
+    endif()
+
     if(${target} STREQUAL "esp32")
         list(APPEND srcs
             "dac_hal.c"
@@ -158,7 +162,6 @@ if(NOT BOOTLOADER_BUILD)
 
     if(${target} STREQUAL "esp32c2")
         list(APPEND srcs
-              "ecc_hal.c"
               "spi_flash_hal_gpspi.c"
               "spi_slave_hd_hal.c"
               "esp32c2/brownout_hal.c"

components/hal/esp32h2/include/hal/clk_gate_ll.h

@@ -55,6 +55,8 @@ static inline uint32_t periph_ll_get_clk_en_mask(periph_module_t periph)
         return SYSTEM_CRYPTO_AES_CLK_EN;
     case PERIPH_SHA_MODULE:
         return SYSTEM_CRYPTO_SHA_CLK_EN;
+    case PERIPH_ECC_MODULE:
+        return SYSTEM_CRYPTO_ECC_CLK_EN;
     case PERIPH_RSA_MODULE:
         return SYSTEM_CRYPTO_RSA_CLK_EN;
     case PERIPH_HMAC_MODULE:
@@ -108,6 +110,8 @@ static inline uint32_t periph_ll_get_rst_en_mask(periph_module_t periph, bool en
         return SYSTEM_CRYPTO_HMAC_RST;
     case PERIPH_TEMPSENSOR_MODULE:
         return SYSTEM_TSENS_RST;
+    case PERIPH_ECC_MODULE:
+        return SYSTEM_CRYPTO_ECC_RST;
     case PERIPH_AES_MODULE:
         if (enable == true) {
             // Clear reset on digital signature, otherwise AES unit is held in reset also.
@@ -147,6 +151,7 @@ static uint32_t periph_ll_get_clk_en_reg(periph_module_t periph)
     case PERIPH_AES_MODULE:
     case PERIPH_RSA_MODULE:
     case PERIPH_SHA_MODULE:
+    case PERIPH_ECC_MODULE:
     case PERIPH_GDMA_MODULE:
     case PERIPH_TEMPSENSOR_MODULE:
         return SYSTEM_PERIP_CLK_EN1_REG;
@@ -165,6 +170,7 @@ static uint32_t periph_ll_get_rst_en_reg(periph_module_t periph)
     case PERIPH_AES_MODULE:
     case PERIPH_RSA_MODULE:
     case PERIPH_SHA_MODULE:
+    case PERIPH_ECC_MODULE:
     case PERIPH_GDMA_MODULE:
     case PERIPH_TEMPSENSOR_MODULE:
         return SYSTEM_PERIP_RST_EN1_REG;

components/hal/esp32h2/include/hal/ecc_ll.h

@@ -0,0 +1,147 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdbool.h>
+#include <string.h>
+#include "hal/assert.h"
+#include "rev2/soc/ecc_mult_reg.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    ECC_PARAM_PX = 0x0,
+    ECC_PARAM_PY,
+    ECC_PARAM_K,
+} ecc_ll_param_t;
+
+static inline void ecc_ll_enable_interrupt(void)
+{
+    REG_SET_FIELD(ECC_MULT_INT_ENA_REG, ECC_MULT_CALC_DONE_INT_ENA, 1);
+}
+
+static inline void ecc_ll_disable_interrupt(void)
+{
+    REG_SET_FIELD(ECC_MULT_INT_ENA_REG, ECC_MULT_CALC_DONE_INT_ENA, 0);
+}
+
+static inline void ecc_ll_clear_interrupt(void)
+{
+    REG_SET_FIELD(ECC_MULT_INT_CLR_REG, ECC_MULT_CALC_DONE_INT_CLR, 1);
+}
+
+static inline void ecc_ll_set_mode(ecc_mode_t mode)
+{
+    switch(mode) {
+        case ECC_MODE_POINT_MUL:
+            REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 0);
+            break;
+        case ECC_MODE_INVERSE_MUL:
+            REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 1);
+            break;
+        case ECC_MODE_VERIFY:
+            REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 2);
+            break;
+        case ECC_MODE_VERIFY_THEN_POINT_MUL:
+            REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 3);
+            break;
+        default:
+            HAL_ASSERT(false && "Unsupported mode");
+            break;
+    }
+}
+
+static inline void ecc_ll_set_curve(ecc_curve_t curve)
+{
+    switch(curve) {
+        case ECC_CURVE_SECP256R1:
+            REG_SET_BIT(ECC_MULT_CONF_REG, ECC_MULT_KEY_LENGTH);
+            break;
+        case ECC_CURVE_SECP192R1:
+            REG_CLR_BIT(ECC_MULT_CONF_REG, ECC_MULT_KEY_LENGTH);
+            break;
+        default:
+            HAL_ASSERT(false && "Unsupported curve");
+            return;
+    }
+}
+
+static inline void ecc_ll_write_param(ecc_ll_param_t param, const uint8_t *buf, uint16_t len)
+{
+    uint32_t reg;
+    uint32_t word;
+    switch (param) {
+        case ECC_PARAM_PX:
+            reg = ECC_MULT_PX_1_REG;
+            break;
+        case ECC_PARAM_PY:
+            reg = ECC_MULT_PY_1_REG;
+            break;
+        case ECC_PARAM_K:
+            reg = ECC_MULT_K_1_REG;
+            break;
+        default:
+            HAL_ASSERT(false && "Invalid parameter");
+            return;
+    }
+
+    for (int i = 0; i < len; i += 4) {
+        memcpy(&word, buf + i, 4);
+        REG_WRITE(reg + i, word);
+    }
+}
+
+static inline void ecc_ll_start_calc(void)
+{
+    REG_SET_BIT(ECC_MULT_CONF_REG, ECC_MULT_START);
+}
+
+static inline int ecc_ll_is_calc_finished(void)
+{
+    return REG_GET_FIELD(ECC_MULT_INT_RAW_REG, ECC_MULT_CALC_DONE_INT_RAW);
+}
+
+static inline ecc_mode_t ecc_ll_get_mode(void)
+{
+    return REG_GET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE);
+}
+
+static inline int ecc_ll_get_verification_result(void)
+{
+    return REG_GET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_VERIFICATION_RESULT);
+}
+
+static inline ecc_curve_t ecc_ll_get_curve(void)
+{
+    return REG_GET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_KEY_LENGTH);
+}
+
+static inline void ecc_ll_read_param(ecc_ll_param_t param, uint8_t *buf, uint16_t len)
+{
+    uint32_t reg;
+    switch (param) {
+        case ECC_PARAM_PX:
+            reg = ECC_MULT_PX_1_REG;
+            break;
+        case ECC_PARAM_PY:
+            reg = ECC_MULT_PY_1_REG;
+            break;
+        case ECC_PARAM_K:
+            reg = ECC_MULT_K_1_REG;
+            break;
+        default:
+            HAL_ASSERT(false && "Invalid parameter");
+            return;
+    }
+
+    memcpy(buf, (void *)reg, len);
+}
+
+#ifdef __cplusplus
+}
+#endif

components/mbedtls/port/ecc/esp_ecc.c

@@ -7,9 +7,6 @@
 #include <string.h>
 #include <stdio.h>
 
-#include "soc/ecc_mult_reg.h"
-#include "soc/system_reg.h"
-
 #include "esp_private/periph_ctrl.h"
 #include "ecc_impl.h"
 #include "hal/ecc_hal.h"

components/soc/esp32h2/include/rev2/soc/ecc_mult_reg.h

@@ -6,126 +6,289 @@
 
 #pragma once
 
-#include <stdint.h>
 #include "soc/soc.h"
+
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-/** ECC_MULT_INT_RAW_REG register
- *  ECC interrupt raw register, valid in level.
- */
-#define ECC_MULT_INT_RAW_REG (DR_REG_ECC_MULT_BASE + 0xc)
-/** ECC_MULT_CALC_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
- *  The raw interrupt status bit  for the ecc calculate done interrupt
- */
+
+#define ECC_MULT_INT_RAW_REG          (DR_REG_ECC_MULT_BASE + 0xC)
+/* ECC_MULT_CALC_DONE_INT_RAW : RO/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit  for the ecc calculate done interrupt.*/
 #define ECC_MULT_CALC_DONE_INT_RAW    (BIT(0))
-#define ECC_MULT_CALC_DONE_INT_RAW_M  (ECC_MULT_CALC_DONE_INT_RAW_V << ECC_MULT_CALC_DONE_INT_RAW_S)
-#define ECC_MULT_CALC_DONE_INT_RAW_V  0x00000001U
+#define ECC_MULT_CALC_DONE_INT_RAW_M  (BIT(0))
+#define ECC_MULT_CALC_DONE_INT_RAW_V  0x1
 #define ECC_MULT_CALC_DONE_INT_RAW_S  0
 
-/** ECC_MULT_INT_ST_REG register
- *  ECC interrupt status register.
- */
-#define ECC_MULT_INT_ST_REG (DR_REG_ECC_MULT_BASE + 0x10)
-/** ECC_MULT_CALC_DONE_INT_ST : RO; bitpos: [0]; default: 0;
- *  The masked interrupt status bit  for the ecc calculate done interrupt
- */
+#define ECC_MULT_INT_ST_REG          (DR_REG_ECC_MULT_BASE + 0x10)
+/* ECC_MULT_CALC_DONE_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The masked interrupt status bit  for the ecc calculate done interrupt.*/
 #define ECC_MULT_CALC_DONE_INT_ST    (BIT(0))
-#define ECC_MULT_CALC_DONE_INT_ST_M  (ECC_MULT_CALC_DONE_INT_ST_V << ECC_MULT_CALC_DONE_INT_ST_S)
-#define ECC_MULT_CALC_DONE_INT_ST_V  0x00000001U
+#define ECC_MULT_CALC_DONE_INT_ST_M  (BIT(0))
+#define ECC_MULT_CALC_DONE_INT_ST_V  0x1
 #define ECC_MULT_CALC_DONE_INT_ST_S  0
 
-/** ECC_MULT_INT_ENA_REG register
- *  ECC interrupt enable register.
- */
-#define ECC_MULT_INT_ENA_REG (DR_REG_ECC_MULT_BASE + 0x14)
-/** ECC_MULT_CALC_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  The interrupt enable bit  for the ecc calculate done interrupt
- */
+#define ECC_MULT_INT_ENA_REG          (DR_REG_ECC_MULT_BASE + 0x14)
+/* ECC_MULT_CALC_DONE_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The interrupt enable bit  for the ecc calculate done interrupt.*/
 #define ECC_MULT_CALC_DONE_INT_ENA    (BIT(0))
-#define ECC_MULT_CALC_DONE_INT_ENA_M  (ECC_MULT_CALC_DONE_INT_ENA_V << ECC_MULT_CALC_DONE_INT_ENA_S)
-#define ECC_MULT_CALC_DONE_INT_ENA_V  0x00000001U
+#define ECC_MULT_CALC_DONE_INT_ENA_M  (BIT(0))
+#define ECC_MULT_CALC_DONE_INT_ENA_V  0x1
 #define ECC_MULT_CALC_DONE_INT_ENA_S  0
 
-/** ECC_MULT_INT_CLR_REG register
- *  ECC interrupt clear register.
- */
-#define ECC_MULT_INT_CLR_REG (DR_REG_ECC_MULT_BASE + 0x18)
-/** ECC_MULT_CALC_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
- *  Set this bit to clear the ecc calculate done interrupt
- */
+#define ECC_MULT_INT_CLR_REG          (DR_REG_ECC_MULT_BASE + 0x18)
+/* ECC_MULT_CALC_DONE_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set this bit to clear the ecc calculate done interrupt.*/
 #define ECC_MULT_CALC_DONE_INT_CLR    (BIT(0))
-#define ECC_MULT_CALC_DONE_INT_CLR_M  (ECC_MULT_CALC_DONE_INT_CLR_V << ECC_MULT_CALC_DONE_INT_CLR_S)
-#define ECC_MULT_CALC_DONE_INT_CLR_V  0x00000001U
+#define ECC_MULT_CALC_DONE_INT_CLR_M  (BIT(0))
+#define ECC_MULT_CALC_DONE_INT_CLR_V  0x1
 #define ECC_MULT_CALC_DONE_INT_CLR_S  0
 
-/** ECC_MULT_CONF_REG register
- *  ECC configure register
- */
-#define ECC_MULT_CONF_REG (DR_REG_ECC_MULT_BASE + 0x1c)
-/** ECC_MULT_START : R/W/SC; bitpos: [0]; default: 0;
- *  Set this bit to start a ECC operation.
- */
-#define ECC_MULT_START    (BIT(0))
-#define ECC_MULT_START_M  (ECC_MULT_START_V << ECC_MULT_START_S)
-#define ECC_MULT_START_V  0x00000001U
-#define ECC_MULT_START_S  0
-/** ECC_MULT_RESET : WT; bitpos: [1]; default: 0;
- *  Set this bit to reset ECC
- */
-#define ECC_MULT_RESET    (BIT(1))
-#define ECC_MULT_RESET_M  (ECC_MULT_RESET_V << ECC_MULT_RESET_S)
-#define ECC_MULT_RESET_V  0x00000001U
-#define ECC_MULT_RESET_S  1
-/** ECC_MULT_KEY_LENGTH : R/W; bitpos: [2]; default: 0;
- *  0:192bit key length mode. 1:256bit key length mode
- */
-#define ECC_MULT_KEY_LENGTH    (BIT(2))
-#define ECC_MULT_KEY_LENGTH_M  (ECC_MULT_KEY_LENGTH_V << ECC_MULT_KEY_LENGTH_S)
-#define ECC_MULT_KEY_LENGTH_V  0x00000001U
-#define ECC_MULT_KEY_LENGTH_S  2
-/** ECC_MULT_SECURITY_MODE : R/W; bitpos: [3]; default: 0;
- *  Reserved
- */
-#define ECC_MULT_SECURITY_MODE    (BIT(3))
-#define ECC_MULT_SECURITY_MODE_M  (ECC_MULT_SECURITY_MODE_V << ECC_MULT_SECURITY_MODE_S)
-#define ECC_MULT_SECURITY_MODE_V  0x00000001U
-#define ECC_MULT_SECURITY_MODE_S  3
-/** ECC_MULT_CLK_EN : R/W; bitpos: [4]; default: 0;
- *  clk gate
- */
-#define ECC_MULT_CLK_EN    (BIT(4))
-#define ECC_MULT_CLK_EN_M  (ECC_MULT_CLK_EN_V << ECC_MULT_CLK_EN_S)
-#define ECC_MULT_CLK_EN_V  0x00000001U
-#define ECC_MULT_CLK_EN_S  4
-/** ECC_MULT_WORK_MODE : R/W; bitpos: [7:5]; default: 0;
- *  ECC operation mode register.
- */
-#define ECC_MULT_WORK_MODE    0x00000007U
-#define ECC_MULT_WORK_MODE_M  (ECC_MULT_WORK_MODE_V << ECC_MULT_WORK_MODE_S)
-#define ECC_MULT_WORK_MODE_V  0x00000007U
-#define ECC_MULT_WORK_MODE_S  5
-/** ECC_MULT_VERIFICATION_RESULT : RO/SS; bitpos: [8]; default: 0;
- *  ECC verification result register.
- */
+#define ECC_MULT_CONF_REG          (DR_REG_ECC_MULT_BASE + 0x1C)
+/* ECC_MULT_VERIFICATION_RESULT : RO/SS ;bitpos:[8] ;default: 1'b0 ; */
+/*description: ECC verification result register..*/
 #define ECC_MULT_VERIFICATION_RESULT    (BIT(8))
-#define ECC_MULT_VERIFICATION_RESULT_M  (ECC_MULT_VERIFICATION_RESULT_V << ECC_MULT_VERIFICATION_RESULT_S)
-#define ECC_MULT_VERIFICATION_RESULT_V  0x00000001U
+#define ECC_MULT_VERIFICATION_RESULT_M  (BIT(8))
+#define ECC_MULT_VERIFICATION_RESULT_V  0x1
 #define ECC_MULT_VERIFICATION_RESULT_S  8
+/* ECC_MULT_WORK_MODE : R/W ;bitpos:[7:5] ;default: 3'b0 ; */
+/*description: ECC operation mode register..*/
+#define ECC_MULT_WORK_MODE    0x00000007
+#define ECC_MULT_WORK_MODE_M  ((ECC_MULT_WORK_MODE_V)<<(ECC_MULT_WORK_MODE_S))
+#define ECC_MULT_WORK_MODE_V  0x7
+#define ECC_MULT_WORK_MODE_S  5
+/* ECC_MULT_CLK_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: clk gate.*/
+#define ECC_MULT_CLK_EN    (BIT(4))
+#define ECC_MULT_CLK_EN_M  (BIT(4))
+#define ECC_MULT_CLK_EN_V  0x1
+#define ECC_MULT_CLK_EN_S  4
+/* ECC_MULT_SECURITY_MODE : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Reserved.*/
+#define ECC_MULT_SECURITY_MODE    (BIT(3))
+#define ECC_MULT_SECURITY_MODE_M  (BIT(3))
+#define ECC_MULT_SECURITY_MODE_V  0x1
+#define ECC_MULT_SECURITY_MODE_S  3
+/* ECC_MULT_KEY_LENGTH : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: 0:192bit key length mode. 1:256bit key length mode.*/
+#define ECC_MULT_KEY_LENGTH    (BIT(2))
+#define ECC_MULT_KEY_LENGTH_M  (BIT(2))
+#define ECC_MULT_KEY_LENGTH_V  0x1
+#define ECC_MULT_KEY_LENGTH_S  2
+/* ECC_MULT_RESET : WT ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Set this bit to reset ECC.*/
+#define ECC_MULT_RESET    (BIT(1))
+#define ECC_MULT_RESET_M  (BIT(1))
+#define ECC_MULT_RESET_V  0x1
+#define ECC_MULT_RESET_S  1
+/* ECC_MULT_START : R/W/SC ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set this bit to start a ECC operation..*/
+#define ECC_MULT_START    (BIT(0))
+#define ECC_MULT_START_M  (BIT(0))
+#define ECC_MULT_START_V  0x1
+#define ECC_MULT_START_S  0
 
-/** ECC_MULT_DATE_REG register
- *  Version control register
- */
-#define ECC_MULT_DATE_REG (DR_REG_ECC_MULT_BASE + 0xfc)
-/** ECC_MULT_DATE : R/W; bitpos: [27:0]; default: 34636176;
- *  ECC mult version control register
- */
-#define ECC_MULT_DATE    0x0FFFFFFFU
-#define ECC_MULT_DATE_M  (ECC_MULT_DATE_V << ECC_MULT_DATE_S)
-#define ECC_MULT_DATE_V  0x0FFFFFFFU
+#define ECC_MULT_DATE_REG          (DR_REG_ECC_MULT_BASE + 0xFC)
+/* ECC_MULT_DATE : R/W ;bitpos:[27:0] ;default: 28'h2108190 ; */
+/*description: ECC mult version control register.*/
+#define ECC_MULT_DATE    0x0FFFFFFF
+#define ECC_MULT_DATE_M  ((ECC_MULT_DATE_V)<<(ECC_MULT_DATE_S))
+#define ECC_MULT_DATE_V  0xFFFFFFF
 #define ECC_MULT_DATE_S  0
 
+#define ECC_MULT_K_1_REG          (DR_REG_ECC_MULT_BASE + 0x0100)
+/* ECC_MULT_MEM_K_1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: ECC Mem Parameter k.*/
+#define ECC_MULT_MEM_K_1  0xFFFFFFFF
+#define ECC_MULT_MEM_K_1_M  ((ECC_MULT_MEM_K_1_V)<<(ECC_MULT_MEM_K_1_S))
+#define ECC_MULT_MEM_K_1_V  0xFFFFFFFF
+#define ECC_MULT_MEM_K_1_S  0
+
+#define ECC_MULT_K_2_REG          (DR_REG_ECC_MULT_BASE + 0x0104)
+/* ECC_MULT_MEM_K_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: ECC Mem Parameter k.*/
+#define ECC_MULT_MEM_K_2  0xFFFFFFFF
+#define ECC_MULT_MEM_K_2_M  ((ECC_MULT_MEM_K_2_V)<<(ECC_MULT_MEM_K_2_S))
+#define ECC_MULT_MEM_K_2_V  0xFFFFFFFF
+#define ECC_MULT_MEM_K_2_S  0
+
+#define ECC_MULT_K_3_REG          (DR_REG_ECC_MULT_BASE + 0x0108)
+/* ECC_MULT_MEM_K_3 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: ECC Mem Parameter k.*/
+#define ECC_MULT_MEM_K_3  0xFFFFFFFF
+#define ECC_MULT_MEM_K_3_M  ((ECC_MULT_MEM_K_3_V)<<(ECC_MULT_MEM_K_3_S))
+#define ECC_MULT_MEM_K_3_V  0xFFFFFFFF
+#define ECC_MULT_MEM_K_3_S  0
+
+#define ECC_MULT_K_4_REG          (DR_REG_ECC_MULT_BASE + 0x010c)
+/* ECC_MULT_MEM_K_4 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: ECC Mem Parameter k.*/
+#define ECC_MULT_MEM_K_4  0xFFFFFFFF
+#define ECC_MULT_MEM_K_4_M  ((ECC_MULT_MEM_K_4_V)<<(ECC_MULT_MEM_K_4_S))
+#define ECC_MULT_MEM_K_4_V  0xFFFFFFFF
+#define ECC_MULT_MEM_K_4_S  0
+
+#define ECC_MULT_K_5_REG          (DR_REG_ECC_MULT_BASE + 0x0110)
+/* ECC_MULT_MEM_K_5 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: ECC Mem Parameter k.*/
+#define ECC_MULT_MEM_K_5  0xFFFFFFFF
+#define ECC_MULT_MEM_K_5_M  ((ECC_MULT_MEM_K_5_V)<<(ECC_MULT_MEM_K_5_S))
+#define ECC_MULT_MEM_K_5_V  0xFFFFFFFF
+#define ECC_MULT_MEM_K_5_S  0
+
+#define ECC_MULT_K_6_REG          (DR_REG_ECC_MULT_BASE + 0x0114)
+/* ECC_MULT_MEM_K_6 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: ECC Mem Parameter k.*/
+#define ECC_MULT_MEM_K_6  0xFFFFFFFF
+#define ECC_MULT_MEM_K_6_M  ((ECC_MULT_MEM_K_6_V)<<(ECC_MULT_MEM_K_6_S))
+#define ECC_MULT_MEM_K_6_V  0xFFFFFFFF
+#define ECC_MULT_MEM_K_6_S  0
+
+#define ECC_MULT_K_7_REG          (DR_REG_ECC_MULT_BASE + 0x0118)
+/* ECC_MULT_MEM_K_7 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: ECC Mem Parameter k.*/
+#define ECC_MULT_MEM_K_7  0xFFFFFFFF
+#define ECC_MULT_MEM_K_7_M  ((ECC_MULT_MEM_K_7_V)<<(ECC_MULT_MEM_K_7_S))
+#define ECC_MULT_MEM_K_7_V  0xFFFFFFFF
+#define ECC_MULT_MEM_K_7_S  0
+
+#define ECC_MULT_K_8_REG          (DR_REG_ECC_MULT_BASE + 0x011c)
+/* ECC_MULT_MEM_K_8 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: ECC Mem Parameter k.*/
+#define ECC_MULT_MEM_K_8  0xFFFFFFFF
+#define ECC_MULT_MEM_K_8_M  ((ECC_MULT_MEM_K_8_V)<<(ECC_MULT_MEM_K_8_S))
+#define ECC_MULT_MEM_K_8_V  0xFFFFFFFF
+#define ECC_MULT_MEM_K_8_S  0
+
+#define ECC_MULT_PX_1_REG          (DR_REG_ECC_MULT_BASE + 0x0120)
+/* ECC_MULT_MEM_PX_1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: ECC Mem Parameter Px.*/
+#define ECC_MULT_MEM_PX_1  0xFFFFFFFF
+#define ECC_MULT_MEM_PX_1_M  ((ECC_MULT_MEM_PX_1_V)<<(ECC_MULT_MEM_PX_1_S))
+#define ECC_MULT_MEM_PX_1_V  0xFFFFFFFF
+#define ECC_MULT_MEM_PX_1_S  0
+
+#define ECC_MULT_PX_2_REG          (DR_REG_ECC_MULT_BASE + 0x0124)
+/* ECC_MULT_MEM_PX_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: ECC Mem Parameter Px.*/
+#define ECC_MULT_MEM_PX_2  0xFFFFFFFF
+#define ECC_MULT_MEM_PX_2_M  ((ECC_MULT_MEM_PX_2_V)<<(ECC_MULT_MEM_PX_2_S))
+#define ECC_MULT_MEM_PX_2_V  0xFFFFFFFF
+#define ECC_MULT_MEM_PX_2_S  0
+
+#define ECC_MULT_PX_3_REG          (DR_REG_ECC_MULT_BASE + 0x0128)
+/* ECC_MULT_MEM_PX_3 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: ECC Mem Parameter Px.*/
+#define ECC_MULT_MEM_PX_3  0xFFFFFFFF
+#define ECC_MULT_MEM_PX_3_M  ((ECC_MULT_MEM_PX_3_V)<<(ECC_MULT_MEM_PX_3_S))
+#define ECC_MULT_MEM_PX_3_V  0xFFFFFFFF
+#define ECC_MULT_MEM_PX_3_S  0
+
+#define ECC_MULT_PX_4_REG          (DR_REG_ECC_MULT_BASE + 0x012c)
+/* ECC_MULT_MEM_PX_4 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: ECC Mem Parameter Px.*/
+#define ECC_MULT_MEM_PX_4  0xFFFFFFFF
+#define ECC_MULT_MEM_PX_4_M  ((ECC_MULT_MEM_PX_4_V)<<(ECC_MULT_MEM_PX_4_S))
+#define ECC_MULT_MEM_PX_4_V  0xFFFFFFFF
+#define ECC_MULT_MEM_PX_4_S  0
+
+#define ECC_MULT_PX_5_REG          (DR_REG_ECC_MULT_BASE + 0x0130)
+/* ECC_MULT_MEM_PX_5 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: ECC Mem Parameter Px.*/
+#define ECC_MULT_MEM_PX_5  0xFFFFFFFF
+#define ECC_MULT_MEM_PX_5_M  ((ECC_MULT_MEM_PX_5_V)<<(ECC_MULT_MEM_PX_5_S))
+#define ECC_MULT_MEM_PX_5_V  0xFFFFFFFF
+#define ECC_MULT_MEM_PX_5_S  0
+
+#define ECC_MULT_PX_6_REG          (DR_REG_ECC_MULT_BASE + 0x0134)
+/* ECC_MULT_MEM_PX_6 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: ECC Mem Parameter Px.*/
+#define ECC_MULT_MEM_PX_6  0xFFFFFFFF
+#define ECC_MULT_MEM_PX_6_M  ((ECC_MULT_MEM_PX_6_V)<<(ECC_MULT_MEM_PX_6_S))
+#define ECC_MULT_MEM_PX_6_V  0xFFFFFFFF
+#define ECC_MULT_MEM_PX_6_S  0
+
+#define ECC_MULT_PX_7_REG          (DR_REG_ECC_MULT_BASE + 0x0138)
+/* ECC_MULT_MEM_PX_7 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: ECC Mem Parameter Px.*/
+#define ECC_MULT_MEM_PX_7  0xFFFFFFFF
+#define ECC_MULT_MEM_PX_7_M  ((ECC_MULT_MEM_PX_7_V)<<(ECC_MULT_MEM_PX_7_S))
+#define ECC_MULT_MEM_PX_7_V  0xFFFFFFFF
+#define ECC_MULT_MEM_PX_7_S  0
+
+#define ECC_MULT_PX_8_REG          (DR_REG_ECC_MULT_BASE + 0x013c)
+/* ECC_MULT_MEM_PX_8 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: ECC Mem Parameter Px.*/
+#define ECC_MULT_MEM_PX_8  0xFFFFFFFF
+#define ECC_MULT_MEM_PX_8_M  ((ECC_MULT_MEM_PX_8_V)<<(ECC_MULT_MEM_PX_8_S))
+#define ECC_MULT_MEM_PX_8_V  0xFFFFFFFF
+#define ECC_MULT_MEM_PX_8_S  0
+
+#define ECC_MULT_PY_1_REG          (DR_REG_ECC_MULT_BASE + 0x0140)
+/* ECC_MULT_MEM_PY_1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: ECC Mem Parameter Py.*/
+#define ECC_MULT_MEM_PY_1  0xFFFFFFFF
+#define ECC_MULT_MEM_PY_1_M  ((ECC_MULT_MEM_PY_1_V)<<(ECC_MULT_MEM_PY_1_S))
+#define ECC_MULT_MEM_PY_1_V  0xFFFFFFFF
+#define ECC_MULT_MEM_PY_1_S  0
+
+#define ECC_MULT_PY_2_REG          (DR_REG_ECC_MULT_BASE + 0x0144)
+/* ECC_MULT_MEM_PY_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: ECC Mem Parameter Py.*/
+#define ECC_MULT_MEM_PY_2  0xFFFFFFFF
+#define ECC_MULT_MEM_PY_2_M  ((ECC_MULT_MEM_PY_2_V)<<(ECC_MULT_MEM_PY_2_S))
+#define ECC_MULT_MEM_PY_2_V  0xFFFFFFFF
+#define ECC_MULT_MEM_PY_2_S  0
+
+#define ECC_MULT_PY_3_REG          (DR_REG_ECC_MULT_BASE + 0x0148)
+/* ECC_MULT_MEM_PY_3 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: ECC Mem Parameter Py.*/
+#define ECC_MULT_MEM_PY_3  0xFFFFFFFF
+#define ECC_MULT_MEM_PY_3_M  ((ECC_MULT_MEM_PY_3_V)<<(ECC_MULT_MEM_PY_3_S))
+#define ECC_MULT_MEM_PY_3_V  0xFFFFFFFF
+#define ECC_MULT_MEM_PY_3_S  0
+
+#define ECC_MULT_PY_4_REG          (DR_REG_ECC_MULT_BASE + 0x014c)
+/* ECC_MULT_MEM_PY_4 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: ECC Mem Parameter Py.*/
+#define ECC_MULT_MEM_PY_4  0xFFFFFFFF
+#define ECC_MULT_MEM_PY_4_M  ((ECC_MULT_MEM_PY_4_V)<<(ECC_MULT_MEM_PY_4_S))
+#define ECC_MULT_MEM_PY_4_V  0xFFFFFFFF
+#define ECC_MULT_MEM_PY_4_S  0
+
+#define ECC_MULT_PY_5_REG          (DR_REG_ECC_MULT_BASE + 0x0150)
+/* ECC_MULT_MEM_PY_5 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: ECC Mem Parameter Py.*/
+#define ECC_MULT_MEM_PY_5  0xFFFFFFFF
+#define ECC_MULT_MEM_PY_5_M  ((ECC_MULT_MEM_PY_5_V)<<(ECC_MULT_MEM_PY_5_S))
+#define ECC_MULT_MEM_PY_5_V  0xFFFFFFFF
+#define ECC_MULT_MEM_PY_5_S  0
+
+#define ECC_MULT_PY_6_REG          (DR_REG_ECC_MULT_BASE + 0x0154)
+/* ECC_MULT_MEM_PY_6 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: ECC Mem Parameter Py.*/
+#define ECC_MULT_MEM_PY_6  0xFFFFFFFF
+#define ECC_MULT_MEM_PY_6_M  ((ECC_MULT_MEM_PY_6_V)<<(ECC_MULT_MEM_PY_6_S))
+#define ECC_MULT_MEM_PY_6_V  0xFFFFFFFF
+#define ECC_MULT_MEM_PY_6_S  0
+
+#define ECC_MULT_PY_7_REG          (DR_REG_ECC_MULT_BASE + 0x0158)
+/* ECC_MULT_MEM_PY_7 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: ECC Mem Parameter Py.*/
+#define ECC_MULT_MEM_PY_7  0xFFFFFFFF
+#define ECC_MULT_MEM_PY_7_M  ((ECC_MULT_MEM_PY_7_V)<<(ECC_MULT_MEM_PY_7_S))
+#define ECC_MULT_MEM_PY_7_V  0xFFFFFFFF
+#define ECC_MULT_MEM_PY_7_S  0
+
+#define ECC_MULT_PY_8_REG          (DR_REG_ECC_MULT_BASE + 0x015c)
+/* ECC_MULT_MEM_PY_8 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: ECC Mem Parameter Py.*/
+#define ECC_MULT_MEM_PY_8  0xFFFFFFFF
+#define ECC_MULT_MEM_PY_8_M  ((ECC_MULT_MEM_PY_8_V)<<(ECC_MULT_MEM_PY_8_S))
+#define ECC_MULT_MEM_PY_8_V  0xFFFFFFFF
+#define ECC_MULT_MEM_PY_8_S  0
+
 #ifdef __cplusplus
 }
 #endif

components/soc/esp32h2/include/soc/Kconfig.soc_caps.in

@@ -85,7 +85,7 @@ config SOC_DIG_SIGN_SUPPORTED
 
 config SOC_ECC_SUPPORTED
     bool
-    default n
+    default y
 
 config SOC_FLASH_ENC_SUPPORTED
     bool

components/soc/esp32h2/include/soc/periph_defs.h

@@ -33,6 +33,7 @@ typedef enum {
     PERIPH_RSA_MODULE,
     PERIPH_AES_MODULE,
     PERIPH_SHA_MODULE,
+    PERIPH_ECC_MODULE,
     PERIPH_HMAC_MODULE,
     PERIPH_DS_MODULE,
     PERIPH_GDMA_MODULE,

components/soc/esp32h2/include/soc/soc_caps.h

@@ -53,7 +53,7 @@
 #define SOC_SHA_SUPPORTED               1
 #define SOC_HMAC_SUPPORTED              1
 #define SOC_DIG_SIGN_SUPPORTED          1
-#define SOC_ECC_SUPPORTED               0 // This will be enabled with IDF-3397
+#define SOC_ECC_SUPPORTED               1
 #define SOC_FLASH_ENC_SUPPORTED         1
 #define SOC_SECURE_BOOT_SUPPORTED       1