This fixes compilation issue of heap tracing feature for RISC-V architecture.
@@ -45,6 +45,8 @@ menu "Heap memory debugging"
config HEAP_TRACING_STACK_DEPTH
int "Heap tracing stack depth"
+ range 0 0 if IDF_TARGET_ARCH_RISCV # Disabled for RISC-V due to `__builtin_return_address` limitation
+ default 0 if IDF_TARGET_ARCH_RISCV
range 0 10
default 2
depends on HEAP_TRACING
@@ -19,7 +19,7 @@
/* Encode the CPU ID in the LSB of the ccount value */
inline static uint32_t get_ccount(void)
{
- uint32_t ccount = xthal_get_ccount() & ~3;
+ uint32_t ccount = cpu_hal_get_cycle_count() & ~3;
#ifndef CONFIG_FREERTOS_UNICORE
ccount |= xPortGetCoreID();
#endif