Merge branch 'feature/gpio_channel_macro' into 'master'

feat(global): add macros for GPIO->channel lookup



See merge request !1170

components/driver/include/driver/adc.h

@@ -22,6 +22,7 @@ extern "C" {
 #include <stdint.h>
 #include "esp_err.h"
 #include "driver/gpio.h"
+#include "soc/adc_channel.h"
 
 typedef enum {
     ADC_ATTEN_0db   = 0,  /*!<The input voltage of ADC will be reduced to about 1/1 */
@@ -49,6 +50,20 @@ typedef enum {
     ADC1_CHANNEL_MAX,
 } adc1_channel_t;
 
+typedef enum {
+    ADC2_CHANNEL_0 = 0, /*!< ADC2 channel 0 is GPIO4 */
+    ADC2_CHANNEL_1,     /*!< ADC2 channel 1 is GPIO0 */
+    ADC2_CHANNEL_2,     /*!< ADC2 channel 2 is GPIO2 */
+    ADC2_CHANNEL_3,     /*!< ADC2 channel 3 is GPIO15 */
+    ADC2_CHANNEL_4,     /*!< ADC2 channel 4 is GPIO13 */
+    ADC2_CHANNEL_5,     /*!< ADC2 channel 5 is GPIO12 */
+    ADC2_CHANNEL_6,     /*!< ADC2 channel 6 is GPIO14 */
+    ADC2_CHANNEL_7,     /*!< ADC2 channel 7 is GPIO27 */
+    ADC2_CHANNEL_8,     /*!< ADC2 channel 8 is GPIO25 */
+    ADC2_CHANNEL_9,     /*!< ADC2 channel 9 is GPIO26 */
+    ADC2_CHANNEL_MAX,
+} adc2_channel_t;
+
 /**
  * @brief Configure ADC1 capture width.
  *

components/driver/include/driver/dac.h

@@ -21,6 +21,7 @@ extern "C" {
 
 #include <stdint.h>
 #include "esp_err.h"
+#include "soc/dac_channel.h"
 
 typedef enum {
     DAC_CHANNEL_1 = 1,  /*!< DAC channel 1 is GPIO25 */

components/driver/include/driver/rtc_io.h

@@ -18,6 +18,7 @@
 #include <stdint.h>
 #include "esp_err.h"
 #include "driver/gpio.h"
+#include "soc/rtc_gpio_channel.h"
 
 #ifdef __cplusplus
 extern "C" {

components/driver/include/driver/touch_pad.h

@@ -20,6 +20,7 @@ extern "C" {
 #include "esp_intr.h"
 #include "esp_err.h"
 #include "esp_intr_alloc.h"
+#include "soc/touch_channel.h"
 
 typedef enum {
     TOUCH_PAD_NUM0 = 0, /*!< Touch pad channel 0 is GPIO4 */

components/driver/include/driver/uart.h

@@ -32,6 +32,7 @@ extern "C" {
 #include "freertos/queue.h"
 #include "freertos/ringbuf.h"
 #include <esp_types.h>
+#include "soc/uart_channel.h"
 
 #define UART_FIFO_LEN           (128)        /*!< Length of the hardware FIFO buffers */
 #define UART_INTR_MASK          0x1ff        /*!< mask of all UART interrupts */

components/driver/rtc_module.c

@@ -74,11 +74,11 @@ static touch_pad_filter_t *s_touch_pad_filter = NULL;
 
 //Reg,Mux,Fun,IE,Up,Down,Rtc_number
 const rtc_gpio_desc_t rtc_gpio_desc[GPIO_PIN_COUNT] = {
-    {RTC_IO_TOUCH_PAD1_REG, RTC_IO_TOUCH_PAD1_MUX_SEL_M, RTC_IO_TOUCH_PAD1_FUN_SEL_S, RTC_IO_TOUCH_PAD1_FUN_IE_M, RTC_IO_TOUCH_PAD1_RUE_M, RTC_IO_TOUCH_PAD1_RDE_M, RTC_IO_TOUCH_PAD1_SLP_SEL_M, RTC_IO_TOUCH_PAD1_SLP_IE_M, RTC_IO_TOUCH_PAD1_HOLD_M, RTC_CNTL_TOUCH_PAD1_HOLD_FORCE_M, RTC_IO_TOUCH_PAD1_DRV_V, RTC_IO_TOUCH_PAD1_DRV_S, 11}, //0
+    {RTC_IO_TOUCH_PAD1_REG, RTC_IO_TOUCH_PAD1_MUX_SEL_M, RTC_IO_TOUCH_PAD1_FUN_SEL_S, RTC_IO_TOUCH_PAD1_FUN_IE_M, RTC_IO_TOUCH_PAD1_RUE_M, RTC_IO_TOUCH_PAD1_RDE_M, RTC_IO_TOUCH_PAD1_SLP_SEL_M, RTC_IO_TOUCH_PAD1_SLP_IE_M, RTC_IO_TOUCH_PAD1_HOLD_M, RTC_CNTL_TOUCH_PAD1_HOLD_FORCE_M, RTC_IO_TOUCH_PAD1_DRV_V, RTC_IO_TOUCH_PAD1_DRV_S, RTCIO_GPIO0_CHANNEL}, //0
     {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1},                                                                                                                                            //1
-    {RTC_IO_TOUCH_PAD2_REG, RTC_IO_TOUCH_PAD2_MUX_SEL_M, RTC_IO_TOUCH_PAD2_FUN_SEL_S, RTC_IO_TOUCH_PAD2_FUN_IE_M, RTC_IO_TOUCH_PAD2_RUE_M, RTC_IO_TOUCH_PAD2_RDE_M, RTC_IO_TOUCH_PAD2_SLP_SEL_M, RTC_IO_TOUCH_PAD2_SLP_IE_M, RTC_IO_TOUCH_PAD2_HOLD_M, RTC_CNTL_TOUCH_PAD2_HOLD_FORCE_M, RTC_IO_TOUCH_PAD2_DRV_V, RTC_IO_TOUCH_PAD2_DRV_S, 12}, //2
+    {RTC_IO_TOUCH_PAD2_REG, RTC_IO_TOUCH_PAD2_MUX_SEL_M, RTC_IO_TOUCH_PAD2_FUN_SEL_S, RTC_IO_TOUCH_PAD2_FUN_IE_M, RTC_IO_TOUCH_PAD2_RUE_M, RTC_IO_TOUCH_PAD2_RDE_M, RTC_IO_TOUCH_PAD2_SLP_SEL_M, RTC_IO_TOUCH_PAD2_SLP_IE_M, RTC_IO_TOUCH_PAD2_HOLD_M, RTC_CNTL_TOUCH_PAD2_HOLD_FORCE_M, RTC_IO_TOUCH_PAD2_DRV_V, RTC_IO_TOUCH_PAD2_DRV_S, RTCIO_GPIO2_CHANNEL}, //2
     {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1},                                                                                                                                            //3
-    {RTC_IO_TOUCH_PAD0_REG, RTC_IO_TOUCH_PAD0_MUX_SEL_M, RTC_IO_TOUCH_PAD0_FUN_SEL_S, RTC_IO_TOUCH_PAD0_FUN_IE_M, RTC_IO_TOUCH_PAD0_RUE_M, RTC_IO_TOUCH_PAD0_RDE_M, RTC_IO_TOUCH_PAD0_SLP_SEL_M, RTC_IO_TOUCH_PAD0_SLP_IE_M, RTC_IO_TOUCH_PAD0_HOLD_M,  RTC_CNTL_TOUCH_PAD0_HOLD_FORCE_M, RTC_IO_TOUCH_PAD0_DRV_V, RTC_IO_TOUCH_PAD0_DRV_S, 10}, //4
+    {RTC_IO_TOUCH_PAD0_REG, RTC_IO_TOUCH_PAD0_MUX_SEL_M, RTC_IO_TOUCH_PAD0_FUN_SEL_S, RTC_IO_TOUCH_PAD0_FUN_IE_M, RTC_IO_TOUCH_PAD0_RUE_M, RTC_IO_TOUCH_PAD0_RDE_M, RTC_IO_TOUCH_PAD0_SLP_SEL_M, RTC_IO_TOUCH_PAD0_SLP_IE_M, RTC_IO_TOUCH_PAD0_HOLD_M,  RTC_CNTL_TOUCH_PAD0_HOLD_FORCE_M, RTC_IO_TOUCH_PAD0_DRV_V, RTC_IO_TOUCH_PAD0_DRV_S, RTCIO_GPIO4_CHANNEL}, //4
     {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1},                                                                                                                                            //5
     {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1},                                                                                                                                            //6
     {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1},                                                                                                                                            //7
@@ -86,10 +86,10 @@ const rtc_gpio_desc_t rtc_gpio_desc[GPIO_PIN_COUNT] = {
     {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1},                                                                                                                                            //9
     {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1},                                                                                                                                            //10
     {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1},                                                                                                                                            //11
-    {RTC_IO_TOUCH_PAD5_REG, RTC_IO_TOUCH_PAD5_MUX_SEL_M, RTC_IO_TOUCH_PAD5_FUN_SEL_S, RTC_IO_TOUCH_PAD5_FUN_IE_M, RTC_IO_TOUCH_PAD5_RUE_M, RTC_IO_TOUCH_PAD5_RDE_M, RTC_IO_TOUCH_PAD5_SLP_SEL_M, RTC_IO_TOUCH_PAD5_SLP_IE_M, RTC_IO_TOUCH_PAD5_HOLD_M, RTC_CNTL_TOUCH_PAD5_HOLD_FORCE_M, RTC_IO_TOUCH_PAD5_DRV_V, RTC_IO_TOUCH_PAD5_DRV_S, 15}, //12
-    {RTC_IO_TOUCH_PAD4_REG, RTC_IO_TOUCH_PAD4_MUX_SEL_M, RTC_IO_TOUCH_PAD4_FUN_SEL_S, RTC_IO_TOUCH_PAD4_FUN_IE_M, RTC_IO_TOUCH_PAD4_RUE_M, RTC_IO_TOUCH_PAD4_RDE_M, RTC_IO_TOUCH_PAD4_SLP_SEL_M, RTC_IO_TOUCH_PAD4_SLP_IE_M, RTC_IO_TOUCH_PAD4_HOLD_M, RTC_CNTL_TOUCH_PAD4_HOLD_FORCE_M, RTC_IO_TOUCH_PAD4_DRV_V, RTC_IO_TOUCH_PAD4_DRV_S, 14}, //13
-    {RTC_IO_TOUCH_PAD6_REG, RTC_IO_TOUCH_PAD6_MUX_SEL_M, RTC_IO_TOUCH_PAD6_FUN_SEL_S, RTC_IO_TOUCH_PAD6_FUN_IE_M, RTC_IO_TOUCH_PAD6_RUE_M, RTC_IO_TOUCH_PAD6_RDE_M, RTC_IO_TOUCH_PAD6_SLP_SEL_M, RTC_IO_TOUCH_PAD6_SLP_IE_M, RTC_IO_TOUCH_PAD6_HOLD_M, RTC_CNTL_TOUCH_PAD6_HOLD_FORCE_M, RTC_IO_TOUCH_PAD6_DRV_V, RTC_IO_TOUCH_PAD6_DRV_S, 16}, //14
-    {RTC_IO_TOUCH_PAD3_REG, RTC_IO_TOUCH_PAD3_MUX_SEL_M, RTC_IO_TOUCH_PAD3_FUN_SEL_S, RTC_IO_TOUCH_PAD3_FUN_IE_M, RTC_IO_TOUCH_PAD3_RUE_M, RTC_IO_TOUCH_PAD3_RDE_M, RTC_IO_TOUCH_PAD3_SLP_SEL_M, RTC_IO_TOUCH_PAD3_SLP_IE_M, RTC_IO_TOUCH_PAD3_HOLD_M, RTC_CNTL_TOUCH_PAD3_HOLD_FORCE_M, RTC_IO_TOUCH_PAD3_DRV_V, RTC_IO_TOUCH_PAD3_DRV_S, 13}, //15
+    {RTC_IO_TOUCH_PAD5_REG, RTC_IO_TOUCH_PAD5_MUX_SEL_M, RTC_IO_TOUCH_PAD5_FUN_SEL_S, RTC_IO_TOUCH_PAD5_FUN_IE_M, RTC_IO_TOUCH_PAD5_RUE_M, RTC_IO_TOUCH_PAD5_RDE_M, RTC_IO_TOUCH_PAD5_SLP_SEL_M, RTC_IO_TOUCH_PAD5_SLP_IE_M, RTC_IO_TOUCH_PAD5_HOLD_M, RTC_CNTL_TOUCH_PAD5_HOLD_FORCE_M, RTC_IO_TOUCH_PAD5_DRV_V, RTC_IO_TOUCH_PAD5_DRV_S, RTCIO_GPIO12_CHANNEL}, //12
+    {RTC_IO_TOUCH_PAD4_REG, RTC_IO_TOUCH_PAD4_MUX_SEL_M, RTC_IO_TOUCH_PAD4_FUN_SEL_S, RTC_IO_TOUCH_PAD4_FUN_IE_M, RTC_IO_TOUCH_PAD4_RUE_M, RTC_IO_TOUCH_PAD4_RDE_M, RTC_IO_TOUCH_PAD4_SLP_SEL_M, RTC_IO_TOUCH_PAD4_SLP_IE_M, RTC_IO_TOUCH_PAD4_HOLD_M, RTC_CNTL_TOUCH_PAD4_HOLD_FORCE_M, RTC_IO_TOUCH_PAD4_DRV_V, RTC_IO_TOUCH_PAD4_DRV_S, RTCIO_GPIO13_CHANNEL}, //13
+    {RTC_IO_TOUCH_PAD6_REG, RTC_IO_TOUCH_PAD6_MUX_SEL_M, RTC_IO_TOUCH_PAD6_FUN_SEL_S, RTC_IO_TOUCH_PAD6_FUN_IE_M, RTC_IO_TOUCH_PAD6_RUE_M, RTC_IO_TOUCH_PAD6_RDE_M, RTC_IO_TOUCH_PAD6_SLP_SEL_M, RTC_IO_TOUCH_PAD6_SLP_IE_M, RTC_IO_TOUCH_PAD6_HOLD_M, RTC_CNTL_TOUCH_PAD6_HOLD_FORCE_M, RTC_IO_TOUCH_PAD6_DRV_V, RTC_IO_TOUCH_PAD6_DRV_S, RTCIO_GPIO14_CHANNEL}, //14
+    {RTC_IO_TOUCH_PAD3_REG, RTC_IO_TOUCH_PAD3_MUX_SEL_M, RTC_IO_TOUCH_PAD3_FUN_SEL_S, RTC_IO_TOUCH_PAD3_FUN_IE_M, RTC_IO_TOUCH_PAD3_RUE_M, RTC_IO_TOUCH_PAD3_RDE_M, RTC_IO_TOUCH_PAD3_SLP_SEL_M, RTC_IO_TOUCH_PAD3_SLP_IE_M, RTC_IO_TOUCH_PAD3_HOLD_M, RTC_CNTL_TOUCH_PAD3_HOLD_FORCE_M, RTC_IO_TOUCH_PAD3_DRV_V, RTC_IO_TOUCH_PAD3_DRV_S, RTCIO_GPIO15_CHANNEL}, //15
     {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1},                                                                                                                                            //16
     {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1},                                                                                                                                            //17
     {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1},                                                                                                                                            //18
@@ -99,21 +99,21 @@ const rtc_gpio_desc_t rtc_gpio_desc[GPIO_PIN_COUNT] = {
     {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1},                                                                                                                                            //22
     {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1},                                                                                                                                            //23
     {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1},                                                                                                                                            //24
-    {RTC_IO_PAD_DAC1_REG, RTC_IO_PDAC1_MUX_SEL_M, RTC_IO_PDAC1_FUN_SEL_S, RTC_IO_PDAC1_FUN_IE_M, RTC_IO_PDAC1_RUE_M, RTC_IO_PDAC1_RDE_M, RTC_IO_PDAC1_SLP_SEL_M, RTC_IO_PDAC1_SLP_IE_M, RTC_IO_PDAC1_HOLD_M, RTC_CNTL_PDAC1_HOLD_FORCE_M, RTC_IO_PDAC1_DRV_V, RTC_IO_PDAC1_DRV_S, 6},                           //25
-    {RTC_IO_PAD_DAC2_REG, RTC_IO_PDAC2_MUX_SEL_M, RTC_IO_PDAC2_FUN_SEL_S, RTC_IO_PDAC2_FUN_IE_M, RTC_IO_PDAC2_RUE_M, RTC_IO_PDAC2_RDE_M, RTC_IO_PDAC2_SLP_SEL_M, RTC_IO_PDAC2_SLP_IE_M, RTC_IO_PDAC2_HOLD_M, RTC_CNTL_PDAC1_HOLD_FORCE_M, RTC_IO_PDAC2_DRV_V, RTC_IO_PDAC2_DRV_S, 7},                           //26
-    {RTC_IO_TOUCH_PAD7_REG, RTC_IO_TOUCH_PAD7_MUX_SEL_M, RTC_IO_TOUCH_PAD7_FUN_SEL_S, RTC_IO_TOUCH_PAD7_FUN_IE_M, RTC_IO_TOUCH_PAD7_RUE_M, RTC_IO_TOUCH_PAD7_RDE_M, RTC_IO_TOUCH_PAD7_SLP_SEL_M, RTC_IO_TOUCH_PAD7_SLP_IE_M, RTC_IO_TOUCH_PAD7_HOLD_M, RTC_CNTL_TOUCH_PAD7_HOLD_FORCE_M, RTC_IO_TOUCH_PAD7_DRV_V, RTC_IO_TOUCH_PAD7_DRV_S, 17}, //27
+    {RTC_IO_PAD_DAC1_REG, RTC_IO_PDAC1_MUX_SEL_M, RTC_IO_PDAC1_FUN_SEL_S, RTC_IO_PDAC1_FUN_IE_M, RTC_IO_PDAC1_RUE_M, RTC_IO_PDAC1_RDE_M, RTC_IO_PDAC1_SLP_SEL_M, RTC_IO_PDAC1_SLP_IE_M, RTC_IO_PDAC1_HOLD_M, RTC_CNTL_PDAC1_HOLD_FORCE_M, RTC_IO_PDAC1_DRV_V, RTC_IO_PDAC1_DRV_S, RTCIO_GPIO25_CHANNEL},                           //25
+    {RTC_IO_PAD_DAC2_REG, RTC_IO_PDAC2_MUX_SEL_M, RTC_IO_PDAC2_FUN_SEL_S, RTC_IO_PDAC2_FUN_IE_M, RTC_IO_PDAC2_RUE_M, RTC_IO_PDAC2_RDE_M, RTC_IO_PDAC2_SLP_SEL_M, RTC_IO_PDAC2_SLP_IE_M, RTC_IO_PDAC2_HOLD_M, RTC_CNTL_PDAC1_HOLD_FORCE_M, RTC_IO_PDAC2_DRV_V, RTC_IO_PDAC2_DRV_S, RTCIO_GPIO26_CHANNEL},                           //26
+    {RTC_IO_TOUCH_PAD7_REG, RTC_IO_TOUCH_PAD7_MUX_SEL_M, RTC_IO_TOUCH_PAD7_FUN_SEL_S, RTC_IO_TOUCH_PAD7_FUN_IE_M, RTC_IO_TOUCH_PAD7_RUE_M, RTC_IO_TOUCH_PAD7_RDE_M, RTC_IO_TOUCH_PAD7_SLP_SEL_M, RTC_IO_TOUCH_PAD7_SLP_IE_M, RTC_IO_TOUCH_PAD7_HOLD_M, RTC_CNTL_TOUCH_PAD7_HOLD_FORCE_M, RTC_IO_TOUCH_PAD7_DRV_V, RTC_IO_TOUCH_PAD7_DRV_S, RTCIO_GPIO27_CHANNEL}, //27
     {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1},                                                                                                                                            //28
     {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1},                                                                                                                                            //29
     {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1},                                                                                                                                            //30
     {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1},                                                                                                                                            //31
-    {RTC_IO_XTAL_32K_PAD_REG, RTC_IO_X32P_MUX_SEL_M, RTC_IO_X32P_FUN_SEL_S, RTC_IO_X32P_FUN_IE_M, RTC_IO_X32P_RUE_M, RTC_IO_X32P_RDE_M, RTC_IO_X32P_SLP_SEL_M, RTC_IO_X32P_SLP_IE_M, RTC_IO_X32P_HOLD_M, RTC_CNTL_X32P_HOLD_FORCE_M, RTC_IO_X32P_DRV_V, RTC_IO_X32P_DRV_S, 9},                            //32
-    {RTC_IO_XTAL_32K_PAD_REG, RTC_IO_X32N_MUX_SEL_M, RTC_IO_X32N_FUN_SEL_S, RTC_IO_X32N_FUN_IE_M, RTC_IO_X32N_RUE_M, RTC_IO_X32N_RDE_M, RTC_IO_X32N_SLP_SEL_M, RTC_IO_X32N_SLP_IE_M, RTC_IO_X32N_HOLD_M, RTC_CNTL_X32N_HOLD_FORCE_M, RTC_IO_X32N_DRV_V, RTC_IO_X32N_DRV_S, 8},                            //33
-    {RTC_IO_ADC_PAD_REG, RTC_IO_ADC1_MUX_SEL_M, RTC_IO_ADC1_FUN_SEL_S, RTC_IO_ADC1_FUN_IE_M, 0, 0, RTC_IO_ADC1_SLP_SEL_M, RTC_IO_ADC1_SLP_IE_M, RTC_IO_ADC1_HOLD_M, RTC_CNTL_ADC1_HOLD_FORCE_M, 0, 0, 4},                                                                //34
-    {RTC_IO_ADC_PAD_REG, RTC_IO_ADC2_MUX_SEL_M, RTC_IO_ADC2_FUN_SEL_S, RTC_IO_ADC2_FUN_IE_M, 0, 0, RTC_IO_ADC2_SLP_SEL_M, RTC_IO_ADC2_SLP_IE_M, RTC_IO_ADC1_HOLD_M, RTC_CNTL_ADC2_HOLD_FORCE_M, 0, 0, 5},                                                                //35
-    {RTC_IO_SENSOR_PADS_REG, RTC_IO_SENSE1_MUX_SEL_M, RTC_IO_SENSE1_FUN_SEL_S, RTC_IO_SENSE1_FUN_IE_M, 0, 0, RTC_IO_SENSE1_SLP_SEL_M, RTC_IO_SENSE1_SLP_IE_M, RTC_IO_SENSE1_HOLD_M, RTC_CNTL_SENSE1_HOLD_FORCE_M, 0, 0, 0},                                                      //36
-    {RTC_IO_SENSOR_PADS_REG, RTC_IO_SENSE2_MUX_SEL_M, RTC_IO_SENSE2_FUN_SEL_S, RTC_IO_SENSE2_FUN_IE_M, 0, 0, RTC_IO_SENSE2_SLP_SEL_M, RTC_IO_SENSE2_SLP_IE_M, RTC_IO_SENSE1_HOLD_M, RTC_CNTL_SENSE2_HOLD_FORCE_M, 0, 0, 1},                                                      //37
-    {RTC_IO_SENSOR_PADS_REG, RTC_IO_SENSE3_MUX_SEL_M, RTC_IO_SENSE3_FUN_SEL_S, RTC_IO_SENSE3_FUN_IE_M, 0, 0, RTC_IO_SENSE3_SLP_SEL_M, RTC_IO_SENSE3_SLP_IE_M, RTC_IO_SENSE1_HOLD_M, RTC_CNTL_SENSE3_HOLD_FORCE_M, 0, 0, 2},                                                       //38
-    {RTC_IO_SENSOR_PADS_REG, RTC_IO_SENSE4_MUX_SEL_M, RTC_IO_SENSE4_FUN_SEL_S, RTC_IO_SENSE4_FUN_IE_M, 0, 0, RTC_IO_SENSE4_SLP_SEL_M, RTC_IO_SENSE4_SLP_IE_M, RTC_IO_SENSE1_HOLD_M, RTC_CNTL_SENSE4_HOLD_FORCE_M, 0, 0, 3},                                                      //39
+    {RTC_IO_XTAL_32K_PAD_REG, RTC_IO_X32P_MUX_SEL_M, RTC_IO_X32P_FUN_SEL_S, RTC_IO_X32P_FUN_IE_M, RTC_IO_X32P_RUE_M, RTC_IO_X32P_RDE_M, RTC_IO_X32P_SLP_SEL_M, RTC_IO_X32P_SLP_IE_M, RTC_IO_X32P_HOLD_M, RTC_CNTL_X32P_HOLD_FORCE_M, RTC_IO_X32P_DRV_V, RTC_IO_X32P_DRV_S, RTCIO_GPIO32_CHANNEL},                            //32
+    {RTC_IO_XTAL_32K_PAD_REG, RTC_IO_X32N_MUX_SEL_M, RTC_IO_X32N_FUN_SEL_S, RTC_IO_X32N_FUN_IE_M, RTC_IO_X32N_RUE_M, RTC_IO_X32N_RDE_M, RTC_IO_X32N_SLP_SEL_M, RTC_IO_X32N_SLP_IE_M, RTC_IO_X32N_HOLD_M, RTC_CNTL_X32N_HOLD_FORCE_M, RTC_IO_X32N_DRV_V, RTC_IO_X32N_DRV_S, RTCIO_GPIO33_CHANNEL},                            //33
+    {RTC_IO_ADC_PAD_REG, RTC_IO_ADC1_MUX_SEL_M, RTC_IO_ADC1_FUN_SEL_S, RTC_IO_ADC1_FUN_IE_M, 0, 0, RTC_IO_ADC1_SLP_SEL_M, RTC_IO_ADC1_SLP_IE_M, RTC_IO_ADC1_HOLD_M, RTC_CNTL_ADC1_HOLD_FORCE_M, 0, 0, RTCIO_GPIO34_CHANNEL},                                                                //34
+    {RTC_IO_ADC_PAD_REG, RTC_IO_ADC2_MUX_SEL_M, RTC_IO_ADC2_FUN_SEL_S, RTC_IO_ADC2_FUN_IE_M, 0, 0, RTC_IO_ADC2_SLP_SEL_M, RTC_IO_ADC2_SLP_IE_M, RTC_IO_ADC1_HOLD_M, RTC_CNTL_ADC2_HOLD_FORCE_M, 0, 0, RTCIO_GPIO35_CHANNEL},                                                                //35
+    {RTC_IO_SENSOR_PADS_REG, RTC_IO_SENSE1_MUX_SEL_M, RTC_IO_SENSE1_FUN_SEL_S, RTC_IO_SENSE1_FUN_IE_M, 0, 0, RTC_IO_SENSE1_SLP_SEL_M, RTC_IO_SENSE1_SLP_IE_M, RTC_IO_SENSE1_HOLD_M, RTC_CNTL_SENSE1_HOLD_FORCE_M, 0, 0, RTCIO_GPIO36_CHANNEL},                                                      //36
+    {RTC_IO_SENSOR_PADS_REG, RTC_IO_SENSE2_MUX_SEL_M, RTC_IO_SENSE2_FUN_SEL_S, RTC_IO_SENSE2_FUN_IE_M, 0, 0, RTC_IO_SENSE2_SLP_SEL_M, RTC_IO_SENSE2_SLP_IE_M, RTC_IO_SENSE1_HOLD_M, RTC_CNTL_SENSE2_HOLD_FORCE_M, 0, 0, RTCIO_GPIO37_CHANNEL},                                                      //37
+    {RTC_IO_SENSOR_PADS_REG, RTC_IO_SENSE3_MUX_SEL_M, RTC_IO_SENSE3_FUN_SEL_S, RTC_IO_SENSE3_FUN_IE_M, 0, 0, RTC_IO_SENSE3_SLP_SEL_M, RTC_IO_SENSE3_SLP_IE_M, RTC_IO_SENSE1_HOLD_M, RTC_CNTL_SENSE3_HOLD_FORCE_M, 0, 0, RTCIO_GPIO38_CHANNEL},                                                       //38
+    {RTC_IO_SENSOR_PADS_REG, RTC_IO_SENSE4_MUX_SEL_M, RTC_IO_SENSE4_FUN_SEL_S, RTC_IO_SENSE4_FUN_IE_M, 0, 0, RTC_IO_SENSE4_SLP_SEL_M, RTC_IO_SENSE4_SLP_IE_M, RTC_IO_SENSE1_HOLD_M, RTC_CNTL_SENSE4_HOLD_FORCE_M, 0, 0, RTCIO_GPIO39_CHANNEL},                                                      //39
 };
 
 /*---------------------------------------------------------------
@@ -377,34 +377,34 @@ static esp_err_t touch_pad_get_io_num(touch_pad_t touch_num, gpio_num_t *gpio_nu
 {
     switch (touch_num) {
     case TOUCH_PAD_NUM0:
-        *gpio_num = 4;
+        *gpio_num = TOUCH_PAD_NUM0_GPIO_NUM;
         break;
     case TOUCH_PAD_NUM1:
-        *gpio_num = 0;
+        *gpio_num = TOUCH_PAD_NUM1_GPIO_NUM;
         break;
     case TOUCH_PAD_NUM2:
-        *gpio_num = 2;
+        *gpio_num = TOUCH_PAD_NUM2_GPIO_NUM;
         break;
     case TOUCH_PAD_NUM3:
-        *gpio_num = 15;
+        *gpio_num = TOUCH_PAD_NUM3_GPIO_NUM;
         break;
     case TOUCH_PAD_NUM4:
-        *gpio_num = 13;
+        *gpio_num = TOUCH_PAD_NUM4_GPIO_NUM;
         break;
     case TOUCH_PAD_NUM5:
-        *gpio_num = 12;
+        *gpio_num = TOUCH_PAD_NUM5_GPIO_NUM;
         break;
     case TOUCH_PAD_NUM6:
-        *gpio_num = 14;
+        *gpio_num = TOUCH_PAD_NUM6_GPIO_NUM;
         break;
     case TOUCH_PAD_NUM7:
-        *gpio_num = 27;
+        *gpio_num = TOUCH_PAD_NUM7_GPIO_NUM;
         break;
     case TOUCH_PAD_NUM8:
-        *gpio_num = 32;
+        *gpio_num = TOUCH_PAD_NUM8_GPIO_NUM;
         break;
     case TOUCH_PAD_NUM9:
-        *gpio_num = 33;
+        *gpio_num = TOUCH_PAD_NUM9_GPIO_NUM;
         break;
     default:
         return ESP_ERR_INVALID_ARG;
@@ -879,28 +879,28 @@ static esp_err_t adc1_pad_get_io_num(adc1_channel_t channel, gpio_num_t *gpio_nu
 
     switch (channel) {
     case ADC1_CHANNEL_0:
-        *gpio_num = 36;
+        *gpio_num = ADC1_CHANNEL_0_GPIO_NUM;
         break;
     case ADC1_CHANNEL_1:
-        *gpio_num = 37;
+        *gpio_num = ADC1_CHANNEL_1_GPIO_NUM;
         break;
     case ADC1_CHANNEL_2:
-        *gpio_num = 38;
+        *gpio_num = ADC1_CHANNEL_2_GPIO_NUM;
         break;
     case ADC1_CHANNEL_3:
-        *gpio_num = 39;
+        *gpio_num = ADC1_CHANNEL_3_GPIO_NUM;
         break;
     case ADC1_CHANNEL_4:
-        *gpio_num = 32;
+        *gpio_num = ADC1_CHANNEL_4_GPIO_NUM;
         break;
     case ADC1_CHANNEL_5:
-        *gpio_num = 33;
+        *gpio_num = ADC1_CHANNEL_5_GPIO_NUM;
         break;
     case ADC1_CHANNEL_6:
-        *gpio_num = 34;
+        *gpio_num = ADC1_CHANNEL_6_GPIO_NUM;
         break;
     case ADC1_CHANNEL_7:
-        *gpio_num = 35;
+        *gpio_num = ADC1_CHANNEL_7_GPIO_NUM;
         break;
     default:
         return ESP_ERR_INVALID_ARG;
@@ -1041,10 +1041,10 @@ static esp_err_t dac_pad_get_io_num(dac_channel_t channel, gpio_num_t *gpio_num)
 
     switch (channel) {
     case DAC_CHANNEL_1:
-        *gpio_num = 25;
+        *gpio_num = DAC_CHANNEL_1_GPIO_NUM;
         break;
     case DAC_CHANNEL_2:
-        *gpio_num = 26;
+        *gpio_num = DAC_CHANNEL_2_GPIO_NUM;
         break;
     default:
         return ESP_ERR_INVALID_ARG;

components/soc/esp32/include/soc/adc_channel.h

@@ -0,0 +1,72 @@
+// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef _SOC_ADC_CHANNEL_H
+#define _SOC_ADC_CHANNEL_H
+
+#define ADC1_GPIO36_CHANNEL     ADC1_CHANNEL_0
+#define ADC1_CHANNEL_0_GPIO_NUM 36
+
+#define ADC1_GPIO37_CHANNEL     ADC1_CHANNEL_1
+#define ADC1_CHANNEL_1_GPIO_NUM 37
+
+#define ADC1_GPIO38_CHANNEL     ADC1_CHANNEL_2
+#define ADC1_CHANNEL_2_GPIO_NUM 38
+
+#define ADC1_GPIO39_CHANNEL     ADC1_CHANNEL_3
+#define ADC1_CHANNEL_3_GPIO_NUM 39
+
+#define ADC1_GPIO32_CHANNEL     ADC1_CHANNEL_4
+#define ADC1_CHANNEL_4_GPIO_NUM 32
+
+#define ADC1_GPIO33_CHANNEL     ADC1_CHANNEL_5
+#define ADC1_CHANNEL_5_GPIO_NUM 33
+
+#define ADC1_GPIO34_CHANNEL     ADC1_CHANNEL_6
+#define ADC1_CHANNEL_6_GPIO_NUM 34
+
+#define ADC1_GPIO35_CHANNEL     ADC1_CHANNEL_7
+#define ADC1_CHANNEL_7_GPIO_NUM 35
+
+#define ADC2_GPIO4_CHANNEL      ADC2_CHANNEL_0
+#define ADC2_CHANNEL_0_GPIO_NUM 4
+
+#define ADC2_GPIO0_CHANNEL      ADC2_CHANNEL_1
+#define ADC2_CHANNEL_1_GPIO_NUM 0
+
+#define ADC2_GPIO2_CHANNEL      ADC2_CHANNEL_2
+#define ADC2_CHANNEL_2_GPIO_NUM 2
+
+#define ADC2_GPIO15_CHANNEL     ADC2_CHANNEL_3
+#define ADC2_CHANNEL_3_GPIO_NUM 15
+
+#define ADC2_GPIO13_CHANNEL     ADC2_CHANNEL_4
+#define ADC2_CHANNEL_4_GPIO_NUM 13
+
+#define ADC2_GPIO12_CHANNEL     ADC2_CHANNEL_5
+#define ADC2_CHANNEL_5_GPIO_NUM 12
+
+#define ADC2_GPIO14_CHANNEL     ADC2_CHANNEL_6
+#define ADC2_CHANNEL_6_GPIO_NUM 14
+
+#define ADC2_GPIO27_CHANNEL     ADC2_CHANNEL_7
+#define ADC2_CHANNEL_7_GPIO_NUM 27
+
+#define ADC2_GPIO25_CHANNEL     ADC2_CHANNEL_8
+#define ADC2_CHANNEL_8_GPIO_NUM 25
+
+#define ADC2_GPIO26_CHANNEL     ADC2_CHANNEL_9
+#define ADC2_CHANNEL_9_GPIO_NUM 26
+
+#endif

components/soc/esp32/include/soc/clkout_channel.h

@@ -0,0 +1,26 @@
+// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef _SOC_CLKOUT_CHANNEL_H
+#define _SOC_CLKOUT_CHANNEL_H
+
+//CLKOUT channels
+#define CLKOUT_GPIO0_DIRECT_CHANNEL         CLKOUT_CHANNEL_1
+#define CLKOUT_CHANNEL_1_DIRECT_GPIO_NUM    0
+#define CLKOUT_GPIO3_DIRECT_CHANNEL         CLKOUT_CHANNEL_2
+#define CLKOUT_CHANNEL_2_DIRECT_GPIO_NUM    3
+#define CLKOUT_GPIO1_DIRECT_CHANNEL         CLKOUT_CHANNEL_3
+#define CLKOUT_CHANNEL_3_DIRECT_GPIO_NUM    1
+
+#endif

components/soc/esp32/include/soc/dac_channel.h

@@ -0,0 +1,24 @@
+// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef _SOC_DAC_CHANNEL_H
+#define _SOC_DAC_CHANNEL_H
+
+#define DAC_GPIO25_CHANNEL      DAC_CHANNEL_1
+#define DAC_CHANNEL_1_GPIO_NUM  25
+
+#define DAC_GPIO26_CHANNEL      DAC_CHANNEL_2
+#define DAC_CHANNEL_2_GPIO_NUM  26
+
+#endif

components/soc/esp32/include/soc/rtc_gpio_channel.h

@@ -0,0 +1,73 @@
+// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef _SOC_RTC_GPIO_CHANNEL_H
+#define _SOC_RTC_GPIO_CHANNEL_H
+
+//RTC GPIO channels
+#define RTCIO_GPIO36_CHANNEL        0   //RTCIO_CHANNEL_0
+#define RTCIO_CHANNEL_0_GPIO_NUM    36
+
+#define RTCIO_GPIO37_CHANNEL        1   //RTCIO_CHANNEL_1
+#define RTCIO_CHANNEL_1_GPIO_NUM    37
+
+#define RTCIO_GPIO38_CHANNEL        2   //RTCIO_CHANNEL_2
+#define RTCIO_CHANNEL_2_GPIO_NUM    38
+
+#define RTCIO_GPIO39_CHANNEL        3   //RTCIO_CHANNEL_3
+#define RTCIO_CHANNEL_3_GPIO_NUM    39
+
+#define RTCIO_GPIO34_CHANNEL        4   //RTCIO_CHANNEL_4
+#define RTCIO_CHANNEL_4_GPIO_NUM    34
+
+#define RTCIO_GPIO35_CHANNEL        5   //RTCIO_CHANNEL_5
+#define RTCIO_CHANNEL_5_GPIO_NUM    35
+
+#define RTCIO_GPIO25_CHANNEL        6   //RTCIO_CHANNEL_6
+#define RTCIO_CHANNEL_6_GPIO_NUM    25
+
+#define RTCIO_GPIO26_CHANNEL        7   //RTCIO_CHANNEL_7
+#define RTCIO_CHANNEL_7_GPIO_NUM    26
+
+#define RTCIO_GPIO33_CHANNEL        8   //RTCIO_CHANNEL_8
+#define RTCIO_CHANNEL_8_GPIO_NUM    33
+
+#define RTCIO_GPIO32_CHANNEL        9   //RTCIO_CHANNEL_9
+#define RTCIO_CHANNEL_9_GPIO_NUM    32
+
+#define RTCIO_GPIO4_CHANNEL         10   //RTCIO_CHANNEL_10
+#define RTCIO_CHANNEL_10_GPIO_NUM   4
+
+#define RTCIO_GPIO0_CHANNEL         11   //RTCIO_CHANNEL_11
+#define RTCIO_CHANNEL_11_GPIO_NUM   0
+
+#define RTCIO_GPIO2_CHANNEL         12   //RTCIO_CHANNEL_12
+#define RTCIO_CHANNEL_12_GPIO_NUM   2
+
+#define RTCIO_GPIO15_CHANNEL        13   //RTCIO_CHANNEL_13
+#define RTCIO_CHANNEL_13_GPIO_NUM   15
+
+#define RTCIO_GPIO13_CHANNEL        14   //RTCIO_CHANNEL_14
+#define RTCIO_CHANNEL_14_GPIO_NUM   13
+
+#define RTCIO_GPIO12_CHANNEL        15   //RTCIO_CHANNEL_15
+#define RTCIO_CHANNEL_15_GPIO_NUM   12
+
+#define RTCIO_GPIO14_CHANNEL        16   //RTCIO_CHANNEL_16
+#define RTCIO_CHANNEL_16_GPIO_NUM   14
+
+#define RTCIO_GPIO27_CHANNEL        17   //RTCIO_CHANNEL_17
+#define RTCIO_CHANNEL_17_GPIO_NUM   27
+
+#endif

components/soc/esp32/include/soc/touch_channel.h

@@ -0,0 +1,49 @@
+// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef _SOC_TOUCH_CHANNEL_H
+#define _SOC_TOUCH_CHANNEL_H
+
+//Touch channels
+#define TOUCH_PAD_GPIO4_CHANNEL     TOUCH_PAD_NUM0
+#define TOUCH_PAD_NUM0_GPIO_NUM     4
+
+#define TOUCH_PAD_GPIO0_CHANNEL     TOUCH_PAD_NUM1
+#define TOUCH_PAD_NUM1_GPIO_NUM     0
+
+#define TOUCH_PAD_GPIO2_CHANNEL     TOUCH_PAD_NUM2
+#define TOUCH_PAD_NUM2_GPIO_NUM     2
+
+#define TOUCH_PAD_GPIO15_CHANNEL    TOUCH_PAD_NUM3
+#define TOUCH_PAD_NUM3_GPIO_NUM     15
+
+#define TOUCH_PAD_GPIO13_CHANNEL    TOUCH_PAD_NUM4
+#define TOUCH_PAD_NUM4_GPIO_NUM     13
+
+#define TOUCH_PAD_GPIO12_CHANNEL    TOUCH_PAD_NUM5
+#define TOUCH_PAD_NUM5_GPIO_NUM     12
+
+#define TOUCH_PAD_GPIO14_CHANNEL    TOUCH_PAD_NUM6
+#define TOUCH_PAD_NUM6_GPIO_NUM     14
+
+#define TOUCH_PAD_GPIO27_CHANNEL    TOUCH_PAD_NUM7
+#define TOUCH_PAD_NUM7_GPIO_NUM     27
+
+#define TOUCH_PAD_GPIO33_CHANNEL    TOUCH_PAD_NUM8
+#define TOUCH_PAD_NUM8_GPIO_NUM     33
+
+#define TOUCH_PAD_GPIO32_CHANNEL    TOUCH_PAD_NUM9
+#define TOUCH_PAD_NUM9_GPIO_NUM     32
+
+#endif

components/soc/esp32/include/soc/uart_channel.h

@@ -0,0 +1,61 @@
+// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef _SOC_UART_CHANNEL_H
+#define _SOC_UART_CHANNEL_H
+
+//UART channels
+#define UART_GPIO1_DIRECT_CHANNEL       UART_NUM_0
+#define UART_NUM_0_TXD_DIRECT_GPIO_NUM  1
+#define UART_GPIO3_DIRECT_CHANNEL       UART_NUM_0
+#define UART_NUM_0_RXD_DIRECT_GPIO_NUM  3
+#define UART_GPIO19_DIRECT_CHANNEL      UART_NUM_0
+#define UART_NUM_0_CTS_DIRECT_GPIO_NUM  19
+#define UART_GPIO22_DIRECT_CHANNEL      UART_NUM_0
+#define UART_NUM_0_RTS_DIRECT_GPIO_NUM  22
+
+#define UART_TXD_GPIO1_DIRECT_CHANNEL   UART_GPIO1_DIRECT_CHANNEL
+#define UART_RXD_GPIO3_DIRECT_CHANNEL   UART_GPIO3_DIRECT_CHANNEL
+#define UART_CTS_GPIO19_DIRECT_CHANNEL  UART_GPIO19_DIRECT_CHANNEL
+#define UART_RTS_GPIO22_DIRECT_CHANNEL  UART_GPIO22_DIRECT_CHANNEL
+
+#define UART_GPIO10_DIRECT_CHANNEL      UART_NUM_1
+#define UART_NUM_1_TXD_DIRECT_GPIO_NUM  10
+#define UART_GPIO9_DIRECT_CHANNEL       UART_NUM_1
+#define UART_NUM_1_RXD_DIRECT_GPIO_NUM  9
+#define UART_GPIO6_DIRECT_CHANNEL       UART_NUM_1
+#define UART_NUM_1_CTS_DIRECT_GPIO_NUM  6
+#define UART_GPIO11_DIRECT_CHANNEL      UART_NUM_1
+#define UART_NUM_1_RTS_DIRECT_GPIO_NUM  11
+
+#define UART_TXD_GPIO10_DIRECT_CHANNEL  UART_GPIO10_DIRECT_CHANNEL
+#define UART_RXD_GPIO9_DIRECT_CHANNEL   UART_GPIO9_DIRECT_CHANNEL
+#define UART_CTS_GPIO6_DIRECT_CHANNEL   UART_GPIO6_DIRECT_CHANNEL
+#define UART_RTS_GPIO11_DIRECT_CHANNEL  UART_GPIO11_DIRECT_CHANNEL
+
+#define UART_GPIO17_DIRECT_CHANNEL      UART_NUM_2
+#define UART_NUM_2_TXD_DIRECT_GPIO_NUM  17
+#define UART_GPIO16_DIRECT_CHANNEL      UART_NUM_2
+#define UART_NUM_2_RXD_DIRECT_GPIO_NUM  16
+#define UART_GPIO8_DIRECT_CHANNEL       UART_NUM_2
+#define UART_NUM_2_CTS_DIRECT_GPIO_NUM  8
+#define UART_GPIO7_DIRECT_CHANNEL       UART_NUM_2
+#define UART_NUM_2_RTS_DIRECT_GPIO_NUM  7
+
+#define UART_TXD_GPIO17_DIRECT_CHANNEL  UART_GPIO17_DIRECT_CHANNEL
+#define UART_RXD_GPIO16_DIRECT_CHANNEL  UART_GPIO16_DIRECT_CHANNEL
+#define UART_CTS_GPIO8_DIRECT_CHANNEL   UART_GPIO8_DIRECT_CHANNEL
+#define UART_RTS_GPIO7_DIRECT_CHANNEL   UART_GPIO7_DIRECT_CHANNEL
+
+#endif

docs/Doxyfile

@@ -75,6 +75,11 @@ INPUT = \
     ../components/driver/include/driver/touch_pad.h \
     ../components/driver/include/driver/uart.h \
     ../components/esp_adc_cal/include/esp_adc_cal.h \
+    ../components/soc/esp32/include/soc/adc_channel.h \
+    ../components/soc/esp32/include/soc/dac_channel.h \
+    ../components/soc/esp32/include/soc/touch_channel.h \
+    ../components/soc/esp32/include/soc/uart_channel.h \
+    ../components/soc/esp32/include/soc/rtc_gpio_channel.h \
     ##
     ## Protocols - API Reference
     ##

docs/api-reference/peripherals/adc.rst

@@ -44,6 +44,15 @@ API Reference
 
 .. include:: /_build/inc/adc.inc
 
+GPIO Lookup Macros
+^^^^^^^^^^^^^^^^^^
+Some useful macros can be used to specified the GPIO number of a ADC channel, or vice versa.
+e.g.
+
+1. ``ADC1_CHANNEL_0_GPIO_NUM`` is the GPIO number of ADC1 channel 0 (36);
+2. ``ADC1_GPIO32_CHANNEL`` is the ADC1 channel number of GPIO 32 (ADC1 channel 4).
+
+.. include:: /_build/inc/adc_channel.inc
 
 ADC Calibration
 ===============
@@ -99,4 +108,4 @@ Routing ADC reference voltage to GPIO::
 API Reference
 -------------
 
-.. include:: /_build/inc/esp_adc_cal.inc
+.. include:: /_build/inc/esp_adc_cal.inc

docs/api-reference/peripherals/dac.rst

@@ -30,3 +30,12 @@ API Reference
 
 .. include:: /_build/inc/dac.inc
 
+GPIO Lookup Macros
+^^^^^^^^^^^^^^^^^^
+Some useful macros can be used to specified the GPIO number of a DAC channel, or vice versa.
+e.g.
+
+1. ``DAC_CHANNEL_1_GPIO_NUM`` is the GPIO number of channel 1 (25);
+2. ``DAC_GPIO26_CHANNEL`` is the channel number of GPIO 26 (channel 2).
+
+.. include:: /_build/inc/dac_channel.inc

docs/api-reference/peripherals/touch_pad.rst

@@ -158,3 +158,13 @@ API Reference
 
 .. include:: /_build/inc/touch_pad.inc
 
+GPIO Lookup Macros
+^^^^^^^^^^^^^^^^^^
+Some useful macros can be used to specified the GPIO number of a touchpad channel, or vice versa.
+e.g.
+
+1. ``TOUCH_PAD_NUM5_GPIO_NUM`` is the GPIO number of channel 5 (12);
+2. ``TOUCH_PAD_GPIO4_CHANNEL`` is the channel number of GPIO 4 (channel 0).
+
+.. include:: /_build/inc/touch_channel.inc
+

docs/api-reference/peripherals/uart.rst

@@ -18,4 +18,17 @@ API Reference
 
 .. include:: /_build/inc/uart.inc
 
+GPIO Lookup Macros
+^^^^^^^^^^^^^^^^^^
+Some useful macros can be used to specified the **direct** GPIO (UART module connected to pads through direct IO mux without the GPIO mux) number of a UART channel, or vice versa. 
+The pin name can be omitted if specify the channel of a GPIO num.
+e.g.
+
+1. ``UART_NUM_2_TXD_DIRECT_GPIO_NUM`` is the GPIO number of UART channel 2 TXD pin (17);
+2. ``UART_GPIO19_DIRECT_CHANNEL`` is the UART channel number of GPIO 19 (channel 0);
+3. ``UART_CTS_GPIO19_DIRECT_CHANNEL`` is the UART channel number of GPIO 19, and GPIO 19 must be a CTS pin (channel 0).
+
+
+.. include:: /_build/inc/uart_channel.inc
+