esp_rom: Patch some cache apis

components/esp_psram/mmu_psram_flash.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -49,13 +49,6 @@ esp_err_t mmu_config_psram_text_segment(uint32_t start_page, uint32_t psram_size
 {
     uint32_t page_id = start_page;
 
-    /**
-     * TODO IDF-4387
-     * `Cache_Count_Flash_Pages` seems give wrong results. Need to confirm this.
-     * FOR NOW, leave these logics just as it used to be.
-     *
-     * The rom API will be redesigned into a MMU driver layer function
-     */
     uint32_t flash_pages = 0;
 #if CONFIG_IDF_TARGET_ESP32S2
     flash_pages += Cache_Count_Flash_Pages(PRO_CACHE_IBUS0, &page0_mapped);
@@ -100,13 +93,6 @@ esp_err_t mmu_config_psram_rodata_segment(uint32_t start_page, uint32_t psram_si
 {
     uint32_t page_id = start_page;
 
-    /**
-     * TODO IDF-4387
-     * `Cache_Count_Flash_Pages` seems give wrong results. Need to confirm this.
-     * FOR NOW, leave these logics just as it used to be.
-     *
-     * The rom API will be redesigned into a MMU driver layer function
-     */
     uint32_t flash_pages = 0;
 #if CONFIG_IDF_TARGET_ESP32S2
     flash_pages += Cache_Count_Flash_Pages(PRO_CACHE_IBUS2, &page0_mapped);

components/esp_rom/CMakeLists.txt

@@ -46,6 +46,10 @@ if(CONFIG_HAL_WDT_USE_ROM_IMPL)
     list(APPEND sources "patches/esp_rom_wdt.c")
 endif()
 
+if(CONFIG_ESP_ROM_HAS_FLASH_COUNT_PAGES_BUG)
+    list(APPEND sources "patches/esp_rom_cache_esp32s2_esp32s3.c")
+endif()
+
 idf_component_register(SRCS ${sources}
                        INCLUDE_DIRS ${include_dirs}
                        PRIV_REQUIRES ${private_required_comp}

components/esp_rom/esp32s2/Kconfig.soc_caps.in

@@ -30,3 +30,7 @@ config ESP_ROM_HAS_NEWLIB_NANO_FORMAT
 config ESP_ROM_USB_OTG_NUM
     int
     default 3
+
+config ESP_ROM_HAS_FLASH_COUNT_PAGES_BUG
+    bool
+    default y

components/esp_rom/esp32s2/esp_rom_caps.h

@@ -13,3 +13,4 @@
 #define ESP_ROM_HAS_REGI2C_BUG              (1) // ROM has the regi2c bug
 #define ESP_ROM_HAS_NEWLIB_NANO_FORMAT      (1) // ROM has the newlib nano version of formatting functions
 #define ESP_ROM_USB_OTG_NUM                 (3) // The serial port ID (UART, USB, ...) of USB_OTG CDC in the ROM.
+#define ESP_ROM_HAS_FLASH_COUNT_PAGES_BUG   (1) // ROM api Cache_Count_Flash_Pages will return unexpected value

components/esp_rom/esp32s2/ld/esp32s2.rom.ld

@@ -17,7 +17,7 @@ PROVIDE ( Cache_Clean_All = 0x40018438 );
 PROVIDE ( Cache_Clean_Items = 0x40018250 );
 PROVIDE ( Cache_Config_DCache_Autoload = 0x40018794 );
 PROVIDE ( Cache_Config_ICache_Autoload = 0x40018664 );
-PROVIDE ( Cache_Count_Flash_Pages = 0x40018f70 );
+PROVIDE ( rom_Cache_Count_Flash_Pages = 0x40018f70 );
 PROVIDE ( Cache_Dbus_MMU_Set = 0x40018eb0 );
 PROVIDE ( Cache_DCache_Preload_Done = 0x40018630 );
 PROVIDE ( Cache_Disable_DCache = 0x40018c68 );

components/esp_rom/esp32s3/Kconfig.soc_caps.in

@@ -74,3 +74,11 @@ config ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE
 config ESP_ROM_RAM_APP_NEEDS_MMU_INIT
     bool
     default y
+
+config ESP_ROM_HAS_FLASH_COUNT_PAGES_BUG
+    bool
+    default y
+
+config ESP_ROM_HAS_CACHE_SUSPEND_WAITI_BUG
+    bool
+    default y

components/esp_rom/esp32s3/esp_rom_caps.h

@@ -24,3 +24,5 @@
 #define ESP_ROM_HAS_NEWLIB_NANO_FORMAT      (1) // ROM has the newlib nano version of formatting functions
 #define ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE    (1) // ROM needs to set cache MMU size according to instruction and rodata for flash mmap
 #define ESP_ROM_RAM_APP_NEEDS_MMU_INIT      (1) // ROM doesn't init cache MMU when it's a RAM APP, needs MMU hal to init
+#define ESP_ROM_HAS_FLASH_COUNT_PAGES_BUG   (1) // ROM api Cache_Count_Flash_Pages will return unexpected value
+#define ESP_ROM_HAS_CACHE_SUSPEND_WAITI_BUG (1) // ROM api Cache_Suspend_I/DCache and Cache_Freeze_I/DCache_Enable does not waiti

components/esp_rom/esp32s3/ld/esp32s3.rom.ld

@@ -420,15 +420,15 @@ PROVIDE( Cache_Disable_ICache = 0x4000186c );
 PROVIDE( Cache_Enable_ICache = 0x40001878 );
 PROVIDE( Cache_Disable_DCache = 0x40001884 );
 PROVIDE( Cache_Enable_DCache = 0x40001890 );
-PROVIDE( Cache_Suspend_ICache = 0x4000189c );
+PROVIDE( rom_Cache_Suspend_ICache = 0x4000189c );
 PROVIDE( Cache_Resume_ICache = 0x400018a8 );
-PROVIDE( Cache_Suspend_DCache = 0x400018b4 );
+PROVIDE( rom_Cache_Suspend_DCache = 0x400018b4 );
 PROVIDE( Cache_Resume_DCache = 0x400018c0 );
 PROVIDE( Cache_Occupy_Items = 0x400018cc );
 PROVIDE( Cache_Occupy_Addr = 0x400018d8 );
-PROVIDE( Cache_Freeze_ICache_Enable = 0x400018e4 );
+PROVIDE( rom_Cache_Freeze_ICache_Enable = 0x400018e4 );
 PROVIDE( Cache_Freeze_ICache_Disable = 0x400018f0 );
-PROVIDE( Cache_Freeze_DCache_Enable = 0x400018fc );
+PROVIDE( rom_Cache_Freeze_DCache_Enable = 0x400018fc );
 PROVIDE( Cache_Freeze_DCache_Disable = 0x40001908 );
 PROVIDE( Cache_Set_IDROM_MMU_Size = 0x40001914 );
 PROVIDE( flash2spiram_instruction_offset = 0x40001920 );
@@ -444,7 +444,7 @@ PROVIDE( Cache_Occupy_DCache_MEMORY = 0x4000198c );
 PROVIDE( Cache_MMU_Init = 0x40001998 );
 PROVIDE( Cache_Ibus_MMU_Set = 0x400019a4 );
 PROVIDE( Cache_Dbus_MMU_Set = 0x400019b0 );
-PROVIDE( Cache_Count_Flash_Pages = 0x400019bc );
+PROVIDE( rom_Cache_Count_Flash_Pages = 0x400019bc );
 PROVIDE( Cache_Flash_To_SPIRAM_Copy = 0x400019c8 );
 PROVIDE( Cache_Travel_Tag_Memory = 0x400019d4 );
 PROVIDE( Cache_Travel_Tag_Memory2 = 0x400019e0 );

components/esp_rom/linker.lf

@@ -2,6 +2,8 @@
 archive: libesp_rom.a
 entries:
     esp_rom_spiflash (noflash)
+    if ESP_ROM_HAS_FLASH_COUNT_PAGES_BUG = y:
+        esp_rom_cache_esp32s2_esp32s3 (noflash)
     if HEAP_TLSF_USE_ROM_IMPL = y && ESP_ROM_TLSF_CHECK_PATCH = y:
         esp_rom_tlsf (noflash)
     if SOC_SYSTIMER_SUPPORTED = y:

components/esp_rom/patches/esp_rom_cache_esp32s2_esp32s3.c

@@ -0,0 +1,85 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "sdkconfig.h"
+#include <stdint.h>
+#include "soc/soc_caps.h"
+#include "soc/extmem_reg.h"
+#if CONFIG_IDF_TARGET_ESP32S3
+#include "esp32s3/rom/cache.h"
+#endif
+
+// this api is renamed for patch
+extern uint32_t rom_Cache_Count_Flash_Pages(uint32_t bus, uint32_t * page0_mapped);
+uint32_t Cache_Count_Flash_Pages(uint32_t bus, uint32_t * page0_mapped)
+{
+    uint32_t page0_before_count = *page0_mapped;
+    uint32_t flash_pages = 0;
+    flash_pages = rom_Cache_Count_Flash_Pages(bus, page0_mapped);
+
+/* No page mapped to page0, in this condition, the rom api will return
+ * unexpected value + 1.
+ */
+    if (page0_before_count == *page0_mapped) {
+        flash_pages--;
+    }
+    return flash_pages;
+}
+extern uint32_t Cache_Count_Flash_Pages(uint32_t bus, uint32_t * page0_mapped);
+
+#if CONFIG_ESP_ROM_HAS_CACHE_SUSPEND_WAITI_BUG
+static inline void Cache_Wait_Idle(int icache)
+{
+    if (icache) {
+        while (REG_GET_FIELD(EXTMEM_CACHE_STATE_REG, EXTMEM_ICACHE_STATE) != 1) {
+            ;
+        }
+    } else {
+        while (REG_GET_FIELD(EXTMEM_CACHE_STATE_REG, EXTMEM_DCACHE_STATE) != 1) {
+            ;
+        }
+    }
+}
+// renamed for patch
+extern uint32_t rom_Cache_Suspend_ICache(void);
+uint32_t Cache_Suspend_ICache(void)
+{
+    uint32_t ret = rom_Cache_Suspend_ICache();
+    Cache_Wait_Idle(1);
+    return ret;
+}
+extern uint32_t Cache_Suspend_ICache(void);
+
+// renamed for patch
+extern uint32_t rom_Cache_Suspend_DCache(void);
+uint32_t Cache_Suspend_DCache(void)
+{
+    uint32_t ret = rom_Cache_Suspend_DCache();
+    Cache_Wait_Idle(0);
+    return ret;
+}
+extern uint32_t Cache_Suspend_DCache(void);
+
+#if SOC_CACHE_FREEZE_SUPPORTED
+// renamed for patch
+extern void rom_Cache_Freeze_ICache_Enable(cache_freeze_mode_t mode);
+void Cache_Freeze_ICache_Enable(cache_freeze_mode_t mode)
+{
+    rom_Cache_Freeze_ICache_Enable(mode);
+    Cache_Wait_Idle(1);
+}
+extern void Cache_Freeze_ICache_Enable(cache_freeze_mode_t mode);
+
+// renamed for patch
+extern void rom_Cache_Freeze_DCache_Enable(cache_freeze_mode_t mode);
+void Cache_Freeze_DCache_Enable(cache_freeze_mode_t mode)
+{
+    rom_Cache_Freeze_DCache_Enable(mode);
+    Cache_Wait_Idle(0);
+}
+extern void Cache_Freeze_DCache_Enable(cache_freeze_mode_t mode);
+#endif
+#endif