app_update: re-enable elf-sha256

components/esp32/ld/esp32.ld

@@ -43,12 +43,14 @@ MEMORY
 
   /* Even though the segment name is iram, it is actually mapped to flash
   */
-  iram0_2_seg (RX) :                 org = 0x400D0018, len = 0x330000-0x18
+  iram0_2_seg (RX) :                 org = 0x400D0020, len = 0x330000-0x20
 
   /*
-    (0x18 offset above is a convenience for the app binary image generation. Flash cache has 64KB pages. The .bin file
-    which is flashed to the chip has a 0x18 byte file header. Setting this offset makes it simple to meet the flash
-    cache MMU's constraint that (paddr % 64KB == vaddr % 64KB).)
+    (0x20 offset above is a convenience for the app binary image generation.
+    Flash cache has 64KB pages. The .bin file which is flashed to the chip
+    has a 0x18 byte file header, and each segment has a 0x08 byte segment
+    header. Setting this offset makes it simple to meet the flash cache MMU's
+    constraint that (paddr % 64KB == vaddr % 64KB).)
   */
 
 
@@ -65,9 +67,9 @@ MEMORY
                                      len = DRAM0_0_SEG_LEN - CONFIG_BT_RESERVE_DRAM
 
   /* Flash mapped constant data */
-  drom0_0_seg (R) :                  org = 0x3F400018, len = 0x400000-0x18
+  drom0_0_seg (R) :                  org = 0x3F400020, len = 0x400000-0x20
 
-  /* (See iram0_2_seg for meaning of 0x18 offset in the above.) */
+  /* (See iram0_2_seg for meaning of 0x20 offset in the above.) */
 
   /* RTC fast memory (executable). Persists over deep sleep.
    */

components/esp32s2beta/ld/esp32s2beta.ld

@@ -55,12 +55,14 @@ MEMORY
 
   /* Even though the segment name is iram, it is actually mapped to flash
   */
-  iram0_2_seg (RX) :                 org = 0x40080018, len = 0xb80000-0x18
+  iram0_2_seg (RX) :                 org = 0x40080020, len = 0xb80000-0x20
 
   /*
-    (0x18 offset above is a convenience for the app binary image generation. Flash cache has 64KB pages. The .bin file
-    which is flashed to the chip has a 0x18 byte file header. Setting this offset makes it simple to meet the flash
-    cache MMU's constraint that (paddr % 64KB == vaddr % 64KB).)
+    (0x20 offset above is a convenience for the app binary image generation.
+    Flash cache has 64KB pages. The .bin file which is flashed to the chip
+    has a 0x18 byte file header, and each segment has a 0x08 byte segment
+    header. Setting this offset makes it simple to meet the flash cache MMU's
+    constraint that (paddr % 64KB == vaddr % 64KB).)
   */
 
 
@@ -72,9 +74,9 @@ MEMORY
   dram0_0_seg (RW) :                 org = DRAM_ORG, len = DRAM_SIZE
 
   /* Flash mapped constant data */
-  drom0_0_seg (R) :                  org = 0x3F000018, len = 0x3f0000-0x18
+  drom0_0_seg (R) :                  org = 0x3F000020, len = 0x3f0000-0x20
 
-  /* (See iram0_2_seg for meaning of 0x18 offset in the above.) */
+  /* (See iram0_2_seg for meaning of 0x20 offset in the above.) */
 
   /* RTC fast memory (executable). Persists over deep sleep.
    */

components/esptool_py/project_include.cmake

@@ -43,7 +43,7 @@ string(REPLACE ";" " " ESPTOOLPY_WRITE_FLASH_STR
     "write_flash ${ESPTOOLPY_FLASH_OPTIONS} ${ESPTOOLPY_EXTRA_FLASH_OPTIONS} ${ESPTOOLPY_COMPRESSED_OPT}")
 
 if(NOT BOOTLOADER_BUILD)
-    # set(ESPTOOLPY_ELF2IMAGE_OPTIONS --elf-sha256-offset 0xb0)
+    set(ESPTOOLPY_ELF2IMAGE_OPTIONS --elf-sha256-offset 0xb0)
 endif()
 
 if(CONFIG_SECURE_BOOT_ENABLED AND