Merge branch 'feature/esp32s2beta_cpu_start_clean' into 'feature/esp32s2beta'

esp32s2beta: Simplify cpu_start.c remove code linked with CPU1

See merge request espressif/esp-idf!5691

components/esp32s2beta/cpu_start.c

@@ -77,12 +77,6 @@
 
 void start_cpu0(void) __attribute__((weak, alias("start_cpu0_default"))) __attribute__((noreturn));
 void start_cpu0_default(void) IRAM_ATTR __attribute__((noreturn));
-#if !CONFIG_FREERTOS_UNICORE
-static void IRAM_ATTR call_start_cpu1() __attribute__((noreturn));
-void start_cpu1(void) __attribute__((weak, alias("start_cpu1_default"))) __attribute__((noreturn));
-void start_cpu1_default(void) IRAM_ATTR __attribute__((noreturn));
-static bool app_cpu_started = false;
-#endif //!CONFIG_FREERTOS_UNICORE
 
 static void do_global_ctors(void);
 static void main_task(void* args);
@@ -114,11 +108,8 @@ static bool s_spiram_okay=true;
 
 void IRAM_ATTR call_start_cpu0()
 {
-#if CONFIG_FREERTOS_UNICORE
-    RESET_REASON rst_reas[1];
-#else
-    RESET_REASON rst_reas[2];
-#endif
+    RESET_REASON rst_reas;
+
     cpu_configure_region_protection();
 
     //Move exception vectors to IRAM
@@ -126,18 +117,10 @@ void IRAM_ATTR call_start_cpu0()
                   "wsr    %0, vecbase\n" \
                   ::"r"(&_init_start));
 
-    rst_reas[0] = rtc_get_reset_reason(0);
-
-#if !CONFIG_FREERTOS_UNICORE
-    rst_reas[1] = rtc_get_reset_reason(1);
-#endif
+    rst_reas = rtc_get_reset_reason(0);
 
     // from panic handler we can be reset by RWDT or TG0WDT
-    if (rst_reas[0] == RTCWDT_SYS_RESET || rst_reas[0] == TG0WDT_SYS_RESET
-#if !CONFIG_FREERTOS_UNICORE
-        || rst_reas[1] == RTCWDT_SYS_RESET || rst_reas[1] == TG0WDT_SYS_RESET
-#endif
-    ) {
+    if (rst_reas == RTCWDT_SYS_RESET || rst_reas == TG0WDT_SYS_RESET) {
 #ifndef CONFIG_BOOTLOADER_WDT_ENABLE
         rtc_wdt_disable();
 #endif
@@ -147,7 +130,7 @@ void IRAM_ATTR call_start_cpu0()
     memset(&_bss_start, 0, (&_bss_end - &_bss_start) * sizeof(_bss_start));
 
     /* Unless waking from deep sleep (implying RTC memory is intact), clear RTC bss */
-    if (rst_reas[0] != DEEPSLEEP_RESET) {
+    if (rst_reas != DEEPSLEEP_RESET) {
         memset(&_rtc_bss_start, 0, (&_rtc_bss_end - &_rtc_bss_start) * sizeof(_rtc_bss_start));
     }
 
@@ -192,32 +175,7 @@ extern void esp_switch_rodata_to_dcache(void);
 #endif
 
     ESP_EARLY_LOGI(TAG, "Pro cpu up.");
-
-#if !CONFIG_FREERTOS_UNICORE
-    ESP_EARLY_LOGI(TAG, "Starting app cpu, entry point is %p", call_start_cpu1);
-    //Flush and enable icache for APP CPU
-    Cache_Flush(1);
-    Cache_Read_Enable(1);
-    esp_cpu_unstall(1);
-    // Enable clock and reset APP CPU. Note that OpenOCD may have already
-    // enabled clock and taken APP CPU out of reset. In this case don't reset
-    // APP CPU again, as that will clear the breakpoints which may have already
-    // been set.
-    if (!DPORT_GET_PERI_REG_MASK(DPORT_APPCPU_CTRL_B_REG, DPORT_APPCPU_CLKGATE_EN)) {
-        DPORT_SET_PERI_REG_MASK(DPORT_APPCPU_CTRL_B_REG, DPORT_APPCPU_CLKGATE_EN);
-        DPORT_CLEAR_PERI_REG_MASK(DPORT_APPCPU_CTRL_C_REG, DPORT_APPCPU_RUNSTALL);
-        DPORT_SET_PERI_REG_MASK(DPORT_APPCPU_CTRL_A_REG, DPORT_APPCPU_RESETTING);
-        DPORT_CLEAR_PERI_REG_MASK(DPORT_APPCPU_CTRL_A_REG, DPORT_APPCPU_RESETTING);
-    }
-    ets_set_appcpu_boot_addr((uint32_t)call_start_cpu1);
-
-    while (!app_cpu_started) {
-        ets_delay_us(100);
-    }
-#else
     ESP_EARLY_LOGI(TAG, "Single core mode");
-#endif
-
 
 #if CONFIG_SPIRAM_MEMTEST
     if (s_spiram_okay) {
@@ -264,47 +222,11 @@ extern void esp_enable_cache_wrap(uint32_t icache_wrap_enable, uint32_t dcache_w
     start_cpu0();
 }
 
-#if !CONFIG_FREERTOS_UNICORE
-
-static void wdt_reset_cpu1_info_enable(void)
-{
-    DPORT_REG_SET_BIT(DPORT_APP_CPU_RECORD_CTRL_REG, DPORT_APP_CPU_PDEBUG_ENABLE | DPORT_APP_CPU_RECORD_ENABLE);
-    DPORT_REG_CLR_BIT(DPORT_APP_CPU_RECORD_CTRL_REG, DPORT_APP_CPU_RECORD_ENABLE);
-}
-
-void IRAM_ATTR call_start_cpu1()
-{
-    asm volatile (\
-                  "wsr    %0, vecbase\n" \
-                  ::"r"(&_init_start));
-
-    ets_set_appcpu_boot_addr(0);
-    cpu_configure_region_protection();
-
-#if CONFIG_CONSOLE_UART_NONE
-    ets_install_putc1(NULL);
-    ets_install_putc2(NULL);
-#else // CONFIG_CONSOLE_UART_NONE
-    uartAttach();
-    ets_install_uart_printf();
-    uart_tx_switch(CONFIG_ESP_CONSOLE_UART_NUM);
-#endif
-
-    wdt_reset_cpu1_info_enable();
-    ESP_EARLY_LOGI(TAG, "App cpu up.");
-    app_cpu_started = 1;
-    start_cpu1();
-}
-#endif //!CONFIG_FREERTOS_UNICORE
-
 static void intr_matrix_clear(void)
 {
     //Clear all the interrupt matrix register
     for (int i = ETS_WIFI_MAC_INTR_SOURCE; i < ETS_MAX_INTR_SOURCE; i++) {
         intr_matrix_set(0, i, ETS_INVALID_INUM);
-#if !CONFIG_FREERTOS_UNICORE
-        intr_matrix_set(1, i, ETS_INVALID_INUM);
-#endif
     }
 }
 
@@ -424,35 +346,6 @@ void start_cpu0_default(void)
     abort(); /* Only get to here if not enough free heap to start scheduler */
 }
 
-#if !CONFIG_FREERTOS_UNICORE
-void start_cpu1_default(void)
-{
-    // Wait for FreeRTOS initialization to finish on PRO CPU
-    while (port_xSchedulerRunning[0] == 0) {
-        ;
-    }
-#if CONFIG_ESP32S2_TRAX_TWOBANKS
-    trax_start_trace(TRAX_DOWNCOUNT_WORDS);
-#endif
-#if CONFIG_ESP32_APPTRACE_ENABLE
-    esp_err_t err = esp_apptrace_init();
-    assert(err == ESP_OK && "Failed to init apptrace module on APP CPU!");
-#endif
-#if CONFIG_ESP_INT_WDT
-    //Initialize the interrupt watch dog for CPU1.
-    //esp_int_wdt_cpu_init();
-#endif
-    //Take care putting stuff here: if asked, FreeRTOS will happily tell you the scheduler
-    //has started, but it isn't active *on this CPU* yet.
-    esp_cache_err_int_init();
-    esp_crosscore_int_init();
-
-    ESP_EARLY_LOGI(TAG, "Starting scheduler on APP CPU.");
-    xPortStartScheduler();
-    abort(); /* Only get to here if FreeRTOS somehow very broken */
-}
-#endif //!CONFIG_FREERTOS_UNICORE
-
 #ifdef CONFIG_COMPILER_CXX_EXCEPTIONS
 size_t __cxx_eh_arena_size_get()
 {
@@ -478,12 +371,7 @@ static void main_task(void* args)
     // Now that the application is about to start, disable boot watchdogs
     REG_CLR_BIT(TIMG_WDTCONFIG0_REG(0), TIMG_WDT_FLASHBOOT_MOD_EN_S);
     REG_CLR_BIT(RTC_CNTL_WDTCONFIG0_REG, RTC_CNTL_WDT_FLASHBOOT_MOD_EN);
-#if !CONFIG_FREERTOS_UNICORE
-    // Wait for FreeRTOS initialization to finish on APP CPU, before replacing its startup stack
-    while (port_xSchedulerRunning[1] == 0) {
-        ;
-    }
-#endif
+
     //Enable allocation in region where the startup stacks were located.
     heap_caps_enable_nonos_stack_heaps();