Merge branch 'fix/xts_aes_register_prefix_discrepency' into 'master'

fix: xts aes register prefix discrepancy

Closes DOC-5136 and DOC-5140

See merge request espressif/esp-idf!23900

components/hal/esp32c2/include/hal/spi_flash_encrypted_ll.h

@@ -15,7 +15,7 @@
 #include <stdbool.h>
 #include <string.h>
 #include "soc/system_reg.h"
-#include "soc/hwcrypto_reg.h"
+#include "soc/xts_aes_reg.h"
 #include "soc/soc.h"
 #include "hal/assert.h"
 
@@ -60,7 +60,7 @@ static inline void spi_flash_encrypt_ll_type(flash_encrypt_ll_type_t type)
 {
     // Our hardware only support flash encryption
     HAL_ASSERT(type == FLASH_ENCRYPTION_MANU);
-    REG_WRITE(AES_XTS_DESTINATION_REG, type);
+    REG_WRITE(XTS_AES_DESTINATION_REG, type);
 }
 
 /**
@@ -71,7 +71,7 @@ static inline void spi_flash_encrypt_ll_type(flash_encrypt_ll_type_t type)
 static inline void spi_flash_encrypt_ll_buffer_length(uint32_t size)
 {
     // Desired block should not be larger than the block size.
-    REG_WRITE(AES_XTS_SIZE_REG, size >> 5);
+    REG_WRITE(XTS_AES_LINESIZE_REG, size >> 5);
 }
 
 /**
@@ -85,7 +85,7 @@ static inline void spi_flash_encrypt_ll_buffer_length(uint32_t size)
 static inline void spi_flash_encrypt_ll_plaintext_save(uint32_t address, const uint32_t* buffer, uint32_t size)
 {
     uint32_t plaintext_offs = (address % 64);
-    memcpy((void *)(AES_XTS_PLAIN_BASE + plaintext_offs), buffer, size);
+    memcpy((void *)(XTS_AES_PLAIN_MEM + plaintext_offs), buffer, size);
 }
 
 /**
@@ -95,7 +95,7 @@ static inline void spi_flash_encrypt_ll_plaintext_save(uint32_t address, const u
  */
 static inline void spi_flash_encrypt_ll_address_save(uint32_t flash_addr)
 {
-    REG_WRITE(AES_XTS_PHYSICAL_ADDR_REG, flash_addr);
+    REG_WRITE(XTS_AES_PHYSICAL_ADDRESS_REG, flash_addr);
 }
 
 /**
@@ -103,7 +103,7 @@ static inline void spi_flash_encrypt_ll_address_save(uint32_t flash_addr)
  */
 static inline void spi_flash_encrypt_ll_calculate_start(void)
 {
-    REG_WRITE(AES_XTS_TRIGGER_REG, 1);
+    REG_WRITE(XTS_AES_TRIGGER_REG, 1);
 }
 
 /**
@@ -111,7 +111,7 @@ static inline void spi_flash_encrypt_ll_calculate_start(void)
  */
 static inline void spi_flash_encrypt_ll_calculate_wait_idle(void)
 {
-    while(REG_READ(AES_XTS_STATE_REG) == 0x1) {
+    while(REG_READ(XTS_AES_STATE_REG) == 0x1) {
     }
 }
 
@@ -120,8 +120,8 @@ static inline void spi_flash_encrypt_ll_calculate_wait_idle(void)
  */
 static inline void spi_flash_encrypt_ll_done(void)
 {
-    REG_WRITE(AES_XTS_RELEASE_REG, 1);
-    while(REG_READ(AES_XTS_STATE_REG) != 0x3) {
+    REG_WRITE(XTS_AES_RELEASE_REG, 1);
+    while(REG_READ(XTS_AES_STATE_REG) != 0x3) {
     }
 }
 
@@ -130,7 +130,7 @@ static inline void spi_flash_encrypt_ll_done(void)
  */
 static inline void spi_flash_encrypt_ll_destroy(void)
 {
-    REG_WRITE(AES_XTS_DESTROY_REG, 1);
+    REG_WRITE(XTS_AES_DESTROY_REG, 1);
 }
 
 /**

components/hal/esp32c3/include/hal/spi_flash_encrypted_ll.h

@@ -1,16 +1,8 @@
-// Copyright 2015-2021 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 
 /*******************************************************************************
  * NOTICE
@@ -23,7 +15,7 @@
 #include <stdbool.h>
 #include <string.h>
 #include "soc/system_reg.h"
-#include "soc/hwcrypto_reg.h"
+#include "soc/xts_aes_reg.h"
 #include "soc/soc.h"
 #include "hal/assert.h"
 
@@ -68,7 +60,7 @@ static inline void spi_flash_encrypt_ll_type(flash_encrypt_ll_type_t type)
 {
     // Our hardware only support flash encryption
     HAL_ASSERT(type == FLASH_ENCRYPTION_MANU);
-    REG_WRITE(AES_XTS_DESTINATION_REG, type);
+    REG_WRITE(XTS_AES_DESTINATION_REG, type);
 }
 
 /**
@@ -79,7 +71,7 @@ static inline void spi_flash_encrypt_ll_type(flash_encrypt_ll_type_t type)
 static inline void spi_flash_encrypt_ll_buffer_length(uint32_t size)
 {
     // Desired block should not be larger than the block size.
-    REG_WRITE(AES_XTS_SIZE_REG, size >> 5);
+    REG_WRITE(XTS_AES_LINESIZE_REG, size >> 5);
 }
 
 /**
@@ -93,7 +85,7 @@ static inline void spi_flash_encrypt_ll_buffer_length(uint32_t size)
 static inline void spi_flash_encrypt_ll_plaintext_save(uint32_t address, const uint32_t* buffer, uint32_t size)
 {
     uint32_t plaintext_offs = (address % 64);
-    memcpy((void *)(AES_XTS_PLAIN_BASE + plaintext_offs), buffer, size);
+    memcpy((void *)(XTS_AES_PLAIN_MEM + plaintext_offs), buffer, size);
 }
 
 /**
@@ -103,7 +95,7 @@ static inline void spi_flash_encrypt_ll_plaintext_save(uint32_t address, const u
  */
 static inline void spi_flash_encrypt_ll_address_save(uint32_t flash_addr)
 {
-    REG_WRITE(AES_XTS_PHYSICAL_ADDR_REG, flash_addr);
+    REG_WRITE(XTS_AES_PHYSICAL_ADDRESS_REG, flash_addr);
 }
 
 /**
@@ -111,7 +103,7 @@ static inline void spi_flash_encrypt_ll_address_save(uint32_t flash_addr)
  */
 static inline void spi_flash_encrypt_ll_calculate_start(void)
 {
-    REG_WRITE(AES_XTS_TRIGGER_REG, 1);
+    REG_WRITE(XTS_AES_TRIGGER_REG, 1);
 }
 
 /**
@@ -119,7 +111,7 @@ static inline void spi_flash_encrypt_ll_calculate_start(void)
  */
 static inline void spi_flash_encrypt_ll_calculate_wait_idle(void)
 {
-    while(REG_READ(AES_XTS_STATE_REG) == 0x1) {
+    while(REG_READ(XTS_AES_STATE_REG) == 0x1) {
     }
 }
 
@@ -128,8 +120,8 @@ static inline void spi_flash_encrypt_ll_calculate_wait_idle(void)
  */
 static inline void spi_flash_encrypt_ll_done(void)
 {
-    REG_WRITE(AES_XTS_RELEASE_REG, 1);
-    while(REG_READ(AES_XTS_STATE_REG) != 0x3) {
+    REG_WRITE(XTS_AES_RELEASE_REG, 1);
+    while(REG_READ(XTS_AES_STATE_REG) != 0x3) {
     }
 }
 
@@ -138,7 +130,7 @@ static inline void spi_flash_encrypt_ll_done(void)
  */
 static inline void spi_flash_encrypt_ll_destroy(void)
 {
-    REG_WRITE(AES_XTS_DESTROY_REG, 1);
+    REG_WRITE(XTS_AES_DESTROY_REG, 1);
 }
 
 /**

components/soc/esp32c2/include/soc/hwcrypto_reg.h

@@ -7,6 +7,7 @@
 #define __HWCRYPTO_REG_H__
 
 #include "soc.h"
+#include "soc/xts_aes_reg.h"
 
 #define SHA_MODE_SHA1       0
 #define SHA_MODE_SHA224     1
@@ -27,15 +28,4 @@
 #define SHA_H_BASE                    ((DR_REG_SHA_BASE) + 0x40)
 #define SHA_TEXT_BASE                 ((DR_REG_SHA_BASE) + 0x80)
 
-/* XTS-AES registers */
-#define AES_XTS_PLAIN_BASE        ((DR_REG_AES_XTS_BASE) + 0x00)
-#define AES_XTS_SIZE_REG          ((DR_REG_AES_XTS_BASE) + 0x40)
-#define AES_XTS_DESTINATION_REG   ((DR_REG_AES_XTS_BASE) + 0x44)
-#define AES_XTS_PHYSICAL_ADDR_REG ((DR_REG_AES_XTS_BASE) + 0x48)
-
-#define AES_XTS_TRIGGER_REG       ((DR_REG_AES_XTS_BASE) + 0x4C)
-#define AES_XTS_RELEASE_REG       ((DR_REG_AES_XTS_BASE) + 0x50)
-#define AES_XTS_DESTROY_REG       ((DR_REG_AES_XTS_BASE) + 0x54)
-#define AES_XTS_STATE_REG         ((DR_REG_AES_XTS_BASE) + 0x58)
-
 #endif

components/soc/esp32c2/include/soc/reg_base.h

@@ -41,4 +41,7 @@
 #define DR_REG_COEX_BIT_BASE                    0x6004C400
 #define DR_REG_MODEM_CLKRST_BASE                0x6004d800
 #define DR_REG_I2C_MST_BASE                     0x6004E800
-#define DR_REG_AES_XTS_BASE                     0x600CC000
+#define DR_REG_XTS_AES_BASE                     0x600CC000
+
+/* For backward compatability with the older register name */
+#define DR_REG_AES_XTS_BASE                     DR_REG_XTS_AES_BASE

components/soc/esp32c2/include/soc/xts_aes_reg.h

@@ -0,0 +1,135 @@
+/**
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** XTS_AES_PLAIN_MEM register
+ *  The memory that stores plaintext
+ */
+#define XTS_AES_PLAIN_MEM (DR_REG_XTS_AES_BASE + 0x0)
+#define XTS_AES_PLAIN_MEM_SIZE_BYTES 16
+
+/** XTS_AES_LINESIZE_REG register
+ *  XTS-AES line-size register
+ */
+#define XTS_AES_LINESIZE_REG (DR_REG_XTS_AES_BASE + 0x40)
+/** XTS_AES_LINESIZE : R/W; bitpos: [0]; default: 0;
+ *  This bit stores the line size parameter. 0: 16Byte, 1: 32Byte.
+ */
+#define XTS_AES_LINESIZE    (BIT(0))
+#define XTS_AES_LINESIZE_M  (XTS_AES_LINESIZE_V << XTS_AES_LINESIZE_S)
+#define XTS_AES_LINESIZE_V  0x00000001U
+#define XTS_AES_LINESIZE_S  0
+
+/** XTS_AES_DESTINATION_REG register
+ *  XTS-AES destination register
+ */
+#define XTS_AES_DESTINATION_REG (DR_REG_XTS_AES_BASE + 0x44)
+/** XTS_AES_DESTINATION : R/W; bitpos: [0]; default: 0;
+ *  This bit stores the destination. 0: flash(default). 1: reserved.
+ */
+#define XTS_AES_DESTINATION    (BIT(0))
+#define XTS_AES_DESTINATION_M  (XTS_AES_DESTINATION_V << XTS_AES_DESTINATION_S)
+#define XTS_AES_DESTINATION_V  0x00000001U
+#define XTS_AES_DESTINATION_S  0
+
+/** XTS_AES_PHYSICAL_ADDRESS_REG register
+ *  XTS-AES physical address register
+ */
+#define XTS_AES_PHYSICAL_ADDRESS_REG (DR_REG_XTS_AES_BASE + 0x48)
+/** XTS_AES_PHYSICAL_ADDRESS : R/W; bitpos: [29:0]; default: 0;
+ *  Those bits stores the physical address. If linesize is 16-byte, the physical
+ *  address should be aligned of 16 bytes. If linesize is 32-byte, the physical address
+ *  should be aligned of 32 bytes.
+ */
+#define XTS_AES_PHYSICAL_ADDRESS    0x3FFFFFFFU
+#define XTS_AES_PHYSICAL_ADDRESS_M  (XTS_AES_PHYSICAL_ADDRESS_V << XTS_AES_PHYSICAL_ADDRESS_S)
+#define XTS_AES_PHYSICAL_ADDRESS_V  0x3FFFFFFFU
+#define XTS_AES_PHYSICAL_ADDRESS_S  0
+
+/** XTS_AES_TRIGGER_REG register
+ *  XTS-AES trigger register
+ */
+#define XTS_AES_TRIGGER_REG (DR_REG_XTS_AES_BASE + 0x4c)
+/** XTS_AES_TRIGGER : WT; bitpos: [0]; default: 0;
+ *  Set this bit to start manual encryption calculation
+ */
+#define XTS_AES_TRIGGER    (BIT(0))
+#define XTS_AES_TRIGGER_M  (XTS_AES_TRIGGER_V << XTS_AES_TRIGGER_S)
+#define XTS_AES_TRIGGER_V  0x00000001U
+#define XTS_AES_TRIGGER_S  0
+
+/** XTS_AES_RELEASE_REG register
+ *  XTS-AES release register
+ */
+#define XTS_AES_RELEASE_REG (DR_REG_XTS_AES_BASE + 0x50)
+/** XTS_AES_RELEASE : WT; bitpos: [0]; default: 0;
+ *  Set this bit to release the manual encrypted result, after that the result will be
+ *  visible to spi
+ */
+#define XTS_AES_RELEASE    (BIT(0))
+#define XTS_AES_RELEASE_M  (XTS_AES_RELEASE_V << XTS_AES_RELEASE_S)
+#define XTS_AES_RELEASE_V  0x00000001U
+#define XTS_AES_RELEASE_S  0
+
+/** XTS_AES_DESTROY_REG register
+ *  XTS-AES destroy register
+ */
+#define XTS_AES_DESTROY_REG (DR_REG_XTS_AES_BASE + 0x54)
+/** XTS_AES_DESTROY : WT; bitpos: [0]; default: 0;
+ *  Set this bit to destroy XTS-AES result.
+ */
+#define XTS_AES_DESTROY    (BIT(0))
+#define XTS_AES_DESTROY_M  (XTS_AES_DESTROY_V << XTS_AES_DESTROY_S)
+#define XTS_AES_DESTROY_V  0x00000001U
+#define XTS_AES_DESTROY_S  0
+
+/** XTS_AES_STATE_REG register
+ *  XTS-AES status register
+ */
+#define XTS_AES_STATE_REG (DR_REG_XTS_AES_BASE + 0x58)
+/** XTS_AES_STATE : RO; bitpos: [1:0]; default: 0;
+ *  Those bits shows XTS-AES status. 0=IDLE, 1=WORK, 2=RELEASE, 3=USE. IDLE means that
+ *  XTS-AES is idle. WORK means that XTS-AES is busy with calculation. RELEASE means
+ *  the encrypted result is generated but not visible to mspi. USE means that the
+ *  encrypted result is visible to mspi.
+ */
+#define XTS_AES_STATE    0x00000003U
+#define XTS_AES_STATE_M  (XTS_AES_STATE_V << XTS_AES_STATE_S)
+#define XTS_AES_STATE_V  0x00000003U
+#define XTS_AES_STATE_S  0
+
+/** XTS_AES_DATE_REG register
+ *  XTS-AES version control register
+ */
+#define XTS_AES_DATE_REG (DR_REG_XTS_AES_BASE + 0x5c)
+/** XTS_AES_DATE : R/W; bitpos: [29:0]; default: 538969635;
+ *  Those bits stores the version information of XTS-AES.
+ */
+#define XTS_AES_DATE    0x3FFFFFFFU
+#define XTS_AES_DATE_M  (XTS_AES_DATE_V << XTS_AES_DATE_S)
+#define XTS_AES_DATE_V  0x3FFFFFFFU
+#define XTS_AES_DATE_S  0
+
+/* For backward compatability with the older register names */
+#define AES_XTS_PLAIN_BASE          XTS_AES_PLAIN_MEM
+#define AES_XTS_SIZE_REG            XTS_AES_LINESIZE_REG
+#define AES_XTS_DESTINATION_REG     XTS_AES_DESTINATION_REG
+#define AES_XTS_PHYSICAL_ADDR_REG   XTS_AES_PHYSICAL_ADDRESS_REG
+#define AES_XTS_TRIGGER_REG         XTS_AES_TRIGGER_REG
+#define AES_XTS_RELEASE_REG         XTS_AES_RELEASE_REG
+#define AES_XTS_DESTROY_REG         XTS_AES_DESTROY_REG
+#define AES_XTS_STATE_REG           XTS_AES_STATE_REG
+#define AES_XTS_DATE_REG            XTS_AES_DATE_REG
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32c3/include/soc/hwcrypto_reg.h

@@ -8,6 +8,7 @@
 #define __HWCRYPTO_REG_H__
 
 #include "soc.h"
+#include "soc/xts_aes_reg.h"
 
 /* registers for RSA acceleration via Multiple Precision Integer ops */
 #define RSA_MEM_M_BLOCK_BASE          ((DR_REG_RSA_BASE)+0x000)
@@ -136,19 +137,6 @@
 
 #define HMAC_DATE_REG                  ((DR_REG_HMAC_BASE) + 0xF8)
 
-
-/* XTS-AES registers */
-#define AES_XTS_PLAIN_BASE        ((DR_REG_AES_XTS_BASE) + 0x00)
-#define AES_XTS_SIZE_REG          ((DR_REG_AES_XTS_BASE) + 0x40)
-#define AES_XTS_DESTINATION_REG   ((DR_REG_AES_XTS_BASE) + 0x44)
-#define AES_XTS_PHYSICAL_ADDR_REG ((DR_REG_AES_XTS_BASE) + 0x48)
-
-#define AES_XTS_TRIGGER_REG       ((DR_REG_AES_XTS_BASE) + 0x4C)
-#define AES_XTS_RELEASE_REG       ((DR_REG_AES_XTS_BASE) + 0x50)
-#define AES_XTS_DESTROY_REG       ((DR_REG_AES_XTS_BASE) + 0x54)
-#define AES_XTS_STATE_REG         ((DR_REG_AES_XTS_BASE) + 0x58)
-#define AES_XTS_DATE_REG          ((DR_REG_AES_XTS_BASE) + 0x5C)
-
 /* Digital Signature registers and memory blocks */
 #define DS_C_BASE                 ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0x000 )
 #define DS_C_Y_BASE               ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0x000 )

components/soc/esp32c3/include/soc/reg_base.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -44,4 +44,7 @@
 #define DR_REG_I2S0_BASE                        0x6002D000
 #define DR_REG_APB_SARADC_BASE                  0x60040000
 #define DR_REG_USB_SERIAL_JTAG_BASE             0x60043000
-#define DR_REG_AES_XTS_BASE                     0x600CC000
+#define DR_REG_XTS_AES_BASE                     0x600CC000
+
+/* For backward compatability with the older register names */
+#define DR_REG_AES_XTS_BASE                     DR_REG_XTS_AES_BASE

components/soc/esp32c3/include/soc/xts_aes_reg.h

@@ -0,0 +1,135 @@
+/**
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** XTS_AES_PLAIN_MEM register
+ *  The memory that stores plaintext
+ */
+#define XTS_AES_PLAIN_MEM (DR_REG_XTS_AES_BASE + 0x0)
+#define XTS_AES_PLAIN_MEM_SIZE_BYTES 16
+
+/** XTS_AES_LINESIZE_REG register
+ *  XTS-AES line-size register
+ */
+#define XTS_AES_LINESIZE_REG (DR_REG_XTS_AES_BASE + 0x40)
+/** XTS_AES_LINESIZE : R/W; bitpos: [0]; default: 0;
+ *  This bit stores the line size parameter. 0: 16Byte, 1: 32Byte.
+ */
+#define XTS_AES_LINESIZE    (BIT(0))
+#define XTS_AES_LINESIZE_M  (XTS_AES_LINESIZE_V << XTS_AES_LINESIZE_S)
+#define XTS_AES_LINESIZE_V  0x00000001U
+#define XTS_AES_LINESIZE_S  0
+
+/** XTS_AES_DESTINATION_REG register
+ *  XTS-AES destination register
+ */
+#define XTS_AES_DESTINATION_REG (DR_REG_XTS_AES_BASE + 0x44)
+/** XTS_AES_DESTINATION : R/W; bitpos: [0]; default: 0;
+ *  This bit stores the destination. 0: flash(default). 1: reserved.
+ */
+#define XTS_AES_DESTINATION    (BIT(0))
+#define XTS_AES_DESTINATION_M  (XTS_AES_DESTINATION_V << XTS_AES_DESTINATION_S)
+#define XTS_AES_DESTINATION_V  0x00000001U
+#define XTS_AES_DESTINATION_S  0
+
+/** XTS_AES_PHYSICAL_ADDRESS_REG register
+ *  XTS-AES physical address register
+ */
+#define XTS_AES_PHYSICAL_ADDRESS_REG (DR_REG_XTS_AES_BASE + 0x48)
+/** XTS_AES_PHYSICAL_ADDRESS : R/W; bitpos: [29:0]; default: 0;
+ *  Those bits stores the physical address. If linesize is 16-byte, the physical
+ *  address should be aligned of 16 bytes. If linesize is 32-byte, the physical address
+ *  should be aligned of 32 bytes.
+ */
+#define XTS_AES_PHYSICAL_ADDRESS    0x3FFFFFFFU
+#define XTS_AES_PHYSICAL_ADDRESS_M  (XTS_AES_PHYSICAL_ADDRESS_V << XTS_AES_PHYSICAL_ADDRESS_S)
+#define XTS_AES_PHYSICAL_ADDRESS_V  0x3FFFFFFFU
+#define XTS_AES_PHYSICAL_ADDRESS_S  0
+
+/** XTS_AES_TRIGGER_REG register
+ *  XTS-AES trigger register
+ */
+#define XTS_AES_TRIGGER_REG (DR_REG_XTS_AES_BASE + 0x4c)
+/** XTS_AES_TRIGGER : WT; bitpos: [0]; default: 0;
+ *  Set this bit to start manual encryption calculation
+ */
+#define XTS_AES_TRIGGER    (BIT(0))
+#define XTS_AES_TRIGGER_M  (XTS_AES_TRIGGER_V << XTS_AES_TRIGGER_S)
+#define XTS_AES_TRIGGER_V  0x00000001U
+#define XTS_AES_TRIGGER_S  0
+
+/** XTS_AES_RELEASE_REG register
+ *  XTS-AES release register
+ */
+#define XTS_AES_RELEASE_REG (DR_REG_XTS_AES_BASE + 0x50)
+/** XTS_AES_RELEASE : WT; bitpos: [0]; default: 0;
+ *  Set this bit to release the manual encrypted result, after that the result will be
+ *  visible to spi
+ */
+#define XTS_AES_RELEASE    (BIT(0))
+#define XTS_AES_RELEASE_M  (XTS_AES_RELEASE_V << XTS_AES_RELEASE_S)
+#define XTS_AES_RELEASE_V  0x00000001U
+#define XTS_AES_RELEASE_S  0
+
+/** XTS_AES_DESTROY_REG register
+ *  XTS-AES destroy register
+ */
+#define XTS_AES_DESTROY_REG (DR_REG_XTS_AES_BASE + 0x54)
+/** XTS_AES_DESTROY : WT; bitpos: [0]; default: 0;
+ *  Set this bit to destroy XTS-AES result.
+ */
+#define XTS_AES_DESTROY    (BIT(0))
+#define XTS_AES_DESTROY_M  (XTS_AES_DESTROY_V << XTS_AES_DESTROY_S)
+#define XTS_AES_DESTROY_V  0x00000001U
+#define XTS_AES_DESTROY_S  0
+
+/** XTS_AES_STATE_REG register
+ *  XTS-AES status register
+ */
+#define XTS_AES_STATE_REG (DR_REG_XTS_AES_BASE + 0x58)
+/** XTS_AES_STATE : RO; bitpos: [1:0]; default: 0;
+ *  Those bits shows XTS-AES status. 0=IDLE, 1=WORK, 2=RELEASE, 3=USE. IDLE means that
+ *  XTS-AES is idle. WORK means that XTS-AES is busy with calculation. RELEASE means
+ *  the encrypted result is generated but not visible to mspi. USE means that the
+ *  encrypted result is visible to mspi.
+ */
+#define XTS_AES_STATE    0x00000003U
+#define XTS_AES_STATE_M  (XTS_AES_STATE_V << XTS_AES_STATE_S)
+#define XTS_AES_STATE_V  0x00000003U
+#define XTS_AES_STATE_S  0
+
+/** XTS_AES_DATE_REG register
+ *  XTS-AES version control register
+ */
+#define XTS_AES_DATE_REG (DR_REG_XTS_AES_BASE + 0x5c)
+/** XTS_AES_DATE : R/W; bitpos: [29:0]; default: 538969635;
+ *  Those bits stores the version information of XTS-AES.
+ */
+#define XTS_AES_DATE    0x3FFFFFFFU
+#define XTS_AES_DATE_M  (XTS_AES_DATE_V << XTS_AES_DATE_S)
+#define XTS_AES_DATE_V  0x3FFFFFFFU
+#define XTS_AES_DATE_S  0
+
+/* For backward compatability with the older register names */
+#define AES_XTS_PLAIN_BASE          XTS_AES_PLAIN_MEM
+#define AES_XTS_SIZE_REG            XTS_AES_LINESIZE_REG
+#define AES_XTS_DESTINATION_REG     XTS_AES_DESTINATION_REG
+#define AES_XTS_PHYSICAL_ADDR_REG   XTS_AES_PHYSICAL_ADDRESS_REG
+#define AES_XTS_TRIGGER_REG         XTS_AES_TRIGGER_REG
+#define AES_XTS_RELEASE_REG         XTS_AES_RELEASE_REG
+#define AES_XTS_DESTROY_REG         XTS_AES_DESTROY_REG
+#define AES_XTS_STATE_REG           XTS_AES_STATE_REG
+#define AES_XTS_DATE_REG            XTS_AES_DATE_REG
+
+#ifdef __cplusplus
+}
+#endif

tools/ci/check_copyright_ignore.txt

@@ -610,7 +610,6 @@ components/hal/esp32c3/include/hal/hmac_hal.h
 components/hal/esp32c3/include/hal/hmac_ll.h
 components/hal/esp32c3/include/hal/mpu_ll.h
 components/hal/esp32c3/include/hal/sha_ll.h
-components/hal/esp32c3/include/hal/spi_flash_encrypted_ll.h
 components/hal/esp32c3/include/hal/uhci_ll.h
 components/hal/esp32c3/rtc_cntl_hal.c
 components/hal/esp32s2/include/hal/crypto_dma_ll.h