lcd: rgb pclk idle default to low

components/esp_lcd/include/esp_lcd_panel_rgb.h

@@ -18,10 +18,10 @@ extern "C" {
 #if SOC_LCD_RGB_SUPPORTED
 /**
  * @brief LCD RGB timing structure
- *
+ * @verbatim
  *                                                 Total Width
  *                             <--------------------------------------------------->
- *                       Hsync width HBP             Active Width                HFP
+ *                       HSYNC width HBP             Active Width                HFP
  *                             <---><--><--------------------------------------><--->
  *                         ____    ____|_______________________________________|____|
  *                             |___|   |                                       |    |
@@ -36,7 +36,7 @@ extern "C" {
  *             |     /|\     |         | / / / / / / / / / / / / / / / / / / / |    |
  *             |      |      |         |/ / / / / / / / / / / / / / / / / / / /|    |
  *    Total    |      |      |         |/ / / / / / / / / / / / / / / / / / / /|    |
- *    Heigh    |      |      |         |/ / / / / / / / / / / / / / / / / / / /|    |
+ *    Height   |      |      |         |/ / / / / / / / / / / / / / / / / / / /|    |
  *             |Active|      |         |/ / / / / / / / / / / / / / / / / / / /|    |
  *             |Heigh |      |         |/ / / / / / Active Display Area / / / /|    |
  *             |      |      |         |/ / / / / / / / / / / / / / / / / / / /|    |
@@ -48,7 +48,7 @@ extern "C" {
  *             |     /|\     |                                                      |
  *             |  VFP |      |                                                      |
  *            \|/    \|/_____|______________________________________________________|
- *
+ * @endverbatim
  */
 typedef struct {
     unsigned int pclk_hz;           /*!< Frequency of pixel clock */
@@ -65,7 +65,7 @@ typedef struct {
         unsigned int vsync_idle_low: 1;  /*!< The vsync signal is low in IDLE state */
         unsigned int de_idle_high: 1;    /*!< The de signal is high in IDLE state */
         unsigned int pclk_active_neg: 1; /*!< The display will write data lines when there's a falling edge on PCLK */
-        unsigned int pclk_idle_low: 1;   /*!< The PCLK stays at low level in IDLE phase */
+        unsigned int pclk_idle_high: 1;  /*!< The PCLK stays at high level in IDLE phase */
     } flags;
 } esp_lcd_rgb_timing_t;
 

components/esp_lcd/src/esp_lcd_rgb_panel.c

@@ -250,7 +250,7 @@ static esp_err_t rgb_panel_init(esp_lcd_panel_t *panel)
     lcd_ll_set_pixel_clock_prescale(rgb_panel->hal.dev, pclk_prescale);
     rgb_panel->timings.pclk_hz = rgb_panel->resolution_hz / pclk_prescale;
     // pixel clock phase and polarity
-    lcd_ll_set_clock_idle_level(rgb_panel->hal.dev, !rgb_panel->timings.flags.pclk_idle_low);
+    lcd_ll_set_clock_idle_level(rgb_panel->hal.dev, rgb_panel->timings.flags.pclk_idle_high);
     lcd_ll_set_pixel_clock_edge(rgb_panel->hal.dev, rgb_panel->timings.flags.pclk_active_neg);
     // enable RGB mode and set data width
     lcd_ll_enable_rgb_mode(rgb_panel->hal.dev, true);

components/hal/esp32s3/include/hal/lcd_ll.h

@@ -35,7 +35,6 @@ static inline void lcd_ll_set_group_clock_src(lcd_cam_dev_t *dev, lcd_clock_sour
 {
     // lcd_clk = module_clock_src / (div_num + div_b / div_a)
     HAL_ASSERT(div_num >= 2);
-    dev->lcd_clock.lcd_clk_sel = src;
     HAL_FORCE_MODIFY_U32_REG_FIELD(dev->lcd_clock, lcd_clkm_div_num, div_num);
     dev->lcd_clock.lcd_clkm_div_a = div_a;
     dev->lcd_clock.lcd_clkm_div_b = div_b;
@@ -43,9 +42,6 @@ static inline void lcd_ll_set_group_clock_src(lcd_cam_dev_t *dev, lcd_clock_sour
     case LCD_CLK_SRC_PLL160M:
         dev->lcd_clock.lcd_clk_sel = 3;
         break;
-    case LCD_CLK_SRC_APLL:
-        dev->lcd_clock.lcd_clk_sel = 2;
-        break;
     case LCD_CLK_SRC_XTAL:
         dev->lcd_clock.lcd_clk_sel = 1;
         break;

components/hal/include/hal/lcd_types.h

@@ -13,12 +13,17 @@ extern "C" {
 /**
  * @brief LCD clock source
  * @note User should select the clock source based on the real requirement:
- *
- * | LCD clock source    | Features                 | Power Management           |
- * |---------------------|--------------------------|----------------------------|
- * | LCD_CLK_SRC_PLL160M | High resolution, fixed   | ESP_PM_APB_FREQ_MAX lock   |
- * | LCD_CLK_SRC_APLL    | Configurable resolution  | ESP_PM_NO_LIGHT_SLEEP lock |
- * | LCD_CLK_SRC_XTAL    | Medium resolution, fixed | No PM lock                 |
+ * @verbatim embed:rst:leading-asterisk
+ * +---------------------+-------------------------+----------------------------+
+ * | LCD clock source    | Features                | Power Management           |
+ * +=====================+=========================+============================+
+ * | LCD_CLK_SRC_PLL160M | High resolution         | ESP_PM_APB_FREQ_MAX lock   |
+ * +---------------------+-------------------------+----------------------------+
+ * | LCD_CLK_SRC_APLL    | Configurable resolution | ESP_PM_NO_LIGHT_SLEEP lock |
+ * +---------------------+-------------------------+----------------------------+
+ * | LCD_CLK_SRC_XTAL    | Medium resolution       | No PM lock                 |
+ * +---------------------+-------------------------+----------------------------+
+ * @endverbatim
  */
 typedef enum {
     LCD_CLK_SRC_PLL160M, /*!< Select PLL160M as the source clock */