Merge branch 'feature/support_access_internal_i2c_register_backport_v4.2' into 'release/v4.2'

feature(rtc): add new APIs support access internal i2c register (backport v4.2)

See merge request espressif/esp-idf!10662

components/bootloader/subproject/main/ld/esp32s2/bootloader.ld

@@ -39,6 +39,7 @@ SECTIONS
     *libmicro-ecc.a:*.*(.literal .text .literal.* .text.*)
     *libspi_flash.a:*.*(.literal .text .literal.* .text.*)
     *libsoc.a:wdt_hal_iram.*(.literal .text .literal.* .text.*)
+    *libsoc.a:regi2c_ctrl.*(.literal .text .literal.* .text.*)
     *libefuse.a:*.*(.literal .text .literal.* .text.*)
     *(.fini.literal)
     *(.fini)

components/driver/esp32s2/rtc_tempsensor.c

@@ -25,6 +25,7 @@
 #include "soc/sens_struct.h"
 #include "driver/temp_sensor.h"
 #include "esp32s2/rom/ets_sys.h"
+#include "regi2c_ctrl.h"
 
 static const char *TAG = "tsens";
 
@@ -39,18 +40,6 @@ static const char *TAG = "tsens";
 #define TSENS_DAC_FACTOR  (27.88)
 #define TSENS_SYS_OFFSET  (20.52)
 
-#include "i2c_rtc_clk.h"
-
-#define ANA_CONFIG2_REG  0x6000E048
-#define ANA_CONFIG2_M   (BIT(18))
-
-#define I2C_ADC            0X69
-#define I2C_ADC_HOSTID     1
-
-#define I2C_SARADC_TSENS_DAC        6
-#define I2C_SARADC_TSENS_DAC_MSB    3
-#define I2C_SARADC_TSENS_DAC_LSB    0
-
 typedef struct {
     int index;
     int offset;
@@ -75,9 +64,9 @@ esp_err_t temp_sensor_set_config(temp_sensor_config_t tsens)
 {
     CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_FORCE_PD_M);
     SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_FORCE_PU_M);
-    CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, BIT(18));
-    SET_PERI_REG_MASK(ANA_CONFIG2_REG, BIT(16));
-    I2C_WRITEREG_MASK_RTC(I2C_ADC, I2C_SARADC_TSENS_DAC, dac_offset[tsens.dac_offset].set_val);
+    CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, I2C_SAR_M);
+    SET_PERI_REG_MASK(ANA_CONFIG2_REG, ANA_SAR_CFG2_M);
+    REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_TSENS_DAC, dac_offset[tsens.dac_offset].set_val);
     SENS.sar_tctrl.tsens_clk_div = tsens.clk_div;
     SENS.sar_tctrl.tsens_power_up_force = 1;
     SENS.sar_tctrl2.tsens_xpd_wait = TSENS_XPD_WAIT_DEFAULT;
@@ -96,9 +85,9 @@ esp_err_t temp_sensor_get_config(temp_sensor_config_t *tsens)
     TSENS_CHECK(tsens != NULL, ESP_ERR_INVALID_ARG);
     CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_FORCE_PD_M);
     SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_FORCE_PU_M);
-    CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, BIT(18));
-    SET_PERI_REG_MASK(ANA_CONFIG2_REG, BIT(16));
-    tsens->dac_offset = I2C_READREG_MASK_RTC(I2C_ADC, I2C_SARADC_TSENS_DAC);
+    CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, I2C_SAR_M);
+    SET_PERI_REG_MASK(ANA_CONFIG2_REG, ANA_SAR_CFG2_M);
+    tsens->dac_offset = REGI2C_READ_MASK(I2C_SAR_ADC, I2C_SARADC_TSENS_DAC);
     for (int i = TSENS_DAC_L0; i < TSENS_DAC_MAX; i++) {
         if (tsens->dac_offset == dac_offset[i].set_val) {
             tsens->dac_offset = dac_offset[i].index;

components/soc/soc/component.mk

@@ -1,2 +1,2 @@
-COMPONENT_ADD_INCLUDEDIRS += soc/include soc/$(SOC_NAME) soc/$(SOC_NAME)/include
+COMPONENT_ADD_INCLUDEDIRS += soc/include soc/$(SOC_NAME)/private_include soc/$(SOC_NAME)/include
 COMPONENT_SRCDIRS += soc/$(SOC_NAME)

components/soc/soc/esp32/CMakeLists.txt

@@ -14,4 +14,4 @@ add_library(soc_esp32 STATIC
     "uart_periph.c"
     "touch_sensor_periph.c")
 
-target_include_directories(soc_esp32 PUBLIC . include ../include)
+target_include_directories(soc_esp32 PUBLIC include ../include private_include)

components/soc/soc/esp32/i2c_apll.h → components/soc/soc/esp32/private_include/regi2c_apll.h

@@ -15,11 +15,11 @@
 #pragma once
 
 /**
- * @file i2c_apll.h
+ * @file regi2c_apll.h
  * @brief Register definitions for audio PLL (APLL)
  *
  * This file lists register fields of APLL, located on an internal configuration
- * bus. These definitions are used via macros defined in i2c_rtc_clk.h, by
+ * bus. These definitions are used via macros defined in regi2c_ctrl.h, by
  * rtc_clk_apll_enable function in rtc_clk.c.
  */
 

components/soc/soc/esp32/i2c_bbpll.h → components/soc/soc/esp32/private_include/regi2c_bbpll.h

@@ -15,11 +15,11 @@
 #pragma once
 
 /**
- * @file i2c_apll.h
+ * @file regi2c_apll.h
  * @brief Register definitions for digital PLL (BBPLL)
  *
  * This file lists register fields of BBPLL, located on an internal configuration
- * bus. These definitions are used via macros defined in i2c_rtc_clk.h, by
+ * bus. These definitions are used via macros defined in regi2c_ctrl.h, by
  * rtc_clk_cpu_freq_set function in rtc_clk.c.
  */
 

components/soc/soc/esp32s2/CMakeLists.txt

@@ -13,4 +13,4 @@ add_library(soc_esp32s2 STATIC
     "usb_periph.c"
     "touch_sensor_periph.c")
 
-target_include_directories(soc_esp32s2 PUBLIC . include ../include)
+target_include_directories(soc_esp32s2 PUBLIC include ../include private_include)

components/soc/soc/esp32s2/i2c_apll.h → components/soc/soc/esp32s2/private_include/regi2c_apll.h

@@ -15,11 +15,11 @@
 #pragma once
 
 /**
- * @file i2c_apll.h
+ * @file regi2c_apll.h
  * @brief Register definitions for audio PLL (APLL)
  *
  * This file lists register fields of APLL, located on an internal configuration
- * bus. These definitions are used via macros defined in i2c_rtc_clk.h, by
+ * bus. These definitions are used via macros defined in regi2c_ctrl.h, by
  * rtc_clk_apll_enable function in rtc_clk.c.
  */
 

components/soc/soc/esp32s2/i2c_bbpll.h → components/soc/soc/esp32s2/private_include/regi2c_bbpll.h

@@ -15,11 +15,11 @@
 #pragma once
 
 /**
- * @file i2c_apll.h
+ * @file regi2c_apll.h
  * @brief Register definitions for digital PLL (BBPLL)
  *
  * This file lists register fields of BBPLL, located on an internal configuration
- * bus. These definitions are used via macros defined in i2c_rtc_clk.h, by
+ * bus. These definitions are used via macros defined in regi2c_ctrl.h, by
  * rtc_clk_cpu_freq_set function in rtc_clk.c.
  */
 

components/soc/src/esp32s2/i2c_brownout.h → components/soc/soc/esp32s2/private_include/regi2c_brownout.h

@@ -15,11 +15,11 @@
 #pragma once
 
 /**
- * @file i2c_brownout.h
+ * @file regi2c_brownout.h
  * @brief Register definitions for brownout detector
  *
  * This file lists register fields of the brownout detector, located on an internal configuration
- * bus. These definitions are used via macros defined in i2c_rtc_clk.h.
+ * bus. These definitions are used via macros defined in regi2c_ctrl.h.
  */
 
 #define I2C_BOD            0x61

components/soc/soc/esp32s2/private_include/regi2c_saradc.h

@@ -0,0 +1,79 @@
+// Copyright 2019-2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#pragma once
+
+/**
+ * @file regi2c_saradc.h
+ * @brief Register definitions for analog to calibrate initial code for getting a more precise voltage of SAR ADC.
+ *
+ * This file lists register fields of SAR, located on an internal configuration
+ * bus. These definitions are used via macros defined in regi2c_ctrl.h, by
+ * function in adc_ll.h.
+ */
+
+#define I2C_SAR_ADC            0X69
+#define I2C_SAR_ADC_HOSTID     1
+
+#define ADC_SAR1_ENCAL_GND_ADDR 0x7
+#define ADC_SAR1_ENCAL_GND_ADDR_MSB 5
+#define ADC_SAR1_ENCAL_GND_ADDR_LSB 5
+
+#define ADC_SAR2_ENCAL_GND_ADDR 0x7
+#define ADC_SAR2_ENCAL_GND_ADDR_MSB 7
+#define ADC_SAR2_ENCAL_GND_ADDR_LSB 7
+
+#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR 0x1
+#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR_MSB 0x3
+#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR_LSB 0x0
+
+#define ADC_SAR1_INITIAL_CODE_LOW_ADDR  0x0
+#define ADC_SAR1_INITIAL_CODE_LOW_ADDR_MSB  0x7
+#define ADC_SAR1_INITIAL_CODE_LOW_ADDR_LSB  0x0
+
+#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR 0x4
+#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_MSB 0x3
+#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_LSB 0x0
+
+#define ADC_SAR2_INITIAL_CODE_LOW_ADDR  0x3
+#define ADC_SAR2_INITIAL_CODE_LOW_ADDR_MSB  0x7
+#define ADC_SAR2_INITIAL_CODE_LOW_ADDR_LSB  0x0
+
+#define ADC_SAR1_DREF_ADDR  0x2
+#define ADC_SAR1_DREF_ADDR_MSB  0x6
+#define ADC_SAR1_DREF_ADDR_LSB  0x4
+
+#define ADC_SAR2_DREF_ADDR  0x5
+#define ADC_SAR2_DREF_ADDR_MSB  0x6
+#define ADC_SAR2_DREF_ADDR_LSB  0x4
+
+#define ADC_SAR1_SAMPLE_CYCLE_ADDR 0x2
+#define ADC_SAR1_SAMPLE_CYCLE_ADDR_MSB 0x2
+#define ADC_SAR1_SAMPLE_CYCLE_ADDR_LSB 0x0
+
+#define ADC_SARADC_DTEST_RTC_ADDR 0x7
+#define ADC_SARADC_DTEST_RTC_ADDR_MSB 1
+#define ADC_SARADC_DTEST_RTC_ADDR_LSB 0
+
+#define ADC_SARADC_ENT_TSENS_ADDR 0x7
+#define ADC_SARADC_ENT_TSENS_ADDR_MSB 2
+#define ADC_SARADC_ENT_TSENS_ADDR_LSB 2
+
+#define ADC_SARADC_ENT_RTC_ADDR 0x7
+#define ADC_SARADC_ENT_RTC_ADDR_MSB 3
+#define ADC_SARADC_ENT_RTC_ADDR_LSB 3
+
+#define I2C_SARADC_TSENS_DAC 0x6
+#define I2C_SARADC_TSENS_DAC_MSB 3
+#define I2C_SARADC_TSENS_DAC_LSB 0

components/soc/soc/esp32s2/i2c_ulp.h → components/soc/soc/esp32s2/private_include/regi2c_ulp.h

@@ -15,11 +15,11 @@
 #pragma once
 
 /**
- * @file i2c_ulp.h
+ * @file regi2c_ulp.h
  * @brief Register definitions for analog to calibrate o_code for getting a more precise voltage.
  *
  * This file lists register fields of ULP, located on an internal configuration
- * bus. These definitions are used via macros defined in i2c_rtc_clk.h, by
+ * bus. These definitions are used via macros defined in regi2c_ctrl.h, by
  * rtc_init function in rtc_init.c.
  */
 

components/soc/src/esp32/i2c_rtc_clk.h → components/soc/src/esp32/regi2c_ctrl.h

@@ -14,8 +14,9 @@
 
 #pragma once
 
-#include "i2c_apll.h"
-#include "i2c_bbpll.h"
+#include <stdint.h>
+#include "regi2c_apll.h"
+#include "regi2c_bbpll.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -37,18 +38,18 @@ void rom_i2c_writeReg(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t d
 void rom_i2c_writeReg_Mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data);
 
 /* Convenience macros for the above functions, these use register definitions
- * from i2c_apll.h/i2c_bbpll.h header files.
+ * from regi2c_apll.h/regi2c_bbpll.h header files.
  */
-#define I2C_WRITEREG_MASK_RTC(block, reg_add, indata) \
+#define REGI2C_WRITE_MASK(block, reg_add, indata) \
       rom_i2c_writeReg_Mask(block, block##_HOSTID,  reg_add,  reg_add##_MSB,  reg_add##_LSB,  indata)
 
-#define I2C_READREG_MASK_RTC(block, reg_add) \
+#define REGI2C_READ_MASK(block, reg_add) \
       rom_i2c_readReg_Mask(block, block##_HOSTID,  reg_add,  reg_add##_MSB,  reg_add##_LSB)
 
-#define I2C_WRITEREG_RTC(block, reg_add, indata) \
+#define REGI2C_WRITE(block, reg_add, indata) \
       rom_i2c_writeReg(block, block##_HOSTID,  reg_add, indata)
 
-#define I2C_READREG_RTC(block, reg_add) \
+#define REGI2C_READ(block, reg_add) \
       rom_i2c_readReg(block, block##_HOSTID,  reg_add)
 
 

components/soc/src/esp32/rtc_clk.c

@@ -26,7 +26,7 @@
 #include "soc/dport_reg.h"
 #include "soc/efuse_periph.h"
 #include "soc/apb_ctrl_reg.h"
-#include "i2c_rtc_clk.h"
+#include "regi2c_ctrl.h"
 #include "soc_log.h"
 #include "sdkconfig.h"
 #include "xtensa/core-macros.h"
@@ -253,21 +253,21 @@ void rtc_clk_apll_enable(bool enable, uint32_t sdm0, uint32_t sdm1, uint32_t sdm
             sdm1 = 0;
             sdm_stop_val_2 = APLL_SDM_STOP_VAL_2_REV0;
         }
-        I2C_WRITEREG_MASK_RTC(I2C_APLL, I2C_APLL_DSDM2, sdm2);
-        I2C_WRITEREG_MASK_RTC(I2C_APLL, I2C_APLL_DSDM0, sdm0);
-        I2C_WRITEREG_MASK_RTC(I2C_APLL, I2C_APLL_DSDM1, sdm1);
-        I2C_WRITEREG_RTC(I2C_APLL, I2C_APLL_SDM_STOP, APLL_SDM_STOP_VAL_1);
-        I2C_WRITEREG_RTC(I2C_APLL, I2C_APLL_SDM_STOP, sdm_stop_val_2);
-        I2C_WRITEREG_MASK_RTC(I2C_APLL, I2C_APLL_OR_OUTPUT_DIV, o_div);
+        REGI2C_WRITE_MASK(I2C_APLL, I2C_APLL_DSDM2, sdm2);
+        REGI2C_WRITE_MASK(I2C_APLL, I2C_APLL_DSDM0, sdm0);
+        REGI2C_WRITE_MASK(I2C_APLL, I2C_APLL_DSDM1, sdm1);
+        REGI2C_WRITE(I2C_APLL, I2C_APLL_SDM_STOP, APLL_SDM_STOP_VAL_1);
+        REGI2C_WRITE(I2C_APLL, I2C_APLL_SDM_STOP, sdm_stop_val_2);
+        REGI2C_WRITE_MASK(I2C_APLL, I2C_APLL_OR_OUTPUT_DIV, o_div);
 
         /* calibration */
-        I2C_WRITEREG_RTC(I2C_APLL, I2C_APLL_IR_CAL_DELAY, APLL_CAL_DELAY_1);
-        I2C_WRITEREG_RTC(I2C_APLL, I2C_APLL_IR_CAL_DELAY, APLL_CAL_DELAY_2);
-        I2C_WRITEREG_RTC(I2C_APLL, I2C_APLL_IR_CAL_DELAY, APLL_CAL_DELAY_3);
+        REGI2C_WRITE(I2C_APLL, I2C_APLL_IR_CAL_DELAY, APLL_CAL_DELAY_1);
+        REGI2C_WRITE(I2C_APLL, I2C_APLL_IR_CAL_DELAY, APLL_CAL_DELAY_2);
+        REGI2C_WRITE(I2C_APLL, I2C_APLL_IR_CAL_DELAY, APLL_CAL_DELAY_3);
 
         /* wait for calibration end */
-        while (!(I2C_READREG_MASK_RTC(I2C_APLL, I2C_APLL_OR_CAL_END))) {
-            /* use ets_delay_us so the RTC bus doesn't get flooded */
+        while (!(REGI2C_READ_MASK(I2C_APLL, I2C_APLL_OR_CAL_END))) {
+            /* use esp_rom_delay_us so the RTC bus doesn't get flooded */
             ets_delay_us(1);
         }
     }
@@ -356,8 +356,8 @@ void rtc_clk_bbpll_configure(rtc_xtal_freq_t xtal_freq, int pll_freq)
                 bw = 0;
                 break;
         }
-        I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_ENDIV5, BBPLL_ENDIV5_VAL_320M);
-        I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_BBADC_DSMP, BBPLL_BBADC_DSMP_VAL_320M);
+        REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_ENDIV5, BBPLL_ENDIV5_VAL_320M);
+        REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_BBADC_DSMP, BBPLL_BBADC_DSMP_VAL_320M);
     } else {
         /* Raise the voltage */
         REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_240M);
@@ -397,16 +397,16 @@ void rtc_clk_bbpll_configure(rtc_xtal_freq_t xtal_freq, int pll_freq)
                 bw = 0;
                 break;
         }
-        I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_ENDIV5, BBPLL_ENDIV5_VAL_480M);
-        I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_BBADC_DSMP, BBPLL_BBADC_DSMP_VAL_480M);
+        REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_ENDIV5, BBPLL_ENDIV5_VAL_480M);
+        REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_BBADC_DSMP, BBPLL_BBADC_DSMP_VAL_480M);
     }
 
     uint8_t i2c_bbpll_lref  = (lref << 7) | (div10_8 << 4) | (div_ref);
     uint8_t i2c_bbpll_div_7_0 = div7_0;
     uint8_t i2c_bbpll_dcur = (bw << 6) | dcur;
-    I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_LREF, i2c_bbpll_lref);
-    I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_DIV_7_0, i2c_bbpll_div_7_0);
-    I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_DCUR, i2c_bbpll_dcur);
+    REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_OC_LREF, i2c_bbpll_lref);
+    REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_OC_DIV_7_0, i2c_bbpll_div_7_0);
+    REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_OC_DCUR, i2c_bbpll_dcur);
     uint32_t delay_pll_en = (rtc_clk_slow_freq_get() == RTC_SLOW_FREQ_RTC) ?
             DELAY_PLL_ENABLE_WITH_150K : DELAY_PLL_ENABLE_WITH_32K;
     ets_delay_us(delay_pll_en);
@@ -465,11 +465,11 @@ static void rtc_clk_bbpll_enable(void)
              RTC_CNTL_BBPLL_FORCE_PD | RTC_CNTL_BBPLL_I2C_FORCE_PD);
 
     /* reset BBPLL configuration */
-    I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_IR_CAL_DELAY, BBPLL_IR_CAL_DELAY_VAL);
-    I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_IR_CAL_EXT_CAP, BBPLL_IR_CAL_EXT_CAP_VAL);
-    I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_ENB_FCAL, BBPLL_OC_ENB_FCAL_VAL);
-    I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_ENB_VCON, BBPLL_OC_ENB_VCON_VAL);
-    I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_BBADC_CAL_7_0, BBPLL_BBADC_CAL_7_0_VAL);
+    REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_IR_CAL_DELAY, BBPLL_IR_CAL_DELAY_VAL);
+    REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_IR_CAL_EXT_CAP, BBPLL_IR_CAL_EXT_CAP_VAL);
+    REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_OC_ENB_FCAL, BBPLL_OC_ENB_FCAL_VAL);
+    REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_OC_ENB_VCON, BBPLL_OC_ENB_VCON_VAL);
+    REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_BBADC_CAL_7_0, BBPLL_BBADC_CAL_7_0_VAL);
 }
 
 /**

components/soc/src/esp32/rtc_clk_init.c

@@ -25,7 +25,7 @@
 #include "soc/sens_periph.h"
 #include "soc/efuse_periph.h"
 #include "soc/apb_ctrl_reg.h"
-#include "i2c_rtc_clk.h"
+#include "regi2c_ctrl.h"
 #include "soc_log.h"
 #include "sdkconfig.h"
 #include "xtensa/core-macros.h"

components/soc/src/esp32s2/CMakeLists.txt

@@ -2,6 +2,7 @@ set(srcs "adc_hal.c"
         "dac_hal.c"
         "brownout_hal.c"
         "rtc_clk.c"
+        "regi2c_ctrl.c"
         "rtc_clk_init.c"
         "rtc_init.c"
         "rtc_pm.c"

components/soc/src/esp32s2/brownout_hal.c

@@ -16,13 +16,13 @@
 #include "hal/brownout_hal.h"
 #include "soc/rtc_cntl_struct.h"
 #include "soc/rtc_cntl_reg.h"
-#include "i2c_rtc_clk.h"
-#include "i2c_brownout.h"
+#include "regi2c_ctrl.h"
+#include "regi2c_brownout.h"
 
 
 void brownout_hal_config(const brownout_hal_config_t *cfg)
 {
-    I2C_WRITEREG_MASK_RTC(I2C_BOD, I2C_BOD_THRESHOLD, cfg->threshold);
+    REGI2C_WRITE_MASK(I2C_BOD, I2C_BOD_THRESHOLD, cfg->threshold);
     typeof(RTCCNTL.brown_out) brown_out_reg = {
         .out2_ena = 1,
         .int_wait = 0x002,

components/soc/src/esp32s2/i2c_rtc_clk.h

@@ -1,57 +0,0 @@
-// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#pragma once
-
-#include "i2c_apll.h"
-#include "i2c_bbpll.h"
-#include "i2c_ulp.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Analog function control register */
-#define ANA_CONFIG_REG  0x6000E044
-#define ANA_CONFIG_S    (8)
-#define ANA_CONFIG_M    (0x3FF)
-/* Clear to enable APLL */
-#define I2C_APLL_M      (BIT(14))
-/* Clear to enable BBPLL */
-#define I2C_BBPLL_M     (BIT(17))
-
-/* ROM functions which read/write internal control bus */
-uint8_t rom_i2c_readReg(uint8_t block, uint8_t host_id, uint8_t reg_add);
-uint8_t rom_i2c_readReg_Mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb);
-void rom_i2c_writeReg(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data);
-void rom_i2c_writeReg_Mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data);
-
-/* Convenience macros for the above functions, these use register definitions
- * from i2c_apll.h/i2c_bbpll.h header files.
- */
-#define I2C_WRITEREG_MASK_RTC(block, reg_add, indata) \
-      rom_i2c_writeReg_Mask(block, block##_HOSTID,  reg_add,  reg_add##_MSB,  reg_add##_LSB,  indata)
-
-#define I2C_READREG_MASK_RTC(block, reg_add) \
-      rom_i2c_readReg_Mask(block, block##_HOSTID,  reg_add,  reg_add##_MSB,  reg_add##_LSB)
-
-#define I2C_WRITEREG_RTC(block, reg_add, indata) \
-      rom_i2c_writeReg(block, block##_HOSTID,  reg_add, indata)
-
-#define I2C_READREG_RTC(block, reg_add) \
-      rom_i2c_readReg(block, block##_HOSTID,  reg_add)
-
-#ifdef __cplusplus
-}
-#endif

components/soc/src/esp32s2/include/hal/adc_ll.h

@@ -7,7 +7,7 @@
 #include "soc/apb_saradc_reg.h"
 #include "soc/rtc_cntl_struct.h"
 #include "soc/rtc_cntl_reg.h"
-#include "i2c_rtc_clk.h"
+#include "regi2c_ctrl.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -69,62 +69,6 @@ typedef enum {
     ADC2_CTRL_FORCE_DIG = 6,    /*!<For ADC2. Arbiter in shield mode. Force select digital controller work. */
 } adc_controller_t;
 
-/* ADC calibration defines. */
-#define ADC_LL_I2C_ADC            0X69
-#define ADC_LL_I2C_ADC_HOSTID     0
-
-#define ADC_LL_ANA_CONFIG2_REG  0x6000E048
-
-#define ADC_LL_SAR1_ENCAL_GND_ADDR 0x7
-#define ADC_LL_SAR1_ENCAL_GND_ADDR_MSB 5
-#define ADC_LL_SAR1_ENCAL_GND_ADDR_LSB 5
-
-#define ADC_LL_SAR2_ENCAL_GND_ADDR 0x7
-#define ADC_LL_SAR2_ENCAL_GND_ADDR_MSB 7
-#define ADC_LL_SAR2_ENCAL_GND_ADDR_LSB 7
-
-#define ADC_LL_SAR1_INITIAL_CODE_HIGH_ADDR 0x1
-#define ADC_LL_SAR1_INITIAL_CODE_HIGH_ADDR_MSB 0x3
-#define ADC_LL_SAR1_INITIAL_CODE_HIGH_ADDR_LSB 0x0
-
-#define ADC_LL_SAR1_INITIAL_CODE_LOW_ADDR  0x0
-#define ADC_LL_SAR1_INITIAL_CODE_LOW_ADDR_MSB  0x7
-#define ADC_LL_SAR1_INITIAL_CODE_LOW_ADDR_LSB  0x0
-
-#define ADC_LL_SAR2_INITIAL_CODE_HIGH_ADDR 0x4
-#define ADC_LL_SAR2_INITIAL_CODE_HIGH_ADDR_MSB 0x3
-#define ADC_LL_SAR2_INITIAL_CODE_HIGH_ADDR_LSB 0x0
-
-#define ADC_LL_SAR2_INITIAL_CODE_LOW_ADDR  0x3
-#define ADC_LL_SAR2_INITIAL_CODE_LOW_ADDR_MSB  0x7
-#define ADC_LL_SAR2_INITIAL_CODE_LOW_ADDR_LSB  0x0
-
-#define ADC_LL_SAR1_DREF_ADDR  0x2
-#define ADC_LL_SAR1_DREF_ADDR_MSB  0x6
-#define ADC_LL_SAR1_DREF_ADDR_LSB  0x4
-
-#define ADC_LL_SAR2_DREF_ADDR  0x5
-#define ADC_LL_SAR2_DREF_ADDR_MSB  0x6
-#define ADC_LL_SAR2_DREF_ADDR_LSB  0x4
-
-#define ADC_LL_SAR1_SAMPLE_CYCLE_ADDR 0x2
-#define ADC_LL_SAR1_SAMPLE_CYCLE_ADDR_MSB 0x2
-#define ADC_LL_SAR1_SAMPLE_CYCLE_ADDR_LSB 0x0
-
-#define ADC_LL_SARADC_DTEST_RTC_ADDR 0x7
-#define ADC_LL_SARADC_DTEST_RTC_ADDR_MSB 1
-#define ADC_LL_SARADC_DTEST_RTC_ADDR_LSB 0
-
-#define ADC_LL_SARADC_ENT_TSENS_ADDR 0x7
-#define ADC_LL_SARADC_ENT_TSENS_ADDR_MSB 2
-#define ADC_LL_SARADC_ENT_TSENS_ADDR_LSB 2
-
-#define ADC_LL_SARADC_ENT_RTC_ADDR 0x7
-#define ADC_LL_SARADC_ENT_RTC_ADDR_MSB 3
-#define ADC_LL_SARADC_ENT_RTC_ADDR_LSB 3
-
-/* ADC calibration defines end. */
-
 /*---------------------------------------------------------------
                     Digital controller setting
 ---------------------------------------------------------------*/
@@ -155,13 +99,11 @@ static inline void adc_ll_digi_set_fsm_time(uint32_t rst_wait, uint32_t start_wa
 static inline void adc_ll_set_sample_cycle(uint32_t sample_cycle)
 {
     /* Should be called before writing I2C registers. */
-    void phy_get_romfunc_addr(void);
-    phy_get_romfunc_addr();
     SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_FORCE_PU_M);
-    CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, BIT(18));
-    SET_PERI_REG_MASK(ADC_LL_ANA_CONFIG2_REG, BIT(16));
+    CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, I2C_SAR_M);
+    SET_PERI_REG_MASK(ANA_CONFIG2_REG, ANA_SAR_CFG2_M);
 
-    I2C_WRITEREG_MASK_RTC(ADC_LL_I2C_ADC, ADC_LL_SAR1_SAMPLE_CYCLE_ADDR, sample_cycle);
+    REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_SAMPLE_CYCLE_ADDR, sample_cycle);
 }
 
 /**
@@ -1194,27 +1136,25 @@ static inline void adc_ll_disable_sleep_controller(void)
 static inline void adc_ll_calibration_prepare(adc_ll_num_t adc_n, adc_channel_t channel, bool internal_gnd)
 {
     /* Should be called before writing I2C registers. */
-    void phy_get_romfunc_addr(void);
-    phy_get_romfunc_addr();
     CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_FORCE_PD_M);
     SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_FORCE_PU_M);
-    CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, BIT(18));
-    SET_PERI_REG_MASK(ADC_LL_ANA_CONFIG2_REG, BIT(16));
+    CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, I2C_SAR_M);
+    SET_PERI_REG_MASK(ANA_CONFIG2_REG, ANA_SAR_CFG2_M);
 
     /* Enable/disable internal connect GND (for calibration). */
     if (adc_n == ADC_NUM_1) {
-        I2C_WRITEREG_MASK_RTC(ADC_LL_I2C_ADC, ADC_LL_SAR1_DREF_ADDR, 4);
+        REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_DREF_ADDR, 4);
         if (internal_gnd) {
-            I2C_WRITEREG_MASK_RTC(ADC_LL_I2C_ADC, ADC_LL_SAR1_ENCAL_GND_ADDR, 1);
+            REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_ENCAL_GND_ADDR, 1);
         } else {
-            I2C_WRITEREG_MASK_RTC(ADC_LL_I2C_ADC, ADC_LL_SAR1_ENCAL_GND_ADDR, 0);
+            REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_ENCAL_GND_ADDR, 0);
         }
     } else {
-        I2C_WRITEREG_MASK_RTC(ADC_LL_I2C_ADC, ADC_LL_SAR2_DREF_ADDR, 4);
+        REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_DREF_ADDR, 4);
         if (internal_gnd) {
-            I2C_WRITEREG_MASK_RTC(ADC_LL_I2C_ADC, ADC_LL_SAR2_ENCAL_GND_ADDR, 1);
+            REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_ENCAL_GND_ADDR, 1);
         } else {
-            I2C_WRITEREG_MASK_RTC(ADC_LL_I2C_ADC, ADC_LL_SAR2_ENCAL_GND_ADDR, 0);
+            REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_ENCAL_GND_ADDR, 0);
         }
     }
 }
@@ -1227,9 +1167,9 @@ static inline void adc_ll_calibration_prepare(adc_ll_num_t adc_n, adc_channel_t
 static inline void adc_ll_calibration_finish(adc_ll_num_t adc_n)
 {
     if (adc_n == ADC_NUM_1) {
-        I2C_WRITEREG_MASK_RTC(ADC_LL_I2C_ADC, ADC_LL_SAR1_ENCAL_GND_ADDR, 0);
+        REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_ENCAL_GND_ADDR, 0);
     } else {
-        I2C_WRITEREG_MASK_RTC(ADC_LL_I2C_ADC, ADC_LL_SAR2_ENCAL_GND_ADDR, 0);
+        REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_ENCAL_GND_ADDR, 0);
     }
 }
 
@@ -1245,18 +1185,16 @@ static inline void adc_ll_set_calibration_param(adc_ll_num_t adc_n, uint32_t par
     uint8_t msb = param >> 8;
     uint8_t lsb = param & 0xFF;
     /* Should be called before writing I2C registers. */
-    void phy_get_romfunc_addr(void);
-    phy_get_romfunc_addr();
     SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_FORCE_PU_M);
-    CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, BIT(18));
-    SET_PERI_REG_MASK(ADC_LL_ANA_CONFIG2_REG, BIT(16));
+    CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, I2C_SAR_M);
+    SET_PERI_REG_MASK(ANA_CONFIG2_REG, ANA_SAR_CFG2_M);
 
     if (adc_n == ADC_NUM_1) {
-        I2C_WRITEREG_MASK_RTC(ADC_LL_I2C_ADC, ADC_LL_SAR1_INITIAL_CODE_HIGH_ADDR, msb);
-        I2C_WRITEREG_MASK_RTC(ADC_LL_I2C_ADC, ADC_LL_SAR1_INITIAL_CODE_LOW_ADDR, lsb);
+        REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_HIGH_ADDR, msb);
+        REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_LOW_ADDR, lsb);
     } else {
-        I2C_WRITEREG_MASK_RTC(ADC_LL_I2C_ADC, ADC_LL_SAR2_INITIAL_CODE_HIGH_ADDR, msb);
-        I2C_WRITEREG_MASK_RTC(ADC_LL_I2C_ADC, ADC_LL_SAR2_INITIAL_CODE_LOW_ADDR, lsb);
+        REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_INITIAL_CODE_HIGH_ADDR, msb);
+        REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_INITIAL_CODE_LOW_ADDR, lsb);
     }
 }
 /* Temp code end. */
@@ -1275,23 +1213,21 @@ static inline void adc_ll_set_calibration_param(adc_ll_num_t adc_n, uint32_t par
 static inline void adc_ll_vref_output(adc_ll_num_t adc, adc_channel_t channel, bool en)
 {
     /* Should be called before writing I2C registers. */
-    void phy_get_romfunc_addr(void);
-    phy_get_romfunc_addr();
     SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_FORCE_PU_M);
-    CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, BIT(18));
-    SET_PERI_REG_MASK(ADC_LL_ANA_CONFIG2_REG, BIT(16));
+    CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, I2C_SAR_M);
+    SET_PERI_REG_MASK(ANA_CONFIG2_REG, ANA_SAR_CFG2_M);
 
     if (en) {
         if (adc == ADC_NUM_1) {
             /* Config test mux to route v_ref to ADC1 Channels */
-            I2C_WRITEREG_MASK_RTC(ADC_LL_I2C_ADC, ADC_LL_SARADC_DTEST_RTC_ADDR, 1);
-            I2C_WRITEREG_MASK_RTC(ADC_LL_I2C_ADC, ADC_LL_SARADC_ENT_TSENS_ADDR, 0);
-            I2C_WRITEREG_MASK_RTC(ADC_LL_I2C_ADC, ADC_LL_SARADC_ENT_RTC_ADDR, 1);
+            REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_DTEST_RTC_ADDR, 1);
+            REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_TSENS_ADDR, 0);
+            REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_RTC_ADDR, 1);
         } else {
             /* Config test mux to route v_ref to ADC2 Channels */
-            I2C_WRITEREG_MASK_RTC(ADC_LL_I2C_ADC, ADC_LL_SARADC_DTEST_RTC_ADDR, 0);
-            I2C_WRITEREG_MASK_RTC(ADC_LL_I2C_ADC, ADC_LL_SARADC_ENT_TSENS_ADDR, 1);
-            I2C_WRITEREG_MASK_RTC(ADC_LL_I2C_ADC, ADC_LL_SARADC_ENT_RTC_ADDR, 0);
+            REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_DTEST_RTC_ADDR, 0);
+            REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_TSENS_ADDR, 1);
+            REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_RTC_ADDR, 0);
         }
         //in sleep force to use rtc to control ADC
         SENS.sar_meas2_mux.sar2_rtc_force = 1;
@@ -1302,8 +1238,8 @@ static inline void adc_ll_vref_output(adc_ll_num_t adc, adc_channel_t channel, b
         //set en_pad for ADC2 channels (bits 0x380)
         SENS.sar_meas2_ctrl2.sar2_en_pad = 1 << channel;
     } else {
-        I2C_WRITEREG_MASK_RTC(ADC_LL_I2C_ADC, ADC_LL_SARADC_ENT_TSENS_ADDR, 0);
-        I2C_WRITEREG_MASK_RTC(ADC_LL_I2C_ADC, ADC_LL_SARADC_ENT_RTC_ADDR, 0);
+        REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_TSENS_ADDR, 0);
+        REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_RTC_ADDR, 0);
         SENS.sar_meas2_mux.sar2_rtc_force = 0;
         //set sar2_en_test
         SENS.sar_meas2_ctrl1.sar2_en_test = 0;

components/soc/src/esp32s2/regi2c_ctrl.c

@@ -0,0 +1,169 @@
+// Copyright 2019-2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#include "esp_err.h"
+#include "soc/soc.h"
+#include "soc/apb_ctrl_reg.h"
+#include "regi2c_ctrl.h"
+#include "regi2c_brownout.h"
+#include "esp_log.h"
+
+#define I2C_RTC_WIFI_CLK_EN (APB_CTRL_WIFI_CLK_EN_REG)
+
+#define I2C_RTC_CLK_GATE_EN    (BIT(18))
+#define I2C_RTC_CLK_GATE_EN_M  (BIT(18))
+#define I2C_RTC_CLK_GATE_EN_V  0x1
+#define I2C_RTC_CLK_GATE_EN_S  18
+
+#define I2C_RTC_CONFIG0  0x6000e048
+
+#define I2C_RTC_MAGIC_CTRL 0x00001FFF
+#define I2C_RTC_MAGIC_CTRL_M  ((I2C_RTC_MAGIC_CTRL_V)<<(I2C_RTC_MAGIC_CTRL_S))
+#define I2C_RTC_MAGIC_CTRL_V  0x1FFF
+#define I2C_RTC_MAGIC_CTRL_S  4
+
+#define I2C_RTC_CONFIG1  0x6000e044
+
+#define I2C_RTC_BOD_MASK (BIT(22))
+#define I2C_RTC_BOD_MASK_M  (BIT(22))
+#define I2C_RTC_BOD_MASK_V  0x1
+#define I2C_RTC_BOD_MASK_S  22
+
+#define I2C_RTC_SAR_MASK (BIT(18))
+#define I2C_RTC_SAR_MASK_M  (BIT(18))
+#define I2C_RTC_SAR_MASK_V  0x1
+#define I2C_RTC_SAR_MASK_S  18
+
+#define I2C_RTC_BBPLL_MASK (BIT(17))
+#define I2C_RTC_BBPLL_MASK_M  (BIT(17))
+#define I2C_RTC_BBPLL_MASK_V  0x1
+#define I2C_RTC_BBPLL_MASK_S  17
+
+#define I2C_RTC_APLL_MASK (BIT(14))
+#define I2C_RTC_APLL_MASK_M  (BIT(14))
+#define I2C_RTC_APLL_MASK_V  0x1
+#define I2C_RTC_APLL_MASK_S  14
+
+#define I2C_RTC_ALL_MASK 0x00007FFF
+#define I2C_RTC_ALL_MASK_M  ((I2C_RTC_ALL_MASK_V)<<(I2C_RTC_ALL_MASK_S))
+#define I2C_RTC_ALL_MASK_V  0x7FFF
+#define I2C_RTC_ALL_MASK_S  8
+
+#define I2C_RTC_CONFIG2  0x6000e000
+
+#define I2C_RTC_BUSY (BIT(25))
+#define I2C_RTC_BUSY_M  (BIT(25))
+#define I2C_RTC_BUSY_V  0x1
+#define I2C_RTC_BUSY_S  25
+
+#define I2C_RTC_WR_CNTL (BIT(24))
+#define I2C_RTC_WR_CNTL_M  (BIT(24))
+#define I2C_RTC_WR_CNTL_V  0x1
+#define I2C_RTC_WR_CNTL_S  24
+
+#define I2C_RTC_DATA 0x000000FF
+#define I2C_RTC_DATA_M  ((I2C_RTC_DATA_V)<<(I2C_RTC_DATA_S))
+#define I2C_RTC_DATA_V  0xFF
+#define I2C_RTC_DATA_S  16
+
+#define I2C_RTC_ADDR 0x000000FF
+#define I2C_RTC_ADDR_M  ((I2C_RTC_ADDR_V)<<(I2C_RTC_ADDR_S))
+#define I2C_RTC_ADDR_V  0xFF
+#define I2C_RTC_ADDR_S  8
+
+#define I2C_RTC_SLAVE_ID 0x000000FF
+#define I2C_RTC_SLAVE_ID_M  ((I2C_RTC_SLAVE_ID_V)<<(I2C_RTC_SLAVE_ID_S))
+#define I2C_RTC_SLAVE_ID_V  0xFF
+#define I2C_RTC_SLAVE_ID_S  0
+
+#define I2C_RTC_MAGIC_DEFAULT (0x1c40)
+
+static void i2c_rtc_enable_block(uint8_t block)
+{
+    REG_SET_FIELD(I2C_RTC_CONFIG0, I2C_RTC_MAGIC_CTRL, I2C_RTC_MAGIC_DEFAULT);
+    REG_SET_FIELD(I2C_RTC_CONFIG1, I2C_RTC_ALL_MASK, I2C_RTC_ALL_MASK_V);
+    REG_SET_BIT(I2C_RTC_WIFI_CLK_EN, I2C_RTC_CLK_GATE_EN);
+    switch (block) {
+    case I2C_APLL:
+        REG_CLR_BIT(I2C_RTC_CONFIG1, I2C_RTC_APLL_MASK);
+        break;
+    case I2C_BBPLL:
+        REG_CLR_BIT(I2C_RTC_CONFIG1, I2C_RTC_BBPLL_MASK);
+        break;
+    case I2C_SAR_ADC:
+        REG_CLR_BIT(I2C_RTC_CONFIG1, I2C_RTC_SAR_MASK);
+        break;
+    case I2C_BOD:
+        REG_CLR_BIT(I2C_RTC_CONFIG1, I2C_RTC_BOD_MASK);
+        break;
+    }
+}
+
+uint8_t i2c_rtc_read_reg(uint8_t block, uint8_t host_id, uint8_t reg_add)
+{
+    i2c_rtc_enable_block(block);
+
+    uint32_t temp = ((block & I2C_RTC_SLAVE_ID_V) << I2C_RTC_SLAVE_ID_S)
+                    | (reg_add & I2C_RTC_ADDR_V) << I2C_RTC_ADDR_S;
+    REG_WRITE(I2C_RTC_CONFIG2, temp);
+    while (REG_GET_BIT(I2C_RTC_CONFIG2, I2C_RTC_BUSY));
+    return REG_GET_FIELD(I2C_RTC_CONFIG2, I2C_RTC_DATA);
+}
+
+uint8_t i2c_rtc_read_reg_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb)
+{
+    assert(msb - lsb < 8);
+    i2c_rtc_enable_block(block);
+
+    uint32_t temp = ((block & I2C_RTC_SLAVE_ID_V) << I2C_RTC_SLAVE_ID_S)
+                    | (reg_add & I2C_RTC_ADDR_V) << I2C_RTC_ADDR_S;
+    REG_WRITE(I2C_RTC_CONFIG2, temp);
+    while (REG_GET_BIT(I2C_RTC_CONFIG2, I2C_RTC_BUSY));
+    uint32_t data = REG_GET_FIELD(I2C_RTC_CONFIG2, I2C_RTC_DATA);
+    return (uint8_t)((data >> lsb) & (~(0xFFFFFFFF << (msb - lsb + 1))));
+}
+
+void i2c_rtc_write_reg(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data)
+{
+    i2c_rtc_enable_block(block);
+
+    uint32_t temp = ((block & I2C_RTC_SLAVE_ID_V) << I2C_RTC_SLAVE_ID_S)
+                    | ((reg_add & I2C_RTC_ADDR_V) << I2C_RTC_ADDR_S)
+                    | ((0x1 & I2C_RTC_WR_CNTL_V) << I2C_RTC_WR_CNTL_S)
+                    | (((uint32_t)data & I2C_RTC_DATA_V) << I2C_RTC_DATA_S);
+    REG_WRITE(I2C_RTC_CONFIG2, temp);
+    while (REG_GET_BIT(I2C_RTC_CONFIG2, I2C_RTC_BUSY));
+}
+
+void i2c_rtc_write_reg_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data)
+{
+    assert(msb - lsb < 8);
+    i2c_rtc_enable_block(block);
+
+    /*Read the i2c bus register*/
+    uint32_t temp = ((block & I2C_RTC_SLAVE_ID_V) << I2C_RTC_SLAVE_ID_S)
+                    | (reg_add & I2C_RTC_ADDR_V) << I2C_RTC_ADDR_S;
+    REG_WRITE(I2C_RTC_CONFIG2, temp);
+    while (REG_GET_BIT(I2C_RTC_CONFIG2, I2C_RTC_BUSY));
+    temp = REG_GET_FIELD(I2C_RTC_CONFIG2, I2C_RTC_DATA);
+    /*Write the i2c bus register*/
+    temp &= ((~(0xFFFFFFFF << lsb)) | (0xFFFFFFFF << (msb + 1)));
+    temp = (((uint32_t)data & (~(0xFFFFFFFF << (msb - lsb + 1)))) << lsb) | temp;
+    temp = ((block & I2C_RTC_SLAVE_ID_V) << I2C_RTC_SLAVE_ID_S)
+            | ((reg_add & I2C_RTC_ADDR_V) << I2C_RTC_ADDR_S)
+            | ((0x1 & I2C_RTC_WR_CNTL_V) << I2C_RTC_WR_CNTL_S)
+            | ((temp & I2C_RTC_DATA_V) << I2C_RTC_DATA_S);
+    REG_WRITE(I2C_RTC_CONFIG2, temp);
+    while (REG_GET_BIT(I2C_RTC_CONFIG2, I2C_RTC_BUSY));
+}

components/soc/src/esp32s2/regi2c_ctrl.h

@@ -0,0 +1,65 @@
+// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#pragma once
+
+#include <stdint.h>
+#include "regi2c_apll.h"
+#include "regi2c_bbpll.h"
+#include "regi2c_ulp.h"
+#include "regi2c_saradc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Analog function control register */
+#define ANA_CONFIG_REG  0x6000E044
+#define ANA_CONFIG_S    (8)
+#define ANA_CONFIG_M    (0x3FF)
+/* Clear to enable APLL */
+#define I2C_APLL_M      (BIT(14))
+/* Clear to enable BBPLL */
+#define I2C_BBPLL_M     (BIT(17))
+/* Clear to enable SAR */
+#define I2C_SAR_M       (BIT(18))
+
+#define ANA_CONFIG2_REG 0x6000E048
+#define ANA_SAR_CFG2_M  (BIT(16))
+
+/* Read/Write internal control bus */
+uint8_t i2c_rtc_read_reg(uint8_t block, uint8_t host_id, uint8_t reg_add);
+uint8_t i2c_rtc_read_reg_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb);
+void i2c_rtc_write_reg(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data);
+void i2c_rtc_write_reg_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data);
+void i2c_rtc_init(void);
+
+/* Convenience macros for the above functions, these use register definitions
+ * from regi2c_apll.h/regi2c_bbpll.h header files.
+ */
+#define REGI2C_WRITE_MASK(block, reg_add, indata) \
+      i2c_rtc_write_reg_mask(block, block##_HOSTID,  reg_add,  reg_add##_MSB,  reg_add##_LSB,  indata)
+
+#define REGI2C_READ_MASK(block, reg_add) \
+      i2c_rtc_read_reg_mask(block, block##_HOSTID,  reg_add,  reg_add##_MSB,  reg_add##_LSB)
+
+#define REGI2C_WRITE(block, reg_add, indata) \
+      i2c_rtc_write_reg(block, block##_HOSTID,  reg_add, indata)
+
+#define REGI2C_READ(block, reg_add) \
+      i2c_rtc_read_reg(block, block##_HOSTID,  reg_add)
+
+#ifdef __cplusplus
+}
+#endif

components/soc/src/esp32s2/rtc_clk.c

@@ -29,7 +29,7 @@
 #include "soc/dport_reg.h"
 #include "soc/efuse_reg.h"
 #include "soc/syscon_reg.h"
-#include "i2c_rtc_clk.h"
+#include "regi2c_ctrl.h"
 #include "soc_log.h"
 #include "rtc_clk_common.h"
 #include "sdkconfig.h"
@@ -133,21 +133,21 @@ void rtc_clk_apll_enable(bool enable, uint32_t sdm0, uint32_t sdm1, uint32_t sdm
     REG_SET_FIELD(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PU, enable ? 1 : 0);
 
     if (enable) {
-        I2C_WRITEREG_MASK_RTC(I2C_APLL, I2C_APLL_DSDM2, sdm2);
-        I2C_WRITEREG_MASK_RTC(I2C_APLL, I2C_APLL_DSDM0, sdm0);
-        I2C_WRITEREG_MASK_RTC(I2C_APLL, I2C_APLL_DSDM1, sdm1);
-        I2C_WRITEREG_RTC(I2C_APLL, I2C_APLL_SDM_STOP, APLL_SDM_STOP_VAL_1);
-        I2C_WRITEREG_RTC(I2C_APLL, I2C_APLL_SDM_STOP, APLL_SDM_STOP_VAL_2_REV1);
-        I2C_WRITEREG_MASK_RTC(I2C_APLL, I2C_APLL_OR_OUTPUT_DIV, o_div);
+        REGI2C_WRITE_MASK(I2C_APLL, I2C_APLL_DSDM2, sdm2);
+        REGI2C_WRITE_MASK(I2C_APLL, I2C_APLL_DSDM0, sdm0);
+        REGI2C_WRITE_MASK(I2C_APLL, I2C_APLL_DSDM1, sdm1);
+        REGI2C_WRITE(I2C_APLL, I2C_APLL_SDM_STOP, APLL_SDM_STOP_VAL_1);
+        REGI2C_WRITE(I2C_APLL, I2C_APLL_SDM_STOP, APLL_SDM_STOP_VAL_2_REV1);
+        REGI2C_WRITE_MASK(I2C_APLL, I2C_APLL_OR_OUTPUT_DIV, o_div);
 
         /* calibration */
-        I2C_WRITEREG_RTC(I2C_APLL, I2C_APLL_IR_CAL_DELAY, APLL_CAL_DELAY_1);
-        I2C_WRITEREG_RTC(I2C_APLL, I2C_APLL_IR_CAL_DELAY, APLL_CAL_DELAY_2);
-        I2C_WRITEREG_RTC(I2C_APLL, I2C_APLL_IR_CAL_DELAY, APLL_CAL_DELAY_3);
+        REGI2C_WRITE(I2C_APLL, I2C_APLL_IR_CAL_DELAY, APLL_CAL_DELAY_1);
+        REGI2C_WRITE(I2C_APLL, I2C_APLL_IR_CAL_DELAY, APLL_CAL_DELAY_2);
+        REGI2C_WRITE(I2C_APLL, I2C_APLL_IR_CAL_DELAY, APLL_CAL_DELAY_3);
 
         /* wait for calibration end */
-        while (!(I2C_READREG_MASK_RTC(I2C_APLL, I2C_APLL_OR_CAL_END))) {
-            /* use ets_delay_us so the RTC bus doesn't get flooded */
+        while (!(REGI2C_READ_MASK(I2C_APLL, I2C_APLL_OR_CAL_END))) {
+            /* use esp_rom_delay_us so the RTC bus doesn't get flooded */
             ets_delay_us(1);
         }
     }
@@ -254,7 +254,7 @@ void rtc_clk_bbpll_configure(rtc_xtal_freq_t xtal_freq, int pll_freq)
         dr3 = 0;
         dchgp = 5;
         dcur = 4;
-        I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_MODE_HF, 0x6B);
+        REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_MODE_HF, 0x6B);
     } else {
         /* Clear this register to let the digital part know 320M PLL is used */
         CLEAR_PERI_REG_MASK(DPORT_CPU_PER_CONF_REG, DPORT_PLL_FREQ_SEL);
@@ -265,23 +265,23 @@ void rtc_clk_bbpll_configure(rtc_xtal_freq_t xtal_freq, int pll_freq)
         dr3 = 0;
         dchgp = 5;
         dcur = 5;
-        I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_MODE_HF, 0x69);
+        REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_MODE_HF, 0x69);
     }
     uint8_t i2c_bbpll_lref  = (dchgp << I2C_BBPLL_OC_DCHGP_LSB) | (div_ref);
     uint8_t i2c_bbpll_div_7_0 = div7_0;
     uint8_t i2c_bbpll_dcur = (2 << I2C_BBPLL_OC_DLREF_SEL_LSB ) | (1 << I2C_BBPLL_OC_DHREF_SEL_LSB) | dcur;
-    I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_REF_DIV, i2c_bbpll_lref);
-    I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_DIV_7_0, i2c_bbpll_div_7_0);
-    I2C_WRITEREG_MASK_RTC(I2C_BBPLL, I2C_BBPLL_OC_DR1, dr1);
-    I2C_WRITEREG_MASK_RTC(I2C_BBPLL, I2C_BBPLL_OC_DR3, dr3);
-    I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_DCUR, i2c_bbpll_dcur);
+    REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_OC_REF_DIV, i2c_bbpll_lref);
+    REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_OC_DIV_7_0, i2c_bbpll_div_7_0);
+    REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_DR1, dr1);
+    REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_DR3, dr3);
+    REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_OC_DCUR, i2c_bbpll_dcur);
 
     // Enable calibration by software
-    I2C_WRITEREG_MASK_RTC(I2C_BBPLL, I2C_BBPLL_IR_CAL_ENX_CAP, 1);
+    REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_IR_CAL_ENX_CAP, 1);
     for (int ext_cap = 0; ext_cap < 16; ext_cap++) {
         uint8_t cal_result;
-        I2C_WRITEREG_MASK_RTC(I2C_BBPLL, I2C_BBPLL_IR_CAL_EXT_CAP, ext_cap);
-        cal_result = I2C_READREG_MASK_RTC(I2C_BBPLL, I2C_BBPLL_OR_CAL_CAP);
+        REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_IR_CAL_EXT_CAP, ext_cap);
+        cal_result = REGI2C_READ_MASK(I2C_BBPLL, I2C_BBPLL_OR_CAL_CAP);
         if (cal_result == 0) {
             break;
         }
@@ -290,7 +290,8 @@ void rtc_clk_bbpll_configure(rtc_xtal_freq_t xtal_freq, int pll_freq)
             abort();
         }
     }
-   s_cur_pll_freq = pll_freq;
+
+    s_cur_pll_freq = pll_freq;
 }
 
 /**

components/soc/src/esp32s2/rtc_clk_init.c

@@ -24,7 +24,7 @@
 #include "soc/sens_periph.h"
 #include "soc/efuse_periph.h"
 #include "soc/apb_ctrl_reg.h"
-#include "i2c_rtc_clk.h"
+#include "regi2c_ctrl.h"
 #include "soc_log.h"
 #include "sdkconfig.h"
 #include "xtensa/core-macros.h"

components/soc/src/esp32s2/rtc_init.c

@@ -21,7 +21,7 @@
 #include "soc/gpio_reg.h"
 #include "soc/spi_mem_reg.h"
 #include "soc/extmem_reg.h"
-#include "i2c_rtc_clk.h"
+#include "regi2c_ctrl.h"
 #include "soc_log.h"
 
 static const char *TAG = "rtc_init";
@@ -179,13 +179,13 @@ void rtc_init(rtc_config_t cfg)
         rtc_clk_cpu_freq_set_xtal();
 
 
-        I2C_WRITEREG_MASK_RTC(I2C_ULP, I2C_ULP_IR_RESETB, 0);
-        I2C_WRITEREG_MASK_RTC(I2C_ULP, I2C_ULP_IR_RESETB, 1);
+        REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_RESETB, 0);
+        REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_RESETB, 1);
         bool odone_flag = 0;
         bool bg_odone_flag = 0;
         while(1) {
-            odone_flag = I2C_READREG_MASK_RTC(I2C_ULP, I2C_ULP_O_DONE_FLAG);
-            bg_odone_flag = I2C_READREG_MASK_RTC(I2C_ULP, I2C_ULP_BG_O_DONE_FLAG);
+            odone_flag = REGI2C_READ_MASK(I2C_ULP, I2C_ULP_O_DONE_FLAG);
+            bg_odone_flag = REGI2C_READ_MASK(I2C_ULP, I2C_ULP_BG_O_DONE_FLAG);
             cycle1 = rtc_time_get();
             if (odone_flag && bg_odone_flag)
                 break;