Merge branch 'feature/enable_i2s_tests_on_esp32s2beta' into 'master'

Enable i2s and freertos test/s on esp32s2beta

See merge request espressif/esp-idf!6790

components/driver/test/esp32/test_i2s.c → components/driver/test/test_i2s.c

@@ -14,11 +14,18 @@
 #define SAMPLE_RATE     (36000)
 #define SAMPLE_BITS     (16)
 #define MASTER_BCK_IO 18
-#define MASTER_WS_IO 25
 #define SLAVE_BCK_IO 19
 #define SLAVE_WS_IO 26
 #define DATA_IN_IO 21
+
+#if CONFIG_IDF_TARGET_ESP32
+#define MASTER_WS_IO 25
 #define DATA_OUT_IO 22
+#elif CONFIG_IDF_TARGET_ESP32S2BETA
+#define MASTER_WS_IO 28
+#define DATA_OUT_IO 20
+#endif
+
 #define PERCENT_DIFF 0.0001
 
 /**
@@ -69,6 +76,10 @@ TEST_CASE("I2S basic driver install, uninstall, set pin test", "[i2s]")
     TEST_ESP_OK(i2s_driver_uninstall(I2S_NUM_0));
 }
 
+#if CONFIG_IDF_TARGET_ESP32
+
+/* ESP32S2BETA has only single I2S port and hence following test cases are not applicable */
+
 TEST_CASE("I2S write and read test(master tx and slave rx)", "[i2s][test_env=UT_T1_I2S]")
 {
     // master driver installed and send data
@@ -234,6 +245,7 @@ TEST_CASE("I2S write and read test(master rx and slave tx)", "[i2s][test_env=UT_
     i2s_driver_uninstall(I2S_NUM_0);
     i2s_driver_uninstall(I2S_NUM_1);
 }
+#endif /* CONFIG_IDF_TARGET_ESP32 */
 
 TEST_CASE("I2S memory leaking test", "[i2s]")
 {

components/freertos/test/test_freertos_mutex.c

@@ -12,7 +12,7 @@ static void mutex_release_task(void* arg)
     TEST_FAIL_MESSAGE("should not be reached");
 }
 
-TEST_CASE_ESP32("mutex released not by owner causes an assert", "[freertos][reset=abort,SW_CPU_RESET]")
+TEST_CASE("mutex released not by owner causes an assert", "[freertos][reset=abort,SW_CPU_RESET]")
 {
     SemaphoreHandle_t mutex = xSemaphoreCreateMutex();
     xSemaphoreTake(mutex, portMAX_DELAY);

components/soc/esp32/include/soc/i2s_caps.h

@@ -27,7 +27,7 @@ extern "C" {
 
 // ESP32 have 2 I2S
 #define I2S_NUM_0             (0) /*!< I2S port 0 */
-#define I2S_NUM_1             (1) /*!< I2S port 0 */
+#define I2S_NUM_1             (1) /*!< I2S port 1 */
 #define I2S_NUM_MAX           (2) /*!< I2S port max */
 #define SOC_I2S_NUM           (I2S_NUM_MAX)
 

components/soc/esp32s2beta/include/soc/i2s_caps.h

@@ -22,7 +22,7 @@
 #define I2S_MAX_BUFFER_SIZE               (4 * 1024 * 1024) //the maximum RAM can be allocated
 #define I2S_BASE_CLK                      (2*APB_CLK_FREQ)
 
-// ESP32-S2 have 2 I2S
+// ESP32-S2 have 1 I2S
 #define I2S_NUM_0             (0) /*!< I2S port 0 */
 #define I2S_NUM_MAX           (1) /*!< I2S port max */
 #define SOC_I2S_NUM           (I2S_NUM_MAX)

tools/ci/config/target-test.yml

@@ -453,7 +453,7 @@ UT_034:
 
 UT_035:
   extends: .unit_test_template
-  parallel: 20
+  parallel: 30
   tags:
     - ESP32S2BETA_IDF
     - UT_T1_1