initialize the clock gating control signal of each modem clock domain

components/esp_system/port/soc/esp32c6/clk.c

@@ -20,6 +20,7 @@
 #include "soc/i2s_reg.h"
 #include "esp_cpu.h"
 #include "hal/wdt_hal.h"
+#include "esp_private/esp_modem_clock.h"
 #include "esp_private/periph_ctrl.h"
 #include "esp_private/esp_clk.h"
 #include "esp_rom_uart.h"
@@ -178,6 +179,7 @@ void rtc_clk_select_rtc_slow_clk(void)
  */
 __attribute__((weak)) void esp_perip_clk_init(void)
 {
+    modem_clock_domain_pmu_state_icg_map_init();
     ESP_EARLY_LOGW(TAG, "esp_perip_clk_init() has not been implemented yet");
 #if 0 // TODO: IDF-5658
     uint32_t common_perip_clk, hwcrypto_perip_clk, wifi_bt_sdio_clk = 0;